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usb: imx21-hcd: Include missing linux/module.h
[linux-2.6/btrfs-unstable.git] / drivers / mfd / omap-usb-host.c
blob05164d7f054b86ccfd6625cc21da545212d5983d
1 /**
2 * omap-usb-host.c - The USBHS core driver for OMAP EHCI & OHCI
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com
5 * Author: Keshava Munegowda <keshava_mgowda@ti.com>
6 *
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 of
9 * the License as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/types.h>
22 #include <linux/slab.h>
23 #include <linux/delay.h>
24 #include <linux/clk.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/spinlock.h>
27 #include <linux/gpio.h>
28 #include <linux/platform_device.h>
29 #include <linux/platform_data/usb-omap.h>
30 #include <linux/pm_runtime.h>
31
32 #include "omap-usb.h"
33
34 #define USBHS_DRIVER_NAME "usbhs_omap"
35 #define OMAP_EHCI_DEVICE "ehci-omap"
36 #define OMAP_OHCI_DEVICE "ohci-omap3"
37
38 /* OMAP USBHOST Register addresses */
39
40 /* UHH Register Set */
41 #define OMAP_UHH_REVISION (0x00)
42 #define OMAP_UHH_SYSCONFIG (0x10)
43 #define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12)
44 #define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8)
45 #define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3)
46 #define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2)
47 #define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1)
48 #define OMAP_UHH_SYSCONFIG_AUTOIDLE (1 << 0)
49
50 #define OMAP_UHH_SYSSTATUS (0x14)
51 #define OMAP_UHH_HOSTCONFIG (0x40)
52 #define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS (1 << 0)
53 #define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS (1 << 0)
54 #define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11)
55 #define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12)
56 #define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2)
57 #define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3)
58 #define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4)
59 #define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5)
60 #define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS (1 << 8)
61 #define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS (1 << 9)
62 #define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS (1 << 10)
63 #define OMAP4_UHH_HOSTCONFIG_APP_START_CLK (1 << 31)
64
65 /* OMAP4-specific defines */
66 #define OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR (3 << 2)
67 #define OMAP4_UHH_SYSCONFIG_NOIDLE (1 << 2)
68 #define OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR (3 << 4)
69 #define OMAP4_UHH_SYSCONFIG_NOSTDBY (1 << 4)
70 #define OMAP4_UHH_SYSCONFIG_SOFTRESET (1 << 0)
71
72 #define OMAP4_P1_MODE_CLEAR (3 << 16)
73 #define OMAP4_P1_MODE_TLL (1 << 16)
74 #define OMAP4_P1_MODE_HSIC (3 << 16)
75 #define OMAP4_P2_MODE_CLEAR (3 << 18)
76 #define OMAP4_P2_MODE_TLL (1 << 18)
77 #define OMAP4_P2_MODE_HSIC (3 << 18)
78
79 #define OMAP_UHH_DEBUG_CSR (0x44)
80
81 /* Values of UHH_REVISION - Note: these are not given in the TRM */
82 #define OMAP_USBHS_REV1 0x00000010 /* OMAP3 */
83 #define OMAP_USBHS_REV2 0x50700100 /* OMAP4 */
84
85 #define is_omap_usbhs_rev1(x) (x->usbhs_rev == OMAP_USBHS_REV1)
86 #define is_omap_usbhs_rev2(x) (x->usbhs_rev == OMAP_USBHS_REV2)
87
88 #define is_ehci_phy_mode(x) (x == OMAP_EHCI_PORT_MODE_PHY)
89 #define is_ehci_tll_mode(x) (x == OMAP_EHCI_PORT_MODE_TLL)
90 #define is_ehci_hsic_mode(x) (x == OMAP_EHCI_PORT_MODE_HSIC)
91
92
93 struct usbhs_hcd_omap {
94 struct clk *xclk60mhsp1_ck;
95 struct clk *xclk60mhsp2_ck;
96 struct clk *utmi_p1_fck;
97 struct clk *usbhost_p1_fck;
98 struct clk *utmi_p2_fck;
99 struct clk *usbhost_p2_fck;
100 struct clk *init_60m_fclk;
101 struct clk *ehci_logic_fck;
102
103 void __iomem *uhh_base;
104
105 struct usbhs_omap_platform_data platdata;
106
107 u32 usbhs_rev;
108 spinlock_t lock;
109 };
110 /*-------------------------------------------------------------------------*/
111
112 const char usbhs_driver_name[] = USBHS_DRIVER_NAME;
113 static u64 usbhs_dmamask = DMA_BIT_MASK(32);
114
115 /*-------------------------------------------------------------------------*/
116
117 static inline void usbhs_write(void __iomem *base, u32 reg, u32 val)
118 {
119 __raw_writel(val, base + reg);
120 }
121
122 static inline u32 usbhs_read(void __iomem *base, u32 reg)
123 {
124 return __raw_readl(base + reg);
125 }
126
127 static inline void usbhs_writeb(void __iomem *base, u8 reg, u8 val)
128 {
129 __raw_writeb(val, base + reg);
130 }
131
132 static inline u8 usbhs_readb(void __iomem *base, u8 reg)
133 {
134 return __raw_readb(base + reg);
135 }
136
137 /*-------------------------------------------------------------------------*/
138
139 static struct platform_device *omap_usbhs_alloc_child(const char *name,
140 struct resource *res, int num_resources, void *pdata,
141 size_t pdata_size, struct device *dev)
142 {
143 struct platform_device *child;
144 int ret;
145
146 child = platform_device_alloc(name, 0);
147
148 if (!child) {
149 dev_err(dev, "platform_device_alloc %s failed\n", name);
150 goto err_end;
151 }
152
153 ret = platform_device_add_resources(child, res, num_resources);
154 if (ret) {
155 dev_err(dev, "platform_device_add_resources failed\n");
156 goto err_alloc;
157 }
158
159 ret = platform_device_add_data(child, pdata, pdata_size);
160 if (ret) {
161 dev_err(dev, "platform_device_add_data failed\n");
162 goto err_alloc;
163 }
164
165 child->dev.dma_mask = &usbhs_dmamask;
166 dma_set_coherent_mask(&child->dev, DMA_BIT_MASK(32));
167 child->dev.parent = dev;
168
169 ret = platform_device_add(child);
170 if (ret) {
171 dev_err(dev, "platform_device_add failed\n");
172 goto err_alloc;
173 }
174
175 return child;
176
177 err_alloc:
178 platform_device_put(child);
179
180 err_end:
181 return NULL;
182 }
183
184 static int omap_usbhs_alloc_children(struct platform_device *pdev)
185 {
186 struct device *dev = &pdev->dev;
187 struct usbhs_hcd_omap *omap;
188 struct ehci_hcd_omap_platform_data *ehci_data;
189 struct ohci_hcd_omap_platform_data *ohci_data;
190 struct platform_device *ehci;
191 struct platform_device *ohci;
192 struct resource *res;
193 struct resource resources[2];
194 int ret;
195
196 omap = platform_get_drvdata(pdev);
197 ehci_data = omap->platdata.ehci_data;
198 ohci_data = omap->platdata.ohci_data;
199
200 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ehci");
201 if (!res) {
202 dev_err(dev, "EHCI get resource IORESOURCE_MEM failed\n");
203 ret = -ENODEV;
204 goto err_end;
205 }
206 resources[0] = *res;
207
208 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ehci-irq");
209 if (!res) {
210 dev_err(dev, " EHCI get resource IORESOURCE_IRQ failed\n");
211 ret = -ENODEV;
212 goto err_end;
213 }
214 resources[1] = *res;
215
216 ehci = omap_usbhs_alloc_child(OMAP_EHCI_DEVICE, resources, 2, ehci_data,
217 sizeof(*ehci_data), dev);
218
219 if (!ehci) {
220 dev_err(dev, "omap_usbhs_alloc_child failed\n");
221 ret = -ENOMEM;
222 goto err_end;
223 }
224
225 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ohci");
226 if (!res) {
227 dev_err(dev, "OHCI get resource IORESOURCE_MEM failed\n");
228 ret = -ENODEV;
229 goto err_ehci;
230 }
231 resources[0] = *res;
232
233 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ohci-irq");
234 if (!res) {
235 dev_err(dev, "OHCI get resource IORESOURCE_IRQ failed\n");
236 ret = -ENODEV;
237 goto err_ehci;
238 }
239 resources[1] = *res;
240
241 ohci = omap_usbhs_alloc_child(OMAP_OHCI_DEVICE, resources, 2, ohci_data,
242 sizeof(*ohci_data), dev);
243 if (!ohci) {
244 dev_err(dev, "omap_usbhs_alloc_child failed\n");
245 ret = -ENOMEM;
246 goto err_ehci;
247 }
248
249 return 0;
250
251 err_ehci:
252 platform_device_unregister(ehci);
253
254 err_end:
255 return ret;
256 }
257
258 static bool is_ohci_port(enum usbhs_omap_port_mode pmode)
259 {
260 switch (pmode) {
261 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
262 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
263 case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
264 case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
265 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
266 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
267 case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
268 case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
269 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
270 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
271 return true;
272
273 default:
274 return false;
275 }
276 }
277
278 static int usbhs_runtime_resume(struct device *dev)
279 {
280 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
281 struct usbhs_omap_platform_data *pdata = &omap->platdata;
282 unsigned long flags;
283
284 dev_dbg(dev, "usbhs_runtime_resume\n");
285
286 if (!pdata) {
287 dev_dbg(dev, "missing platform_data\n");
288 return -ENODEV;
289 }
290
291 omap_tll_enable();
292 spin_lock_irqsave(&omap->lock, flags);
293
294 if (omap->ehci_logic_fck && !IS_ERR(omap->ehci_logic_fck))
295 clk_enable(omap->ehci_logic_fck);
296
297 if (is_ehci_tll_mode(pdata->port_mode[0]))
298 clk_enable(omap->usbhost_p1_fck);
299 if (is_ehci_tll_mode(pdata->port_mode[1]))
300 clk_enable(omap->usbhost_p2_fck);
301
302 clk_enable(omap->utmi_p1_fck);
303 clk_enable(omap->utmi_p2_fck);
304
305 spin_unlock_irqrestore(&omap->lock, flags);
306
307 return 0;
308 }
309
310 static int usbhs_runtime_suspend(struct device *dev)
311 {
312 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
313 struct usbhs_omap_platform_data *pdata = &omap->platdata;
314 unsigned long flags;
315
316 dev_dbg(dev, "usbhs_runtime_suspend\n");
317
318 if (!pdata) {
319 dev_dbg(dev, "missing platform_data\n");
320 return -ENODEV;
321 }
322
323 spin_lock_irqsave(&omap->lock, flags);
324
325 if (is_ehci_tll_mode(pdata->port_mode[0]))
326 clk_disable(omap->usbhost_p1_fck);
327 if (is_ehci_tll_mode(pdata->port_mode[1]))
328 clk_disable(omap->usbhost_p2_fck);
329
330 clk_disable(omap->utmi_p2_fck);
331 clk_disable(omap->utmi_p1_fck);
332
333 if (omap->ehci_logic_fck && !IS_ERR(omap->ehci_logic_fck))
334 clk_disable(omap->ehci_logic_fck);
335
336 spin_unlock_irqrestore(&omap->lock, flags);
337 omap_tll_disable();
338
339 return 0;
340 }
341
342 static void omap_usbhs_init(struct device *dev)
343 {
344 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
345 struct usbhs_omap_platform_data *pdata = &omap->platdata;
346 unsigned long flags;
347 unsigned reg;
348
349 dev_dbg(dev, "starting TI HSUSB Controller\n");
350
351 if (pdata->ehci_data->phy_reset) {
352 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0]))
353 gpio_request_one(pdata->ehci_data->reset_gpio_port[0],
354 GPIOF_OUT_INIT_LOW, "USB1 PHY reset");
355
356 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1]))
357 gpio_request_one(pdata->ehci_data->reset_gpio_port[1],
358 GPIOF_OUT_INIT_LOW, "USB2 PHY reset");
359
360 /* Hold the PHY in RESET for enough time till DIR is high */
361 udelay(10);
362 }
363
364 pm_runtime_get_sync(dev);
365 spin_lock_irqsave(&omap->lock, flags);
366 omap->usbhs_rev = usbhs_read(omap->uhh_base, OMAP_UHH_REVISION);
367 dev_dbg(dev, "OMAP UHH_REVISION 0x%x\n", omap->usbhs_rev);
368
369 reg = usbhs_read(omap->uhh_base, OMAP_UHH_HOSTCONFIG);
370 /* setup ULPI bypass and burst configurations */
371 reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
372 | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
373 | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN);
374 reg |= OMAP4_UHH_HOSTCONFIG_APP_START_CLK;
375 reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN;
376
377 if (is_omap_usbhs_rev1(omap)) {
378 if (pdata->port_mode[0] == OMAP_USBHS_PORT_MODE_UNUSED)
379 reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS;
380 if (pdata->port_mode[1] == OMAP_USBHS_PORT_MODE_UNUSED)
381 reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS;
382 if (pdata->port_mode[2] == OMAP_USBHS_PORT_MODE_UNUSED)
383 reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS;
384
385 /* Bypass the TLL module for PHY mode operation */
386 if (pdata->single_ulpi_bypass) {
387 dev_dbg(dev, "OMAP3 ES version <= ES2.1\n");
388 if (is_ehci_phy_mode(pdata->port_mode[0]) ||
389 is_ehci_phy_mode(pdata->port_mode[1]) ||
390 is_ehci_phy_mode(pdata->port_mode[2]))
391 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
392 else
393 reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
394 } else {
395 dev_dbg(dev, "OMAP3 ES version > ES2.1\n");
396 if (is_ehci_phy_mode(pdata->port_mode[0]))
397 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
398 else
399 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
400 if (is_ehci_phy_mode(pdata->port_mode[1]))
401 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
402 else
403 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
404 if (is_ehci_phy_mode(pdata->port_mode[2]))
405 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
406 else
407 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
408 }
409 } else if (is_omap_usbhs_rev2(omap)) {
410 /* Clear port mode fields for PHY mode*/
411 reg &= ~OMAP4_P1_MODE_CLEAR;
412 reg &= ~OMAP4_P2_MODE_CLEAR;
413
414 if (is_ehci_tll_mode(pdata->port_mode[0]) ||
415 (is_ohci_port(pdata->port_mode[0])))
416 reg |= OMAP4_P1_MODE_TLL;
417 else if (is_ehci_hsic_mode(pdata->port_mode[0]))
418 reg |= OMAP4_P1_MODE_HSIC;
419
420 if (is_ehci_tll_mode(pdata->port_mode[1]) ||
421 (is_ohci_port(pdata->port_mode[1])))
422 reg |= OMAP4_P2_MODE_TLL;
423 else if (is_ehci_hsic_mode(pdata->port_mode[1]))
424 reg |= OMAP4_P2_MODE_HSIC;
425 }
426
427 usbhs_write(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg);
428 dev_dbg(dev, "UHH setup done, uhh_hostconfig=%x\n", reg);
429
430 spin_unlock_irqrestore(&omap->lock, flags);
431
432 pm_runtime_put_sync(dev);
433 if (pdata->ehci_data->phy_reset) {
434 /* Hold the PHY in RESET for enough time till
435 * PHY is settled and ready
436 */
437 udelay(10);
438
439 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0]))
440 gpio_set_value_cansleep
441 (pdata->ehci_data->reset_gpio_port[0], 1);
442
443 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1]))
444 gpio_set_value_cansleep
445 (pdata->ehci_data->reset_gpio_port[1], 1);
446 }
447 }
448
449 static void omap_usbhs_deinit(struct device *dev)
450 {
451 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
452 struct usbhs_omap_platform_data *pdata = &omap->platdata;
453
454 if (pdata->ehci_data->phy_reset) {
455 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0]))
456 gpio_free(pdata->ehci_data->reset_gpio_port[0]);
457
458 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1]))
459 gpio_free(pdata->ehci_data->reset_gpio_port[1]);
460 }
461 }
462
463
464 /**
465 * usbhs_omap_probe - initialize TI-based HCDs
466 *
467 * Allocates basic resources for this USB host controller.
468 */
469 static int usbhs_omap_probe(struct platform_device *pdev)
470 {
471 struct device *dev = &pdev->dev;
472 struct usbhs_omap_platform_data *pdata = dev->platform_data;
473 struct usbhs_hcd_omap *omap;
474 struct resource *res;
475 int ret = 0;
476 int i;
477
478 if (!pdata) {
479 dev_err(dev, "Missing platform data\n");
480 ret = -ENOMEM;
481 goto end_probe;
482 }
483
484 omap = kzalloc(sizeof(*omap), GFP_KERNEL);
485 if (!omap) {
486 dev_err(dev, "Memory allocation failed\n");
487 ret = -ENOMEM;
488 goto end_probe;
489 }
490
491 spin_lock_init(&omap->lock);
492
493 for (i = 0; i < OMAP3_HS_USB_PORTS; i++)
494 omap->platdata.port_mode[i] = pdata->port_mode[i];
495
496 omap->platdata.ehci_data = pdata->ehci_data;
497 omap->platdata.ohci_data = pdata->ohci_data;
498
499 pm_runtime_enable(dev);
500
501
502 for (i = 0; i < OMAP3_HS_USB_PORTS; i++)
503 if (is_ehci_phy_mode(i) || is_ehci_tll_mode(i) ||
504 is_ehci_hsic_mode(i)) {
505 omap->ehci_logic_fck = clk_get(dev, "ehci_logic_fck");
506 if (IS_ERR(omap->ehci_logic_fck)) {
507 ret = PTR_ERR(omap->ehci_logic_fck);
508 dev_warn(dev, "ehci_logic_fck failed:%d\n",
509 ret);
510 }
511 break;
512 }
513
514 omap->utmi_p1_fck = clk_get(dev, "utmi_p1_gfclk");
515 if (IS_ERR(omap->utmi_p1_fck)) {
516 ret = PTR_ERR(omap->utmi_p1_fck);
517 dev_err(dev, "utmi_p1_gfclk failed error:%d\n", ret);
518 goto err_end;
519 }
520
521 omap->xclk60mhsp1_ck = clk_get(dev, "xclk60mhsp1_ck");
522 if (IS_ERR(omap->xclk60mhsp1_ck)) {
523 ret = PTR_ERR(omap->xclk60mhsp1_ck);
524 dev_err(dev, "xclk60mhsp1_ck failed error:%d\n", ret);
525 goto err_utmi_p1_fck;
526 }
527
528 omap->utmi_p2_fck = clk_get(dev, "utmi_p2_gfclk");
529 if (IS_ERR(omap->utmi_p2_fck)) {
530 ret = PTR_ERR(omap->utmi_p2_fck);
531 dev_err(dev, "utmi_p2_gfclk failed error:%d\n", ret);
532 goto err_xclk60mhsp1_ck;
533 }
534
535 omap->xclk60mhsp2_ck = clk_get(dev, "xclk60mhsp2_ck");
536 if (IS_ERR(omap->xclk60mhsp2_ck)) {
537 ret = PTR_ERR(omap->xclk60mhsp2_ck);
538 dev_err(dev, "xclk60mhsp2_ck failed error:%d\n", ret);
539 goto err_utmi_p2_fck;
540 }
541
542 omap->usbhost_p1_fck = clk_get(dev, "usb_host_hs_utmi_p1_clk");
543 if (IS_ERR(omap->usbhost_p1_fck)) {
544 ret = PTR_ERR(omap->usbhost_p1_fck);
545 dev_err(dev, "usbhost_p1_fck failed error:%d\n", ret);
546 goto err_xclk60mhsp2_ck;
547 }
548
549 omap->usbhost_p2_fck = clk_get(dev, "usb_host_hs_utmi_p2_clk");
550 if (IS_ERR(omap->usbhost_p2_fck)) {
551 ret = PTR_ERR(omap->usbhost_p2_fck);
552 dev_err(dev, "usbhost_p2_fck failed error:%d\n", ret);
553 goto err_usbhost_p1_fck;
554 }
555
556 omap->init_60m_fclk = clk_get(dev, "init_60m_fclk");
557 if (IS_ERR(omap->init_60m_fclk)) {
558 ret = PTR_ERR(omap->init_60m_fclk);
559 dev_err(dev, "init_60m_fclk failed error:%d\n", ret);
560 goto err_usbhost_p2_fck;
561 }
562
563 if (is_ehci_phy_mode(pdata->port_mode[0])) {
564 /* for OMAP3 , the clk set paretn fails */
565 ret = clk_set_parent(omap->utmi_p1_fck,
566 omap->xclk60mhsp1_ck);
567 if (ret != 0)
568 dev_err(dev, "xclk60mhsp1_ck set parent"
569 "failed error:%d\n", ret);
570 } else if (is_ehci_tll_mode(pdata->port_mode[0])) {
571 ret = clk_set_parent(omap->utmi_p1_fck,
572 omap->init_60m_fclk);
573 if (ret != 0)
574 dev_err(dev, "init_60m_fclk set parent"
575 "failed error:%d\n", ret);
576 }
577
578 if (is_ehci_phy_mode(pdata->port_mode[1])) {
579 ret = clk_set_parent(omap->utmi_p2_fck,
580 omap->xclk60mhsp2_ck);
581 if (ret != 0)
582 dev_err(dev, "xclk60mhsp2_ck set parent"
583 "failed error:%d\n", ret);
584 } else if (is_ehci_tll_mode(pdata->port_mode[1])) {
585 ret = clk_set_parent(omap->utmi_p2_fck,
586 omap->init_60m_fclk);
587 if (ret != 0)
588 dev_err(dev, "init_60m_fclk set parent"
589 "failed error:%d\n", ret);
590 }
591
592 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "uhh");
593 if (!res) {
594 dev_err(dev, "UHH EHCI get resource failed\n");
595 ret = -ENODEV;
596 goto err_init_60m_fclk;
597 }
598
599 omap->uhh_base = ioremap(res->start, resource_size(res));
600 if (!omap->uhh_base) {
601 dev_err(dev, "UHH ioremap failed\n");
602 ret = -ENOMEM;
603 goto err_init_60m_fclk;
604 }
605
606 platform_set_drvdata(pdev, omap);
607
608 omap_usbhs_init(dev);
609 ret = omap_usbhs_alloc_children(pdev);
610 if (ret) {
611 dev_err(dev, "omap_usbhs_alloc_children failed\n");
612 goto err_alloc;
613 }
614
615 goto end_probe;
616
617 err_alloc:
618 omap_usbhs_deinit(&pdev->dev);
619 iounmap(omap->uhh_base);
620
621 err_init_60m_fclk:
622 clk_put(omap->init_60m_fclk);
623
624 err_usbhost_p2_fck:
625 clk_put(omap->usbhost_p2_fck);
626
627 err_usbhost_p1_fck:
628 clk_put(omap->usbhost_p1_fck);
629
630 err_xclk60mhsp2_ck:
631 clk_put(omap->xclk60mhsp2_ck);
632
633 err_utmi_p2_fck:
634 clk_put(omap->utmi_p2_fck);
635
636 err_xclk60mhsp1_ck:
637 clk_put(omap->xclk60mhsp1_ck);
638
639 err_utmi_p1_fck:
640 clk_put(omap->utmi_p1_fck);
641
642 err_end:
643 clk_put(omap->ehci_logic_fck);
644 pm_runtime_disable(dev);
645 kfree(omap);
646
647 end_probe:
648 return ret;
649 }
650
651 /**
652 * usbhs_omap_remove - shutdown processing for UHH & TLL HCDs
653 * @pdev: USB Host Controller being removed
654 *
655 * Reverses the effect of usbhs_omap_probe().
656 */
657 static int usbhs_omap_remove(struct platform_device *pdev)
658 {
659 struct usbhs_hcd_omap *omap = platform_get_drvdata(pdev);
660
661 omap_usbhs_deinit(&pdev->dev);
662 iounmap(omap->uhh_base);
663 clk_put(omap->init_60m_fclk);
664 clk_put(omap->usbhost_p2_fck);
665 clk_put(omap->usbhost_p1_fck);
666 clk_put(omap->xclk60mhsp2_ck);
667 clk_put(omap->utmi_p2_fck);
668 clk_put(omap->xclk60mhsp1_ck);
669 clk_put(omap->utmi_p1_fck);
670 clk_put(omap->ehci_logic_fck);
671 pm_runtime_disable(&pdev->dev);
672 kfree(omap);
673
674 return 0;
675 }
676
677 static const struct dev_pm_ops usbhsomap_dev_pm_ops = {
678 .runtime_suspend = usbhs_runtime_suspend,
679 .runtime_resume = usbhs_runtime_resume,
680 };
681
682 static struct platform_driver usbhs_omap_driver = {
683 .driver = {
684 .name = (char *)usbhs_driver_name,
685 .owner = THIS_MODULE,
686 .pm = &usbhsomap_dev_pm_ops,
687 },
688 .remove = __exit_p(usbhs_omap_remove),
689 };
690
691 MODULE_AUTHOR("Keshava Munegowda <keshava_mgowda@ti.com>");
692 MODULE_ALIAS("platform:" USBHS_DRIVER_NAME);
693 MODULE_LICENSE("GPL v2");
694 MODULE_DESCRIPTION("usb host common core driver for omap EHCI and OHCI");
695
696 static int __init omap_usbhs_drvinit(void)
697 {
698 return platform_driver_probe(&usbhs_omap_driver, usbhs_omap_probe);
699 }
700
701 /*
702 * init before ehci and ohci drivers;
703 * The usbhs core driver should be initialized much before
704 * the omap ehci and ohci probe functions are called.
705 * This usbhs core driver should be initialized after
706 * usb tll driver
707 */
708 fs_initcall_sync(omap_usbhs_drvinit);
709
710 static void __exit omap_usbhs_drvexit(void)
711 {
712 platform_driver_unregister(&usbhs_omap_driver);
713 }
714 module_exit(omap_usbhs_drvexit);
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