2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/radeon_drm.h>
31 #include <asm/div64.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
36 static void avivo_crtc_load_lut(struct drm_crtc
*crtc
)
38 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
39 struct drm_device
*dev
= crtc
->dev
;
40 struct radeon_device
*rdev
= dev
->dev_private
;
43 DRM_DEBUG_KMS("%d\n", radeon_crtc
->crtc_id
);
44 WREG32(AVIVO_DC_LUTA_CONTROL
+ radeon_crtc
->crtc_offset
, 0);
46 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0);
47 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0);
48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0);
50 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0xffff);
51 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0xffff);
52 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0xffff);
54 WREG32(AVIVO_DC_LUT_RW_SELECT
, radeon_crtc
->crtc_id
);
55 WREG32(AVIVO_DC_LUT_RW_MODE
, 0);
56 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK
, 0x0000003f);
58 WREG8(AVIVO_DC_LUT_RW_INDEX
, 0);
59 for (i
= 0; i
< 256; i
++) {
60 WREG32(AVIVO_DC_LUT_30_COLOR
,
61 (radeon_crtc
->lut_r
[i
] << 20) |
62 (radeon_crtc
->lut_g
[i
] << 10) |
63 (radeon_crtc
->lut_b
[i
] << 0));
66 WREG32(AVIVO_D1GRPH_LUT_SEL
+ radeon_crtc
->crtc_offset
, radeon_crtc
->crtc_id
);
69 static void dce4_crtc_load_lut(struct drm_crtc
*crtc
)
71 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
72 struct drm_device
*dev
= crtc
->dev
;
73 struct radeon_device
*rdev
= dev
->dev_private
;
76 DRM_DEBUG_KMS("%d\n", radeon_crtc
->crtc_id
);
77 WREG32(EVERGREEN_DC_LUT_CONTROL
+ radeon_crtc
->crtc_offset
, 0);
79 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0);
80 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0);
81 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0);
83 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0xffff);
84 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0xffff);
85 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0xffff);
87 WREG32(EVERGREEN_DC_LUT_RW_MODE
+ radeon_crtc
->crtc_offset
, 0);
88 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK
+ radeon_crtc
->crtc_offset
, 0x00000007);
90 WREG32(EVERGREEN_DC_LUT_RW_INDEX
+ radeon_crtc
->crtc_offset
, 0);
91 for (i
= 0; i
< 256; i
++) {
92 WREG32(EVERGREEN_DC_LUT_30_COLOR
+ radeon_crtc
->crtc_offset
,
93 (radeon_crtc
->lut_r
[i
] << 20) |
94 (radeon_crtc
->lut_g
[i
] << 10) |
95 (radeon_crtc
->lut_b
[i
] << 0));
99 static void dce5_crtc_load_lut(struct drm_crtc
*crtc
)
101 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
102 struct drm_device
*dev
= crtc
->dev
;
103 struct radeon_device
*rdev
= dev
->dev_private
;
106 DRM_DEBUG_KMS("%d\n", radeon_crtc
->crtc_id
);
108 WREG32(NI_INPUT_CSC_CONTROL
+ radeon_crtc
->crtc_offset
,
109 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS
) |
110 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS
)));
111 WREG32(NI_PRESCALE_GRPH_CONTROL
+ radeon_crtc
->crtc_offset
,
112 NI_GRPH_PRESCALE_BYPASS
);
113 WREG32(NI_PRESCALE_OVL_CONTROL
+ radeon_crtc
->crtc_offset
,
114 NI_OVL_PRESCALE_BYPASS
);
115 WREG32(NI_INPUT_GAMMA_CONTROL
+ radeon_crtc
->crtc_offset
,
116 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT
) |
117 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT
)));
119 WREG32(EVERGREEN_DC_LUT_CONTROL
+ radeon_crtc
->crtc_offset
, 0);
121 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0);
122 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0);
123 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0);
125 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE
+ radeon_crtc
->crtc_offset
, 0xffff);
126 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN
+ radeon_crtc
->crtc_offset
, 0xffff);
127 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED
+ radeon_crtc
->crtc_offset
, 0xffff);
129 WREG32(EVERGREEN_DC_LUT_RW_MODE
+ radeon_crtc
->crtc_offset
, 0);
130 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK
+ radeon_crtc
->crtc_offset
, 0x00000007);
132 WREG32(EVERGREEN_DC_LUT_RW_INDEX
+ radeon_crtc
->crtc_offset
, 0);
133 for (i
= 0; i
< 256; i
++) {
134 WREG32(EVERGREEN_DC_LUT_30_COLOR
+ radeon_crtc
->crtc_offset
,
135 (radeon_crtc
->lut_r
[i
] << 20) |
136 (radeon_crtc
->lut_g
[i
] << 10) |
137 (radeon_crtc
->lut_b
[i
] << 0));
140 WREG32(NI_DEGAMMA_CONTROL
+ radeon_crtc
->crtc_offset
,
141 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS
) |
142 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS
) |
143 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS
) |
144 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS
)));
145 WREG32(NI_GAMUT_REMAP_CONTROL
+ radeon_crtc
->crtc_offset
,
146 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS
) |
147 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS
)));
148 WREG32(NI_REGAMMA_CONTROL
+ radeon_crtc
->crtc_offset
,
149 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS
) |
150 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS
)));
151 WREG32(NI_OUTPUT_CSC_CONTROL
+ radeon_crtc
->crtc_offset
,
152 (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS
) |
153 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS
)));
154 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
155 WREG32(0x6940 + radeon_crtc
->crtc_offset
, 0);
159 static void legacy_crtc_load_lut(struct drm_crtc
*crtc
)
161 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
162 struct drm_device
*dev
= crtc
->dev
;
163 struct radeon_device
*rdev
= dev
->dev_private
;
167 dac2_cntl
= RREG32(RADEON_DAC_CNTL2
);
168 if (radeon_crtc
->crtc_id
== 0)
169 dac2_cntl
&= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL
;
171 dac2_cntl
|= RADEON_DAC2_PALETTE_ACC_CTL
;
172 WREG32(RADEON_DAC_CNTL2
, dac2_cntl
);
174 WREG8(RADEON_PALETTE_INDEX
, 0);
175 for (i
= 0; i
< 256; i
++) {
176 WREG32(RADEON_PALETTE_30_DATA
,
177 (radeon_crtc
->lut_r
[i
] << 20) |
178 (radeon_crtc
->lut_g
[i
] << 10) |
179 (radeon_crtc
->lut_b
[i
] << 0));
183 void radeon_crtc_load_lut(struct drm_crtc
*crtc
)
185 struct drm_device
*dev
= crtc
->dev
;
186 struct radeon_device
*rdev
= dev
->dev_private
;
191 if (ASIC_IS_DCE5(rdev
))
192 dce5_crtc_load_lut(crtc
);
193 else if (ASIC_IS_DCE4(rdev
))
194 dce4_crtc_load_lut(crtc
);
195 else if (ASIC_IS_AVIVO(rdev
))
196 avivo_crtc_load_lut(crtc
);
198 legacy_crtc_load_lut(crtc
);
201 /** Sets the color ramps on behalf of fbcon */
202 void radeon_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
205 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
207 radeon_crtc
->lut_r
[regno
] = red
>> 6;
208 radeon_crtc
->lut_g
[regno
] = green
>> 6;
209 radeon_crtc
->lut_b
[regno
] = blue
>> 6;
212 /** Gets the color ramps on behalf of fbcon */
213 void radeon_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
214 u16
*blue
, int regno
)
216 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
218 *red
= radeon_crtc
->lut_r
[regno
] << 6;
219 *green
= radeon_crtc
->lut_g
[regno
] << 6;
220 *blue
= radeon_crtc
->lut_b
[regno
] << 6;
223 static void radeon_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
224 u16
*blue
, uint32_t start
, uint32_t size
)
226 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
227 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
229 /* userspace palettes are always correct as is */
230 for (i
= start
; i
< end
; i
++) {
231 radeon_crtc
->lut_r
[i
] = red
[i
] >> 6;
232 radeon_crtc
->lut_g
[i
] = green
[i
] >> 6;
233 radeon_crtc
->lut_b
[i
] = blue
[i
] >> 6;
235 radeon_crtc_load_lut(crtc
);
238 static void radeon_crtc_destroy(struct drm_crtc
*crtc
)
240 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
242 drm_crtc_cleanup(crtc
);
247 * Handle unpin events outside the interrupt handler proper.
249 static void radeon_unpin_work_func(struct work_struct
*__work
)
251 struct radeon_unpin_work
*work
=
252 container_of(__work
, struct radeon_unpin_work
, work
);
255 /* unpin of the old buffer */
256 r
= radeon_bo_reserve(work
->old_rbo
, false);
257 if (likely(r
== 0)) {
258 r
= radeon_bo_unpin(work
->old_rbo
);
259 if (unlikely(r
!= 0)) {
260 DRM_ERROR("failed to unpin buffer after flip\n");
262 radeon_bo_unreserve(work
->old_rbo
);
264 DRM_ERROR("failed to reserve buffer after flip\n");
266 drm_gem_object_unreference_unlocked(&work
->old_rbo
->gem_base
);
270 void radeon_crtc_handle_flip(struct radeon_device
*rdev
, int crtc_id
)
272 struct radeon_crtc
*radeon_crtc
= rdev
->mode_info
.crtcs
[crtc_id
];
273 struct radeon_unpin_work
*work
;
274 struct drm_pending_vblank_event
*e
;
280 spin_lock_irqsave(&rdev
->ddev
->event_lock
, flags
);
281 work
= radeon_crtc
->unpin_work
;
283 (work
->fence
&& !radeon_fence_signaled(work
->fence
))) {
284 spin_unlock_irqrestore(&rdev
->ddev
->event_lock
, flags
);
287 /* New pageflip, or just completion of a previous one? */
288 if (!radeon_crtc
->deferred_flip_completion
) {
289 /* do the flip (mmio) */
290 update_pending
= radeon_page_flip(rdev
, crtc_id
, work
->new_crtc_base
);
292 /* This is just a completion of a flip queued in crtc
293 * at last invocation. Make sure we go directly to
294 * completion routine.
297 radeon_crtc
->deferred_flip_completion
= 0;
300 /* Has the pageflip already completed in crtc, or is it certain
301 * to complete in this vblank?
303 if (update_pending
&&
304 (DRM_SCANOUTPOS_VALID
& radeon_get_crtc_scanoutpos(rdev
->ddev
, crtc_id
,
306 ((vpos
>= (99 * rdev
->mode_info
.crtcs
[crtc_id
]->base
.hwmode
.crtc_vdisplay
)/100) ||
307 (vpos
< 0 && !ASIC_IS_AVIVO(rdev
)))) {
308 /* crtc didn't flip in this target vblank interval,
309 * but flip is pending in crtc. Based on the current
310 * scanout position we know that the current frame is
311 * (nearly) complete and the flip will (likely)
312 * complete before the start of the next frame.
316 if (update_pending
) {
317 /* crtc didn't flip in this target vblank interval,
318 * but flip is pending in crtc. It will complete it
319 * in next vblank interval, so complete the flip at
322 radeon_crtc
->deferred_flip_completion
= 1;
323 spin_unlock_irqrestore(&rdev
->ddev
->event_lock
, flags
);
327 /* Pageflip (will be) certainly completed in this vblank. Clean up. */
328 radeon_crtc
->unpin_work
= NULL
;
330 /* wakeup userspace */
333 e
->event
.sequence
= drm_vblank_count_and_time(rdev
->ddev
, crtc_id
, &now
);
334 e
->event
.tv_sec
= now
.tv_sec
;
335 e
->event
.tv_usec
= now
.tv_usec
;
336 list_add_tail(&e
->base
.link
, &e
->base
.file_priv
->event_list
);
337 wake_up_interruptible(&e
->base
.file_priv
->event_wait
);
339 spin_unlock_irqrestore(&rdev
->ddev
->event_lock
, flags
);
341 drm_vblank_put(rdev
->ddev
, radeon_crtc
->crtc_id
);
342 radeon_fence_unref(&work
->fence
);
343 radeon_post_page_flip(work
->rdev
, work
->crtc_id
);
344 schedule_work(&work
->work
);
347 static int radeon_crtc_page_flip(struct drm_crtc
*crtc
,
348 struct drm_framebuffer
*fb
,
349 struct drm_pending_vblank_event
*event
)
351 struct drm_device
*dev
= crtc
->dev
;
352 struct radeon_device
*rdev
= dev
->dev_private
;
353 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
354 struct radeon_framebuffer
*old_radeon_fb
;
355 struct radeon_framebuffer
*new_radeon_fb
;
356 struct drm_gem_object
*obj
;
357 struct radeon_bo
*rbo
;
358 struct radeon_unpin_work
*work
;
360 u32 tiling_flags
, pitch_pixels
;
364 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
370 work
->crtc_id
= radeon_crtc
->crtc_id
;
371 old_radeon_fb
= to_radeon_framebuffer(crtc
->fb
);
372 new_radeon_fb
= to_radeon_framebuffer(fb
);
373 /* schedule unpin of the old buffer */
374 obj
= old_radeon_fb
->obj
;
375 /* take a reference to the old object */
376 drm_gem_object_reference(obj
);
377 rbo
= gem_to_radeon_bo(obj
);
379 obj
= new_radeon_fb
->obj
;
380 rbo
= gem_to_radeon_bo(obj
);
382 spin_lock(&rbo
->tbo
.bdev
->fence_lock
);
383 if (rbo
->tbo
.sync_obj
)
384 work
->fence
= radeon_fence_ref(rbo
->tbo
.sync_obj
);
385 spin_unlock(&rbo
->tbo
.bdev
->fence_lock
);
387 INIT_WORK(&work
->work
, radeon_unpin_work_func
);
389 /* We borrow the event spin lock for protecting unpin_work */
390 spin_lock_irqsave(&dev
->event_lock
, flags
);
391 if (radeon_crtc
->unpin_work
) {
392 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
396 radeon_crtc
->unpin_work
= work
;
397 radeon_crtc
->deferred_flip_completion
= 0;
398 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
400 /* pin the new buffer */
401 DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
404 r
= radeon_bo_reserve(rbo
, false);
405 if (unlikely(r
!= 0)) {
406 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
409 /* Only 27 bit offset for legacy CRTC */
410 r
= radeon_bo_pin_restricted(rbo
, RADEON_GEM_DOMAIN_VRAM
,
411 ASIC_IS_AVIVO(rdev
) ? 0 : 1 << 27, &base
);
412 if (unlikely(r
!= 0)) {
413 radeon_bo_unreserve(rbo
);
415 DRM_ERROR("failed to pin new rbo buffer before flip\n");
418 radeon_bo_get_tiling_flags(rbo
, &tiling_flags
, NULL
);
419 radeon_bo_unreserve(rbo
);
421 if (!ASIC_IS_AVIVO(rdev
)) {
422 /* crtc offset is from display base addr not FB location */
423 base
-= radeon_crtc
->legacy_display_base_addr
;
424 pitch_pixels
= fb
->pitches
[0] / (fb
->bits_per_pixel
/ 8);
426 if (tiling_flags
& RADEON_TILING_MACRO
) {
427 if (ASIC_IS_R300(rdev
)) {
430 int byteshift
= fb
->bits_per_pixel
>> 4;
431 int tile_addr
= (((crtc
->y
>> 3) * pitch_pixels
+ crtc
->x
) >> (8 - byteshift
)) << 11;
432 base
+= tile_addr
+ ((crtc
->x
<< byteshift
) % 256) + ((crtc
->y
% 8) << 8);
435 int offset
= crtc
->y
* pitch_pixels
+ crtc
->x
;
436 switch (fb
->bits_per_pixel
) {
457 spin_lock_irqsave(&dev
->event_lock
, flags
);
458 work
->new_crtc_base
= base
;
459 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
464 r
= drm_vblank_get(dev
, radeon_crtc
->crtc_id
);
466 DRM_ERROR("failed to get vblank before flip\n");
470 /* set the proper interrupt */
471 radeon_pre_page_flip(rdev
, radeon_crtc
->crtc_id
);
476 if (unlikely(radeon_bo_reserve(rbo
, false) != 0)) {
477 DRM_ERROR("failed to reserve new rbo in error path\n");
480 if (unlikely(radeon_bo_unpin(rbo
) != 0)) {
481 DRM_ERROR("failed to unpin new rbo in error path\n");
483 radeon_bo_unreserve(rbo
);
486 spin_lock_irqsave(&dev
->event_lock
, flags
);
487 radeon_crtc
->unpin_work
= NULL
;
489 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
490 drm_gem_object_unreference_unlocked(old_radeon_fb
->obj
);
491 radeon_fence_unref(&work
->fence
);
497 static const struct drm_crtc_funcs radeon_crtc_funcs
= {
498 .cursor_set
= radeon_crtc_cursor_set
,
499 .cursor_move
= radeon_crtc_cursor_move
,
500 .gamma_set
= radeon_crtc_gamma_set
,
501 .set_config
= drm_crtc_helper_set_config
,
502 .destroy
= radeon_crtc_destroy
,
503 .page_flip
= radeon_crtc_page_flip
,
506 static void radeon_crtc_init(struct drm_device
*dev
, int index
)
508 struct radeon_device
*rdev
= dev
->dev_private
;
509 struct radeon_crtc
*radeon_crtc
;
512 radeon_crtc
= kzalloc(sizeof(struct radeon_crtc
) + (RADEONFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
513 if (radeon_crtc
== NULL
)
516 drm_crtc_init(dev
, &radeon_crtc
->base
, &radeon_crtc_funcs
);
518 drm_mode_crtc_set_gamma_size(&radeon_crtc
->base
, 256);
519 radeon_crtc
->crtc_id
= index
;
520 rdev
->mode_info
.crtcs
[index
] = radeon_crtc
;
523 radeon_crtc
->mode_set
.crtc
= &radeon_crtc
->base
;
524 radeon_crtc
->mode_set
.connectors
= (struct drm_connector
**)(radeon_crtc
+ 1);
525 radeon_crtc
->mode_set
.num_connectors
= 0;
528 for (i
= 0; i
< 256; i
++) {
529 radeon_crtc
->lut_r
[i
] = i
<< 2;
530 radeon_crtc
->lut_g
[i
] = i
<< 2;
531 radeon_crtc
->lut_b
[i
] = i
<< 2;
534 if (rdev
->is_atom_bios
&& (ASIC_IS_AVIVO(rdev
) || radeon_r4xx_atom
))
535 radeon_atombios_init_crtc(dev
, radeon_crtc
);
537 radeon_legacy_init_crtc(dev
, radeon_crtc
);
540 static const char *encoder_names
[37] = {
560 "INTERNAL_KLDSCP_TMDS1",
561 "INTERNAL_KLDSCP_DVO1",
562 "INTERNAL_KLDSCP_DAC1",
563 "INTERNAL_KLDSCP_DAC2",
572 "INTERNAL_KLDSCP_LVTMA",
580 static const char *hpd_names
[6] = {
589 static void radeon_print_display_setup(struct drm_device
*dev
)
591 struct drm_connector
*connector
;
592 struct radeon_connector
*radeon_connector
;
593 struct drm_encoder
*encoder
;
594 struct radeon_encoder
*radeon_encoder
;
598 DRM_INFO("Radeon Display Connectors\n");
599 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
600 radeon_connector
= to_radeon_connector(connector
);
601 DRM_INFO("Connector %d:\n", i
);
602 DRM_INFO(" %s\n", drm_get_connector_name(connector
));
603 if (radeon_connector
->hpd
.hpd
!= RADEON_HPD_NONE
)
604 DRM_INFO(" %s\n", hpd_names
[radeon_connector
->hpd
.hpd
]);
605 if (radeon_connector
->ddc_bus
) {
606 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
607 radeon_connector
->ddc_bus
->rec
.mask_clk_reg
,
608 radeon_connector
->ddc_bus
->rec
.mask_data_reg
,
609 radeon_connector
->ddc_bus
->rec
.a_clk_reg
,
610 radeon_connector
->ddc_bus
->rec
.a_data_reg
,
611 radeon_connector
->ddc_bus
->rec
.en_clk_reg
,
612 radeon_connector
->ddc_bus
->rec
.en_data_reg
,
613 radeon_connector
->ddc_bus
->rec
.y_clk_reg
,
614 radeon_connector
->ddc_bus
->rec
.y_data_reg
);
615 if (radeon_connector
->router
.ddc_valid
)
616 DRM_INFO(" DDC Router 0x%x/0x%x\n",
617 radeon_connector
->router
.ddc_mux_control_pin
,
618 radeon_connector
->router
.ddc_mux_state
);
619 if (radeon_connector
->router
.cd_valid
)
620 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
621 radeon_connector
->router
.cd_mux_control_pin
,
622 radeon_connector
->router
.cd_mux_state
);
624 if (connector
->connector_type
== DRM_MODE_CONNECTOR_VGA
||
625 connector
->connector_type
== DRM_MODE_CONNECTOR_DVII
||
626 connector
->connector_type
== DRM_MODE_CONNECTOR_DVID
||
627 connector
->connector_type
== DRM_MODE_CONNECTOR_DVIA
||
628 connector
->connector_type
== DRM_MODE_CONNECTOR_HDMIA
||
629 connector
->connector_type
== DRM_MODE_CONNECTOR_HDMIB
)
630 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
632 DRM_INFO(" Encoders:\n");
633 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
634 radeon_encoder
= to_radeon_encoder(encoder
);
635 devices
= radeon_encoder
->devices
& radeon_connector
->devices
;
637 if (devices
& ATOM_DEVICE_CRT1_SUPPORT
)
638 DRM_INFO(" CRT1: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
639 if (devices
& ATOM_DEVICE_CRT2_SUPPORT
)
640 DRM_INFO(" CRT2: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
641 if (devices
& ATOM_DEVICE_LCD1_SUPPORT
)
642 DRM_INFO(" LCD1: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
643 if (devices
& ATOM_DEVICE_DFP1_SUPPORT
)
644 DRM_INFO(" DFP1: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
645 if (devices
& ATOM_DEVICE_DFP2_SUPPORT
)
646 DRM_INFO(" DFP2: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
647 if (devices
& ATOM_DEVICE_DFP3_SUPPORT
)
648 DRM_INFO(" DFP3: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
649 if (devices
& ATOM_DEVICE_DFP4_SUPPORT
)
650 DRM_INFO(" DFP4: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
651 if (devices
& ATOM_DEVICE_DFP5_SUPPORT
)
652 DRM_INFO(" DFP5: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
653 if (devices
& ATOM_DEVICE_DFP6_SUPPORT
)
654 DRM_INFO(" DFP6: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
655 if (devices
& ATOM_DEVICE_TV1_SUPPORT
)
656 DRM_INFO(" TV1: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
657 if (devices
& ATOM_DEVICE_CV_SUPPORT
)
658 DRM_INFO(" CV: %s\n", encoder_names
[radeon_encoder
->encoder_id
]);
665 static bool radeon_setup_enc_conn(struct drm_device
*dev
)
667 struct radeon_device
*rdev
= dev
->dev_private
;
671 if (rdev
->is_atom_bios
) {
672 ret
= radeon_get_atom_connector_info_from_supported_devices_table(dev
);
674 ret
= radeon_get_atom_connector_info_from_object_table(dev
);
676 ret
= radeon_get_legacy_connector_info_from_bios(dev
);
678 ret
= radeon_get_legacy_connector_info_from_table(dev
);
681 if (!ASIC_IS_AVIVO(rdev
))
682 ret
= radeon_get_legacy_connector_info_from_table(dev
);
685 radeon_setup_encoder_clones(dev
);
686 radeon_print_display_setup(dev
);
692 int radeon_ddc_get_modes(struct radeon_connector
*radeon_connector
)
694 struct drm_device
*dev
= radeon_connector
->base
.dev
;
695 struct radeon_device
*rdev
= dev
->dev_private
;
698 /* on hw with routers, select right port */
699 if (radeon_connector
->router
.ddc_valid
)
700 radeon_router_select_ddc_port(radeon_connector
);
702 if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector
->base
) !=
703 ENCODER_OBJECT_ID_NONE
) {
704 struct radeon_connector_atom_dig
*dig
= radeon_connector
->con_priv
;
707 radeon_connector
->edid
= drm_get_edid(&radeon_connector
->base
,
708 &dig
->dp_i2c_bus
->adapter
);
709 } else if ((radeon_connector
->base
.connector_type
== DRM_MODE_CONNECTOR_DisplayPort
) ||
710 (radeon_connector
->base
.connector_type
== DRM_MODE_CONNECTOR_eDP
)) {
711 struct radeon_connector_atom_dig
*dig
= radeon_connector
->con_priv
;
713 if ((dig
->dp_sink_type
== CONNECTOR_OBJECT_ID_DISPLAYPORT
||
714 dig
->dp_sink_type
== CONNECTOR_OBJECT_ID_eDP
) && dig
->dp_i2c_bus
)
715 radeon_connector
->edid
= drm_get_edid(&radeon_connector
->base
,
716 &dig
->dp_i2c_bus
->adapter
);
717 else if (radeon_connector
->ddc_bus
&& !radeon_connector
->edid
)
718 radeon_connector
->edid
= drm_get_edid(&radeon_connector
->base
,
719 &radeon_connector
->ddc_bus
->adapter
);
721 if (radeon_connector
->ddc_bus
&& !radeon_connector
->edid
)
722 radeon_connector
->edid
= drm_get_edid(&radeon_connector
->base
,
723 &radeon_connector
->ddc_bus
->adapter
);
726 if (!radeon_connector
->edid
) {
727 if (rdev
->is_atom_bios
) {
728 /* some laptops provide a hardcoded edid in rom for LCDs */
729 if (((radeon_connector
->base
.connector_type
== DRM_MODE_CONNECTOR_LVDS
) ||
730 (radeon_connector
->base
.connector_type
== DRM_MODE_CONNECTOR_eDP
)))
731 radeon_connector
->edid
= radeon_bios_get_hardcoded_edid(rdev
);
733 /* some servers provide a hardcoded edid in rom for KVMs */
734 radeon_connector
->edid
= radeon_bios_get_hardcoded_edid(rdev
);
736 if (radeon_connector
->edid
) {
737 drm_mode_connector_update_edid_property(&radeon_connector
->base
, radeon_connector
->edid
);
738 ret
= drm_add_edid_modes(&radeon_connector
->base
, radeon_connector
->edid
);
741 drm_mode_connector_update_edid_property(&radeon_connector
->base
, NULL
);
746 static void avivo_get_fb_div(struct radeon_pll
*pll
,
753 u32 tmp
= post_div
* ref_div
;
756 *fb_div
= tmp
/ pll
->reference_freq
;
757 *frac_fb_div
= tmp
% pll
->reference_freq
;
759 if (*fb_div
> pll
->max_feedback_div
)
760 *fb_div
= pll
->max_feedback_div
;
761 else if (*fb_div
< pll
->min_feedback_div
)
762 *fb_div
= pll
->min_feedback_div
;
765 static u32
avivo_get_post_div(struct radeon_pll
*pll
,
768 u32 vco
, post_div
, tmp
;
770 if (pll
->flags
& RADEON_PLL_USE_POST_DIV
)
771 return pll
->post_div
;
773 if (pll
->flags
& RADEON_PLL_PREFER_MINM_OVER_MAXP
) {
774 if (pll
->flags
& RADEON_PLL_IS_LCD
)
775 vco
= pll
->lcd_pll_out_min
;
777 vco
= pll
->pll_out_min
;
779 if (pll
->flags
& RADEON_PLL_IS_LCD
)
780 vco
= pll
->lcd_pll_out_max
;
782 vco
= pll
->pll_out_max
;
785 post_div
= vco
/ target_clock
;
786 tmp
= vco
% target_clock
;
788 if (pll
->flags
& RADEON_PLL_PREFER_MINM_OVER_MAXP
) {
796 if (post_div
> pll
->max_post_div
)
797 post_div
= pll
->max_post_div
;
798 else if (post_div
< pll
->min_post_div
)
799 post_div
= pll
->min_post_div
;
804 #define MAX_TOLERANCE 10
806 void radeon_compute_pll_avivo(struct radeon_pll
*pll
,
814 u32 target_clock
= freq
/ 10;
815 u32 post_div
= avivo_get_post_div(pll
, target_clock
);
816 u32 ref_div
= pll
->min_ref_div
;
817 u32 fb_div
= 0, frac_fb_div
= 0, tmp
;
819 if (pll
->flags
& RADEON_PLL_USE_REF_DIV
)
820 ref_div
= pll
->reference_div
;
822 if (pll
->flags
& RADEON_PLL_USE_FRAC_FB_DIV
) {
823 avivo_get_fb_div(pll
, target_clock
, post_div
, ref_div
, &fb_div
, &frac_fb_div
);
824 frac_fb_div
= (100 * frac_fb_div
) / pll
->reference_freq
;
825 if (frac_fb_div
>= 5) {
827 frac_fb_div
= frac_fb_div
/ 10;
830 if (frac_fb_div
>= 10) {
835 while (ref_div
<= pll
->max_ref_div
) {
836 avivo_get_fb_div(pll
, target_clock
, post_div
, ref_div
,
837 &fb_div
, &frac_fb_div
);
838 if (frac_fb_div
>= (pll
->reference_freq
/ 2))
841 tmp
= (pll
->reference_freq
* fb_div
) / (post_div
* ref_div
);
842 tmp
= (tmp
* 10000) / target_clock
;
844 if (tmp
> (10000 + MAX_TOLERANCE
))
846 else if (tmp
>= (10000 - MAX_TOLERANCE
))
853 *dot_clock_p
= ((pll
->reference_freq
* fb_div
* 10) + (pll
->reference_freq
* frac_fb_div
)) /
854 (ref_div
* post_div
* 10);
856 *frac_fb_div_p
= frac_fb_div
;
857 *ref_div_p
= ref_div
;
858 *post_div_p
= post_div
;
859 DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",
860 *dot_clock_p
, fb_div
, frac_fb_div
, ref_div
, post_div
);
864 static inline uint32_t radeon_div(uint64_t n
, uint32_t d
)
874 void radeon_compute_pll_legacy(struct radeon_pll
*pll
,
876 uint32_t *dot_clock_p
,
878 uint32_t *frac_fb_div_p
,
880 uint32_t *post_div_p
)
882 uint32_t min_ref_div
= pll
->min_ref_div
;
883 uint32_t max_ref_div
= pll
->max_ref_div
;
884 uint32_t min_post_div
= pll
->min_post_div
;
885 uint32_t max_post_div
= pll
->max_post_div
;
886 uint32_t min_fractional_feed_div
= 0;
887 uint32_t max_fractional_feed_div
= 0;
888 uint32_t best_vco
= pll
->best_vco
;
889 uint32_t best_post_div
= 1;
890 uint32_t best_ref_div
= 1;
891 uint32_t best_feedback_div
= 1;
892 uint32_t best_frac_feedback_div
= 0;
893 uint32_t best_freq
= -1;
894 uint32_t best_error
= 0xffffffff;
895 uint32_t best_vco_diff
= 1;
897 u32 pll_out_min
, pll_out_max
;
899 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq
, pll
->min_ref_div
, pll
->max_ref_div
);
902 if (pll
->flags
& RADEON_PLL_IS_LCD
) {
903 pll_out_min
= pll
->lcd_pll_out_min
;
904 pll_out_max
= pll
->lcd_pll_out_max
;
906 pll_out_min
= pll
->pll_out_min
;
907 pll_out_max
= pll
->pll_out_max
;
910 if (pll_out_min
> 64800)
913 if (pll
->flags
& RADEON_PLL_USE_REF_DIV
)
914 min_ref_div
= max_ref_div
= pll
->reference_div
;
916 while (min_ref_div
< max_ref_div
-1) {
917 uint32_t mid
= (min_ref_div
+ max_ref_div
) / 2;
918 uint32_t pll_in
= pll
->reference_freq
/ mid
;
919 if (pll_in
< pll
->pll_in_min
)
921 else if (pll_in
> pll
->pll_in_max
)
928 if (pll
->flags
& RADEON_PLL_USE_POST_DIV
)
929 min_post_div
= max_post_div
= pll
->post_div
;
931 if (pll
->flags
& RADEON_PLL_USE_FRAC_FB_DIV
) {
932 min_fractional_feed_div
= pll
->min_frac_feedback_div
;
933 max_fractional_feed_div
= pll
->max_frac_feedback_div
;
936 for (post_div
= max_post_div
; post_div
>= min_post_div
; --post_div
) {
939 if ((pll
->flags
& RADEON_PLL_NO_ODD_POST_DIV
) && (post_div
& 1))
942 /* legacy radeons only have a few post_divs */
943 if (pll
->flags
& RADEON_PLL_LEGACY
) {
944 if ((post_div
== 5) ||
955 for (ref_div
= min_ref_div
; ref_div
<= max_ref_div
; ++ref_div
) {
956 uint32_t feedback_div
, current_freq
= 0, error
, vco_diff
;
957 uint32_t pll_in
= pll
->reference_freq
/ ref_div
;
958 uint32_t min_feed_div
= pll
->min_feedback_div
;
959 uint32_t max_feed_div
= pll
->max_feedback_div
+ 1;
961 if (pll_in
< pll
->pll_in_min
|| pll_in
> pll
->pll_in_max
)
964 while (min_feed_div
< max_feed_div
) {
966 uint32_t min_frac_feed_div
= min_fractional_feed_div
;
967 uint32_t max_frac_feed_div
= max_fractional_feed_div
+ 1;
968 uint32_t frac_feedback_div
;
971 feedback_div
= (min_feed_div
+ max_feed_div
) / 2;
973 tmp
= (uint64_t)pll
->reference_freq
* feedback_div
;
974 vco
= radeon_div(tmp
, ref_div
);
976 if (vco
< pll_out_min
) {
977 min_feed_div
= feedback_div
+ 1;
979 } else if (vco
> pll_out_max
) {
980 max_feed_div
= feedback_div
;
984 while (min_frac_feed_div
< max_frac_feed_div
) {
985 frac_feedback_div
= (min_frac_feed_div
+ max_frac_feed_div
) / 2;
986 tmp
= (uint64_t)pll
->reference_freq
* 10000 * feedback_div
;
987 tmp
+= (uint64_t)pll
->reference_freq
* 1000 * frac_feedback_div
;
988 current_freq
= radeon_div(tmp
, ref_div
* post_div
);
990 if (pll
->flags
& RADEON_PLL_PREFER_CLOSEST_LOWER
) {
991 if (freq
< current_freq
)
994 error
= freq
- current_freq
;
996 error
= abs(current_freq
- freq
);
997 vco_diff
= abs(vco
- best_vco
);
999 if ((best_vco
== 0 && error
< best_error
) ||
1001 ((best_error
> 100 && error
< best_error
- 100) ||
1002 (abs(error
- best_error
) < 100 && vco_diff
< best_vco_diff
)))) {
1003 best_post_div
= post_div
;
1004 best_ref_div
= ref_div
;
1005 best_feedback_div
= feedback_div
;
1006 best_frac_feedback_div
= frac_feedback_div
;
1007 best_freq
= current_freq
;
1009 best_vco_diff
= vco_diff
;
1010 } else if (current_freq
== freq
) {
1011 if (best_freq
== -1) {
1012 best_post_div
= post_div
;
1013 best_ref_div
= ref_div
;
1014 best_feedback_div
= feedback_div
;
1015 best_frac_feedback_div
= frac_feedback_div
;
1016 best_freq
= current_freq
;
1018 best_vco_diff
= vco_diff
;
1019 } else if (((pll
->flags
& RADEON_PLL_PREFER_LOW_REF_DIV
) && (ref_div
< best_ref_div
)) ||
1020 ((pll
->flags
& RADEON_PLL_PREFER_HIGH_REF_DIV
) && (ref_div
> best_ref_div
)) ||
1021 ((pll
->flags
& RADEON_PLL_PREFER_LOW_FB_DIV
) && (feedback_div
< best_feedback_div
)) ||
1022 ((pll
->flags
& RADEON_PLL_PREFER_HIGH_FB_DIV
) && (feedback_div
> best_feedback_div
)) ||
1023 ((pll
->flags
& RADEON_PLL_PREFER_LOW_POST_DIV
) && (post_div
< best_post_div
)) ||
1024 ((pll
->flags
& RADEON_PLL_PREFER_HIGH_POST_DIV
) && (post_div
> best_post_div
))) {
1025 best_post_div
= post_div
;
1026 best_ref_div
= ref_div
;
1027 best_feedback_div
= feedback_div
;
1028 best_frac_feedback_div
= frac_feedback_div
;
1029 best_freq
= current_freq
;
1031 best_vco_diff
= vco_diff
;
1034 if (current_freq
< freq
)
1035 min_frac_feed_div
= frac_feedback_div
+ 1;
1037 max_frac_feed_div
= frac_feedback_div
;
1039 if (current_freq
< freq
)
1040 min_feed_div
= feedback_div
+ 1;
1042 max_feed_div
= feedback_div
;
1047 *dot_clock_p
= best_freq
/ 10000;
1048 *fb_div_p
= best_feedback_div
;
1049 *frac_fb_div_p
= best_frac_feedback_div
;
1050 *ref_div_p
= best_ref_div
;
1051 *post_div_p
= best_post_div
;
1052 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1054 best_freq
/ 1000, best_feedback_div
, best_frac_feedback_div
,
1055 best_ref_div
, best_post_div
);
1059 static void radeon_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
1061 struct radeon_framebuffer
*radeon_fb
= to_radeon_framebuffer(fb
);
1063 if (radeon_fb
->obj
) {
1064 drm_gem_object_unreference_unlocked(radeon_fb
->obj
);
1066 drm_framebuffer_cleanup(fb
);
1070 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
1071 struct drm_file
*file_priv
,
1072 unsigned int *handle
)
1074 struct radeon_framebuffer
*radeon_fb
= to_radeon_framebuffer(fb
);
1076 return drm_gem_handle_create(file_priv
, radeon_fb
->obj
, handle
);
1079 static const struct drm_framebuffer_funcs radeon_fb_funcs
= {
1080 .destroy
= radeon_user_framebuffer_destroy
,
1081 .create_handle
= radeon_user_framebuffer_create_handle
,
1085 radeon_framebuffer_init(struct drm_device
*dev
,
1086 struct radeon_framebuffer
*rfb
,
1087 struct drm_mode_fb_cmd2
*mode_cmd
,
1088 struct drm_gem_object
*obj
)
1092 drm_helper_mode_fill_fb_struct(&rfb
->base
, mode_cmd
);
1093 ret
= drm_framebuffer_init(dev
, &rfb
->base
, &radeon_fb_funcs
);
1101 static struct drm_framebuffer
*
1102 radeon_user_framebuffer_create(struct drm_device
*dev
,
1103 struct drm_file
*file_priv
,
1104 struct drm_mode_fb_cmd2
*mode_cmd
)
1106 struct drm_gem_object
*obj
;
1107 struct radeon_framebuffer
*radeon_fb
;
1110 obj
= drm_gem_object_lookup(dev
, file_priv
, mode_cmd
->handles
[0]);
1112 dev_err(&dev
->pdev
->dev
, "No GEM object associated to handle 0x%08X, "
1113 "can't create framebuffer\n", mode_cmd
->handles
[0]);
1114 return ERR_PTR(-ENOENT
);
1117 radeon_fb
= kzalloc(sizeof(*radeon_fb
), GFP_KERNEL
);
1118 if (radeon_fb
== NULL
) {
1119 drm_gem_object_unreference_unlocked(obj
);
1120 return ERR_PTR(-ENOMEM
);
1123 ret
= radeon_framebuffer_init(dev
, radeon_fb
, mode_cmd
, obj
);
1126 drm_gem_object_unreference_unlocked(obj
);
1127 return ERR_PTR(ret
);
1130 return &radeon_fb
->base
;
1133 static void radeon_output_poll_changed(struct drm_device
*dev
)
1135 struct radeon_device
*rdev
= dev
->dev_private
;
1136 radeon_fb_output_poll_changed(rdev
);
1139 static const struct drm_mode_config_funcs radeon_mode_funcs
= {
1140 .fb_create
= radeon_user_framebuffer_create
,
1141 .output_poll_changed
= radeon_output_poll_changed
1144 static struct drm_prop_enum_list radeon_tmds_pll_enum_list
[] =
1149 static struct drm_prop_enum_list radeon_tv_std_enum_list
[] =
1150 { { TV_STD_NTSC
, "ntsc" },
1151 { TV_STD_PAL
, "pal" },
1152 { TV_STD_PAL_M
, "pal-m" },
1153 { TV_STD_PAL_60
, "pal-60" },
1154 { TV_STD_NTSC_J
, "ntsc-j" },
1155 { TV_STD_SCART_PAL
, "scart-pal" },
1156 { TV_STD_PAL_CN
, "pal-cn" },
1157 { TV_STD_SECAM
, "secam" },
1160 static struct drm_prop_enum_list radeon_underscan_enum_list
[] =
1161 { { UNDERSCAN_OFF
, "off" },
1162 { UNDERSCAN_ON
, "on" },
1163 { UNDERSCAN_AUTO
, "auto" },
1166 static int radeon_modeset_create_props(struct radeon_device
*rdev
)
1170 if (rdev
->is_atom_bios
) {
1171 rdev
->mode_info
.coherent_mode_property
=
1172 drm_property_create_range(rdev
->ddev
, 0 , "coherent", 0, 1);
1173 if (!rdev
->mode_info
.coherent_mode_property
)
1177 if (!ASIC_IS_AVIVO(rdev
)) {
1178 sz
= ARRAY_SIZE(radeon_tmds_pll_enum_list
);
1179 rdev
->mode_info
.tmds_pll_property
=
1180 drm_property_create_enum(rdev
->ddev
, 0,
1182 radeon_tmds_pll_enum_list
, sz
);
1185 rdev
->mode_info
.load_detect_property
=
1186 drm_property_create_range(rdev
->ddev
, 0, "load detection", 0, 1);
1187 if (!rdev
->mode_info
.load_detect_property
)
1190 drm_mode_create_scaling_mode_property(rdev
->ddev
);
1192 sz
= ARRAY_SIZE(radeon_tv_std_enum_list
);
1193 rdev
->mode_info
.tv_std_property
=
1194 drm_property_create_enum(rdev
->ddev
, 0,
1196 radeon_tv_std_enum_list
, sz
);
1198 sz
= ARRAY_SIZE(radeon_underscan_enum_list
);
1199 rdev
->mode_info
.underscan_property
=
1200 drm_property_create_enum(rdev
->ddev
, 0,
1202 radeon_underscan_enum_list
, sz
);
1204 rdev
->mode_info
.underscan_hborder_property
=
1205 drm_property_create_range(rdev
->ddev
, 0,
1206 "underscan hborder", 0, 128);
1207 if (!rdev
->mode_info
.underscan_hborder_property
)
1210 rdev
->mode_info
.underscan_vborder_property
=
1211 drm_property_create_range(rdev
->ddev
, 0,
1212 "underscan vborder", 0, 128);
1213 if (!rdev
->mode_info
.underscan_vborder_property
)
1219 void radeon_update_display_priority(struct radeon_device
*rdev
)
1221 /* adjustment options for the display watermarks */
1222 if ((radeon_disp_priority
== 0) || (radeon_disp_priority
> 2)) {
1223 /* set display priority to high for r3xx, rv515 chips
1224 * this avoids flickering due to underflow to the
1225 * display controllers during heavy acceleration.
1226 * Don't force high on rs4xx igp chips as it seems to
1227 * affect the sound card. See kernel bug 15982.
1229 if ((ASIC_IS_R300(rdev
) || (rdev
->family
== CHIP_RV515
)) &&
1230 !(rdev
->flags
& RADEON_IS_IGP
))
1231 rdev
->disp_priority
= 2;
1233 rdev
->disp_priority
= 0;
1235 rdev
->disp_priority
= radeon_disp_priority
;
1240 * Allocate hdmi structs and determine register offsets
1242 static void radeon_afmt_init(struct radeon_device
*rdev
)
1246 for (i
= 0; i
< RADEON_MAX_AFMT_BLOCKS
; i
++)
1247 rdev
->mode_info
.afmt
[i
] = NULL
;
1249 if (ASIC_IS_DCE6(rdev
)) {
1251 } else if (ASIC_IS_DCE4(rdev
)) {
1252 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1253 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1254 rdev
->mode_info
.afmt
[0] = kzalloc(sizeof(struct radeon_afmt
), GFP_KERNEL
);
1255 if (rdev
->mode_info
.afmt
[0]) {
1256 rdev
->mode_info
.afmt
[0]->offset
= EVERGREEN_CRTC0_REGISTER_OFFSET
;
1257 rdev
->mode_info
.afmt
[0]->id
= 0;
1259 rdev
->mode_info
.afmt
[1] = kzalloc(sizeof(struct radeon_afmt
), GFP_KERNEL
);
1260 if (rdev
->mode_info
.afmt
[1]) {
1261 rdev
->mode_info
.afmt
[1]->offset
= EVERGREEN_CRTC1_REGISTER_OFFSET
;
1262 rdev
->mode_info
.afmt
[1]->id
= 1;
1264 if (!ASIC_IS_DCE41(rdev
)) {
1265 rdev
->mode_info
.afmt
[2] = kzalloc(sizeof(struct radeon_afmt
), GFP_KERNEL
);
1266 if (rdev
->mode_info
.afmt
[2]) {
1267 rdev
->mode_info
.afmt
[2]->offset
= EVERGREEN_CRTC2_REGISTER_OFFSET
;
1268 rdev
->mode_info
.afmt
[2]->id
= 2;
1270 rdev
->mode_info
.afmt
[3] = kzalloc(sizeof(struct radeon_afmt
), GFP_KERNEL
);
1271 if (rdev
->mode_info
.afmt
[3]) {
1272 rdev
->mode_info
.afmt
[3]->offset
= EVERGREEN_CRTC3_REGISTER_OFFSET
;
1273 rdev
->mode_info
.afmt
[3]->id
= 3;
1275 rdev
->mode_info
.afmt
[4] = kzalloc(sizeof(struct radeon_afmt
), GFP_KERNEL
);
1276 if (rdev
->mode_info
.afmt
[4]) {
1277 rdev
->mode_info
.afmt
[4]->offset
= EVERGREEN_CRTC4_REGISTER_OFFSET
;
1278 rdev
->mode_info
.afmt
[4]->id
= 4;
1280 rdev
->mode_info
.afmt
[5] = kzalloc(sizeof(struct radeon_afmt
), GFP_KERNEL
);
1281 if (rdev
->mode_info
.afmt
[5]) {
1282 rdev
->mode_info
.afmt
[5]->offset
= EVERGREEN_CRTC5_REGISTER_OFFSET
;
1283 rdev
->mode_info
.afmt
[5]->id
= 5;
1286 } else if (ASIC_IS_DCE3(rdev
)) {
1287 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1288 rdev
->mode_info
.afmt
[0] = kzalloc(sizeof(struct radeon_afmt
), GFP_KERNEL
);
1289 if (rdev
->mode_info
.afmt
[0]) {
1290 rdev
->mode_info
.afmt
[0]->offset
= DCE3_HDMI_OFFSET0
;
1291 rdev
->mode_info
.afmt
[0]->id
= 0;
1293 rdev
->mode_info
.afmt
[1] = kzalloc(sizeof(struct radeon_afmt
), GFP_KERNEL
);
1294 if (rdev
->mode_info
.afmt
[1]) {
1295 rdev
->mode_info
.afmt
[1]->offset
= DCE3_HDMI_OFFSET1
;
1296 rdev
->mode_info
.afmt
[1]->id
= 1;
1298 } else if (ASIC_IS_DCE2(rdev
)) {
1299 /* DCE2 has at least 1 routable audio block */
1300 rdev
->mode_info
.afmt
[0] = kzalloc(sizeof(struct radeon_afmt
), GFP_KERNEL
);
1301 if (rdev
->mode_info
.afmt
[0]) {
1302 rdev
->mode_info
.afmt
[0]->offset
= DCE2_HDMI_OFFSET0
;
1303 rdev
->mode_info
.afmt
[0]->id
= 0;
1305 /* r6xx has 2 routable audio blocks */
1306 if (rdev
->family
>= CHIP_R600
) {
1307 rdev
->mode_info
.afmt
[1] = kzalloc(sizeof(struct radeon_afmt
), GFP_KERNEL
);
1308 if (rdev
->mode_info
.afmt
[1]) {
1309 rdev
->mode_info
.afmt
[1]->offset
= DCE2_HDMI_OFFSET1
;
1310 rdev
->mode_info
.afmt
[1]->id
= 1;
1316 static void radeon_afmt_fini(struct radeon_device
*rdev
)
1320 for (i
= 0; i
< RADEON_MAX_AFMT_BLOCKS
; i
++) {
1321 kfree(rdev
->mode_info
.afmt
[i
]);
1322 rdev
->mode_info
.afmt
[i
] = NULL
;
1326 int radeon_modeset_init(struct radeon_device
*rdev
)
1331 drm_mode_config_init(rdev
->ddev
);
1332 rdev
->mode_info
.mode_config_initialized
= true;
1334 rdev
->ddev
->mode_config
.funcs
= &radeon_mode_funcs
;
1336 if (ASIC_IS_DCE5(rdev
)) {
1337 rdev
->ddev
->mode_config
.max_width
= 16384;
1338 rdev
->ddev
->mode_config
.max_height
= 16384;
1339 } else if (ASIC_IS_AVIVO(rdev
)) {
1340 rdev
->ddev
->mode_config
.max_width
= 8192;
1341 rdev
->ddev
->mode_config
.max_height
= 8192;
1343 rdev
->ddev
->mode_config
.max_width
= 4096;
1344 rdev
->ddev
->mode_config
.max_height
= 4096;
1347 rdev
->ddev
->mode_config
.preferred_depth
= 24;
1348 rdev
->ddev
->mode_config
.prefer_shadow
= 1;
1350 rdev
->ddev
->mode_config
.fb_base
= rdev
->mc
.aper_base
;
1352 ret
= radeon_modeset_create_props(rdev
);
1357 /* init i2c buses */
1358 radeon_i2c_init(rdev
);
1360 /* check combios for a valid hardcoded EDID - Sun servers */
1361 if (!rdev
->is_atom_bios
) {
1362 /* check for hardcoded EDID in BIOS */
1363 radeon_combios_check_hardcoded_edid(rdev
);
1366 /* allocate crtcs */
1367 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
1368 radeon_crtc_init(rdev
->ddev
, i
);
1371 /* okay we should have all the bios connectors */
1372 ret
= radeon_setup_enc_conn(rdev
->ddev
);
1377 /* init dig PHYs, disp eng pll */
1378 if (rdev
->is_atom_bios
) {
1379 radeon_atom_encoder_init(rdev
);
1380 radeon_atom_disp_eng_pll_init(rdev
);
1383 /* initialize hpd */
1384 radeon_hpd_init(rdev
);
1387 radeon_afmt_init(rdev
);
1389 /* Initialize power management */
1390 radeon_pm_init(rdev
);
1392 radeon_fbdev_init(rdev
);
1393 drm_kms_helper_poll_init(rdev
->ddev
);
1398 void radeon_modeset_fini(struct radeon_device
*rdev
)
1400 radeon_fbdev_fini(rdev
);
1401 kfree(rdev
->mode_info
.bios_hardcoded_edid
);
1402 radeon_pm_fini(rdev
);
1404 if (rdev
->mode_info
.mode_config_initialized
) {
1405 radeon_afmt_fini(rdev
);
1406 drm_kms_helper_poll_fini(rdev
->ddev
);
1407 radeon_hpd_fini(rdev
);
1408 drm_mode_config_cleanup(rdev
->ddev
);
1409 rdev
->mode_info
.mode_config_initialized
= false;
1411 /* free i2c buses */
1412 radeon_i2c_fini(rdev
);
1415 static bool is_hdtv_mode(const struct drm_display_mode
*mode
)
1417 /* try and guess if this is a tv or a monitor */
1418 if ((mode
->vdisplay
== 480 && mode
->hdisplay
== 720) || /* 480p */
1419 (mode
->vdisplay
== 576) || /* 576p */
1420 (mode
->vdisplay
== 720) || /* 720p */
1421 (mode
->vdisplay
== 1080)) /* 1080p */
1427 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc
*crtc
,
1428 const struct drm_display_mode
*mode
,
1429 struct drm_display_mode
*adjusted_mode
)
1431 struct drm_device
*dev
= crtc
->dev
;
1432 struct radeon_device
*rdev
= dev
->dev_private
;
1433 struct drm_encoder
*encoder
;
1434 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
1435 struct radeon_encoder
*radeon_encoder
;
1436 struct drm_connector
*connector
;
1437 struct radeon_connector
*radeon_connector
;
1439 u32 src_v
= 1, dst_v
= 1;
1440 u32 src_h
= 1, dst_h
= 1;
1442 radeon_crtc
->h_border
= 0;
1443 radeon_crtc
->v_border
= 0;
1445 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
1446 if (encoder
->crtc
!= crtc
)
1448 radeon_encoder
= to_radeon_encoder(encoder
);
1449 connector
= radeon_get_connector_for_encoder(encoder
);
1450 radeon_connector
= to_radeon_connector(connector
);
1454 if (radeon_encoder
->rmx_type
== RMX_OFF
)
1455 radeon_crtc
->rmx_type
= RMX_OFF
;
1456 else if (mode
->hdisplay
< radeon_encoder
->native_mode
.hdisplay
||
1457 mode
->vdisplay
< radeon_encoder
->native_mode
.vdisplay
)
1458 radeon_crtc
->rmx_type
= radeon_encoder
->rmx_type
;
1460 radeon_crtc
->rmx_type
= RMX_OFF
;
1461 /* copy native mode */
1462 memcpy(&radeon_crtc
->native_mode
,
1463 &radeon_encoder
->native_mode
,
1464 sizeof(struct drm_display_mode
));
1465 src_v
= crtc
->mode
.vdisplay
;
1466 dst_v
= radeon_crtc
->native_mode
.vdisplay
;
1467 src_h
= crtc
->mode
.hdisplay
;
1468 dst_h
= radeon_crtc
->native_mode
.hdisplay
;
1470 /* fix up for overscan on hdmi */
1471 if (ASIC_IS_AVIVO(rdev
) &&
1472 (!(mode
->flags
& DRM_MODE_FLAG_INTERLACE
)) &&
1473 ((radeon_encoder
->underscan_type
== UNDERSCAN_ON
) ||
1474 ((radeon_encoder
->underscan_type
== UNDERSCAN_AUTO
) &&
1475 drm_detect_hdmi_monitor(radeon_connector
->edid
) &&
1476 is_hdtv_mode(mode
)))) {
1477 if (radeon_encoder
->underscan_hborder
!= 0)
1478 radeon_crtc
->h_border
= radeon_encoder
->underscan_hborder
;
1480 radeon_crtc
->h_border
= (mode
->hdisplay
>> 5) + 16;
1481 if (radeon_encoder
->underscan_vborder
!= 0)
1482 radeon_crtc
->v_border
= radeon_encoder
->underscan_vborder
;
1484 radeon_crtc
->v_border
= (mode
->vdisplay
>> 5) + 16;
1485 radeon_crtc
->rmx_type
= RMX_FULL
;
1486 src_v
= crtc
->mode
.vdisplay
;
1487 dst_v
= crtc
->mode
.vdisplay
- (radeon_crtc
->v_border
* 2);
1488 src_h
= crtc
->mode
.hdisplay
;
1489 dst_h
= crtc
->mode
.hdisplay
- (radeon_crtc
->h_border
* 2);
1493 if (radeon_crtc
->rmx_type
!= radeon_encoder
->rmx_type
) {
1494 /* WARNING: Right now this can't happen but
1495 * in the future we need to check that scaling
1496 * are consistent across different encoder
1497 * (ie all encoder can work with the same
1500 DRM_ERROR("Scaling not consistent across encoder.\n");
1505 if (radeon_crtc
->rmx_type
!= RMX_OFF
) {
1507 a
.full
= dfixed_const(src_v
);
1508 b
.full
= dfixed_const(dst_v
);
1509 radeon_crtc
->vsc
.full
= dfixed_div(a
, b
);
1510 a
.full
= dfixed_const(src_h
);
1511 b
.full
= dfixed_const(dst_h
);
1512 radeon_crtc
->hsc
.full
= dfixed_div(a
, b
);
1514 radeon_crtc
->vsc
.full
= dfixed_const(1);
1515 radeon_crtc
->hsc
.full
= dfixed_const(1);
1521 * Retrieve current video scanout position of crtc on a given gpu.
1523 * \param dev Device to query.
1524 * \param crtc Crtc to query.
1525 * \param *vpos Location where vertical scanout position should be stored.
1526 * \param *hpos Location where horizontal scanout position should go.
1528 * Returns vpos as a positive number while in active scanout area.
1529 * Returns vpos as a negative number inside vblank, counting the number
1530 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1531 * until start of active scanout / end of vblank."
1533 * \return Flags, or'ed together as follows:
1535 * DRM_SCANOUTPOS_VALID = Query successful.
1536 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1537 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1538 * this flag means that returned position may be offset by a constant but
1539 * unknown small number of scanlines wrt. real scanout position.
1542 int radeon_get_crtc_scanoutpos(struct drm_device
*dev
, int crtc
, int *vpos
, int *hpos
)
1544 u32 stat_crtc
= 0, vbl
= 0, position
= 0;
1545 int vbl_start
, vbl_end
, vtotal
, ret
= 0;
1548 struct radeon_device
*rdev
= dev
->dev_private
;
1550 if (ASIC_IS_DCE4(rdev
)) {
1552 vbl
= RREG32(EVERGREEN_CRTC_V_BLANK_START_END
+
1553 EVERGREEN_CRTC0_REGISTER_OFFSET
);
1554 position
= RREG32(EVERGREEN_CRTC_STATUS_POSITION
+
1555 EVERGREEN_CRTC0_REGISTER_OFFSET
);
1556 ret
|= DRM_SCANOUTPOS_VALID
;
1559 vbl
= RREG32(EVERGREEN_CRTC_V_BLANK_START_END
+
1560 EVERGREEN_CRTC1_REGISTER_OFFSET
);
1561 position
= RREG32(EVERGREEN_CRTC_STATUS_POSITION
+
1562 EVERGREEN_CRTC1_REGISTER_OFFSET
);
1563 ret
|= DRM_SCANOUTPOS_VALID
;
1566 vbl
= RREG32(EVERGREEN_CRTC_V_BLANK_START_END
+
1567 EVERGREEN_CRTC2_REGISTER_OFFSET
);
1568 position
= RREG32(EVERGREEN_CRTC_STATUS_POSITION
+
1569 EVERGREEN_CRTC2_REGISTER_OFFSET
);
1570 ret
|= DRM_SCANOUTPOS_VALID
;
1573 vbl
= RREG32(EVERGREEN_CRTC_V_BLANK_START_END
+
1574 EVERGREEN_CRTC3_REGISTER_OFFSET
);
1575 position
= RREG32(EVERGREEN_CRTC_STATUS_POSITION
+
1576 EVERGREEN_CRTC3_REGISTER_OFFSET
);
1577 ret
|= DRM_SCANOUTPOS_VALID
;
1580 vbl
= RREG32(EVERGREEN_CRTC_V_BLANK_START_END
+
1581 EVERGREEN_CRTC4_REGISTER_OFFSET
);
1582 position
= RREG32(EVERGREEN_CRTC_STATUS_POSITION
+
1583 EVERGREEN_CRTC4_REGISTER_OFFSET
);
1584 ret
|= DRM_SCANOUTPOS_VALID
;
1587 vbl
= RREG32(EVERGREEN_CRTC_V_BLANK_START_END
+
1588 EVERGREEN_CRTC5_REGISTER_OFFSET
);
1589 position
= RREG32(EVERGREEN_CRTC_STATUS_POSITION
+
1590 EVERGREEN_CRTC5_REGISTER_OFFSET
);
1591 ret
|= DRM_SCANOUTPOS_VALID
;
1593 } else if (ASIC_IS_AVIVO(rdev
)) {
1595 vbl
= RREG32(AVIVO_D1CRTC_V_BLANK_START_END
);
1596 position
= RREG32(AVIVO_D1CRTC_STATUS_POSITION
);
1597 ret
|= DRM_SCANOUTPOS_VALID
;
1600 vbl
= RREG32(AVIVO_D2CRTC_V_BLANK_START_END
);
1601 position
= RREG32(AVIVO_D2CRTC_STATUS_POSITION
);
1602 ret
|= DRM_SCANOUTPOS_VALID
;
1605 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1607 /* Assume vbl_end == 0, get vbl_start from
1610 vbl
= (RREG32(RADEON_CRTC_V_TOTAL_DISP
) &
1611 RADEON_CRTC_V_DISP
) >> RADEON_CRTC_V_DISP_SHIFT
;
1612 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1613 position
= (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE
) >> 16) & RADEON_CRTC_V_TOTAL
;
1614 stat_crtc
= RREG32(RADEON_CRTC_STATUS
);
1615 if (!(stat_crtc
& 1))
1618 ret
|= DRM_SCANOUTPOS_VALID
;
1621 vbl
= (RREG32(RADEON_CRTC2_V_TOTAL_DISP
) &
1622 RADEON_CRTC_V_DISP
) >> RADEON_CRTC_V_DISP_SHIFT
;
1623 position
= (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE
) >> 16) & RADEON_CRTC_V_TOTAL
;
1624 stat_crtc
= RREG32(RADEON_CRTC2_STATUS
);
1625 if (!(stat_crtc
& 1))
1628 ret
|= DRM_SCANOUTPOS_VALID
;
1632 /* Decode into vertical and horizontal scanout position. */
1633 *vpos
= position
& 0x1fff;
1634 *hpos
= (position
>> 16) & 0x1fff;
1636 /* Valid vblank area boundaries from gpu retrieved? */
1639 ret
|= DRM_SCANOUTPOS_ACCURATE
;
1640 vbl_start
= vbl
& 0x1fff;
1641 vbl_end
= (vbl
>> 16) & 0x1fff;
1644 /* No: Fake something reasonable which gives at least ok results. */
1645 vbl_start
= rdev
->mode_info
.crtcs
[crtc
]->base
.hwmode
.crtc_vdisplay
;
1649 /* Test scanout position against vblank region. */
1650 if ((*vpos
< vbl_start
) && (*vpos
>= vbl_end
))
1653 /* Check if inside vblank area and apply corrective offsets:
1654 * vpos will then be >=0 in video scanout area, but negative
1655 * within vblank area, counting down the number of lines until
1659 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1660 if (in_vbl
&& (*vpos
>= vbl_start
)) {
1661 vtotal
= rdev
->mode_info
.crtcs
[crtc
]->base
.hwmode
.crtc_vtotal
;
1662 *vpos
= *vpos
- vtotal
;
1665 /* Correct for shifted end of vbl at vbl_end. */
1666 *vpos
= *vpos
- vbl_end
;
1670 ret
|= DRM_SCANOUTPOS_INVBL
;