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netxen: firmware download support
[linux-2.6/btrfs-unstable.git] / drivers / net / netxen / netxen_nic_hw.c
blobaef39e7a5e291964f45009420462edd334cba97f
1 /*
2 * Copyright (C) 2003 - 2006 NetXen, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
22 *
23 * Contact Information:
24 * info@netxen.com
25 * NetXen,
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
28 *
29 *
30 * Source file for NIC routines to access the Phantom hardware
31 *
32 */
33
34 #include "netxen_nic.h"
35 #include "netxen_nic_hw.h"
36 #include "netxen_nic_phan_reg.h"
37
38 #include <linux/firmware.h>
39 #include <net/ip.h>
40
41 #define MASK(n) ((1ULL<<(n))-1)
42 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
43 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
44 #define MS_WIN(addr) (addr & 0x0ffc0000)
45
46 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
47
48 #define CRB_BLK(off) ((off >> 20) & 0x3f)
49 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
50 #define CRB_WINDOW_2M (0x130060)
51 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
52 #define CRB_INDIRECT_2M (0x1e0000UL)
53
54 #define CRB_WIN_LOCK_TIMEOUT 100000000
55 static crb_128M_2M_block_map_t crb_128M_2M_map[64] = {
56 {{{0, 0, 0, 0} } }, /* 0: PCI */
57 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
58 {1, 0x0110000, 0x0120000, 0x130000},
59 {1, 0x0120000, 0x0122000, 0x124000},
60 {1, 0x0130000, 0x0132000, 0x126000},
61 {1, 0x0140000, 0x0142000, 0x128000},
62 {1, 0x0150000, 0x0152000, 0x12a000},
63 {1, 0x0160000, 0x0170000, 0x110000},
64 {1, 0x0170000, 0x0172000, 0x12e000},
65 {0, 0x0000000, 0x0000000, 0x000000},
66 {0, 0x0000000, 0x0000000, 0x000000},
67 {0, 0x0000000, 0x0000000, 0x000000},
68 {0, 0x0000000, 0x0000000, 0x000000},
69 {0, 0x0000000, 0x0000000, 0x000000},
70 {0, 0x0000000, 0x0000000, 0x000000},
71 {1, 0x01e0000, 0x01e0800, 0x122000},
72 {0, 0x0000000, 0x0000000, 0x000000} } },
73 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
74 {{{0, 0, 0, 0} } }, /* 3: */
75 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
76 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
77 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
78 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
79 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
80 {0, 0x0000000, 0x0000000, 0x000000},
81 {0, 0x0000000, 0x0000000, 0x000000},
82 {0, 0x0000000, 0x0000000, 0x000000},
83 {0, 0x0000000, 0x0000000, 0x000000},
84 {0, 0x0000000, 0x0000000, 0x000000},
85 {0, 0x0000000, 0x0000000, 0x000000},
86 {0, 0x0000000, 0x0000000, 0x000000},
87 {0, 0x0000000, 0x0000000, 0x000000},
88 {0, 0x0000000, 0x0000000, 0x000000},
89 {0, 0x0000000, 0x0000000, 0x000000},
90 {0, 0x0000000, 0x0000000, 0x000000},
91 {0, 0x0000000, 0x0000000, 0x000000},
92 {0, 0x0000000, 0x0000000, 0x000000},
93 {0, 0x0000000, 0x0000000, 0x000000},
94 {1, 0x08f0000, 0x08f2000, 0x172000} } },
95 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
96 {0, 0x0000000, 0x0000000, 0x000000},
97 {0, 0x0000000, 0x0000000, 0x000000},
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {0, 0x0000000, 0x0000000, 0x000000},
108 {0, 0x0000000, 0x0000000, 0x000000},
109 {0, 0x0000000, 0x0000000, 0x000000},
110 {1, 0x09f0000, 0x09f2000, 0x176000} } },
111 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
112 {0, 0x0000000, 0x0000000, 0x000000},
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
127 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
143 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
144 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
145 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
146 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
147 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
148 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
149 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
150 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
151 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
152 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
153 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
154 {{{0, 0, 0, 0} } }, /* 23: */
155 {{{0, 0, 0, 0} } }, /* 24: */
156 {{{0, 0, 0, 0} } }, /* 25: */
157 {{{0, 0, 0, 0} } }, /* 26: */
158 {{{0, 0, 0, 0} } }, /* 27: */
159 {{{0, 0, 0, 0} } }, /* 28: */
160 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
161 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
162 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
163 {{{0} } }, /* 32: PCI */
164 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
165 {1, 0x2110000, 0x2120000, 0x130000},
166 {1, 0x2120000, 0x2122000, 0x124000},
167 {1, 0x2130000, 0x2132000, 0x126000},
168 {1, 0x2140000, 0x2142000, 0x128000},
169 {1, 0x2150000, 0x2152000, 0x12a000},
170 {1, 0x2160000, 0x2170000, 0x110000},
171 {1, 0x2170000, 0x2172000, 0x12e000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000} } },
180 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
181 {{{0} } }, /* 35: */
182 {{{0} } }, /* 36: */
183 {{{0} } }, /* 37: */
184 {{{0} } }, /* 38: */
185 {{{0} } }, /* 39: */
186 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
187 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
188 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
189 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
190 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
191 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
192 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
193 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
194 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
195 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
196 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
197 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
198 {{{0} } }, /* 52: */
199 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
200 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
201 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
202 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
203 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
204 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
205 {{{0} } }, /* 59: I2C0 */
206 {{{0} } }, /* 60: I2C1 */
207 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
208 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
209 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
210 };
211
212 /*
213 * top 12 bits of crb internal address (hub, agent)
214 */
215 static unsigned crb_hub_agt[64] =
216 {
217 0,
218 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
219 NETXEN_HW_CRB_HUB_AGT_ADR_MN,
220 NETXEN_HW_CRB_HUB_AGT_ADR_MS,
221 0,
222 NETXEN_HW_CRB_HUB_AGT_ADR_SRE,
223 NETXEN_HW_CRB_HUB_AGT_ADR_NIU,
224 NETXEN_HW_CRB_HUB_AGT_ADR_QMN,
225 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0,
226 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1,
227 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2,
228 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3,
229 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
230 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
231 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
232 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4,
233 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
234 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0,
235 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1,
236 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2,
237 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3,
238 NETXEN_HW_CRB_HUB_AGT_ADR_PGND,
239 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI,
240 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0,
241 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1,
242 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2,
243 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3,
244 0,
245 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI,
246 NETXEN_HW_CRB_HUB_AGT_ADR_SN,
247 0,
248 NETXEN_HW_CRB_HUB_AGT_ADR_EG,
249 0,
250 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
251 NETXEN_HW_CRB_HUB_AGT_ADR_CAM,
252 0,
253 0,
254 0,
255 0,
256 0,
257 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
258 0,
259 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1,
260 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2,
261 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3,
262 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4,
263 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5,
264 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6,
265 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7,
266 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
267 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
268 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
269 0,
270 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0,
271 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8,
272 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9,
273 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0,
274 0,
275 NETXEN_HW_CRB_HUB_AGT_ADR_SMB,
276 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0,
277 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1,
278 0,
279 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC,
280 0,
281 };
282
283 /* PCI Windowing for DDR regions. */
284
285 #define ADDR_IN_RANGE(addr, low, high) \
286 (((addr) <= (high)) && ((addr) >= (low)))
287
288 #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
289
290 #define NETXEN_NIC_ZERO_PAUSE_ADDR 0ULL
291 #define NETXEN_NIC_UNIT_PAUSE_ADDR 0x200ULL
292 #define NETXEN_NIC_EPG_PAUSE_ADDR1 0x2200010000c28001ULL
293 #define NETXEN_NIC_EPG_PAUSE_ADDR2 0x0100088866554433ULL
294
295 #define NETXEN_NIC_WINDOW_MARGIN 0x100000
296
297 int netxen_nic_set_mac(struct net_device *netdev, void *p)
298 {
299 struct netxen_adapter *adapter = netdev_priv(netdev);
300 struct sockaddr *addr = p;
301
302 if (netif_running(netdev))
303 return -EBUSY;
304
305 if (!is_valid_ether_addr(addr->sa_data))
306 return -EADDRNOTAVAIL;
307
308 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
309
310 /* For P3, MAC addr is not set in NIU */
311 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
312 if (adapter->macaddr_set)
313 adapter->macaddr_set(adapter, addr->sa_data);
314
315 return 0;
316 }
317
318 #define NETXEN_UNICAST_ADDR(port, index) \
319 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
320 #define NETXEN_MCAST_ADDR(port, index) \
321 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
322 #define MAC_HI(addr) \
323 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
324 #define MAC_LO(addr) \
325 ((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
326
327 static int
328 netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
329 {
330 u32 val = 0;
331 u16 port = adapter->physical_port;
332 u8 *addr = adapter->netdev->dev_addr;
333
334 if (adapter->mc_enabled)
335 return 0;
336
337 adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
338 val |= (1UL << (28+port));
339 adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
340
341 /* add broadcast addr to filter */
342 val = 0xffffff;
343 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
344 netxen_crb_writelit_adapter(adapter,
345 NETXEN_UNICAST_ADDR(port, 0)+4, val);
346
347 /* add station addr to filter */
348 val = MAC_HI(addr);
349 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
350 val = MAC_LO(addr);
351 netxen_crb_writelit_adapter(adapter,
352 NETXEN_UNICAST_ADDR(port, 1)+4, val);
353
354 adapter->mc_enabled = 1;
355 return 0;
356 }
357
358 static int
359 netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
360 {
361 u32 val = 0;
362 u16 port = adapter->physical_port;
363 u8 *addr = adapter->netdev->dev_addr;
364
365 if (!adapter->mc_enabled)
366 return 0;
367
368 adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
369 val &= ~(1UL << (28+port));
370 adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
371
372 val = MAC_HI(addr);
373 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
374 val = MAC_LO(addr);
375 netxen_crb_writelit_adapter(adapter,
376 NETXEN_UNICAST_ADDR(port, 0)+4, val);
377
378 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
379 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
380
381 adapter->mc_enabled = 0;
382 return 0;
383 }
384
385 static int
386 netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
387 int index, u8 *addr)
388 {
389 u32 hi = 0, lo = 0;
390 u16 port = adapter->physical_port;
391
392 lo = MAC_LO(addr);
393 hi = MAC_HI(addr);
394
395 netxen_crb_writelit_adapter(adapter,
396 NETXEN_MCAST_ADDR(port, index), hi);
397 netxen_crb_writelit_adapter(adapter,
398 NETXEN_MCAST_ADDR(port, index)+4, lo);
399
400 return 0;
401 }
402
403 void netxen_p2_nic_set_multi(struct net_device *netdev)
404 {
405 struct netxen_adapter *adapter = netdev_priv(netdev);
406 struct dev_mc_list *mc_ptr;
407 u8 null_addr[6];
408 int index = 0;
409
410 memset(null_addr, 0, 6);
411
412 if (netdev->flags & IFF_PROMISC) {
413
414 adapter->set_promisc(adapter,
415 NETXEN_NIU_PROMISC_MODE);
416
417 /* Full promiscuous mode */
418 netxen_nic_disable_mcast_filter(adapter);
419
420 return;
421 }
422
423 if (netdev->mc_count == 0) {
424 adapter->set_promisc(adapter,
425 NETXEN_NIU_NON_PROMISC_MODE);
426 netxen_nic_disable_mcast_filter(adapter);
427 return;
428 }
429
430 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE);
431 if (netdev->flags & IFF_ALLMULTI ||
432 netdev->mc_count > adapter->max_mc_count) {
433 netxen_nic_disable_mcast_filter(adapter);
434 return;
435 }
436
437 netxen_nic_enable_mcast_filter(adapter);
438
439 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next, index++)
440 netxen_nic_set_mcast_addr(adapter, index, mc_ptr->dmi_addr);
441
442 if (index != netdev->mc_count)
443 printk(KERN_WARNING "%s: %s multicast address count mismatch\n",
444 netxen_nic_driver_name, netdev->name);
445
446 /* Clear out remaining addresses */
447 for (; index < adapter->max_mc_count; index++)
448 netxen_nic_set_mcast_addr(adapter, index, null_addr);
449 }
450
451 static int nx_p3_nic_add_mac(struct netxen_adapter *adapter,
452 u8 *addr, nx_mac_list_t **add_list, nx_mac_list_t **del_list)
453 {
454 nx_mac_list_t *cur, *prev;
455
456 /* if in del_list, move it to adapter->mac_list */
457 for (cur = *del_list, prev = NULL; cur;) {
458 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) {
459 if (prev == NULL)
460 *del_list = cur->next;
461 else
462 prev->next = cur->next;
463 cur->next = adapter->mac_list;
464 adapter->mac_list = cur;
465 return 0;
466 }
467 prev = cur;
468 cur = cur->next;
469 }
470
471 /* make sure to add each mac address only once */
472 for (cur = adapter->mac_list; cur; cur = cur->next) {
473 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0)
474 return 0;
475 }
476 /* not in del_list, create new entry and add to add_list */
477 cur = kmalloc(sizeof(*cur), in_atomic()? GFP_ATOMIC : GFP_KERNEL);
478 if (cur == NULL) {
479 printk(KERN_ERR "%s: cannot allocate memory. MAC filtering may"
480 "not work properly from now.\n", __func__);
481 return -1;
482 }
483
484 memcpy(cur->mac_addr, addr, ETH_ALEN);
485 cur->next = *add_list;
486 *add_list = cur;
487 return 0;
488 }
489
490 static int
491 netxen_send_cmd_descs(struct netxen_adapter *adapter,
492 struct cmd_desc_type0 *cmd_desc_arr, int nr_elements)
493 {
494 uint32_t i, producer;
495 struct netxen_cmd_buffer *pbuf;
496 struct cmd_desc_type0 *cmd_desc;
497
498 if (nr_elements > MAX_PENDING_DESC_BLOCK_SIZE || nr_elements == 0) {
499 printk(KERN_WARNING "%s: Too many command descriptors in a "
500 "request\n", __func__);
501 return -EINVAL;
502 }
503
504 i = 0;
505
506 netif_tx_lock_bh(adapter->netdev);
507
508 producer = adapter->cmd_producer;
509 do {
510 cmd_desc = &cmd_desc_arr[i];
511
512 pbuf = &adapter->cmd_buf_arr[producer];
513 pbuf->skb = NULL;
514 pbuf->frag_count = 0;
515
516 /* adapter->ahw.cmd_desc_head[producer] = *cmd_desc; */
517 memcpy(&adapter->ahw.cmd_desc_head[producer],
518 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
519
520 producer = get_next_index(producer,
521 adapter->max_tx_desc_count);
522 i++;
523
524 } while (i != nr_elements);
525
526 adapter->cmd_producer = producer;
527
528 /* write producer index to start the xmit */
529
530 netxen_nic_update_cmd_producer(adapter, adapter->cmd_producer);
531
532 netif_tx_unlock_bh(adapter->netdev);
533
534 return 0;
535 }
536
537 static int nx_p3_sre_macaddr_change(struct net_device *dev,
538 u8 *addr, unsigned op)
539 {
540 struct netxen_adapter *adapter = netdev_priv(dev);
541 nx_nic_req_t req;
542 nx_mac_req_t *mac_req;
543 u64 word;
544 int rv;
545
546 memset(&req, 0, sizeof(nx_nic_req_t));
547 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
548
549 word = NX_MAC_EVENT | ((u64)adapter->portnum << 16);
550 req.req_hdr = cpu_to_le64(word);
551
552 mac_req = (nx_mac_req_t *)&req.words[0];
553 mac_req->op = op;
554 memcpy(mac_req->mac_addr, addr, 6);
555
556 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
557 if (rv != 0) {
558 printk(KERN_ERR "ERROR. Could not send mac update\n");
559 return rv;
560 }
561
562 return 0;
563 }
564
565 void netxen_p3_nic_set_multi(struct net_device *netdev)
566 {
567 struct netxen_adapter *adapter = netdev_priv(netdev);
568 nx_mac_list_t *cur, *next, *del_list, *add_list = NULL;
569 struct dev_mc_list *mc_ptr;
570 u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
571 u32 mode = VPORT_MISS_MODE_DROP;
572
573 del_list = adapter->mac_list;
574 adapter->mac_list = NULL;
575
576 nx_p3_nic_add_mac(adapter, netdev->dev_addr, &add_list, &del_list);
577 nx_p3_nic_add_mac(adapter, bcast_addr, &add_list, &del_list);
578
579 if (netdev->flags & IFF_PROMISC) {
580 mode = VPORT_MISS_MODE_ACCEPT_ALL;
581 goto send_fw_cmd;
582 }
583
584 if ((netdev->flags & IFF_ALLMULTI) ||
585 (netdev->mc_count > adapter->max_mc_count)) {
586 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
587 goto send_fw_cmd;
588 }
589
590 if (netdev->mc_count > 0) {
591 for (mc_ptr = netdev->mc_list; mc_ptr;
592 mc_ptr = mc_ptr->next) {
593 nx_p3_nic_add_mac(adapter, mc_ptr->dmi_addr,
594 &add_list, &del_list);
595 }
596 }
597
598 send_fw_cmd:
599 adapter->set_promisc(adapter, mode);
600 for (cur = del_list; cur;) {
601 nx_p3_sre_macaddr_change(netdev, cur->mac_addr, NETXEN_MAC_DEL);
602 next = cur->next;
603 kfree(cur);
604 cur = next;
605 }
606 for (cur = add_list; cur;) {
607 nx_p3_sre_macaddr_change(netdev, cur->mac_addr, NETXEN_MAC_ADD);
608 next = cur->next;
609 cur->next = adapter->mac_list;
610 adapter->mac_list = cur;
611 cur = next;
612 }
613 }
614
615 int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
616 {
617 nx_nic_req_t req;
618 u64 word;
619
620 memset(&req, 0, sizeof(nx_nic_req_t));
621
622 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
623
624 word = NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
625 ((u64)adapter->portnum << 16);
626 req.req_hdr = cpu_to_le64(word);
627
628 req.words[0] = cpu_to_le64(mode);
629
630 return netxen_send_cmd_descs(adapter,
631 (struct cmd_desc_type0 *)&req, 1);
632 }
633
634 void netxen_p3_free_mac_list(struct netxen_adapter *adapter)
635 {
636 nx_mac_list_t *cur, *next;
637
638 cur = adapter->mac_list;
639
640 while (cur) {
641 next = cur->next;
642 kfree(cur);
643 cur = next;
644 }
645 }
646
647 #define NETXEN_CONFIG_INTR_COALESCE 3
648
649 /*
650 * Send the interrupt coalescing parameter set by ethtool to the card.
651 */
652 int netxen_config_intr_coalesce(struct netxen_adapter *adapter)
653 {
654 nx_nic_req_t req;
655 u64 word;
656 int rv;
657
658 memset(&req, 0, sizeof(nx_nic_req_t));
659
660 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
661
662 word = NETXEN_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
663 req.req_hdr = cpu_to_le64(word);
664
665 memcpy(&req.words[0], &adapter->coal, sizeof(adapter->coal));
666
667 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
668 if (rv != 0) {
669 printk(KERN_ERR "ERROR. Could not send "
670 "interrupt coalescing parameters\n");
671 }
672
673 return rv;
674 }
675
676 /*
677 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
678 * @returns 0 on success, negative on failure
679 */
680
681 #define MTU_FUDGE_FACTOR 100
682
683 int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
684 {
685 struct netxen_adapter *adapter = netdev_priv(netdev);
686 int max_mtu;
687 int rc = 0;
688
689 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
690 max_mtu = P3_MAX_MTU;
691 else
692 max_mtu = P2_MAX_MTU;
693
694 if (mtu > max_mtu) {
695 printk(KERN_ERR "%s: mtu > %d bytes unsupported\n",
696 netdev->name, max_mtu);
697 return -EINVAL;
698 }
699
700 if (adapter->set_mtu)
701 rc = adapter->set_mtu(adapter, mtu);
702
703 if (!rc)
704 netdev->mtu = mtu;
705
706 return rc;
707 }
708
709 int netxen_is_flash_supported(struct netxen_adapter *adapter)
710 {
711 const int locs[] = { 0, 0x4, 0x100, 0x4000, 0x4128 };
712 int addr, val01, val02, i, j;
713
714 /* if the flash size less than 4Mb, make huge war cry and die */
715 for (j = 1; j < 4; j++) {
716 addr = j * NETXEN_NIC_WINDOW_MARGIN;
717 for (i = 0; i < ARRAY_SIZE(locs); i++) {
718 if (netxen_rom_fast_read(adapter, locs[i], &val01) == 0
719 && netxen_rom_fast_read(adapter, (addr + locs[i]),
720 &val02) == 0) {
721 if (val01 == val02)
722 return -1;
723 } else
724 return -1;
725 }
726 }
727
728 return 0;
729 }
730
731 static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
732 int size, __le32 * buf)
733 {
734 int i, addr;
735 __le32 *ptr32;
736 u32 v;
737
738 addr = base;
739 ptr32 = buf;
740 for (i = 0; i < size / sizeof(u32); i++) {
741 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
742 return -1;
743 *ptr32 = cpu_to_le32(v);
744 ptr32++;
745 addr += sizeof(u32);
746 }
747 if ((char *)buf + size > (char *)ptr32) {
748 __le32 local;
749 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
750 return -1;
751 local = cpu_to_le32(v);
752 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
753 }
754
755 return 0;
756 }
757
758 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
759 {
760 __le32 *pmac = (__le32 *) mac;
761 u32 offset;
762
763 offset = NETXEN_USER_START +
764 offsetof(struct netxen_new_user_info, mac_addr) +
765 adapter->portnum * sizeof(u64);
766
767 if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1)
768 return -1;
769
770 if (*mac == cpu_to_le64(~0ULL)) {
771
772 offset = NETXEN_USER_START_OLD +
773 offsetof(struct netxen_user_old_info, mac_addr) +
774 adapter->portnum * sizeof(u64);
775
776 if (netxen_get_flash_block(adapter,
777 offset, sizeof(u64), pmac) == -1)
778 return -1;
779
780 if (*mac == cpu_to_le64(~0ULL))
781 return -1;
782 }
783 return 0;
784 }
785
786 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
787 {
788 uint32_t crbaddr, mac_hi, mac_lo;
789 int pci_func = adapter->ahw.pci_func;
790
791 crbaddr = CRB_MAC_BLOCK_START +
792 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
793
794 adapter->hw_read_wx(adapter, crbaddr, &mac_lo, 4);
795 adapter->hw_read_wx(adapter, crbaddr+4, &mac_hi, 4);
796
797 if (pci_func & 1)
798 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
799 else
800 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32));
801
802 return 0;
803 }
804
805 #define CRB_WIN_LOCK_TIMEOUT 100000000
806
807 static int crb_win_lock(struct netxen_adapter *adapter)
808 {
809 int done = 0, timeout = 0;
810
811 while (!done) {
812 /* acquire semaphore3 from PCI HW block */
813 adapter->hw_read_wx(adapter,
814 NETXEN_PCIE_REG(PCIE_SEM7_LOCK), &done, 4);
815 if (done == 1)
816 break;
817 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
818 return -1;
819 timeout++;
820 udelay(1);
821 }
822 netxen_crb_writelit_adapter(adapter,
823 NETXEN_CRB_WIN_LOCK_ID, adapter->portnum);
824 return 0;
825 }
826
827 static void crb_win_unlock(struct netxen_adapter *adapter)
828 {
829 int val;
830
831 adapter->hw_read_wx(adapter,
832 NETXEN_PCIE_REG(PCIE_SEM7_UNLOCK), &val, 4);
833 }
834
835 /*
836 * Changes the CRB window to the specified window.
837 */
838 void
839 netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter, u32 wndw)
840 {
841 void __iomem *offset;
842 u32 tmp;
843 int count = 0;
844 uint8_t func = adapter->ahw.pci_func;
845
846 if (adapter->curr_window == wndw)
847 return;
848 /*
849 * Move the CRB window.
850 * We need to write to the "direct access" region of PCI
851 * to avoid a race condition where the window register has
852 * not been successfully written across CRB before the target
853 * register address is received by PCI. The direct region bypasses
854 * the CRB bus.
855 */
856 offset = PCI_OFFSET_SECOND_RANGE(adapter,
857 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func)));
858
859 if (wndw & 0x1)
860 wndw = NETXEN_WINDOW_ONE;
861
862 writel(wndw, offset);
863
864 /* MUST make sure window is set before we forge on... */
865 while ((tmp = readl(offset)) != wndw) {
866 printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
867 "registered properly: 0x%08x.\n",
868 netxen_nic_driver_name, __func__, tmp);
869 mdelay(1);
870 if (count >= 10)
871 break;
872 count++;
873 }
874
875 if (wndw == NETXEN_WINDOW_ONE)
876 adapter->curr_window = 1;
877 else
878 adapter->curr_window = 0;
879 }
880
881 /*
882 * Return -1 if off is not valid,
883 * 1 if window access is needed. 'off' is set to offset from
884 * CRB space in 128M pci map
885 * 0 if no window access is needed. 'off' is set to 2M addr
886 * In: 'off' is offset from base in 128M pci map
887 */
888 static int
889 netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter,
890 ulong *off, int len)
891 {
892 unsigned long end = *off + len;
893 crb_128M_2M_sub_block_map_t *m;
894
895
896 if (*off >= NETXEN_CRB_MAX)
897 return -1;
898
899 if (*off >= NETXEN_PCI_CAMQM && (end <= NETXEN_PCI_CAMQM_2M_END)) {
900 *off = (*off - NETXEN_PCI_CAMQM) + NETXEN_PCI_CAMQM_2M_BASE +
901 (ulong)adapter->ahw.pci_base0;
902 return 0;
903 }
904
905 if (*off < NETXEN_PCI_CRBSPACE)
906 return -1;
907
908 *off -= NETXEN_PCI_CRBSPACE;
909 end = *off + len;
910
911 /*
912 * Try direct map
913 */
914 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
915
916 if (m->valid && (m->start_128M <= *off) && (m->end_128M >= end)) {
917 *off = *off + m->start_2M - m->start_128M +
918 (ulong)adapter->ahw.pci_base0;
919 return 0;
920 }
921
922 /*
923 * Not in direct map, use crb window
924 */
925 return 1;
926 }
927
928 /*
929 * In: 'off' is offset from CRB space in 128M pci map
930 * Out: 'off' is 2M pci map addr
931 * side effect: lock crb window
932 */
933 static void
934 netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong *off)
935 {
936 u32 win_read;
937
938 adapter->crb_win = CRB_HI(*off);
939 writel(adapter->crb_win, (adapter->ahw.pci_base0 + CRB_WINDOW_2M));
940 /*
941 * Read back value to make sure write has gone through before trying
942 * to use it.
943 */
944 win_read = readl(adapter->ahw.pci_base0 + CRB_WINDOW_2M);
945 if (win_read != adapter->crb_win) {
946 printk(KERN_ERR "%s: Written crbwin (0x%x) != "
947 "Read crbwin (0x%x), off=0x%lx\n",
948 __func__, adapter->crb_win, win_read, *off);
949 }
950 *off = (*off & MASK(16)) + CRB_INDIRECT_2M +
951 (ulong)adapter->ahw.pci_base0;
952 }
953
954 static int
955 netxen_do_load_firmware(struct netxen_adapter *adapter, const char *fwname,
956 const struct firmware *fw)
957 {
958 u64 *ptr64;
959 u32 i, flashaddr, size;
960 struct pci_dev *pdev = adapter->pdev;
961
962 if (fw)
963 dev_info(&pdev->dev, "loading firmware from file %s\n", fwname);
964 else
965 dev_info(&pdev->dev, "loading firmware from flash\n");
966
967 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
968 adapter->pci_write_normalize(adapter,
969 NETXEN_ROMUSB_GLB_CAS_RST, 1);
970
971 if (fw) {
972 __le64 data;
973
974 size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
975
976 ptr64 = (u64 *)&fw->data[NETXEN_BOOTLD_START];
977 flashaddr = NETXEN_BOOTLD_START;
978
979 for (i = 0; i < size; i++) {
980 data = cpu_to_le64(ptr64[i]);
981 adapter->pci_mem_write(adapter, flashaddr, &data, 8);
982 flashaddr += 8;
983 }
984
985 size = *(u32 *)&fw->data[NX_FW_SIZE_OFFSET];
986 size = (__force u32)cpu_to_le32(size) / 8;
987
988 ptr64 = (u64 *)&fw->data[NETXEN_IMAGE_START];
989 flashaddr = NETXEN_IMAGE_START;
990
991 for (i = 0; i < size; i++) {
992 data = cpu_to_le64(ptr64[i]);
993
994 if (adapter->pci_mem_write(adapter,
995 flashaddr, &data, 8))
996 return -EIO;
997
998 flashaddr += 8;
999 }
1000 } else {
1001 u32 data;
1002
1003 size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 4;
1004 flashaddr = NETXEN_BOOTLD_START;
1005
1006 for (i = 0; i < size; i++) {
1007 if (netxen_rom_fast_read(adapter,
1008 flashaddr, (int *)&data) != 0)
1009 return -EIO;
1010
1011 if (adapter->pci_mem_write(adapter,
1012 flashaddr, &data, 4))
1013 return -EIO;
1014
1015 flashaddr += 4;
1016 }
1017 }
1018 msleep(1);
1019
1020 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
1021 adapter->pci_write_normalize(adapter,
1022 NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
1023 else {
1024 adapter->pci_write_normalize(adapter,
1025 NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
1026 adapter->pci_write_normalize(adapter,
1027 NETXEN_ROMUSB_GLB_CAS_RST, 0);
1028 }
1029
1030 return 0;
1031 }
1032
1033 static int
1034 netxen_validate_firmware(struct netxen_adapter *adapter, const char *fwname,
1035 const struct firmware *fw)
1036 {
1037 __le32 val;
1038 u32 major, minor, build, ver, min_ver, bios;
1039 struct pci_dev *pdev = adapter->pdev;
1040
1041 if (fw->size < NX_FW_MIN_SIZE)
1042 return -EINVAL;
1043
1044 val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]);
1045 if ((__force u32)val != NETXEN_BDINFO_MAGIC)
1046 return -EINVAL;
1047
1048 val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
1049 major = (__force u32)val & 0xff;
1050 minor = ((__force u32)val >> 8) & 0xff;
1051 build = (__force u32)val >> 16;
1052
1053 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
1054 min_ver = NETXEN_VERSION_CODE(4, 0, 216);
1055 else
1056 min_ver = NETXEN_VERSION_CODE(3, 4, 216);
1057
1058 ver = NETXEN_VERSION_CODE(major, minor, build);
1059
1060 if ((major > _NETXEN_NIC_LINUX_MAJOR) || (ver < min_ver)) {
1061 dev_err(&pdev->dev,
1062 "%s: firmware version %d.%d.%d unsupported\n",
1063 fwname, major, minor, build);
1064 return -EINVAL;
1065 }
1066
1067 val = cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]);
1068 netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios);
1069 if ((__force u32)val != bios) {
1070 dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
1071 fwname);
1072 return -EINVAL;
1073 }
1074
1075 netxen_nic_reg_write(adapter, NETXEN_CAM_RAM(0x1fc),
1076 NETXEN_BDINFO_MAGIC);
1077 return 0;
1078 }
1079
1080 int netxen_load_firmware(struct netxen_adapter *adapter)
1081 {
1082 u32 capability, flashed_ver;
1083 const struct firmware *fw;
1084 char *fw_name = NULL;
1085 struct pci_dev *pdev = adapter->pdev;
1086 int rc = 0;
1087
1088 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1089 fw_name = NX_P2_MN_ROMIMAGE;
1090 goto request_fw;
1091 }
1092
1093 capability = 0;
1094
1095 netxen_rom_fast_read(adapter,
1096 NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
1097 if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
1098 adapter->hw_read_wx(adapter,
1099 NX_PEG_TUNE_CAPABILITY, &capability, 4);
1100 if (capability & NX_PEG_TUNE_MN_PRESENT) {
1101 fw_name = NX_P3_MN_ROMIMAGE;
1102 goto request_fw;
1103 }
1104 }
1105
1106 request_ct:
1107 fw_name = NX_P3_CT_ROMIMAGE;
1108
1109 request_fw:
1110 rc = request_firmware(&fw, fw_name, &pdev->dev);
1111 if (rc != 0) {
1112 if (fw_name == NX_P3_MN_ROMIMAGE) {
1113 msleep(1);
1114 goto request_ct;
1115 }
1116
1117 fw = NULL;
1118 goto load_fw;
1119 }
1120
1121 rc = netxen_validate_firmware(adapter, fw_name, fw);
1122 if (rc != 0) {
1123 release_firmware(fw);
1124
1125 if (fw_name == NX_P3_MN_ROMIMAGE) {
1126 msleep(1);
1127 goto request_ct;
1128 }
1129
1130 fw = NULL;
1131 }
1132
1133 load_fw:
1134 rc = netxen_do_load_firmware(adapter, fw_name, fw);
1135
1136 if (fw)
1137 release_firmware(fw);
1138 return rc;
1139 }
1140
1141 int
1142 netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
1143 ulong off, void *data, int len)
1144 {
1145 void __iomem *addr;
1146
1147 BUG_ON(len != 4);
1148
1149 if (ADDR_IN_WINDOW1(off)) {
1150 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1151 } else { /* Window 0 */
1152 addr = pci_base_offset(adapter, off);
1153 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1154 }
1155
1156 if (!addr) {
1157 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1158 return 1;
1159 }
1160
1161 writel(*(u32 *) data, addr);
1162
1163 if (!ADDR_IN_WINDOW1(off))
1164 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1165
1166 return 0;
1167 }
1168
1169 int
1170 netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter,
1171 ulong off, void *data, int len)
1172 {
1173 void __iomem *addr;
1174
1175 BUG_ON(len != 4);
1176
1177 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1178 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1179 } else { /* Window 0 */
1180 addr = pci_base_offset(adapter, off);
1181 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1182 }
1183
1184 if (!addr) {
1185 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1186 return 1;
1187 }
1188
1189 *(u32 *)data = readl(addr);
1190
1191 if (!ADDR_IN_WINDOW1(off))
1192 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1193
1194 return 0;
1195 }
1196
1197 int
1198 netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
1199 ulong off, void *data, int len)
1200 {
1201 unsigned long flags = 0;
1202 int rv;
1203
1204 BUG_ON(len != 4);
1205
1206 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len);
1207
1208 if (rv == -1) {
1209 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1210 __func__, off);
1211 dump_stack();
1212 return -1;
1213 }
1214
1215 if (rv == 1) {
1216 write_lock_irqsave(&adapter->adapter_lock, flags);
1217 crb_win_lock(adapter);
1218 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1219 writel(*(uint32_t *)data, (void __iomem *)off);
1220 crb_win_unlock(adapter);
1221 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1222 } else
1223 writel(*(uint32_t *)data, (void __iomem *)off);
1224
1225
1226 return 0;
1227 }
1228
1229 int
1230 netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter,
1231 ulong off, void *data, int len)
1232 {
1233 unsigned long flags = 0;
1234 int rv;
1235
1236 BUG_ON(len != 4);
1237
1238 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len);
1239
1240 if (rv == -1) {
1241 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1242 __func__, off);
1243 dump_stack();
1244 return -1;
1245 }
1246
1247 if (rv == 1) {
1248 write_lock_irqsave(&adapter->adapter_lock, flags);
1249 crb_win_lock(adapter);
1250 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1251 *(uint32_t *)data = readl((void __iomem *)off);
1252 crb_win_unlock(adapter);
1253 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1254 } else
1255 *(uint32_t *)data = readl((void __iomem *)off);
1256
1257 return 0;
1258 }
1259
1260 void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val)
1261 {
1262 adapter->hw_write_wx(adapter, off, &val, 4);
1263 }
1264
1265 int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off)
1266 {
1267 int val;
1268 adapter->hw_read_wx(adapter, off, &val, 4);
1269 return val;
1270 }
1271
1272 /* Change the window to 0, write and change back to window 1. */
1273 void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value)
1274 {
1275 adapter->hw_write_wx(adapter, index, &value, 4);
1276 }
1277
1278 /* Change the window to 0, read and change back to window 1. */
1279 void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 *value)
1280 {
1281 adapter->hw_read_wx(adapter, index, value, 4);
1282 }
1283
1284 void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value)
1285 {
1286 adapter->hw_write_wx(adapter, index, &value, 4);
1287 }
1288
1289 void netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index, u32 *value)
1290 {
1291 adapter->hw_read_wx(adapter, index, value, 4);
1292 }
1293
1294 /*
1295 * check memory access boundary.
1296 * used by test agent. support ddr access only for now
1297 */
1298 static unsigned long
1299 netxen_nic_pci_mem_bound_check(struct netxen_adapter *adapter,
1300 unsigned long long addr, int size)
1301 {
1302 if (!ADDR_IN_RANGE(addr,
1303 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1304 !ADDR_IN_RANGE(addr+size-1,
1305 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1306 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
1307 return 0;
1308 }
1309
1310 return 1;
1311 }
1312
1313 static int netxen_pci_set_window_warning_count;
1314
1315 unsigned long
1316 netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1317 unsigned long long addr)
1318 {
1319 void __iomem *offset;
1320 int window;
1321 unsigned long long qdr_max;
1322 uint8_t func = adapter->ahw.pci_func;
1323
1324 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1325 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1326 } else {
1327 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1328 }
1329
1330 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1331 /* DDR network side */
1332 addr -= NETXEN_ADDR_DDR_NET;
1333 window = (addr >> 25) & 0x3ff;
1334 if (adapter->ahw.ddr_mn_window != window) {
1335 adapter->ahw.ddr_mn_window = window;
1336 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1337 NETXEN_PCIX_PH_REG(PCIE_MN_WINDOW_REG(func)));
1338 writel(window, offset);
1339 /* MUST make sure window is set before we forge on... */
1340 readl(offset);
1341 }
1342 addr -= (window * NETXEN_WINDOW_ONE);
1343 addr += NETXEN_PCI_DDR_NET;
1344 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1345 addr -= NETXEN_ADDR_OCM0;
1346 addr += NETXEN_PCI_OCM0;
1347 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1348 addr -= NETXEN_ADDR_OCM1;
1349 addr += NETXEN_PCI_OCM1;
1350 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1351 /* QDR network side */
1352 addr -= NETXEN_ADDR_QDR_NET;
1353 window = (addr >> 22) & 0x3f;
1354 if (adapter->ahw.qdr_sn_window != window) {
1355 adapter->ahw.qdr_sn_window = window;
1356 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1357 NETXEN_PCIX_PH_REG(PCIE_SN_WINDOW_REG(func)));
1358 writel((window << 22), offset);
1359 /* MUST make sure window is set before we forge on... */
1360 readl(offset);
1361 }
1362 addr -= (window * 0x400000);
1363 addr += NETXEN_PCI_QDR_NET;
1364 } else {
1365 /*
1366 * peg gdb frequently accesses memory that doesn't exist,
1367 * this limits the chit chat so debugging isn't slowed down.
1368 */
1369 if ((netxen_pci_set_window_warning_count++ < 8)
1370 || (netxen_pci_set_window_warning_count % 64 == 0))
1371 printk("%s: Warning:netxen_nic_pci_set_window()"
1372 " Unknown address range!\n",
1373 netxen_nic_driver_name);
1374 addr = -1UL;
1375 }
1376 return addr;
1377 }
1378
1379 /*
1380 * Note : only 32-bit writes!
1381 */
1382 int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1383 u64 off, u32 data)
1384 {
1385 writel(data, (void __iomem *)(PCI_OFFSET_SECOND_RANGE(adapter, off)));
1386 return 0;
1387 }
1388
1389 u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off)
1390 {
1391 return readl((void __iomem *)(pci_base_offset(adapter, off)));
1392 }
1393
1394 void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
1395 u64 off, u32 data)
1396 {
1397 writel(data, NETXEN_CRB_NORMALIZE(adapter, off));
1398 }
1399
1400 u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off)
1401 {
1402 return readl(NETXEN_CRB_NORMALIZE(adapter, off));
1403 }
1404
1405 unsigned long
1406 netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1407 unsigned long long addr)
1408 {
1409 int window;
1410 u32 win_read;
1411
1412 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1413 /* DDR network side */
1414 window = MN_WIN(addr);
1415 adapter->ahw.ddr_mn_window = window;
1416 adapter->hw_write_wx(adapter,
1417 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1418 &window, 4);
1419 adapter->hw_read_wx(adapter,
1420 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1421 &win_read, 4);
1422 if ((win_read << 17) != window) {
1423 printk(KERN_INFO "Written MNwin (0x%x) != "
1424 "Read MNwin (0x%x)\n", window, win_read);
1425 }
1426 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_DDR_NET;
1427 } else if (ADDR_IN_RANGE(addr,
1428 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1429 if ((addr & 0x00ff800) == 0xff800) {
1430 printk("%s: QM access not handled.\n", __func__);
1431 addr = -1UL;
1432 }
1433
1434 window = OCM_WIN(addr);
1435 adapter->ahw.ddr_mn_window = window;
1436 adapter->hw_write_wx(adapter,
1437 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1438 &window, 4);
1439 adapter->hw_read_wx(adapter,
1440 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1441 &win_read, 4);
1442 if ((win_read >> 7) != window) {
1443 printk(KERN_INFO "%s: Written OCMwin (0x%x) != "
1444 "Read OCMwin (0x%x)\n",
1445 __func__, window, win_read);
1446 }
1447 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_OCM0_2M;
1448
1449 } else if (ADDR_IN_RANGE(addr,
1450 NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX_P3)) {
1451 /* QDR network side */
1452 window = MS_WIN(addr);
1453 adapter->ahw.qdr_sn_window = window;
1454 adapter->hw_write_wx(adapter,
1455 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1456 &window, 4);
1457 adapter->hw_read_wx(adapter,
1458 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1459 &win_read, 4);
1460 if (win_read != window) {
1461 printk(KERN_INFO "%s: Written MSwin (0x%x) != "
1462 "Read MSwin (0x%x)\n",
1463 __func__, window, win_read);
1464 }
1465 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_QDR_NET;
1466
1467 } else {
1468 /*
1469 * peg gdb frequently accesses memory that doesn't exist,
1470 * this limits the chit chat so debugging isn't slowed down.
1471 */
1472 if ((netxen_pci_set_window_warning_count++ < 8)
1473 || (netxen_pci_set_window_warning_count%64 == 0)) {
1474 printk("%s: Warning:%s Unknown address range!\n",
1475 __func__, netxen_nic_driver_name);
1476 }
1477 addr = -1UL;
1478 }
1479 return addr;
1480 }
1481
1482 static int netxen_nic_pci_is_same_window(struct netxen_adapter *adapter,
1483 unsigned long long addr)
1484 {
1485 int window;
1486 unsigned long long qdr_max;
1487
1488 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1489 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1490 else
1491 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1492
1493 if (ADDR_IN_RANGE(addr,
1494 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1495 /* DDR network side */
1496 BUG(); /* MN access can not come here */
1497 } else if (ADDR_IN_RANGE(addr,
1498 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1499 return 1;
1500 } else if (ADDR_IN_RANGE(addr,
1501 NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1502 return 1;
1503 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1504 /* QDR network side */
1505 window = ((addr - NETXEN_ADDR_QDR_NET) >> 22) & 0x3f;
1506 if (adapter->ahw.qdr_sn_window == window)
1507 return 1;
1508 }
1509
1510 return 0;
1511 }
1512
1513 static int netxen_nic_pci_mem_read_direct(struct netxen_adapter *adapter,
1514 u64 off, void *data, int size)
1515 {
1516 unsigned long flags;
1517 void __iomem *addr, *mem_ptr = NULL;
1518 int ret = 0;
1519 u64 start;
1520 unsigned long mem_base;
1521 unsigned long mem_page;
1522
1523 write_lock_irqsave(&adapter->adapter_lock, flags);
1524
1525 /*
1526 * If attempting to access unknown address or straddle hw windows,
1527 * do not access.
1528 */
1529 start = adapter->pci_set_window(adapter, off);
1530 if ((start == -1UL) ||
1531 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1532 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1533 printk(KERN_ERR "%s out of bound pci memory access. "
1534 "offset is 0x%llx\n", netxen_nic_driver_name,
1535 (unsigned long long)off);
1536 return -1;
1537 }
1538
1539 addr = pci_base_offset(adapter, start);
1540 if (!addr) {
1541 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1542 mem_base = pci_resource_start(adapter->pdev, 0);
1543 mem_page = start & PAGE_MASK;
1544 /* Map two pages whenever user tries to access addresses in two
1545 consecutive pages.
1546 */
1547 if (mem_page != ((start + size - 1) & PAGE_MASK))
1548 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
1549 else
1550 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
1551 if (mem_ptr == NULL) {
1552 *(uint8_t *)data = 0;
1553 return -1;
1554 }
1555 addr = mem_ptr;
1556 addr += start & (PAGE_SIZE - 1);
1557 write_lock_irqsave(&adapter->adapter_lock, flags);
1558 }
1559
1560 switch (size) {
1561 case 1:
1562 *(uint8_t *)data = readb(addr);
1563 break;
1564 case 2:
1565 *(uint16_t *)data = readw(addr);
1566 break;
1567 case 4:
1568 *(uint32_t *)data = readl(addr);
1569 break;
1570 case 8:
1571 *(uint64_t *)data = readq(addr);
1572 break;
1573 default:
1574 ret = -1;
1575 break;
1576 }
1577 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1578
1579 if (mem_ptr)
1580 iounmap(mem_ptr);
1581 return ret;
1582 }
1583
1584 static int
1585 netxen_nic_pci_mem_write_direct(struct netxen_adapter *adapter, u64 off,
1586 void *data, int size)
1587 {
1588 unsigned long flags;
1589 void __iomem *addr, *mem_ptr = NULL;
1590 int ret = 0;
1591 u64 start;
1592 unsigned long mem_base;
1593 unsigned long mem_page;
1594
1595 write_lock_irqsave(&adapter->adapter_lock, flags);
1596
1597 /*
1598 * If attempting to access unknown address or straddle hw windows,
1599 * do not access.
1600 */
1601 start = adapter->pci_set_window(adapter, off);
1602 if ((start == -1UL) ||
1603 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1604 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1605 printk(KERN_ERR "%s out of bound pci memory access. "
1606 "offset is 0x%llx\n", netxen_nic_driver_name,
1607 (unsigned long long)off);
1608 return -1;
1609 }
1610
1611 addr = pci_base_offset(adapter, start);
1612 if (!addr) {
1613 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1614 mem_base = pci_resource_start(adapter->pdev, 0);
1615 mem_page = start & PAGE_MASK;
1616 /* Map two pages whenever user tries to access addresses in two
1617 * consecutive pages.
1618 */
1619 if (mem_page != ((start + size - 1) & PAGE_MASK))
1620 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
1621 else
1622 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
1623 if (mem_ptr == NULL)
1624 return -1;
1625 addr = mem_ptr;
1626 addr += start & (PAGE_SIZE - 1);
1627 write_lock_irqsave(&adapter->adapter_lock, flags);
1628 }
1629
1630 switch (size) {
1631 case 1:
1632 writeb(*(uint8_t *)data, addr);
1633 break;
1634 case 2:
1635 writew(*(uint16_t *)data, addr);
1636 break;
1637 case 4:
1638 writel(*(uint32_t *)data, addr);
1639 break;
1640 case 8:
1641 writeq(*(uint64_t *)data, addr);
1642 break;
1643 default:
1644 ret = -1;
1645 break;
1646 }
1647 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1648 if (mem_ptr)
1649 iounmap(mem_ptr);
1650 return ret;
1651 }
1652
1653 #define MAX_CTL_CHECK 1000
1654
1655 int
1656 netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1657 u64 off, void *data, int size)
1658 {
1659 unsigned long flags;
1660 int i, j, ret = 0, loop, sz[2], off0;
1661 uint32_t temp;
1662 uint64_t off8, tmpw, word[2] = {0, 0};
1663 void __iomem *mem_crb;
1664
1665 /*
1666 * If not MN, go check for MS or invalid.
1667 */
1668 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1669 return netxen_nic_pci_mem_write_direct(adapter,
1670 off, data, size);
1671
1672 off8 = off & 0xfffffff8;
1673 off0 = off & 0x7;
1674 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1675 sz[1] = size - sz[0];
1676 loop = ((off0 + size - 1) >> 3) + 1;
1677 mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1678
1679 if ((size != 8) || (off0 != 0)) {
1680 for (i = 0; i < loop; i++) {
1681 if (adapter->pci_mem_read(adapter,
1682 off8 + (i << 3), &word[i], 8))
1683 return -1;
1684 }
1685 }
1686
1687 switch (size) {
1688 case 1:
1689 tmpw = *((uint8_t *)data);
1690 break;
1691 case 2:
1692 tmpw = *((uint16_t *)data);
1693 break;
1694 case 4:
1695 tmpw = *((uint32_t *)data);
1696 break;
1697 case 8:
1698 default:
1699 tmpw = *((uint64_t *)data);
1700 break;
1701 }
1702 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1703 word[0] |= tmpw << (off0 * 8);
1704
1705 if (loop == 2) {
1706 word[1] &= ~(~0ULL << (sz[1] * 8));
1707 word[1] |= tmpw >> (sz[0] * 8);
1708 }
1709
1710 write_lock_irqsave(&adapter->adapter_lock, flags);
1711 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1712
1713 for (i = 0; i < loop; i++) {
1714 writel((uint32_t)(off8 + (i << 3)),
1715 (mem_crb+MIU_TEST_AGT_ADDR_LO));
1716 writel(0,
1717 (mem_crb+MIU_TEST_AGT_ADDR_HI));
1718 writel(word[i] & 0xffffffff,
1719 (mem_crb+MIU_TEST_AGT_WRDATA_LO));
1720 writel((word[i] >> 32) & 0xffffffff,
1721 (mem_crb+MIU_TEST_AGT_WRDATA_HI));
1722 writel(MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1723 (mem_crb+MIU_TEST_AGT_CTRL));
1724 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1725 (mem_crb+MIU_TEST_AGT_CTRL));
1726
1727 for (j = 0; j < MAX_CTL_CHECK; j++) {
1728 temp = readl(
1729 (mem_crb+MIU_TEST_AGT_CTRL));
1730 if ((temp & MIU_TA_CTL_BUSY) == 0)
1731 break;
1732 }
1733
1734 if (j >= MAX_CTL_CHECK) {
1735 if (printk_ratelimit())
1736 dev_err(&adapter->pdev->dev,
1737 "failed to write through agent\n");
1738 ret = -1;
1739 break;
1740 }
1741 }
1742
1743 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1744 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1745 return ret;
1746 }
1747
1748 int
1749 netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1750 u64 off, void *data, int size)
1751 {
1752 unsigned long flags;
1753 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1754 uint32_t temp;
1755 uint64_t off8, val, word[2] = {0, 0};
1756 void __iomem *mem_crb;
1757
1758
1759 /*
1760 * If not MN, go check for MS or invalid.
1761 */
1762 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1763 return netxen_nic_pci_mem_read_direct(adapter, off, data, size);
1764
1765 off8 = off & 0xfffffff8;
1766 off0[0] = off & 0x7;
1767 off0[1] = 0;
1768 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1769 sz[1] = size - sz[0];
1770 loop = ((off0[0] + size - 1) >> 3) + 1;
1771 mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1772
1773 write_lock_irqsave(&adapter->adapter_lock, flags);
1774 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1775
1776 for (i = 0; i < loop; i++) {
1777 writel((uint32_t)(off8 + (i << 3)),
1778 (mem_crb+MIU_TEST_AGT_ADDR_LO));
1779 writel(0,
1780 (mem_crb+MIU_TEST_AGT_ADDR_HI));
1781 writel(MIU_TA_CTL_ENABLE,
1782 (mem_crb+MIU_TEST_AGT_CTRL));
1783 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE,
1784 (mem_crb+MIU_TEST_AGT_CTRL));
1785
1786 for (j = 0; j < MAX_CTL_CHECK; j++) {
1787 temp = readl(
1788 (mem_crb+MIU_TEST_AGT_CTRL));
1789 if ((temp & MIU_TA_CTL_BUSY) == 0)
1790 break;
1791 }
1792
1793 if (j >= MAX_CTL_CHECK) {
1794 if (printk_ratelimit())
1795 dev_err(&adapter->pdev->dev,
1796 "failed to read through agent\n");
1797 break;
1798 }
1799
1800 start = off0[i] >> 2;
1801 end = (off0[i] + sz[i] - 1) >> 2;
1802 for (k = start; k <= end; k++) {
1803 word[i] |= ((uint64_t) readl(
1804 (mem_crb +
1805 MIU_TEST_AGT_RDDATA(k))) << (32*k));
1806 }
1807 }
1808
1809 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1810 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1811
1812 if (j >= MAX_CTL_CHECK)
1813 return -1;
1814
1815 if (sz[0] == 8) {
1816 val = word[0];
1817 } else {
1818 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1819 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1820 }
1821
1822 switch (size) {
1823 case 1:
1824 *(uint8_t *)data = val;
1825 break;
1826 case 2:
1827 *(uint16_t *)data = val;
1828 break;
1829 case 4:
1830 *(uint32_t *)data = val;
1831 break;
1832 case 8:
1833 *(uint64_t *)data = val;
1834 break;
1835 }
1836 return 0;
1837 }
1838
1839 int
1840 netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1841 u64 off, void *data, int size)
1842 {
1843 int i, j, ret = 0, loop, sz[2], off0;
1844 uint32_t temp;
1845 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1846
1847 /*
1848 * If not MN, go check for MS or invalid.
1849 */
1850 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1851 mem_crb = NETXEN_CRB_QDR_NET;
1852 else {
1853 mem_crb = NETXEN_CRB_DDR_NET;
1854 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1855 return netxen_nic_pci_mem_write_direct(adapter,
1856 off, data, size);
1857 }
1858
1859 off8 = off & 0xfffffff8;
1860 off0 = off & 0x7;
1861 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1862 sz[1] = size - sz[0];
1863 loop = ((off0 + size - 1) >> 3) + 1;
1864
1865 if ((size != 8) || (off0 != 0)) {
1866 for (i = 0; i < loop; i++) {
1867 if (adapter->pci_mem_read(adapter, off8 + (i << 3),
1868 &word[i], 8))
1869 return -1;
1870 }
1871 }
1872
1873 switch (size) {
1874 case 1:
1875 tmpw = *((uint8_t *)data);
1876 break;
1877 case 2:
1878 tmpw = *((uint16_t *)data);
1879 break;
1880 case 4:
1881 tmpw = *((uint32_t *)data);
1882 break;
1883 case 8:
1884 default:
1885 tmpw = *((uint64_t *)data);
1886 break;
1887 }
1888
1889 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1890 word[0] |= tmpw << (off0 * 8);
1891
1892 if (loop == 2) {
1893 word[1] &= ~(~0ULL << (sz[1] * 8));
1894 word[1] |= tmpw >> (sz[0] * 8);
1895 }
1896
1897 /*
1898 * don't lock here - write_wx gets the lock if each time
1899 * write_lock_irqsave(&adapter->adapter_lock, flags);
1900 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1901 */
1902
1903 for (i = 0; i < loop; i++) {
1904 temp = off8 + (i << 3);
1905 adapter->hw_write_wx(adapter,
1906 mem_crb+MIU_TEST_AGT_ADDR_LO, &temp, 4);
1907 temp = 0;
1908 adapter->hw_write_wx(adapter,
1909 mem_crb+MIU_TEST_AGT_ADDR_HI, &temp, 4);
1910 temp = word[i] & 0xffffffff;
1911 adapter->hw_write_wx(adapter,
1912 mem_crb+MIU_TEST_AGT_WRDATA_LO, &temp, 4);
1913 temp = (word[i] >> 32) & 0xffffffff;
1914 adapter->hw_write_wx(adapter,
1915 mem_crb+MIU_TEST_AGT_WRDATA_HI, &temp, 4);
1916 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1917 adapter->hw_write_wx(adapter,
1918 mem_crb+MIU_TEST_AGT_CTRL, &temp, 4);
1919 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1920 adapter->hw_write_wx(adapter,
1921 mem_crb+MIU_TEST_AGT_CTRL, &temp, 4);
1922
1923 for (j = 0; j < MAX_CTL_CHECK; j++) {
1924 adapter->hw_read_wx(adapter,
1925 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1926 if ((temp & MIU_TA_CTL_BUSY) == 0)
1927 break;
1928 }
1929
1930 if (j >= MAX_CTL_CHECK) {
1931 if (printk_ratelimit())
1932 dev_err(&adapter->pdev->dev,
1933 "failed to write through agent\n");
1934 ret = -1;
1935 break;
1936 }
1937 }
1938
1939 /*
1940 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1941 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1942 */
1943 return ret;
1944 }
1945
1946 int
1947 netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1948 u64 off, void *data, int size)
1949 {
1950 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1951 uint32_t temp;
1952 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1953
1954 /*
1955 * If not MN, go check for MS or invalid.
1956 */
1957
1958 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1959 mem_crb = NETXEN_CRB_QDR_NET;
1960 else {
1961 mem_crb = NETXEN_CRB_DDR_NET;
1962 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1963 return netxen_nic_pci_mem_read_direct(adapter,
1964 off, data, size);
1965 }
1966
1967 off8 = off & 0xfffffff8;
1968 off0[0] = off & 0x7;
1969 off0[1] = 0;
1970 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1971 sz[1] = size - sz[0];
1972 loop = ((off0[0] + size - 1) >> 3) + 1;
1973
1974 /*
1975 * don't lock here - write_wx gets the lock if each time
1976 * write_lock_irqsave(&adapter->adapter_lock, flags);
1977 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1978 */
1979
1980 for (i = 0; i < loop; i++) {
1981 temp = off8 + (i << 3);
1982 adapter->hw_write_wx(adapter,
1983 mem_crb + MIU_TEST_AGT_ADDR_LO, &temp, 4);
1984 temp = 0;
1985 adapter->hw_write_wx(adapter,
1986 mem_crb + MIU_TEST_AGT_ADDR_HI, &temp, 4);
1987 temp = MIU_TA_CTL_ENABLE;
1988 adapter->hw_write_wx(adapter,
1989 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1990 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1991 adapter->hw_write_wx(adapter,
1992 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1993
1994 for (j = 0; j < MAX_CTL_CHECK; j++) {
1995 adapter->hw_read_wx(adapter,
1996 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1997 if ((temp & MIU_TA_CTL_BUSY) == 0)
1998 break;
1999 }
2000
2001 if (j >= MAX_CTL_CHECK) {
2002 if (printk_ratelimit())
2003 dev_err(&adapter->pdev->dev,
2004 "failed to read through agent\n");
2005 break;
2006 }
2007
2008 start = off0[i] >> 2;
2009 end = (off0[i] + sz[i] - 1) >> 2;
2010 for (k = start; k <= end; k++) {
2011 adapter->hw_read_wx(adapter,
2012 mem_crb + MIU_TEST_AGT_RDDATA(k), &temp, 4);
2013 word[i] |= ((uint64_t)temp << (32 * k));
2014 }
2015 }
2016
2017 /*
2018 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
2019 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
2020 */
2021
2022 if (j >= MAX_CTL_CHECK)
2023 return -1;
2024
2025 if (sz[0] == 8) {
2026 val = word[0];
2027 } else {
2028 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
2029 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
2030 }
2031
2032 switch (size) {
2033 case 1:
2034 *(uint8_t *)data = val;
2035 break;
2036 case 2:
2037 *(uint16_t *)data = val;
2038 break;
2039 case 4:
2040 *(uint32_t *)data = val;
2041 break;
2042 case 8:
2043 *(uint64_t *)data = val;
2044 break;
2045 }
2046 return 0;
2047 }
2048
2049 /*
2050 * Note : only 32-bit writes!
2051 */
2052 int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
2053 u64 off, u32 data)
2054 {
2055 adapter->hw_write_wx(adapter, off, &data, 4);
2056
2057 return 0;
2058 }
2059
2060 u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off)
2061 {
2062 u32 temp;
2063 adapter->hw_read_wx(adapter, off, &temp, 4);
2064 return temp;
2065 }
2066
2067 void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
2068 u64 off, u32 data)
2069 {
2070 adapter->hw_write_wx(adapter, off, &data, 4);
2071 }
2072
2073 u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off)
2074 {
2075 u32 temp;
2076 adapter->hw_read_wx(adapter, off, &temp, 4);
2077 return temp;
2078 }
2079
2080 #if 0
2081 int
2082 netxen_nic_erase_pxe(struct netxen_adapter *adapter)
2083 {
2084 if (netxen_rom_fast_write(adapter, NETXEN_PXE_START, 0) == -1) {
2085 printk(KERN_ERR "%s: erase pxe failed\n",
2086 netxen_nic_driver_name);
2087 return -1;
2088 }
2089 return 0;
2090 }
2091 #endif /* 0 */
2092
2093 int netxen_nic_get_board_info(struct netxen_adapter *adapter)
2094 {
2095 int rv = 0;
2096 int addr = NETXEN_BRDCFG_START;
2097 struct netxen_board_info *boardinfo;
2098 int index;
2099 int *ptr32;
2100
2101 boardinfo = &adapter->ahw.boardcfg;
2102 ptr32 = (int *) boardinfo;
2103
2104 for (index = 0; index < sizeof(struct netxen_board_info) / sizeof(u32);
2105 index++) {
2106 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
2107 return -EIO;
2108 }
2109 ptr32++;
2110 addr += sizeof(u32);
2111 }
2112 if (boardinfo->magic != NETXEN_BDINFO_MAGIC) {
2113 printk("%s: ERROR reading %s board config."
2114 " Read %x, expected %x\n", netxen_nic_driver_name,
2115 netxen_nic_driver_name,
2116 boardinfo->magic, NETXEN_BDINFO_MAGIC);
2117 rv = -1;
2118 }
2119 if (boardinfo->header_version != NETXEN_BDINFO_VERSION) {
2120 printk("%s: Unknown board config version."
2121 " Read %x, expected %x\n", netxen_nic_driver_name,
2122 boardinfo->header_version, NETXEN_BDINFO_VERSION);
2123 rv = -1;
2124 }
2125
2126 if (boardinfo->board_type == NETXEN_BRDTYPE_P3_4_GB_MM) {
2127 u32 gpio = netxen_nic_reg_read(adapter,
2128 NETXEN_ROMUSB_GLB_PAD_GPIO_I);
2129 if ((gpio & 0x8000) == 0)
2130 boardinfo->board_type = NETXEN_BRDTYPE_P3_10G_TP;
2131 }
2132
2133 switch ((netxen_brdtype_t) boardinfo->board_type) {
2134 case NETXEN_BRDTYPE_P2_SB35_4G:
2135 adapter->ahw.board_type = NETXEN_NIC_GBE;
2136 break;
2137 case NETXEN_BRDTYPE_P2_SB31_10G:
2138 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
2139 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
2140 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
2141 case NETXEN_BRDTYPE_P3_HMEZ:
2142 case NETXEN_BRDTYPE_P3_XG_LOM:
2143 case NETXEN_BRDTYPE_P3_10G_CX4:
2144 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
2145 case NETXEN_BRDTYPE_P3_IMEZ:
2146 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
2147 case NETXEN_BRDTYPE_P3_10G_SFP_CT:
2148 case NETXEN_BRDTYPE_P3_10G_SFP_QT:
2149 case NETXEN_BRDTYPE_P3_10G_XFP:
2150 case NETXEN_BRDTYPE_P3_10000_BASE_T:
2151 adapter->ahw.board_type = NETXEN_NIC_XGBE;
2152 break;
2153 case NETXEN_BRDTYPE_P1_BD:
2154 case NETXEN_BRDTYPE_P1_SB:
2155 case NETXEN_BRDTYPE_P1_SMAX:
2156 case NETXEN_BRDTYPE_P1_SOCK:
2157 case NETXEN_BRDTYPE_P3_REF_QG:
2158 case NETXEN_BRDTYPE_P3_4_GB:
2159 case NETXEN_BRDTYPE_P3_4_GB_MM:
2160 adapter->ahw.board_type = NETXEN_NIC_GBE;
2161 break;
2162 case NETXEN_BRDTYPE_P3_10G_TP:
2163 adapter->ahw.board_type = (adapter->portnum < 2) ?
2164 NETXEN_NIC_XGBE : NETXEN_NIC_GBE;
2165 break;
2166 default:
2167 printk("%s: Unknown(%x)\n", netxen_nic_driver_name,
2168 boardinfo->board_type);
2169 rv = -ENODEV;
2170 break;
2171 }
2172
2173 return rv;
2174 }
2175
2176 /* NIU access sections */
2177
2178 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
2179 {
2180 new_mtu += MTU_FUDGE_FACTOR;
2181 netxen_nic_write_w0(adapter,
2182 NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
2183 new_mtu);
2184 return 0;
2185 }
2186
2187 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
2188 {
2189 new_mtu += MTU_FUDGE_FACTOR;
2190 if (adapter->physical_port == 0)
2191 netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE,
2192 new_mtu);
2193 else
2194 netxen_nic_write_w0(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE,
2195 new_mtu);
2196 return 0;
2197 }
2198
2199 void
2200 netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
2201 unsigned long off, int data)
2202 {
2203 adapter->hw_write_wx(adapter, off, &data, 4);
2204 }
2205
2206 void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
2207 {
2208 __u32 status;
2209 __u32 autoneg;
2210 __u32 port_mode;
2211
2212 if (!netif_carrier_ok(adapter->netdev)) {
2213 adapter->link_speed = 0;
2214 adapter->link_duplex = -1;
2215 adapter->link_autoneg = AUTONEG_ENABLE;
2216 return;
2217 }
2218
2219 if (adapter->ahw.board_type == NETXEN_NIC_GBE) {
2220 adapter->hw_read_wx(adapter,
2221 NETXEN_PORT_MODE_ADDR, &port_mode, 4);
2222 if (port_mode == NETXEN_PORT_MODE_802_3_AP) {
2223 adapter->link_speed = SPEED_1000;
2224 adapter->link_duplex = DUPLEX_FULL;
2225 adapter->link_autoneg = AUTONEG_DISABLE;
2226 return;
2227 }
2228
2229 if (adapter->phy_read
2230 && adapter->phy_read(adapter,
2231 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
2232 &status) == 0) {
2233 if (netxen_get_phy_link(status)) {
2234 switch (netxen_get_phy_speed(status)) {
2235 case 0:
2236 adapter->link_speed = SPEED_10;
2237 break;
2238 case 1:
2239 adapter->link_speed = SPEED_100;
2240 break;
2241 case 2:
2242 adapter->link_speed = SPEED_1000;
2243 break;
2244 default:
2245 adapter->link_speed = 0;
2246 break;
2247 }
2248 switch (netxen_get_phy_duplex(status)) {
2249 case 0:
2250 adapter->link_duplex = DUPLEX_HALF;
2251 break;
2252 case 1:
2253 adapter->link_duplex = DUPLEX_FULL;
2254 break;
2255 default:
2256 adapter->link_duplex = -1;
2257 break;
2258 }
2259 if (adapter->phy_read
2260 && adapter->phy_read(adapter,
2261 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
2262 &autoneg) != 0)
2263 adapter->link_autoneg = autoneg;
2264 } else
2265 goto link_down;
2266 } else {
2267 link_down:
2268 adapter->link_speed = 0;
2269 adapter->link_duplex = -1;
2270 }
2271 }
2272 }
2273
2274 void netxen_nic_flash_print(struct netxen_adapter *adapter)
2275 {
2276 u32 fw_major = 0;
2277 u32 fw_minor = 0;
2278 u32 fw_build = 0;
2279 char brd_name[NETXEN_MAX_SHORT_NAME];
2280 char serial_num[32];
2281 int i, addr;
2282 int *ptr32;
2283
2284 struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
2285
2286 adapter->driver_mismatch = 0;
2287
2288 ptr32 = (int *)&serial_num;
2289 addr = NETXEN_USER_START +
2290 offsetof(struct netxen_new_user_info, serial_num);
2291 for (i = 0; i < 8; i++) {
2292 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
2293 printk("%s: ERROR reading %s board userarea.\n",
2294 netxen_nic_driver_name,
2295 netxen_nic_driver_name);
2296 adapter->driver_mismatch = 1;
2297 return;
2298 }
2299 ptr32++;
2300 addr += sizeof(u32);
2301 }
2302
2303 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MAJOR, &fw_major, 4);
2304 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MINOR, &fw_minor, 4);
2305 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_SUB, &fw_build, 4);
2306
2307 adapter->fw_major = fw_major;
2308
2309 if (adapter->portnum == 0) {
2310 get_brd_name_by_type(board_info->board_type, brd_name);
2311
2312 printk(KERN_INFO "NetXen %s Board S/N %s Chip rev 0x%x\n",
2313 brd_name, serial_num, adapter->ahw.revision_id);
2314 printk(KERN_INFO "NetXen Firmware version %d.%d.%d\n",
2315 fw_major, fw_minor, fw_build);
2316 }
2317
2318 if (NETXEN_VERSION_CODE(fw_major, fw_minor, fw_build) <
2319 NETXEN_VERSION_CODE(3, 4, 216)) {
2320 adapter->driver_mismatch = 1;
2321 printk(KERN_ERR "%s: firmware version %d.%d.%d unsupported\n",
2322 netxen_nic_driver_name,
2323 fw_major, fw_minor, fw_build);
2324 return;
2325 }
2326 }
2327
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