2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
4 * PCI Bus Services, see include/linux/pci.h for further explanation.
6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
9 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/init.h>
15 #include <linux/pci.h>
17 #include <linux/module.h>
18 #include <linux/spinlock.h>
19 #include <linux/string.h>
20 #include <linux/log2.h>
21 #include <asm/dma.h> /* isa_dma_bridge_buggy */
24 unsigned int pci_pm_d3_delay
= 10;
26 #ifdef CONFIG_PCI_DOMAINS
27 int pci_domains_supported
= 1;
30 #define DEFAULT_CARDBUS_IO_SIZE (256)
31 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
32 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
33 unsigned long pci_cardbus_io_size
= DEFAULT_CARDBUS_IO_SIZE
;
34 unsigned long pci_cardbus_mem_size
= DEFAULT_CARDBUS_MEM_SIZE
;
37 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
38 * @bus: pointer to PCI bus structure to search
40 * Given a PCI bus, returns the highest PCI bus number present in the set
41 * including the given PCI bus and its list of child PCI buses.
43 unsigned char pci_bus_max_busnr(struct pci_bus
* bus
)
45 struct list_head
*tmp
;
48 max
= bus
->subordinate
;
49 list_for_each(tmp
, &bus
->children
) {
50 n
= pci_bus_max_busnr(pci_bus_b(tmp
));
56 EXPORT_SYMBOL_GPL(pci_bus_max_busnr
);
60 * pci_max_busnr - returns maximum PCI bus number
62 * Returns the highest PCI bus number present in the system global list of
65 unsigned char __devinit
68 struct pci_bus
*bus
= NULL
;
72 while ((bus
= pci_find_next_bus(bus
)) != NULL
) {
73 n
= pci_bus_max_busnr(bus
);
82 #define PCI_FIND_CAP_TTL 48
84 static int __pci_find_next_cap_ttl(struct pci_bus
*bus
, unsigned int devfn
,
85 u8 pos
, int cap
, int *ttl
)
90 pci_bus_read_config_byte(bus
, devfn
, pos
, &pos
);
94 pci_bus_read_config_byte(bus
, devfn
, pos
+ PCI_CAP_LIST_ID
,
100 pos
+= PCI_CAP_LIST_NEXT
;
105 static int __pci_find_next_cap(struct pci_bus
*bus
, unsigned int devfn
,
108 int ttl
= PCI_FIND_CAP_TTL
;
110 return __pci_find_next_cap_ttl(bus
, devfn
, pos
, cap
, &ttl
);
113 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
)
115 return __pci_find_next_cap(dev
->bus
, dev
->devfn
,
116 pos
+ PCI_CAP_LIST_NEXT
, cap
);
118 EXPORT_SYMBOL_GPL(pci_find_next_capability
);
120 static int __pci_bus_find_cap_start(struct pci_bus
*bus
,
121 unsigned int devfn
, u8 hdr_type
)
125 pci_bus_read_config_word(bus
, devfn
, PCI_STATUS
, &status
);
126 if (!(status
& PCI_STATUS_CAP_LIST
))
130 case PCI_HEADER_TYPE_NORMAL
:
131 case PCI_HEADER_TYPE_BRIDGE
:
132 return PCI_CAPABILITY_LIST
;
133 case PCI_HEADER_TYPE_CARDBUS
:
134 return PCI_CB_CAPABILITY_LIST
;
143 * pci_find_capability - query for devices' capabilities
144 * @dev: PCI device to query
145 * @cap: capability code
147 * Tell if a device supports a given PCI capability.
148 * Returns the address of the requested capability structure within the
149 * device's PCI configuration space or 0 in case the device does not
150 * support it. Possible values for @cap:
152 * %PCI_CAP_ID_PM Power Management
153 * %PCI_CAP_ID_AGP Accelerated Graphics Port
154 * %PCI_CAP_ID_VPD Vital Product Data
155 * %PCI_CAP_ID_SLOTID Slot Identification
156 * %PCI_CAP_ID_MSI Message Signalled Interrupts
157 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
158 * %PCI_CAP_ID_PCIX PCI-X
159 * %PCI_CAP_ID_EXP PCI Express
161 int pci_find_capability(struct pci_dev
*dev
, int cap
)
165 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
167 pos
= __pci_find_next_cap(dev
->bus
, dev
->devfn
, pos
, cap
);
173 * pci_bus_find_capability - query for devices' capabilities
174 * @bus: the PCI bus to query
175 * @devfn: PCI device to query
176 * @cap: capability code
178 * Like pci_find_capability() but works for pci devices that do not have a
179 * pci_dev structure set up yet.
181 * Returns the address of the requested capability structure within the
182 * device's PCI configuration space or 0 in case the device does not
185 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
)
190 pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
);
192 pos
= __pci_bus_find_cap_start(bus
, devfn
, hdr_type
& 0x7f);
194 pos
= __pci_find_next_cap(bus
, devfn
, pos
, cap
);
200 * pci_find_ext_capability - Find an extended capability
201 * @dev: PCI device to query
202 * @cap: capability code
204 * Returns the address of the requested extended capability structure
205 * within the device's PCI configuration space or 0 if the device does
206 * not support it. Possible values for @cap:
208 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
209 * %PCI_EXT_CAP_ID_VC Virtual Channel
210 * %PCI_EXT_CAP_ID_DSN Device Serial Number
211 * %PCI_EXT_CAP_ID_PWR Power Budgeting
213 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
216 int ttl
= 480; /* 3840 bytes, minimum 8 bytes per capability */
219 if (dev
->cfg_size
<= 256)
222 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
226 * If we have no capabilities, this is indicated by cap ID,
227 * cap version and next pointer all being 0.
233 if (PCI_EXT_CAP_ID(header
) == cap
)
236 pos
= PCI_EXT_CAP_NEXT(header
);
240 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
246 EXPORT_SYMBOL_GPL(pci_find_ext_capability
);
248 static int __pci_find_next_ht_cap(struct pci_dev
*dev
, int pos
, int ht_cap
)
250 int rc
, ttl
= PCI_FIND_CAP_TTL
;
253 if (ht_cap
== HT_CAPTYPE_SLAVE
|| ht_cap
== HT_CAPTYPE_HOST
)
254 mask
= HT_3BIT_CAP_MASK
;
256 mask
= HT_5BIT_CAP_MASK
;
258 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
, pos
,
259 PCI_CAP_ID_HT
, &ttl
);
261 rc
= pci_read_config_byte(dev
, pos
+ 3, &cap
);
262 if (rc
!= PCIBIOS_SUCCESSFUL
)
265 if ((cap
& mask
) == ht_cap
)
268 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
,
269 pos
+ PCI_CAP_LIST_NEXT
,
270 PCI_CAP_ID_HT
, &ttl
);
276 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
277 * @dev: PCI device to query
278 * @pos: Position from which to continue searching
279 * @ht_cap: Hypertransport capability code
281 * To be used in conjunction with pci_find_ht_capability() to search for
282 * all capabilities matching @ht_cap. @pos should always be a value returned
283 * from pci_find_ht_capability().
285 * NB. To be 100% safe against broken PCI devices, the caller should take
286 * steps to avoid an infinite loop.
288 int pci_find_next_ht_capability(struct pci_dev
*dev
, int pos
, int ht_cap
)
290 return __pci_find_next_ht_cap(dev
, pos
+ PCI_CAP_LIST_NEXT
, ht_cap
);
292 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability
);
295 * pci_find_ht_capability - query a device's Hypertransport capabilities
296 * @dev: PCI device to query
297 * @ht_cap: Hypertransport capability code
299 * Tell if a device supports a given Hypertransport capability.
300 * Returns an address within the device's PCI configuration space
301 * or 0 in case the device does not support the request capability.
302 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
303 * which has a Hypertransport capability matching @ht_cap.
305 int pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
)
309 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
311 pos
= __pci_find_next_ht_cap(dev
, pos
, ht_cap
);
315 EXPORT_SYMBOL_GPL(pci_find_ht_capability
);
318 * pci_find_parent_resource - return resource region of parent bus of given region
319 * @dev: PCI device structure contains resources to be searched
320 * @res: child resource record for which parent is sought
322 * For given resource region of given device, return the resource
323 * region of parent bus the given region is contained in or where
324 * it should be allocated from.
327 pci_find_parent_resource(const struct pci_dev
*dev
, struct resource
*res
)
329 const struct pci_bus
*bus
= dev
->bus
;
331 struct resource
*best
= NULL
;
333 for(i
= 0; i
< PCI_BUS_NUM_RESOURCES
; i
++) {
334 struct resource
*r
= bus
->resource
[i
];
337 if (res
->start
&& !(res
->start
>= r
->start
&& res
->end
<= r
->end
))
338 continue; /* Not contained */
339 if ((res
->flags
^ r
->flags
) & (IORESOURCE_IO
| IORESOURCE_MEM
))
340 continue; /* Wrong type */
341 if (!((res
->flags
^ r
->flags
) & IORESOURCE_PREFETCH
))
342 return r
; /* Exact match */
343 if ((res
->flags
& IORESOURCE_PREFETCH
) && !(r
->flags
& IORESOURCE_PREFETCH
))
344 best
= r
; /* Approximating prefetchable by non-prefetchable */
350 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
351 * @dev: PCI device to have its BARs restored
353 * Restore the BAR values for a given device, so as to make it
354 * accessible by its driver.
357 pci_restore_bars(struct pci_dev
*dev
)
361 switch (dev
->hdr_type
) {
362 case PCI_HEADER_TYPE_NORMAL
:
365 case PCI_HEADER_TYPE_BRIDGE
:
368 case PCI_HEADER_TYPE_CARDBUS
:
372 /* Should never get here, but just in case... */
376 for (i
= 0; i
< numres
; i
++)
377 pci_update_resource(dev
, &dev
->resource
[i
], i
);
380 int (*platform_pci_set_power_state
)(struct pci_dev
*dev
, pci_power_t t
);
383 * pci_set_power_state - Set the power state of a PCI device
384 * @dev: PCI device to be suspended
385 * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
387 * Transition a device to a new power state, using the Power Management
388 * Capabilities in the device's config space.
391 * -EINVAL if trying to enter a lower state than we're already in.
392 * 0 if we're already in the requested state.
393 * -EIO if device does not support PCI PM.
394 * 0 if we can successfully change the power state.
397 pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
399 int pm
, need_restore
= 0;
402 /* bound the state we're entering */
403 if (state
> PCI_D3hot
)
407 * If the device or the parent bridge can't support PCI PM, ignore
408 * the request if we're doing anything besides putting it into D0
409 * (which would only happen on boot).
411 if ((state
== PCI_D1
|| state
== PCI_D2
) && pci_no_d1d2(dev
))
414 /* find PCI PM capability in list */
415 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
417 /* abort if the device doesn't support PM capabilities */
421 /* Validate current state:
422 * Can enter D0 from any state, but if we can only go deeper
423 * to sleep if we're already in a low power state
425 if (state
!= PCI_D0
&& dev
->current_state
> state
) {
426 printk(KERN_ERR
"%s(): %s: state=%d, current state=%d\n",
427 __FUNCTION__
, pci_name(dev
), state
, dev
->current_state
);
429 } else if (dev
->current_state
== state
)
430 return 0; /* we're already there */
433 pci_read_config_word(dev
,pm
+ PCI_PM_PMC
,&pmc
);
434 if ((pmc
& PCI_PM_CAP_VER_MASK
) > 3) {
436 "PCI: %s has unsupported PM cap regs version (%u)\n",
437 pci_name(dev
), pmc
& PCI_PM_CAP_VER_MASK
);
441 /* check if this device supports the desired state */
442 if (state
== PCI_D1
&& !(pmc
& PCI_PM_CAP_D1
))
444 else if (state
== PCI_D2
&& !(pmc
& PCI_PM_CAP_D2
))
447 pci_read_config_word(dev
, pm
+ PCI_PM_CTRL
, &pmcsr
);
449 /* If we're (effectively) in D3, force entire word to 0.
450 * This doesn't affect PME_Status, disables PME_En, and
451 * sets PowerState to 0.
453 switch (dev
->current_state
) {
457 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
460 case PCI_UNKNOWN
: /* Boot-up */
461 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) == PCI_D3hot
462 && !(pmcsr
& PCI_PM_CTRL_NO_SOFT_RESET
))
464 /* Fall-through: force to D0 */
470 /* enter specified state */
471 pci_write_config_word(dev
, pm
+ PCI_PM_CTRL
, pmcsr
);
473 /* Mandatory power management transition delays */
474 /* see PCI PM 1.1 5.6.1 table 18 */
475 if (state
== PCI_D3hot
|| dev
->current_state
== PCI_D3hot
)
476 msleep(pci_pm_d3_delay
);
477 else if (state
== PCI_D2
|| dev
->current_state
== PCI_D2
)
481 * Give firmware a chance to be called, such as ACPI _PRx, _PSx
482 * Firmware method after native method ?
484 if (platform_pci_set_power_state
)
485 platform_pci_set_power_state(dev
, state
);
487 dev
->current_state
= state
;
489 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
490 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
491 * from D3hot to D0 _may_ perform an internal reset, thereby
492 * going to "D0 Uninitialized" rather than "D0 Initialized".
493 * For example, at least some versions of the 3c905B and the
494 * 3c556B exhibit this behaviour.
496 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
497 * devices in a D3hot state at boot. Consequently, we need to
498 * restore at least the BARs so that the device will be
499 * accessible to its driver.
502 pci_restore_bars(dev
);
507 pci_power_t (*platform_pci_choose_state
)(struct pci_dev
*dev
, pm_message_t state
);
510 * pci_choose_state - Choose the power state of a PCI device
511 * @dev: PCI device to be suspended
512 * @state: target sleep state for the whole system. This is the value
513 * that is passed to suspend() function.
515 * Returns PCI power state suitable for given device and given system
519 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
)
523 if (!pci_find_capability(dev
, PCI_CAP_ID_PM
))
526 if (platform_pci_choose_state
) {
527 ret
= platform_pci_choose_state(dev
, state
);
528 if (ret
!= PCI_POWER_ERROR
)
532 switch (state
.event
) {
535 case PM_EVENT_FREEZE
:
536 case PM_EVENT_PRETHAW
:
537 /* REVISIT both freeze and pre-thaw "should" use D0 */
538 case PM_EVENT_SUSPEND
:
541 printk("Unrecognized suspend event %d\n", state
.event
);
547 EXPORT_SYMBOL(pci_choose_state
);
549 static int pci_save_pcie_state(struct pci_dev
*dev
)
552 struct pci_cap_saved_state
*save_state
;
555 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
559 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
561 save_state
= kzalloc(sizeof(*save_state
) + sizeof(u16
) * 4, GFP_KERNEL
);
563 dev_err(&dev
->dev
, "Out of memory in pci_save_pcie_state\n");
566 cap
= (u16
*)&save_state
->data
[0];
568 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, &cap
[i
++]);
569 pci_read_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, &cap
[i
++]);
570 pci_read_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, &cap
[i
++]);
571 pci_read_config_word(dev
, pos
+ PCI_EXP_RTCTL
, &cap
[i
++]);
572 pci_add_saved_cap(dev
, save_state
);
576 static void pci_restore_pcie_state(struct pci_dev
*dev
)
579 struct pci_cap_saved_state
*save_state
;
582 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
583 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
584 if (!save_state
|| pos
<= 0)
586 cap
= (u16
*)&save_state
->data
[0];
588 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, cap
[i
++]);
589 pci_write_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, cap
[i
++]);
590 pci_write_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, cap
[i
++]);
591 pci_write_config_word(dev
, pos
+ PCI_EXP_RTCTL
, cap
[i
++]);
595 static int pci_save_pcix_state(struct pci_dev
*dev
)
598 struct pci_cap_saved_state
*save_state
;
601 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
605 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
607 save_state
= kzalloc(sizeof(*save_state
) + sizeof(u16
), GFP_KERNEL
);
609 dev_err(&dev
->dev
, "Out of memory in pci_save_pcie_state\n");
612 cap
= (u16
*)&save_state
->data
[0];
614 pci_read_config_word(dev
, pos
+ PCI_X_CMD
, &cap
[i
++]);
615 pci_add_saved_cap(dev
, save_state
);
619 static void pci_restore_pcix_state(struct pci_dev
*dev
)
622 struct pci_cap_saved_state
*save_state
;
625 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
626 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
627 if (!save_state
|| pos
<= 0)
629 cap
= (u16
*)&save_state
->data
[0];
631 pci_write_config_word(dev
, pos
+ PCI_X_CMD
, cap
[i
++]);
636 * pci_save_state - save the PCI configuration space of a device before suspending
637 * @dev: - PCI device that we're dealing with
640 pci_save_state(struct pci_dev
*dev
)
643 /* XXX: 100% dword access ok here? */
644 for (i
= 0; i
< 16; i
++)
645 pci_read_config_dword(dev
, i
* 4,&dev
->saved_config_space
[i
]);
646 if ((i
= pci_save_pcie_state(dev
)) != 0)
648 if ((i
= pci_save_pcix_state(dev
)) != 0)
654 * pci_restore_state - Restore the saved state of a PCI device
655 * @dev: - PCI device that we're dealing with
658 pci_restore_state(struct pci_dev
*dev
)
663 /* PCI Express register must be restored first */
664 pci_restore_pcie_state(dev
);
667 * The Base Address register should be programmed before the command
670 for (i
= 15; i
>= 0; i
--) {
671 pci_read_config_dword(dev
, i
* 4, &val
);
672 if (val
!= dev
->saved_config_space
[i
]) {
673 printk(KERN_DEBUG
"PM: Writing back config space on "
674 "device %s at offset %x (was %x, writing %x)\n",
676 val
, (int)dev
->saved_config_space
[i
]);
677 pci_write_config_dword(dev
,i
* 4,
678 dev
->saved_config_space
[i
]);
681 pci_restore_pcix_state(dev
);
682 pci_restore_msi_state(dev
);
687 static int do_pci_enable_device(struct pci_dev
*dev
, int bars
)
691 err
= pci_set_power_state(dev
, PCI_D0
);
692 if (err
< 0 && err
!= -EIO
)
694 err
= pcibios_enable_device(dev
, bars
);
697 pci_fixup_device(pci_fixup_enable
, dev
);
703 * pci_reenable_device - Resume abandoned device
704 * @dev: PCI device to be resumed
706 * Note this function is a backend of pci_default_resume and is not supposed
707 * to be called by normal code, write proper resume handler and use it instead.
709 int pci_reenable_device(struct pci_dev
*dev
)
711 if (atomic_read(&dev
->enable_cnt
))
712 return do_pci_enable_device(dev
, (1 << PCI_NUM_RESOURCES
) - 1);
717 * pci_enable_device_bars - Initialize some of a device for use
718 * @dev: PCI device to be initialized
719 * @bars: bitmask of BAR's that must be configured
721 * Initialize device before it's used by a driver. Ask low-level code
722 * to enable selected I/O and memory resources. Wake up the device if it
723 * was suspended. Beware, this function can fail.
726 pci_enable_device_bars(struct pci_dev
*dev
, int bars
)
730 if (atomic_add_return(1, &dev
->enable_cnt
) > 1)
731 return 0; /* already enabled */
733 err
= do_pci_enable_device(dev
, bars
);
735 atomic_dec(&dev
->enable_cnt
);
740 * pci_enable_device - Initialize device before it's used by a driver.
741 * @dev: PCI device to be initialized
743 * Initialize device before it's used by a driver. Ask low-level code
744 * to enable I/O and memory. Wake up the device if it was suspended.
745 * Beware, this function can fail.
747 * Note we don't actually enable the device many times if we call
748 * this function repeatedly (we just increment the count).
750 int pci_enable_device(struct pci_dev
*dev
)
752 return pci_enable_device_bars(dev
, (1 << PCI_NUM_RESOURCES
) - 1);
756 * Managed PCI resources. This manages device on/off, intx/msi/msix
757 * on/off and BAR regions. pci_dev itself records msi/msix status, so
758 * there's no need to track it separately. pci_devres is initialized
759 * when a device is enabled using managed PCI device enable interface.
762 unsigned int enabled
:1;
763 unsigned int pinned
:1;
764 unsigned int orig_intx
:1;
765 unsigned int restore_intx
:1;
769 static void pcim_release(struct device
*gendev
, void *res
)
771 struct pci_dev
*dev
= container_of(gendev
, struct pci_dev
, dev
);
772 struct pci_devres
*this = res
;
775 if (dev
->msi_enabled
)
776 pci_disable_msi(dev
);
777 if (dev
->msix_enabled
)
778 pci_disable_msix(dev
);
780 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
781 if (this->region_mask
& (1 << i
))
782 pci_release_region(dev
, i
);
784 if (this->restore_intx
)
785 pci_intx(dev
, this->orig_intx
);
787 if (this->enabled
&& !this->pinned
)
788 pci_disable_device(dev
);
791 static struct pci_devres
* get_pci_dr(struct pci_dev
*pdev
)
793 struct pci_devres
*dr
, *new_dr
;
795 dr
= devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
799 new_dr
= devres_alloc(pcim_release
, sizeof(*new_dr
), GFP_KERNEL
);
802 return devres_get(&pdev
->dev
, new_dr
, NULL
, NULL
);
805 static struct pci_devres
* find_pci_dr(struct pci_dev
*pdev
)
807 if (pci_is_managed(pdev
))
808 return devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
813 * pcim_enable_device - Managed pci_enable_device()
814 * @pdev: PCI device to be initialized
816 * Managed pci_enable_device().
818 int pcim_enable_device(struct pci_dev
*pdev
)
820 struct pci_devres
*dr
;
823 dr
= get_pci_dr(pdev
);
829 rc
= pci_enable_device(pdev
);
831 pdev
->is_managed
= 1;
838 * pcim_pin_device - Pin managed PCI device
839 * @pdev: PCI device to pin
841 * Pin managed PCI device @pdev. Pinned device won't be disabled on
842 * driver detach. @pdev must have been enabled with
843 * pcim_enable_device().
845 void pcim_pin_device(struct pci_dev
*pdev
)
847 struct pci_devres
*dr
;
849 dr
= find_pci_dr(pdev
);
850 WARN_ON(!dr
|| !dr
->enabled
);
856 * pcibios_disable_device - disable arch specific PCI resources for device dev
857 * @dev: the PCI device to disable
859 * Disables architecture specific PCI resources for the device. This
860 * is the default implementation. Architecture implementations can
863 void __attribute__ ((weak
)) pcibios_disable_device (struct pci_dev
*dev
) {}
866 * pci_disable_device - Disable PCI device after use
867 * @dev: PCI device to be disabled
869 * Signal to the system that the PCI device is not in use by the system
870 * anymore. This only involves disabling PCI bus-mastering, if active.
872 * Note we don't actually disable the device until all callers of
873 * pci_device_enable() have called pci_device_disable().
876 pci_disable_device(struct pci_dev
*dev
)
878 struct pci_devres
*dr
;
881 dr
= find_pci_dr(dev
);
885 if (atomic_sub_return(1, &dev
->enable_cnt
) != 0)
888 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
889 if (pci_command
& PCI_COMMAND_MASTER
) {
890 pci_command
&= ~PCI_COMMAND_MASTER
;
891 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
893 dev
->is_busmaster
= 0;
895 pcibios_disable_device(dev
);
899 * pcibios_set_pcie_reset_state - set reset state for device dev
900 * @dev: the PCI-E device reset
901 * @state: Reset state to enter into
904 * Sets the PCI-E reset state for the device. This is the default
905 * implementation. Architecture implementations can override this.
907 int __attribute__ ((weak
)) pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
908 enum pcie_reset_state state
)
914 * pci_set_pcie_reset_state - set reset state for device dev
915 * @dev: the PCI-E device reset
916 * @state: Reset state to enter into
919 * Sets the PCI reset state for the device.
921 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
)
923 return pcibios_set_pcie_reset_state(dev
, state
);
927 * pci_enable_wake - enable PCI device as wakeup event source
928 * @dev: PCI device affected
929 * @state: PCI state from which device will issue wakeup events
930 * @enable: True to enable event generation; false to disable
932 * This enables the device as a wakeup event source, or disables it.
933 * When such events involves platform-specific hooks, those hooks are
934 * called automatically by this routine.
936 * Devices with legacy power management (no standard PCI PM capabilities)
937 * always require such platform hooks. Depending on the platform, devices
938 * supporting the standard PCI PME# signal may require such platform hooks;
939 * they always update bits in config space to allow PME# generation.
941 * -EIO is returned if the device can't ever be a wakeup event source.
942 * -EINVAL is returned if the device can't generate wakeup events from
943 * the specified PCI state. Returns zero if the operation is successful.
945 int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
, int enable
)
951 /* Note that drivers should verify device_may_wakeup(&dev->dev)
952 * before calling this function. Platform code should report
953 * errors when drivers try to enable wakeup on devices that
954 * can't issue wakeups, or on which wakeups were disabled by
955 * userspace updating the /sys/devices.../power/wakeup file.
958 status
= call_platform_enable_wakeup(&dev
->dev
, enable
);
960 /* find PCI PM capability in list */
961 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
963 /* If device doesn't support PM Capabilities, but caller wants to
964 * disable wake events, it's a NOP. Otherwise fail unless the
965 * platform hooks handled this legacy device already.
968 return enable
? status
: 0;
970 /* Check device's ability to generate PME# */
971 pci_read_config_word(dev
,pm
+PCI_PM_PMC
,&value
);
973 value
&= PCI_PM_CAP_PME_MASK
;
974 value
>>= ffs(PCI_PM_CAP_PME_MASK
) - 1; /* First bit of mask */
976 /* Check if it can generate PME# from requested state. */
977 if (!value
|| !(value
& (1 << state
))) {
978 /* if it can't, revert what the platform hook changed,
979 * always reporting the base "EINVAL, can't PME#" error
982 call_platform_enable_wakeup(&dev
->dev
, 0);
983 return enable
? -EINVAL
: 0;
986 pci_read_config_word(dev
, pm
+ PCI_PM_CTRL
, &value
);
988 /* Clear PME_Status by writing 1 to it and enable PME# */
989 value
|= PCI_PM_CTRL_PME_STATUS
| PCI_PM_CTRL_PME_ENABLE
;
992 value
&= ~PCI_PM_CTRL_PME_ENABLE
;
994 pci_write_config_word(dev
, pm
+ PCI_PM_CTRL
, value
);
1000 pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
1008 while (dev
->bus
->self
) {
1009 pin
= (pin
+ PCI_SLOT(dev
->devfn
)) % 4;
1010 dev
= dev
->bus
->self
;
1017 * pci_release_region - Release a PCI bar
1018 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1019 * @bar: BAR to release
1021 * Releases the PCI I/O and memory resources previously reserved by a
1022 * successful call to pci_request_region. Call this function only
1023 * after all use of the PCI regions has ceased.
1025 void pci_release_region(struct pci_dev
*pdev
, int bar
)
1027 struct pci_devres
*dr
;
1029 if (pci_resource_len(pdev
, bar
) == 0)
1031 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
)
1032 release_region(pci_resource_start(pdev
, bar
),
1033 pci_resource_len(pdev
, bar
));
1034 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)
1035 release_mem_region(pci_resource_start(pdev
, bar
),
1036 pci_resource_len(pdev
, bar
));
1038 dr
= find_pci_dr(pdev
);
1040 dr
->region_mask
&= ~(1 << bar
);
1044 * pci_request_region - Reserved PCI I/O and memory resource
1045 * @pdev: PCI device whose resources are to be reserved
1046 * @bar: BAR to be reserved
1047 * @res_name: Name to be associated with resource.
1049 * Mark the PCI region associated with PCI device @pdev BR @bar as
1050 * being reserved by owner @res_name. Do not access any
1051 * address inside the PCI regions unless this call returns
1054 * Returns 0 on success, or %EBUSY on error. A warning
1055 * message is also printed on failure.
1057 int pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
)
1059 struct pci_devres
*dr
;
1061 if (pci_resource_len(pdev
, bar
) == 0)
1064 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
) {
1065 if (!request_region(pci_resource_start(pdev
, bar
),
1066 pci_resource_len(pdev
, bar
), res_name
))
1069 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
1070 if (!request_mem_region(pci_resource_start(pdev
, bar
),
1071 pci_resource_len(pdev
, bar
), res_name
))
1075 dr
= find_pci_dr(pdev
);
1077 dr
->region_mask
|= 1 << bar
;
1082 printk (KERN_WARNING
"PCI: Unable to reserve %s region #%d:%llx@%llx "
1084 pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
? "I/O" : "mem",
1085 bar
+ 1, /* PCI BAR # */
1086 (unsigned long long)pci_resource_len(pdev
, bar
),
1087 (unsigned long long)pci_resource_start(pdev
, bar
),
1093 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1094 * @pdev: PCI device whose resources were previously reserved
1095 * @bars: Bitmask of BARs to be released
1097 * Release selected PCI I/O and memory resources previously reserved.
1098 * Call this function only after all use of the PCI regions has ceased.
1100 void pci_release_selected_regions(struct pci_dev
*pdev
, int bars
)
1104 for (i
= 0; i
< 6; i
++)
1105 if (bars
& (1 << i
))
1106 pci_release_region(pdev
, i
);
1110 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
1111 * @pdev: PCI device whose resources are to be reserved
1112 * @bars: Bitmask of BARs to be requested
1113 * @res_name: Name to be associated with resource
1115 int pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
1116 const char *res_name
)
1120 for (i
= 0; i
< 6; i
++)
1121 if (bars
& (1 << i
))
1122 if(pci_request_region(pdev
, i
, res_name
))
1128 if (bars
& (1 << i
))
1129 pci_release_region(pdev
, i
);
1135 * pci_release_regions - Release reserved PCI I/O and memory resources
1136 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
1138 * Releases all PCI I/O and memory resources previously reserved by a
1139 * successful call to pci_request_regions. Call this function only
1140 * after all use of the PCI regions has ceased.
1143 void pci_release_regions(struct pci_dev
*pdev
)
1145 pci_release_selected_regions(pdev
, (1 << 6) - 1);
1149 * pci_request_regions - Reserved PCI I/O and memory resources
1150 * @pdev: PCI device whose resources are to be reserved
1151 * @res_name: Name to be associated with resource.
1153 * Mark all PCI regions associated with PCI device @pdev as
1154 * being reserved by owner @res_name. Do not access any
1155 * address inside the PCI regions unless this call returns
1158 * Returns 0 on success, or %EBUSY on error. A warning
1159 * message is also printed on failure.
1161 int pci_request_regions(struct pci_dev
*pdev
, const char *res_name
)
1163 return pci_request_selected_regions(pdev
, ((1 << 6) - 1), res_name
);
1167 * pci_set_master - enables bus-mastering for device dev
1168 * @dev: the PCI device to enable
1170 * Enables bus-mastering on the device and calls pcibios_set_master()
1171 * to do the needed arch specific settings.
1174 pci_set_master(struct pci_dev
*dev
)
1178 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1179 if (! (cmd
& PCI_COMMAND_MASTER
)) {
1180 pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev
));
1181 cmd
|= PCI_COMMAND_MASTER
;
1182 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1184 dev
->is_busmaster
= 1;
1185 pcibios_set_master(dev
);
1188 #ifdef PCI_DISABLE_MWI
1189 int pci_set_mwi(struct pci_dev
*dev
)
1194 int pci_try_set_mwi(struct pci_dev
*dev
)
1199 void pci_clear_mwi(struct pci_dev
*dev
)
1205 #ifndef PCI_CACHE_LINE_BYTES
1206 #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
1209 /* This can be overridden by arch code. */
1210 /* Don't forget this is measured in 32-bit words, not bytes */
1211 u8 pci_cache_line_size
= PCI_CACHE_LINE_BYTES
/ 4;
1214 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1215 * @dev: the PCI device for which MWI is to be enabled
1217 * Helper function for pci_set_mwi.
1218 * Originally copied from drivers/net/acenic.c.
1219 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
1221 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1224 pci_set_cacheline_size(struct pci_dev
*dev
)
1228 if (!pci_cache_line_size
)
1229 return -EINVAL
; /* The system doesn't support MWI. */
1231 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
1232 equal to or multiple of the right value. */
1233 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
1234 if (cacheline_size
>= pci_cache_line_size
&&
1235 (cacheline_size
% pci_cache_line_size
) == 0)
1238 /* Write the correct value. */
1239 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
1241 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
1242 if (cacheline_size
== pci_cache_line_size
)
1245 printk(KERN_DEBUG
"PCI: cache line size of %d is not supported "
1246 "by device %s\n", pci_cache_line_size
<< 2, pci_name(dev
));
1252 * pci_set_mwi - enables memory-write-invalidate PCI transaction
1253 * @dev: the PCI device for which MWI is enabled
1255 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1257 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1260 pci_set_mwi(struct pci_dev
*dev
)
1265 rc
= pci_set_cacheline_size(dev
);
1269 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1270 if (! (cmd
& PCI_COMMAND_INVALIDATE
)) {
1271 pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n",
1273 cmd
|= PCI_COMMAND_INVALIDATE
;
1274 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1281 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
1282 * @dev: the PCI device for which MWI is enabled
1284 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1285 * Callers are not required to check the return value.
1287 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1289 int pci_try_set_mwi(struct pci_dev
*dev
)
1291 int rc
= pci_set_mwi(dev
);
1296 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
1297 * @dev: the PCI device to disable
1299 * Disables PCI Memory-Write-Invalidate transaction on the device
1302 pci_clear_mwi(struct pci_dev
*dev
)
1306 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1307 if (cmd
& PCI_COMMAND_INVALIDATE
) {
1308 cmd
&= ~PCI_COMMAND_INVALIDATE
;
1309 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1312 #endif /* ! PCI_DISABLE_MWI */
1315 * pci_intx - enables/disables PCI INTx for device dev
1316 * @pdev: the PCI device to operate on
1317 * @enable: boolean: whether to enable or disable PCI INTx
1319 * Enables/disables PCI INTx for device dev
1322 pci_intx(struct pci_dev
*pdev
, int enable
)
1324 u16 pci_command
, new;
1326 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
1329 new = pci_command
& ~PCI_COMMAND_INTX_DISABLE
;
1331 new = pci_command
| PCI_COMMAND_INTX_DISABLE
;
1334 if (new != pci_command
) {
1335 struct pci_devres
*dr
;
1337 pci_write_config_word(pdev
, PCI_COMMAND
, new);
1339 dr
= find_pci_dr(pdev
);
1340 if (dr
&& !dr
->restore_intx
) {
1341 dr
->restore_intx
= 1;
1342 dr
->orig_intx
= !enable
;
1348 * pci_msi_off - disables any msi or msix capabilities
1349 * @dev: the PCI device to operate on
1351 * If you want to use msi see pci_enable_msi and friends.
1352 * This is a lower level primitive that allows us to disable
1353 * msi operation at the device level.
1355 void pci_msi_off(struct pci_dev
*dev
)
1360 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
1362 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &control
);
1363 control
&= ~PCI_MSI_FLAGS_ENABLE
;
1364 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, control
);
1366 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
1368 pci_read_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, &control
);
1369 control
&= ~PCI_MSIX_FLAGS_ENABLE
;
1370 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
1374 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
1376 * These can be overridden by arch-specific implementations
1379 pci_set_dma_mask(struct pci_dev
*dev
, u64 mask
)
1381 if (!pci_dma_supported(dev
, mask
))
1384 dev
->dma_mask
= mask
;
1390 pci_set_consistent_dma_mask(struct pci_dev
*dev
, u64 mask
)
1392 if (!pci_dma_supported(dev
, mask
))
1395 dev
->dev
.coherent_dma_mask
= mask
;
1402 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
1403 * @dev: PCI device to query
1405 * Returns mmrbc: maximum designed memory read count in bytes
1406 * or appropriate error value.
1408 int pcix_get_max_mmrbc(struct pci_dev
*dev
)
1413 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1417 err
= pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
);
1421 return (stat
& PCI_X_STATUS_MAX_READ
) >> 12;
1423 EXPORT_SYMBOL(pcix_get_max_mmrbc
);
1426 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
1427 * @dev: PCI device to query
1429 * Returns mmrbc: maximum memory read count in bytes
1430 * or appropriate error value.
1432 int pcix_get_mmrbc(struct pci_dev
*dev
)
1437 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1441 ret
= pci_read_config_dword(dev
, cap
+ PCI_X_CMD
, &cmd
);
1443 ret
= 512 << ((cmd
& PCI_X_CMD_MAX_READ
) >> 2);
1447 EXPORT_SYMBOL(pcix_get_mmrbc
);
1450 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
1451 * @dev: PCI device to query
1452 * @mmrbc: maximum memory read count in bytes
1453 * valid values are 512, 1024, 2048, 4096
1455 * If possible sets maximum memory read byte count, some bridges have erratas
1456 * that prevent this.
1458 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
)
1460 int cap
, err
= -EINVAL
;
1461 u32 stat
, cmd
, v
, o
;
1463 if (mmrbc
< 512 || mmrbc
> 4096 || !is_power_of_2(mmrbc
))
1466 v
= ffs(mmrbc
) - 10;
1468 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1472 err
= pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
);
1476 if (v
> (stat
& PCI_X_STATUS_MAX_READ
) >> 21)
1479 err
= pci_read_config_dword(dev
, cap
+ PCI_X_CMD
, &cmd
);
1483 o
= (cmd
& PCI_X_CMD_MAX_READ
) >> 2;
1485 if (v
> o
&& dev
->bus
&&
1486 (dev
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_MMRBC
))
1489 cmd
&= ~PCI_X_CMD_MAX_READ
;
1491 err
= pci_write_config_dword(dev
, cap
+ PCI_X_CMD
, cmd
);
1496 EXPORT_SYMBOL(pcix_set_mmrbc
);
1499 * pcie_get_readrq - get PCI Express read request size
1500 * @dev: PCI device to query
1502 * Returns maximum memory read request in bytes
1503 * or appropriate error value.
1505 int pcie_get_readrq(struct pci_dev
*dev
)
1510 cap
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
1514 ret
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
1516 ret
= 128 << ((ctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
1520 EXPORT_SYMBOL(pcie_get_readrq
);
1523 * pcie_set_readrq - set PCI Express maximum memory read request
1524 * @dev: PCI device to query
1525 * @rq: maximum memory read count in bytes
1526 * valid values are 128, 256, 512, 1024, 2048, 4096
1528 * If possible sets maximum read byte count
1530 int pcie_set_readrq(struct pci_dev
*dev
, int rq
)
1532 int cap
, err
= -EINVAL
;
1535 if (rq
< 128 || rq
> 4096 || !is_power_of_2(rq
))
1538 v
= (ffs(rq
) - 8) << 12;
1540 cap
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
1544 err
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
1548 if ((ctl
& PCI_EXP_DEVCTL_READRQ
) != v
) {
1549 ctl
&= ~PCI_EXP_DEVCTL_READRQ
;
1551 err
= pci_write_config_dword(dev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
1557 EXPORT_SYMBOL(pcie_set_readrq
);
1560 * pci_select_bars - Make BAR mask from the type of resource
1561 * @dev: the PCI device for which BAR mask is made
1562 * @flags: resource type mask to be selected
1564 * This helper routine makes bar mask from the type of resource.
1566 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
)
1569 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
1570 if (pci_resource_flags(dev
, i
) & flags
)
1575 static void __devinit
pci_no_domains(void)
1577 #ifdef CONFIG_PCI_DOMAINS
1578 pci_domains_supported
= 0;
1582 static int __devinit
pci_init(void)
1584 struct pci_dev
*dev
= NULL
;
1586 while ((dev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
1587 pci_fixup_device(pci_fixup_final
, dev
);
1592 static int __devinit
pci_setup(char *str
)
1595 char *k
= strchr(str
, ',');
1598 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
1599 if (!strcmp(str
, "nomsi")) {
1601 } else if (!strcmp(str
, "noaer")) {
1603 } else if (!strcmp(str
, "nodomains")) {
1605 } else if (!strncmp(str
, "cbiosize=", 9)) {
1606 pci_cardbus_io_size
= memparse(str
+ 9, &str
);
1607 } else if (!strncmp(str
, "cbmemsize=", 10)) {
1608 pci_cardbus_mem_size
= memparse(str
+ 10, &str
);
1610 printk(KERN_ERR
"PCI: Unknown option `%s'\n",
1618 early_param("pci", pci_setup
);
1620 device_initcall(pci_init
);
1622 EXPORT_SYMBOL_GPL(pci_restore_bars
);
1623 EXPORT_SYMBOL(pci_reenable_device
);
1624 EXPORT_SYMBOL(pci_enable_device_bars
);
1625 EXPORT_SYMBOL(pci_enable_device
);
1626 EXPORT_SYMBOL(pcim_enable_device
);
1627 EXPORT_SYMBOL(pcim_pin_device
);
1628 EXPORT_SYMBOL(pci_disable_device
);
1629 EXPORT_SYMBOL(pci_find_capability
);
1630 EXPORT_SYMBOL(pci_bus_find_capability
);
1631 EXPORT_SYMBOL(pci_release_regions
);
1632 EXPORT_SYMBOL(pci_request_regions
);
1633 EXPORT_SYMBOL(pci_release_region
);
1634 EXPORT_SYMBOL(pci_request_region
);
1635 EXPORT_SYMBOL(pci_release_selected_regions
);
1636 EXPORT_SYMBOL(pci_request_selected_regions
);
1637 EXPORT_SYMBOL(pci_set_master
);
1638 EXPORT_SYMBOL(pci_set_mwi
);
1639 EXPORT_SYMBOL(pci_try_set_mwi
);
1640 EXPORT_SYMBOL(pci_clear_mwi
);
1641 EXPORT_SYMBOL_GPL(pci_intx
);
1642 EXPORT_SYMBOL(pci_set_dma_mask
);
1643 EXPORT_SYMBOL(pci_set_consistent_dma_mask
);
1644 EXPORT_SYMBOL(pci_assign_resource
);
1645 EXPORT_SYMBOL(pci_find_parent_resource
);
1646 EXPORT_SYMBOL(pci_select_bars
);
1648 EXPORT_SYMBOL(pci_set_power_state
);
1649 EXPORT_SYMBOL(pci_save_state
);
1650 EXPORT_SYMBOL(pci_restore_state
);
1651 EXPORT_SYMBOL(pci_enable_wake
);
1652 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state
);