arch/arm/kernel/perf_event.c

   1 #undef DEBUG
   2
   3 /*
   4  * ARM performance counter support.
   5  *
   6  * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
   7  * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
   8  *
   9  * This code is based on the sparc64 perf event code, which is in turn based
  10  * on the x86 code. Callchain code is based on the ARM OProfile backtrace
  11  * code.
  12  */
  13 #define pr_fmt(fmt) "hw perfevents: " fmt
  14
  15 #include <linux/kernel.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/pm_runtime.h>
  18 #include <linux/uaccess.h>
  19
  20 #include <asm/irq_regs.h>
  21 #include <asm/pmu.h>
  22 #include <asm/stacktrace.h>
  23
  24 static int
  25 armpmu_map_cache_event(const unsigned (*cache_map)
  26                                       [PERF_COUNT_HW_CACHE_MAX]
  27                                       [PERF_COUNT_HW_CACHE_OP_MAX]
  28                                       [PERF_COUNT_HW_CACHE_RESULT_MAX],
  29                        u64 config)
  30 {
  31         unsigned int cache_type, cache_op, cache_result, ret;
  32
  33         cache_type = (config >>  0) & 0xff;
  34         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
  35                 return -EINVAL;
  36
  37         cache_op = (config >>  8) & 0xff;
  38         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
  39                 return -EINVAL;
  40
  41         cache_result = (config >> 16) & 0xff;
  42         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
  43                 return -EINVAL;
  44
  45         ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
  46
  47         if (ret == CACHE_OP_UNSUPPORTED)
  48                 return -ENOENT;
  49
  50         return ret;
  51 }
  52
  53 static int
  54 armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
  55 {
  56         int mapping;
  57
  58         if (config >= PERF_COUNT_HW_MAX)
  59                 return -ENOENT;
  60
  61         mapping = (*event_map)[config];
  62         return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
  63 }
  64
  65 static int
  66 armpmu_map_raw_event(u32 raw_event_mask, u64 config)
  67 {
  68         return (int)(config & raw_event_mask);
  69 }
  70
  71 int
  72 armpmu_map_event(struct perf_event *event,
  73                  const unsigned (*event_map)[PERF_COUNT_HW_MAX],
  74                  const unsigned (*cache_map)
  75                                 [PERF_COUNT_HW_CACHE_MAX]
  76                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  77                                 [PERF_COUNT_HW_CACHE_RESULT_MAX],
  78                  u32 raw_event_mask)
  79 {
  80         u64 config = event->attr.config;
  81
  82         switch (event->attr.type) {
  83         case PERF_TYPE_HARDWARE:
  84                 return armpmu_map_hw_event(event_map, config);
  85         case PERF_TYPE_HW_CACHE:
  86                 return armpmu_map_cache_event(cache_map, config);
  87         case PERF_TYPE_RAW:
  88                 return armpmu_map_raw_event(raw_event_mask, config);
  89         }
  90
  91         return -ENOENT;
  92 }
  93
  94 int armpmu_event_set_period(struct perf_event *event)
  95 {
  96         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
  97         struct hw_perf_event *hwc = &event->hw;
  98         s64 left = local64_read(&hwc->period_left);
  99         s64 period = hwc->sample_period;
 100         int ret = 0;
 101
 102         /* The period may have been changed by PERF_EVENT_IOC_PERIOD */
 103         if (unlikely(period != hwc->last_period))
 104                 left = period - (hwc->last_period - left);
 105
 106         if (unlikely(left <= -period)) {
 107                 left = period;
 108                 local64_set(&hwc->period_left, left);
 109                 hwc->last_period = period;
 110                 ret = 1;
 111         }
 112
 113         if (unlikely(left <= 0)) {
 114                 left += period;
 115                 local64_set(&hwc->period_left, left);
 116                 hwc->last_period = period;
 117                 ret = 1;
 118         }
 119
 120         if (left > (s64)armpmu->max_period)
 121                 left = armpmu->max_period;
 122
 123         local64_set(&hwc->prev_count, (u64)-left);
 124
 125         armpmu->write_counter(event, (u64)(-left) & 0xffffffff);
 126
 127         perf_event_update_userpage(event);
 128
 129         return ret;
 130 }
 131
 132 u64 armpmu_event_update(struct perf_event *event)
 133 {
 134         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 135         struct hw_perf_event *hwc = &event->hw;
 136         u64 delta, prev_raw_count, new_raw_count;
 137
 138 again:
 139         prev_raw_count = local64_read(&hwc->prev_count);
 140         new_raw_count = armpmu->read_counter(event);
 141
 142         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
 143                              new_raw_count) != prev_raw_count)
 144                 goto again;
 145
 146         delta = (new_raw_count - prev_raw_count) & armpmu->max_period;
 147
 148         local64_add(delta, &event->count);
 149         local64_sub(delta, &hwc->period_left);
 150
 151         return new_raw_count;
 152 }
 153
 154 static void
 155 armpmu_read(struct perf_event *event)
 156 {
 157         armpmu_event_update(event);
 158 }
 159
 160 static void
 161 armpmu_stop(struct perf_event *event, int flags)
 162 {
 163         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 164         struct hw_perf_event *hwc = &event->hw;
 165
 166         /*
 167          * ARM pmu always has to update the counter, so ignore
 168          * PERF_EF_UPDATE, see comments in armpmu_start().
 169          */
 170         if (!(hwc->state & PERF_HES_STOPPED)) {
 171                 armpmu->disable(event);
 172                 armpmu_event_update(event);
 173                 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
 174         }
 175 }
 176
 177 static void armpmu_start(struct perf_event *event, int flags)
 178 {
 179         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 180         struct hw_perf_event *hwc = &event->hw;
 181
 182         /*
 183          * ARM pmu always has to reprogram the period, so ignore
 184          * PERF_EF_RELOAD, see the comment below.
 185          */
 186         if (flags & PERF_EF_RELOAD)
 187                 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
 188
 189         hwc->state = 0;
 190         /*
 191          * Set the period again. Some counters can't be stopped, so when we
 192          * were stopped we simply disabled the IRQ source and the counter
 193          * may have been left counting. If we don't do this step then we may
 194          * get an interrupt too soon or *way* too late if the overflow has
 195          * happened since disabling.
 196          */
 197         armpmu_event_set_period(event);
 198         armpmu->enable(event);
 199 }
 200
 201 static void
 202 armpmu_del(struct perf_event *event, int flags)
 203 {
 204         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 205         struct pmu_hw_events *hw_events = armpmu->get_hw_events();
 206         struct hw_perf_event *hwc = &event->hw;
 207         int idx = hwc->idx;
 208
 209         armpmu_stop(event, PERF_EF_UPDATE);
 210         hw_events->events[idx] = NULL;
 211         clear_bit(idx, hw_events->used_mask);
 212
 213         perf_event_update_userpage(event);
 214 }
 215
 216 static int
 217 armpmu_add(struct perf_event *event, int flags)
 218 {
 219         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 220         struct pmu_hw_events *hw_events = armpmu->get_hw_events();
 221         struct hw_perf_event *hwc = &event->hw;
 222         int idx;
 223         int err = 0;
 224
 225         perf_pmu_disable(event->pmu);
 226
 227         /* If we don't have a space for the counter then finish early. */
 228         idx = armpmu->get_event_idx(hw_events, event);
 229         if (idx < 0) {
 230                 err = idx;
 231                 goto out;
 232         }
 233
 234         /*
 235          * If there is an event in the counter we are going to use then make
 236          * sure it is disabled.
 237          */
 238         event->hw.idx = idx;
 239         armpmu->disable(event);
 240         hw_events->events[idx] = event;
 241
 242         hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
 243         if (flags & PERF_EF_START)
 244                 armpmu_start(event, PERF_EF_RELOAD);
 245
 246         /* Propagate our changes to the userspace mapping. */
 247         perf_event_update_userpage(event);
 248
 249 out:
 250         perf_pmu_enable(event->pmu);
 251         return err;
 252 }
 253
 254 static int
 255 validate_event(struct pmu_hw_events *hw_events,
 256                struct perf_event *event)
 257 {
 258         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 259         struct pmu *leader_pmu = event->group_leader->pmu;
 260
 261         if (event->pmu != leader_pmu || event->state < PERF_EVENT_STATE_OFF)
 262                 return 1;
 263
 264         if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec)
 265                 return 1;
 266
 267         return armpmu->get_event_idx(hw_events, event) >= 0;
 268 }
 269
 270 static int
 271 validate_group(struct perf_event *event)
 272 {
 273         struct perf_event *sibling, *leader = event->group_leader;
 274         struct pmu_hw_events fake_pmu;
 275         DECLARE_BITMAP(fake_used_mask, ARMPMU_MAX_HWEVENTS);
 276
 277         /*
 278          * Initialise the fake PMU. We only need to populate the
 279          * used_mask for the purposes of validation.
 280          */
 281         memset(fake_used_mask, 0, sizeof(fake_used_mask));
 282         fake_pmu.used_mask = fake_used_mask;
 283
 284         if (!validate_event(&fake_pmu, leader))
 285                 return -EINVAL;
 286
 287         list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
 288                 if (!validate_event(&fake_pmu, sibling))
 289                         return -EINVAL;
 290         }
 291
 292         if (!validate_event(&fake_pmu, event))
 293                 return -EINVAL;
 294
 295         return 0;
 296 }
 297
 298 static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
 299 {
 300         struct arm_pmu *armpmu = (struct arm_pmu *) dev;
 301         struct platform_device *plat_device = armpmu->plat_device;
 302         struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev);
 303
 304         if (plat && plat->handle_irq)
 305                 return plat->handle_irq(irq, dev, armpmu->handle_irq);
 306         else
 307                 return armpmu->handle_irq(irq, dev);
 308 }
 309
 310 static void
 311 armpmu_release_hardware(struct arm_pmu *armpmu)
 312 {
 313         armpmu->free_irq(armpmu);
 314         pm_runtime_put_sync(&armpmu->plat_device->dev);
 315 }
 316
 317 static int
 318 armpmu_reserve_hardware(struct arm_pmu *armpmu)
 319 {
 320         int err;
 321         struct platform_device *pmu_device = armpmu->plat_device;
 322
 323         if (!pmu_device)
 324                 return -ENODEV;
 325
 326         pm_runtime_get_sync(&pmu_device->dev);
 327         err = armpmu->request_irq(armpmu, armpmu_dispatch_irq);
 328         if (err) {
 329                 armpmu_release_hardware(armpmu);
 330                 return err;
 331         }
 332
 333         return 0;
 334 }
 335
 336 static void
 337 hw_perf_event_destroy(struct perf_event *event)
 338 {
 339         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 340         atomic_t *active_events  = &armpmu->active_events;
 341         struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex;
 342
 343         if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) {
 344                 armpmu_release_hardware(armpmu);
 345                 mutex_unlock(pmu_reserve_mutex);
 346         }
 347 }
 348
 349 static int
 350 event_requires_mode_exclusion(struct perf_event_attr *attr)
 351 {
 352         return attr->exclude_idle || attr->exclude_user ||
 353                attr->exclude_kernel || attr->exclude_hv;
 354 }
 355
 356 static int
 357 __hw_perf_event_init(struct perf_event *event)
 358 {
 359         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 360         struct hw_perf_event *hwc = &event->hw;
 361         int mapping;
 362
 363         mapping = armpmu->map_event(event);
 364
 365         if (mapping < 0) {
 366                 pr_debug("event %x:%llx not supported\n", event->attr.type,
 367                          event->attr.config);
 368                 return mapping;
 369         }
 370
 371         /*
 372          * We don't assign an index until we actually place the event onto
 373          * hardware. Use -1 to signify that we haven't decided where to put it
 374          * yet. For SMP systems, each core has it's own PMU so we can't do any
 375          * clever allocation or constraints checking at this point.
 376          */
 377         hwc->idx                = -1;
 378         hwc->config_base        = 0;
 379         hwc->config             = 0;
 380         hwc->event_base         = 0;
 381
 382         /*
 383          * Check whether we need to exclude the counter from certain modes.
 384          */
 385         if ((!armpmu->set_event_filter ||
 386              armpmu->set_event_filter(hwc, &event->attr)) &&
 387              event_requires_mode_exclusion(&event->attr)) {
 388                 pr_debug("ARM performance counters do not support "
 389                          "mode exclusion\n");
 390                 return -EOPNOTSUPP;
 391         }
 392
 393         /*
 394          * Store the event encoding into the config_base field.
 395          */
 396         hwc->config_base            |= (unsigned long)mapping;
 397
 398         if (!hwc->sample_period) {
 399                 /*
 400                  * For non-sampling runs, limit the sample_period to half
 401                  * of the counter width. That way, the new counter value
 402                  * is far less likely to overtake the previous one unless
 403                  * you have some serious IRQ latency issues.
 404                  */
 405                 hwc->sample_period  = armpmu->max_period >> 1;
 406                 hwc->last_period    = hwc->sample_period;
 407                 local64_set(&hwc->period_left, hwc->sample_period);
 408         }
 409
 410         if (event->group_leader != event) {
 411                 if (validate_group(event) != 0)
 412                         return -EINVAL;
 413         }
 414
 415         return 0;
 416 }
 417
 418 static int armpmu_event_init(struct perf_event *event)
 419 {
 420         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 421         int err = 0;
 422         atomic_t *active_events = &armpmu->active_events;
 423
 424         /* does not support taken branch sampling */
 425         if (has_branch_stack(event))
 426                 return -EOPNOTSUPP;
 427
 428         if (armpmu->map_event(event) == -ENOENT)
 429                 return -ENOENT;
 430
 431         event->destroy = hw_perf_event_destroy;
 432
 433         if (!atomic_inc_not_zero(active_events)) {
 434                 mutex_lock(&armpmu->reserve_mutex);
 435                 if (atomic_read(active_events) == 0)
 436                         err = armpmu_reserve_hardware(armpmu);
 437
 438                 if (!err)
 439                         atomic_inc(active_events);
 440                 mutex_unlock(&armpmu->reserve_mutex);
 441         }
 442
 443         if (err)
 444                 return err;
 445
 446         err = __hw_perf_event_init(event);
 447         if (err)
 448                 hw_perf_event_destroy(event);
 449
 450         return err;
 451 }
 452
 453 static void armpmu_enable(struct pmu *pmu)
 454 {
 455         struct arm_pmu *armpmu = to_arm_pmu(pmu);
 456         struct pmu_hw_events *hw_events = armpmu->get_hw_events();
 457         int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
 458
 459         if (enabled)
 460                 armpmu->start(armpmu);
 461 }
 462
 463 static void armpmu_disable(struct pmu *pmu)
 464 {
 465         struct arm_pmu *armpmu = to_arm_pmu(pmu);
 466         armpmu->stop(armpmu);
 467 }
 468
 469 #ifdef CONFIG_PM_RUNTIME
 470 static int armpmu_runtime_resume(struct device *dev)
 471 {
 472         struct arm_pmu_platdata *plat = dev_get_platdata(dev);
 473
 474         if (plat && plat->runtime_resume)
 475                 return plat->runtime_resume(dev);
 476
 477         return 0;
 478 }
 479
 480 static int armpmu_runtime_suspend(struct device *dev)
 481 {
 482         struct arm_pmu_platdata *plat = dev_get_platdata(dev);
 483
 484         if (plat && plat->runtime_suspend)
 485                 return plat->runtime_suspend(dev);
 486
 487         return 0;
 488 }
 489 #endif
 490
 491 const struct dev_pm_ops armpmu_dev_pm_ops = {
 492         SET_RUNTIME_PM_OPS(armpmu_runtime_suspend, armpmu_runtime_resume, NULL)
 493 };
 494
 495 static void armpmu_init(struct arm_pmu *armpmu)
 496 {
 497         atomic_set(&armpmu->active_events, 0);
 498         mutex_init(&armpmu->reserve_mutex);
 499
 500         armpmu->pmu = (struct pmu) {
 501                 .pmu_enable     = armpmu_enable,
 502                 .pmu_disable    = armpmu_disable,
 503                 .event_init     = armpmu_event_init,
 504                 .add            = armpmu_add,
 505                 .del            = armpmu_del,
 506                 .start          = armpmu_start,
 507                 .stop           = armpmu_stop,
 508                 .read           = armpmu_read,
 509         };
 510 }
 511
 512 int armpmu_register(struct arm_pmu *armpmu, int type)
 513 {
 514         armpmu_init(armpmu);
 515         pm_runtime_enable(&armpmu->plat_device->dev);
 516         pr_info("enabled with %s PMU driver, %d counters available\n",
 517                         armpmu->name, armpmu->num_events);
 518         return perf_pmu_register(&armpmu->pmu, armpmu->name, type);
 519 }
 520
 521 /*
 522  * Callchain handling code.
 523  */
 524
 525 /*
 526  * The registers we're interested in are at the end of the variable
 527  * length saved register structure. The fp points at the end of this
 528  * structure so the address of this struct is:
 529  * (struct frame_tail *)(xxx->fp)-1
 530  *
 531  * This code has been adapted from the ARM OProfile support.
 532  */
 533 struct frame_tail {
 534         struct frame_tail __user *fp;
 535         unsigned long sp;
 536         unsigned long lr;
 537 } __attribute__((packed));
 538
 539 /*
 540  * Get the return address for a single stackframe and return a pointer to the
 541  * next frame tail.
 542  */
 543 static struct frame_tail __user *
 544 user_backtrace(struct frame_tail __user *tail,
 545                struct perf_callchain_entry *entry)
 546 {
 547         struct frame_tail buftail;
 548
 549         /* Also check accessibility of one struct frame_tail beyond */
 550         if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
 551                 return NULL;
 552         if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail)))
 553                 return NULL;
 554
 555         perf_callchain_store(entry, buftail.lr);
 556
 557         /*
 558          * Frame pointers should strictly progress back up the stack
 559          * (towards higher addresses).
 560          */
 561         if (tail + 1 >= buftail.fp)
 562                 return NULL;
 563
 564         return buftail.fp - 1;
 565 }
 566
 567 void
 568 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
 569 {
 570         struct frame_tail __user *tail;
 571
 572         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
 573                 /* We don't support guest os callchain now */
 574                 return;
 575         }
 576
 577         perf_callchain_store(entry, regs->ARM_pc);
 578         tail = (struct frame_tail __user *)regs->ARM_fp - 1;
 579
 580         while ((entry->nr < PERF_MAX_STACK_DEPTH) &&
 581                tail && !((unsigned long)tail & 0x3))
 582                 tail = user_backtrace(tail, entry);
 583 }
 584
 585 /*
 586  * Gets called by walk_stackframe() for every stackframe. This will be called
 587  * whist unwinding the stackframe and is like a subroutine return so we use
 588  * the PC.
 589  */
 590 static int
 591 callchain_trace(struct stackframe *fr,
 592                 void *data)
 593 {
 594         struct perf_callchain_entry *entry = data;
 595         perf_callchain_store(entry, fr->pc);
 596         return 0;
 597 }
 598
 599 void
 600 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
 601 {
 602         struct stackframe fr;
 603
 604         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
 605                 /* We don't support guest os callchain now */
 606                 return;
 607         }
 608
 609         fr.fp = regs->ARM_fp;
 610         fr.sp = regs->ARM_sp;
 611         fr.lr = regs->ARM_lr;
 612         fr.pc = regs->ARM_pc;
 613         walk_stackframe(&fr, callchain_trace, entry);
 614 }
 615
 616 unsigned long perf_instruction_pointer(struct pt_regs *regs)
 617 {
 618         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
 619                 return perf_guest_cbs->get_guest_ip();
 620
 621         return instruction_pointer(regs);
 622 }
 623
 624 unsigned long perf_misc_flags(struct pt_regs *regs)
 625 {
 626         int misc = 0;
 627
 628         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
 629                 if (perf_guest_cbs->is_user_mode())
 630                         misc |= PERF_RECORD_MISC_GUEST_USER;
 631                 else
 632                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
 633         } else {
 634                 if (user_mode(regs))
 635                         misc |= PERF_RECORD_MISC_USER;
 636                 else
 637                         misc |= PERF_RECORD_MISC_KERNEL;
 638         }
 639
 640         return misc;
 641 }