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scsi: Do not set cmd_per_lun to 1 in the host template
[linux-2.6/btrfs-unstable.git] / drivers / scsi / advansys.c
blob14d3aa54daa5c389a4a40946a63d161a8c3ca7dd
1 /*
2 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
3 *
4 * Copyright (c) 1995-2000 Advanced System Products, Inc.
5 * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
6 * Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx>
7 * Copyright (c) 2014 Hannes Reinecke <hare@suse.de>
8 * All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16 /*
17 * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
18 * changed its name to ConnectCom Solutions, Inc.
19 * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets
20 */
21
22 #include <linux/module.h>
23 #include <linux/string.h>
24 #include <linux/kernel.h>
25 #include <linux/types.h>
26 #include <linux/ioport.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/slab.h>
30 #include <linux/mm.h>
31 #include <linux/proc_fs.h>
32 #include <linux/init.h>
33 #include <linux/blkdev.h>
34 #include <linux/isa.h>
35 #include <linux/eisa.h>
36 #include <linux/pci.h>
37 #include <linux/spinlock.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/firmware.h>
40
41 #include <asm/io.h>
42 #include <asm/dma.h>
43
44 #include <scsi/scsi_cmnd.h>
45 #include <scsi/scsi_device.h>
46 #include <scsi/scsi_tcq.h>
47 #include <scsi/scsi.h>
48 #include <scsi/scsi_host.h>
49
50 #define DRV_NAME "advansys"
51 #define ASC_VERSION "3.5" /* AdvanSys Driver Version */
52
53 /* FIXME:
54 *
55 * 1. Use scsi_transport_spi
56 * 2. advansys_info is not safe against multiple simultaneous callers
57 * 3. Add module_param to override ISA/VLB ioport array
58 */
59
60 /* Enable driver /proc statistics. */
61 #define ADVANSYS_STATS
62
63 /* Enable driver tracing. */
64 #undef ADVANSYS_DEBUG
65
66 typedef unsigned char uchar;
67
68 #define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0)
69
70 #define PCI_VENDOR_ID_ASP 0x10cd
71 #define PCI_DEVICE_ID_ASP_1200A 0x1100
72 #define PCI_DEVICE_ID_ASP_ABP940 0x1200
73 #define PCI_DEVICE_ID_ASP_ABP940U 0x1300
74 #define PCI_DEVICE_ID_ASP_ABP940UW 0x2300
75 #define PCI_DEVICE_ID_38C0800_REV1 0x2500
76 #define PCI_DEVICE_ID_38C1600_REV1 0x2700
77
78 #define PortAddr unsigned int /* port address size */
79 #define inp(port) inb(port)
80 #define outp(port, byte) outb((byte), (port))
81
82 #define inpw(port) inw(port)
83 #define outpw(port, word) outw((word), (port))
84
85 #define ASC_MAX_SG_QUEUE 7
86 #define ASC_MAX_SG_LIST 255
87
88 #define ASC_CS_TYPE unsigned short
89
90 #define ASC_IS_ISA (0x0001)
91 #define ASC_IS_ISAPNP (0x0081)
92 #define ASC_IS_EISA (0x0002)
93 #define ASC_IS_PCI (0x0004)
94 #define ASC_IS_PCI_ULTRA (0x0104)
95 #define ASC_IS_PCMCIA (0x0008)
96 #define ASC_IS_MCA (0x0020)
97 #define ASC_IS_VL (0x0040)
98 #define ASC_IS_WIDESCSI_16 (0x0100)
99 #define ASC_IS_WIDESCSI_32 (0x0200)
100 #define ASC_IS_BIG_ENDIAN (0x8000)
101
102 #define ASC_CHIP_MIN_VER_VL (0x01)
103 #define ASC_CHIP_MAX_VER_VL (0x07)
104 #define ASC_CHIP_MIN_VER_PCI (0x09)
105 #define ASC_CHIP_MAX_VER_PCI (0x0F)
106 #define ASC_CHIP_VER_PCI_BIT (0x08)
107 #define ASC_CHIP_MIN_VER_ISA (0x11)
108 #define ASC_CHIP_MIN_VER_ISA_PNP (0x21)
109 #define ASC_CHIP_MAX_VER_ISA (0x27)
110 #define ASC_CHIP_VER_ISA_BIT (0x30)
111 #define ASC_CHIP_VER_ISAPNP_BIT (0x20)
112 #define ASC_CHIP_VER_ASYN_BUG (0x21)
113 #define ASC_CHIP_VER_PCI 0x08
114 #define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02)
115 #define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03)
116 #define ASC_CHIP_MIN_VER_EISA (0x41)
117 #define ASC_CHIP_MAX_VER_EISA (0x47)
118 #define ASC_CHIP_VER_EISA_BIT (0x40)
119 #define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
120 #define ASC_MAX_VL_DMA_COUNT (0x07FFFFFFL)
121 #define ASC_MAX_PCI_DMA_COUNT (0xFFFFFFFFL)
122 #define ASC_MAX_ISA_DMA_COUNT (0x00FFFFFFL)
123
124 #define ASC_SCSI_ID_BITS 3
125 #define ASC_SCSI_TIX_TYPE uchar
126 #define ASC_ALL_DEVICE_BIT_SET 0xFF
127 #define ASC_SCSI_BIT_ID_TYPE uchar
128 #define ASC_MAX_TID 7
129 #define ASC_MAX_LUN 7
130 #define ASC_SCSI_WIDTH_BIT_SET 0xFF
131 #define ASC_MAX_SENSE_LEN 32
132 #define ASC_MIN_SENSE_LEN 14
133 #define ASC_SCSI_RESET_HOLD_TIME_US 60
134
135 /*
136 * Narrow boards only support 12-byte commands, while wide boards
137 * extend to 16-byte commands.
138 */
139 #define ASC_MAX_CDB_LEN 12
140 #define ADV_MAX_CDB_LEN 16
141
142 #define MS_SDTR_LEN 0x03
143 #define MS_WDTR_LEN 0x02
144
145 #define ASC_SG_LIST_PER_Q 7
146 #define QS_FREE 0x00
147 #define QS_READY 0x01
148 #define QS_DISC1 0x02
149 #define QS_DISC2 0x04
150 #define QS_BUSY 0x08
151 #define QS_ABORTED 0x40
152 #define QS_DONE 0x80
153 #define QC_NO_CALLBACK 0x01
154 #define QC_SG_SWAP_QUEUE 0x02
155 #define QC_SG_HEAD 0x04
156 #define QC_DATA_IN 0x08
157 #define QC_DATA_OUT 0x10
158 #define QC_URGENT 0x20
159 #define QC_MSG_OUT 0x40
160 #define QC_REQ_SENSE 0x80
161 #define QCSG_SG_XFER_LIST 0x02
162 #define QCSG_SG_XFER_MORE 0x04
163 #define QCSG_SG_XFER_END 0x08
164 #define QD_IN_PROGRESS 0x00
165 #define QD_NO_ERROR 0x01
166 #define QD_ABORTED_BY_HOST 0x02
167 #define QD_WITH_ERROR 0x04
168 #define QD_INVALID_REQUEST 0x80
169 #define QD_INVALID_HOST_NUM 0x81
170 #define QD_INVALID_DEVICE 0x82
171 #define QD_ERR_INTERNAL 0xFF
172 #define QHSTA_NO_ERROR 0x00
173 #define QHSTA_M_SEL_TIMEOUT 0x11
174 #define QHSTA_M_DATA_OVER_RUN 0x12
175 #define QHSTA_M_DATA_UNDER_RUN 0x12
176 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
177 #define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14
178 #define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
179 #define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22
180 #define QHSTA_D_HOST_ABORT_FAILED 0x23
181 #define QHSTA_D_EXE_SCSI_Q_FAILED 0x24
182 #define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
183 #define QHSTA_D_ASPI_NO_BUF_POOL 0x26
184 #define QHSTA_M_WTM_TIMEOUT 0x41
185 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
186 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
187 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
188 #define QHSTA_M_TARGET_STATUS_BUSY 0x45
189 #define QHSTA_M_BAD_TAG_CODE 0x46
190 #define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47
191 #define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
192 #define QHSTA_D_LRAM_CMP_ERROR 0x81
193 #define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
194 #define ASC_FLAG_SCSIQ_REQ 0x01
195 #define ASC_FLAG_BIOS_SCSIQ_REQ 0x02
196 #define ASC_FLAG_BIOS_ASYNC_IO 0x04
197 #define ASC_FLAG_SRB_LINEAR_ADDR 0x08
198 #define ASC_FLAG_WIN16 0x10
199 #define ASC_FLAG_WIN32 0x20
200 #define ASC_FLAG_ISA_OVER_16MB 0x40
201 #define ASC_FLAG_DOS_VM_CALLBACK 0x80
202 #define ASC_TAG_FLAG_EXTRA_BYTES 0x10
203 #define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04
204 #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08
205 #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
206 #define ASC_SCSIQ_CPY_BEG 4
207 #define ASC_SCSIQ_SGHD_CPY_BEG 2
208 #define ASC_SCSIQ_B_FWD 0
209 #define ASC_SCSIQ_B_BWD 1
210 #define ASC_SCSIQ_B_STATUS 2
211 #define ASC_SCSIQ_B_QNO 3
212 #define ASC_SCSIQ_B_CNTL 4
213 #define ASC_SCSIQ_B_SG_QUEUE_CNT 5
214 #define ASC_SCSIQ_D_DATA_ADDR 8
215 #define ASC_SCSIQ_D_DATA_CNT 12
216 #define ASC_SCSIQ_B_SENSE_LEN 20
217 #define ASC_SCSIQ_DONE_INFO_BEG 22
218 #define ASC_SCSIQ_D_SRBPTR 22
219 #define ASC_SCSIQ_B_TARGET_IX 26
220 #define ASC_SCSIQ_B_CDB_LEN 28
221 #define ASC_SCSIQ_B_TAG_CODE 29
222 #define ASC_SCSIQ_W_VM_ID 30
223 #define ASC_SCSIQ_DONE_STATUS 32
224 #define ASC_SCSIQ_HOST_STATUS 33
225 #define ASC_SCSIQ_SCSI_STATUS 34
226 #define ASC_SCSIQ_CDB_BEG 36
227 #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
228 #define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60
229 #define ASC_SCSIQ_B_FIRST_SG_WK_QP 48
230 #define ASC_SCSIQ_B_SG_WK_QP 49
231 #define ASC_SCSIQ_B_SG_WK_IX 50
232 #define ASC_SCSIQ_W_ALT_DC1 52
233 #define ASC_SCSIQ_B_LIST_CNT 6
234 #define ASC_SCSIQ_B_CUR_LIST_CNT 7
235 #define ASC_SGQ_B_SG_CNTL 4
236 #define ASC_SGQ_B_SG_HEAD_QP 5
237 #define ASC_SGQ_B_SG_LIST_CNT 6
238 #define ASC_SGQ_B_SG_CUR_LIST_CNT 7
239 #define ASC_SGQ_LIST_BEG 8
240 #define ASC_DEF_SCSI1_QNG 4
241 #define ASC_MAX_SCSI1_QNG 4
242 #define ASC_DEF_SCSI2_QNG 16
243 #define ASC_MAX_SCSI2_QNG 32
244 #define ASC_TAG_CODE_MASK 0x23
245 #define ASC_STOP_REQ_RISC_STOP 0x01
246 #define ASC_STOP_ACK_RISC_STOP 0x03
247 #define ASC_STOP_CLEAN_UP_BUSY_Q 0x10
248 #define ASC_STOP_CLEAN_UP_DISC_Q 0x20
249 #define ASC_STOP_HOST_REQ_RISC_HALT 0x40
250 #define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
251 #define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
252 #define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID))
253 #define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID)
254 #define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID)
255 #define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
256 #define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6))
257
258 typedef struct asc_scsiq_1 {
259 uchar status;
260 uchar q_no;
261 uchar cntl;
262 uchar sg_queue_cnt;
263 uchar target_id;
264 uchar target_lun;
265 __le32 data_addr;
266 __le32 data_cnt;
267 __le32 sense_addr;
268 uchar sense_len;
269 uchar extra_bytes;
270 } ASC_SCSIQ_1;
271
272 typedef struct asc_scsiq_2 {
273 u32 srb_tag;
274 uchar target_ix;
275 uchar flag;
276 uchar cdb_len;
277 uchar tag_code;
278 ushort vm_id;
279 } ASC_SCSIQ_2;
280
281 typedef struct asc_scsiq_3 {
282 uchar done_stat;
283 uchar host_stat;
284 uchar scsi_stat;
285 uchar scsi_msg;
286 } ASC_SCSIQ_3;
287
288 typedef struct asc_scsiq_4 {
289 uchar cdb[ASC_MAX_CDB_LEN];
290 uchar y_first_sg_list_qp;
291 uchar y_working_sg_qp;
292 uchar y_working_sg_ix;
293 uchar y_res;
294 ushort x_req_count;
295 ushort x_reconnect_rtn;
296 __le32 x_saved_data_addr;
297 __le32 x_saved_data_cnt;
298 } ASC_SCSIQ_4;
299
300 typedef struct asc_q_done_info {
301 ASC_SCSIQ_2 d2;
302 ASC_SCSIQ_3 d3;
303 uchar q_status;
304 uchar q_no;
305 uchar cntl;
306 uchar sense_len;
307 uchar extra_bytes;
308 uchar res;
309 u32 remain_bytes;
310 } ASC_QDONE_INFO;
311
312 typedef struct asc_sg_list {
313 __le32 addr;
314 __le32 bytes;
315 } ASC_SG_LIST;
316
317 typedef struct asc_sg_head {
318 ushort entry_cnt;
319 ushort queue_cnt;
320 ushort entry_to_copy;
321 ushort res;
322 ASC_SG_LIST sg_list[0];
323 } ASC_SG_HEAD;
324
325 typedef struct asc_scsi_q {
326 ASC_SCSIQ_1 q1;
327 ASC_SCSIQ_2 q2;
328 uchar *cdbptr;
329 ASC_SG_HEAD *sg_head;
330 ushort remain_sg_entry_cnt;
331 ushort next_sg_index;
332 } ASC_SCSI_Q;
333
334 typedef struct asc_scsi_bios_req_q {
335 ASC_SCSIQ_1 r1;
336 ASC_SCSIQ_2 r2;
337 uchar *cdbptr;
338 ASC_SG_HEAD *sg_head;
339 uchar *sense_ptr;
340 ASC_SCSIQ_3 r3;
341 uchar cdb[ASC_MAX_CDB_LEN];
342 uchar sense[ASC_MIN_SENSE_LEN];
343 } ASC_SCSI_BIOS_REQ_Q;
344
345 typedef struct asc_risc_q {
346 uchar fwd;
347 uchar bwd;
348 ASC_SCSIQ_1 i1;
349 ASC_SCSIQ_2 i2;
350 ASC_SCSIQ_3 i3;
351 ASC_SCSIQ_4 i4;
352 } ASC_RISC_Q;
353
354 typedef struct asc_sg_list_q {
355 uchar seq_no;
356 uchar q_no;
357 uchar cntl;
358 uchar sg_head_qp;
359 uchar sg_list_cnt;
360 uchar sg_cur_list_cnt;
361 } ASC_SG_LIST_Q;
362
363 typedef struct asc_risc_sg_list_q {
364 uchar fwd;
365 uchar bwd;
366 ASC_SG_LIST_Q sg;
367 ASC_SG_LIST sg_list[7];
368 } ASC_RISC_SG_LIST_Q;
369
370 #define ASCQ_ERR_Q_STATUS 0x0D
371 #define ASCQ_ERR_CUR_QNG 0x17
372 #define ASCQ_ERR_SG_Q_LINKS 0x18
373 #define ASCQ_ERR_ISR_RE_ENTRY 0x1A
374 #define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B
375 #define ASCQ_ERR_ISR_ON_CRITICAL 0x1C
376
377 /*
378 * Warning code values are set in ASC_DVC_VAR 'warn_code'.
379 */
380 #define ASC_WARN_NO_ERROR 0x0000
381 #define ASC_WARN_IO_PORT_ROTATE 0x0001
382 #define ASC_WARN_EEPROM_CHKSUM 0x0002
383 #define ASC_WARN_IRQ_MODIFIED 0x0004
384 #define ASC_WARN_AUTO_CONFIG 0x0008
385 #define ASC_WARN_CMD_QNG_CONFLICT 0x0010
386 #define ASC_WARN_EEPROM_RECOVER 0x0020
387 #define ASC_WARN_CFG_MSW_RECOVER 0x0040
388
389 /*
390 * Error code values are set in {ASC/ADV}_DVC_VAR 'err_code'.
391 */
392 #define ASC_IERR_NO_CARRIER 0x0001 /* No more carrier memory */
393 #define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */
394 #define ASC_IERR_SET_PC_ADDR 0x0004
395 #define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */
396 #define ASC_IERR_ILLEGAL_CONNECTION 0x0010 /* Illegal cable connection */
397 #define ASC_IERR_SINGLE_END_DEVICE 0x0020 /* SE device on DIFF bus */
398 #define ASC_IERR_REVERSED_CABLE 0x0040 /* Narrow flat cable reversed */
399 #define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */
400 #define ASC_IERR_HVD_DEVICE 0x0100 /* HVD device on LVD port */
401 #define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */
402 #define ASC_IERR_NO_BUS_TYPE 0x0400
403 #define ASC_IERR_BIST_PRE_TEST 0x0800 /* BIST pre-test error */
404 #define ASC_IERR_BIST_RAM_TEST 0x1000 /* BIST RAM test error */
405 #define ASC_IERR_BAD_CHIPTYPE 0x2000 /* Invalid chip_type setting */
406
407 #define ASC_DEF_MAX_TOTAL_QNG (0xF0)
408 #define ASC_MIN_TAG_Q_PER_DVC (0x04)
409 #define ASC_MIN_FREE_Q (0x02)
410 #define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
411 #define ASC_MAX_TOTAL_QNG 240
412 #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
413 #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8
414 #define ASC_MAX_PCI_INRAM_TOTAL_QNG 20
415 #define ASC_MAX_INRAM_TAG_QNG 16
416 #define ASC_IOADR_GAP 0x10
417 #define ASC_SYN_MAX_OFFSET 0x0F
418 #define ASC_DEF_SDTR_OFFSET 0x0F
419 #define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02
420 #define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
421
422 /* The narrow chip only supports a limited selection of transfer rates.
423 * These are encoded in the range 0..7 or 0..15 depending whether the chip
424 * is Ultra-capable or not. These tables let us convert from one to the other.
425 */
426 static const unsigned char asc_syn_xfer_period[8] = {
427 25, 30, 35, 40, 50, 60, 70, 85
428 };
429
430 static const unsigned char asc_syn_ultra_xfer_period[16] = {
431 12, 19, 25, 32, 38, 44, 50, 57, 63, 69, 75, 82, 88, 94, 100, 107
432 };
433
434 typedef struct ext_msg {
435 uchar msg_type;
436 uchar msg_len;
437 uchar msg_req;
438 union {
439 struct {
440 uchar sdtr_xfer_period;
441 uchar sdtr_req_ack_offset;
442 } sdtr;
443 struct {
444 uchar wdtr_width;
445 } wdtr;
446 struct {
447 uchar mdp_b3;
448 uchar mdp_b2;
449 uchar mdp_b1;
450 uchar mdp_b0;
451 } mdp;
452 } u_ext_msg;
453 uchar res;
454 } EXT_MSG;
455
456 #define xfer_period u_ext_msg.sdtr.sdtr_xfer_period
457 #define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset
458 #define wdtr_width u_ext_msg.wdtr.wdtr_width
459 #define mdp_b3 u_ext_msg.mdp_b3
460 #define mdp_b2 u_ext_msg.mdp_b2
461 #define mdp_b1 u_ext_msg.mdp_b1
462 #define mdp_b0 u_ext_msg.mdp_b0
463
464 typedef struct asc_dvc_cfg {
465 ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
466 ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
467 ASC_SCSI_BIT_ID_TYPE disc_enable;
468 ASC_SCSI_BIT_ID_TYPE sdtr_enable;
469 uchar chip_scsi_id;
470 uchar isa_dma_speed;
471 uchar isa_dma_channel;
472 uchar chip_version;
473 ushort mcode_date;
474 ushort mcode_version;
475 uchar max_tag_qng[ASC_MAX_TID + 1];
476 uchar sdtr_period_offset[ASC_MAX_TID + 1];
477 uchar adapter_info[6];
478 } ASC_DVC_CFG;
479
480 #define ASC_DEF_DVC_CNTL 0xFFFF
481 #define ASC_DEF_CHIP_SCSI_ID 7
482 #define ASC_DEF_ISA_DMA_SPEED 4
483 #define ASC_INIT_STATE_BEG_GET_CFG 0x0001
484 #define ASC_INIT_STATE_END_GET_CFG 0x0002
485 #define ASC_INIT_STATE_BEG_SET_CFG 0x0004
486 #define ASC_INIT_STATE_END_SET_CFG 0x0008
487 #define ASC_INIT_STATE_BEG_LOAD_MC 0x0010
488 #define ASC_INIT_STATE_END_LOAD_MC 0x0020
489 #define ASC_INIT_STATE_BEG_INQUIRY 0x0040
490 #define ASC_INIT_STATE_END_INQUIRY 0x0080
491 #define ASC_INIT_RESET_SCSI_DONE 0x0100
492 #define ASC_INIT_STATE_WITHOUT_EEP 0x8000
493 #define ASC_BUG_FIX_IF_NOT_DWB 0x0001
494 #define ASC_BUG_FIX_ASYN_USE_SYN 0x0002
495 #define ASC_MIN_TAGGED_CMD 7
496 #define ASC_MAX_SCSI_RESET_WAIT 30
497 #define ASC_OVERRUN_BSIZE 64
498
499 struct asc_dvc_var; /* Forward Declaration. */
500
501 typedef struct asc_dvc_var {
502 PortAddr iop_base;
503 ushort err_code;
504 ushort dvc_cntl;
505 ushort bug_fix_cntl;
506 ushort bus_type;
507 ASC_SCSI_BIT_ID_TYPE init_sdtr;
508 ASC_SCSI_BIT_ID_TYPE sdtr_done;
509 ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
510 ASC_SCSI_BIT_ID_TYPE unit_not_ready;
511 ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
512 ASC_SCSI_BIT_ID_TYPE start_motor;
513 uchar *overrun_buf;
514 dma_addr_t overrun_dma;
515 uchar scsi_reset_wait;
516 uchar chip_no;
517 bool is_in_int;
518 uchar max_total_qng;
519 uchar cur_total_qng;
520 uchar in_critical_cnt;
521 uchar last_q_shortage;
522 ushort init_state;
523 uchar cur_dvc_qng[ASC_MAX_TID + 1];
524 uchar max_dvc_qng[ASC_MAX_TID + 1];
525 ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
526 ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
527 const uchar *sdtr_period_tbl;
528 ASC_DVC_CFG *cfg;
529 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
530 char redo_scam;
531 ushort res2;
532 uchar dos_int13_table[ASC_MAX_TID + 1];
533 unsigned int max_dma_count;
534 ASC_SCSI_BIT_ID_TYPE no_scam;
535 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
536 uchar min_sdtr_index;
537 uchar max_sdtr_index;
538 struct asc_board *drv_ptr;
539 unsigned int uc_break;
540 } ASC_DVC_VAR;
541
542 typedef struct asc_dvc_inq_info {
543 uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
544 } ASC_DVC_INQ_INFO;
545
546 typedef struct asc_cap_info {
547 u32 lba;
548 u32 blk_size;
549 } ASC_CAP_INFO;
550
551 typedef struct asc_cap_info_array {
552 ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
553 } ASC_CAP_INFO_ARRAY;
554
555 #define ASC_MCNTL_NO_SEL_TIMEOUT (ushort)0x0001
556 #define ASC_MCNTL_NULL_TARGET (ushort)0x0002
557 #define ASC_CNTL_INITIATOR (ushort)0x0001
558 #define ASC_CNTL_BIOS_GT_1GB (ushort)0x0002
559 #define ASC_CNTL_BIOS_GT_2_DISK (ushort)0x0004
560 #define ASC_CNTL_BIOS_REMOVABLE (ushort)0x0008
561 #define ASC_CNTL_NO_SCAM (ushort)0x0010
562 #define ASC_CNTL_INT_MULTI_Q (ushort)0x0080
563 #define ASC_CNTL_NO_LUN_SUPPORT (ushort)0x0040
564 #define ASC_CNTL_NO_VERIFY_COPY (ushort)0x0100
565 #define ASC_CNTL_RESET_SCSI (ushort)0x0200
566 #define ASC_CNTL_INIT_INQUIRY (ushort)0x0400
567 #define ASC_CNTL_INIT_VERBOSE (ushort)0x0800
568 #define ASC_CNTL_SCSI_PARITY (ushort)0x1000
569 #define ASC_CNTL_BURST_MODE (ushort)0x2000
570 #define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
571 #define ASC_EEP_DVC_CFG_BEG_VL 2
572 #define ASC_EEP_MAX_DVC_ADDR_VL 15
573 #define ASC_EEP_DVC_CFG_BEG 32
574 #define ASC_EEP_MAX_DVC_ADDR 45
575 #define ASC_EEP_MAX_RETRY 20
576
577 /*
578 * These macros keep the chip SCSI id and ISA DMA speed
579 * bitfields in board order. C bitfields aren't portable
580 * between big and little-endian platforms so they are
581 * not used.
582 */
583
584 #define ASC_EEP_GET_CHIP_ID(cfg) ((cfg)->id_speed & 0x0f)
585 #define ASC_EEP_GET_DMA_SPD(cfg) (((cfg)->id_speed & 0xf0) >> 4)
586 #define ASC_EEP_SET_CHIP_ID(cfg, sid) \
587 ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
588 #define ASC_EEP_SET_DMA_SPD(cfg, spd) \
589 ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
590
591 typedef struct asceep_config {
592 ushort cfg_lsw;
593 ushort cfg_msw;
594 uchar init_sdtr;
595 uchar disc_enable;
596 uchar use_cmd_qng;
597 uchar start_motor;
598 uchar max_total_qng;
599 uchar max_tag_qng;
600 uchar bios_scan;
601 uchar power_up_wait;
602 uchar no_scam;
603 uchar id_speed; /* low order 4 bits is chip scsi id */
604 /* high order 4 bits is isa dma speed */
605 uchar dos_int13_table[ASC_MAX_TID + 1];
606 uchar adapter_info[6];
607 ushort cntl;
608 ushort chksum;
609 } ASCEEP_CONFIG;
610
611 #define ASC_EEP_CMD_READ 0x80
612 #define ASC_EEP_CMD_WRITE 0x40
613 #define ASC_EEP_CMD_WRITE_ABLE 0x30
614 #define ASC_EEP_CMD_WRITE_DISABLE 0x00
615 #define ASCV_MSGOUT_BEG 0x0000
616 #define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
617 #define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
618 #define ASCV_BREAK_SAVED_CODE (ushort)0x0006
619 #define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8)
620 #define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3)
621 #define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4)
622 #define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8)
623 #define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8)
624 #define ASCV_MAX_DVC_QNG_BEG (ushort)0x0020
625 #define ASCV_BREAK_ADDR (ushort)0x0028
626 #define ASCV_BREAK_NOTIFY_COUNT (ushort)0x002A
627 #define ASCV_BREAK_CONTROL (ushort)0x002C
628 #define ASCV_BREAK_HIT_COUNT (ushort)0x002E
629
630 #define ASCV_ASCDVC_ERR_CODE_W (ushort)0x0030
631 #define ASCV_MCODE_CHKSUM_W (ushort)0x0032
632 #define ASCV_MCODE_SIZE_W (ushort)0x0034
633 #define ASCV_STOP_CODE_B (ushort)0x0036
634 #define ASCV_DVC_ERR_CODE_B (ushort)0x0037
635 #define ASCV_OVERRUN_PADDR_D (ushort)0x0038
636 #define ASCV_OVERRUN_BSIZE_D (ushort)0x003C
637 #define ASCV_HALTCODE_W (ushort)0x0040
638 #define ASCV_CHKSUM_W (ushort)0x0042
639 #define ASCV_MC_DATE_W (ushort)0x0044
640 #define ASCV_MC_VER_W (ushort)0x0046
641 #define ASCV_NEXTRDY_B (ushort)0x0048
642 #define ASCV_DONENEXT_B (ushort)0x0049
643 #define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
644 #define ASCV_SCSIBUSY_B (ushort)0x004B
645 #define ASCV_Q_DONE_IN_PROGRESS_B (ushort)0x004C
646 #define ASCV_CURCDB_B (ushort)0x004D
647 #define ASCV_RCLUN_B (ushort)0x004E
648 #define ASCV_BUSY_QHEAD_B (ushort)0x004F
649 #define ASCV_DISC1_QHEAD_B (ushort)0x0050
650 #define ASCV_DISC_ENABLE_B (ushort)0x0052
651 #define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
652 #define ASCV_HOSTSCSI_ID_B (ushort)0x0055
653 #define ASCV_MCODE_CNTL_B (ushort)0x0056
654 #define ASCV_NULL_TARGET_B (ushort)0x0057
655 #define ASCV_FREE_Q_HEAD_W (ushort)0x0058
656 #define ASCV_DONE_Q_TAIL_W (ushort)0x005A
657 #define ASCV_FREE_Q_HEAD_B (ushort)(ASCV_FREE_Q_HEAD_W+1)
658 #define ASCV_DONE_Q_TAIL_B (ushort)(ASCV_DONE_Q_TAIL_W+1)
659 #define ASCV_HOST_FLAG_B (ushort)0x005D
660 #define ASCV_TOTAL_READY_Q_B (ushort)0x0064
661 #define ASCV_VER_SERIAL_B (ushort)0x0065
662 #define ASCV_HALTCODE_SAVED_W (ushort)0x0066
663 #define ASCV_WTM_FLAG_B (ushort)0x0068
664 #define ASCV_RISC_FLAG_B (ushort)0x006A
665 #define ASCV_REQ_SG_LIST_QP (ushort)0x006B
666 #define ASC_HOST_FLAG_IN_ISR 0x01
667 #define ASC_HOST_FLAG_ACK_INT 0x02
668 #define ASC_RISC_FLAG_GEN_INT 0x01
669 #define ASC_RISC_FLAG_REQ_SG_LIST 0x02
670 #define IOP_CTRL (0x0F)
671 #define IOP_STATUS (0x0E)
672 #define IOP_INT_ACK IOP_STATUS
673 #define IOP_REG_IFC (0x0D)
674 #define IOP_SYN_OFFSET (0x0B)
675 #define IOP_EXTRA_CONTROL (0x0D)
676 #define IOP_REG_PC (0x0C)
677 #define IOP_RAM_ADDR (0x0A)
678 #define IOP_RAM_DATA (0x08)
679 #define IOP_EEP_DATA (0x06)
680 #define IOP_EEP_CMD (0x07)
681 #define IOP_VERSION (0x03)
682 #define IOP_CONFIG_HIGH (0x04)
683 #define IOP_CONFIG_LOW (0x02)
684 #define IOP_SIG_BYTE (0x01)
685 #define IOP_SIG_WORD (0x00)
686 #define IOP_REG_DC1 (0x0E)
687 #define IOP_REG_DC0 (0x0C)
688 #define IOP_REG_SB (0x0B)
689 #define IOP_REG_DA1 (0x0A)
690 #define IOP_REG_DA0 (0x08)
691 #define IOP_REG_SC (0x09)
692 #define IOP_DMA_SPEED (0x07)
693 #define IOP_REG_FLAG (0x07)
694 #define IOP_FIFO_H (0x06)
695 #define IOP_FIFO_L (0x04)
696 #define IOP_REG_ID (0x05)
697 #define IOP_REG_QP (0x03)
698 #define IOP_REG_IH (0x02)
699 #define IOP_REG_IX (0x01)
700 #define IOP_REG_AX (0x00)
701 #define IFC_REG_LOCK (0x00)
702 #define IFC_REG_UNLOCK (0x09)
703 #define IFC_WR_EN_FILTER (0x10)
704 #define IFC_RD_NO_EEPROM (0x10)
705 #define IFC_SLEW_RATE (0x20)
706 #define IFC_ACT_NEG (0x40)
707 #define IFC_INP_FILTER (0x80)
708 #define IFC_INIT_DEFAULT (IFC_ACT_NEG | IFC_REG_UNLOCK)
709 #define SC_SEL (uchar)(0x80)
710 #define SC_BSY (uchar)(0x40)
711 #define SC_ACK (uchar)(0x20)
712 #define SC_REQ (uchar)(0x10)
713 #define SC_ATN (uchar)(0x08)
714 #define SC_IO (uchar)(0x04)
715 #define SC_CD (uchar)(0x02)
716 #define SC_MSG (uchar)(0x01)
717 #define SEC_SCSI_CTL (uchar)(0x80)
718 #define SEC_ACTIVE_NEGATE (uchar)(0x40)
719 #define SEC_SLEW_RATE (uchar)(0x20)
720 #define SEC_ENABLE_FILTER (uchar)(0x10)
721 #define ASC_HALT_EXTMSG_IN (ushort)0x8000
722 #define ASC_HALT_CHK_CONDITION (ushort)0x8100
723 #define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
724 #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX (ushort)0x8300
725 #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX (ushort)0x8400
726 #define ASC_HALT_SDTR_REJECTED (ushort)0x4000
727 #define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
728 #define ASC_MAX_QNO 0xF8
729 #define ASC_DATA_SEC_BEG (ushort)0x0080
730 #define ASC_DATA_SEC_END (ushort)0x0080
731 #define ASC_CODE_SEC_BEG (ushort)0x0080
732 #define ASC_CODE_SEC_END (ushort)0x0080
733 #define ASC_QADR_BEG (0x4000)
734 #define ASC_QADR_USED (ushort)(ASC_MAX_QNO * 64)
735 #define ASC_QADR_END (ushort)0x7FFF
736 #define ASC_QLAST_ADR (ushort)0x7FC0
737 #define ASC_QBLK_SIZE 0x40
738 #define ASC_BIOS_DATA_QBEG 0xF8
739 #define ASC_MIN_ACTIVE_QNO 0x01
740 #define ASC_QLINK_END 0xFF
741 #define ASC_EEPROM_WORDS 0x10
742 #define ASC_MAX_MGS_LEN 0x10
743 #define ASC_BIOS_ADDR_DEF 0xDC00
744 #define ASC_BIOS_SIZE 0x3800
745 #define ASC_BIOS_RAM_OFF 0x3800
746 #define ASC_BIOS_RAM_SIZE 0x800
747 #define ASC_BIOS_MIN_ADDR 0xC000
748 #define ASC_BIOS_MAX_ADDR 0xEC00
749 #define ASC_BIOS_BANK_SIZE 0x0400
750 #define ASC_MCODE_START_ADDR 0x0080
751 #define ASC_CFG0_HOST_INT_ON 0x0020
752 #define ASC_CFG0_BIOS_ON 0x0040
753 #define ASC_CFG0_VERA_BURST_ON 0x0080
754 #define ASC_CFG0_SCSI_PARITY_ON 0x0800
755 #define ASC_CFG1_SCSI_TARGET_ON 0x0080
756 #define ASC_CFG1_LRAM_8BITS_ON 0x0800
757 #define ASC_CFG_MSW_CLR_MASK 0x3080
758 #define CSW_TEST1 (ASC_CS_TYPE)0x8000
759 #define CSW_AUTO_CONFIG (ASC_CS_TYPE)0x4000
760 #define CSW_RESERVED1 (ASC_CS_TYPE)0x2000
761 #define CSW_IRQ_WRITTEN (ASC_CS_TYPE)0x1000
762 #define CSW_33MHZ_SELECTED (ASC_CS_TYPE)0x0800
763 #define CSW_TEST2 (ASC_CS_TYPE)0x0400
764 #define CSW_TEST3 (ASC_CS_TYPE)0x0200
765 #define CSW_RESERVED2 (ASC_CS_TYPE)0x0100
766 #define CSW_DMA_DONE (ASC_CS_TYPE)0x0080
767 #define CSW_FIFO_RDY (ASC_CS_TYPE)0x0040
768 #define CSW_EEP_READ_DONE (ASC_CS_TYPE)0x0020
769 #define CSW_HALTED (ASC_CS_TYPE)0x0010
770 #define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
771 #define CSW_PARITY_ERR (ASC_CS_TYPE)0x0004
772 #define CSW_SCSI_RESET_LATCH (ASC_CS_TYPE)0x0002
773 #define CSW_INT_PENDING (ASC_CS_TYPE)0x0001
774 #define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
775 #define CIW_INT_ACK (ASC_CS_TYPE)0x0100
776 #define CIW_TEST1 (ASC_CS_TYPE)0x0200
777 #define CIW_TEST2 (ASC_CS_TYPE)0x0400
778 #define CIW_SEL_33MHZ (ASC_CS_TYPE)0x0800
779 #define CIW_IRQ_ACT (ASC_CS_TYPE)0x1000
780 #define CC_CHIP_RESET (uchar)0x80
781 #define CC_SCSI_RESET (uchar)0x40
782 #define CC_HALT (uchar)0x20
783 #define CC_SINGLE_STEP (uchar)0x10
784 #define CC_DMA_ABLE (uchar)0x08
785 #define CC_TEST (uchar)0x04
786 #define CC_BANK_ONE (uchar)0x02
787 #define CC_DIAG (uchar)0x01
788 #define ASC_1000_ID0W 0x04C1
789 #define ASC_1000_ID0W_FIX 0x00C1
790 #define ASC_1000_ID1B 0x25
791 #define ASC_EISA_REV_IOP_MASK (0x0C83)
792 #define ASC_EISA_CFG_IOP_MASK (0x0C86)
793 #define ASC_GET_EISA_SLOT(iop) (PortAddr)((iop) & 0xF000)
794 #define INS_HALTINT (ushort)0x6281
795 #define INS_HALT (ushort)0x6280
796 #define INS_SINT (ushort)0x6200
797 #define INS_RFLAG_WTM (ushort)0x7380
798 #define ASC_MC_SAVE_CODE_WSIZE 0x500
799 #define ASC_MC_SAVE_DATA_WSIZE 0x40
800
801 typedef struct asc_mc_saved {
802 ushort data[ASC_MC_SAVE_DATA_WSIZE];
803 ushort code[ASC_MC_SAVE_CODE_WSIZE];
804 } ASC_MC_SAVED;
805
806 #define AscGetQDoneInProgress(port) AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
807 #define AscPutQDoneInProgress(port, val) AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
808 #define AscGetVarFreeQHead(port) AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
809 #define AscGetVarDoneQTail(port) AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
810 #define AscPutVarFreeQHead(port, val) AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
811 #define AscPutVarDoneQTail(port, val) AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
812 #define AscGetRiscVarFreeQHead(port) AscReadLramByte((port), ASCV_NEXTRDY_B)
813 #define AscGetRiscVarDoneQTail(port) AscReadLramByte((port), ASCV_DONENEXT_B)
814 #define AscPutRiscVarFreeQHead(port, val) AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
815 #define AscPutRiscVarDoneQTail(port, val) AscWriteLramByte((port), ASCV_DONENEXT_B, val)
816 #define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data))
817 #define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id))
818 #define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data)
819 #define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id))
820 #define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE)
821 #define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD)
822 #define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION)
823 #define AscGetChipCfgLsw(port) (ushort)inpw((port)+IOP_CONFIG_LOW)
824 #define AscGetChipCfgMsw(port) (ushort)inpw((port)+IOP_CONFIG_HIGH)
825 #define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data)
826 #define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data)
827 #define AscGetChipEEPCmd(port) (uchar)inp((port)+IOP_EEP_CMD)
828 #define AscSetChipEEPCmd(port, data) outp((port)+IOP_EEP_CMD, data)
829 #define AscGetChipEEPData(port) (ushort)inpw((port)+IOP_EEP_DATA)
830 #define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data)
831 #define AscGetChipLramAddr(port) (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
832 #define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
833 #define AscGetChipLramData(port) (ushort)inpw((port)+IOP_RAM_DATA)
834 #define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data)
835 #define AscGetChipIFC(port) (uchar)inp((port)+IOP_REG_IFC)
836 #define AscSetChipIFC(port, data) outp((port)+IOP_REG_IFC, data)
837 #define AscGetChipStatus(port) (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
838 #define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val)
839 #define AscGetChipControl(port) (uchar)inp((port)+IOP_CTRL)
840 #define AscSetChipControl(port, cc_val) outp((port)+IOP_CTRL, cc_val)
841 #define AscGetChipSyn(port) (uchar)inp((port)+IOP_SYN_OFFSET)
842 #define AscSetChipSyn(port, data) outp((port)+IOP_SYN_OFFSET, data)
843 #define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data)
844 #define AscGetPCAddr(port) (ushort)inpw((port)+IOP_REG_PC)
845 #define AscIsIntPending(port) (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
846 #define AscGetChipScsiID(port) ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
847 #define AscGetExtraControl(port) (uchar)inp((port)+IOP_EXTRA_CONTROL)
848 #define AscSetExtraControl(port, data) outp((port)+IOP_EXTRA_CONTROL, data)
849 #define AscReadChipAX(port) (ushort)inpw((port)+IOP_REG_AX)
850 #define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data)
851 #define AscReadChipIX(port) (uchar)inp((port)+IOP_REG_IX)
852 #define AscWriteChipIX(port, data) outp((port)+IOP_REG_IX, data)
853 #define AscReadChipIH(port) (ushort)inpw((port)+IOP_REG_IH)
854 #define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data)
855 #define AscReadChipQP(port) (uchar)inp((port)+IOP_REG_QP)
856 #define AscWriteChipQP(port, data) outp((port)+IOP_REG_QP, data)
857 #define AscReadChipFIFO_L(port) (ushort)inpw((port)+IOP_REG_FIFO_L)
858 #define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data)
859 #define AscReadChipFIFO_H(port) (ushort)inpw((port)+IOP_REG_FIFO_H)
860 #define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data)
861 #define AscReadChipDmaSpeed(port) (uchar)inp((port)+IOP_DMA_SPEED)
862 #define AscWriteChipDmaSpeed(port, data) outp((port)+IOP_DMA_SPEED, data)
863 #define AscReadChipDA0(port) (ushort)inpw((port)+IOP_REG_DA0)
864 #define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data)
865 #define AscReadChipDA1(port) (ushort)inpw((port)+IOP_REG_DA1)
866 #define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data)
867 #define AscReadChipDC0(port) (ushort)inpw((port)+IOP_REG_DC0)
868 #define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data)
869 #define AscReadChipDC1(port) (ushort)inpw((port)+IOP_REG_DC1)
870 #define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data)
871 #define AscReadChipDvcID(port) (uchar)inp((port)+IOP_REG_ID)
872 #define AscWriteChipDvcID(port, data) outp((port)+IOP_REG_ID, data)
873
874 #define AdvPortAddr void __iomem * /* Virtual memory address size */
875
876 /*
877 * Define Adv Library required memory access macros.
878 */
879 #define ADV_MEM_READB(addr) readb(addr)
880 #define ADV_MEM_READW(addr) readw(addr)
881 #define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
882 #define ADV_MEM_WRITEW(addr, word) writew(word, addr)
883 #define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
884
885 /*
886 * Define total number of simultaneous maximum element scatter-gather
887 * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
888 * maximum number of outstanding commands per wide host adapter. Each
889 * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
890 * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
891 * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
892 * structures or 255 scatter-gather elements.
893 */
894 #define ADV_TOT_SG_BLOCK ASC_DEF_MAX_HOST_QNG
895
896 /*
897 * Define maximum number of scatter-gather elements per request.
898 */
899 #define ADV_MAX_SG_LIST 255
900 #define NO_OF_SG_PER_BLOCK 15
901
902 #define ADV_EEP_DVC_CFG_BEGIN (0x00)
903 #define ADV_EEP_DVC_CFG_END (0x15)
904 #define ADV_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */
905 #define ADV_EEP_MAX_WORD_ADDR (0x1E)
906
907 #define ADV_EEP_DELAY_MS 100
908
909 #define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */
910 #define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */
911 /*
912 * For the ASC3550 Bit 13 is Termination Polarity control bit.
913 * For later ICs Bit 13 controls whether the CIS (Card Information
914 * Service Section) is loaded from EEPROM.
915 */
916 #define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */
917 #define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */
918 /*
919 * ASC38C1600 Bit 11
920 *
921 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
922 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
923 * Function 0 will specify INT B.
924 *
925 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
926 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
927 * Function 1 will specify INT A.
928 */
929 #define ADV_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */
930
931 typedef struct adveep_3550_config {
932 /* Word Offset, Description */
933
934 ushort cfg_lsw; /* 00 power up initialization */
935 /* bit 13 set - Term Polarity Control */
936 /* bit 14 set - BIOS Enable */
937 /* bit 15 set - Big Endian Mode */
938 ushort cfg_msw; /* 01 unused */
939 ushort disc_enable; /* 02 disconnect enable */
940 ushort wdtr_able; /* 03 Wide DTR able */
941 ushort sdtr_able; /* 04 Synchronous DTR able */
942 ushort start_motor; /* 05 send start up motor */
943 ushort tagqng_able; /* 06 tag queuing able */
944 ushort bios_scan; /* 07 BIOS device control */
945 ushort scam_tolerant; /* 08 no scam */
946
947 uchar adapter_scsi_id; /* 09 Host Adapter ID */
948 uchar bios_boot_delay; /* power up wait */
949
950 uchar scsi_reset_delay; /* 10 reset delay */
951 uchar bios_id_lun; /* first boot device scsi id & lun */
952 /* high nibble is lun */
953 /* low nibble is scsi id */
954
955 uchar termination; /* 11 0 - automatic */
956 /* 1 - low off / high off */
957 /* 2 - low off / high on */
958 /* 3 - low on / high on */
959 /* There is no low on / high off */
960
961 uchar reserved1; /* reserved byte (not used) */
962
963 ushort bios_ctrl; /* 12 BIOS control bits */
964 /* bit 0 BIOS don't act as initiator. */
965 /* bit 1 BIOS > 1 GB support */
966 /* bit 2 BIOS > 2 Disk Support */
967 /* bit 3 BIOS don't support removables */
968 /* bit 4 BIOS support bootable CD */
969 /* bit 5 BIOS scan enabled */
970 /* bit 6 BIOS support multiple LUNs */
971 /* bit 7 BIOS display of message */
972 /* bit 8 SCAM disabled */
973 /* bit 9 Reset SCSI bus during init. */
974 /* bit 10 */
975 /* bit 11 No verbose initialization. */
976 /* bit 12 SCSI parity enabled */
977 /* bit 13 */
978 /* bit 14 */
979 /* bit 15 */
980 ushort ultra_able; /* 13 ULTRA speed able */
981 ushort reserved2; /* 14 reserved */
982 uchar max_host_qng; /* 15 maximum host queuing */
983 uchar max_dvc_qng; /* maximum per device queuing */
984 ushort dvc_cntl; /* 16 control bit for driver */
985 ushort bug_fix; /* 17 control bit for bug fix */
986 ushort serial_number_word1; /* 18 Board serial number word 1 */
987 ushort serial_number_word2; /* 19 Board serial number word 2 */
988 ushort serial_number_word3; /* 20 Board serial number word 3 */
989 ushort check_sum; /* 21 EEP check sum */
990 uchar oem_name[16]; /* 22 OEM name */
991 ushort dvc_err_code; /* 30 last device driver error code */
992 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
993 ushort adv_err_addr; /* 32 last uc error address */
994 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
995 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
996 ushort saved_adv_err_addr; /* 35 saved last uc error address */
997 ushort num_of_err; /* 36 number of error */
998 } ADVEEP_3550_CONFIG;
999
1000 typedef struct adveep_38C0800_config {
1001 /* Word Offset, Description */
1002
1003 ushort cfg_lsw; /* 00 power up initialization */
1004 /* bit 13 set - Load CIS */
1005 /* bit 14 set - BIOS Enable */
1006 /* bit 15 set - Big Endian Mode */
1007 ushort cfg_msw; /* 01 unused */
1008 ushort disc_enable; /* 02 disconnect enable */
1009 ushort wdtr_able; /* 03 Wide DTR able */
1010 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1011 ushort start_motor; /* 05 send start up motor */
1012 ushort tagqng_able; /* 06 tag queuing able */
1013 ushort bios_scan; /* 07 BIOS device control */
1014 ushort scam_tolerant; /* 08 no scam */
1015
1016 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1017 uchar bios_boot_delay; /* power up wait */
1018
1019 uchar scsi_reset_delay; /* 10 reset delay */
1020 uchar bios_id_lun; /* first boot device scsi id & lun */
1021 /* high nibble is lun */
1022 /* low nibble is scsi id */
1023
1024 uchar termination_se; /* 11 0 - automatic */
1025 /* 1 - low off / high off */
1026 /* 2 - low off / high on */
1027 /* 3 - low on / high on */
1028 /* There is no low on / high off */
1029
1030 uchar termination_lvd; /* 11 0 - automatic */
1031 /* 1 - low off / high off */
1032 /* 2 - low off / high on */
1033 /* 3 - low on / high on */
1034 /* There is no low on / high off */
1035
1036 ushort bios_ctrl; /* 12 BIOS control bits */
1037 /* bit 0 BIOS don't act as initiator. */
1038 /* bit 1 BIOS > 1 GB support */
1039 /* bit 2 BIOS > 2 Disk Support */
1040 /* bit 3 BIOS don't support removables */
1041 /* bit 4 BIOS support bootable CD */
1042 /* bit 5 BIOS scan enabled */
1043 /* bit 6 BIOS support multiple LUNs */
1044 /* bit 7 BIOS display of message */
1045 /* bit 8 SCAM disabled */
1046 /* bit 9 Reset SCSI bus during init. */
1047 /* bit 10 */
1048 /* bit 11 No verbose initialization. */
1049 /* bit 12 SCSI parity enabled */
1050 /* bit 13 */
1051 /* bit 14 */
1052 /* bit 15 */
1053 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1054 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1055 uchar max_host_qng; /* 15 maximum host queueing */
1056 uchar max_dvc_qng; /* maximum per device queuing */
1057 ushort dvc_cntl; /* 16 control bit for driver */
1058 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1059 ushort serial_number_word1; /* 18 Board serial number word 1 */
1060 ushort serial_number_word2; /* 19 Board serial number word 2 */
1061 ushort serial_number_word3; /* 20 Board serial number word 3 */
1062 ushort check_sum; /* 21 EEP check sum */
1063 uchar oem_name[16]; /* 22 OEM name */
1064 ushort dvc_err_code; /* 30 last device driver error code */
1065 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1066 ushort adv_err_addr; /* 32 last uc error address */
1067 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1068 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1069 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1070 ushort reserved36; /* 36 reserved */
1071 ushort reserved37; /* 37 reserved */
1072 ushort reserved38; /* 38 reserved */
1073 ushort reserved39; /* 39 reserved */
1074 ushort reserved40; /* 40 reserved */
1075 ushort reserved41; /* 41 reserved */
1076 ushort reserved42; /* 42 reserved */
1077 ushort reserved43; /* 43 reserved */
1078 ushort reserved44; /* 44 reserved */
1079 ushort reserved45; /* 45 reserved */
1080 ushort reserved46; /* 46 reserved */
1081 ushort reserved47; /* 47 reserved */
1082 ushort reserved48; /* 48 reserved */
1083 ushort reserved49; /* 49 reserved */
1084 ushort reserved50; /* 50 reserved */
1085 ushort reserved51; /* 51 reserved */
1086 ushort reserved52; /* 52 reserved */
1087 ushort reserved53; /* 53 reserved */
1088 ushort reserved54; /* 54 reserved */
1089 ushort reserved55; /* 55 reserved */
1090 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1091 ushort cisprt_msw; /* 57 CIS PTR MSW */
1092 ushort subsysvid; /* 58 SubSystem Vendor ID */
1093 ushort subsysid; /* 59 SubSystem ID */
1094 ushort reserved60; /* 60 reserved */
1095 ushort reserved61; /* 61 reserved */
1096 ushort reserved62; /* 62 reserved */
1097 ushort reserved63; /* 63 reserved */
1098 } ADVEEP_38C0800_CONFIG;
1099
1100 typedef struct adveep_38C1600_config {
1101 /* Word Offset, Description */
1102
1103 ushort cfg_lsw; /* 00 power up initialization */
1104 /* bit 11 set - Func. 0 INTB, Func. 1 INTA */
1105 /* clear - Func. 0 INTA, Func. 1 INTB */
1106 /* bit 13 set - Load CIS */
1107 /* bit 14 set - BIOS Enable */
1108 /* bit 15 set - Big Endian Mode */
1109 ushort cfg_msw; /* 01 unused */
1110 ushort disc_enable; /* 02 disconnect enable */
1111 ushort wdtr_able; /* 03 Wide DTR able */
1112 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1113 ushort start_motor; /* 05 send start up motor */
1114 ushort tagqng_able; /* 06 tag queuing able */
1115 ushort bios_scan; /* 07 BIOS device control */
1116 ushort scam_tolerant; /* 08 no scam */
1117
1118 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1119 uchar bios_boot_delay; /* power up wait */
1120
1121 uchar scsi_reset_delay; /* 10 reset delay */
1122 uchar bios_id_lun; /* first boot device scsi id & lun */
1123 /* high nibble is lun */
1124 /* low nibble is scsi id */
1125
1126 uchar termination_se; /* 11 0 - automatic */
1127 /* 1 - low off / high off */
1128 /* 2 - low off / high on */
1129 /* 3 - low on / high on */
1130 /* There is no low on / high off */
1131
1132 uchar termination_lvd; /* 11 0 - automatic */
1133 /* 1 - low off / high off */
1134 /* 2 - low off / high on */
1135 /* 3 - low on / high on */
1136 /* There is no low on / high off */
1137
1138 ushort bios_ctrl; /* 12 BIOS control bits */
1139 /* bit 0 BIOS don't act as initiator. */
1140 /* bit 1 BIOS > 1 GB support */
1141 /* bit 2 BIOS > 2 Disk Support */
1142 /* bit 3 BIOS don't support removables */
1143 /* bit 4 BIOS support bootable CD */
1144 /* bit 5 BIOS scan enabled */
1145 /* bit 6 BIOS support multiple LUNs */
1146 /* bit 7 BIOS display of message */
1147 /* bit 8 SCAM disabled */
1148 /* bit 9 Reset SCSI bus during init. */
1149 /* bit 10 Basic Integrity Checking disabled */
1150 /* bit 11 No verbose initialization. */
1151 /* bit 12 SCSI parity enabled */
1152 /* bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
1153 /* bit 14 */
1154 /* bit 15 */
1155 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1156 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1157 uchar max_host_qng; /* 15 maximum host queueing */
1158 uchar max_dvc_qng; /* maximum per device queuing */
1159 ushort dvc_cntl; /* 16 control bit for driver */
1160 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1161 ushort serial_number_word1; /* 18 Board serial number word 1 */
1162 ushort serial_number_word2; /* 19 Board serial number word 2 */
1163 ushort serial_number_word3; /* 20 Board serial number word 3 */
1164 ushort check_sum; /* 21 EEP check sum */
1165 uchar oem_name[16]; /* 22 OEM name */
1166 ushort dvc_err_code; /* 30 last device driver error code */
1167 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1168 ushort adv_err_addr; /* 32 last uc error address */
1169 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1170 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1171 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1172 ushort reserved36; /* 36 reserved */
1173 ushort reserved37; /* 37 reserved */
1174 ushort reserved38; /* 38 reserved */
1175 ushort reserved39; /* 39 reserved */
1176 ushort reserved40; /* 40 reserved */
1177 ushort reserved41; /* 41 reserved */
1178 ushort reserved42; /* 42 reserved */
1179 ushort reserved43; /* 43 reserved */
1180 ushort reserved44; /* 44 reserved */
1181 ushort reserved45; /* 45 reserved */
1182 ushort reserved46; /* 46 reserved */
1183 ushort reserved47; /* 47 reserved */
1184 ushort reserved48; /* 48 reserved */
1185 ushort reserved49; /* 49 reserved */
1186 ushort reserved50; /* 50 reserved */
1187 ushort reserved51; /* 51 reserved */
1188 ushort reserved52; /* 52 reserved */
1189 ushort reserved53; /* 53 reserved */
1190 ushort reserved54; /* 54 reserved */
1191 ushort reserved55; /* 55 reserved */
1192 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1193 ushort cisprt_msw; /* 57 CIS PTR MSW */
1194 ushort subsysvid; /* 58 SubSystem Vendor ID */
1195 ushort subsysid; /* 59 SubSystem ID */
1196 ushort reserved60; /* 60 reserved */
1197 ushort reserved61; /* 61 reserved */
1198 ushort reserved62; /* 62 reserved */
1199 ushort reserved63; /* 63 reserved */
1200 } ADVEEP_38C1600_CONFIG;
1201
1202 /*
1203 * EEPROM Commands
1204 */
1205 #define ASC_EEP_CMD_DONE 0x0200
1206
1207 /* bios_ctrl */
1208 #define BIOS_CTRL_BIOS 0x0001
1209 #define BIOS_CTRL_EXTENDED_XLAT 0x0002
1210 #define BIOS_CTRL_GT_2_DISK 0x0004
1211 #define BIOS_CTRL_BIOS_REMOVABLE 0x0008
1212 #define BIOS_CTRL_BOOTABLE_CD 0x0010
1213 #define BIOS_CTRL_MULTIPLE_LUN 0x0040
1214 #define BIOS_CTRL_DISPLAY_MSG 0x0080
1215 #define BIOS_CTRL_NO_SCAM 0x0100
1216 #define BIOS_CTRL_RESET_SCSI_BUS 0x0200
1217 #define BIOS_CTRL_INIT_VERBOSE 0x0800
1218 #define BIOS_CTRL_SCSI_PARITY 0x1000
1219 #define BIOS_CTRL_AIPP_DIS 0x2000
1220
1221 #define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */
1222
1223 #define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1224
1225 /*
1226 * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
1227 * a special 16K Adv Library and Microcode version. After the issue is
1228 * resolved, should restore 32K support.
1229 *
1230 * #define ADV_38C1600_MEMSIZE 0x8000L * 32 KB Internal Memory *
1231 */
1232 #define ADV_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1233
1234 /*
1235 * Byte I/O register address from base of 'iop_base'.
1236 */
1237 #define IOPB_INTR_STATUS_REG 0x00
1238 #define IOPB_CHIP_ID_1 0x01
1239 #define IOPB_INTR_ENABLES 0x02
1240 #define IOPB_CHIP_TYPE_REV 0x03
1241 #define IOPB_RES_ADDR_4 0x04
1242 #define IOPB_RES_ADDR_5 0x05
1243 #define IOPB_RAM_DATA 0x06
1244 #define IOPB_RES_ADDR_7 0x07
1245 #define IOPB_FLAG_REG 0x08
1246 #define IOPB_RES_ADDR_9 0x09
1247 #define IOPB_RISC_CSR 0x0A
1248 #define IOPB_RES_ADDR_B 0x0B
1249 #define IOPB_RES_ADDR_C 0x0C
1250 #define IOPB_RES_ADDR_D 0x0D
1251 #define IOPB_SOFT_OVER_WR 0x0E
1252 #define IOPB_RES_ADDR_F 0x0F
1253 #define IOPB_MEM_CFG 0x10
1254 #define IOPB_RES_ADDR_11 0x11
1255 #define IOPB_GPIO_DATA 0x12
1256 #define IOPB_RES_ADDR_13 0x13
1257 #define IOPB_FLASH_PAGE 0x14
1258 #define IOPB_RES_ADDR_15 0x15
1259 #define IOPB_GPIO_CNTL 0x16
1260 #define IOPB_RES_ADDR_17 0x17
1261 #define IOPB_FLASH_DATA 0x18
1262 #define IOPB_RES_ADDR_19 0x19
1263 #define IOPB_RES_ADDR_1A 0x1A
1264 #define IOPB_RES_ADDR_1B 0x1B
1265 #define IOPB_RES_ADDR_1C 0x1C
1266 #define IOPB_RES_ADDR_1D 0x1D
1267 #define IOPB_RES_ADDR_1E 0x1E
1268 #define IOPB_RES_ADDR_1F 0x1F
1269 #define IOPB_DMA_CFG0 0x20
1270 #define IOPB_DMA_CFG1 0x21
1271 #define IOPB_TICKLE 0x22
1272 #define IOPB_DMA_REG_WR 0x23
1273 #define IOPB_SDMA_STATUS 0x24
1274 #define IOPB_SCSI_BYTE_CNT 0x25
1275 #define IOPB_HOST_BYTE_CNT 0x26
1276 #define IOPB_BYTE_LEFT_TO_XFER 0x27
1277 #define IOPB_BYTE_TO_XFER_0 0x28
1278 #define IOPB_BYTE_TO_XFER_1 0x29
1279 #define IOPB_BYTE_TO_XFER_2 0x2A
1280 #define IOPB_BYTE_TO_XFER_3 0x2B
1281 #define IOPB_ACC_GRP 0x2C
1282 #define IOPB_RES_ADDR_2D 0x2D
1283 #define IOPB_DEV_ID 0x2E
1284 #define IOPB_RES_ADDR_2F 0x2F
1285 #define IOPB_SCSI_DATA 0x30
1286 #define IOPB_RES_ADDR_31 0x31
1287 #define IOPB_RES_ADDR_32 0x32
1288 #define IOPB_SCSI_DATA_HSHK 0x33
1289 #define IOPB_SCSI_CTRL 0x34
1290 #define IOPB_RES_ADDR_35 0x35
1291 #define IOPB_RES_ADDR_36 0x36
1292 #define IOPB_RES_ADDR_37 0x37
1293 #define IOPB_RAM_BIST 0x38
1294 #define IOPB_PLL_TEST 0x39
1295 #define IOPB_PCI_INT_CFG 0x3A
1296 #define IOPB_RES_ADDR_3B 0x3B
1297 #define IOPB_RFIFO_CNT 0x3C
1298 #define IOPB_RES_ADDR_3D 0x3D
1299 #define IOPB_RES_ADDR_3E 0x3E
1300 #define IOPB_RES_ADDR_3F 0x3F
1301
1302 /*
1303 * Word I/O register address from base of 'iop_base'.
1304 */
1305 #define IOPW_CHIP_ID_0 0x00 /* CID0 */
1306 #define IOPW_CTRL_REG 0x02 /* CC */
1307 #define IOPW_RAM_ADDR 0x04 /* LA */
1308 #define IOPW_RAM_DATA 0x06 /* LD */
1309 #define IOPW_RES_ADDR_08 0x08
1310 #define IOPW_RISC_CSR 0x0A /* CSR */
1311 #define IOPW_SCSI_CFG0 0x0C /* CFG0 */
1312 #define IOPW_SCSI_CFG1 0x0E /* CFG1 */
1313 #define IOPW_RES_ADDR_10 0x10
1314 #define IOPW_SEL_MASK 0x12 /* SM */
1315 #define IOPW_RES_ADDR_14 0x14
1316 #define IOPW_FLASH_ADDR 0x16 /* FA */
1317 #define IOPW_RES_ADDR_18 0x18
1318 #define IOPW_EE_CMD 0x1A /* EC */
1319 #define IOPW_EE_DATA 0x1C /* ED */
1320 #define IOPW_SFIFO_CNT 0x1E /* SFC */
1321 #define IOPW_RES_ADDR_20 0x20
1322 #define IOPW_Q_BASE 0x22 /* QB */
1323 #define IOPW_QP 0x24 /* QP */
1324 #define IOPW_IX 0x26 /* IX */
1325 #define IOPW_SP 0x28 /* SP */
1326 #define IOPW_PC 0x2A /* PC */
1327 #define IOPW_RES_ADDR_2C 0x2C
1328 #define IOPW_RES_ADDR_2E 0x2E
1329 #define IOPW_SCSI_DATA 0x30 /* SD */
1330 #define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */
1331 #define IOPW_SCSI_CTRL 0x34 /* SC */
1332 #define IOPW_HSHK_CFG 0x36 /* HCFG */
1333 #define IOPW_SXFR_STATUS 0x36 /* SXS */
1334 #define IOPW_SXFR_CNTL 0x38 /* SXL */
1335 #define IOPW_SXFR_CNTH 0x3A /* SXH */
1336 #define IOPW_RES_ADDR_3C 0x3C
1337 #define IOPW_RFIFO_DATA 0x3E /* RFD */
1338
1339 /*
1340 * Doubleword I/O register address from base of 'iop_base'.
1341 */
1342 #define IOPDW_RES_ADDR_0 0x00
1343 #define IOPDW_RAM_DATA 0x04
1344 #define IOPDW_RES_ADDR_8 0x08
1345 #define IOPDW_RES_ADDR_C 0x0C
1346 #define IOPDW_RES_ADDR_10 0x10
1347 #define IOPDW_COMMA 0x14
1348 #define IOPDW_COMMB 0x18
1349 #define IOPDW_RES_ADDR_1C 0x1C
1350 #define IOPDW_SDMA_ADDR0 0x20
1351 #define IOPDW_SDMA_ADDR1 0x24
1352 #define IOPDW_SDMA_COUNT 0x28
1353 #define IOPDW_SDMA_ERROR 0x2C
1354 #define IOPDW_RDMA_ADDR0 0x30
1355 #define IOPDW_RDMA_ADDR1 0x34
1356 #define IOPDW_RDMA_COUNT 0x38
1357 #define IOPDW_RDMA_ERROR 0x3C
1358
1359 #define ADV_CHIP_ID_BYTE 0x25
1360 #define ADV_CHIP_ID_WORD 0x04C1
1361
1362 #define ADV_INTR_ENABLE_HOST_INTR 0x01
1363 #define ADV_INTR_ENABLE_SEL_INTR 0x02
1364 #define ADV_INTR_ENABLE_DPR_INTR 0x04
1365 #define ADV_INTR_ENABLE_RTA_INTR 0x08
1366 #define ADV_INTR_ENABLE_RMA_INTR 0x10
1367 #define ADV_INTR_ENABLE_RST_INTR 0x20
1368 #define ADV_INTR_ENABLE_DPE_INTR 0x40
1369 #define ADV_INTR_ENABLE_GLOBAL_INTR 0x80
1370
1371 #define ADV_INTR_STATUS_INTRA 0x01
1372 #define ADV_INTR_STATUS_INTRB 0x02
1373 #define ADV_INTR_STATUS_INTRC 0x04
1374
1375 #define ADV_RISC_CSR_STOP (0x0000)
1376 #define ADV_RISC_TEST_COND (0x2000)
1377 #define ADV_RISC_CSR_RUN (0x4000)
1378 #define ADV_RISC_CSR_SINGLE_STEP (0x8000)
1379
1380 #define ADV_CTRL_REG_HOST_INTR 0x0100
1381 #define ADV_CTRL_REG_SEL_INTR 0x0200
1382 #define ADV_CTRL_REG_DPR_INTR 0x0400
1383 #define ADV_CTRL_REG_RTA_INTR 0x0800
1384 #define ADV_CTRL_REG_RMA_INTR 0x1000
1385 #define ADV_CTRL_REG_RES_BIT14 0x2000
1386 #define ADV_CTRL_REG_DPE_INTR 0x4000
1387 #define ADV_CTRL_REG_POWER_DONE 0x8000
1388 #define ADV_CTRL_REG_ANY_INTR 0xFF00
1389
1390 #define ADV_CTRL_REG_CMD_RESET 0x00C6
1391 #define ADV_CTRL_REG_CMD_WR_IO_REG 0x00C5
1392 #define ADV_CTRL_REG_CMD_RD_IO_REG 0x00C4
1393 #define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3
1394 #define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2
1395
1396 #define ADV_TICKLE_NOP 0x00
1397 #define ADV_TICKLE_A 0x01
1398 #define ADV_TICKLE_B 0x02
1399 #define ADV_TICKLE_C 0x03
1400
1401 #define AdvIsIntPending(port) \
1402 (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
1403
1404 /*
1405 * SCSI_CFG0 Register bit definitions
1406 */
1407 #define TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */
1408 #define PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */
1409 #define EVEN_PARITY 0x1000 /* Select Even Parity */
1410 #define WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */
1411 #define QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */
1412 #define PRIM_MODE 0x0100 /* Primitive SCSI mode */
1413 #define SCAM_EN 0x0080 /* Enable SCAM selection */
1414 #define SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
1415 #define CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
1416 #define OUR_ID_EN 0x0010 /* Enable OUR_ID bits */
1417 #define OUR_ID 0x000F /* SCSI ID */
1418
1419 /*
1420 * SCSI_CFG1 Register bit definitions
1421 */
1422 #define BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */
1423 #define TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
1424 #define SLEW_RATE 0x1000 /* SCSI output buffer slew rate */
1425 #define FILTER_SEL 0x0C00 /* Filter Period Selection */
1426 #define FLTR_DISABLE 0x0000 /* Input Filtering Disabled */
1427 #define FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
1428 #define FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
1429 #define ACTIVE_DBL 0x0200 /* Disable Active Negation */
1430 #define DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */
1431 #define DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */
1432 #define TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */
1433 #define TERM_CTL 0x0030 /* External SCSI Termination Bits */
1434 #define TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */
1435 #define TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */
1436 #define CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */
1437
1438 /*
1439 * Addendum for ASC-38C0800 Chip
1440 *
1441 * The ASC-38C1600 Chip uses the same definitions except that the
1442 * bus mode override bits [12:10] have been moved to byte register
1443 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
1444 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
1445 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
1446 * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
1447 * and [1:0]. Bits [14], [7:6], [3:2] are unused.
1448 */
1449 #define DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */
1450 #define HVD_LVD_SE 0x1C00 /* Device Detect Bits */
1451 #define HVD 0x1000 /* HVD Device Detect */
1452 #define LVD 0x0800 /* LVD Device Detect */
1453 #define SE 0x0400 /* SE Device Detect */
1454 #define TERM_LVD 0x00C0 /* LVD Termination Bits */
1455 #define TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */
1456 #define TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */
1457 #define TERM_SE 0x0030 /* SE Termination Bits */
1458 #define TERM_SE_HI 0x0020 /* Enable SE Upper Termination */
1459 #define TERM_SE_LO 0x0010 /* Enable SE Lower Termination */
1460 #define C_DET_LVD 0x000C /* LVD Cable Detect Bits */
1461 #define C_DET3 0x0008 /* Cable Detect for LVD External Wide */
1462 #define C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */
1463 #define C_DET_SE 0x0003 /* SE Cable Detect Bits */
1464 #define C_DET1 0x0002 /* Cable Detect for SE Internal Wide */
1465 #define C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */
1466
1467 #define CABLE_ILLEGAL_A 0x7
1468 /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */
1469
1470 #define CABLE_ILLEGAL_B 0xB
1471 /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */
1472
1473 /*
1474 * MEM_CFG Register bit definitions
1475 */
1476 #define BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */
1477 #define FAST_EE_CLK 0x20 /* Diagnostic Bit */
1478 #define RAM_SZ 0x1C /* Specify size of RAM to RISC */
1479 #define RAM_SZ_2KB 0x00 /* 2 KB */
1480 #define RAM_SZ_4KB 0x04 /* 4 KB */
1481 #define RAM_SZ_8KB 0x08 /* 8 KB */
1482 #define RAM_SZ_16KB 0x0C /* 16 KB */
1483 #define RAM_SZ_32KB 0x10 /* 32 KB */
1484 #define RAM_SZ_64KB 0x14 /* 64 KB */
1485
1486 /*
1487 * DMA_CFG0 Register bit definitions
1488 *
1489 * This register is only accessible to the host.
1490 */
1491 #define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */
1492 #define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */
1493 #define FIFO_THRESH_16B 0x00 /* 16 bytes */
1494 #define FIFO_THRESH_32B 0x20 /* 32 bytes */
1495 #define FIFO_THRESH_48B 0x30 /* 48 bytes */
1496 #define FIFO_THRESH_64B 0x40 /* 64 bytes */
1497 #define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */
1498 #define FIFO_THRESH_96B 0x60 /* 96 bytes */
1499 #define FIFO_THRESH_112B 0x70 /* 112 bytes */
1500 #define START_CTL 0x0C /* DMA start conditions */
1501 #define START_CTL_TH 0x00 /* Wait threshold level (default) */
1502 #define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */
1503 #define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */
1504 #define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */
1505 #define READ_CMD 0x03 /* Memory Read Method */
1506 #define READ_CMD_MR 0x00 /* Memory Read */
1507 #define READ_CMD_MRL 0x02 /* Memory Read Long */
1508 #define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */
1509
1510 /*
1511 * ASC-38C0800 RAM BIST Register bit definitions
1512 */
1513 #define RAM_TEST_MODE 0x80
1514 #define PRE_TEST_MODE 0x40
1515 #define NORMAL_MODE 0x00
1516 #define RAM_TEST_DONE 0x10
1517 #define RAM_TEST_STATUS 0x0F
1518 #define RAM_TEST_HOST_ERROR 0x08
1519 #define RAM_TEST_INTRAM_ERROR 0x04
1520 #define RAM_TEST_RISC_ERROR 0x02
1521 #define RAM_TEST_SCSI_ERROR 0x01
1522 #define RAM_TEST_SUCCESS 0x00
1523 #define PRE_TEST_VALUE 0x05
1524 #define NORMAL_VALUE 0x00
1525
1526 /*
1527 * ASC38C1600 Definitions
1528 *
1529 * IOPB_PCI_INT_CFG Bit Field Definitions
1530 */
1531
1532 #define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */
1533
1534 /*
1535 * Bit 1 can be set to change the interrupt for the Function to operate in
1536 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
1537 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
1538 * mode, otherwise the operating mode is undefined.
1539 */
1540 #define TOTEMPOLE 0x02
1541
1542 /*
1543 * Bit 0 can be used to change the Int Pin for the Function. The value is
1544 * 0 by default for both Functions with Function 0 using INT A and Function
1545 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
1546 * INT A is used.
1547 *
1548 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
1549 * value specified in the PCI Configuration Space.
1550 */
1551 #define INTAB 0x01
1552
1553 /*
1554 * Adv Library Status Definitions
1555 */
1556 #define ADV_TRUE 1
1557 #define ADV_FALSE 0
1558 #define ADV_SUCCESS 1
1559 #define ADV_BUSY 0
1560 #define ADV_ERROR (-1)
1561
1562 /*
1563 * ADV_DVC_VAR 'warn_code' values
1564 */
1565 #define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */
1566 #define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */
1567 #define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */
1568 #define ASC_WARN_ERROR 0xFFFF /* ADV_ERROR return */
1569
1570 #define ADV_MAX_TID 15 /* max. target identifier */
1571 #define ADV_MAX_LUN 7 /* max. logical unit number */
1572
1573 /*
1574 * Fixed locations of microcode operating variables.
1575 */
1576 #define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */
1577 #define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */
1578 #define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */
1579 #define ASC_MC_VERSION_DATE 0x0038 /* microcode version */
1580 #define ASC_MC_VERSION_NUM 0x003A /* microcode number */
1581 #define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
1582 #define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
1583 #define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */
1584 #define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */
1585 #define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */
1586 #define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */
1587 #define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */
1588 #define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */
1589 #define ASC_MC_CHIP_TYPE 0x009A
1590 #define ASC_MC_INTRB_CODE 0x009B
1591 #define ASC_MC_WDTR_ABLE 0x009C
1592 #define ASC_MC_SDTR_ABLE 0x009E
1593 #define ASC_MC_TAGQNG_ABLE 0x00A0
1594 #define ASC_MC_DISC_ENABLE 0x00A2
1595 #define ASC_MC_IDLE_CMD_STATUS 0x00A4
1596 #define ASC_MC_IDLE_CMD 0x00A6
1597 #define ASC_MC_IDLE_CMD_PARAMETER 0x00A8
1598 #define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC
1599 #define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE
1600 #define ASC_MC_DEFAULT_MEM_CFG 0x00B0
1601 #define ASC_MC_DEFAULT_SEL_MASK 0x00B2
1602 #define ASC_MC_SDTR_DONE 0x00B6
1603 #define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0
1604 #define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0
1605 #define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100
1606 #define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */
1607 #define ASC_MC_WDTR_DONE 0x0124
1608 #define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */
1609 #define ASC_MC_ICQ 0x0160
1610 #define ASC_MC_IRQ 0x0164
1611 #define ASC_MC_PPR_ABLE 0x017A
1612
1613 /*
1614 * BIOS LRAM variable absolute offsets.
1615 */
1616 #define BIOS_CODESEG 0x54
1617 #define BIOS_CODELEN 0x56
1618 #define BIOS_SIGNATURE 0x58
1619 #define BIOS_VERSION 0x5A
1620
1621 /*
1622 * Microcode Control Flags
1623 *
1624 * Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
1625 * and handled by the microcode.
1626 */
1627 #define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */
1628 #define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */
1629
1630 /*
1631 * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
1632 */
1633 #define HSHK_CFG_WIDE_XFR 0x8000
1634 #define HSHK_CFG_RATE 0x0F00
1635 #define HSHK_CFG_OFFSET 0x001F
1636
1637 #define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */
1638 #define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */
1639 #define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */
1640 #define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */
1641
1642 #define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */
1643 #define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */
1644 #define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
1645 #define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */
1646 #define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
1647
1648 #define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */
1649 #define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */
1650 #define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */
1651 #define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */
1652 #define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */
1653 /*
1654 * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
1655 * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
1656 */
1657 #define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */
1658 #define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */
1659
1660 /*
1661 * All fields here are accessed by the board microcode and need to be
1662 * little-endian.
1663 */
1664 typedef struct adv_carr_t {
1665 __le32 carr_va; /* Carrier Virtual Address */
1666 __le32 carr_pa; /* Carrier Physical Address */
1667 __le32 areq_vpa; /* ADV_SCSI_REQ_Q Virtual or Physical Address */
1668 /*
1669 * next_vpa [31:4] Carrier Virtual or Physical Next Pointer
1670 *
1671 * next_vpa [3:1] Reserved Bits
1672 * next_vpa [0] Done Flag set in Response Queue.
1673 */
1674 __le32 next_vpa;
1675 } ADV_CARR_T;
1676
1677 /*
1678 * Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
1679 */
1680 #define ADV_NEXT_VPA_MASK 0xFFFFFFF0
1681
1682 #define ADV_RQ_DONE 0x00000001
1683 #define ADV_RQ_GOOD 0x00000002
1684 #define ADV_CQ_STOPPER 0x00000000
1685
1686 #define ADV_GET_CARRP(carrp) ((carrp) & ADV_NEXT_VPA_MASK)
1687
1688 /*
1689 * Each carrier is 64 bytes, and we need three additional
1690 * carrier for icq, irq, and the termination carrier.
1691 */
1692 #define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 3)
1693
1694 #define ADV_CARRIER_BUFSIZE \
1695 (ADV_CARRIER_COUNT * sizeof(ADV_CARR_T))
1696
1697 #define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */
1698 #define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */
1699 #define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */
1700
1701 /*
1702 * Adapter temporary configuration structure
1703 *
1704 * This structure can be discarded after initialization. Don't add
1705 * fields here needed after initialization.
1706 *
1707 * Field naming convention:
1708 *
1709 * *_enable indicates the field enables or disables a feature. The
1710 * value of the field is never reset.
1711 */
1712 typedef struct adv_dvc_cfg {
1713 ushort disc_enable; /* enable disconnection */
1714 uchar chip_version; /* chip version */
1715 uchar termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
1716 ushort control_flag; /* Microcode Control Flag */
1717 ushort mcode_date; /* Microcode date */
1718 ushort mcode_version; /* Microcode version */
1719 ushort serial1; /* EEPROM serial number word 1 */
1720 ushort serial2; /* EEPROM serial number word 2 */
1721 ushort serial3; /* EEPROM serial number word 3 */
1722 } ADV_DVC_CFG;
1723
1724 struct adv_dvc_var;
1725 struct adv_scsi_req_q;
1726
1727 typedef struct adv_sg_block {
1728 uchar reserved1;
1729 uchar reserved2;
1730 uchar reserved3;
1731 uchar sg_cnt; /* Valid entries in block. */
1732 __le32 sg_ptr; /* Pointer to next sg block. */
1733 struct {
1734 __le32 sg_addr; /* SG element address. */
1735 __le32 sg_count; /* SG element count. */
1736 } sg_list[NO_OF_SG_PER_BLOCK];
1737 } ADV_SG_BLOCK;
1738
1739 /*
1740 * ADV_SCSI_REQ_Q - microcode request structure
1741 *
1742 * All fields in this structure up to byte 60 are used by the microcode.
1743 * The microcode makes assumptions about the size and ordering of fields
1744 * in this structure. Do not change the structure definition here without
1745 * coordinating the change with the microcode.
1746 *
1747 * All fields accessed by microcode must be maintained in little_endian
1748 * order.
1749 */
1750 typedef struct adv_scsi_req_q {
1751 uchar cntl; /* Ucode flags and state (ASC_MC_QC_*). */
1752 uchar target_cmd;
1753 uchar target_id; /* Device target identifier. */
1754 uchar target_lun; /* Device target logical unit number. */
1755 __le32 data_addr; /* Data buffer physical address. */
1756 __le32 data_cnt; /* Data count. Ucode sets to residual. */
1757 __le32 sense_addr;
1758 __le32 carr_pa;
1759 uchar mflag;
1760 uchar sense_len;
1761 uchar cdb_len; /* SCSI CDB length. Must <= 16 bytes. */
1762 uchar scsi_cntl;
1763 uchar done_status; /* Completion status. */
1764 uchar scsi_status; /* SCSI status byte. */
1765 uchar host_status; /* Ucode host status. */
1766 uchar sg_working_ix;
1767 uchar cdb[12]; /* SCSI CDB bytes 0-11. */
1768 __le32 sg_real_addr; /* SG list physical address. */
1769 __le32 scsiq_rptr;
1770 uchar cdb16[4]; /* SCSI CDB bytes 12-15. */
1771 __le32 scsiq_ptr;
1772 __le32 carr_va;
1773 /*
1774 * End of microcode structure - 60 bytes. The rest of the structure
1775 * is used by the Adv Library and ignored by the microcode.
1776 */
1777 u32 srb_tag;
1778 ADV_SG_BLOCK *sg_list_ptr; /* SG list virtual address. */
1779 } ADV_SCSI_REQ_Q;
1780
1781 /*
1782 * The following two structures are used to process Wide Board requests.
1783 *
1784 * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
1785 * and microcode with the ADV_SCSI_REQ_Q field 'srb_tag' set to the
1786 * SCSI request tag. The adv_req_t structure 'cmndp' field in turn points
1787 * to the Mid-Level SCSI request structure.
1788 *
1789 * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
1790 * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
1791 * up to 255 scatter-gather elements may be used per request or
1792 * ADV_SCSI_REQ_Q.
1793 *
1794 * Both structures must be 32 byte aligned.
1795 */
1796 typedef struct adv_sgblk {
1797 ADV_SG_BLOCK sg_block; /* Sgblock structure. */
1798 dma_addr_t sg_addr; /* Physical address */
1799 struct adv_sgblk *next_sgblkp; /* Next scatter-gather structure. */
1800 } adv_sgblk_t;
1801
1802 typedef struct adv_req {
1803 ADV_SCSI_REQ_Q scsi_req_q; /* Adv Library request structure. */
1804 uchar align[24]; /* Request structure padding. */
1805 struct scsi_cmnd *cmndp; /* Mid-Level SCSI command pointer. */
1806 dma_addr_t req_addr;
1807 adv_sgblk_t *sgblkp; /* Adv Library scatter-gather pointer. */
1808 } adv_req_t __aligned(32);
1809
1810 /*
1811 * Adapter operation variable structure.
1812 *
1813 * One structure is required per host adapter.
1814 *
1815 * Field naming convention:
1816 *
1817 * *_able indicates both whether a feature should be enabled or disabled
1818 * and whether a device isi capable of the feature. At initialization
1819 * this field may be set, but later if a device is found to be incapable
1820 * of the feature, the field is cleared.
1821 */
1822 typedef struct adv_dvc_var {
1823 AdvPortAddr iop_base; /* I/O port address */
1824 ushort err_code; /* fatal error code */
1825 ushort bios_ctrl; /* BIOS control word, EEPROM word 12 */
1826 ushort wdtr_able; /* try WDTR for a device */
1827 ushort sdtr_able; /* try SDTR for a device */
1828 ushort ultra_able; /* try SDTR Ultra speed for a device */
1829 ushort sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */
1830 ushort sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */
1831 ushort sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */
1832 ushort sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */
1833 ushort tagqng_able; /* try tagged queuing with a device */
1834 ushort ppr_able; /* PPR message capable per TID bitmask. */
1835 uchar max_dvc_qng; /* maximum number of tagged commands per device */
1836 ushort start_motor; /* start motor command allowed */
1837 uchar scsi_reset_wait; /* delay in seconds after scsi bus reset */
1838 uchar chip_no; /* should be assigned by caller */
1839 uchar max_host_qng; /* maximum number of Q'ed command allowed */
1840 ushort no_scam; /* scam_tolerant of EEPROM */
1841 struct asc_board *drv_ptr; /* driver pointer to private structure */
1842 uchar chip_scsi_id; /* chip SCSI target ID */
1843 uchar chip_type;
1844 uchar bist_err_code;
1845 ADV_CARR_T *carrier;
1846 ADV_CARR_T *carr_freelist; /* Carrier free list. */
1847 dma_addr_t carrier_addr;
1848 ADV_CARR_T *icq_sp; /* Initiator command queue stopper pointer. */
1849 ADV_CARR_T *irq_sp; /* Initiator response queue stopper pointer. */
1850 ushort carr_pending_cnt; /* Count of pending carriers. */
1851 /*
1852 * Note: The following fields will not be used after initialization. The
1853 * driver may discard the buffer after initialization is done.
1854 */
1855 ADV_DVC_CFG *cfg; /* temporary configuration structure */
1856 } ADV_DVC_VAR;
1857
1858 /*
1859 * Microcode idle loop commands
1860 */
1861 #define IDLE_CMD_COMPLETED 0
1862 #define IDLE_CMD_STOP_CHIP 0x0001
1863 #define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002
1864 #define IDLE_CMD_SEND_INT 0x0004
1865 #define IDLE_CMD_ABORT 0x0008
1866 #define IDLE_CMD_DEVICE_RESET 0x0010
1867 #define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */
1868 #define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */
1869 #define IDLE_CMD_SCSIREQ 0x0080
1870
1871 #define IDLE_CMD_STATUS_SUCCESS 0x0001
1872 #define IDLE_CMD_STATUS_FAILURE 0x0002
1873
1874 /*
1875 * AdvSendIdleCmd() flag definitions.
1876 */
1877 #define ADV_NOWAIT 0x01
1878
1879 /*
1880 * Wait loop time out values.
1881 */
1882 #define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */
1883 #define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */
1884 #define SCSI_MAX_RETRY 10 /* retry count */
1885
1886 #define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */
1887 #define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */
1888 #define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */
1889 #define ADV_RDMA_IN_CARR_AND_Q_INVALID 0x04 /* RDMAed-in data invalid. */
1890
1891 #define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */
1892
1893 /* Read byte from a register. */
1894 #define AdvReadByteRegister(iop_base, reg_off) \
1895 (ADV_MEM_READB((iop_base) + (reg_off)))
1896
1897 /* Write byte to a register. */
1898 #define AdvWriteByteRegister(iop_base, reg_off, byte) \
1899 (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
1900
1901 /* Read word (2 bytes) from a register. */
1902 #define AdvReadWordRegister(iop_base, reg_off) \
1903 (ADV_MEM_READW((iop_base) + (reg_off)))
1904
1905 /* Write word (2 bytes) to a register. */
1906 #define AdvWriteWordRegister(iop_base, reg_off, word) \
1907 (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
1908
1909 /* Write dword (4 bytes) to a register. */
1910 #define AdvWriteDWordRegister(iop_base, reg_off, dword) \
1911 (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
1912
1913 /* Read byte from LRAM. */
1914 #define AdvReadByteLram(iop_base, addr, byte) \
1915 do { \
1916 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
1917 (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
1918 } while (0)
1919
1920 /* Write byte to LRAM. */
1921 #define AdvWriteByteLram(iop_base, addr, byte) \
1922 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
1923 ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
1924
1925 /* Read word (2 bytes) from LRAM. */
1926 #define AdvReadWordLram(iop_base, addr, word) \
1927 do { \
1928 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
1929 (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
1930 } while (0)
1931
1932 /* Write word (2 bytes) to LRAM. */
1933 #define AdvWriteWordLram(iop_base, addr, word) \
1934 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
1935 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
1936
1937 /* Write little-endian double word (4 bytes) to LRAM */
1938 /* Because of unspecified C language ordering don't use auto-increment. */
1939 #define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
1940 ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
1941 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
1942 cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
1943 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
1944 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
1945 cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
1946
1947 /* Read word (2 bytes) from LRAM assuming that the address is already set. */
1948 #define AdvReadWordAutoIncLram(iop_base) \
1949 (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
1950
1951 /* Write word (2 bytes) to LRAM assuming that the address is already set. */
1952 #define AdvWriteWordAutoIncLram(iop_base, word) \
1953 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
1954
1955 /*
1956 * Define macro to check for Condor signature.
1957 *
1958 * Evaluate to ADV_TRUE if a Condor chip is found the specified port
1959 * address 'iop_base'. Otherwise evalue to ADV_FALSE.
1960 */
1961 #define AdvFindSignature(iop_base) \
1962 (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
1963 ADV_CHIP_ID_BYTE) && \
1964 (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
1965 ADV_CHIP_ID_WORD)) ? ADV_TRUE : ADV_FALSE)
1966
1967 /*
1968 * Define macro to Return the version number of the chip at 'iop_base'.
1969 *
1970 * The second parameter 'bus_type' is currently unused.
1971 */
1972 #define AdvGetChipVersion(iop_base, bus_type) \
1973 AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
1974
1975 /*
1976 * Abort an SRB in the chip's RISC Memory. The 'srb_tag' argument must
1977 * match the ADV_SCSI_REQ_Q 'srb_tag' field.
1978 *
1979 * If the request has not yet been sent to the device it will simply be
1980 * aborted from RISC memory. If the request is disconnected it will be
1981 * aborted on reselection by sending an Abort Message to the target ID.
1982 *
1983 * Return value:
1984 * ADV_TRUE(1) - Queue was successfully aborted.
1985 * ADV_FALSE(0) - Queue was not found on the active queue list.
1986 */
1987 #define AdvAbortQueue(asc_dvc, srb_tag) \
1988 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
1989 (ADV_DCNT) (srb_tag))
1990
1991 /*
1992 * Send a Bus Device Reset Message to the specified target ID.
1993 *
1994 * All outstanding commands will be purged if sending the
1995 * Bus Device Reset Message is successful.
1996 *
1997 * Return Value:
1998 * ADV_TRUE(1) - All requests on the target are purged.
1999 * ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
2000 * are not purged.
2001 */
2002 #define AdvResetDevice(asc_dvc, target_id) \
2003 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
2004 (ADV_DCNT) (target_id))
2005
2006 /*
2007 * SCSI Wide Type definition.
2008 */
2009 #define ADV_SCSI_BIT_ID_TYPE ushort
2010
2011 /*
2012 * AdvInitScsiTarget() 'cntl_flag' options.
2013 */
2014 #define ADV_SCAN_LUN 0x01
2015 #define ADV_CAPINFO_NOLUN 0x02
2016
2017 /*
2018 * Convert target id to target id bit mask.
2019 */
2020 #define ADV_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADV_MAX_TID))
2021
2022 /*
2023 * ADV_SCSI_REQ_Q 'done_status' and 'host_status' return values.
2024 */
2025
2026 #define QD_NO_STATUS 0x00 /* Request not completed yet. */
2027 #define QD_NO_ERROR 0x01
2028 #define QD_ABORTED_BY_HOST 0x02
2029 #define QD_WITH_ERROR 0x04
2030
2031 #define QHSTA_NO_ERROR 0x00
2032 #define QHSTA_M_SEL_TIMEOUT 0x11
2033 #define QHSTA_M_DATA_OVER_RUN 0x12
2034 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
2035 #define QHSTA_M_QUEUE_ABORTED 0x15
2036 #define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */
2037 #define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */
2038 #define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */
2039 #define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */
2040 #define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */
2041 #define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */
2042 #define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */
2043 /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
2044 #define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */
2045 #define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */
2046 #define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */
2047 #define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */
2048 #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */
2049 #define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */
2050 #define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */
2051 #define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */
2052 #define QHSTA_M_WTM_TIMEOUT 0x41
2053 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
2054 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
2055 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
2056 #define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */
2057 #define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */
2058 #define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */
2059
2060 /* Return the address that is aligned at the next doubleword >= to 'addr'. */
2061 #define ADV_32BALIGN(addr) (((ulong) (addr) + 0x1F) & ~0x1F)
2062
2063 /*
2064 * Total contiguous memory needed for driver SG blocks.
2065 *
2066 * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
2067 * number of scatter-gather elements the driver supports in a
2068 * single request.
2069 */
2070
2071 #define ADV_SG_LIST_MAX_BYTE_SIZE \
2072 (sizeof(ADV_SG_BLOCK) * \
2073 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
2074
2075 /* struct asc_board flags */
2076 #define ASC_IS_WIDE_BOARD 0x04 /* AdvanSys Wide Board */
2077
2078 #define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
2079
2080 #define NO_ISA_DMA 0xff /* No ISA DMA Channel Used */
2081
2082 #define ASC_INFO_SIZE 128 /* advansys_info() line size */
2083
2084 /* Asc Library return codes */
2085 #define ASC_TRUE 1
2086 #define ASC_FALSE 0
2087 #define ASC_NOERROR 1
2088 #define ASC_BUSY 0
2089 #define ASC_ERROR (-1)
2090
2091 /* struct scsi_cmnd function return codes */
2092 #define STATUS_BYTE(byte) (byte)
2093 #define MSG_BYTE(byte) ((byte) << 8)
2094 #define HOST_BYTE(byte) ((byte) << 16)
2095 #define DRIVER_BYTE(byte) ((byte) << 24)
2096
2097 #define ASC_STATS(shost, counter) ASC_STATS_ADD(shost, counter, 1)
2098 #ifndef ADVANSYS_STATS
2099 #define ASC_STATS_ADD(shost, counter, count)
2100 #else /* ADVANSYS_STATS */
2101 #define ASC_STATS_ADD(shost, counter, count) \
2102 (((struct asc_board *) shost_priv(shost))->asc_stats.counter += (count))
2103 #endif /* ADVANSYS_STATS */
2104
2105 /* If the result wraps when calculating tenths, return 0. */
2106 #define ASC_TENTHS(num, den) \
2107 (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
2108 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
2109
2110 /*
2111 * Display a message to the console.
2112 */
2113 #define ASC_PRINT(s) \
2114 { \
2115 printk("advansys: "); \
2116 printk(s); \
2117 }
2118
2119 #define ASC_PRINT1(s, a1) \
2120 { \
2121 printk("advansys: "); \
2122 printk((s), (a1)); \
2123 }
2124
2125 #define ASC_PRINT2(s, a1, a2) \
2126 { \
2127 printk("advansys: "); \
2128 printk((s), (a1), (a2)); \
2129 }
2130
2131 #define ASC_PRINT3(s, a1, a2, a3) \
2132 { \
2133 printk("advansys: "); \
2134 printk((s), (a1), (a2), (a3)); \
2135 }
2136
2137 #define ASC_PRINT4(s, a1, a2, a3, a4) \
2138 { \
2139 printk("advansys: "); \
2140 printk((s), (a1), (a2), (a3), (a4)); \
2141 }
2142
2143 #ifndef ADVANSYS_DEBUG
2144
2145 #define ASC_DBG(lvl, s...)
2146 #define ASC_DBG_PRT_SCSI_HOST(lvl, s)
2147 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
2148 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2149 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
2150 #define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2151 #define ASC_DBG_PRT_HEX(lvl, name, start, length)
2152 #define ASC_DBG_PRT_CDB(lvl, cdb, len)
2153 #define ASC_DBG_PRT_SENSE(lvl, sense, len)
2154 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
2155
2156 #else /* ADVANSYS_DEBUG */
2157
2158 /*
2159 * Debugging Message Levels:
2160 * 0: Errors Only
2161 * 1: High-Level Tracing
2162 * 2-N: Verbose Tracing
2163 */
2164
2165 #define ASC_DBG(lvl, format, arg...) { \
2166 if (asc_dbglvl >= (lvl)) \
2167 printk(KERN_DEBUG "%s: %s: " format, DRV_NAME, \
2168 __func__ , ## arg); \
2169 }
2170
2171 #define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
2172 { \
2173 if (asc_dbglvl >= (lvl)) { \
2174 asc_prt_scsi_host(s); \
2175 } \
2176 }
2177
2178 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
2179 { \
2180 if (asc_dbglvl >= (lvl)) { \
2181 asc_prt_asc_scsi_q(scsiqp); \
2182 } \
2183 }
2184
2185 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
2186 { \
2187 if (asc_dbglvl >= (lvl)) { \
2188 asc_prt_asc_qdone_info(qdone); \
2189 } \
2190 }
2191
2192 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
2193 { \
2194 if (asc_dbglvl >= (lvl)) { \
2195 asc_prt_adv_scsi_req_q(scsiqp); \
2196 } \
2197 }
2198
2199 #define ASC_DBG_PRT_HEX(lvl, name, start, length) \
2200 { \
2201 if (asc_dbglvl >= (lvl)) { \
2202 asc_prt_hex((name), (start), (length)); \
2203 } \
2204 }
2205
2206 #define ASC_DBG_PRT_CDB(lvl, cdb, len) \
2207 ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
2208
2209 #define ASC_DBG_PRT_SENSE(lvl, sense, len) \
2210 ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
2211
2212 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
2213 ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
2214 #endif /* ADVANSYS_DEBUG */
2215
2216 #ifdef ADVANSYS_STATS
2217
2218 /* Per board statistics structure */
2219 struct asc_stats {
2220 /* Driver Entrypoint Statistics */
2221 unsigned int queuecommand; /* # calls to advansys_queuecommand() */
2222 unsigned int reset; /* # calls to advansys_eh_bus_reset() */
2223 unsigned int biosparam; /* # calls to advansys_biosparam() */
2224 unsigned int interrupt; /* # advansys_interrupt() calls */
2225 unsigned int callback; /* # calls to asc/adv_isr_callback() */
2226 unsigned int done; /* # calls to request's scsi_done function */
2227 unsigned int build_error; /* # asc/adv_build_req() ASC_ERROR returns. */
2228 unsigned int adv_build_noreq; /* # adv_build_req() adv_req_t alloc. fail. */
2229 unsigned int adv_build_nosg; /* # adv_build_req() adv_sgblk_t alloc. fail. */
2230 /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
2231 unsigned int exe_noerror; /* # ASC_NOERROR returns. */
2232 unsigned int exe_busy; /* # ASC_BUSY returns. */
2233 unsigned int exe_error; /* # ASC_ERROR returns. */
2234 unsigned int exe_unknown; /* # unknown returns. */
2235 /* Data Transfer Statistics */
2236 unsigned int xfer_cnt; /* # I/O requests received */
2237 unsigned int xfer_elem; /* # scatter-gather elements */
2238 unsigned int xfer_sect; /* # 512-byte blocks */
2239 };
2240 #endif /* ADVANSYS_STATS */
2241
2242 /*
2243 * Structure allocated for each board.
2244 *
2245 * This structure is allocated by scsi_host_alloc() at the end
2246 * of the 'Scsi_Host' structure starting at the 'hostdata'
2247 * field. It is guaranteed to be allocated from DMA-able memory.
2248 */
2249 struct asc_board {
2250 struct device *dev;
2251 struct Scsi_Host *shost;
2252 uint flags; /* Board flags */
2253 unsigned int irq;
2254 union {
2255 ASC_DVC_VAR asc_dvc_var; /* Narrow board */
2256 ADV_DVC_VAR adv_dvc_var; /* Wide board */
2257 } dvc_var;
2258 union {
2259 ASC_DVC_CFG asc_dvc_cfg; /* Narrow board */
2260 ADV_DVC_CFG adv_dvc_cfg; /* Wide board */
2261 } dvc_cfg;
2262 ushort asc_n_io_port; /* Number I/O ports. */
2263 ADV_SCSI_BIT_ID_TYPE init_tidmask; /* Target init./valid mask */
2264 ushort reqcnt[ADV_MAX_TID + 1]; /* Starvation request count */
2265 ADV_SCSI_BIT_ID_TYPE queue_full; /* Queue full mask */
2266 ushort queue_full_cnt[ADV_MAX_TID + 1]; /* Queue full count */
2267 union {
2268 ASCEEP_CONFIG asc_eep; /* Narrow EEPROM config. */
2269 ADVEEP_3550_CONFIG adv_3550_eep; /* 3550 EEPROM config. */
2270 ADVEEP_38C0800_CONFIG adv_38C0800_eep; /* 38C0800 EEPROM config. */
2271 ADVEEP_38C1600_CONFIG adv_38C1600_eep; /* 38C1600 EEPROM config. */
2272 } eep_config;
2273 /* /proc/scsi/advansys/[0...] */
2274 #ifdef ADVANSYS_STATS
2275 struct asc_stats asc_stats; /* Board statistics */
2276 #endif /* ADVANSYS_STATS */
2277 /*
2278 * The following fields are used only for Narrow Boards.
2279 */
2280 uchar sdtr_data[ASC_MAX_TID + 1]; /* SDTR information */
2281 /*
2282 * The following fields are used only for Wide Boards.
2283 */
2284 void __iomem *ioremap_addr; /* I/O Memory remap address. */
2285 ushort ioport; /* I/O Port address. */
2286 adv_req_t *adv_reqp; /* Request structures. */
2287 dma_addr_t adv_reqp_addr;
2288 size_t adv_reqp_size;
2289 struct dma_pool *adv_sgblk_pool; /* Scatter-gather structures. */
2290 ushort bios_signature; /* BIOS Signature. */
2291 ushort bios_version; /* BIOS Version. */
2292 ushort bios_codeseg; /* BIOS Code Segment. */
2293 ushort bios_codelen; /* BIOS Code Segment Length. */
2294 };
2295
2296 #define asc_dvc_to_board(asc_dvc) container_of(asc_dvc, struct asc_board, \
2297 dvc_var.asc_dvc_var)
2298 #define adv_dvc_to_board(adv_dvc) container_of(adv_dvc, struct asc_board, \
2299 dvc_var.adv_dvc_var)
2300 #define adv_dvc_to_pdev(adv_dvc) to_pci_dev(adv_dvc_to_board(adv_dvc)->dev)
2301
2302 #ifdef ADVANSYS_DEBUG
2303 static int asc_dbglvl = 3;
2304
2305 /*
2306 * asc_prt_asc_dvc_var()
2307 */
2308 static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
2309 {
2310 printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h);
2311
2312 printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl "
2313 "%d,\n", h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
2314
2315 printk(" bus_type %d, init_sdtr 0x%x,\n", h->bus_type,
2316 (unsigned)h->init_sdtr);
2317
2318 printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, "
2319 "chip_no 0x%x,\n", (unsigned)h->sdtr_done,
2320 (unsigned)h->use_tagged_qng, (unsigned)h->unit_not_ready,
2321 (unsigned)h->chip_no);
2322
2323 printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait "
2324 "%u,\n", (unsigned)h->queue_full_or_busy,
2325 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2326
2327 printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, "
2328 "in_critical_cnt %u,\n", (unsigned)h->is_in_int,
2329 (unsigned)h->max_total_qng, (unsigned)h->cur_total_qng,
2330 (unsigned)h->in_critical_cnt);
2331
2332 printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, "
2333 "pci_fix_asyn_xfer 0x%x,\n", (unsigned)h->last_q_shortage,
2334 (unsigned)h->init_state, (unsigned)h->no_scam,
2335 (unsigned)h->pci_fix_asyn_xfer);
2336
2337 printk(" cfg 0x%lx\n", (ulong)h->cfg);
2338 }
2339
2340 /*
2341 * asc_prt_asc_dvc_cfg()
2342 */
2343 static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
2344 {
2345 printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h);
2346
2347 printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
2348 h->can_tagged_qng, h->cmd_qng_enabled);
2349 printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n",
2350 h->disc_enable, h->sdtr_enable);
2351
2352 printk(" chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, "
2353 "chip_version %d,\n", h->chip_scsi_id, h->isa_dma_speed,
2354 h->isa_dma_channel, h->chip_version);
2355
2356 printk(" mcode_date 0x%x, mcode_version %d\n",
2357 h->mcode_date, h->mcode_version);
2358 }
2359
2360 /*
2361 * asc_prt_adv_dvc_var()
2362 *
2363 * Display an ADV_DVC_VAR structure.
2364 */
2365 static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h)
2366 {
2367 printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h);
2368
2369 printk(" iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
2370 (ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able);
2371
2372 printk(" sdtr_able 0x%x, wdtr_able 0x%x\n",
2373 (unsigned)h->sdtr_able, (unsigned)h->wdtr_able);
2374
2375 printk(" start_motor 0x%x, scsi_reset_wait 0x%x\n",
2376 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2377
2378 printk(" max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%p\n",
2379 (unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng,
2380 h->carr_freelist);
2381
2382 printk(" icq_sp 0x%p, irq_sp 0x%p\n", h->icq_sp, h->irq_sp);
2383
2384 printk(" no_scam 0x%x, tagqng_able 0x%x\n",
2385 (unsigned)h->no_scam, (unsigned)h->tagqng_able);
2386
2387 printk(" chip_scsi_id 0x%x, cfg 0x%lx\n",
2388 (unsigned)h->chip_scsi_id, (ulong)h->cfg);
2389 }
2390
2391 /*
2392 * asc_prt_adv_dvc_cfg()
2393 *
2394 * Display an ADV_DVC_CFG structure.
2395 */
2396 static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h)
2397 {
2398 printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h);
2399
2400 printk(" disc_enable 0x%x, termination 0x%x\n",
2401 h->disc_enable, h->termination);
2402
2403 printk(" chip_version 0x%x, mcode_date 0x%x\n",
2404 h->chip_version, h->mcode_date);
2405
2406 printk(" mcode_version 0x%x, control_flag 0x%x\n",
2407 h->mcode_version, h->control_flag);
2408 }
2409
2410 /*
2411 * asc_prt_scsi_host()
2412 */
2413 static void asc_prt_scsi_host(struct Scsi_Host *s)
2414 {
2415 struct asc_board *boardp = shost_priv(s);
2416
2417 printk("Scsi_Host at addr 0x%p, device %s\n", s, dev_name(boardp->dev));
2418 printk(" host_busy %u, host_no %d,\n",
2419 atomic_read(&s->host_busy), s->host_no);
2420
2421 printk(" base 0x%lx, io_port 0x%lx, irq %d,\n",
2422 (ulong)s->base, (ulong)s->io_port, boardp->irq);
2423
2424 printk(" dma_channel %d, this_id %d, can_queue %d,\n",
2425 s->dma_channel, s->this_id, s->can_queue);
2426
2427 printk(" cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n",
2428 s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma);
2429
2430 if (ASC_NARROW_BOARD(boardp)) {
2431 asc_prt_asc_dvc_var(&boardp->dvc_var.asc_dvc_var);
2432 asc_prt_asc_dvc_cfg(&boardp->dvc_cfg.asc_dvc_cfg);
2433 } else {
2434 asc_prt_adv_dvc_var(&boardp->dvc_var.adv_dvc_var);
2435 asc_prt_adv_dvc_cfg(&boardp->dvc_cfg.adv_dvc_cfg);
2436 }
2437 }
2438
2439 /*
2440 * asc_prt_hex()
2441 *
2442 * Print hexadecimal output in 4 byte groupings 32 bytes
2443 * or 8 double-words per line.
2444 */
2445 static void asc_prt_hex(char *f, uchar *s, int l)
2446 {
2447 int i;
2448 int j;
2449 int k;
2450 int m;
2451
2452 printk("%s: (%d bytes)\n", f, l);
2453
2454 for (i = 0; i < l; i += 32) {
2455
2456 /* Display a maximum of 8 double-words per line. */
2457 if ((k = (l - i) / 4) >= 8) {
2458 k = 8;
2459 m = 0;
2460 } else {
2461 m = (l - i) % 4;
2462 }
2463
2464 for (j = 0; j < k; j++) {
2465 printk(" %2.2X%2.2X%2.2X%2.2X",
2466 (unsigned)s[i + (j * 4)],
2467 (unsigned)s[i + (j * 4) + 1],
2468 (unsigned)s[i + (j * 4) + 2],
2469 (unsigned)s[i + (j * 4) + 3]);
2470 }
2471
2472 switch (m) {
2473 case 0:
2474 default:
2475 break;
2476 case 1:
2477 printk(" %2.2X", (unsigned)s[i + (j * 4)]);
2478 break;
2479 case 2:
2480 printk(" %2.2X%2.2X",
2481 (unsigned)s[i + (j * 4)],
2482 (unsigned)s[i + (j * 4) + 1]);
2483 break;
2484 case 3:
2485 printk(" %2.2X%2.2X%2.2X",
2486 (unsigned)s[i + (j * 4) + 1],
2487 (unsigned)s[i + (j * 4) + 2],
2488 (unsigned)s[i + (j * 4) + 3]);
2489 break;
2490 }
2491
2492 printk("\n");
2493 }
2494 }
2495
2496 /*
2497 * asc_prt_asc_scsi_q()
2498 */
2499 static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q)
2500 {
2501 ASC_SG_HEAD *sgp;
2502 int i;
2503
2504 printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q);
2505
2506 printk
2507 (" target_ix 0x%x, target_lun %u, srb_tag 0x%x, tag_code 0x%x,\n",
2508 q->q2.target_ix, q->q1.target_lun, q->q2.srb_tag,
2509 q->q2.tag_code);
2510
2511 printk
2512 (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2513 (ulong)le32_to_cpu(q->q1.data_addr),
2514 (ulong)le32_to_cpu(q->q1.data_cnt),
2515 (ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len);
2516
2517 printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
2518 (ulong)q->cdbptr, q->q2.cdb_len,
2519 (ulong)q->sg_head, q->q1.sg_queue_cnt);
2520
2521 if (q->sg_head) {
2522 sgp = q->sg_head;
2523 printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp);
2524 printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt,
2525 sgp->queue_cnt);
2526 for (i = 0; i < sgp->entry_cnt; i++) {
2527 printk(" [%u]: addr 0x%lx, bytes %lu\n",
2528 i, (ulong)le32_to_cpu(sgp->sg_list[i].addr),
2529 (ulong)le32_to_cpu(sgp->sg_list[i].bytes));
2530 }
2531
2532 }
2533 }
2534
2535 /*
2536 * asc_prt_asc_qdone_info()
2537 */
2538 static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
2539 {
2540 printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q);
2541 printk(" srb_tag 0x%x, target_ix %u, cdb_len %u, tag_code %u,\n",
2542 q->d2.srb_tag, q->d2.target_ix, q->d2.cdb_len,
2543 q->d2.tag_code);
2544 printk
2545 (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
2546 q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg);
2547 }
2548
2549 /*
2550 * asc_prt_adv_sgblock()
2551 *
2552 * Display an ADV_SG_BLOCK structure.
2553 */
2554 static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b)
2555 {
2556 int i;
2557
2558 printk(" ADV_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
2559 (ulong)b, sgblockno);
2560 printk(" sg_cnt %u, sg_ptr 0x%x\n",
2561 b->sg_cnt, (u32)le32_to_cpu(b->sg_ptr));
2562 BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK);
2563 if (b->sg_ptr != 0)
2564 BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK);
2565 for (i = 0; i < b->sg_cnt; i++) {
2566 printk(" [%u]: sg_addr 0x%x, sg_count 0x%x\n",
2567 i, (u32)le32_to_cpu(b->sg_list[i].sg_addr),
2568 (u32)le32_to_cpu(b->sg_list[i].sg_count));
2569 }
2570 }
2571
2572 /*
2573 * asc_prt_adv_scsi_req_q()
2574 *
2575 * Display an ADV_SCSI_REQ_Q structure.
2576 */
2577 static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q)
2578 {
2579 int sg_blk_cnt;
2580 struct adv_sg_block *sg_ptr;
2581 adv_sgblk_t *sgblkp;
2582
2583 printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q);
2584
2585 printk(" target_id %u, target_lun %u, srb_tag 0x%x\n",
2586 q->target_id, q->target_lun, q->srb_tag);
2587
2588 printk(" cntl 0x%x, data_addr 0x%lx\n",
2589 q->cntl, (ulong)le32_to_cpu(q->data_addr));
2590
2591 printk(" data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2592 (ulong)le32_to_cpu(q->data_cnt),
2593 (ulong)le32_to_cpu(q->sense_addr), q->sense_len);
2594
2595 printk
2596 (" cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
2597 q->cdb_len, q->done_status, q->host_status, q->scsi_status);
2598
2599 printk(" sg_working_ix 0x%x, target_cmd %u\n",
2600 q->sg_working_ix, q->target_cmd);
2601
2602 printk(" scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
2603 (ulong)le32_to_cpu(q->scsiq_rptr),
2604 (ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr);
2605
2606 /* Display the request's ADV_SG_BLOCK structures. */
2607 if (q->sg_list_ptr != NULL) {
2608 sgblkp = container_of(q->sg_list_ptr, adv_sgblk_t, sg_block);
2609 sg_blk_cnt = 0;
2610 while (sgblkp) {
2611 sg_ptr = &sgblkp->sg_block;
2612 asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
2613 if (sg_ptr->sg_ptr == 0) {
2614 break;
2615 }
2616 sgblkp = sgblkp->next_sgblkp;
2617 sg_blk_cnt++;
2618 }
2619 }
2620 }
2621 #endif /* ADVANSYS_DEBUG */
2622
2623 /*
2624 * advansys_info()
2625 *
2626 * Return suitable for printing on the console with the argument
2627 * adapter's configuration information.
2628 *
2629 * Note: The information line should not exceed ASC_INFO_SIZE bytes,
2630 * otherwise the static 'info' array will be overrun.
2631 */
2632 static const char *advansys_info(struct Scsi_Host *shost)
2633 {
2634 static char info[ASC_INFO_SIZE];
2635 struct asc_board *boardp = shost_priv(shost);
2636 ASC_DVC_VAR *asc_dvc_varp;
2637 ADV_DVC_VAR *adv_dvc_varp;
2638 char *busname;
2639 char *widename = NULL;
2640
2641 if (ASC_NARROW_BOARD(boardp)) {
2642 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
2643 ASC_DBG(1, "begin\n");
2644 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
2645 if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) ==
2646 ASC_IS_ISAPNP) {
2647 busname = "ISA PnP";
2648 } else {
2649 busname = "ISA";
2650 }
2651 sprintf(info,
2652 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X",
2653 ASC_VERSION, busname,
2654 (ulong)shost->io_port,
2655 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2656 boardp->irq, shost->dma_channel);
2657 } else {
2658 if (asc_dvc_varp->bus_type & ASC_IS_VL) {
2659 busname = "VL";
2660 } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) {
2661 busname = "EISA";
2662 } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
2663 if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
2664 == ASC_IS_PCI_ULTRA) {
2665 busname = "PCI Ultra";
2666 } else {
2667 busname = "PCI";
2668 }
2669 } else {
2670 busname = "?";
2671 shost_printk(KERN_ERR, shost, "unknown bus "
2672 "type %d\n", asc_dvc_varp->bus_type);
2673 }
2674 sprintf(info,
2675 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
2676 ASC_VERSION, busname, (ulong)shost->io_port,
2677 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2678 boardp->irq);
2679 }
2680 } else {
2681 /*
2682 * Wide Adapter Information
2683 *
2684 * Memory-mapped I/O is used instead of I/O space to access
2685 * the adapter, but display the I/O Port range. The Memory
2686 * I/O address is displayed through the driver /proc file.
2687 */
2688 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
2689 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2690 widename = "Ultra-Wide";
2691 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
2692 widename = "Ultra2-Wide";
2693 } else {
2694 widename = "Ultra3-Wide";
2695 }
2696 sprintf(info,
2697 "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
2698 ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base,
2699 (ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, boardp->irq);
2700 }
2701 BUG_ON(strlen(info) >= ASC_INFO_SIZE);
2702 ASC_DBG(1, "end\n");
2703 return info;
2704 }
2705
2706 #ifdef CONFIG_PROC_FS
2707
2708 /*
2709 * asc_prt_board_devices()
2710 *
2711 * Print driver information for devices attached to the board.
2712 */
2713 static void asc_prt_board_devices(struct seq_file *m, struct Scsi_Host *shost)
2714 {
2715 struct asc_board *boardp = shost_priv(shost);
2716 int chip_scsi_id;
2717 int i;
2718
2719 seq_printf(m,
2720 "\nDevice Information for AdvanSys SCSI Host %d:\n",
2721 shost->host_no);
2722
2723 if (ASC_NARROW_BOARD(boardp)) {
2724 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
2725 } else {
2726 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
2727 }
2728
2729 seq_puts(m, "Target IDs Detected:");
2730 for (i = 0; i <= ADV_MAX_TID; i++) {
2731 if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i))
2732 seq_printf(m, " %X,", i);
2733 }
2734 seq_printf(m, " (%X=Host Adapter)\n", chip_scsi_id);
2735 }
2736
2737 /*
2738 * Display Wide Board BIOS Information.
2739 */
2740 static void asc_prt_adv_bios(struct seq_file *m, struct Scsi_Host *shost)
2741 {
2742 struct asc_board *boardp = shost_priv(shost);
2743 ushort major, minor, letter;
2744
2745 seq_puts(m, "\nROM BIOS Version: ");
2746
2747 /*
2748 * If the BIOS saved a valid signature, then fill in
2749 * the BIOS code segment base address.
2750 */
2751 if (boardp->bios_signature != 0x55AA) {
2752 seq_puts(m, "Disabled or Pre-3.1\n"
2753 "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n"
2754 "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
2755 } else {
2756 major = (boardp->bios_version >> 12) & 0xF;
2757 minor = (boardp->bios_version >> 8) & 0xF;
2758 letter = (boardp->bios_version & 0xFF);
2759
2760 seq_printf(m, "%d.%d%c\n",
2761 major, minor,
2762 letter >= 26 ? '?' : letter + 'A');
2763 /*
2764 * Current available ROM BIOS release is 3.1I for UW
2765 * and 3.2I for U2W. This code doesn't differentiate
2766 * UW and U2W boards.
2767 */
2768 if (major < 3 || (major <= 3 && minor < 1) ||
2769 (major <= 3 && minor <= 1 && letter < ('I' - 'A'))) {
2770 seq_puts(m, "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n"
2771 "ftp://ftp.connectcom.net/pub\n");
2772 }
2773 }
2774 }
2775
2776 /*
2777 * Add serial number to information bar if signature AAh
2778 * is found in at bit 15-9 (7 bits) of word 1.
2779 *
2780 * Serial Number consists fo 12 alpha-numeric digits.
2781 *
2782 * 1 - Product type (A,B,C,D..) Word0: 15-13 (3 bits)
2783 * 2 - MFG Location (A,B,C,D..) Word0: 12-10 (3 bits)
2784 * 3-4 - Product ID (0-99) Word0: 9-0 (10 bits)
2785 * 5 - Product revision (A-J) Word0: " "
2786 *
2787 * Signature Word1: 15-9 (7 bits)
2788 * 6 - Year (0-9) Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
2789 * 7-8 - Week of the year (1-52) Word1: 5-0 (6 bits)
2790 *
2791 * 9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
2792 *
2793 * Note 1: Only production cards will have a serial number.
2794 *
2795 * Note 2: Signature is most significant 7 bits (0xFE).
2796 *
2797 * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
2798 */
2799 static int asc_get_eeprom_string(ushort *serialnum, uchar *cp)
2800 {
2801 ushort w, num;
2802
2803 if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) {
2804 return ASC_FALSE;
2805 } else {
2806 /*
2807 * First word - 6 digits.
2808 */
2809 w = serialnum[0];
2810
2811 /* Product type - 1st digit. */
2812 if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') {
2813 /* Product type is P=Prototype */
2814 *cp += 0x8;
2815 }
2816 cp++;
2817
2818 /* Manufacturing location - 2nd digit. */
2819 *cp++ = 'A' + ((w & 0x1C00) >> 10);
2820
2821 /* Product ID - 3rd, 4th digits. */
2822 num = w & 0x3FF;
2823 *cp++ = '0' + (num / 100);
2824 num %= 100;
2825 *cp++ = '0' + (num / 10);
2826
2827 /* Product revision - 5th digit. */
2828 *cp++ = 'A' + (num % 10);
2829
2830 /*
2831 * Second word
2832 */
2833 w = serialnum[1];
2834
2835 /*
2836 * Year - 6th digit.
2837 *
2838 * If bit 15 of third word is set, then the
2839 * last digit of the year is greater than 7.
2840 */
2841 if (serialnum[2] & 0x8000) {
2842 *cp++ = '8' + ((w & 0x1C0) >> 6);
2843 } else {
2844 *cp++ = '0' + ((w & 0x1C0) >> 6);
2845 }
2846
2847 /* Week of year - 7th, 8th digits. */
2848 num = w & 0x003F;
2849 *cp++ = '0' + num / 10;
2850 num %= 10;
2851 *cp++ = '0' + num;
2852
2853 /*
2854 * Third word
2855 */
2856 w = serialnum[2] & 0x7FFF;
2857
2858 /* Serial number - 9th digit. */
2859 *cp++ = 'A' + (w / 1000);
2860
2861 /* 10th, 11th, 12th digits. */
2862 num = w % 1000;
2863 *cp++ = '0' + num / 100;
2864 num %= 100;
2865 *cp++ = '0' + num / 10;
2866 num %= 10;
2867 *cp++ = '0' + num;
2868
2869 *cp = '\0'; /* Null Terminate the string. */
2870 return ASC_TRUE;
2871 }
2872 }
2873
2874 /*
2875 * asc_prt_asc_board_eeprom()
2876 *
2877 * Print board EEPROM configuration.
2878 */
2879 static void asc_prt_asc_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
2880 {
2881 struct asc_board *boardp = shost_priv(shost);
2882 ASC_DVC_VAR *asc_dvc_varp;
2883 ASCEEP_CONFIG *ep;
2884 int i;
2885 #ifdef CONFIG_ISA
2886 int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 };
2887 #endif /* CONFIG_ISA */
2888 uchar serialstr[13];
2889
2890 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
2891 ep = &boardp->eep_config.asc_eep;
2892
2893 seq_printf(m,
2894 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
2895 shost->host_no);
2896
2897 if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr)
2898 == ASC_TRUE)
2899 seq_printf(m, " Serial Number: %s\n", serialstr);
2900 else if (ep->adapter_info[5] == 0xBB)
2901 seq_puts(m,
2902 " Default Settings Used for EEPROM-less Adapter.\n");
2903 else
2904 seq_puts(m, " Serial Number Signature Not Present.\n");
2905
2906 seq_printf(m,
2907 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
2908 ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng,
2909 ep->max_tag_qng);
2910
2911 seq_printf(m,
2912 " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam);
2913
2914 seq_puts(m, " Target ID: ");
2915 for (i = 0; i <= ASC_MAX_TID; i++)
2916 seq_printf(m, " %d", i);
2917
2918 seq_puts(m, "\n Disconnects: ");
2919 for (i = 0; i <= ASC_MAX_TID; i++)
2920 seq_printf(m, " %c",
2921 (ep->disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2922
2923 seq_puts(m, "\n Command Queuing: ");
2924 for (i = 0; i <= ASC_MAX_TID; i++)
2925 seq_printf(m, " %c",
2926 (ep->use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2927
2928 seq_puts(m, "\n Start Motor: ");
2929 for (i = 0; i <= ASC_MAX_TID; i++)
2930 seq_printf(m, " %c",
2931 (ep->start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2932
2933 seq_puts(m, "\n Synchronous Transfer:");
2934 for (i = 0; i <= ASC_MAX_TID; i++)
2935 seq_printf(m, " %c",
2936 (ep->init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2937 seq_putc(m, '\n');
2938
2939 #ifdef CONFIG_ISA
2940 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
2941 seq_printf(m,
2942 " Host ISA DMA speed: %d MB/S\n",
2943 isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]);
2944 }
2945 #endif /* CONFIG_ISA */
2946 }
2947
2948 /*
2949 * asc_prt_adv_board_eeprom()
2950 *
2951 * Print board EEPROM configuration.
2952 */
2953 static void asc_prt_adv_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
2954 {
2955 struct asc_board *boardp = shost_priv(shost);
2956 ADV_DVC_VAR *adv_dvc_varp;
2957 int i;
2958 char *termstr;
2959 uchar serialstr[13];
2960 ADVEEP_3550_CONFIG *ep_3550 = NULL;
2961 ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL;
2962 ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL;
2963 ushort word;
2964 ushort *wordp;
2965 ushort sdtr_speed = 0;
2966
2967 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
2968 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2969 ep_3550 = &boardp->eep_config.adv_3550_eep;
2970 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
2971 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
2972 } else {
2973 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
2974 }
2975
2976 seq_printf(m,
2977 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
2978 shost->host_no);
2979
2980 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2981 wordp = &ep_3550->serial_number_word1;
2982 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
2983 wordp = &ep_38C0800->serial_number_word1;
2984 } else {
2985 wordp = &ep_38C1600->serial_number_word1;
2986 }
2987
2988 if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE)
2989 seq_printf(m, " Serial Number: %s\n", serialstr);
2990 else
2991 seq_puts(m, " Serial Number Signature Not Present.\n");
2992
2993 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
2994 seq_printf(m,
2995 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
2996 ep_3550->adapter_scsi_id,
2997 ep_3550->max_host_qng, ep_3550->max_dvc_qng);
2998 else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
2999 seq_printf(m,
3000 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3001 ep_38C0800->adapter_scsi_id,
3002 ep_38C0800->max_host_qng,
3003 ep_38C0800->max_dvc_qng);
3004 else
3005 seq_printf(m,
3006 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3007 ep_38C1600->adapter_scsi_id,
3008 ep_38C1600->max_host_qng,
3009 ep_38C1600->max_dvc_qng);
3010 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3011 word = ep_3550->termination;
3012 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3013 word = ep_38C0800->termination_lvd;
3014 } else {
3015 word = ep_38C1600->termination_lvd;
3016 }
3017 switch (word) {
3018 case 1:
3019 termstr = "Low Off/High Off";
3020 break;
3021 case 2:
3022 termstr = "Low Off/High On";
3023 break;
3024 case 3:
3025 termstr = "Low On/High On";
3026 break;
3027 default:
3028 case 0:
3029 termstr = "Automatic";
3030 break;
3031 }
3032
3033 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
3034 seq_printf(m,
3035 " termination: %u (%s), bios_ctrl: 0x%x\n",
3036 ep_3550->termination, termstr,
3037 ep_3550->bios_ctrl);
3038 else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
3039 seq_printf(m,
3040 " termination: %u (%s), bios_ctrl: 0x%x\n",
3041 ep_38C0800->termination_lvd, termstr,
3042 ep_38C0800->bios_ctrl);
3043 else
3044 seq_printf(m,
3045 " termination: %u (%s), bios_ctrl: 0x%x\n",
3046 ep_38C1600->termination_lvd, termstr,
3047 ep_38C1600->bios_ctrl);
3048
3049 seq_puts(m, " Target ID: ");
3050 for (i = 0; i <= ADV_MAX_TID; i++)
3051 seq_printf(m, " %X", i);
3052 seq_putc(m, '\n');
3053
3054 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3055 word = ep_3550->disc_enable;
3056 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3057 word = ep_38C0800->disc_enable;
3058 } else {
3059 word = ep_38C1600->disc_enable;
3060 }
3061 seq_puts(m, " Disconnects: ");
3062 for (i = 0; i <= ADV_MAX_TID; i++)
3063 seq_printf(m, " %c",
3064 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3065 seq_putc(m, '\n');
3066
3067 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3068 word = ep_3550->tagqng_able;
3069 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3070 word = ep_38C0800->tagqng_able;
3071 } else {
3072 word = ep_38C1600->tagqng_able;
3073 }
3074 seq_puts(m, " Command Queuing: ");
3075 for (i = 0; i <= ADV_MAX_TID; i++)
3076 seq_printf(m, " %c",
3077 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3078 seq_putc(m, '\n');
3079
3080 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3081 word = ep_3550->start_motor;
3082 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3083 word = ep_38C0800->start_motor;
3084 } else {
3085 word = ep_38C1600->start_motor;
3086 }
3087 seq_puts(m, " Start Motor: ");
3088 for (i = 0; i <= ADV_MAX_TID; i++)
3089 seq_printf(m, " %c",
3090 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3091 seq_putc(m, '\n');
3092
3093 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3094 seq_puts(m, " Synchronous Transfer:");
3095 for (i = 0; i <= ADV_MAX_TID; i++)
3096 seq_printf(m, " %c",
3097 (ep_3550->sdtr_able & ADV_TID_TO_TIDMASK(i)) ?
3098 'Y' : 'N');
3099 seq_putc(m, '\n');
3100 }
3101
3102 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3103 seq_puts(m, " Ultra Transfer: ");
3104 for (i = 0; i <= ADV_MAX_TID; i++)
3105 seq_printf(m, " %c",
3106 (ep_3550->ultra_able & ADV_TID_TO_TIDMASK(i))
3107 ? 'Y' : 'N');
3108 seq_putc(m, '\n');
3109 }
3110
3111 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3112 word = ep_3550->wdtr_able;
3113 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3114 word = ep_38C0800->wdtr_able;
3115 } else {
3116 word = ep_38C1600->wdtr_able;
3117 }
3118 seq_puts(m, " Wide Transfer: ");
3119 for (i = 0; i <= ADV_MAX_TID; i++)
3120 seq_printf(m, " %c",
3121 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3122 seq_putc(m, '\n');
3123
3124 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 ||
3125 adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600) {
3126 seq_puts(m, " Synchronous Transfer Speed (Mhz):\n ");
3127 for (i = 0; i <= ADV_MAX_TID; i++) {
3128 char *speed_str;
3129
3130 if (i == 0) {
3131 sdtr_speed = adv_dvc_varp->sdtr_speed1;
3132 } else if (i == 4) {
3133 sdtr_speed = adv_dvc_varp->sdtr_speed2;
3134 } else if (i == 8) {
3135 sdtr_speed = adv_dvc_varp->sdtr_speed3;
3136 } else if (i == 12) {
3137 sdtr_speed = adv_dvc_varp->sdtr_speed4;
3138 }
3139 switch (sdtr_speed & ADV_MAX_TID) {
3140 case 0:
3141 speed_str = "Off";
3142 break;
3143 case 1:
3144 speed_str = " 5";
3145 break;
3146 case 2:
3147 speed_str = " 10";
3148 break;
3149 case 3:
3150 speed_str = " 20";
3151 break;
3152 case 4:
3153 speed_str = " 40";
3154 break;
3155 case 5:
3156 speed_str = " 80";
3157 break;
3158 default:
3159 speed_str = "Unk";
3160 break;
3161 }
3162 seq_printf(m, "%X:%s ", i, speed_str);
3163 if (i == 7)
3164 seq_puts(m, "\n ");
3165 sdtr_speed >>= 4;
3166 }
3167 seq_putc(m, '\n');
3168 }
3169 }
3170
3171 /*
3172 * asc_prt_driver_conf()
3173 */
3174 static void asc_prt_driver_conf(struct seq_file *m, struct Scsi_Host *shost)
3175 {
3176 struct asc_board *boardp = shost_priv(shost);
3177 int chip_scsi_id;
3178
3179 seq_printf(m,
3180 "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
3181 shost->host_no);
3182
3183 seq_printf(m,
3184 " host_busy %u, max_id %u, max_lun %llu, max_channel %u\n",
3185 atomic_read(&shost->host_busy), shost->max_id,
3186 shost->max_lun, shost->max_channel);
3187
3188 seq_printf(m,
3189 " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
3190 shost->unique_id, shost->can_queue, shost->this_id,
3191 shost->sg_tablesize, shost->cmd_per_lun);
3192
3193 seq_printf(m,
3194 " unchecked_isa_dma %d, use_clustering %d\n",
3195 shost->unchecked_isa_dma, shost->use_clustering);
3196
3197 seq_printf(m,
3198 " flags 0x%x, last_reset 0x%lx, jiffies 0x%lx, asc_n_io_port 0x%x\n",
3199 boardp->flags, shost->last_reset, jiffies,
3200 boardp->asc_n_io_port);
3201
3202 seq_printf(m, " io_port 0x%lx\n", shost->io_port);
3203
3204 if (ASC_NARROW_BOARD(boardp)) {
3205 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
3206 } else {
3207 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
3208 }
3209 }
3210
3211 /*
3212 * asc_prt_asc_board_info()
3213 *
3214 * Print dynamic board configuration information.
3215 */
3216 static void asc_prt_asc_board_info(struct seq_file *m, struct Scsi_Host *shost)
3217 {
3218 struct asc_board *boardp = shost_priv(shost);
3219 int chip_scsi_id;
3220 ASC_DVC_VAR *v;
3221 ASC_DVC_CFG *c;
3222 int i;
3223 int renegotiate = 0;
3224
3225 v = &boardp->dvc_var.asc_dvc_var;
3226 c = &boardp->dvc_cfg.asc_dvc_cfg;
3227 chip_scsi_id = c->chip_scsi_id;
3228
3229 seq_printf(m,
3230 "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3231 shost->host_no);
3232
3233 seq_printf(m, " chip_version %u, mcode_date 0x%x, "
3234 "mcode_version 0x%x, err_code %u\n",
3235 c->chip_version, c->mcode_date, c->mcode_version,
3236 v->err_code);
3237
3238 /* Current number of commands waiting for the host. */
3239 seq_printf(m,
3240 " Total Command Pending: %d\n", v->cur_total_qng);
3241
3242 seq_puts(m, " Command Queuing:");
3243 for (i = 0; i <= ASC_MAX_TID; i++) {
3244 if ((chip_scsi_id == i) ||
3245 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3246 continue;
3247 }
3248 seq_printf(m, " %X:%c",
3249 i,
3250 (v->use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3251 }
3252
3253 /* Current number of commands waiting for a device. */
3254 seq_puts(m, "\n Command Queue Pending:");
3255 for (i = 0; i <= ASC_MAX_TID; i++) {
3256 if ((chip_scsi_id == i) ||
3257 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3258 continue;
3259 }
3260 seq_printf(m, " %X:%u", i, v->cur_dvc_qng[i]);
3261 }
3262
3263 /* Current limit on number of commands that can be sent to a device. */
3264 seq_puts(m, "\n Command Queue Limit:");
3265 for (i = 0; i <= ASC_MAX_TID; i++) {
3266 if ((chip_scsi_id == i) ||
3267 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3268 continue;
3269 }
3270 seq_printf(m, " %X:%u", i, v->max_dvc_qng[i]);
3271 }
3272
3273 /* Indicate whether the device has returned queue full status. */
3274 seq_puts(m, "\n Command Queue Full:");
3275 for (i = 0; i <= ASC_MAX_TID; i++) {
3276 if ((chip_scsi_id == i) ||
3277 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3278 continue;
3279 }
3280 if (boardp->queue_full & ADV_TID_TO_TIDMASK(i))
3281 seq_printf(m, " %X:Y-%d",
3282 i, boardp->queue_full_cnt[i]);
3283 else
3284 seq_printf(m, " %X:N", i);
3285 }
3286
3287 seq_puts(m, "\n Synchronous Transfer:");
3288 for (i = 0; i <= ASC_MAX_TID; i++) {
3289 if ((chip_scsi_id == i) ||
3290 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3291 continue;
3292 }
3293 seq_printf(m, " %X:%c",
3294 i,
3295 (v->sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3296 }
3297 seq_putc(m, '\n');
3298
3299 for (i = 0; i <= ASC_MAX_TID; i++) {
3300 uchar syn_period_ix;
3301
3302 if ((chip_scsi_id == i) ||
3303 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3304 ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
3305 continue;
3306 }
3307
3308 seq_printf(m, " %X:", i);
3309
3310 if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0) {
3311 seq_puts(m, " Asynchronous");
3312 } else {
3313 syn_period_ix =
3314 (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index -
3315 1);
3316
3317 seq_printf(m,
3318 " Transfer Period Factor: %d (%d.%d Mhz),",
3319 v->sdtr_period_tbl[syn_period_ix],
3320 250 / v->sdtr_period_tbl[syn_period_ix],
3321 ASC_TENTHS(250,
3322 v->sdtr_period_tbl[syn_period_ix]));
3323
3324 seq_printf(m, " REQ/ACK Offset: %d",
3325 boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET);
3326 }
3327
3328 if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3329 seq_puts(m, "*\n");
3330 renegotiate = 1;
3331 } else {
3332 seq_putc(m, '\n');
3333 }
3334 }
3335
3336 if (renegotiate) {
3337 seq_puts(m, " * = Re-negotiation pending before next command.\n");
3338 }
3339 }
3340
3341 /*
3342 * asc_prt_adv_board_info()
3343 *
3344 * Print dynamic board configuration information.
3345 */
3346 static void asc_prt_adv_board_info(struct seq_file *m, struct Scsi_Host *shost)
3347 {
3348 struct asc_board *boardp = shost_priv(shost);
3349 int i;
3350 ADV_DVC_VAR *v;
3351 ADV_DVC_CFG *c;
3352 AdvPortAddr iop_base;
3353 ushort chip_scsi_id;
3354 ushort lramword;
3355 uchar lrambyte;
3356 ushort tagqng_able;
3357 ushort sdtr_able, wdtr_able;
3358 ushort wdtr_done, sdtr_done;
3359 ushort period = 0;
3360 int renegotiate = 0;
3361
3362 v = &boardp->dvc_var.adv_dvc_var;
3363 c = &boardp->dvc_cfg.adv_dvc_cfg;
3364 iop_base = v->iop_base;
3365 chip_scsi_id = v->chip_scsi_id;
3366
3367 seq_printf(m,
3368 "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3369 shost->host_no);
3370
3371 seq_printf(m,
3372 " iop_base 0x%lx, cable_detect: %X, err_code %u\n",
3373 (unsigned long)v->iop_base,
3374 AdvReadWordRegister(iop_base,IOPW_SCSI_CFG1) & CABLE_DETECT,
3375 v->err_code);
3376
3377 seq_printf(m, " chip_version %u, mcode_date 0x%x, "
3378 "mcode_version 0x%x\n", c->chip_version,
3379 c->mcode_date, c->mcode_version);
3380
3381 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
3382 seq_puts(m, " Queuing Enabled:");
3383 for (i = 0; i <= ADV_MAX_TID; i++) {
3384 if ((chip_scsi_id == i) ||
3385 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3386 continue;
3387 }
3388
3389 seq_printf(m, " %X:%c",
3390 i,
3391 (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3392 }
3393
3394 seq_puts(m, "\n Queue Limit:");
3395 for (i = 0; i <= ADV_MAX_TID; i++) {
3396 if ((chip_scsi_id == i) ||
3397 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3398 continue;
3399 }
3400
3401 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i,
3402 lrambyte);
3403
3404 seq_printf(m, " %X:%d", i, lrambyte);
3405 }
3406
3407 seq_puts(m, "\n Command Pending:");
3408 for (i = 0; i <= ADV_MAX_TID; i++) {
3409 if ((chip_scsi_id == i) ||
3410 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3411 continue;
3412 }
3413
3414 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i,
3415 lrambyte);
3416
3417 seq_printf(m, " %X:%d", i, lrambyte);
3418 }
3419 seq_putc(m, '\n');
3420
3421 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
3422 seq_puts(m, " Wide Enabled:");
3423 for (i = 0; i <= ADV_MAX_TID; i++) {
3424 if ((chip_scsi_id == i) ||
3425 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3426 continue;
3427 }
3428
3429 seq_printf(m, " %X:%c",
3430 i,
3431 (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3432 }
3433 seq_putc(m, '\n');
3434
3435 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done);
3436 seq_puts(m, " Transfer Bit Width:");
3437 for (i = 0; i <= ADV_MAX_TID; i++) {
3438 if ((chip_scsi_id == i) ||
3439 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3440 continue;
3441 }
3442
3443 AdvReadWordLram(iop_base,
3444 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3445 lramword);
3446
3447 seq_printf(m, " %X:%d",
3448 i, (lramword & 0x8000) ? 16 : 8);
3449
3450 if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) &&
3451 (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3452 seq_putc(m, '*');
3453 renegotiate = 1;
3454 }
3455 }
3456 seq_putc(m, '\n');
3457
3458 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
3459 seq_puts(m, " Synchronous Enabled:");
3460 for (i = 0; i <= ADV_MAX_TID; i++) {
3461 if ((chip_scsi_id == i) ||
3462 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3463 continue;
3464 }
3465
3466 seq_printf(m, " %X:%c",
3467 i,
3468 (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3469 }
3470 seq_putc(m, '\n');
3471
3472 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done);
3473 for (i = 0; i <= ADV_MAX_TID; i++) {
3474
3475 AdvReadWordLram(iop_base,
3476 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3477 lramword);
3478 lramword &= ~0x8000;
3479
3480 if ((chip_scsi_id == i) ||
3481 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3482 ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
3483 continue;
3484 }
3485
3486 seq_printf(m, " %X:", i);
3487
3488 if ((lramword & 0x1F) == 0) { /* Check for REQ/ACK Offset 0. */
3489 seq_puts(m, " Asynchronous");
3490 } else {
3491 seq_puts(m, " Transfer Period Factor: ");
3492
3493 if ((lramword & 0x1F00) == 0x1100) { /* 80 Mhz */
3494 seq_puts(m, "9 (80.0 Mhz),");
3495 } else if ((lramword & 0x1F00) == 0x1000) { /* 40 Mhz */
3496 seq_puts(m, "10 (40.0 Mhz),");
3497 } else { /* 20 Mhz or below. */
3498
3499 period = (((lramword >> 8) * 25) + 50) / 4;
3500
3501 if (period == 0) { /* Should never happen. */
3502 seq_printf(m, "%d (? Mhz), ", period);
3503 } else {
3504 seq_printf(m,
3505 "%d (%d.%d Mhz),",
3506 period, 250 / period,
3507 ASC_TENTHS(250, period));
3508 }
3509 }
3510
3511 seq_printf(m, " REQ/ACK Offset: %d",
3512 lramword & 0x1F);
3513 }
3514
3515 if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3516 seq_puts(m, "*\n");
3517 renegotiate = 1;
3518 } else {
3519 seq_putc(m, '\n');
3520 }
3521 }
3522
3523 if (renegotiate) {
3524 seq_puts(m, " * = Re-negotiation pending before next command.\n");
3525 }
3526 }
3527
3528 #ifdef ADVANSYS_STATS
3529 /*
3530 * asc_prt_board_stats()
3531 */
3532 static void asc_prt_board_stats(struct seq_file *m, struct Scsi_Host *shost)
3533 {
3534 struct asc_board *boardp = shost_priv(shost);
3535 struct asc_stats *s = &boardp->asc_stats;
3536
3537 seq_printf(m,
3538 "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n",
3539 shost->host_no);
3540
3541 seq_printf(m,
3542 " queuecommand %u, reset %u, biosparam %u, interrupt %u\n",
3543 s->queuecommand, s->reset, s->biosparam,
3544 s->interrupt);
3545
3546 seq_printf(m,
3547 " callback %u, done %u, build_error %u, build_noreq %u, build_nosg %u\n",
3548 s->callback, s->done, s->build_error,
3549 s->adv_build_noreq, s->adv_build_nosg);
3550
3551 seq_printf(m,
3552 " exe_noerror %u, exe_busy %u, exe_error %u, exe_unknown %u\n",
3553 s->exe_noerror, s->exe_busy, s->exe_error,
3554 s->exe_unknown);
3555
3556 /*
3557 * Display data transfer statistics.
3558 */
3559 if (s->xfer_cnt > 0) {
3560 seq_printf(m, " xfer_cnt %u, xfer_elem %u, ",
3561 s->xfer_cnt, s->xfer_elem);
3562
3563 seq_printf(m, "xfer_bytes %u.%01u kb\n",
3564 s->xfer_sect / 2, ASC_TENTHS(s->xfer_sect, 2));
3565
3566 /* Scatter gather transfer statistics */
3567 seq_printf(m, " avg_num_elem %u.%01u, ",
3568 s->xfer_elem / s->xfer_cnt,
3569 ASC_TENTHS(s->xfer_elem, s->xfer_cnt));
3570
3571 seq_printf(m, "avg_elem_size %u.%01u kb, ",
3572 (s->xfer_sect / 2) / s->xfer_elem,
3573 ASC_TENTHS((s->xfer_sect / 2), s->xfer_elem));
3574
3575 seq_printf(m, "avg_xfer_size %u.%01u kb\n",
3576 (s->xfer_sect / 2) / s->xfer_cnt,
3577 ASC_TENTHS((s->xfer_sect / 2), s->xfer_cnt));
3578 }
3579 }
3580 #endif /* ADVANSYS_STATS */
3581
3582 /*
3583 * advansys_show_info() - /proc/scsi/advansys/{0,1,2,3,...}
3584 *
3585 * m: seq_file to print into
3586 * shost: Scsi_Host
3587 *
3588 * Return the number of bytes read from or written to a
3589 * /proc/scsi/advansys/[0...] file.
3590 */
3591 static int
3592 advansys_show_info(struct seq_file *m, struct Scsi_Host *shost)
3593 {
3594 struct asc_board *boardp = shost_priv(shost);
3595
3596 ASC_DBG(1, "begin\n");
3597
3598 /*
3599 * User read of /proc/scsi/advansys/[0...] file.
3600 */
3601
3602 /*
3603 * Get board configuration information.
3604 *
3605 * advansys_info() returns the board string from its own static buffer.
3606 */
3607 /* Copy board information. */
3608 seq_printf(m, "%s\n", (char *)advansys_info(shost));
3609 /*
3610 * Display Wide Board BIOS Information.
3611 */
3612 if (!ASC_NARROW_BOARD(boardp))
3613 asc_prt_adv_bios(m, shost);
3614
3615 /*
3616 * Display driver information for each device attached to the board.
3617 */
3618 asc_prt_board_devices(m, shost);
3619
3620 /*
3621 * Display EEPROM configuration for the board.
3622 */
3623 if (ASC_NARROW_BOARD(boardp))
3624 asc_prt_asc_board_eeprom(m, shost);
3625 else
3626 asc_prt_adv_board_eeprom(m, shost);
3627
3628 /*
3629 * Display driver configuration and information for the board.
3630 */
3631 asc_prt_driver_conf(m, shost);
3632
3633 #ifdef ADVANSYS_STATS
3634 /*
3635 * Display driver statistics for the board.
3636 */
3637 asc_prt_board_stats(m, shost);
3638 #endif /* ADVANSYS_STATS */
3639
3640 /*
3641 * Display Asc Library dynamic configuration information
3642 * for the board.
3643 */
3644 if (ASC_NARROW_BOARD(boardp))
3645 asc_prt_asc_board_info(m, shost);
3646 else
3647 asc_prt_adv_board_info(m, shost);
3648 return 0;
3649 }
3650 #endif /* CONFIG_PROC_FS */
3651
3652 static void asc_scsi_done(struct scsi_cmnd *scp)
3653 {
3654 scsi_dma_unmap(scp);
3655 ASC_STATS(scp->device->host, done);
3656 scp->scsi_done(scp);
3657 }
3658
3659 static void AscSetBank(PortAddr iop_base, uchar bank)
3660 {
3661 uchar val;
3662
3663 val = AscGetChipControl(iop_base) &
3664 (~
3665 (CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET |
3666 CC_CHIP_RESET));
3667 if (bank == 1) {
3668 val |= CC_BANK_ONE;
3669 } else if (bank == 2) {
3670 val |= CC_DIAG | CC_BANK_ONE;
3671 } else {
3672 val &= ~CC_BANK_ONE;
3673 }
3674 AscSetChipControl(iop_base, val);
3675 }
3676
3677 static void AscSetChipIH(PortAddr iop_base, ushort ins_code)
3678 {
3679 AscSetBank(iop_base, 1);
3680 AscWriteChipIH(iop_base, ins_code);
3681 AscSetBank(iop_base, 0);
3682 }
3683
3684 static int AscStartChip(PortAddr iop_base)
3685 {
3686 AscSetChipControl(iop_base, 0);
3687 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
3688 return (0);
3689 }
3690 return (1);
3691 }
3692
3693 static bool AscStopChip(PortAddr iop_base)
3694 {
3695 uchar cc_val;
3696
3697 cc_val =
3698 AscGetChipControl(iop_base) &
3699 (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG));
3700 AscSetChipControl(iop_base, (uchar)(cc_val | CC_HALT));
3701 AscSetChipIH(iop_base, INS_HALT);
3702 AscSetChipIH(iop_base, INS_RFLAG_WTM);
3703 if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) {
3704 return false;
3705 }
3706 return true;
3707 }
3708
3709 static bool AscIsChipHalted(PortAddr iop_base)
3710 {
3711 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
3712 if ((AscGetChipControl(iop_base) & CC_HALT) != 0) {
3713 return true;
3714 }
3715 }
3716 return false;
3717 }
3718
3719 static bool AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc)
3720 {
3721 PortAddr iop_base;
3722 int i = 10;
3723
3724 iop_base = asc_dvc->iop_base;
3725 while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE)
3726 && (i-- > 0)) {
3727 mdelay(100);
3728 }
3729 AscStopChip(iop_base);
3730 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT);
3731 udelay(60);
3732 AscSetChipIH(iop_base, INS_RFLAG_WTM);
3733 AscSetChipIH(iop_base, INS_HALT);
3734 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT);
3735 AscSetChipControl(iop_base, CC_HALT);
3736 mdelay(200);
3737 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
3738 AscSetChipStatus(iop_base, 0);
3739 return (AscIsChipHalted(iop_base));
3740 }
3741
3742 static int AscFindSignature(PortAddr iop_base)
3743 {
3744 ushort sig_word;
3745
3746 ASC_DBG(1, "AscGetChipSignatureByte(0x%x) 0x%x\n",
3747 iop_base, AscGetChipSignatureByte(iop_base));
3748 if (AscGetChipSignatureByte(iop_base) == (uchar)ASC_1000_ID1B) {
3749 ASC_DBG(1, "AscGetChipSignatureWord(0x%x) 0x%x\n",
3750 iop_base, AscGetChipSignatureWord(iop_base));
3751 sig_word = AscGetChipSignatureWord(iop_base);
3752 if ((sig_word == (ushort)ASC_1000_ID0W) ||
3753 (sig_word == (ushort)ASC_1000_ID0W_FIX)) {
3754 return (1);
3755 }
3756 }
3757 return (0);
3758 }
3759
3760 static void AscEnableInterrupt(PortAddr iop_base)
3761 {
3762 ushort cfg;
3763
3764 cfg = AscGetChipCfgLsw(iop_base);
3765 AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON);
3766 }
3767
3768 static void AscDisableInterrupt(PortAddr iop_base)
3769 {
3770 ushort cfg;
3771
3772 cfg = AscGetChipCfgLsw(iop_base);
3773 AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON));
3774 }
3775
3776 static uchar AscReadLramByte(PortAddr iop_base, ushort addr)
3777 {
3778 unsigned char byte_data;
3779 unsigned short word_data;
3780
3781 if (isodd_word(addr)) {
3782 AscSetChipLramAddr(iop_base, addr - 1);
3783 word_data = AscGetChipLramData(iop_base);
3784 byte_data = (word_data >> 8) & 0xFF;
3785 } else {
3786 AscSetChipLramAddr(iop_base, addr);
3787 word_data = AscGetChipLramData(iop_base);
3788 byte_data = word_data & 0xFF;
3789 }
3790 return byte_data;
3791 }
3792
3793 static ushort AscReadLramWord(PortAddr iop_base, ushort addr)
3794 {
3795 ushort word_data;
3796
3797 AscSetChipLramAddr(iop_base, addr);
3798 word_data = AscGetChipLramData(iop_base);
3799 return (word_data);
3800 }
3801
3802 static void
3803 AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words)
3804 {
3805 int i;
3806
3807 AscSetChipLramAddr(iop_base, s_addr);
3808 for (i = 0; i < words; i++) {
3809 AscSetChipLramData(iop_base, set_wval);
3810 }
3811 }
3812
3813 static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val)
3814 {
3815 AscSetChipLramAddr(iop_base, addr);
3816 AscSetChipLramData(iop_base, word_val);
3817 }
3818
3819 static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val)
3820 {
3821 ushort word_data;
3822
3823 if (isodd_word(addr)) {
3824 addr--;
3825 word_data = AscReadLramWord(iop_base, addr);
3826 word_data &= 0x00FF;
3827 word_data |= (((ushort)byte_val << 8) & 0xFF00);
3828 } else {
3829 word_data = AscReadLramWord(iop_base, addr);
3830 word_data &= 0xFF00;
3831 word_data |= ((ushort)byte_val & 0x00FF);
3832 }
3833 AscWriteLramWord(iop_base, addr, word_data);
3834 }
3835
3836 /*
3837 * Copy 2 bytes to LRAM.
3838 *
3839 * The source data is assumed to be in little-endian order in memory
3840 * and is maintained in little-endian order when written to LRAM.
3841 */
3842 static void
3843 AscMemWordCopyPtrToLram(PortAddr iop_base, ushort s_addr,
3844 const uchar *s_buffer, int words)
3845 {
3846 int i;
3847
3848 AscSetChipLramAddr(iop_base, s_addr);
3849 for (i = 0; i < 2 * words; i += 2) {
3850 /*
3851 * On a little-endian system the second argument below
3852 * produces a little-endian ushort which is written to
3853 * LRAM in little-endian order. On a big-endian system
3854 * the second argument produces a big-endian ushort which
3855 * is "transparently" byte-swapped by outpw() and written
3856 * in little-endian order to LRAM.
3857 */
3858 outpw(iop_base + IOP_RAM_DATA,
3859 ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);
3860 }
3861 }
3862
3863 /*
3864 * Copy 4 bytes to LRAM.
3865 *
3866 * The source data is assumed to be in little-endian order in memory
3867 * and is maintained in little-endian order when written to LRAM.
3868 */
3869 static void
3870 AscMemDWordCopyPtrToLram(PortAddr iop_base,
3871 ushort s_addr, uchar *s_buffer, int dwords)
3872 {
3873 int i;
3874
3875 AscSetChipLramAddr(iop_base, s_addr);
3876 for (i = 0; i < 4 * dwords; i += 4) {
3877 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]); /* LSW */
3878 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]); /* MSW */
3879 }
3880 }
3881
3882 /*
3883 * Copy 2 bytes from LRAM.
3884 *
3885 * The source data is assumed to be in little-endian order in LRAM
3886 * and is maintained in little-endian order when written to memory.
3887 */
3888 static void
3889 AscMemWordCopyPtrFromLram(PortAddr iop_base,
3890 ushort s_addr, uchar *d_buffer, int words)
3891 {
3892 int i;
3893 ushort word;
3894
3895 AscSetChipLramAddr(iop_base, s_addr);
3896 for (i = 0; i < 2 * words; i += 2) {
3897 word = inpw(iop_base + IOP_RAM_DATA);
3898 d_buffer[i] = word & 0xff;
3899 d_buffer[i + 1] = (word >> 8) & 0xff;
3900 }
3901 }
3902
3903 static u32 AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words)
3904 {
3905 u32 sum = 0;
3906 int i;
3907
3908 for (i = 0; i < words; i++, s_addr += 2) {
3909 sum += AscReadLramWord(iop_base, s_addr);
3910 }
3911 return (sum);
3912 }
3913
3914 static void AscInitLram(ASC_DVC_VAR *asc_dvc)
3915 {
3916 uchar i;
3917 ushort s_addr;
3918 PortAddr iop_base;
3919
3920 iop_base = asc_dvc->iop_base;
3921 AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0,
3922 (ushort)(((int)(asc_dvc->max_total_qng + 2 + 1) *
3923 64) >> 1));
3924 i = ASC_MIN_ACTIVE_QNO;
3925 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
3926 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
3927 (uchar)(i + 1));
3928 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
3929 (uchar)(asc_dvc->max_total_qng));
3930 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
3931 (uchar)i);
3932 i++;
3933 s_addr += ASC_QBLK_SIZE;
3934 for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
3935 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
3936 (uchar)(i + 1));
3937 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
3938 (uchar)(i - 1));
3939 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
3940 (uchar)i);
3941 }
3942 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
3943 (uchar)ASC_QLINK_END);
3944 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
3945 (uchar)(asc_dvc->max_total_qng - 1));
3946 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
3947 (uchar)asc_dvc->max_total_qng);
3948 i++;
3949 s_addr += ASC_QBLK_SIZE;
3950 for (; i <= (uchar)(asc_dvc->max_total_qng + 3);
3951 i++, s_addr += ASC_QBLK_SIZE) {
3952 AscWriteLramByte(iop_base,
3953 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_FWD), i);
3954 AscWriteLramByte(iop_base,
3955 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_BWD), i);
3956 AscWriteLramByte(iop_base,
3957 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_QNO), i);
3958 }
3959 }
3960
3961 static u32
3962 AscLoadMicroCode(PortAddr iop_base, ushort s_addr,
3963 const uchar *mcode_buf, ushort mcode_size)
3964 {
3965 u32 chksum;
3966 ushort mcode_word_size;
3967 ushort mcode_chksum;
3968
3969 /* Write the microcode buffer starting at LRAM address 0. */
3970 mcode_word_size = (ushort)(mcode_size >> 1);
3971 AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size);
3972 AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size);
3973
3974 chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size);
3975 ASC_DBG(1, "chksum 0x%lx\n", (ulong)chksum);
3976 mcode_chksum = (ushort)AscMemSumLramWord(iop_base,
3977 (ushort)ASC_CODE_SEC_BEG,
3978 (ushort)((mcode_size -
3979 s_addr - (ushort)
3980 ASC_CODE_SEC_BEG) /
3981 2));
3982 ASC_DBG(1, "mcode_chksum 0x%lx\n", (ulong)mcode_chksum);
3983 AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum);
3984 AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size);
3985 return chksum;
3986 }
3987
3988 static void AscInitQLinkVar(ASC_DVC_VAR *asc_dvc)
3989 {
3990 PortAddr iop_base;
3991 int i;
3992 ushort lram_addr;
3993
3994 iop_base = asc_dvc->iop_base;
3995 AscPutRiscVarFreeQHead(iop_base, 1);
3996 AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng);
3997 AscPutVarFreeQHead(iop_base, 1);
3998 AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng);
3999 AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B,
4000 (uchar)((int)asc_dvc->max_total_qng + 1));
4001 AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B,
4002 (uchar)((int)asc_dvc->max_total_qng + 2));
4003 AscWriteLramByte(iop_base, (ushort)ASCV_TOTAL_READY_Q_B,
4004 asc_dvc->max_total_qng);
4005 AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0);
4006 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
4007 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0);
4008 AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0);
4009 AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0);
4010 AscPutQDoneInProgress(iop_base, 0);
4011 lram_addr = ASC_QADR_BEG;
4012 for (i = 0; i < 32; i++, lram_addr += 2) {
4013 AscWriteLramWord(iop_base, lram_addr, 0);
4014 }
4015 }
4016
4017 static int AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc)
4018 {
4019 int i;
4020 int warn_code;
4021 PortAddr iop_base;
4022 __le32 phy_addr;
4023 __le32 phy_size;
4024 struct asc_board *board = asc_dvc_to_board(asc_dvc);
4025
4026 iop_base = asc_dvc->iop_base;
4027 warn_code = 0;
4028 for (i = 0; i <= ASC_MAX_TID; i++) {
4029 AscPutMCodeInitSDTRAtID(iop_base, i,
4030 asc_dvc->cfg->sdtr_period_offset[i]);
4031 }
4032
4033 AscInitQLinkVar(asc_dvc);
4034 AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B,
4035 asc_dvc->cfg->disc_enable);
4036 AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B,
4037 ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id));
4038
4039 /* Ensure overrun buffer is aligned on an 8 byte boundary. */
4040 BUG_ON((unsigned long)asc_dvc->overrun_buf & 7);
4041 asc_dvc->overrun_dma = dma_map_single(board->dev, asc_dvc->overrun_buf,
4042 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
4043 if (dma_mapping_error(board->dev, asc_dvc->overrun_dma)) {
4044 warn_code = -ENOMEM;
4045 goto err_dma_map;
4046 }
4047 phy_addr = cpu_to_le32(asc_dvc->overrun_dma);
4048 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D,
4049 (uchar *)&phy_addr, 1);
4050 phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE);
4051 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D,
4052 (uchar *)&phy_size, 1);
4053
4054 asc_dvc->cfg->mcode_date =
4055 AscReadLramWord(iop_base, (ushort)ASCV_MC_DATE_W);
4056 asc_dvc->cfg->mcode_version =
4057 AscReadLramWord(iop_base, (ushort)ASCV_MC_VER_W);
4058
4059 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
4060 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
4061 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
4062 warn_code = -EINVAL;
4063 goto err_mcode_start;
4064 }
4065 if (AscStartChip(iop_base) != 1) {
4066 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
4067 warn_code = -EIO;
4068 goto err_mcode_start;
4069 }
4070
4071 return warn_code;
4072
4073 err_mcode_start:
4074 dma_unmap_single(board->dev, asc_dvc->overrun_dma,
4075 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
4076 err_dma_map:
4077 asc_dvc->overrun_dma = 0;
4078 return warn_code;
4079 }
4080
4081 static int AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc)
4082 {
4083 const struct firmware *fw;
4084 const char fwname[] = "advansys/mcode.bin";
4085 int err;
4086 unsigned long chksum;
4087 int warn_code;
4088 PortAddr iop_base;
4089
4090 iop_base = asc_dvc->iop_base;
4091 warn_code = 0;
4092 if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) &&
4093 !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) {
4094 AscResetChipAndScsiBus(asc_dvc);
4095 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
4096 }
4097 asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC;
4098 if (asc_dvc->err_code != 0)
4099 return ASC_ERROR;
4100 if (!AscFindSignature(asc_dvc->iop_base)) {
4101 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
4102 return warn_code;
4103 }
4104 AscDisableInterrupt(iop_base);
4105 AscInitLram(asc_dvc);
4106
4107 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4108 if (err) {
4109 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4110 fwname, err);
4111 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4112 return err;
4113 }
4114 if (fw->size < 4) {
4115 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4116 fw->size, fwname);
4117 release_firmware(fw);
4118 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4119 return -EINVAL;
4120 }
4121 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4122 (fw->data[1] << 8) | fw->data[0];
4123 ASC_DBG(1, "_asc_mcode_chksum 0x%lx\n", (ulong)chksum);
4124 if (AscLoadMicroCode(iop_base, 0, &fw->data[4],
4125 fw->size - 4) != chksum) {
4126 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4127 release_firmware(fw);
4128 return warn_code;
4129 }
4130 release_firmware(fw);
4131 warn_code |= AscInitMicroCodeVar(asc_dvc);
4132 if (!asc_dvc->overrun_dma)
4133 return warn_code;
4134 asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC;
4135 AscEnableInterrupt(iop_base);
4136 return warn_code;
4137 }
4138
4139 /*
4140 * Load the Microcode
4141 *
4142 * Write the microcode image to RISC memory starting at address 0.
4143 *
4144 * The microcode is stored compressed in the following format:
4145 *
4146 * 254 word (508 byte) table indexed by byte code followed
4147 * by the following byte codes:
4148 *
4149 * 1-Byte Code:
4150 * 00: Emit word 0 in table.
4151 * 01: Emit word 1 in table.
4152 * .
4153 * FD: Emit word 253 in table.
4154 *
4155 * Multi-Byte Code:
4156 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
4157 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
4158 *
4159 * Returns 0 or an error if the checksum doesn't match
4160 */
4161 static int AdvLoadMicrocode(AdvPortAddr iop_base, const unsigned char *buf,
4162 int size, int memsize, int chksum)
4163 {
4164 int i, j, end, len = 0;
4165 u32 sum;
4166
4167 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4168
4169 for (i = 253 * 2; i < size; i++) {
4170 if (buf[i] == 0xff) {
4171 unsigned short word = (buf[i + 3] << 8) | buf[i + 2];
4172 for (j = 0; j < buf[i + 1]; j++) {
4173 AdvWriteWordAutoIncLram(iop_base, word);
4174 len += 2;
4175 }
4176 i += 3;
4177 } else if (buf[i] == 0xfe) {
4178 unsigned short word = (buf[i + 2] << 8) | buf[i + 1];
4179 AdvWriteWordAutoIncLram(iop_base, word);
4180 i += 2;
4181 len += 2;
4182 } else {
4183 unsigned int off = buf[i] * 2;
4184 unsigned short word = (buf[off + 1] << 8) | buf[off];
4185 AdvWriteWordAutoIncLram(iop_base, word);
4186 len += 2;
4187 }
4188 }
4189
4190 end = len;
4191
4192 while (len < memsize) {
4193 AdvWriteWordAutoIncLram(iop_base, 0);
4194 len += 2;
4195 }
4196
4197 /* Verify the microcode checksum. */
4198 sum = 0;
4199 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4200
4201 for (len = 0; len < end; len += 2) {
4202 sum += AdvReadWordAutoIncLram(iop_base);
4203 }
4204
4205 if (sum != chksum)
4206 return ASC_IERR_MCODE_CHKSUM;
4207
4208 return 0;
4209 }
4210
4211 static void AdvBuildCarrierFreelist(struct adv_dvc_var *adv_dvc)
4212 {
4213 off_t carr_offset = 0, next_offset;
4214 dma_addr_t carr_paddr;
4215 int carr_num = ADV_CARRIER_BUFSIZE / sizeof(ADV_CARR_T), i;
4216
4217 for (i = 0; i < carr_num; i++) {
4218 carr_offset = i * sizeof(ADV_CARR_T);
4219 /* Get physical address of the carrier 'carrp'. */
4220 carr_paddr = adv_dvc->carrier_addr + carr_offset;
4221
4222 adv_dvc->carrier[i].carr_pa = cpu_to_le32(carr_paddr);
4223 adv_dvc->carrier[i].carr_va = cpu_to_le32(carr_offset);
4224 adv_dvc->carrier[i].areq_vpa = 0;
4225 next_offset = carr_offset + sizeof(ADV_CARR_T);
4226 if (i == carr_num)
4227 next_offset = ~0;
4228 adv_dvc->carrier[i].next_vpa = cpu_to_le32(next_offset);
4229 }
4230 /*
4231 * We cannot have a carrier with 'carr_va' of '0', as
4232 * a reference to this carrier would be interpreted as
4233 * list termination.
4234 * So start at carrier 1 with the freelist.
4235 */
4236 adv_dvc->carr_freelist = &adv_dvc->carrier[1];
4237 }
4238
4239 static ADV_CARR_T *adv_get_carrier(struct adv_dvc_var *adv_dvc, u32 offset)
4240 {
4241 int index;
4242
4243 BUG_ON(offset > ADV_CARRIER_BUFSIZE);
4244
4245 index = offset / sizeof(ADV_CARR_T);
4246 return &adv_dvc->carrier[index];
4247 }
4248
4249 static ADV_CARR_T *adv_get_next_carrier(struct adv_dvc_var *adv_dvc)
4250 {
4251 ADV_CARR_T *carrp = adv_dvc->carr_freelist;
4252 u32 next_vpa = le32_to_cpu(carrp->next_vpa);
4253
4254 if (next_vpa == 0 || next_vpa == ~0) {
4255 ASC_DBG(1, "invalid vpa offset 0x%x\n", next_vpa);
4256 return NULL;
4257 }
4258
4259 adv_dvc->carr_freelist = adv_get_carrier(adv_dvc, next_vpa);
4260 /*
4261 * insert stopper carrier to terminate list
4262 */
4263 carrp->next_vpa = cpu_to_le32(ADV_CQ_STOPPER);
4264
4265 return carrp;
4266 }
4267
4268 /*
4269 * 'offset' is the index in the request pointer array
4270 */
4271 static adv_req_t * adv_get_reqp(struct adv_dvc_var *adv_dvc, u32 offset)
4272 {
4273 struct asc_board *boardp = adv_dvc->drv_ptr;
4274
4275 BUG_ON(offset > adv_dvc->max_host_qng);
4276 return &boardp->adv_reqp[offset];
4277 }
4278
4279 /*
4280 * Send an idle command to the chip and wait for completion.
4281 *
4282 * Command completion is polled for once per microsecond.
4283 *
4284 * The function can be called from anywhere including an interrupt handler.
4285 * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
4286 * functions to prevent reentrancy.
4287 *
4288 * Return Values:
4289 * ADV_TRUE - command completed successfully
4290 * ADV_FALSE - command failed
4291 * ADV_ERROR - command timed out
4292 */
4293 static int
4294 AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
4295 ushort idle_cmd, u32 idle_cmd_parameter)
4296 {
4297 int result, i, j;
4298 AdvPortAddr iop_base;
4299
4300 iop_base = asc_dvc->iop_base;
4301
4302 /*
4303 * Clear the idle command status which is set by the microcode
4304 * to a non-zero value to indicate when the command is completed.
4305 * The non-zero result is one of the IDLE_CMD_STATUS_* values
4306 */
4307 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort)0);
4308
4309 /*
4310 * Write the idle command value after the idle command parameter
4311 * has been written to avoid a race condition. If the order is not
4312 * followed, the microcode may process the idle command before the
4313 * parameters have been written to LRAM.
4314 */
4315 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER,
4316 cpu_to_le32(idle_cmd_parameter));
4317 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd);
4318
4319 /*
4320 * Tickle the RISC to tell it to process the idle command.
4321 */
4322 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B);
4323 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
4324 /*
4325 * Clear the tickle value. In the ASC-3550 the RISC flag
4326 * command 'clr_tickle_b' does not work unless the host
4327 * value is cleared.
4328 */
4329 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
4330 }
4331
4332 /* Wait for up to 100 millisecond for the idle command to timeout. */
4333 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) {
4334 /* Poll once each microsecond for command completion. */
4335 for (j = 0; j < SCSI_US_PER_MSEC; j++) {
4336 AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS,
4337 result);
4338 if (result != 0)
4339 return result;
4340 udelay(1);
4341 }
4342 }
4343
4344 BUG(); /* The idle command should never timeout. */
4345 return ADV_ERROR;
4346 }
4347
4348 /*
4349 * Reset SCSI Bus and purge all outstanding requests.
4350 *
4351 * Return Value:
4352 * ADV_TRUE(1) - All requests are purged and SCSI Bus is reset.
4353 * ADV_FALSE(0) - Microcode command failed.
4354 * ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
4355 * may be hung which requires driver recovery.
4356 */
4357 static int AdvResetSB(ADV_DVC_VAR *asc_dvc)
4358 {
4359 int status;
4360
4361 /*
4362 * Send the SCSI Bus Reset idle start idle command which asserts
4363 * the SCSI Bus Reset signal.
4364 */
4365 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_START, 0L);
4366 if (status != ADV_TRUE) {
4367 return status;
4368 }
4369
4370 /*
4371 * Delay for the specified SCSI Bus Reset hold time.
4372 *
4373 * The hold time delay is done on the host because the RISC has no
4374 * microsecond accurate timer.
4375 */
4376 udelay(ASC_SCSI_RESET_HOLD_TIME_US);
4377
4378 /*
4379 * Send the SCSI Bus Reset end idle command which de-asserts
4380 * the SCSI Bus Reset signal and purges any pending requests.
4381 */
4382 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_END, 0L);
4383 if (status != ADV_TRUE) {
4384 return status;
4385 }
4386
4387 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
4388
4389 return status;
4390 }
4391
4392 /*
4393 * Initialize the ASC-3550.
4394 *
4395 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
4396 *
4397 * For a non-fatal error return a warning code. If there are no warnings
4398 * then 0 is returned.
4399 *
4400 * Needed after initialization for error recovery.
4401 */
4402 static int AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc)
4403 {
4404 const struct firmware *fw;
4405 const char fwname[] = "advansys/3550.bin";
4406 AdvPortAddr iop_base;
4407 ushort warn_code;
4408 int begin_addr;
4409 int end_addr;
4410 ushort code_sum;
4411 int word;
4412 int i;
4413 int err;
4414 unsigned long chksum;
4415 ushort scsi_cfg1;
4416 uchar tid;
4417 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
4418 ushort wdtr_able = 0, sdtr_able, tagqng_able;
4419 uchar max_cmd[ADV_MAX_TID + 1];
4420
4421 /* If there is already an error, don't continue. */
4422 if (asc_dvc->err_code != 0)
4423 return ADV_ERROR;
4424
4425 /*
4426 * The caller must set 'chip_type' to ADV_CHIP_ASC3550.
4427 */
4428 if (asc_dvc->chip_type != ADV_CHIP_ASC3550) {
4429 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
4430 return ADV_ERROR;
4431 }
4432
4433 warn_code = 0;
4434 iop_base = asc_dvc->iop_base;
4435
4436 /*
4437 * Save the RISC memory BIOS region before writing the microcode.
4438 * The BIOS may already be loaded and using its RISC LRAM region
4439 * so its region must be saved and restored.
4440 *
4441 * Note: This code makes the assumption, which is currently true,
4442 * that a chip reset does not clear RISC LRAM.
4443 */
4444 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4445 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4446 bios_mem[i]);
4447 }
4448
4449 /*
4450 * Save current per TID negotiated values.
4451 */
4452 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 0x55AA) {
4453 ushort bios_version, major, minor;
4454
4455 bios_version =
4456 bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM) / 2];
4457 major = (bios_version >> 12) & 0xF;
4458 minor = (bios_version >> 8) & 0xF;
4459 if (major < 3 || (major == 3 && minor == 1)) {
4460 /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */
4461 AdvReadWordLram(iop_base, 0x120, wdtr_able);
4462 } else {
4463 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4464 }
4465 }
4466 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4467 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
4468 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4469 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
4470 max_cmd[tid]);
4471 }
4472
4473 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4474 if (err) {
4475 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4476 fwname, err);
4477 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
4478 return err;
4479 }
4480 if (fw->size < 4) {
4481 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4482 fw->size, fwname);
4483 release_firmware(fw);
4484 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
4485 return -EINVAL;
4486 }
4487 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4488 (fw->data[1] << 8) | fw->data[0];
4489 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
4490 fw->size - 4, ADV_3550_MEMSIZE,
4491 chksum);
4492 release_firmware(fw);
4493 if (asc_dvc->err_code)
4494 return ADV_ERROR;
4495
4496 /*
4497 * Restore the RISC memory BIOS region.
4498 */
4499 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4500 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4501 bios_mem[i]);
4502 }
4503
4504 /*
4505 * Calculate and write the microcode code checksum to the microcode
4506 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
4507 */
4508 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
4509 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
4510 code_sum = 0;
4511 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
4512 for (word = begin_addr; word < end_addr; word += 2) {
4513 code_sum += AdvReadWordAutoIncLram(iop_base);
4514 }
4515 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
4516
4517 /*
4518 * Read and save microcode version and date.
4519 */
4520 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
4521 asc_dvc->cfg->mcode_date);
4522 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
4523 asc_dvc->cfg->mcode_version);
4524
4525 /*
4526 * Set the chip type to indicate the ASC3550.
4527 */
4528 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550);
4529
4530 /*
4531 * If the PCI Configuration Command Register "Parity Error Response
4532 * Control" Bit was clear (0), then set the microcode variable
4533 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
4534 * to ignore DMA parity errors.
4535 */
4536 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
4537 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
4538 word |= CONTROL_FLAG_IGNORE_PERR;
4539 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
4540 }
4541
4542 /*
4543 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO
4544 * threshold of 128 bytes. This register is only accessible to the host.
4545 */
4546 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
4547 START_CTL_EMFU | READ_CMD_MRM);
4548
4549 /*
4550 * Microcode operating variables for WDTR, SDTR, and command tag
4551 * queuing will be set in slave_configure() based on what a
4552 * device reports it is capable of in Inquiry byte 7.
4553 *
4554 * If SCSI Bus Resets have been disabled, then directly set
4555 * SDTR and WDTR from the EEPROM configuration. This will allow
4556 * the BIOS and warm boot to work without a SCSI bus hang on
4557 * the Inquiry caused by host and target mismatched DTR values.
4558 * Without the SCSI Bus Reset, before an Inquiry a device can't
4559 * be assumed to be in Asynchronous, Narrow mode.
4560 */
4561 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
4562 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
4563 asc_dvc->wdtr_able);
4564 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
4565 asc_dvc->sdtr_able);
4566 }
4567
4568 /*
4569 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
4570 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
4571 * bitmask. These values determine the maximum SDTR speed negotiated
4572 * with a device.
4573 *
4574 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
4575 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
4576 * without determining here whether the device supports SDTR.
4577 *
4578 * 4-bit speed SDTR speed name
4579 * =========== ===============
4580 * 0000b (0x0) SDTR disabled
4581 * 0001b (0x1) 5 Mhz
4582 * 0010b (0x2) 10 Mhz
4583 * 0011b (0x3) 20 Mhz (Ultra)
4584 * 0100b (0x4) 40 Mhz (LVD/Ultra2)
4585 * 0101b (0x5) 80 Mhz (LVD2/Ultra3)
4586 * 0110b (0x6) Undefined
4587 * .
4588 * 1111b (0xF) Undefined
4589 */
4590 word = 0;
4591 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4592 if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able) {
4593 /* Set Ultra speed for TID 'tid'. */
4594 word |= (0x3 << (4 * (tid % 4)));
4595 } else {
4596 /* Set Fast speed for TID 'tid'. */
4597 word |= (0x2 << (4 * (tid % 4)));
4598 }
4599 if (tid == 3) { /* Check if done with sdtr_speed1. */
4600 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word);
4601 word = 0;
4602 } else if (tid == 7) { /* Check if done with sdtr_speed2. */
4603 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word);
4604 word = 0;
4605 } else if (tid == 11) { /* Check if done with sdtr_speed3. */
4606 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word);
4607 word = 0;
4608 } else if (tid == 15) { /* Check if done with sdtr_speed4. */
4609 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word);
4610 /* End of loop. */
4611 }
4612 }
4613
4614 /*
4615 * Set microcode operating variable for the disconnect per TID bitmask.
4616 */
4617 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
4618 asc_dvc->cfg->disc_enable);
4619
4620 /*
4621 * Set SCSI_CFG0 Microcode Default Value.
4622 *
4623 * The microcode will set the SCSI_CFG0 register using this value
4624 * after it is started below.
4625 */
4626 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
4627 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
4628 asc_dvc->chip_scsi_id);
4629
4630 /*
4631 * Determine SCSI_CFG1 Microcode Default Value.
4632 *
4633 * The microcode will set the SCSI_CFG1 register using this value
4634 * after it is started below.
4635 */
4636
4637 /* Read current SCSI_CFG1 Register value. */
4638 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
4639
4640 /*
4641 * If all three connectors are in use, return an error.
4642 */
4643 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
4644 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) {
4645 asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION;
4646 return ADV_ERROR;
4647 }
4648
4649 /*
4650 * If the internal narrow cable is reversed all of the SCSI_CTRL
4651 * register signals will be set. Check for and return an error if
4652 * this condition is found.
4653 */
4654 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
4655 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
4656 return ADV_ERROR;
4657 }
4658
4659 /*
4660 * If this is a differential board and a single-ended device
4661 * is attached to one of the connectors, return an error.
4662 */
4663 if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0) {
4664 asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE;
4665 return ADV_ERROR;
4666 }
4667
4668 /*
4669 * If automatic termination control is enabled, then set the
4670 * termination value based on a table listed in a_condor.h.
4671 *
4672 * If manual termination was specified with an EEPROM setting
4673 * then 'termination' was set-up in AdvInitFrom3550EEPROM() and
4674 * is ready to be 'ored' into SCSI_CFG1.
4675 */
4676 if (asc_dvc->cfg->termination == 0) {
4677 /*
4678 * The software always controls termination by setting TERM_CTL_SEL.
4679 * If TERM_CTL_SEL were set to 0, the hardware would set termination.
4680 */
4681 asc_dvc->cfg->termination |= TERM_CTL_SEL;
4682
4683 switch (scsi_cfg1 & CABLE_DETECT) {
4684 /* TERM_CTL_H: on, TERM_CTL_L: on */
4685 case 0x3:
4686 case 0x7:
4687 case 0xB:
4688 case 0xD:
4689 case 0xE:
4690 case 0xF:
4691 asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L);
4692 break;
4693
4694 /* TERM_CTL_H: on, TERM_CTL_L: off */
4695 case 0x1:
4696 case 0x5:
4697 case 0x9:
4698 case 0xA:
4699 case 0xC:
4700 asc_dvc->cfg->termination |= TERM_CTL_H;
4701 break;
4702
4703 /* TERM_CTL_H: off, TERM_CTL_L: off */
4704 case 0x2:
4705 case 0x6:
4706 break;
4707 }
4708 }
4709
4710 /*
4711 * Clear any set TERM_CTL_H and TERM_CTL_L bits.
4712 */
4713 scsi_cfg1 &= ~TERM_CTL;
4714
4715 /*
4716 * Invert the TERM_CTL_H and TERM_CTL_L bits and then
4717 * set 'scsi_cfg1'. The TERM_POL bit does not need to be
4718 * referenced, because the hardware internally inverts
4719 * the Termination High and Low bits if TERM_POL is set.
4720 */
4721 scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL));
4722
4723 /*
4724 * Set SCSI_CFG1 Microcode Default Value
4725 *
4726 * Set filter value and possibly modified termination control
4727 * bits in the Microcode SCSI_CFG1 Register Value.
4728 *
4729 * The microcode will set the SCSI_CFG1 register using this value
4730 * after it is started below.
4731 */
4732 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1,
4733 FLTR_DISABLE | scsi_cfg1);
4734
4735 /*
4736 * Set MEM_CFG Microcode Default Value
4737 *
4738 * The microcode will set the MEM_CFG register using this value
4739 * after it is started below.
4740 *
4741 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
4742 * are defined.
4743 *
4744 * ASC-3550 has 8KB internal memory.
4745 */
4746 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
4747 BIOS_EN | RAM_SZ_8KB);
4748
4749 /*
4750 * Set SEL_MASK Microcode Default Value
4751 *
4752 * The microcode will set the SEL_MASK register using this value
4753 * after it is started below.
4754 */
4755 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
4756 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
4757
4758 AdvBuildCarrierFreelist(asc_dvc);
4759
4760 /*
4761 * Set-up the Host->RISC Initiator Command Queue (ICQ).
4762 */
4763
4764 asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc);
4765 if (!asc_dvc->icq_sp) {
4766 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
4767 return ADV_ERROR;
4768 }
4769
4770 /*
4771 * Set RISC ICQ physical address start value.
4772 */
4773 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
4774
4775 /*
4776 * Set-up the RISC->Host Initiator Response Queue (IRQ).
4777 */
4778 asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc);
4779 if (!asc_dvc->irq_sp) {
4780 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
4781 return ADV_ERROR;
4782 }
4783
4784 /*
4785 * Set RISC IRQ physical address start value.
4786 */
4787 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
4788 asc_dvc->carr_pending_cnt = 0;
4789
4790 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
4791 (ADV_INTR_ENABLE_HOST_INTR |
4792 ADV_INTR_ENABLE_GLOBAL_INTR));
4793
4794 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
4795 AdvWriteWordRegister(iop_base, IOPW_PC, word);
4796
4797 /* finally, finally, gentlemen, start your engine */
4798 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
4799
4800 /*
4801 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
4802 * Resets should be performed. The RISC has to be running
4803 * to issue a SCSI Bus Reset.
4804 */
4805 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
4806 /*
4807 * If the BIOS Signature is present in memory, restore the
4808 * BIOS Handshake Configuration Table and do not perform
4809 * a SCSI Bus Reset.
4810 */
4811 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
4812 0x55AA) {
4813 /*
4814 * Restore per TID negotiated values.
4815 */
4816 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4817 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4818 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
4819 tagqng_able);
4820 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4821 AdvWriteByteLram(iop_base,
4822 ASC_MC_NUMBER_OF_MAX_CMD + tid,
4823 max_cmd[tid]);
4824 }
4825 } else {
4826 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
4827 warn_code = ASC_WARN_BUSRESET_ERROR;
4828 }
4829 }
4830 }
4831
4832 return warn_code;
4833 }
4834
4835 /*
4836 * Initialize the ASC-38C0800.
4837 *
4838 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
4839 *
4840 * For a non-fatal error return a warning code. If there are no warnings
4841 * then 0 is returned.
4842 *
4843 * Needed after initialization for error recovery.
4844 */
4845 static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc)
4846 {
4847 const struct firmware *fw;
4848 const char fwname[] = "advansys/38C0800.bin";
4849 AdvPortAddr iop_base;
4850 ushort warn_code;
4851 int begin_addr;
4852 int end_addr;
4853 ushort code_sum;
4854 int word;
4855 int i;
4856 int err;
4857 unsigned long chksum;
4858 ushort scsi_cfg1;
4859 uchar byte;
4860 uchar tid;
4861 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
4862 ushort wdtr_able, sdtr_able, tagqng_able;
4863 uchar max_cmd[ADV_MAX_TID + 1];
4864
4865 /* If there is already an error, don't continue. */
4866 if (asc_dvc->err_code != 0)
4867 return ADV_ERROR;
4868
4869 /*
4870 * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800.
4871 */
4872 if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800) {
4873 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
4874 return ADV_ERROR;
4875 }
4876
4877 warn_code = 0;
4878 iop_base = asc_dvc->iop_base;
4879
4880 /*
4881 * Save the RISC memory BIOS region before writing the microcode.
4882 * The BIOS may already be loaded and using its RISC LRAM region
4883 * so its region must be saved and restored.
4884 *
4885 * Note: This code makes the assumption, which is currently true,
4886 * that a chip reset does not clear RISC LRAM.
4887 */
4888 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4889 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4890 bios_mem[i]);
4891 }
4892
4893 /*
4894 * Save current per TID negotiated values.
4895 */
4896 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4897 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4898 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
4899 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4900 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
4901 max_cmd[tid]);
4902 }
4903
4904 /*
4905 * RAM BIST (RAM Built-In Self Test)
4906 *
4907 * Address : I/O base + offset 0x38h register (byte).
4908 * Function: Bit 7-6(RW) : RAM mode
4909 * Normal Mode : 0x00
4910 * Pre-test Mode : 0x40
4911 * RAM Test Mode : 0x80
4912 * Bit 5 : unused
4913 * Bit 4(RO) : Done bit
4914 * Bit 3-0(RO) : Status
4915 * Host Error : 0x08
4916 * Int_RAM Error : 0x04
4917 * RISC Error : 0x02
4918 * SCSI Error : 0x01
4919 * No Error : 0x00
4920 *
4921 * Note: RAM BIST code should be put right here, before loading the
4922 * microcode and after saving the RISC memory BIOS region.
4923 */
4924
4925 /*
4926 * LRAM Pre-test
4927 *
4928 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
4929 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
4930 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
4931 * to NORMAL_MODE, return an error too.
4932 */
4933 for (i = 0; i < 2; i++) {
4934 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
4935 mdelay(10); /* Wait for 10ms before reading back. */
4936 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
4937 if ((byte & RAM_TEST_DONE) == 0
4938 || (byte & 0x0F) != PRE_TEST_VALUE) {
4939 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
4940 return ADV_ERROR;
4941 }
4942
4943 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
4944 mdelay(10); /* Wait for 10ms before reading back. */
4945 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
4946 != NORMAL_VALUE) {
4947 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
4948 return ADV_ERROR;
4949 }
4950 }
4951
4952 /*
4953 * LRAM Test - It takes about 1.5 ms to run through the test.
4954 *
4955 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
4956 * If Done bit not set or Status not 0, save register byte, set the
4957 * err_code, and return an error.
4958 */
4959 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
4960 mdelay(10); /* Wait for 10ms before checking status. */
4961
4962 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
4963 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
4964 /* Get here if Done bit not set or Status not 0. */
4965 asc_dvc->bist_err_code = byte; /* for BIOS display message */
4966 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
4967 return ADV_ERROR;
4968 }
4969
4970 /* We need to reset back to normal mode after LRAM test passes. */
4971 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
4972
4973 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4974 if (err) {
4975 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4976 fwname, err);
4977 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
4978 return err;
4979 }
4980 if (fw->size < 4) {
4981 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4982 fw->size, fwname);
4983 release_firmware(fw);
4984 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
4985 return -EINVAL;
4986 }
4987 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4988 (fw->data[1] << 8) | fw->data[0];
4989 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
4990 fw->size - 4, ADV_38C0800_MEMSIZE,
4991 chksum);
4992 release_firmware(fw);
4993 if (asc_dvc->err_code)
4994 return ADV_ERROR;
4995
4996 /*
4997 * Restore the RISC memory BIOS region.
4998 */
4999 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5000 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5001 bios_mem[i]);
5002 }
5003
5004 /*
5005 * Calculate and write the microcode code checksum to the microcode
5006 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
5007 */
5008 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
5009 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
5010 code_sum = 0;
5011 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
5012 for (word = begin_addr; word < end_addr; word += 2) {
5013 code_sum += AdvReadWordAutoIncLram(iop_base);
5014 }
5015 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
5016
5017 /*
5018 * Read microcode version and date.
5019 */
5020 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
5021 asc_dvc->cfg->mcode_date);
5022 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
5023 asc_dvc->cfg->mcode_version);
5024
5025 /*
5026 * Set the chip type to indicate the ASC38C0800.
5027 */
5028 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800);
5029
5030 /*
5031 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
5032 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
5033 * cable detection and then we are able to read C_DET[3:0].
5034 *
5035 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
5036 * Microcode Default Value' section below.
5037 */
5038 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5039 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
5040 scsi_cfg1 | DIS_TERM_DRV);
5041
5042 /*
5043 * If the PCI Configuration Command Register "Parity Error Response
5044 * Control" Bit was clear (0), then set the microcode variable
5045 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
5046 * to ignore DMA parity errors.
5047 */
5048 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
5049 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5050 word |= CONTROL_FLAG_IGNORE_PERR;
5051 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5052 }
5053
5054 /*
5055 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2]
5056 * bits for the default FIFO threshold.
5057 *
5058 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
5059 *
5060 * For DMA Errata #4 set the BC_THRESH_ENB bit.
5061 */
5062 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
5063 BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH |
5064 READ_CMD_MRM);
5065
5066 /*
5067 * Microcode operating variables for WDTR, SDTR, and command tag
5068 * queuing will be set in slave_configure() based on what a
5069 * device reports it is capable of in Inquiry byte 7.
5070 *
5071 * If SCSI Bus Resets have been disabled, then directly set
5072 * SDTR and WDTR from the EEPROM configuration. This will allow
5073 * the BIOS and warm boot to work without a SCSI bus hang on
5074 * the Inquiry caused by host and target mismatched DTR values.
5075 * Without the SCSI Bus Reset, before an Inquiry a device can't
5076 * be assumed to be in Asynchronous, Narrow mode.
5077 */
5078 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
5079 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
5080 asc_dvc->wdtr_able);
5081 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
5082 asc_dvc->sdtr_able);
5083 }
5084
5085 /*
5086 * Set microcode operating variables for DISC and SDTR_SPEED1,
5087 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
5088 * configuration values.
5089 *
5090 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
5091 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
5092 * without determining here whether the device supports SDTR.
5093 */
5094 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
5095 asc_dvc->cfg->disc_enable);
5096 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
5097 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
5098 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
5099 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
5100
5101 /*
5102 * Set SCSI_CFG0 Microcode Default Value.
5103 *
5104 * The microcode will set the SCSI_CFG0 register using this value
5105 * after it is started below.
5106 */
5107 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
5108 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
5109 asc_dvc->chip_scsi_id);
5110
5111 /*
5112 * Determine SCSI_CFG1 Microcode Default Value.
5113 *
5114 * The microcode will set the SCSI_CFG1 register using this value
5115 * after it is started below.
5116 */
5117
5118 /* Read current SCSI_CFG1 Register value. */
5119 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5120
5121 /*
5122 * If the internal narrow cable is reversed all of the SCSI_CTRL
5123 * register signals will be set. Check for and return an error if
5124 * this condition is found.
5125 */
5126 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
5127 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
5128 return ADV_ERROR;
5129 }
5130
5131 /*
5132 * All kind of combinations of devices attached to one of four
5133 * connectors are acceptable except HVD device attached. For example,
5134 * LVD device can be attached to SE connector while SE device attached
5135 * to LVD connector. If LVD device attached to SE connector, it only
5136 * runs up to Ultra speed.
5137 *
5138 * If an HVD device is attached to one of LVD connectors, return an
5139 * error. However, there is no way to detect HVD device attached to
5140 * SE connectors.
5141 */
5142 if (scsi_cfg1 & HVD) {
5143 asc_dvc->err_code = ASC_IERR_HVD_DEVICE;
5144 return ADV_ERROR;
5145 }
5146
5147 /*
5148 * If either SE or LVD automatic termination control is enabled, then
5149 * set the termination value based on a table listed in a_condor.h.
5150 *
5151 * If manual termination was specified with an EEPROM setting then
5152 * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready
5153 * to be 'ored' into SCSI_CFG1.
5154 */
5155 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
5156 /* SE automatic termination control is enabled. */
5157 switch (scsi_cfg1 & C_DET_SE) {
5158 /* TERM_SE_HI: on, TERM_SE_LO: on */
5159 case 0x1:
5160 case 0x2:
5161 case 0x3:
5162 asc_dvc->cfg->termination |= TERM_SE;
5163 break;
5164
5165 /* TERM_SE_HI: on, TERM_SE_LO: off */
5166 case 0x0:
5167 asc_dvc->cfg->termination |= TERM_SE_HI;
5168 break;
5169 }
5170 }
5171
5172 if ((asc_dvc->cfg->termination & TERM_LVD) == 0) {
5173 /* LVD automatic termination control is enabled. */
5174 switch (scsi_cfg1 & C_DET_LVD) {
5175 /* TERM_LVD_HI: on, TERM_LVD_LO: on */
5176 case 0x4:
5177 case 0x8:
5178 case 0xC:
5179 asc_dvc->cfg->termination |= TERM_LVD;
5180 break;
5181
5182 /* TERM_LVD_HI: off, TERM_LVD_LO: off */
5183 case 0x0:
5184 break;
5185 }
5186 }
5187
5188 /*
5189 * Clear any set TERM_SE and TERM_LVD bits.
5190 */
5191 scsi_cfg1 &= (~TERM_SE & ~TERM_LVD);
5192
5193 /*
5194 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
5195 */
5196 scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0);
5197
5198 /*
5199 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE
5200 * bits and set possibly modified termination control bits in the
5201 * Microcode SCSI_CFG1 Register Value.
5202 */
5203 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE);
5204
5205 /*
5206 * Set SCSI_CFG1 Microcode Default Value
5207 *
5208 * Set possibly modified termination control and reset DIS_TERM_DRV
5209 * bits in the Microcode SCSI_CFG1 Register Value.
5210 *
5211 * The microcode will set the SCSI_CFG1 register using this value
5212 * after it is started below.
5213 */
5214 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
5215
5216 /*
5217 * Set MEM_CFG Microcode Default Value
5218 *
5219 * The microcode will set the MEM_CFG register using this value
5220 * after it is started below.
5221 *
5222 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
5223 * are defined.
5224 *
5225 * ASC-38C0800 has 16KB internal memory.
5226 */
5227 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5228 BIOS_EN | RAM_SZ_16KB);
5229
5230 /*
5231 * Set SEL_MASK Microcode Default Value
5232 *
5233 * The microcode will set the SEL_MASK register using this value
5234 * after it is started below.
5235 */
5236 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
5237 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
5238
5239 AdvBuildCarrierFreelist(asc_dvc);
5240
5241 /*
5242 * Set-up the Host->RISC Initiator Command Queue (ICQ).
5243 */
5244
5245 asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc);
5246 if (!asc_dvc->icq_sp) {
5247 ASC_DBG(0, "Failed to get ICQ carrier\n");
5248 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5249 return ADV_ERROR;
5250 }
5251
5252 /*
5253 * Set RISC ICQ physical address start value.
5254 * carr_pa is LE, must be native before write
5255 */
5256 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
5257
5258 /*
5259 * Set-up the RISC->Host Initiator Response Queue (IRQ).
5260 */
5261 asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc);
5262 if (!asc_dvc->irq_sp) {
5263 ASC_DBG(0, "Failed to get IRQ carrier\n");
5264 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5265 return ADV_ERROR;
5266 }
5267
5268 /*
5269 * Set RISC IRQ physical address start value.
5270 *
5271 * carr_pa is LE, must be native before write *
5272 */
5273 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
5274 asc_dvc->carr_pending_cnt = 0;
5275
5276 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
5277 (ADV_INTR_ENABLE_HOST_INTR |
5278 ADV_INTR_ENABLE_GLOBAL_INTR));
5279
5280 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
5281 AdvWriteWordRegister(iop_base, IOPW_PC, word);
5282
5283 /* finally, finally, gentlemen, start your engine */
5284 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
5285
5286 /*
5287 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
5288 * Resets should be performed. The RISC has to be running
5289 * to issue a SCSI Bus Reset.
5290 */
5291 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
5292 /*
5293 * If the BIOS Signature is present in memory, restore the
5294 * BIOS Handshake Configuration Table and do not perform
5295 * a SCSI Bus Reset.
5296 */
5297 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
5298 0x55AA) {
5299 /*
5300 * Restore per TID negotiated values.
5301 */
5302 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5303 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5304 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
5305 tagqng_able);
5306 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5307 AdvWriteByteLram(iop_base,
5308 ASC_MC_NUMBER_OF_MAX_CMD + tid,
5309 max_cmd[tid]);
5310 }
5311 } else {
5312 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
5313 warn_code = ASC_WARN_BUSRESET_ERROR;
5314 }
5315 }
5316 }
5317
5318 return warn_code;
5319 }
5320
5321 /*
5322 * Initialize the ASC-38C1600.
5323 *
5324 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
5325 *
5326 * For a non-fatal error return a warning code. If there are no warnings
5327 * then 0 is returned.
5328 *
5329 * Needed after initialization for error recovery.
5330 */
5331 static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc)
5332 {
5333 const struct firmware *fw;
5334 const char fwname[] = "advansys/38C1600.bin";
5335 AdvPortAddr iop_base;
5336 ushort warn_code;
5337 int begin_addr;
5338 int end_addr;
5339 ushort code_sum;
5340 long word;
5341 int i;
5342 int err;
5343 unsigned long chksum;
5344 ushort scsi_cfg1;
5345 uchar byte;
5346 uchar tid;
5347 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
5348 ushort wdtr_able, sdtr_able, ppr_able, tagqng_able;
5349 uchar max_cmd[ASC_MAX_TID + 1];
5350
5351 /* If there is already an error, don't continue. */
5352 if (asc_dvc->err_code != 0) {
5353 return ADV_ERROR;
5354 }
5355
5356 /*
5357 * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600.
5358 */
5359 if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
5360 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
5361 return ADV_ERROR;
5362 }
5363
5364 warn_code = 0;
5365 iop_base = asc_dvc->iop_base;
5366
5367 /*
5368 * Save the RISC memory BIOS region before writing the microcode.
5369 * The BIOS may already be loaded and using its RISC LRAM region
5370 * so its region must be saved and restored.
5371 *
5372 * Note: This code makes the assumption, which is currently true,
5373 * that a chip reset does not clear RISC LRAM.
5374 */
5375 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5376 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5377 bios_mem[i]);
5378 }
5379
5380 /*
5381 * Save current per TID negotiated values.
5382 */
5383 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5384 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5385 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5386 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5387 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
5388 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5389 max_cmd[tid]);
5390 }
5391
5392 /*
5393 * RAM BIST (Built-In Self Test)
5394 *
5395 * Address : I/O base + offset 0x38h register (byte).
5396 * Function: Bit 7-6(RW) : RAM mode
5397 * Normal Mode : 0x00
5398 * Pre-test Mode : 0x40
5399 * RAM Test Mode : 0x80
5400 * Bit 5 : unused
5401 * Bit 4(RO) : Done bit
5402 * Bit 3-0(RO) : Status
5403 * Host Error : 0x08
5404 * Int_RAM Error : 0x04
5405 * RISC Error : 0x02
5406 * SCSI Error : 0x01
5407 * No Error : 0x00
5408 *
5409 * Note: RAM BIST code should be put right here, before loading the
5410 * microcode and after saving the RISC memory BIOS region.
5411 */
5412
5413 /*
5414 * LRAM Pre-test
5415 *
5416 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
5417 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
5418 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
5419 * to NORMAL_MODE, return an error too.
5420 */
5421 for (i = 0; i < 2; i++) {
5422 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
5423 mdelay(10); /* Wait for 10ms before reading back. */
5424 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5425 if ((byte & RAM_TEST_DONE) == 0
5426 || (byte & 0x0F) != PRE_TEST_VALUE) {
5427 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5428 return ADV_ERROR;
5429 }
5430
5431 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5432 mdelay(10); /* Wait for 10ms before reading back. */
5433 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
5434 != NORMAL_VALUE) {
5435 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5436 return ADV_ERROR;
5437 }
5438 }
5439
5440 /*
5441 * LRAM Test - It takes about 1.5 ms to run through the test.
5442 *
5443 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
5444 * If Done bit not set or Status not 0, save register byte, set the
5445 * err_code, and return an error.
5446 */
5447 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
5448 mdelay(10); /* Wait for 10ms before checking status. */
5449
5450 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5451 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
5452 /* Get here if Done bit not set or Status not 0. */
5453 asc_dvc->bist_err_code = byte; /* for BIOS display message */
5454 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
5455 return ADV_ERROR;
5456 }
5457
5458 /* We need to reset back to normal mode after LRAM test passes. */
5459 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5460
5461 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
5462 if (err) {
5463 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
5464 fwname, err);
5465 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5466 return err;
5467 }
5468 if (fw->size < 4) {
5469 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
5470 fw->size, fwname);
5471 release_firmware(fw);
5472 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5473 return -EINVAL;
5474 }
5475 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
5476 (fw->data[1] << 8) | fw->data[0];
5477 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
5478 fw->size - 4, ADV_38C1600_MEMSIZE,
5479 chksum);
5480 release_firmware(fw);
5481 if (asc_dvc->err_code)
5482 return ADV_ERROR;
5483
5484 /*
5485 * Restore the RISC memory BIOS region.
5486 */
5487 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5488 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5489 bios_mem[i]);
5490 }
5491
5492 /*
5493 * Calculate and write the microcode code checksum to the microcode
5494 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
5495 */
5496 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
5497 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
5498 code_sum = 0;
5499 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
5500 for (word = begin_addr; word < end_addr; word += 2) {
5501 code_sum += AdvReadWordAutoIncLram(iop_base);
5502 }
5503 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
5504
5505 /*
5506 * Read microcode version and date.
5507 */
5508 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
5509 asc_dvc->cfg->mcode_date);
5510 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
5511 asc_dvc->cfg->mcode_version);
5512
5513 /*
5514 * Set the chip type to indicate the ASC38C1600.
5515 */
5516 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600);
5517
5518 /*
5519 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
5520 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
5521 * cable detection and then we are able to read C_DET[3:0].
5522 *
5523 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
5524 * Microcode Default Value' section below.
5525 */
5526 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5527 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
5528 scsi_cfg1 | DIS_TERM_DRV);
5529
5530 /*
5531 * If the PCI Configuration Command Register "Parity Error Response
5532 * Control" Bit was clear (0), then set the microcode variable
5533 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
5534 * to ignore DMA parity errors.
5535 */
5536 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
5537 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5538 word |= CONTROL_FLAG_IGNORE_PERR;
5539 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5540 }
5541
5542 /*
5543 * If the BIOS control flag AIPP (Asynchronous Information
5544 * Phase Protection) disable bit is not set, then set the firmware
5545 * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable
5546 * AIPP checking and encoding.
5547 */
5548 if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) {
5549 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5550 word |= CONTROL_FLAG_ENABLE_AIPP;
5551 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5552 }
5553
5554 /*
5555 * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4],
5556 * and START_CTL_TH [3:2].
5557 */
5558 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
5559 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
5560
5561 /*
5562 * Microcode operating variables for WDTR, SDTR, and command tag
5563 * queuing will be set in slave_configure() based on what a
5564 * device reports it is capable of in Inquiry byte 7.
5565 *
5566 * If SCSI Bus Resets have been disabled, then directly set
5567 * SDTR and WDTR from the EEPROM configuration. This will allow
5568 * the BIOS and warm boot to work without a SCSI bus hang on
5569 * the Inquiry caused by host and target mismatched DTR values.
5570 * Without the SCSI Bus Reset, before an Inquiry a device can't
5571 * be assumed to be in Asynchronous, Narrow mode.
5572 */
5573 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
5574 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
5575 asc_dvc->wdtr_able);
5576 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
5577 asc_dvc->sdtr_able);
5578 }
5579
5580 /*
5581 * Set microcode operating variables for DISC and SDTR_SPEED1,
5582 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
5583 * configuration values.
5584 *
5585 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
5586 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
5587 * without determining here whether the device supports SDTR.
5588 */
5589 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
5590 asc_dvc->cfg->disc_enable);
5591 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
5592 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
5593 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
5594 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
5595
5596 /*
5597 * Set SCSI_CFG0 Microcode Default Value.
5598 *
5599 * The microcode will set the SCSI_CFG0 register using this value
5600 * after it is started below.
5601 */
5602 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
5603 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
5604 asc_dvc->chip_scsi_id);
5605
5606 /*
5607 * Calculate SCSI_CFG1 Microcode Default Value.
5608 *
5609 * The microcode will set the SCSI_CFG1 register using this value
5610 * after it is started below.
5611 *
5612 * Each ASC-38C1600 function has only two cable detect bits.
5613 * The bus mode override bits are in IOPB_SOFT_OVER_WR.
5614 */
5615 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5616
5617 /*
5618 * If the cable is reversed all of the SCSI_CTRL register signals
5619 * will be set. Check for and return an error if this condition is
5620 * found.
5621 */
5622 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
5623 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
5624 return ADV_ERROR;
5625 }
5626
5627 /*
5628 * Each ASC-38C1600 function has two connectors. Only an HVD device
5629 * can not be connected to either connector. An LVD device or SE device
5630 * may be connected to either connecor. If an SE device is connected,
5631 * then at most Ultra speed (20 Mhz) can be used on both connectors.
5632 *
5633 * If an HVD device is attached, return an error.
5634 */
5635 if (scsi_cfg1 & HVD) {
5636 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
5637 return ADV_ERROR;
5638 }
5639
5640 /*
5641 * Each function in the ASC-38C1600 uses only the SE cable detect and
5642 * termination because there are two connectors for each function. Each
5643 * function may use either LVD or SE mode. Corresponding the SE automatic
5644 * termination control EEPROM bits are used for each function. Each
5645 * function has its own EEPROM. If SE automatic control is enabled for
5646 * the function, then set the termination value based on a table listed
5647 * in a_condor.h.
5648 *
5649 * If manual termination is specified in the EEPROM for the function,
5650 * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is
5651 * ready to be 'ored' into SCSI_CFG1.
5652 */
5653 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
5654 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
5655 /* SE automatic termination control is enabled. */
5656 switch (scsi_cfg1 & C_DET_SE) {
5657 /* TERM_SE_HI: on, TERM_SE_LO: on */
5658 case 0x1:
5659 case 0x2:
5660 case 0x3:
5661 asc_dvc->cfg->termination |= TERM_SE;
5662 break;
5663
5664 case 0x0:
5665 if (PCI_FUNC(pdev->devfn) == 0) {
5666 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
5667 } else {
5668 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
5669 asc_dvc->cfg->termination |= TERM_SE_HI;
5670 }
5671 break;
5672 }
5673 }
5674
5675 /*
5676 * Clear any set TERM_SE bits.
5677 */
5678 scsi_cfg1 &= ~TERM_SE;
5679
5680 /*
5681 * Invert the TERM_SE bits and then set 'scsi_cfg1'.
5682 */
5683 scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE);
5684
5685 /*
5686 * Clear Big Endian and Terminator Polarity bits and set possibly
5687 * modified termination control bits in the Microcode SCSI_CFG1
5688 * Register Value.
5689 *
5690 * Big Endian bit is not used even on big endian machines.
5691 */
5692 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL);
5693
5694 /*
5695 * Set SCSI_CFG1 Microcode Default Value
5696 *
5697 * Set possibly modified termination control bits in the Microcode
5698 * SCSI_CFG1 Register Value.
5699 *
5700 * The microcode will set the SCSI_CFG1 register using this value
5701 * after it is started below.
5702 */
5703 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
5704
5705 /*
5706 * Set MEM_CFG Microcode Default Value
5707 *
5708 * The microcode will set the MEM_CFG register using this value
5709 * after it is started below.
5710 *
5711 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
5712 * are defined.
5713 *
5714 * ASC-38C1600 has 32KB internal memory.
5715 *
5716 * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come
5717 * out a special 16K Adv Library and Microcode version. After the issue
5718 * resolved, we should turn back to the 32K support. Both a_condor.h and
5719 * mcode.sas files also need to be updated.
5720 *
5721 * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5722 * BIOS_EN | RAM_SZ_32KB);
5723 */
5724 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5725 BIOS_EN | RAM_SZ_16KB);
5726
5727 /*
5728 * Set SEL_MASK Microcode Default Value
5729 *
5730 * The microcode will set the SEL_MASK register using this value
5731 * after it is started below.
5732 */
5733 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
5734 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
5735
5736 AdvBuildCarrierFreelist(asc_dvc);
5737
5738 /*
5739 * Set-up the Host->RISC Initiator Command Queue (ICQ).
5740 */
5741 asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc);
5742 if (!asc_dvc->icq_sp) {
5743 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5744 return ADV_ERROR;
5745 }
5746
5747 /*
5748 * Set RISC ICQ physical address start value. Initialize the
5749 * COMMA register to the same value otherwise the RISC will
5750 * prematurely detect a command is available.
5751 */
5752 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
5753 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
5754 le32_to_cpu(asc_dvc->icq_sp->carr_pa));
5755
5756 /*
5757 * Set-up the RISC->Host Initiator Response Queue (IRQ).
5758 */
5759 asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc);
5760 if (!asc_dvc->irq_sp) {
5761 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5762 return ADV_ERROR;
5763 }
5764
5765 /*
5766 * Set RISC IRQ physical address start value.
5767 */
5768 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
5769 asc_dvc->carr_pending_cnt = 0;
5770
5771 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
5772 (ADV_INTR_ENABLE_HOST_INTR |
5773 ADV_INTR_ENABLE_GLOBAL_INTR));
5774 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
5775 AdvWriteWordRegister(iop_base, IOPW_PC, word);
5776
5777 /* finally, finally, gentlemen, start your engine */
5778 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
5779
5780 /*
5781 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
5782 * Resets should be performed. The RISC has to be running
5783 * to issue a SCSI Bus Reset.
5784 */
5785 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
5786 /*
5787 * If the BIOS Signature is present in memory, restore the
5788 * per TID microcode operating variables.
5789 */
5790 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
5791 0x55AA) {
5792 /*
5793 * Restore per TID negotiated values.
5794 */
5795 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5796 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5797 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5798 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
5799 tagqng_able);
5800 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
5801 AdvWriteByteLram(iop_base,
5802 ASC_MC_NUMBER_OF_MAX_CMD + tid,
5803 max_cmd[tid]);
5804 }
5805 } else {
5806 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
5807 warn_code = ASC_WARN_BUSRESET_ERROR;
5808 }
5809 }
5810 }
5811
5812 return warn_code;
5813 }
5814
5815 /*
5816 * Reset chip and SCSI Bus.
5817 *
5818 * Return Value:
5819 * ADV_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful.
5820 * ADV_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure.
5821 */
5822 static int AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc)
5823 {
5824 int status;
5825 ushort wdtr_able, sdtr_able, tagqng_able;
5826 ushort ppr_able = 0;
5827 uchar tid, max_cmd[ADV_MAX_TID + 1];
5828 AdvPortAddr iop_base;
5829 ushort bios_sig;
5830
5831 iop_base = asc_dvc->iop_base;
5832
5833 /*
5834 * Save current per TID negotiated values.
5835 */
5836 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5837 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5838 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
5839 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5840 }
5841 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5842 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5843 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5844 max_cmd[tid]);
5845 }
5846
5847 /*
5848 * Force the AdvInitAsc3550/38C0800Driver() function to
5849 * perform a SCSI Bus Reset by clearing the BIOS signature word.
5850 * The initialization functions assumes a SCSI Bus Reset is not
5851 * needed if the BIOS signature word is present.
5852 */
5853 AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
5854 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0);
5855
5856 /*
5857 * Stop chip and reset it.
5858 */
5859 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP);
5860 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET);
5861 mdelay(100);
5862 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
5863 ADV_CTRL_REG_CMD_WR_IO_REG);
5864
5865 /*
5866 * Reset Adv Library error code, if any, and try
5867 * re-initializing the chip.
5868 */
5869 asc_dvc->err_code = 0;
5870 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
5871 status = AdvInitAsc38C1600Driver(asc_dvc);
5872 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
5873 status = AdvInitAsc38C0800Driver(asc_dvc);
5874 } else {
5875 status = AdvInitAsc3550Driver(asc_dvc);
5876 }
5877
5878 /* Translate initialization return value to status value. */
5879 if (status == 0) {
5880 status = ADV_TRUE;
5881 } else {
5882 status = ADV_FALSE;
5883 }
5884
5885 /*
5886 * Restore the BIOS signature word.
5887 */
5888 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
5889
5890 /*
5891 * Restore per TID negotiated values.
5892 */
5893 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5894 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5895 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
5896 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5897 }
5898 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5899 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5900 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5901 max_cmd[tid]);
5902 }
5903
5904 return status;
5905 }
5906
5907 /*
5908 * adv_async_callback() - Adv Library asynchronous event callback function.
5909 */
5910 static void adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code)
5911 {
5912 switch (code) {
5913 case ADV_ASYNC_SCSI_BUS_RESET_DET:
5914 /*
5915 * The firmware detected a SCSI Bus reset.
5916 */
5917 ASC_DBG(0, "ADV_ASYNC_SCSI_BUS_RESET_DET\n");
5918 break;
5919
5920 case ADV_ASYNC_RDMA_FAILURE:
5921 /*
5922 * Handle RDMA failure by resetting the SCSI Bus and
5923 * possibly the chip if it is unresponsive. Log the error
5924 * with a unique code.
5925 */
5926 ASC_DBG(0, "ADV_ASYNC_RDMA_FAILURE\n");
5927 AdvResetChipAndSB(adv_dvc_varp);
5928 break;
5929
5930 case ADV_HOST_SCSI_BUS_RESET:
5931 /*
5932 * Host generated SCSI bus reset occurred.
5933 */
5934 ASC_DBG(0, "ADV_HOST_SCSI_BUS_RESET\n");
5935 break;
5936
5937 default:
5938 ASC_DBG(0, "unknown code 0x%x\n", code);
5939 break;
5940 }
5941 }
5942
5943 /*
5944 * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR().
5945 *
5946 * Callback function for the Wide SCSI Adv Library.
5947 */
5948 static void adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp)
5949 {
5950 struct asc_board *boardp = adv_dvc_varp->drv_ptr;
5951 u32 srb_tag;
5952 adv_req_t *reqp;
5953 adv_sgblk_t *sgblkp;
5954 struct scsi_cmnd *scp;
5955 u32 resid_cnt;
5956 dma_addr_t sense_addr;
5957
5958 ASC_DBG(1, "adv_dvc_varp 0x%p, scsiqp 0x%p\n",
5959 adv_dvc_varp, scsiqp);
5960 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
5961
5962 /*
5963 * Get the adv_req_t structure for the command that has been
5964 * completed. The adv_req_t structure actually contains the
5965 * completed ADV_SCSI_REQ_Q structure.
5966 */
5967 srb_tag = le32_to_cpu(scsiqp->srb_tag);
5968 scp = scsi_host_find_tag(boardp->shost, scsiqp->srb_tag);
5969
5970 ASC_DBG(1, "scp 0x%p\n", scp);
5971 if (scp == NULL) {
5972 ASC_PRINT
5973 ("adv_isr_callback: scp is NULL; adv_req_t dropped.\n");
5974 return;
5975 }
5976 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
5977
5978 reqp = (adv_req_t *)scp->host_scribble;
5979 ASC_DBG(1, "reqp 0x%lx\n", (ulong)reqp);
5980 if (reqp == NULL) {
5981 ASC_PRINT("adv_isr_callback: reqp is NULL\n");
5982 return;
5983 }
5984 /*
5985 * Remove backreferences to avoid duplicate
5986 * command completions.
5987 */
5988 scp->host_scribble = NULL;
5989 reqp->cmndp = NULL;
5990
5991 ASC_STATS(boardp->shost, callback);
5992 ASC_DBG(1, "shost 0x%p\n", boardp->shost);
5993
5994 sense_addr = le32_to_cpu(scsiqp->sense_addr);
5995 dma_unmap_single(boardp->dev, sense_addr,
5996 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
5997
5998 /*
5999 * 'done_status' contains the command's ending status.
6000 */
6001 switch (scsiqp->done_status) {
6002 case QD_NO_ERROR:
6003 ASC_DBG(2, "QD_NO_ERROR\n");
6004 scp->result = 0;
6005
6006 /*
6007 * Check for an underrun condition.
6008 *
6009 * If there was no error and an underrun condition, then
6010 * then return the number of underrun bytes.
6011 */
6012 resid_cnt = le32_to_cpu(scsiqp->data_cnt);
6013 if (scsi_bufflen(scp) != 0 && resid_cnt != 0 &&
6014 resid_cnt <= scsi_bufflen(scp)) {
6015 ASC_DBG(1, "underrun condition %lu bytes\n",
6016 (ulong)resid_cnt);
6017 scsi_set_resid(scp, resid_cnt);
6018 }
6019 break;
6020
6021 case QD_WITH_ERROR:
6022 ASC_DBG(2, "QD_WITH_ERROR\n");
6023 switch (scsiqp->host_status) {
6024 case QHSTA_NO_ERROR:
6025 if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) {
6026 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
6027 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
6028 SCSI_SENSE_BUFFERSIZE);
6029 /*
6030 * Note: The 'status_byte()' macro used by
6031 * target drivers defined in scsi.h shifts the
6032 * status byte returned by host drivers right
6033 * by 1 bit. This is why target drivers also
6034 * use right shifted status byte definitions.
6035 * For instance target drivers use
6036 * CHECK_CONDITION, defined to 0x1, instead of
6037 * the SCSI defined check condition value of
6038 * 0x2. Host drivers are supposed to return
6039 * the status byte as it is defined by SCSI.
6040 */
6041 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
6042 STATUS_BYTE(scsiqp->scsi_status);
6043 } else {
6044 scp->result = STATUS_BYTE(scsiqp->scsi_status);
6045 }
6046 break;
6047
6048 default:
6049 /* Some other QHSTA error occurred. */
6050 ASC_DBG(1, "host_status 0x%x\n", scsiqp->host_status);
6051 scp->result = HOST_BYTE(DID_BAD_TARGET);
6052 break;
6053 }
6054 break;
6055
6056 case QD_ABORTED_BY_HOST:
6057 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
6058 scp->result =
6059 HOST_BYTE(DID_ABORT) | STATUS_BYTE(scsiqp->scsi_status);
6060 break;
6061
6062 default:
6063 ASC_DBG(1, "done_status 0x%x\n", scsiqp->done_status);
6064 scp->result =
6065 HOST_BYTE(DID_ERROR) | STATUS_BYTE(scsiqp->scsi_status);
6066 break;
6067 }
6068
6069 /*
6070 * If the 'init_tidmask' bit isn't already set for the target and the
6071 * current request finished normally, then set the bit for the target
6072 * to indicate that a device is present.
6073 */
6074 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
6075 scsiqp->done_status == QD_NO_ERROR &&
6076 scsiqp->host_status == QHSTA_NO_ERROR) {
6077 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
6078 }
6079
6080 asc_scsi_done(scp);
6081
6082 /*
6083 * Free all 'adv_sgblk_t' structures allocated for the request.
6084 */
6085 while ((sgblkp = reqp->sgblkp) != NULL) {
6086 /* Remove 'sgblkp' from the request list. */
6087 reqp->sgblkp = sgblkp->next_sgblkp;
6088
6089 dma_pool_free(boardp->adv_sgblk_pool, sgblkp,
6090 sgblkp->sg_addr);
6091 }
6092
6093 ASC_DBG(1, "done\n");
6094 }
6095
6096 /*
6097 * Adv Library Interrupt Service Routine
6098 *
6099 * This function is called by a driver's interrupt service routine.
6100 * The function disables and re-enables interrupts.
6101 *
6102 * When a microcode idle command is completed, the ADV_DVC_VAR
6103 * 'idle_cmd_done' field is set to ADV_TRUE.
6104 *
6105 * Note: AdvISR() can be called when interrupts are disabled or even
6106 * when there is no hardware interrupt condition present. It will
6107 * always check for completed idle commands and microcode requests.
6108 * This is an important feature that shouldn't be changed because it
6109 * allows commands to be completed from polling mode loops.
6110 *
6111 * Return:
6112 * ADV_TRUE(1) - interrupt was pending
6113 * ADV_FALSE(0) - no interrupt was pending
6114 */
6115 static int AdvISR(ADV_DVC_VAR *asc_dvc)
6116 {
6117 AdvPortAddr iop_base;
6118 uchar int_stat;
6119 ushort target_bit;
6120 ADV_CARR_T *free_carrp;
6121 __le32 irq_next_vpa;
6122 ADV_SCSI_REQ_Q *scsiq;
6123 adv_req_t *reqp;
6124
6125 iop_base = asc_dvc->iop_base;
6126
6127 /* Reading the register clears the interrupt. */
6128 int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG);
6129
6130 if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB |
6131 ADV_INTR_STATUS_INTRC)) == 0) {
6132 return ADV_FALSE;
6133 }
6134
6135 /*
6136 * Notify the driver of an asynchronous microcode condition by
6137 * calling the adv_async_callback function. The function
6138 * is passed the microcode ASC_MC_INTRB_CODE byte value.
6139 */
6140 if (int_stat & ADV_INTR_STATUS_INTRB) {
6141 uchar intrb_code;
6142
6143 AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code);
6144
6145 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
6146 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
6147 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE &&
6148 asc_dvc->carr_pending_cnt != 0) {
6149 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
6150 ADV_TICKLE_A);
6151 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
6152 AdvWriteByteRegister(iop_base,
6153 IOPB_TICKLE,
6154 ADV_TICKLE_NOP);
6155 }
6156 }
6157 }
6158
6159 adv_async_callback(asc_dvc, intrb_code);
6160 }
6161
6162 /*
6163 * Check if the IRQ stopper carrier contains a completed request.
6164 */
6165 while (((irq_next_vpa =
6166 le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ADV_RQ_DONE) != 0) {
6167 /*
6168 * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure.
6169 * The RISC will have set 'areq_vpa' to a virtual address.
6170 *
6171 * The firmware will have copied the ADV_SCSI_REQ_Q.scsiq_ptr
6172 * field to the carrier ADV_CARR_T.areq_vpa field. The conversion
6173 * below complements the conversion of ADV_SCSI_REQ_Q.scsiq_ptr'
6174 * in AdvExeScsiQueue().
6175 */
6176 u32 pa_offset = le32_to_cpu(asc_dvc->irq_sp->areq_vpa);
6177 ASC_DBG(1, "irq_sp %p areq_vpa %u\n",
6178 asc_dvc->irq_sp, pa_offset);
6179 reqp = adv_get_reqp(asc_dvc, pa_offset);
6180 scsiq = &reqp->scsi_req_q;
6181
6182 /*
6183 * Request finished with good status and the queue was not
6184 * DMAed to host memory by the firmware. Set all status fields
6185 * to indicate good status.
6186 */
6187 if ((irq_next_vpa & ADV_RQ_GOOD) != 0) {
6188 scsiq->done_status = QD_NO_ERROR;
6189 scsiq->host_status = scsiq->scsi_status = 0;
6190 scsiq->data_cnt = 0L;
6191 }
6192
6193 /*
6194 * Advance the stopper pointer to the next carrier
6195 * ignoring the lower four bits. Free the previous
6196 * stopper carrier.
6197 */
6198 free_carrp = asc_dvc->irq_sp;
6199 asc_dvc->irq_sp = adv_get_carrier(asc_dvc,
6200 ADV_GET_CARRP(irq_next_vpa));
6201
6202 free_carrp->next_vpa = asc_dvc->carr_freelist->carr_va;
6203 asc_dvc->carr_freelist = free_carrp;
6204 asc_dvc->carr_pending_cnt--;
6205
6206 target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id);
6207
6208 /*
6209 * Clear request microcode control flag.
6210 */
6211 scsiq->cntl = 0;
6212
6213 /*
6214 * Notify the driver of the completed request by passing
6215 * the ADV_SCSI_REQ_Q pointer to its callback function.
6216 */
6217 adv_isr_callback(asc_dvc, scsiq);
6218 /*
6219 * Note: After the driver callback function is called, 'scsiq'
6220 * can no longer be referenced.
6221 *
6222 * Fall through and continue processing other completed
6223 * requests...
6224 */
6225 }
6226 return ADV_TRUE;
6227 }
6228
6229 static int AscSetLibErrorCode(ASC_DVC_VAR *asc_dvc, ushort err_code)
6230 {
6231 if (asc_dvc->err_code == 0) {
6232 asc_dvc->err_code = err_code;
6233 AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W,
6234 err_code);
6235 }
6236 return err_code;
6237 }
6238
6239 static void AscAckInterrupt(PortAddr iop_base)
6240 {
6241 uchar host_flag;
6242 uchar risc_flag;
6243 ushort loop;
6244
6245 loop = 0;
6246 do {
6247 risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B);
6248 if (loop++ > 0x7FFF) {
6249 break;
6250 }
6251 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0);
6252 host_flag =
6253 AscReadLramByte(iop_base,
6254 ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT);
6255 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
6256 (uchar)(host_flag | ASC_HOST_FLAG_ACK_INT));
6257 AscSetChipStatus(iop_base, CIW_INT_ACK);
6258 loop = 0;
6259 while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) {
6260 AscSetChipStatus(iop_base, CIW_INT_ACK);
6261 if (loop++ > 3) {
6262 break;
6263 }
6264 }
6265 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
6266 }
6267
6268 static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time)
6269 {
6270 const uchar *period_table;
6271 int max_index;
6272 int min_index;
6273 int i;
6274
6275 period_table = asc_dvc->sdtr_period_tbl;
6276 max_index = (int)asc_dvc->max_sdtr_index;
6277 min_index = (int)asc_dvc->min_sdtr_index;
6278 if ((syn_time <= period_table[max_index])) {
6279 for (i = min_index; i < (max_index - 1); i++) {
6280 if (syn_time <= period_table[i]) {
6281 return (uchar)i;
6282 }
6283 }
6284 return (uchar)max_index;
6285 } else {
6286 return (uchar)(max_index + 1);
6287 }
6288 }
6289
6290 static uchar
6291 AscMsgOutSDTR(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar sdtr_offset)
6292 {
6293 EXT_MSG sdtr_buf;
6294 uchar sdtr_period_index;
6295 PortAddr iop_base;
6296
6297 iop_base = asc_dvc->iop_base;
6298 sdtr_buf.msg_type = EXTENDED_MESSAGE;
6299 sdtr_buf.msg_len = MS_SDTR_LEN;
6300 sdtr_buf.msg_req = EXTENDED_SDTR;
6301 sdtr_buf.xfer_period = sdtr_period;
6302 sdtr_offset &= ASC_SYN_MAX_OFFSET;
6303 sdtr_buf.req_ack_offset = sdtr_offset;
6304 sdtr_period_index = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
6305 if (sdtr_period_index <= asc_dvc->max_sdtr_index) {
6306 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
6307 (uchar *)&sdtr_buf,
6308 sizeof(EXT_MSG) >> 1);
6309 return ((sdtr_period_index << 4) | sdtr_offset);
6310 } else {
6311 sdtr_buf.req_ack_offset = 0;
6312 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
6313 (uchar *)&sdtr_buf,
6314 sizeof(EXT_MSG) >> 1);
6315 return 0;
6316 }
6317 }
6318
6319 static uchar
6320 AscCalSDTRData(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar syn_offset)
6321 {
6322 uchar byte;
6323 uchar sdtr_period_ix;
6324
6325 sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
6326 if (sdtr_period_ix > asc_dvc->max_sdtr_index)
6327 return 0xFF;
6328 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
6329 return byte;
6330 }
6331
6332 static bool AscSetChipSynRegAtID(PortAddr iop_base, uchar id, uchar sdtr_data)
6333 {
6334 ASC_SCSI_BIT_ID_TYPE org_id;
6335 int i;
6336 bool sta = true;
6337
6338 AscSetBank(iop_base, 1);
6339 org_id = AscReadChipDvcID(iop_base);
6340 for (i = 0; i <= ASC_MAX_TID; i++) {
6341 if (org_id == (0x01 << i))
6342 break;
6343 }
6344 org_id = (ASC_SCSI_BIT_ID_TYPE) i;
6345 AscWriteChipDvcID(iop_base, id);
6346 if (AscReadChipDvcID(iop_base) == (0x01 << id)) {
6347 AscSetBank(iop_base, 0);
6348 AscSetChipSyn(iop_base, sdtr_data);
6349 if (AscGetChipSyn(iop_base) != sdtr_data) {
6350 sta = false;
6351 }
6352 } else {
6353 sta = false;
6354 }
6355 AscSetBank(iop_base, 1);
6356 AscWriteChipDvcID(iop_base, org_id);
6357 AscSetBank(iop_base, 0);
6358 return (sta);
6359 }
6360
6361 static void AscSetChipSDTR(PortAddr iop_base, uchar sdtr_data, uchar tid_no)
6362 {
6363 AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
6364 AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data);
6365 }
6366
6367 static void AscIsrChipHalted(ASC_DVC_VAR *asc_dvc)
6368 {
6369 EXT_MSG ext_msg;
6370 EXT_MSG out_msg;
6371 ushort halt_q_addr;
6372 bool sdtr_accept;
6373 ushort int_halt_code;
6374 ASC_SCSI_BIT_ID_TYPE scsi_busy;
6375 ASC_SCSI_BIT_ID_TYPE target_id;
6376 PortAddr iop_base;
6377 uchar tag_code;
6378 uchar q_status;
6379 uchar halt_qp;
6380 uchar sdtr_data;
6381 uchar target_ix;
6382 uchar q_cntl, tid_no;
6383 uchar cur_dvc_qng;
6384 uchar asyn_sdtr;
6385 uchar scsi_status;
6386 struct asc_board *boardp;
6387
6388 BUG_ON(!asc_dvc->drv_ptr);
6389 boardp = asc_dvc->drv_ptr;
6390
6391 iop_base = asc_dvc->iop_base;
6392 int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W);
6393
6394 halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B);
6395 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp);
6396 target_ix = AscReadLramByte(iop_base,
6397 (ushort)(halt_q_addr +
6398 (ushort)ASC_SCSIQ_B_TARGET_IX));
6399 q_cntl = AscReadLramByte(iop_base,
6400 (ushort)(halt_q_addr + (ushort)ASC_SCSIQ_B_CNTL));
6401 tid_no = ASC_TIX_TO_TID(target_ix);
6402 target_id = (uchar)ASC_TID_TO_TARGET_ID(tid_no);
6403 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6404 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB;
6405 } else {
6406 asyn_sdtr = 0;
6407 }
6408 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) {
6409 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6410 AscSetChipSDTR(iop_base, 0, tid_no);
6411 boardp->sdtr_data[tid_no] = 0;
6412 }
6413 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6414 return;
6415 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) {
6416 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6417 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6418 boardp->sdtr_data[tid_no] = asyn_sdtr;
6419 }
6420 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6421 return;
6422 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) {
6423 AscMemWordCopyPtrFromLram(iop_base,
6424 ASCV_MSGIN_BEG,
6425 (uchar *)&ext_msg,
6426 sizeof(EXT_MSG) >> 1);
6427
6428 if (ext_msg.msg_type == EXTENDED_MESSAGE &&
6429 ext_msg.msg_req == EXTENDED_SDTR &&
6430 ext_msg.msg_len == MS_SDTR_LEN) {
6431 sdtr_accept = true;
6432 if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) {
6433
6434 sdtr_accept = false;
6435 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
6436 }
6437 if ((ext_msg.xfer_period <
6438 asc_dvc->sdtr_period_tbl[asc_dvc->min_sdtr_index])
6439 || (ext_msg.xfer_period >
6440 asc_dvc->sdtr_period_tbl[asc_dvc->
6441 max_sdtr_index])) {
6442 sdtr_accept = false;
6443 ext_msg.xfer_period =
6444 asc_dvc->sdtr_period_tbl[asc_dvc->
6445 min_sdtr_index];
6446 }
6447 if (sdtr_accept) {
6448 sdtr_data =
6449 AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
6450 ext_msg.req_ack_offset);
6451 if ((sdtr_data == 0xFF)) {
6452
6453 q_cntl |= QC_MSG_OUT;
6454 asc_dvc->init_sdtr &= ~target_id;
6455 asc_dvc->sdtr_done &= ~target_id;
6456 AscSetChipSDTR(iop_base, asyn_sdtr,
6457 tid_no);
6458 boardp->sdtr_data[tid_no] = asyn_sdtr;
6459 }
6460 }
6461 if (ext_msg.req_ack_offset == 0) {
6462
6463 q_cntl &= ~QC_MSG_OUT;
6464 asc_dvc->init_sdtr &= ~target_id;
6465 asc_dvc->sdtr_done &= ~target_id;
6466 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6467 } else {
6468 if (sdtr_accept && (q_cntl & QC_MSG_OUT)) {
6469 q_cntl &= ~QC_MSG_OUT;
6470 asc_dvc->sdtr_done |= target_id;
6471 asc_dvc->init_sdtr |= target_id;
6472 asc_dvc->pci_fix_asyn_xfer &=
6473 ~target_id;
6474 sdtr_data =
6475 AscCalSDTRData(asc_dvc,
6476 ext_msg.xfer_period,
6477 ext_msg.
6478 req_ack_offset);
6479 AscSetChipSDTR(iop_base, sdtr_data,
6480 tid_no);
6481 boardp->sdtr_data[tid_no] = sdtr_data;
6482 } else {
6483 q_cntl |= QC_MSG_OUT;
6484 AscMsgOutSDTR(asc_dvc,
6485 ext_msg.xfer_period,
6486 ext_msg.req_ack_offset);
6487 asc_dvc->pci_fix_asyn_xfer &=
6488 ~target_id;
6489 sdtr_data =
6490 AscCalSDTRData(asc_dvc,
6491 ext_msg.xfer_period,
6492 ext_msg.
6493 req_ack_offset);
6494 AscSetChipSDTR(iop_base, sdtr_data,
6495 tid_no);
6496 boardp->sdtr_data[tid_no] = sdtr_data;
6497 asc_dvc->sdtr_done |= target_id;
6498 asc_dvc->init_sdtr |= target_id;
6499 }
6500 }
6501
6502 AscWriteLramByte(iop_base,
6503 (ushort)(halt_q_addr +
6504 (ushort)ASC_SCSIQ_B_CNTL),
6505 q_cntl);
6506 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6507 return;
6508 } else if (ext_msg.msg_type == EXTENDED_MESSAGE &&
6509 ext_msg.msg_req == EXTENDED_WDTR &&
6510 ext_msg.msg_len == MS_WDTR_LEN) {
6511
6512 ext_msg.wdtr_width = 0;
6513 AscMemWordCopyPtrToLram(iop_base,
6514 ASCV_MSGOUT_BEG,
6515 (uchar *)&ext_msg,
6516 sizeof(EXT_MSG) >> 1);
6517 q_cntl |= QC_MSG_OUT;
6518 AscWriteLramByte(iop_base,
6519 (ushort)(halt_q_addr +
6520 (ushort)ASC_SCSIQ_B_CNTL),
6521 q_cntl);
6522 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6523 return;
6524 } else {
6525
6526 ext_msg.msg_type = MESSAGE_REJECT;
6527 AscMemWordCopyPtrToLram(iop_base,
6528 ASCV_MSGOUT_BEG,
6529 (uchar *)&ext_msg,
6530 sizeof(EXT_MSG) >> 1);
6531 q_cntl |= QC_MSG_OUT;
6532 AscWriteLramByte(iop_base,
6533 (ushort)(halt_q_addr +
6534 (ushort)ASC_SCSIQ_B_CNTL),
6535 q_cntl);
6536 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6537 return;
6538 }
6539 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) {
6540
6541 q_cntl |= QC_REQ_SENSE;
6542
6543 if ((asc_dvc->init_sdtr & target_id) != 0) {
6544
6545 asc_dvc->sdtr_done &= ~target_id;
6546
6547 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
6548 q_cntl |= QC_MSG_OUT;
6549 AscMsgOutSDTR(asc_dvc,
6550 asc_dvc->
6551 sdtr_period_tbl[(sdtr_data >> 4) &
6552 (uchar)(asc_dvc->
6553 max_sdtr_index -
6554 1)],
6555 (uchar)(sdtr_data & (uchar)
6556 ASC_SYN_MAX_OFFSET));
6557 }
6558
6559 AscWriteLramByte(iop_base,
6560 (ushort)(halt_q_addr +
6561 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
6562
6563 tag_code = AscReadLramByte(iop_base,
6564 (ushort)(halt_q_addr + (ushort)
6565 ASC_SCSIQ_B_TAG_CODE));
6566 tag_code &= 0xDC;
6567 if ((asc_dvc->pci_fix_asyn_xfer & target_id)
6568 && !(asc_dvc->pci_fix_asyn_xfer_always & target_id)
6569 ) {
6570
6571 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT
6572 | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX);
6573
6574 }
6575 AscWriteLramByte(iop_base,
6576 (ushort)(halt_q_addr +
6577 (ushort)ASC_SCSIQ_B_TAG_CODE),
6578 tag_code);
6579
6580 q_status = AscReadLramByte(iop_base,
6581 (ushort)(halt_q_addr + (ushort)
6582 ASC_SCSIQ_B_STATUS));
6583 q_status |= (QS_READY | QS_BUSY);
6584 AscWriteLramByte(iop_base,
6585 (ushort)(halt_q_addr +
6586 (ushort)ASC_SCSIQ_B_STATUS),
6587 q_status);
6588
6589 scsi_busy = AscReadLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B);
6590 scsi_busy &= ~target_id;
6591 AscWriteLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B, scsi_busy);
6592
6593 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6594 return;
6595 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) {
6596
6597 AscMemWordCopyPtrFromLram(iop_base,
6598 ASCV_MSGOUT_BEG,
6599 (uchar *)&out_msg,
6600 sizeof(EXT_MSG) >> 1);
6601
6602 if ((out_msg.msg_type == EXTENDED_MESSAGE) &&
6603 (out_msg.msg_len == MS_SDTR_LEN) &&
6604 (out_msg.msg_req == EXTENDED_SDTR)) {
6605
6606 asc_dvc->init_sdtr &= ~target_id;
6607 asc_dvc->sdtr_done &= ~target_id;
6608 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6609 boardp->sdtr_data[tid_no] = asyn_sdtr;
6610 }
6611 q_cntl &= ~QC_MSG_OUT;
6612 AscWriteLramByte(iop_base,
6613 (ushort)(halt_q_addr +
6614 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
6615 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6616 return;
6617 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) {
6618
6619 scsi_status = AscReadLramByte(iop_base,
6620 (ushort)((ushort)halt_q_addr +
6621 (ushort)
6622 ASC_SCSIQ_SCSI_STATUS));
6623 cur_dvc_qng =
6624 AscReadLramByte(iop_base,
6625 (ushort)((ushort)ASC_QADR_BEG +
6626 (ushort)target_ix));
6627 if ((cur_dvc_qng > 0) && (asc_dvc->cur_dvc_qng[tid_no] > 0)) {
6628
6629 scsi_busy = AscReadLramByte(iop_base,
6630 (ushort)ASCV_SCSIBUSY_B);
6631 scsi_busy |= target_id;
6632 AscWriteLramByte(iop_base,
6633 (ushort)ASCV_SCSIBUSY_B, scsi_busy);
6634 asc_dvc->queue_full_or_busy |= target_id;
6635
6636 if (scsi_status == SAM_STAT_TASK_SET_FULL) {
6637 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) {
6638 cur_dvc_qng -= 1;
6639 asc_dvc->max_dvc_qng[tid_no] =
6640 cur_dvc_qng;
6641
6642 AscWriteLramByte(iop_base,
6643 (ushort)((ushort)
6644 ASCV_MAX_DVC_QNG_BEG
6645 + (ushort)
6646 tid_no),
6647 cur_dvc_qng);
6648
6649 /*
6650 * Set the device queue depth to the
6651 * number of active requests when the
6652 * QUEUE FULL condition was encountered.
6653 */
6654 boardp->queue_full |= target_id;
6655 boardp->queue_full_cnt[tid_no] =
6656 cur_dvc_qng;
6657 }
6658 }
6659 }
6660 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6661 return;
6662 }
6663 return;
6664 }
6665
6666 /*
6667 * void
6668 * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
6669 *
6670 * Calling/Exit State:
6671 * none
6672 *
6673 * Description:
6674 * Input an ASC_QDONE_INFO structure from the chip
6675 */
6676 static void
6677 DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
6678 {
6679 int i;
6680 ushort word;
6681
6682 AscSetChipLramAddr(iop_base, s_addr);
6683 for (i = 0; i < 2 * words; i += 2) {
6684 if (i == 10) {
6685 continue;
6686 }
6687 word = inpw(iop_base + IOP_RAM_DATA);
6688 inbuf[i] = word & 0xff;
6689 inbuf[i + 1] = (word >> 8) & 0xff;
6690 }
6691 ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words);
6692 }
6693
6694 static uchar
6695 _AscCopyLramScsiDoneQ(PortAddr iop_base,
6696 ushort q_addr,
6697 ASC_QDONE_INFO *scsiq, unsigned int max_dma_count)
6698 {
6699 ushort _val;
6700 uchar sg_queue_cnt;
6701
6702 DvcGetQinfo(iop_base,
6703 q_addr + ASC_SCSIQ_DONE_INFO_BEG,
6704 (uchar *)scsiq,
6705 (sizeof(ASC_SCSIQ_2) + sizeof(ASC_SCSIQ_3)) / 2);
6706
6707 _val = AscReadLramWord(iop_base,
6708 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS));
6709 scsiq->q_status = (uchar)_val;
6710 scsiq->q_no = (uchar)(_val >> 8);
6711 _val = AscReadLramWord(iop_base,
6712 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_CNTL));
6713 scsiq->cntl = (uchar)_val;
6714 sg_queue_cnt = (uchar)(_val >> 8);
6715 _val = AscReadLramWord(iop_base,
6716 (ushort)(q_addr +
6717 (ushort)ASC_SCSIQ_B_SENSE_LEN));
6718 scsiq->sense_len = (uchar)_val;
6719 scsiq->extra_bytes = (uchar)(_val >> 8);
6720
6721 /*
6722 * Read high word of remain bytes from alternate location.
6723 */
6724 scsiq->remain_bytes = (((u32)AscReadLramWord(iop_base,
6725 (ushort)(q_addr +
6726 (ushort)
6727 ASC_SCSIQ_W_ALT_DC1)))
6728 << 16);
6729 /*
6730 * Read low word of remain bytes from original location.
6731 */
6732 scsiq->remain_bytes += AscReadLramWord(iop_base,
6733 (ushort)(q_addr + (ushort)
6734 ASC_SCSIQ_DW_REMAIN_XFER_CNT));
6735
6736 scsiq->remain_bytes &= max_dma_count;
6737 return sg_queue_cnt;
6738 }
6739
6740 /*
6741 * asc_isr_callback() - Second Level Interrupt Handler called by AscISR().
6742 *
6743 * Interrupt callback function for the Narrow SCSI Asc Library.
6744 */
6745 static void asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep)
6746 {
6747 struct asc_board *boardp = asc_dvc_varp->drv_ptr;
6748 u32 srb_tag;
6749 struct scsi_cmnd *scp;
6750
6751 ASC_DBG(1, "asc_dvc_varp 0x%p, qdonep 0x%p\n", asc_dvc_varp, qdonep);
6752 ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep);
6753
6754 /*
6755 * Decrease the srb_tag by 1 to find the SCSI command
6756 */
6757 srb_tag = qdonep->d2.srb_tag - 1;
6758 scp = scsi_host_find_tag(boardp->shost, srb_tag);
6759 if (!scp)
6760 return;
6761
6762 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
6763
6764 ASC_STATS(boardp->shost, callback);
6765
6766 dma_unmap_single(boardp->dev, scp->SCp.dma_handle,
6767 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
6768 /*
6769 * 'qdonep' contains the command's ending status.
6770 */
6771 switch (qdonep->d3.done_stat) {
6772 case QD_NO_ERROR:
6773 ASC_DBG(2, "QD_NO_ERROR\n");
6774 scp->result = 0;
6775
6776 /*
6777 * Check for an underrun condition.
6778 *
6779 * If there was no error and an underrun condition, then
6780 * return the number of underrun bytes.
6781 */
6782 if (scsi_bufflen(scp) != 0 && qdonep->remain_bytes != 0 &&
6783 qdonep->remain_bytes <= scsi_bufflen(scp)) {
6784 ASC_DBG(1, "underrun condition %u bytes\n",
6785 (unsigned)qdonep->remain_bytes);
6786 scsi_set_resid(scp, qdonep->remain_bytes);
6787 }
6788 break;
6789
6790 case QD_WITH_ERROR:
6791 ASC_DBG(2, "QD_WITH_ERROR\n");
6792 switch (qdonep->d3.host_stat) {
6793 case QHSTA_NO_ERROR:
6794 if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) {
6795 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
6796 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
6797 SCSI_SENSE_BUFFERSIZE);
6798 /*
6799 * Note: The 'status_byte()' macro used by
6800 * target drivers defined in scsi.h shifts the
6801 * status byte returned by host drivers right
6802 * by 1 bit. This is why target drivers also
6803 * use right shifted status byte definitions.
6804 * For instance target drivers use
6805 * CHECK_CONDITION, defined to 0x1, instead of
6806 * the SCSI defined check condition value of
6807 * 0x2. Host drivers are supposed to return
6808 * the status byte as it is defined by SCSI.
6809 */
6810 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
6811 STATUS_BYTE(qdonep->d3.scsi_stat);
6812 } else {
6813 scp->result = STATUS_BYTE(qdonep->d3.scsi_stat);
6814 }
6815 break;
6816
6817 default:
6818 /* QHSTA error occurred */
6819 ASC_DBG(1, "host_stat 0x%x\n", qdonep->d3.host_stat);
6820 scp->result = HOST_BYTE(DID_BAD_TARGET);
6821 break;
6822 }
6823 break;
6824
6825 case QD_ABORTED_BY_HOST:
6826 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
6827 scp->result =
6828 HOST_BYTE(DID_ABORT) | MSG_BYTE(qdonep->d3.
6829 scsi_msg) |
6830 STATUS_BYTE(qdonep->d3.scsi_stat);
6831 break;
6832
6833 default:
6834 ASC_DBG(1, "done_stat 0x%x\n", qdonep->d3.done_stat);
6835 scp->result =
6836 HOST_BYTE(DID_ERROR) | MSG_BYTE(qdonep->d3.
6837 scsi_msg) |
6838 STATUS_BYTE(qdonep->d3.scsi_stat);
6839 break;
6840 }
6841
6842 /*
6843 * If the 'init_tidmask' bit isn't already set for the target and the
6844 * current request finished normally, then set the bit for the target
6845 * to indicate that a device is present.
6846 */
6847 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
6848 qdonep->d3.done_stat == QD_NO_ERROR &&
6849 qdonep->d3.host_stat == QHSTA_NO_ERROR) {
6850 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
6851 }
6852
6853 asc_scsi_done(scp);
6854 }
6855
6856 static int AscIsrQDone(ASC_DVC_VAR *asc_dvc)
6857 {
6858 uchar next_qp;
6859 uchar n_q_used;
6860 uchar sg_list_qp;
6861 uchar sg_queue_cnt;
6862 uchar q_cnt;
6863 uchar done_q_tail;
6864 uchar tid_no;
6865 ASC_SCSI_BIT_ID_TYPE scsi_busy;
6866 ASC_SCSI_BIT_ID_TYPE target_id;
6867 PortAddr iop_base;
6868 ushort q_addr;
6869 ushort sg_q_addr;
6870 uchar cur_target_qng;
6871 ASC_QDONE_INFO scsiq_buf;
6872 ASC_QDONE_INFO *scsiq;
6873 bool false_overrun;
6874
6875 iop_base = asc_dvc->iop_base;
6876 n_q_used = 1;
6877 scsiq = (ASC_QDONE_INFO *)&scsiq_buf;
6878 done_q_tail = (uchar)AscGetVarDoneQTail(iop_base);
6879 q_addr = ASC_QNO_TO_QADDR(done_q_tail);
6880 next_qp = AscReadLramByte(iop_base,
6881 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_FWD));
6882 if (next_qp != ASC_QLINK_END) {
6883 AscPutVarDoneQTail(iop_base, next_qp);
6884 q_addr = ASC_QNO_TO_QADDR(next_qp);
6885 sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq,
6886 asc_dvc->max_dma_count);
6887 AscWriteLramByte(iop_base,
6888 (ushort)(q_addr +
6889 (ushort)ASC_SCSIQ_B_STATUS),
6890 (uchar)(scsiq->
6891 q_status & (uchar)~(QS_READY |
6892 QS_ABORTED)));
6893 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix);
6894 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix);
6895 if ((scsiq->cntl & QC_SG_HEAD) != 0) {
6896 sg_q_addr = q_addr;
6897 sg_list_qp = next_qp;
6898 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) {
6899 sg_list_qp = AscReadLramByte(iop_base,
6900 (ushort)(sg_q_addr
6901 + (ushort)
6902 ASC_SCSIQ_B_FWD));
6903 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp);
6904 if (sg_list_qp == ASC_QLINK_END) {
6905 AscSetLibErrorCode(asc_dvc,
6906 ASCQ_ERR_SG_Q_LINKS);
6907 scsiq->d3.done_stat = QD_WITH_ERROR;
6908 scsiq->d3.host_stat =
6909 QHSTA_D_QDONE_SG_LIST_CORRUPTED;
6910 goto FATAL_ERR_QDONE;
6911 }
6912 AscWriteLramByte(iop_base,
6913 (ushort)(sg_q_addr + (ushort)
6914 ASC_SCSIQ_B_STATUS),
6915 QS_FREE);
6916 }
6917 n_q_used = sg_queue_cnt + 1;
6918 AscPutVarDoneQTail(iop_base, sg_list_qp);
6919 }
6920 if (asc_dvc->queue_full_or_busy & target_id) {
6921 cur_target_qng = AscReadLramByte(iop_base,
6922 (ushort)((ushort)
6923 ASC_QADR_BEG
6924 + (ushort)
6925 scsiq->d2.
6926 target_ix));
6927 if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) {
6928 scsi_busy = AscReadLramByte(iop_base, (ushort)
6929 ASCV_SCSIBUSY_B);
6930 scsi_busy &= ~target_id;
6931 AscWriteLramByte(iop_base,
6932 (ushort)ASCV_SCSIBUSY_B,
6933 scsi_busy);
6934 asc_dvc->queue_full_or_busy &= ~target_id;
6935 }
6936 }
6937 if (asc_dvc->cur_total_qng >= n_q_used) {
6938 asc_dvc->cur_total_qng -= n_q_used;
6939 if (asc_dvc->cur_dvc_qng[tid_no] != 0) {
6940 asc_dvc->cur_dvc_qng[tid_no]--;
6941 }
6942 } else {
6943 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CUR_QNG);
6944 scsiq->d3.done_stat = QD_WITH_ERROR;
6945 goto FATAL_ERR_QDONE;
6946 }
6947 if ((scsiq->d2.srb_tag == 0UL) ||
6948 ((scsiq->q_status & QS_ABORTED) != 0)) {
6949 return (0x11);
6950 } else if (scsiq->q_status == QS_DONE) {
6951 /*
6952 * This is also curious.
6953 * false_overrun will _always_ be set to 'false'
6954 */
6955 false_overrun = false;
6956 if (scsiq->extra_bytes != 0) {
6957 scsiq->remain_bytes += scsiq->extra_bytes;
6958 }
6959 if (scsiq->d3.done_stat == QD_WITH_ERROR) {
6960 if (scsiq->d3.host_stat ==
6961 QHSTA_M_DATA_OVER_RUN) {
6962 if ((scsiq->
6963 cntl & (QC_DATA_IN | QC_DATA_OUT))
6964 == 0) {
6965 scsiq->d3.done_stat =
6966 QD_NO_ERROR;
6967 scsiq->d3.host_stat =
6968 QHSTA_NO_ERROR;
6969 } else if (false_overrun) {
6970 scsiq->d3.done_stat =
6971 QD_NO_ERROR;
6972 scsiq->d3.host_stat =
6973 QHSTA_NO_ERROR;
6974 }
6975 } else if (scsiq->d3.host_stat ==
6976 QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) {
6977 AscStopChip(iop_base);
6978 AscSetChipControl(iop_base,
6979 (uchar)(CC_SCSI_RESET
6980 | CC_HALT));
6981 udelay(60);
6982 AscSetChipControl(iop_base, CC_HALT);
6983 AscSetChipStatus(iop_base,
6984 CIW_CLR_SCSI_RESET_INT);
6985 AscSetChipStatus(iop_base, 0);
6986 AscSetChipControl(iop_base, 0);
6987 }
6988 }
6989 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
6990 asc_isr_callback(asc_dvc, scsiq);
6991 } else {
6992 if ((AscReadLramByte(iop_base,
6993 (ushort)(q_addr + (ushort)
6994 ASC_SCSIQ_CDB_BEG))
6995 == START_STOP)) {
6996 asc_dvc->unit_not_ready &= ~target_id;
6997 if (scsiq->d3.done_stat != QD_NO_ERROR) {
6998 asc_dvc->start_motor &=
6999 ~target_id;
7000 }
7001 }
7002 }
7003 return (1);
7004 } else {
7005 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_Q_STATUS);
7006 FATAL_ERR_QDONE:
7007 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
7008 asc_isr_callback(asc_dvc, scsiq);
7009 }
7010 return (0x80);
7011 }
7012 }
7013 return (0);
7014 }
7015
7016 static int AscISR(ASC_DVC_VAR *asc_dvc)
7017 {
7018 ASC_CS_TYPE chipstat;
7019 PortAddr iop_base;
7020 ushort saved_ram_addr;
7021 uchar ctrl_reg;
7022 uchar saved_ctrl_reg;
7023 int int_pending;
7024 int status;
7025 uchar host_flag;
7026
7027 iop_base = asc_dvc->iop_base;
7028 int_pending = ASC_FALSE;
7029
7030 if (AscIsIntPending(iop_base) == 0)
7031 return int_pending;
7032
7033 if ((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0) {
7034 return ASC_ERROR;
7035 }
7036 if (asc_dvc->in_critical_cnt != 0) {
7037 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL);
7038 return ASC_ERROR;
7039 }
7040 if (asc_dvc->is_in_int) {
7041 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY);
7042 return ASC_ERROR;
7043 }
7044 asc_dvc->is_in_int = true;
7045 ctrl_reg = AscGetChipControl(iop_base);
7046 saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET |
7047 CC_SINGLE_STEP | CC_DIAG | CC_TEST));
7048 chipstat = AscGetChipStatus(iop_base);
7049 if (chipstat & CSW_SCSI_RESET_LATCH) {
7050 if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) {
7051 int i = 10;
7052 int_pending = ASC_TRUE;
7053 asc_dvc->sdtr_done = 0;
7054 saved_ctrl_reg &= (uchar)(~CC_HALT);
7055 while ((AscGetChipStatus(iop_base) &
7056 CSW_SCSI_RESET_ACTIVE) && (i-- > 0)) {
7057 mdelay(100);
7058 }
7059 AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT));
7060 AscSetChipControl(iop_base, CC_HALT);
7061 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
7062 AscSetChipStatus(iop_base, 0);
7063 chipstat = AscGetChipStatus(iop_base);
7064 }
7065 }
7066 saved_ram_addr = AscGetChipLramAddr(iop_base);
7067 host_flag = AscReadLramByte(iop_base,
7068 ASCV_HOST_FLAG_B) &
7069 (uchar)(~ASC_HOST_FLAG_IN_ISR);
7070 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
7071 (uchar)(host_flag | (uchar)ASC_HOST_FLAG_IN_ISR));
7072 if ((chipstat & CSW_INT_PENDING) || (int_pending)) {
7073 AscAckInterrupt(iop_base);
7074 int_pending = ASC_TRUE;
7075 if ((chipstat & CSW_HALTED) && (ctrl_reg & CC_SINGLE_STEP)) {
7076 AscIsrChipHalted(asc_dvc);
7077 saved_ctrl_reg &= (uchar)(~CC_HALT);
7078 } else {
7079 if ((asc_dvc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) != 0) {
7080 while (((status =
7081 AscIsrQDone(asc_dvc)) & 0x01) != 0) {
7082 }
7083 } else {
7084 do {
7085 if ((status =
7086 AscIsrQDone(asc_dvc)) == 1) {
7087 break;
7088 }
7089 } while (status == 0x11);
7090 }
7091 if ((status & 0x80) != 0)
7092 int_pending = ASC_ERROR;
7093 }
7094 }
7095 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
7096 AscSetChipLramAddr(iop_base, saved_ram_addr);
7097 AscSetChipControl(iop_base, saved_ctrl_reg);
7098 asc_dvc->is_in_int = false;
7099 return int_pending;
7100 }
7101
7102 /*
7103 * advansys_reset()
7104 *
7105 * Reset the host associated with the command 'scp'.
7106 *
7107 * This function runs its own thread. Interrupts must be blocked but
7108 * sleeping is allowed and no locking other than for host structures is
7109 * required. Returns SUCCESS or FAILED.
7110 */
7111 static int advansys_reset(struct scsi_cmnd *scp)
7112 {
7113 struct Scsi_Host *shost = scp->device->host;
7114 struct asc_board *boardp = shost_priv(shost);
7115 unsigned long flags;
7116 int status;
7117 int ret = SUCCESS;
7118
7119 ASC_DBG(1, "0x%p\n", scp);
7120
7121 ASC_STATS(shost, reset);
7122
7123 scmd_printk(KERN_INFO, scp, "SCSI host reset started...\n");
7124
7125 if (ASC_NARROW_BOARD(boardp)) {
7126 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
7127
7128 /* Reset the chip and SCSI bus. */
7129 ASC_DBG(1, "before AscInitAsc1000Driver()\n");
7130 status = AscInitAsc1000Driver(asc_dvc);
7131
7132 /* Refer to ASC_IERR_* definitions for meaning of 'err_code'. */
7133 if (asc_dvc->err_code || !asc_dvc->overrun_dma) {
7134 scmd_printk(KERN_INFO, scp, "SCSI host reset error: "
7135 "0x%x, status: 0x%x\n", asc_dvc->err_code,
7136 status);
7137 ret = FAILED;
7138 } else if (status) {
7139 scmd_printk(KERN_INFO, scp, "SCSI host reset warning: "
7140 "0x%x\n", status);
7141 } else {
7142 scmd_printk(KERN_INFO, scp, "SCSI host reset "
7143 "successful\n");
7144 }
7145
7146 ASC_DBG(1, "after AscInitAsc1000Driver()\n");
7147 } else {
7148 /*
7149 * If the suggest reset bus flags are set, then reset the bus.
7150 * Otherwise only reset the device.
7151 */
7152 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
7153
7154 /*
7155 * Reset the chip and SCSI bus.
7156 */
7157 ASC_DBG(1, "before AdvResetChipAndSB()\n");
7158 switch (AdvResetChipAndSB(adv_dvc)) {
7159 case ASC_TRUE:
7160 scmd_printk(KERN_INFO, scp, "SCSI host reset "
7161 "successful\n");
7162 break;
7163 case ASC_FALSE:
7164 default:
7165 scmd_printk(KERN_INFO, scp, "SCSI host reset error\n");
7166 ret = FAILED;
7167 break;
7168 }
7169 spin_lock_irqsave(shost->host_lock, flags);
7170 AdvISR(adv_dvc);
7171 spin_unlock_irqrestore(shost->host_lock, flags);
7172 }
7173
7174 ASC_DBG(1, "ret %d\n", ret);
7175
7176 return ret;
7177 }
7178
7179 /*
7180 * advansys_biosparam()
7181 *
7182 * Translate disk drive geometry if the "BIOS greater than 1 GB"
7183 * support is enabled for a drive.
7184 *
7185 * ip (information pointer) is an int array with the following definition:
7186 * ip[0]: heads
7187 * ip[1]: sectors
7188 * ip[2]: cylinders
7189 */
7190 static int
7191 advansys_biosparam(struct scsi_device *sdev, struct block_device *bdev,
7192 sector_t capacity, int ip[])
7193 {
7194 struct asc_board *boardp = shost_priv(sdev->host);
7195
7196 ASC_DBG(1, "begin\n");
7197 ASC_STATS(sdev->host, biosparam);
7198 if (ASC_NARROW_BOARD(boardp)) {
7199 if ((boardp->dvc_var.asc_dvc_var.dvc_cntl &
7200 ASC_CNTL_BIOS_GT_1GB) && capacity > 0x200000) {
7201 ip[0] = 255;
7202 ip[1] = 63;
7203 } else {
7204 ip[0] = 64;
7205 ip[1] = 32;
7206 }
7207 } else {
7208 if ((boardp->dvc_var.adv_dvc_var.bios_ctrl &
7209 BIOS_CTRL_EXTENDED_XLAT) && capacity > 0x200000) {
7210 ip[0] = 255;
7211 ip[1] = 63;
7212 } else {
7213 ip[0] = 64;
7214 ip[1] = 32;
7215 }
7216 }
7217 ip[2] = (unsigned long)capacity / (ip[0] * ip[1]);
7218 ASC_DBG(1, "end\n");
7219 return 0;
7220 }
7221
7222 /*
7223 * First-level interrupt handler.
7224 *
7225 * 'dev_id' is a pointer to the interrupting adapter's Scsi_Host.
7226 */
7227 static irqreturn_t advansys_interrupt(int irq, void *dev_id)
7228 {
7229 struct Scsi_Host *shost = dev_id;
7230 struct asc_board *boardp = shost_priv(shost);
7231 irqreturn_t result = IRQ_NONE;
7232 unsigned long flags;
7233
7234 ASC_DBG(2, "boardp 0x%p\n", boardp);
7235 spin_lock_irqsave(shost->host_lock, flags);
7236 if (ASC_NARROW_BOARD(boardp)) {
7237 if (AscIsIntPending(shost->io_port)) {
7238 result = IRQ_HANDLED;
7239 ASC_STATS(shost, interrupt);
7240 ASC_DBG(1, "before AscISR()\n");
7241 AscISR(&boardp->dvc_var.asc_dvc_var);
7242 }
7243 } else {
7244 ASC_DBG(1, "before AdvISR()\n");
7245 if (AdvISR(&boardp->dvc_var.adv_dvc_var)) {
7246 result = IRQ_HANDLED;
7247 ASC_STATS(shost, interrupt);
7248 }
7249 }
7250 spin_unlock_irqrestore(shost->host_lock, flags);
7251
7252 ASC_DBG(1, "end\n");
7253 return result;
7254 }
7255
7256 static bool AscHostReqRiscHalt(PortAddr iop_base)
7257 {
7258 int count = 0;
7259 bool sta = false;
7260 uchar saved_stop_code;
7261
7262 if (AscIsChipHalted(iop_base))
7263 return true;
7264 saved_stop_code = AscReadLramByte(iop_base, ASCV_STOP_CODE_B);
7265 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
7266 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP);
7267 do {
7268 if (AscIsChipHalted(iop_base)) {
7269 sta = true;
7270 break;
7271 }
7272 mdelay(100);
7273 } while (count++ < 20);
7274 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code);
7275 return sta;
7276 }
7277
7278 static bool
7279 AscSetRunChipSynRegAtID(PortAddr iop_base, uchar tid_no, uchar sdtr_data)
7280 {
7281 bool sta = false;
7282
7283 if (AscHostReqRiscHalt(iop_base)) {
7284 sta = AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
7285 AscStartChip(iop_base);
7286 }
7287 return sta;
7288 }
7289
7290 static void AscAsyncFix(ASC_DVC_VAR *asc_dvc, struct scsi_device *sdev)
7291 {
7292 char type = sdev->type;
7293 ASC_SCSI_BIT_ID_TYPE tid_bits = 1 << sdev->id;
7294
7295 if (!(asc_dvc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN))
7296 return;
7297 if (asc_dvc->init_sdtr & tid_bits)
7298 return;
7299
7300 if ((type == TYPE_ROM) && (strncmp(sdev->vendor, "HP ", 3) == 0))
7301 asc_dvc->pci_fix_asyn_xfer_always |= tid_bits;
7302
7303 asc_dvc->pci_fix_asyn_xfer |= tid_bits;
7304 if ((type == TYPE_PROCESSOR) || (type == TYPE_SCANNER) ||
7305 (type == TYPE_ROM) || (type == TYPE_TAPE))
7306 asc_dvc->pci_fix_asyn_xfer &= ~tid_bits;
7307
7308 if (asc_dvc->pci_fix_asyn_xfer & tid_bits)
7309 AscSetRunChipSynRegAtID(asc_dvc->iop_base, sdev->id,
7310 ASYN_SDTR_DATA_FIX_PCI_REV_AB);
7311 }
7312
7313 static void
7314 advansys_narrow_slave_configure(struct scsi_device *sdev, ASC_DVC_VAR *asc_dvc)
7315 {
7316 ASC_SCSI_BIT_ID_TYPE tid_bit = 1 << sdev->id;
7317 ASC_SCSI_BIT_ID_TYPE orig_use_tagged_qng = asc_dvc->use_tagged_qng;
7318
7319 if (sdev->lun == 0) {
7320 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr = asc_dvc->init_sdtr;
7321 if ((asc_dvc->cfg->sdtr_enable & tid_bit) && sdev->sdtr) {
7322 asc_dvc->init_sdtr |= tid_bit;
7323 } else {
7324 asc_dvc->init_sdtr &= ~tid_bit;
7325 }
7326
7327 if (orig_init_sdtr != asc_dvc->init_sdtr)
7328 AscAsyncFix(asc_dvc, sdev);
7329 }
7330
7331 if (sdev->tagged_supported) {
7332 if (asc_dvc->cfg->cmd_qng_enabled & tid_bit) {
7333 if (sdev->lun == 0) {
7334 asc_dvc->cfg->can_tagged_qng |= tid_bit;
7335 asc_dvc->use_tagged_qng |= tid_bit;
7336 }
7337 scsi_change_queue_depth(sdev,
7338 asc_dvc->max_dvc_qng[sdev->id]);
7339 }
7340 } else {
7341 if (sdev->lun == 0) {
7342 asc_dvc->cfg->can_tagged_qng &= ~tid_bit;
7343 asc_dvc->use_tagged_qng &= ~tid_bit;
7344 }
7345 }
7346
7347 if ((sdev->lun == 0) &&
7348 (orig_use_tagged_qng != asc_dvc->use_tagged_qng)) {
7349 AscWriteLramByte(asc_dvc->iop_base, ASCV_DISC_ENABLE_B,
7350 asc_dvc->cfg->disc_enable);
7351 AscWriteLramByte(asc_dvc->iop_base, ASCV_USE_TAGGED_QNG_B,
7352 asc_dvc->use_tagged_qng);
7353 AscWriteLramByte(asc_dvc->iop_base, ASCV_CAN_TAGGED_QNG_B,
7354 asc_dvc->cfg->can_tagged_qng);
7355
7356 asc_dvc->max_dvc_qng[sdev->id] =
7357 asc_dvc->cfg->max_tag_qng[sdev->id];
7358 AscWriteLramByte(asc_dvc->iop_base,
7359 (ushort)(ASCV_MAX_DVC_QNG_BEG + sdev->id),
7360 asc_dvc->max_dvc_qng[sdev->id]);
7361 }
7362 }
7363
7364 /*
7365 * Wide Transfers
7366 *
7367 * If the EEPROM enabled WDTR for the device and the device supports wide
7368 * bus (16 bit) transfers, then turn on the device's 'wdtr_able' bit and
7369 * write the new value to the microcode.
7370 */
7371 static void
7372 advansys_wide_enable_wdtr(AdvPortAddr iop_base, unsigned short tidmask)
7373 {
7374 unsigned short cfg_word;
7375 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
7376 if ((cfg_word & tidmask) != 0)
7377 return;
7378
7379 cfg_word |= tidmask;
7380 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
7381
7382 /*
7383 * Clear the microcode SDTR and WDTR negotiation done indicators for
7384 * the target to cause it to negotiate with the new setting set above.
7385 * WDTR when accepted causes the target to enter asynchronous mode, so
7386 * SDTR must be negotiated.
7387 */
7388 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7389 cfg_word &= ~tidmask;
7390 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7391 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
7392 cfg_word &= ~tidmask;
7393 AdvWriteWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
7394 }
7395
7396 /*
7397 * Synchronous Transfers
7398 *
7399 * If the EEPROM enabled SDTR for the device and the device
7400 * supports synchronous transfers, then turn on the device's
7401 * 'sdtr_able' bit. Write the new value to the microcode.
7402 */
7403 static void
7404 advansys_wide_enable_sdtr(AdvPortAddr iop_base, unsigned short tidmask)
7405 {
7406 unsigned short cfg_word;
7407 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
7408 if ((cfg_word & tidmask) != 0)
7409 return;
7410
7411 cfg_word |= tidmask;
7412 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
7413
7414 /*
7415 * Clear the microcode "SDTR negotiation" done indicator for the
7416 * target to cause it to negotiate with the new setting set above.
7417 */
7418 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7419 cfg_word &= ~tidmask;
7420 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7421 }
7422
7423 /*
7424 * PPR (Parallel Protocol Request) Capable
7425 *
7426 * If the device supports DT mode, then it must be PPR capable.
7427 * The PPR message will be used in place of the SDTR and WDTR
7428 * messages to negotiate synchronous speed and offset, transfer
7429 * width, and protocol options.
7430 */
7431 static void advansys_wide_enable_ppr(ADV_DVC_VAR *adv_dvc,
7432 AdvPortAddr iop_base, unsigned short tidmask)
7433 {
7434 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
7435 adv_dvc->ppr_able |= tidmask;
7436 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
7437 }
7438
7439 static void
7440 advansys_wide_slave_configure(struct scsi_device *sdev, ADV_DVC_VAR *adv_dvc)
7441 {
7442 AdvPortAddr iop_base = adv_dvc->iop_base;
7443 unsigned short tidmask = 1 << sdev->id;
7444
7445 if (sdev->lun == 0) {
7446 /*
7447 * Handle WDTR, SDTR, and Tag Queuing. If the feature
7448 * is enabled in the EEPROM and the device supports the
7449 * feature, then enable it in the microcode.
7450 */
7451
7452 if ((adv_dvc->wdtr_able & tidmask) && sdev->wdtr)
7453 advansys_wide_enable_wdtr(iop_base, tidmask);
7454 if ((adv_dvc->sdtr_able & tidmask) && sdev->sdtr)
7455 advansys_wide_enable_sdtr(iop_base, tidmask);
7456 if (adv_dvc->chip_type == ADV_CHIP_ASC38C1600 && sdev->ppr)
7457 advansys_wide_enable_ppr(adv_dvc, iop_base, tidmask);
7458
7459 /*
7460 * Tag Queuing is disabled for the BIOS which runs in polled
7461 * mode and would see no benefit from Tag Queuing. Also by
7462 * disabling Tag Queuing in the BIOS devices with Tag Queuing
7463 * bugs will at least work with the BIOS.
7464 */
7465 if ((adv_dvc->tagqng_able & tidmask) &&
7466 sdev->tagged_supported) {
7467 unsigned short cfg_word;
7468 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
7469 cfg_word |= tidmask;
7470 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
7471 cfg_word);
7472 AdvWriteByteLram(iop_base,
7473 ASC_MC_NUMBER_OF_MAX_CMD + sdev->id,
7474 adv_dvc->max_dvc_qng);
7475 }
7476 }
7477
7478 if ((adv_dvc->tagqng_able & tidmask) && sdev->tagged_supported)
7479 scsi_change_queue_depth(sdev, adv_dvc->max_dvc_qng);
7480 }
7481
7482 /*
7483 * Set the number of commands to queue per device for the
7484 * specified host adapter.
7485 */
7486 static int advansys_slave_configure(struct scsi_device *sdev)
7487 {
7488 struct asc_board *boardp = shost_priv(sdev->host);
7489
7490 if (ASC_NARROW_BOARD(boardp))
7491 advansys_narrow_slave_configure(sdev,
7492 &boardp->dvc_var.asc_dvc_var);
7493 else
7494 advansys_wide_slave_configure(sdev,
7495 &boardp->dvc_var.adv_dvc_var);
7496
7497 return 0;
7498 }
7499
7500 static __le32 asc_get_sense_buffer_dma(struct scsi_cmnd *scp)
7501 {
7502 struct asc_board *board = shost_priv(scp->device->host);
7503
7504 scp->SCp.dma_handle = dma_map_single(board->dev, scp->sense_buffer,
7505 SCSI_SENSE_BUFFERSIZE,
7506 DMA_FROM_DEVICE);
7507 if (dma_mapping_error(board->dev, scp->SCp.dma_handle)) {
7508 ASC_DBG(1, "failed to map sense buffer\n");
7509 return 0;
7510 }
7511 return cpu_to_le32(scp->SCp.dma_handle);
7512 }
7513
7514 static int asc_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
7515 struct asc_scsi_q *asc_scsi_q)
7516 {
7517 struct asc_dvc_var *asc_dvc = &boardp->dvc_var.asc_dvc_var;
7518 int use_sg;
7519 u32 srb_tag;
7520
7521 memset(asc_scsi_q, 0, sizeof(*asc_scsi_q));
7522
7523 /*
7524 * Set the srb_tag to the command tag + 1, as
7525 * srb_tag '0' is used internally by the chip.
7526 */
7527 srb_tag = scp->request->tag + 1;
7528 asc_scsi_q->q2.srb_tag = srb_tag;
7529
7530 /*
7531 * Build the ASC_SCSI_Q request.
7532 */
7533 asc_scsi_q->cdbptr = &scp->cmnd[0];
7534 asc_scsi_q->q2.cdb_len = scp->cmd_len;
7535 asc_scsi_q->q1.target_id = ASC_TID_TO_TARGET_ID(scp->device->id);
7536 asc_scsi_q->q1.target_lun = scp->device->lun;
7537 asc_scsi_q->q2.target_ix =
7538 ASC_TIDLUN_TO_IX(scp->device->id, scp->device->lun);
7539 asc_scsi_q->q1.sense_addr = asc_get_sense_buffer_dma(scp);
7540 asc_scsi_q->q1.sense_len = SCSI_SENSE_BUFFERSIZE;
7541 if (!asc_scsi_q->q1.sense_addr)
7542 return ASC_BUSY;
7543
7544 /*
7545 * If there are any outstanding requests for the current target,
7546 * then every 255th request send an ORDERED request. This heuristic
7547 * tries to retain the benefit of request sorting while preventing
7548 * request starvation. 255 is the max number of tags or pending commands
7549 * a device may have outstanding.
7550 *
7551 * The request count is incremented below for every successfully
7552 * started request.
7553 *
7554 */
7555 if ((asc_dvc->cur_dvc_qng[scp->device->id] > 0) &&
7556 (boardp->reqcnt[scp->device->id] % 255) == 0) {
7557 asc_scsi_q->q2.tag_code = ORDERED_QUEUE_TAG;
7558 } else {
7559 asc_scsi_q->q2.tag_code = SIMPLE_QUEUE_TAG;
7560 }
7561
7562 /* Build ASC_SCSI_Q */
7563 use_sg = scsi_dma_map(scp);
7564 if (use_sg < 0) {
7565 ASC_DBG(1, "failed to map sglist\n");
7566 return ASC_BUSY;
7567 } else if (use_sg > 0) {
7568 int sgcnt;
7569 struct scatterlist *slp;
7570 struct asc_sg_head *asc_sg_head;
7571
7572 if (use_sg > scp->device->host->sg_tablesize) {
7573 scmd_printk(KERN_ERR, scp, "use_sg %d > "
7574 "sg_tablesize %d\n", use_sg,
7575 scp->device->host->sg_tablesize);
7576 scsi_dma_unmap(scp);
7577 scp->result = HOST_BYTE(DID_ERROR);
7578 return ASC_ERROR;
7579 }
7580
7581 asc_sg_head = kzalloc(sizeof(asc_scsi_q->sg_head) +
7582 use_sg * sizeof(struct asc_sg_list), GFP_ATOMIC);
7583 if (!asc_sg_head) {
7584 scsi_dma_unmap(scp);
7585 scp->result = HOST_BYTE(DID_SOFT_ERROR);
7586 return ASC_ERROR;
7587 }
7588
7589 asc_scsi_q->q1.cntl |= QC_SG_HEAD;
7590 asc_scsi_q->sg_head = asc_sg_head;
7591 asc_scsi_q->q1.data_cnt = 0;
7592 asc_scsi_q->q1.data_addr = 0;
7593 /* This is a byte value, otherwise it would need to be swapped. */
7594 asc_sg_head->entry_cnt = asc_scsi_q->q1.sg_queue_cnt = use_sg;
7595 ASC_STATS_ADD(scp->device->host, xfer_elem,
7596 asc_sg_head->entry_cnt);
7597
7598 /*
7599 * Convert scatter-gather list into ASC_SG_HEAD list.
7600 */
7601 scsi_for_each_sg(scp, slp, use_sg, sgcnt) {
7602 asc_sg_head->sg_list[sgcnt].addr =
7603 cpu_to_le32(sg_dma_address(slp));
7604 asc_sg_head->sg_list[sgcnt].bytes =
7605 cpu_to_le32(sg_dma_len(slp));
7606 ASC_STATS_ADD(scp->device->host, xfer_sect,
7607 DIV_ROUND_UP(sg_dma_len(slp), 512));
7608 }
7609 }
7610
7611 ASC_STATS(scp->device->host, xfer_cnt);
7612
7613 ASC_DBG_PRT_ASC_SCSI_Q(2, asc_scsi_q);
7614 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
7615
7616 return ASC_NOERROR;
7617 }
7618
7619 /*
7620 * Build scatter-gather list for Adv Library (Wide Board).
7621 *
7622 * Additional ADV_SG_BLOCK structures will need to be allocated
7623 * if the total number of scatter-gather elements exceeds
7624 * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are
7625 * assumed to be physically contiguous.
7626 *
7627 * Return:
7628 * ADV_SUCCESS(1) - SG List successfully created
7629 * ADV_ERROR(-1) - SG List creation failed
7630 */
7631 static int
7632 adv_get_sglist(struct asc_board *boardp, adv_req_t *reqp,
7633 ADV_SCSI_REQ_Q *scsiqp, struct scsi_cmnd *scp, int use_sg)
7634 {
7635 adv_sgblk_t *sgblkp, *prev_sgblkp;
7636 struct scatterlist *slp;
7637 int sg_elem_cnt;
7638 ADV_SG_BLOCK *sg_block, *prev_sg_block;
7639 dma_addr_t sgblk_paddr;
7640 int i;
7641
7642 slp = scsi_sglist(scp);
7643 sg_elem_cnt = use_sg;
7644 prev_sgblkp = NULL;
7645 prev_sg_block = NULL;
7646 reqp->sgblkp = NULL;
7647
7648 for (;;) {
7649 /*
7650 * Allocate a 'adv_sgblk_t' structure from the board free
7651 * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK
7652 * (15) scatter-gather elements.
7653 */
7654 sgblkp = dma_pool_alloc(boardp->adv_sgblk_pool, GFP_ATOMIC,
7655 &sgblk_paddr);
7656 if (!sgblkp) {
7657 ASC_DBG(1, "no free adv_sgblk_t\n");
7658 ASC_STATS(scp->device->host, adv_build_nosg);
7659
7660 /*
7661 * Allocation failed. Free 'adv_sgblk_t' structures
7662 * already allocated for the request.
7663 */
7664 while ((sgblkp = reqp->sgblkp) != NULL) {
7665 /* Remove 'sgblkp' from the request list. */
7666 reqp->sgblkp = sgblkp->next_sgblkp;
7667 sgblkp->next_sgblkp = NULL;
7668 dma_pool_free(boardp->adv_sgblk_pool, sgblkp,
7669 sgblkp->sg_addr);
7670 }
7671 return ASC_BUSY;
7672 }
7673 /* Complete 'adv_sgblk_t' board allocation. */
7674 sgblkp->sg_addr = sgblk_paddr;
7675 sgblkp->next_sgblkp = NULL;
7676 sg_block = &sgblkp->sg_block;
7677
7678 /*
7679 * Check if this is the first 'adv_sgblk_t' for the
7680 * request.
7681 */
7682 if (reqp->sgblkp == NULL) {
7683 /* Request's first scatter-gather block. */
7684 reqp->sgblkp = sgblkp;
7685
7686 /*
7687 * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical
7688 * address pointers.
7689 */
7690 scsiqp->sg_list_ptr = sg_block;
7691 scsiqp->sg_real_addr = cpu_to_le32(sgblk_paddr);
7692 } else {
7693 /* Request's second or later scatter-gather block. */
7694 prev_sgblkp->next_sgblkp = sgblkp;
7695
7696 /*
7697 * Point the previous ADV_SG_BLOCK structure to
7698 * the newly allocated ADV_SG_BLOCK structure.
7699 */
7700 prev_sg_block->sg_ptr = cpu_to_le32(sgblk_paddr);
7701 }
7702
7703 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) {
7704 sg_block->sg_list[i].sg_addr =
7705 cpu_to_le32(sg_dma_address(slp));
7706 sg_block->sg_list[i].sg_count =
7707 cpu_to_le32(sg_dma_len(slp));
7708 ASC_STATS_ADD(scp->device->host, xfer_sect,
7709 DIV_ROUND_UP(sg_dma_len(slp), 512));
7710
7711 if (--sg_elem_cnt == 0) {
7712 /*
7713 * Last ADV_SG_BLOCK and scatter-gather entry.
7714 */
7715 sg_block->sg_cnt = i + 1;
7716 sg_block->sg_ptr = 0L; /* Last ADV_SG_BLOCK in list. */
7717 return ADV_SUCCESS;
7718 }
7719 slp++;
7720 }
7721 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
7722 prev_sg_block = sg_block;
7723 prev_sgblkp = sgblkp;
7724 }
7725 }
7726
7727 /*
7728 * Build a request structure for the Adv Library (Wide Board).
7729 *
7730 * If an adv_req_t can not be allocated to issue the request,
7731 * then return ASC_BUSY. If an error occurs, then return ASC_ERROR.
7732 *
7733 * Multi-byte fields in the ADV_SCSI_REQ_Q that are used by the
7734 * microcode for DMA addresses or math operations are byte swapped
7735 * to little-endian order.
7736 */
7737 static int
7738 adv_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
7739 adv_req_t **adv_reqpp)
7740 {
7741 u32 srb_tag = scp->request->tag;
7742 adv_req_t *reqp;
7743 ADV_SCSI_REQ_Q *scsiqp;
7744 int ret;
7745 int use_sg;
7746 dma_addr_t sense_addr;
7747
7748 /*
7749 * Allocate an adv_req_t structure from the board to execute
7750 * the command.
7751 */
7752 reqp = &boardp->adv_reqp[srb_tag];
7753 if (reqp->cmndp && reqp->cmndp != scp ) {
7754 ASC_DBG(1, "no free adv_req_t\n");
7755 ASC_STATS(scp->device->host, adv_build_noreq);
7756 return ASC_BUSY;
7757 }
7758
7759 reqp->req_addr = boardp->adv_reqp_addr + (srb_tag * sizeof(adv_req_t));
7760
7761 scsiqp = &reqp->scsi_req_q;
7762
7763 /*
7764 * Initialize the structure.
7765 */
7766 scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0;
7767
7768 /*
7769 * Set the srb_tag to the command tag.
7770 */
7771 scsiqp->srb_tag = srb_tag;
7772
7773 /*
7774 * Set 'host_scribble' to point to the adv_req_t structure.
7775 */
7776 reqp->cmndp = scp;
7777 scp->host_scribble = (void *)reqp;
7778
7779 /*
7780 * Build the ADV_SCSI_REQ_Q request.
7781 */
7782
7783 /* Set CDB length and copy it to the request structure. */
7784 scsiqp->cdb_len = scp->cmd_len;
7785 /* Copy first 12 CDB bytes to cdb[]. */
7786 memcpy(scsiqp->cdb, scp->cmnd, scp->cmd_len < 12 ? scp->cmd_len : 12);
7787 /* Copy last 4 CDB bytes, if present, to cdb16[]. */
7788 if (scp->cmd_len > 12) {
7789 int cdb16_len = scp->cmd_len - 12;
7790
7791 memcpy(scsiqp->cdb16, &scp->cmnd[12], cdb16_len);
7792 }
7793
7794 scsiqp->target_id = scp->device->id;
7795 scsiqp->target_lun = scp->device->lun;
7796
7797 sense_addr = dma_map_single(boardp->dev, scp->sense_buffer,
7798 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
7799 if (dma_mapping_error(boardp->dev, sense_addr)) {
7800 ASC_DBG(1, "failed to map sense buffer\n");
7801 ASC_STATS(scp->device->host, adv_build_noreq);
7802 return ASC_BUSY;
7803 }
7804 scsiqp->sense_addr = cpu_to_le32(sense_addr);
7805 scsiqp->sense_len = cpu_to_le32(SCSI_SENSE_BUFFERSIZE);
7806
7807 /* Build ADV_SCSI_REQ_Q */
7808
7809 use_sg = scsi_dma_map(scp);
7810 if (use_sg < 0) {
7811 ASC_DBG(1, "failed to map SG list\n");
7812 ASC_STATS(scp->device->host, adv_build_noreq);
7813 return ASC_BUSY;
7814 } else if (use_sg == 0) {
7815 /* Zero-length transfer */
7816 reqp->sgblkp = NULL;
7817 scsiqp->data_cnt = 0;
7818
7819 scsiqp->data_addr = 0;
7820 scsiqp->sg_list_ptr = NULL;
7821 scsiqp->sg_real_addr = 0;
7822 } else {
7823 if (use_sg > ADV_MAX_SG_LIST) {
7824 scmd_printk(KERN_ERR, scp, "use_sg %d > "
7825 "ADV_MAX_SG_LIST %d\n", use_sg,
7826 scp->device->host->sg_tablesize);
7827 scsi_dma_unmap(scp);
7828 scp->result = HOST_BYTE(DID_ERROR);
7829 reqp->cmndp = NULL;
7830 scp->host_scribble = NULL;
7831
7832 return ASC_ERROR;
7833 }
7834
7835 scsiqp->data_cnt = cpu_to_le32(scsi_bufflen(scp));
7836
7837 ret = adv_get_sglist(boardp, reqp, scsiqp, scp, use_sg);
7838 if (ret != ADV_SUCCESS) {
7839 scsi_dma_unmap(scp);
7840 scp->result = HOST_BYTE(DID_ERROR);
7841 reqp->cmndp = NULL;
7842 scp->host_scribble = NULL;
7843
7844 return ret;
7845 }
7846
7847 ASC_STATS_ADD(scp->device->host, xfer_elem, use_sg);
7848 }
7849
7850 ASC_STATS(scp->device->host, xfer_cnt);
7851
7852 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
7853 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
7854
7855 *adv_reqpp = reqp;
7856
7857 return ASC_NOERROR;
7858 }
7859
7860 static int AscSgListToQueue(int sg_list)
7861 {
7862 int n_sg_list_qs;
7863
7864 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q);
7865 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0)
7866 n_sg_list_qs++;
7867 return n_sg_list_qs + 1;
7868 }
7869
7870 static uint
7871 AscGetNumOfFreeQueue(ASC_DVC_VAR *asc_dvc, uchar target_ix, uchar n_qs)
7872 {
7873 uint cur_used_qs;
7874 uint cur_free_qs;
7875 ASC_SCSI_BIT_ID_TYPE target_id;
7876 uchar tid_no;
7877
7878 target_id = ASC_TIX_TO_TARGET_ID(target_ix);
7879 tid_no = ASC_TIX_TO_TID(target_ix);
7880 if ((asc_dvc->unit_not_ready & target_id) ||
7881 (asc_dvc->queue_full_or_busy & target_id)) {
7882 return 0;
7883 }
7884 if (n_qs == 1) {
7885 cur_used_qs = (uint) asc_dvc->cur_total_qng +
7886 (uint) asc_dvc->last_q_shortage + (uint) ASC_MIN_FREE_Q;
7887 } else {
7888 cur_used_qs = (uint) asc_dvc->cur_total_qng +
7889 (uint) ASC_MIN_FREE_Q;
7890 }
7891 if ((uint) (cur_used_qs + n_qs) <= (uint) asc_dvc->max_total_qng) {
7892 cur_free_qs = (uint) asc_dvc->max_total_qng - cur_used_qs;
7893 if (asc_dvc->cur_dvc_qng[tid_no] >=
7894 asc_dvc->max_dvc_qng[tid_no]) {
7895 return 0;
7896 }
7897 return cur_free_qs;
7898 }
7899 if (n_qs > 1) {
7900 if ((n_qs > asc_dvc->last_q_shortage)
7901 && (n_qs <= (asc_dvc->max_total_qng - ASC_MIN_FREE_Q))) {
7902 asc_dvc->last_q_shortage = n_qs;
7903 }
7904 }
7905 return 0;
7906 }
7907
7908 static uchar AscAllocFreeQueue(PortAddr iop_base, uchar free_q_head)
7909 {
7910 ushort q_addr;
7911 uchar next_qp;
7912 uchar q_status;
7913
7914 q_addr = ASC_QNO_TO_QADDR(free_q_head);
7915 q_status = (uchar)AscReadLramByte(iop_base,
7916 (ushort)(q_addr +
7917 ASC_SCSIQ_B_STATUS));
7918 next_qp = AscReadLramByte(iop_base, (ushort)(q_addr + ASC_SCSIQ_B_FWD));
7919 if (((q_status & QS_READY) == 0) && (next_qp != ASC_QLINK_END))
7920 return next_qp;
7921 return ASC_QLINK_END;
7922 }
7923
7924 static uchar
7925 AscAllocMultipleFreeQueue(PortAddr iop_base, uchar free_q_head, uchar n_free_q)
7926 {
7927 uchar i;
7928
7929 for (i = 0; i < n_free_q; i++) {
7930 free_q_head = AscAllocFreeQueue(iop_base, free_q_head);
7931 if (free_q_head == ASC_QLINK_END)
7932 break;
7933 }
7934 return free_q_head;
7935 }
7936
7937 /*
7938 * void
7939 * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
7940 *
7941 * Calling/Exit State:
7942 * none
7943 *
7944 * Description:
7945 * Output an ASC_SCSI_Q structure to the chip
7946 */
7947 static void
7948 DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
7949 {
7950 int i;
7951
7952 ASC_DBG_PRT_HEX(2, "DvcPutScsiQ", outbuf, 2 * words);
7953 AscSetChipLramAddr(iop_base, s_addr);
7954 for (i = 0; i < 2 * words; i += 2) {
7955 if (i == 4 || i == 20) {
7956 continue;
7957 }
7958 outpw(iop_base + IOP_RAM_DATA,
7959 ((ushort)outbuf[i + 1] << 8) | outbuf[i]);
7960 }
7961 }
7962
7963 static int AscPutReadyQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
7964 {
7965 ushort q_addr;
7966 uchar tid_no;
7967 uchar sdtr_data;
7968 uchar syn_period_ix;
7969 uchar syn_offset;
7970 PortAddr iop_base;
7971
7972 iop_base = asc_dvc->iop_base;
7973 if (((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) &&
7974 ((asc_dvc->sdtr_done & scsiq->q1.target_id) == 0)) {
7975 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix);
7976 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
7977 syn_period_ix =
7978 (sdtr_data >> 4) & (asc_dvc->max_sdtr_index - 1);
7979 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
7980 AscMsgOutSDTR(asc_dvc,
7981 asc_dvc->sdtr_period_tbl[syn_period_ix],
7982 syn_offset);
7983 scsiq->q1.cntl |= QC_MSG_OUT;
7984 }
7985 q_addr = ASC_QNO_TO_QADDR(q_no);
7986 if ((scsiq->q1.target_id & asc_dvc->use_tagged_qng) == 0) {
7987 scsiq->q2.tag_code &= ~SIMPLE_QUEUE_TAG;
7988 }
7989 scsiq->q1.status = QS_FREE;
7990 AscMemWordCopyPtrToLram(iop_base,
7991 q_addr + ASC_SCSIQ_CDB_BEG,
7992 (uchar *)scsiq->cdbptr, scsiq->q2.cdb_len >> 1);
7993
7994 DvcPutScsiQ(iop_base,
7995 q_addr + ASC_SCSIQ_CPY_BEG,
7996 (uchar *)&scsiq->q1.cntl,
7997 ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1);
7998 AscWriteLramWord(iop_base,
7999 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS),
8000 (ushort)(((ushort)scsiq->q1.
8001 q_no << 8) | (ushort)QS_READY));
8002 return 1;
8003 }
8004
8005 static int
8006 AscPutReadySgListQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
8007 {
8008 int sta;
8009 int i;
8010 ASC_SG_HEAD *sg_head;
8011 ASC_SG_LIST_Q scsi_sg_q;
8012 __le32 saved_data_addr;
8013 __le32 saved_data_cnt;
8014 PortAddr iop_base;
8015 ushort sg_list_dwords;
8016 ushort sg_index;
8017 ushort sg_entry_cnt;
8018 ushort q_addr;
8019 uchar next_qp;
8020
8021 iop_base = asc_dvc->iop_base;
8022 sg_head = scsiq->sg_head;
8023 saved_data_addr = scsiq->q1.data_addr;
8024 saved_data_cnt = scsiq->q1.data_cnt;
8025 scsiq->q1.data_addr = cpu_to_le32(sg_head->sg_list[0].addr);
8026 scsiq->q1.data_cnt = cpu_to_le32(sg_head->sg_list[0].bytes);
8027 /*
8028 * Set sg_entry_cnt to be the number of SG elements that
8029 * will fit in the allocated SG queues. It is minus 1, because
8030 * the first SG element is handled above.
8031 */
8032 sg_entry_cnt = sg_head->entry_cnt - 1;
8033
8034 if (sg_entry_cnt != 0) {
8035 scsiq->q1.cntl |= QC_SG_HEAD;
8036 q_addr = ASC_QNO_TO_QADDR(q_no);
8037 sg_index = 1;
8038 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt;
8039 scsi_sg_q.sg_head_qp = q_no;
8040 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
8041 for (i = 0; i < sg_head->queue_cnt; i++) {
8042 scsi_sg_q.seq_no = i + 1;
8043 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
8044 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
8045 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
8046 if (i == 0) {
8047 scsi_sg_q.sg_list_cnt =
8048 ASC_SG_LIST_PER_Q;
8049 scsi_sg_q.sg_cur_list_cnt =
8050 ASC_SG_LIST_PER_Q;
8051 } else {
8052 scsi_sg_q.sg_list_cnt =
8053 ASC_SG_LIST_PER_Q - 1;
8054 scsi_sg_q.sg_cur_list_cnt =
8055 ASC_SG_LIST_PER_Q - 1;
8056 }
8057 } else {
8058 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
8059 sg_list_dwords = sg_entry_cnt << 1;
8060 if (i == 0) {
8061 scsi_sg_q.sg_list_cnt = sg_entry_cnt;
8062 scsi_sg_q.sg_cur_list_cnt =
8063 sg_entry_cnt;
8064 } else {
8065 scsi_sg_q.sg_list_cnt =
8066 sg_entry_cnt - 1;
8067 scsi_sg_q.sg_cur_list_cnt =
8068 sg_entry_cnt - 1;
8069 }
8070 sg_entry_cnt = 0;
8071 }
8072 next_qp = AscReadLramByte(iop_base,
8073 (ushort)(q_addr +
8074 ASC_SCSIQ_B_FWD));
8075 scsi_sg_q.q_no = next_qp;
8076 q_addr = ASC_QNO_TO_QADDR(next_qp);
8077 AscMemWordCopyPtrToLram(iop_base,
8078 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
8079 (uchar *)&scsi_sg_q,
8080 sizeof(ASC_SG_LIST_Q) >> 1);
8081 AscMemDWordCopyPtrToLram(iop_base,
8082 q_addr + ASC_SGQ_LIST_BEG,
8083 (uchar *)&sg_head->
8084 sg_list[sg_index],
8085 sg_list_dwords);
8086 sg_index += ASC_SG_LIST_PER_Q;
8087 scsiq->next_sg_index = sg_index;
8088 }
8089 } else {
8090 scsiq->q1.cntl &= ~QC_SG_HEAD;
8091 }
8092 sta = AscPutReadyQueue(asc_dvc, scsiq, q_no);
8093 scsiq->q1.data_addr = saved_data_addr;
8094 scsiq->q1.data_cnt = saved_data_cnt;
8095 return (sta);
8096 }
8097
8098 static int
8099 AscSendScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar n_q_required)
8100 {
8101 PortAddr iop_base;
8102 uchar free_q_head;
8103 uchar next_qp;
8104 uchar tid_no;
8105 uchar target_ix;
8106 int sta;
8107
8108 iop_base = asc_dvc->iop_base;
8109 target_ix = scsiq->q2.target_ix;
8110 tid_no = ASC_TIX_TO_TID(target_ix);
8111 sta = 0;
8112 free_q_head = (uchar)AscGetVarFreeQHead(iop_base);
8113 if (n_q_required > 1) {
8114 next_qp = AscAllocMultipleFreeQueue(iop_base, free_q_head,
8115 (uchar)n_q_required);
8116 if (next_qp != ASC_QLINK_END) {
8117 asc_dvc->last_q_shortage = 0;
8118 scsiq->sg_head->queue_cnt = n_q_required - 1;
8119 scsiq->q1.q_no = free_q_head;
8120 sta = AscPutReadySgListQueue(asc_dvc, scsiq,
8121 free_q_head);
8122 }
8123 } else if (n_q_required == 1) {
8124 next_qp = AscAllocFreeQueue(iop_base, free_q_head);
8125 if (next_qp != ASC_QLINK_END) {
8126 scsiq->q1.q_no = free_q_head;
8127 sta = AscPutReadyQueue(asc_dvc, scsiq, free_q_head);
8128 }
8129 }
8130 if (sta == 1) {
8131 AscPutVarFreeQHead(iop_base, next_qp);
8132 asc_dvc->cur_total_qng += n_q_required;
8133 asc_dvc->cur_dvc_qng[tid_no]++;
8134 }
8135 return sta;
8136 }
8137
8138 #define ASC_SYN_OFFSET_ONE_DISABLE_LIST 16
8139 static uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] = {
8140 INQUIRY,
8141 REQUEST_SENSE,
8142 READ_CAPACITY,
8143 READ_TOC,
8144 MODE_SELECT,
8145 MODE_SENSE,
8146 MODE_SELECT_10,
8147 MODE_SENSE_10,
8148 0xFF,
8149 0xFF,
8150 0xFF,
8151 0xFF,
8152 0xFF,
8153 0xFF,
8154 0xFF,
8155 0xFF
8156 };
8157
8158 static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq)
8159 {
8160 PortAddr iop_base;
8161 int sta;
8162 int n_q_required;
8163 bool disable_syn_offset_one_fix;
8164 int i;
8165 u32 addr;
8166 ushort sg_entry_cnt = 0;
8167 ushort sg_entry_cnt_minus_one = 0;
8168 uchar target_ix;
8169 uchar tid_no;
8170 uchar sdtr_data;
8171 uchar extra_bytes;
8172 uchar scsi_cmd;
8173 uchar disable_cmd;
8174 ASC_SG_HEAD *sg_head;
8175 unsigned long data_cnt;
8176
8177 iop_base = asc_dvc->iop_base;
8178 sg_head = scsiq->sg_head;
8179 if (asc_dvc->err_code != 0)
8180 return ASC_ERROR;
8181 scsiq->q1.q_no = 0;
8182 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) {
8183 scsiq->q1.extra_bytes = 0;
8184 }
8185 sta = 0;
8186 target_ix = scsiq->q2.target_ix;
8187 tid_no = ASC_TIX_TO_TID(target_ix);
8188 n_q_required = 1;
8189 if (scsiq->cdbptr[0] == REQUEST_SENSE) {
8190 if ((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) {
8191 asc_dvc->sdtr_done &= ~scsiq->q1.target_id;
8192 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
8193 AscMsgOutSDTR(asc_dvc,
8194 asc_dvc->
8195 sdtr_period_tbl[(sdtr_data >> 4) &
8196 (uchar)(asc_dvc->
8197 max_sdtr_index -
8198 1)],
8199 (uchar)(sdtr_data & (uchar)
8200 ASC_SYN_MAX_OFFSET));
8201 scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT);
8202 }
8203 }
8204 if (asc_dvc->in_critical_cnt != 0) {
8205 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY);
8206 return ASC_ERROR;
8207 }
8208 asc_dvc->in_critical_cnt++;
8209 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
8210 if ((sg_entry_cnt = sg_head->entry_cnt) == 0) {
8211 asc_dvc->in_critical_cnt--;
8212 return ASC_ERROR;
8213 }
8214 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
8215 asc_dvc->in_critical_cnt--;
8216 return ASC_ERROR;
8217 }
8218 if (sg_entry_cnt == 1) {
8219 scsiq->q1.data_addr = cpu_to_le32(sg_head->sg_list[0].addr);
8220 scsiq->q1.data_cnt = cpu_to_le32(sg_head->sg_list[0].bytes);
8221 scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE);
8222 }
8223 sg_entry_cnt_minus_one = sg_entry_cnt - 1;
8224 }
8225 scsi_cmd = scsiq->cdbptr[0];
8226 disable_syn_offset_one_fix = false;
8227 if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) &&
8228 !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) {
8229 if (scsiq->q1.cntl & QC_SG_HEAD) {
8230 data_cnt = 0;
8231 for (i = 0; i < sg_entry_cnt; i++) {
8232 data_cnt += le32_to_cpu(sg_head->sg_list[i].
8233 bytes);
8234 }
8235 } else {
8236 data_cnt = le32_to_cpu(scsiq->q1.data_cnt);
8237 }
8238 if (data_cnt != 0UL) {
8239 if (data_cnt < 512UL) {
8240 disable_syn_offset_one_fix = true;
8241 } else {
8242 for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST;
8243 i++) {
8244 disable_cmd =
8245 _syn_offset_one_disable_cmd[i];
8246 if (disable_cmd == 0xFF) {
8247 break;
8248 }
8249 if (scsi_cmd == disable_cmd) {
8250 disable_syn_offset_one_fix =
8251 true;
8252 break;
8253 }
8254 }
8255 }
8256 }
8257 }
8258 if (disable_syn_offset_one_fix) {
8259 scsiq->q2.tag_code &= ~SIMPLE_QUEUE_TAG;
8260 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX |
8261 ASC_TAG_FLAG_DISABLE_DISCONNECT);
8262 } else {
8263 scsiq->q2.tag_code &= 0x27;
8264 }
8265 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
8266 if (asc_dvc->bug_fix_cntl) {
8267 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
8268 if ((scsi_cmd == READ_6) ||
8269 (scsi_cmd == READ_10)) {
8270 addr = le32_to_cpu(sg_head->
8271 sg_list
8272 [sg_entry_cnt_minus_one].
8273 addr) +
8274 le32_to_cpu(sg_head->
8275 sg_list
8276 [sg_entry_cnt_minus_one].
8277 bytes);
8278 extra_bytes =
8279 (uchar)((ushort)addr & 0x0003);
8280 if ((extra_bytes != 0)
8281 &&
8282 ((scsiq->q2.
8283 tag_code &
8284 ASC_TAG_FLAG_EXTRA_BYTES)
8285 == 0)) {
8286 scsiq->q2.tag_code |=
8287 ASC_TAG_FLAG_EXTRA_BYTES;
8288 scsiq->q1.extra_bytes =
8289 extra_bytes;
8290 data_cnt =
8291 le32_to_cpu(sg_head->
8292 sg_list
8293 [sg_entry_cnt_minus_one].
8294 bytes);
8295 data_cnt -= extra_bytes;
8296 sg_head->
8297 sg_list
8298 [sg_entry_cnt_minus_one].
8299 bytes =
8300 cpu_to_le32(data_cnt);
8301 }
8302 }
8303 }
8304 }
8305 sg_head->entry_to_copy = sg_head->entry_cnt;
8306 n_q_required = AscSgListToQueue(sg_entry_cnt);
8307 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, n_q_required) >=
8308 (uint) n_q_required)
8309 || ((scsiq->q1.cntl & QC_URGENT) != 0)) {
8310 if ((sta =
8311 AscSendScsiQueue(asc_dvc, scsiq,
8312 n_q_required)) == 1) {
8313 asc_dvc->in_critical_cnt--;
8314 return (sta);
8315 }
8316 }
8317 } else {
8318 if (asc_dvc->bug_fix_cntl) {
8319 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
8320 if ((scsi_cmd == READ_6) ||
8321 (scsi_cmd == READ_10)) {
8322 addr =
8323 le32_to_cpu(scsiq->q1.data_addr) +
8324 le32_to_cpu(scsiq->q1.data_cnt);
8325 extra_bytes =
8326 (uchar)((ushort)addr & 0x0003);
8327 if ((extra_bytes != 0)
8328 &&
8329 ((scsiq->q2.
8330 tag_code &
8331 ASC_TAG_FLAG_EXTRA_BYTES)
8332 == 0)) {
8333 data_cnt =
8334 le32_to_cpu(scsiq->q1.
8335 data_cnt);
8336 if (((ushort)data_cnt & 0x01FF)
8337 == 0) {
8338 scsiq->q2.tag_code |=
8339 ASC_TAG_FLAG_EXTRA_BYTES;
8340 data_cnt -= extra_bytes;
8341 scsiq->q1.data_cnt =
8342 cpu_to_le32
8343 (data_cnt);
8344 scsiq->q1.extra_bytes =
8345 extra_bytes;
8346 }
8347 }
8348 }
8349 }
8350 }
8351 n_q_required = 1;
8352 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, 1) >= 1) ||
8353 ((scsiq->q1.cntl & QC_URGENT) != 0)) {
8354 if ((sta = AscSendScsiQueue(asc_dvc, scsiq,
8355 n_q_required)) == 1) {
8356 asc_dvc->in_critical_cnt--;
8357 return (sta);
8358 }
8359 }
8360 }
8361 asc_dvc->in_critical_cnt--;
8362 return (sta);
8363 }
8364
8365 /*
8366 * AdvExeScsiQueue() - Send a request to the RISC microcode program.
8367 *
8368 * Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q,
8369 * add the carrier to the ICQ (Initiator Command Queue), and tickle the
8370 * RISC to notify it a new command is ready to be executed.
8371 *
8372 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
8373 * set to SCSI_MAX_RETRY.
8374 *
8375 * Multi-byte fields in the ADV_SCSI_REQ_Q that are used by the microcode
8376 * for DMA addresses or math operations are byte swapped to little-endian
8377 * order.
8378 *
8379 * Return:
8380 * ADV_SUCCESS(1) - The request was successfully queued.
8381 * ADV_BUSY(0) - Resource unavailable; Retry again after pending
8382 * request completes.
8383 * ADV_ERROR(-1) - Invalid ADV_SCSI_REQ_Q request structure
8384 * host IC error.
8385 */
8386 static int AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc, adv_req_t *reqp)
8387 {
8388 AdvPortAddr iop_base;
8389 ADV_CARR_T *new_carrp;
8390 ADV_SCSI_REQ_Q *scsiq = &reqp->scsi_req_q;
8391
8392 /*
8393 * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID.
8394 */
8395 if (scsiq->target_id > ADV_MAX_TID) {
8396 scsiq->host_status = QHSTA_M_INVALID_DEVICE;
8397 scsiq->done_status = QD_WITH_ERROR;
8398 return ADV_ERROR;
8399 }
8400
8401 iop_base = asc_dvc->iop_base;
8402
8403 /*
8404 * Allocate a carrier ensuring at least one carrier always
8405 * remains on the freelist and initialize fields.
8406 */
8407 new_carrp = adv_get_next_carrier(asc_dvc);
8408 if (!new_carrp) {
8409 ASC_DBG(1, "No free carriers\n");
8410 return ADV_BUSY;
8411 }
8412
8413 asc_dvc->carr_pending_cnt++;
8414
8415 /* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */
8416 scsiq->scsiq_ptr = cpu_to_le32(scsiq->srb_tag);
8417 scsiq->scsiq_rptr = cpu_to_le32(reqp->req_addr);
8418
8419 scsiq->carr_va = asc_dvc->icq_sp->carr_va;
8420 scsiq->carr_pa = asc_dvc->icq_sp->carr_pa;
8421
8422 /*
8423 * Use the current stopper to send the ADV_SCSI_REQ_Q command to
8424 * the microcode. The newly allocated stopper will become the new
8425 * stopper.
8426 */
8427 asc_dvc->icq_sp->areq_vpa = scsiq->scsiq_rptr;
8428
8429 /*
8430 * Set the 'next_vpa' pointer for the old stopper to be the
8431 * physical address of the new stopper. The RISC can only
8432 * follow physical addresses.
8433 */
8434 asc_dvc->icq_sp->next_vpa = new_carrp->carr_pa;
8435
8436 /*
8437 * Set the host adapter stopper pointer to point to the new carrier.
8438 */
8439 asc_dvc->icq_sp = new_carrp;
8440
8441 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
8442 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
8443 /*
8444 * Tickle the RISC to tell it to read its Command Queue Head pointer.
8445 */
8446 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
8447 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
8448 /*
8449 * Clear the tickle value. In the ASC-3550 the RISC flag
8450 * command 'clr_tickle_a' does not work unless the host
8451 * value is cleared.
8452 */
8453 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
8454 ADV_TICKLE_NOP);
8455 }
8456 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
8457 /*
8458 * Notify the RISC a carrier is ready by writing the physical
8459 * address of the new carrier stopper to the COMMA register.
8460 */
8461 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
8462 le32_to_cpu(new_carrp->carr_pa));
8463 }
8464
8465 return ADV_SUCCESS;
8466 }
8467
8468 /*
8469 * Execute a single 'Scsi_Cmnd'.
8470 */
8471 static int asc_execute_scsi_cmnd(struct scsi_cmnd *scp)
8472 {
8473 int ret, err_code;
8474 struct asc_board *boardp = shost_priv(scp->device->host);
8475
8476 ASC_DBG(1, "scp 0x%p\n", scp);
8477
8478 if (ASC_NARROW_BOARD(boardp)) {
8479 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
8480 struct asc_scsi_q asc_scsi_q;
8481
8482 ret = asc_build_req(boardp, scp, &asc_scsi_q);
8483 if (ret != ASC_NOERROR) {
8484 ASC_STATS(scp->device->host, build_error);
8485 return ret;
8486 }
8487
8488 ret = AscExeScsiQueue(asc_dvc, &asc_scsi_q);
8489 kfree(asc_scsi_q.sg_head);
8490 err_code = asc_dvc->err_code;
8491 } else {
8492 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
8493 adv_req_t *adv_reqp;
8494
8495 switch (adv_build_req(boardp, scp, &adv_reqp)) {
8496 case ASC_NOERROR:
8497 ASC_DBG(3, "adv_build_req ASC_NOERROR\n");
8498 break;
8499 case ASC_BUSY:
8500 ASC_DBG(1, "adv_build_req ASC_BUSY\n");
8501 /*
8502 * The asc_stats fields 'adv_build_noreq' and
8503 * 'adv_build_nosg' count wide board busy conditions.
8504 * They are updated in adv_build_req and
8505 * adv_get_sglist, respectively.
8506 */
8507 return ASC_BUSY;
8508 case ASC_ERROR:
8509 default:
8510 ASC_DBG(1, "adv_build_req ASC_ERROR\n");
8511 ASC_STATS(scp->device->host, build_error);
8512 return ASC_ERROR;
8513 }
8514
8515 ret = AdvExeScsiQueue(adv_dvc, adv_reqp);
8516 err_code = adv_dvc->err_code;
8517 }
8518
8519 switch (ret) {
8520 case ASC_NOERROR:
8521 ASC_STATS(scp->device->host, exe_noerror);
8522 /*
8523 * Increment monotonically increasing per device
8524 * successful request counter. Wrapping doesn't matter.
8525 */
8526 boardp->reqcnt[scp->device->id]++;
8527 ASC_DBG(1, "ExeScsiQueue() ASC_NOERROR\n");
8528 break;
8529 case ASC_BUSY:
8530 ASC_DBG(1, "ExeScsiQueue() ASC_BUSY\n");
8531 ASC_STATS(scp->device->host, exe_busy);
8532 break;
8533 case ASC_ERROR:
8534 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() ASC_ERROR, "
8535 "err_code 0x%x\n", err_code);
8536 ASC_STATS(scp->device->host, exe_error);
8537 scp->result = HOST_BYTE(DID_ERROR);
8538 break;
8539 default:
8540 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() unknown, "
8541 "err_code 0x%x\n", err_code);
8542 ASC_STATS(scp->device->host, exe_unknown);
8543 scp->result = HOST_BYTE(DID_ERROR);
8544 break;
8545 }
8546
8547 ASC_DBG(1, "end\n");
8548 return ret;
8549 }
8550
8551 /*
8552 * advansys_queuecommand() - interrupt-driven I/O entrypoint.
8553 *
8554 * This function always returns 0. Command return status is saved
8555 * in the 'scp' result field.
8556 */
8557 static int
8558 advansys_queuecommand_lck(struct scsi_cmnd *scp, void (*done)(struct scsi_cmnd *))
8559 {
8560 struct Scsi_Host *shost = scp->device->host;
8561 int asc_res, result = 0;
8562
8563 ASC_STATS(shost, queuecommand);
8564 scp->scsi_done = done;
8565
8566 asc_res = asc_execute_scsi_cmnd(scp);
8567
8568 switch (asc_res) {
8569 case ASC_NOERROR:
8570 break;
8571 case ASC_BUSY:
8572 result = SCSI_MLQUEUE_HOST_BUSY;
8573 break;
8574 case ASC_ERROR:
8575 default:
8576 asc_scsi_done(scp);
8577 break;
8578 }
8579
8580 return result;
8581 }
8582
8583 static DEF_SCSI_QCMD(advansys_queuecommand)
8584
8585 static ushort AscGetEisaChipCfg(PortAddr iop_base)
8586 {
8587 PortAddr eisa_cfg_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
8588 (PortAddr) (ASC_EISA_CFG_IOP_MASK);
8589 return inpw(eisa_cfg_iop);
8590 }
8591
8592 /*
8593 * Return the BIOS address of the adapter at the specified
8594 * I/O port and with the specified bus type.
8595 */
8596 static unsigned short AscGetChipBiosAddress(PortAddr iop_base,
8597 unsigned short bus_type)
8598 {
8599 unsigned short cfg_lsw;
8600 unsigned short bios_addr;
8601
8602 /*
8603 * The PCI BIOS is re-located by the motherboard BIOS. Because
8604 * of this the driver can not determine where a PCI BIOS is
8605 * loaded and executes.
8606 */
8607 if (bus_type & ASC_IS_PCI)
8608 return 0;
8609
8610 if ((bus_type & ASC_IS_EISA) != 0) {
8611 cfg_lsw = AscGetEisaChipCfg(iop_base);
8612 cfg_lsw &= 0x000F;
8613 bios_addr = ASC_BIOS_MIN_ADDR + cfg_lsw * ASC_BIOS_BANK_SIZE;
8614 return bios_addr;
8615 }
8616
8617 cfg_lsw = AscGetChipCfgLsw(iop_base);
8618
8619 /*
8620 * ISA PnP uses the top bit as the 32K BIOS flag
8621 */
8622 if (bus_type == ASC_IS_ISAPNP)
8623 cfg_lsw &= 0x7FFF;
8624 bios_addr = ASC_BIOS_MIN_ADDR + (cfg_lsw >> 12) * ASC_BIOS_BANK_SIZE;
8625 return bios_addr;
8626 }
8627
8628 static uchar AscSetChipScsiID(PortAddr iop_base, uchar new_host_id)
8629 {
8630 ushort cfg_lsw;
8631
8632 if (AscGetChipScsiID(iop_base) == new_host_id) {
8633 return (new_host_id);
8634 }
8635 cfg_lsw = AscGetChipCfgLsw(iop_base);
8636 cfg_lsw &= 0xF8FF;
8637 cfg_lsw |= (ushort)((new_host_id & ASC_MAX_TID) << 8);
8638 AscSetChipCfgLsw(iop_base, cfg_lsw);
8639 return (AscGetChipScsiID(iop_base));
8640 }
8641
8642 static unsigned char AscGetChipScsiCtrl(PortAddr iop_base)
8643 {
8644 unsigned char sc;
8645
8646 AscSetBank(iop_base, 1);
8647 sc = inp(iop_base + IOP_REG_SC);
8648 AscSetBank(iop_base, 0);
8649 return sc;
8650 }
8651
8652 static unsigned char AscGetChipVersion(PortAddr iop_base,
8653 unsigned short bus_type)
8654 {
8655 if (bus_type & ASC_IS_EISA) {
8656 PortAddr eisa_iop;
8657 unsigned char revision;
8658 eisa_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
8659 (PortAddr) ASC_EISA_REV_IOP_MASK;
8660 revision = inp(eisa_iop);
8661 return ASC_CHIP_MIN_VER_EISA - 1 + revision;
8662 }
8663 return AscGetChipVerNo(iop_base);
8664 }
8665
8666 #ifdef CONFIG_ISA
8667 static void AscEnableIsaDma(uchar dma_channel)
8668 {
8669 if (dma_channel < 4) {
8670 outp(0x000B, (ushort)(0xC0 | dma_channel));
8671 outp(0x000A, dma_channel);
8672 } else if (dma_channel < 8) {
8673 outp(0x00D6, (ushort)(0xC0 | (dma_channel - 4)));
8674 outp(0x00D4, (ushort)(dma_channel - 4));
8675 }
8676 }
8677 #endif /* CONFIG_ISA */
8678
8679 static int AscStopQueueExe(PortAddr iop_base)
8680 {
8681 int count = 0;
8682
8683 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) == 0) {
8684 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
8685 ASC_STOP_REQ_RISC_STOP);
8686 do {
8687 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) &
8688 ASC_STOP_ACK_RISC_STOP) {
8689 return (1);
8690 }
8691 mdelay(100);
8692 } while (count++ < 20);
8693 }
8694 return (0);
8695 }
8696
8697 static unsigned int AscGetMaxDmaCount(ushort bus_type)
8698 {
8699 if (bus_type & ASC_IS_ISA)
8700 return ASC_MAX_ISA_DMA_COUNT;
8701 else if (bus_type & (ASC_IS_EISA | ASC_IS_VL))
8702 return ASC_MAX_VL_DMA_COUNT;
8703 return ASC_MAX_PCI_DMA_COUNT;
8704 }
8705
8706 #ifdef CONFIG_ISA
8707 static ushort AscGetIsaDmaChannel(PortAddr iop_base)
8708 {
8709 ushort channel;
8710
8711 channel = AscGetChipCfgLsw(iop_base) & 0x0003;
8712 if (channel == 0x03)
8713 return (0);
8714 else if (channel == 0x00)
8715 return (7);
8716 return (channel + 4);
8717 }
8718
8719 static ushort AscSetIsaDmaChannel(PortAddr iop_base, ushort dma_channel)
8720 {
8721 ushort cfg_lsw;
8722 uchar value;
8723
8724 if ((dma_channel >= 5) && (dma_channel <= 7)) {
8725 if (dma_channel == 7)
8726 value = 0x00;
8727 else
8728 value = dma_channel - 4;
8729 cfg_lsw = AscGetChipCfgLsw(iop_base) & 0xFFFC;
8730 cfg_lsw |= value;
8731 AscSetChipCfgLsw(iop_base, cfg_lsw);
8732 return (AscGetIsaDmaChannel(iop_base));
8733 }
8734 return 0;
8735 }
8736
8737 static uchar AscGetIsaDmaSpeed(PortAddr iop_base)
8738 {
8739 uchar speed_value;
8740
8741 AscSetBank(iop_base, 1);
8742 speed_value = AscReadChipDmaSpeed(iop_base);
8743 speed_value &= 0x07;
8744 AscSetBank(iop_base, 0);
8745 return speed_value;
8746 }
8747
8748 static uchar AscSetIsaDmaSpeed(PortAddr iop_base, uchar speed_value)
8749 {
8750 speed_value &= 0x07;
8751 AscSetBank(iop_base, 1);
8752 AscWriteChipDmaSpeed(iop_base, speed_value);
8753 AscSetBank(iop_base, 0);
8754 return AscGetIsaDmaSpeed(iop_base);
8755 }
8756 #endif /* CONFIG_ISA */
8757
8758 static void AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc)
8759 {
8760 int i;
8761 PortAddr iop_base;
8762 uchar chip_version;
8763
8764 iop_base = asc_dvc->iop_base;
8765 asc_dvc->err_code = 0;
8766 if ((asc_dvc->bus_type &
8767 (ASC_IS_ISA | ASC_IS_PCI | ASC_IS_EISA | ASC_IS_VL)) == 0) {
8768 asc_dvc->err_code |= ASC_IERR_NO_BUS_TYPE;
8769 }
8770 AscSetChipControl(iop_base, CC_HALT);
8771 AscSetChipStatus(iop_base, 0);
8772 asc_dvc->bug_fix_cntl = 0;
8773 asc_dvc->pci_fix_asyn_xfer = 0;
8774 asc_dvc->pci_fix_asyn_xfer_always = 0;
8775 /* asc_dvc->init_state initialized in AscInitGetConfig(). */
8776 asc_dvc->sdtr_done = 0;
8777 asc_dvc->cur_total_qng = 0;
8778 asc_dvc->is_in_int = false;
8779 asc_dvc->in_critical_cnt = 0;
8780 asc_dvc->last_q_shortage = 0;
8781 asc_dvc->use_tagged_qng = 0;
8782 asc_dvc->no_scam = 0;
8783 asc_dvc->unit_not_ready = 0;
8784 asc_dvc->queue_full_or_busy = 0;
8785 asc_dvc->redo_scam = 0;
8786 asc_dvc->res2 = 0;
8787 asc_dvc->min_sdtr_index = 0;
8788 asc_dvc->cfg->can_tagged_qng = 0;
8789 asc_dvc->cfg->cmd_qng_enabled = 0;
8790 asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL;
8791 asc_dvc->init_sdtr = 0;
8792 asc_dvc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG;
8793 asc_dvc->scsi_reset_wait = 3;
8794 asc_dvc->start_motor = ASC_SCSI_WIDTH_BIT_SET;
8795 asc_dvc->max_dma_count = AscGetMaxDmaCount(asc_dvc->bus_type);
8796 asc_dvc->cfg->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET;
8797 asc_dvc->cfg->disc_enable = ASC_SCSI_WIDTH_BIT_SET;
8798 asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID;
8799 chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type);
8800 asc_dvc->cfg->chip_version = chip_version;
8801 asc_dvc->sdtr_period_tbl = asc_syn_xfer_period;
8802 asc_dvc->max_sdtr_index = 7;
8803 if ((asc_dvc->bus_type & ASC_IS_PCI) &&
8804 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) {
8805 asc_dvc->bus_type = ASC_IS_PCI_ULTRA;
8806 asc_dvc->sdtr_period_tbl = asc_syn_ultra_xfer_period;
8807 asc_dvc->max_sdtr_index = 15;
8808 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) {
8809 AscSetExtraControl(iop_base,
8810 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
8811 } else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) {
8812 AscSetExtraControl(iop_base,
8813 (SEC_ACTIVE_NEGATE |
8814 SEC_ENABLE_FILTER));
8815 }
8816 }
8817 if (asc_dvc->bus_type == ASC_IS_PCI) {
8818 AscSetExtraControl(iop_base,
8819 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
8820 }
8821
8822 asc_dvc->cfg->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED;
8823 #ifdef CONFIG_ISA
8824 if ((asc_dvc->bus_type & ASC_IS_ISA) != 0) {
8825 if (chip_version >= ASC_CHIP_MIN_VER_ISA_PNP) {
8826 AscSetChipIFC(iop_base, IFC_INIT_DEFAULT);
8827 asc_dvc->bus_type = ASC_IS_ISAPNP;
8828 }
8829 asc_dvc->cfg->isa_dma_channel =
8830 (uchar)AscGetIsaDmaChannel(iop_base);
8831 }
8832 #endif /* CONFIG_ISA */
8833 for (i = 0; i <= ASC_MAX_TID; i++) {
8834 asc_dvc->cur_dvc_qng[i] = 0;
8835 asc_dvc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG;
8836 asc_dvc->scsiq_busy_head[i] = (ASC_SCSI_Q *)0L;
8837 asc_dvc->scsiq_busy_tail[i] = (ASC_SCSI_Q *)0L;
8838 asc_dvc->cfg->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG;
8839 }
8840 }
8841
8842 static int AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg)
8843 {
8844 int retry;
8845
8846 for (retry = 0; retry < ASC_EEP_MAX_RETRY; retry++) {
8847 unsigned char read_back;
8848 AscSetChipEEPCmd(iop_base, cmd_reg);
8849 mdelay(1);
8850 read_back = AscGetChipEEPCmd(iop_base);
8851 if (read_back == cmd_reg)
8852 return 1;
8853 }
8854 return 0;
8855 }
8856
8857 static void AscWaitEEPRead(void)
8858 {
8859 mdelay(1);
8860 }
8861
8862 static ushort AscReadEEPWord(PortAddr iop_base, uchar addr)
8863 {
8864 ushort read_wval;
8865 uchar cmd_reg;
8866
8867 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
8868 AscWaitEEPRead();
8869 cmd_reg = addr | ASC_EEP_CMD_READ;
8870 AscWriteEEPCmdReg(iop_base, cmd_reg);
8871 AscWaitEEPRead();
8872 read_wval = AscGetChipEEPData(iop_base);
8873 AscWaitEEPRead();
8874 return read_wval;
8875 }
8876
8877 static ushort AscGetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
8878 ushort bus_type)
8879 {
8880 ushort wval;
8881 ushort sum;
8882 ushort *wbuf;
8883 int cfg_beg;
8884 int cfg_end;
8885 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
8886 int s_addr;
8887
8888 wbuf = (ushort *)cfg_buf;
8889 sum = 0;
8890 /* Read two config words; Byte-swapping done by AscReadEEPWord(). */
8891 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
8892 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
8893 sum += *wbuf;
8894 }
8895 if (bus_type & ASC_IS_VL) {
8896 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
8897 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
8898 } else {
8899 cfg_beg = ASC_EEP_DVC_CFG_BEG;
8900 cfg_end = ASC_EEP_MAX_DVC_ADDR;
8901 }
8902 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
8903 wval = AscReadEEPWord(iop_base, (uchar)s_addr);
8904 if (s_addr <= uchar_end_in_config) {
8905 /*
8906 * Swap all char fields - must unswap bytes already swapped
8907 * by AscReadEEPWord().
8908 */
8909 *wbuf = le16_to_cpu(wval);
8910 } else {
8911 /* Don't swap word field at the end - cntl field. */
8912 *wbuf = wval;
8913 }
8914 sum += wval; /* Checksum treats all EEPROM data as words. */
8915 }
8916 /*
8917 * Read the checksum word which will be compared against 'sum'
8918 * by the caller. Word field already swapped.
8919 */
8920 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
8921 return sum;
8922 }
8923
8924 static int AscTestExternalLram(ASC_DVC_VAR *asc_dvc)
8925 {
8926 PortAddr iop_base;
8927 ushort q_addr;
8928 ushort saved_word;
8929 int sta;
8930
8931 iop_base = asc_dvc->iop_base;
8932 sta = 0;
8933 q_addr = ASC_QNO_TO_QADDR(241);
8934 saved_word = AscReadLramWord(iop_base, q_addr);
8935 AscSetChipLramAddr(iop_base, q_addr);
8936 AscSetChipLramData(iop_base, 0x55AA);
8937 mdelay(10);
8938 AscSetChipLramAddr(iop_base, q_addr);
8939 if (AscGetChipLramData(iop_base) == 0x55AA) {
8940 sta = 1;
8941 AscWriteLramWord(iop_base, q_addr, saved_word);
8942 }
8943 return (sta);
8944 }
8945
8946 static void AscWaitEEPWrite(void)
8947 {
8948 mdelay(20);
8949 }
8950
8951 static int AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg)
8952 {
8953 ushort read_back;
8954 int retry;
8955
8956 retry = 0;
8957 while (true) {
8958 AscSetChipEEPData(iop_base, data_reg);
8959 mdelay(1);
8960 read_back = AscGetChipEEPData(iop_base);
8961 if (read_back == data_reg) {
8962 return (1);
8963 }
8964 if (retry++ > ASC_EEP_MAX_RETRY) {
8965 return (0);
8966 }
8967 }
8968 }
8969
8970 static ushort AscWriteEEPWord(PortAddr iop_base, uchar addr, ushort word_val)
8971 {
8972 ushort read_wval;
8973
8974 read_wval = AscReadEEPWord(iop_base, addr);
8975 if (read_wval != word_val) {
8976 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_ABLE);
8977 AscWaitEEPRead();
8978 AscWriteEEPDataReg(iop_base, word_val);
8979 AscWaitEEPRead();
8980 AscWriteEEPCmdReg(iop_base,
8981 (uchar)((uchar)ASC_EEP_CMD_WRITE | addr));
8982 AscWaitEEPWrite();
8983 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
8984 AscWaitEEPRead();
8985 return (AscReadEEPWord(iop_base, addr));
8986 }
8987 return (read_wval);
8988 }
8989
8990 static int AscSetEEPConfigOnce(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
8991 ushort bus_type)
8992 {
8993 int n_error;
8994 ushort *wbuf;
8995 ushort word;
8996 ushort sum;
8997 int s_addr;
8998 int cfg_beg;
8999 int cfg_end;
9000 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
9001
9002 wbuf = (ushort *)cfg_buf;
9003 n_error = 0;
9004 sum = 0;
9005 /* Write two config words; AscWriteEEPWord() will swap bytes. */
9006 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9007 sum += *wbuf;
9008 if (*wbuf != AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
9009 n_error++;
9010 }
9011 }
9012 if (bus_type & ASC_IS_VL) {
9013 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9014 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9015 } else {
9016 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9017 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9018 }
9019 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9020 if (s_addr <= uchar_end_in_config) {
9021 /*
9022 * This is a char field. Swap char fields before they are
9023 * swapped again by AscWriteEEPWord().
9024 */
9025 word = cpu_to_le16(*wbuf);
9026 if (word !=
9027 AscWriteEEPWord(iop_base, (uchar)s_addr, word)) {
9028 n_error++;
9029 }
9030 } else {
9031 /* Don't swap word field at the end - cntl field. */
9032 if (*wbuf !=
9033 AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
9034 n_error++;
9035 }
9036 }
9037 sum += *wbuf; /* Checksum calculated from word values. */
9038 }
9039 /* Write checksum word. It will be swapped by AscWriteEEPWord(). */
9040 *wbuf = sum;
9041 if (sum != AscWriteEEPWord(iop_base, (uchar)s_addr, sum)) {
9042 n_error++;
9043 }
9044
9045 /* Read EEPROM back again. */
9046 wbuf = (ushort *)cfg_buf;
9047 /*
9048 * Read two config words; Byte-swapping done by AscReadEEPWord().
9049 */
9050 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9051 if (*wbuf != AscReadEEPWord(iop_base, (uchar)s_addr)) {
9052 n_error++;
9053 }
9054 }
9055 if (bus_type & ASC_IS_VL) {
9056 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9057 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9058 } else {
9059 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9060 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9061 }
9062 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9063 if (s_addr <= uchar_end_in_config) {
9064 /*
9065 * Swap all char fields. Must unswap bytes already swapped
9066 * by AscReadEEPWord().
9067 */
9068 word =
9069 le16_to_cpu(AscReadEEPWord
9070 (iop_base, (uchar)s_addr));
9071 } else {
9072 /* Don't swap word field at the end - cntl field. */
9073 word = AscReadEEPWord(iop_base, (uchar)s_addr);
9074 }
9075 if (*wbuf != word) {
9076 n_error++;
9077 }
9078 }
9079 /* Read checksum; Byte swapping not needed. */
9080 if (AscReadEEPWord(iop_base, (uchar)s_addr) != sum) {
9081 n_error++;
9082 }
9083 return n_error;
9084 }
9085
9086 static int AscSetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
9087 ushort bus_type)
9088 {
9089 int retry;
9090 int n_error;
9091
9092 retry = 0;
9093 while (true) {
9094 if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf,
9095 bus_type)) == 0) {
9096 break;
9097 }
9098 if (++retry > ASC_EEP_MAX_RETRY) {
9099 break;
9100 }
9101 }
9102 return n_error;
9103 }
9104
9105 static int AscInitFromEEP(ASC_DVC_VAR *asc_dvc)
9106 {
9107 ASCEEP_CONFIG eep_config_buf;
9108 ASCEEP_CONFIG *eep_config;
9109 PortAddr iop_base;
9110 ushort chksum;
9111 ushort warn_code;
9112 ushort cfg_msw, cfg_lsw;
9113 int i;
9114 int write_eep = 0;
9115
9116 iop_base = asc_dvc->iop_base;
9117 warn_code = 0;
9118 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE);
9119 AscStopQueueExe(iop_base);
9120 if ((AscStopChip(iop_base)) ||
9121 (AscGetChipScsiCtrl(iop_base) != 0)) {
9122 asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE;
9123 AscResetChipAndScsiBus(asc_dvc);
9124 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
9125 }
9126 if (!AscIsChipHalted(iop_base)) {
9127 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
9128 return (warn_code);
9129 }
9130 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
9131 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
9132 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
9133 return (warn_code);
9134 }
9135 eep_config = (ASCEEP_CONFIG *)&eep_config_buf;
9136 cfg_msw = AscGetChipCfgMsw(iop_base);
9137 cfg_lsw = AscGetChipCfgLsw(iop_base);
9138 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
9139 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9140 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
9141 AscSetChipCfgMsw(iop_base, cfg_msw);
9142 }
9143 chksum = AscGetEEPConfig(iop_base, eep_config, asc_dvc->bus_type);
9144 ASC_DBG(1, "chksum 0x%x\n", chksum);
9145 if (chksum == 0) {
9146 chksum = 0xaa55;
9147 }
9148 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
9149 warn_code |= ASC_WARN_AUTO_CONFIG;
9150 if (asc_dvc->cfg->chip_version == 3) {
9151 if (eep_config->cfg_lsw != cfg_lsw) {
9152 warn_code |= ASC_WARN_EEPROM_RECOVER;
9153 eep_config->cfg_lsw =
9154 AscGetChipCfgLsw(iop_base);
9155 }
9156 if (eep_config->cfg_msw != cfg_msw) {
9157 warn_code |= ASC_WARN_EEPROM_RECOVER;
9158 eep_config->cfg_msw =
9159 AscGetChipCfgMsw(iop_base);
9160 }
9161 }
9162 }
9163 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9164 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON;
9165 ASC_DBG(1, "eep_config->chksum 0x%x\n", eep_config->chksum);
9166 if (chksum != eep_config->chksum) {
9167 if (AscGetChipVersion(iop_base, asc_dvc->bus_type) ==
9168 ASC_CHIP_VER_PCI_ULTRA_3050) {
9169 ASC_DBG(1, "chksum error ignored; EEPROM-less board\n");
9170 eep_config->init_sdtr = 0xFF;
9171 eep_config->disc_enable = 0xFF;
9172 eep_config->start_motor = 0xFF;
9173 eep_config->use_cmd_qng = 0;
9174 eep_config->max_total_qng = 0xF0;
9175 eep_config->max_tag_qng = 0x20;
9176 eep_config->cntl = 0xBFFF;
9177 ASC_EEP_SET_CHIP_ID(eep_config, 7);
9178 eep_config->no_scam = 0;
9179 eep_config->adapter_info[0] = 0;
9180 eep_config->adapter_info[1] = 0;
9181 eep_config->adapter_info[2] = 0;
9182 eep_config->adapter_info[3] = 0;
9183 eep_config->adapter_info[4] = 0;
9184 /* Indicate EEPROM-less board. */
9185 eep_config->adapter_info[5] = 0xBB;
9186 } else {
9187 ASC_PRINT
9188 ("AscInitFromEEP: EEPROM checksum error; Will try to re-write EEPROM.\n");
9189 write_eep = 1;
9190 warn_code |= ASC_WARN_EEPROM_CHKSUM;
9191 }
9192 }
9193 asc_dvc->cfg->sdtr_enable = eep_config->init_sdtr;
9194 asc_dvc->cfg->disc_enable = eep_config->disc_enable;
9195 asc_dvc->cfg->cmd_qng_enabled = eep_config->use_cmd_qng;
9196 asc_dvc->cfg->isa_dma_speed = ASC_EEP_GET_DMA_SPD(eep_config);
9197 asc_dvc->start_motor = eep_config->start_motor;
9198 asc_dvc->dvc_cntl = eep_config->cntl;
9199 asc_dvc->no_scam = eep_config->no_scam;
9200 asc_dvc->cfg->adapter_info[0] = eep_config->adapter_info[0];
9201 asc_dvc->cfg->adapter_info[1] = eep_config->adapter_info[1];
9202 asc_dvc->cfg->adapter_info[2] = eep_config->adapter_info[2];
9203 asc_dvc->cfg->adapter_info[3] = eep_config->adapter_info[3];
9204 asc_dvc->cfg->adapter_info[4] = eep_config->adapter_info[4];
9205 asc_dvc->cfg->adapter_info[5] = eep_config->adapter_info[5];
9206 if (!AscTestExternalLram(asc_dvc)) {
9207 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) ==
9208 ASC_IS_PCI_ULTRA)) {
9209 eep_config->max_total_qng =
9210 ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
9211 eep_config->max_tag_qng =
9212 ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG;
9213 } else {
9214 eep_config->cfg_msw |= 0x0800;
9215 cfg_msw |= 0x0800;
9216 AscSetChipCfgMsw(iop_base, cfg_msw);
9217 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG;
9218 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG;
9219 }
9220 } else {
9221 }
9222 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) {
9223 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG;
9224 }
9225 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) {
9226 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG;
9227 }
9228 if (eep_config->max_tag_qng > eep_config->max_total_qng) {
9229 eep_config->max_tag_qng = eep_config->max_total_qng;
9230 }
9231 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) {
9232 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC;
9233 }
9234 asc_dvc->max_total_qng = eep_config->max_total_qng;
9235 if ((eep_config->use_cmd_qng & eep_config->disc_enable) !=
9236 eep_config->use_cmd_qng) {
9237 eep_config->disc_enable = eep_config->use_cmd_qng;
9238 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
9239 }
9240 ASC_EEP_SET_CHIP_ID(eep_config,
9241 ASC_EEP_GET_CHIP_ID(eep_config) & ASC_MAX_TID);
9242 asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config);
9243 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) &&
9244 !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) {
9245 asc_dvc->min_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX;
9246 }
9247
9248 for (i = 0; i <= ASC_MAX_TID; i++) {
9249 asc_dvc->dos_int13_table[i] = eep_config->dos_int13_table[i];
9250 asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng;
9251 asc_dvc->cfg->sdtr_period_offset[i] =
9252 (uchar)(ASC_DEF_SDTR_OFFSET |
9253 (asc_dvc->min_sdtr_index << 4));
9254 }
9255 eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
9256 if (write_eep) {
9257 if ((i = AscSetEEPConfig(iop_base, eep_config,
9258 asc_dvc->bus_type)) != 0) {
9259 ASC_PRINT1
9260 ("AscInitFromEEP: Failed to re-write EEPROM with %d errors.\n",
9261 i);
9262 } else {
9263 ASC_PRINT
9264 ("AscInitFromEEP: Successfully re-wrote EEPROM.\n");
9265 }
9266 }
9267 return (warn_code);
9268 }
9269
9270 static int AscInitGetConfig(struct Scsi_Host *shost)
9271 {
9272 struct asc_board *board = shost_priv(shost);
9273 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
9274 unsigned short warn_code = 0;
9275
9276 asc_dvc->init_state = ASC_INIT_STATE_BEG_GET_CFG;
9277 if (asc_dvc->err_code != 0)
9278 return asc_dvc->err_code;
9279
9280 if (AscFindSignature(asc_dvc->iop_base)) {
9281 AscInitAscDvcVar(asc_dvc);
9282 warn_code = AscInitFromEEP(asc_dvc);
9283 asc_dvc->init_state |= ASC_INIT_STATE_END_GET_CFG;
9284 if (asc_dvc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT)
9285 asc_dvc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
9286 } else {
9287 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
9288 }
9289
9290 switch (warn_code) {
9291 case 0: /* No error */
9292 break;
9293 case ASC_WARN_IO_PORT_ROTATE:
9294 shost_printk(KERN_WARNING, shost, "I/O port address "
9295 "modified\n");
9296 break;
9297 case ASC_WARN_AUTO_CONFIG:
9298 shost_printk(KERN_WARNING, shost, "I/O port increment switch "
9299 "enabled\n");
9300 break;
9301 case ASC_WARN_EEPROM_CHKSUM:
9302 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
9303 break;
9304 case ASC_WARN_IRQ_MODIFIED:
9305 shost_printk(KERN_WARNING, shost, "IRQ modified\n");
9306 break;
9307 case ASC_WARN_CMD_QNG_CONFLICT:
9308 shost_printk(KERN_WARNING, shost, "tag queuing enabled w/o "
9309 "disconnects\n");
9310 break;
9311 default:
9312 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
9313 warn_code);
9314 break;
9315 }
9316
9317 if (asc_dvc->err_code != 0)
9318 shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
9319 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
9320
9321 return asc_dvc->err_code;
9322 }
9323
9324 static int AscInitSetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
9325 {
9326 struct asc_board *board = shost_priv(shost);
9327 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
9328 PortAddr iop_base = asc_dvc->iop_base;
9329 unsigned short cfg_msw;
9330 unsigned short warn_code = 0;
9331
9332 asc_dvc->init_state |= ASC_INIT_STATE_BEG_SET_CFG;
9333 if (asc_dvc->err_code != 0)
9334 return asc_dvc->err_code;
9335 if (!AscFindSignature(asc_dvc->iop_base)) {
9336 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
9337 return asc_dvc->err_code;
9338 }
9339
9340 cfg_msw = AscGetChipCfgMsw(iop_base);
9341 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
9342 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9343 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
9344 AscSetChipCfgMsw(iop_base, cfg_msw);
9345 }
9346 if ((asc_dvc->cfg->cmd_qng_enabled & asc_dvc->cfg->disc_enable) !=
9347 asc_dvc->cfg->cmd_qng_enabled) {
9348 asc_dvc->cfg->disc_enable = asc_dvc->cfg->cmd_qng_enabled;
9349 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
9350 }
9351 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
9352 warn_code |= ASC_WARN_AUTO_CONFIG;
9353 }
9354 #ifdef CONFIG_PCI
9355 if (asc_dvc->bus_type & ASC_IS_PCI) {
9356 cfg_msw &= 0xFFC0;
9357 AscSetChipCfgMsw(iop_base, cfg_msw);
9358 if ((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) {
9359 } else {
9360 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
9361 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
9362 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB;
9363 asc_dvc->bug_fix_cntl |=
9364 ASC_BUG_FIX_ASYN_USE_SYN;
9365 }
9366 }
9367 } else
9368 #endif /* CONFIG_PCI */
9369 if (asc_dvc->bus_type == ASC_IS_ISAPNP) {
9370 if (AscGetChipVersion(iop_base, asc_dvc->bus_type)
9371 == ASC_CHIP_VER_ASYN_BUG) {
9372 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
9373 }
9374 }
9375 if (AscSetChipScsiID(iop_base, asc_dvc->cfg->chip_scsi_id) !=
9376 asc_dvc->cfg->chip_scsi_id) {
9377 asc_dvc->err_code |= ASC_IERR_SET_SCSI_ID;
9378 }
9379 #ifdef CONFIG_ISA
9380 if (asc_dvc->bus_type & ASC_IS_ISA) {
9381 AscSetIsaDmaChannel(iop_base, asc_dvc->cfg->isa_dma_channel);
9382 AscSetIsaDmaSpeed(iop_base, asc_dvc->cfg->isa_dma_speed);
9383 }
9384 #endif /* CONFIG_ISA */
9385
9386 asc_dvc->init_state |= ASC_INIT_STATE_END_SET_CFG;
9387
9388 switch (warn_code) {
9389 case 0: /* No error. */
9390 break;
9391 case ASC_WARN_IO_PORT_ROTATE:
9392 shost_printk(KERN_WARNING, shost, "I/O port address "
9393 "modified\n");
9394 break;
9395 case ASC_WARN_AUTO_CONFIG:
9396 shost_printk(KERN_WARNING, shost, "I/O port increment switch "
9397 "enabled\n");
9398 break;
9399 case ASC_WARN_EEPROM_CHKSUM:
9400 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
9401 break;
9402 case ASC_WARN_IRQ_MODIFIED:
9403 shost_printk(KERN_WARNING, shost, "IRQ modified\n");
9404 break;
9405 case ASC_WARN_CMD_QNG_CONFLICT:
9406 shost_printk(KERN_WARNING, shost, "tag queuing w/o "
9407 "disconnects\n");
9408 break;
9409 default:
9410 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
9411 warn_code);
9412 break;
9413 }
9414
9415 if (asc_dvc->err_code != 0)
9416 shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
9417 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
9418
9419 return asc_dvc->err_code;
9420 }
9421
9422 /*
9423 * EEPROM Configuration.
9424 *
9425 * All drivers should use this structure to set the default EEPROM
9426 * configuration. The BIOS now uses this structure when it is built.
9427 * Additional structure information can be found in a_condor.h where
9428 * the structure is defined.
9429 *
9430 * The *_Field_IsChar structs are needed to correct for endianness.
9431 * These values are read from the board 16 bits at a time directly
9432 * into the structs. Because some fields are char, the values will be
9433 * in the wrong order. The *_Field_IsChar tells when to flip the
9434 * bytes. Data read and written to PCI memory is automatically swapped
9435 * on big-endian platforms so char fields read as words are actually being
9436 * unswapped on big-endian platforms.
9437 */
9438 static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config = {
9439 ADV_EEPROM_BIOS_ENABLE, /* cfg_lsw */
9440 0x0000, /* cfg_msw */
9441 0xFFFF, /* disc_enable */
9442 0xFFFF, /* wdtr_able */
9443 0xFFFF, /* sdtr_able */
9444 0xFFFF, /* start_motor */
9445 0xFFFF, /* tagqng_able */
9446 0xFFFF, /* bios_scan */
9447 0, /* scam_tolerant */
9448 7, /* adapter_scsi_id */
9449 0, /* bios_boot_delay */
9450 3, /* scsi_reset_delay */
9451 0, /* bios_id_lun */
9452 0, /* termination */
9453 0, /* reserved1 */
9454 0xFFE7, /* bios_ctrl */
9455 0xFFFF, /* ultra_able */
9456 0, /* reserved2 */
9457 ASC_DEF_MAX_HOST_QNG, /* max_host_qng */
9458 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
9459 0, /* dvc_cntl */
9460 0, /* bug_fix */
9461 0, /* serial_number_word1 */
9462 0, /* serial_number_word2 */
9463 0, /* serial_number_word3 */
9464 0, /* check_sum */
9465 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
9466 , /* oem_name[16] */
9467 0, /* dvc_err_code */
9468 0, /* adv_err_code */
9469 0, /* adv_err_addr */
9470 0, /* saved_dvc_err_code */
9471 0, /* saved_adv_err_code */
9472 0, /* saved_adv_err_addr */
9473 0 /* num_of_err */
9474 };
9475
9476 static ADVEEP_3550_CONFIG ADVEEP_3550_Config_Field_IsChar = {
9477 0, /* cfg_lsw */
9478 0, /* cfg_msw */
9479 0, /* -disc_enable */
9480 0, /* wdtr_able */
9481 0, /* sdtr_able */
9482 0, /* start_motor */
9483 0, /* tagqng_able */
9484 0, /* bios_scan */
9485 0, /* scam_tolerant */
9486 1, /* adapter_scsi_id */
9487 1, /* bios_boot_delay */
9488 1, /* scsi_reset_delay */
9489 1, /* bios_id_lun */
9490 1, /* termination */
9491 1, /* reserved1 */
9492 0, /* bios_ctrl */
9493 0, /* ultra_able */
9494 0, /* reserved2 */
9495 1, /* max_host_qng */
9496 1, /* max_dvc_qng */
9497 0, /* dvc_cntl */
9498 0, /* bug_fix */
9499 0, /* serial_number_word1 */
9500 0, /* serial_number_word2 */
9501 0, /* serial_number_word3 */
9502 0, /* check_sum */
9503 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
9504 , /* oem_name[16] */
9505 0, /* dvc_err_code */
9506 0, /* adv_err_code */
9507 0, /* adv_err_addr */
9508 0, /* saved_dvc_err_code */
9509 0, /* saved_adv_err_code */
9510 0, /* saved_adv_err_addr */
9511 0 /* num_of_err */
9512 };
9513
9514 static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config = {
9515 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
9516 0x0000, /* 01 cfg_msw */
9517 0xFFFF, /* 02 disc_enable */
9518 0xFFFF, /* 03 wdtr_able */
9519 0x4444, /* 04 sdtr_speed1 */
9520 0xFFFF, /* 05 start_motor */
9521 0xFFFF, /* 06 tagqng_able */
9522 0xFFFF, /* 07 bios_scan */
9523 0, /* 08 scam_tolerant */
9524 7, /* 09 adapter_scsi_id */
9525 0, /* bios_boot_delay */
9526 3, /* 10 scsi_reset_delay */
9527 0, /* bios_id_lun */
9528 0, /* 11 termination_se */
9529 0, /* termination_lvd */
9530 0xFFE7, /* 12 bios_ctrl */
9531 0x4444, /* 13 sdtr_speed2 */
9532 0x4444, /* 14 sdtr_speed3 */
9533 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
9534 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
9535 0, /* 16 dvc_cntl */
9536 0x4444, /* 17 sdtr_speed4 */
9537 0, /* 18 serial_number_word1 */
9538 0, /* 19 serial_number_word2 */
9539 0, /* 20 serial_number_word3 */
9540 0, /* 21 check_sum */
9541 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
9542 , /* 22-29 oem_name[16] */
9543 0, /* 30 dvc_err_code */
9544 0, /* 31 adv_err_code */
9545 0, /* 32 adv_err_addr */
9546 0, /* 33 saved_dvc_err_code */
9547 0, /* 34 saved_adv_err_code */
9548 0, /* 35 saved_adv_err_addr */
9549 0, /* 36 reserved */
9550 0, /* 37 reserved */
9551 0, /* 38 reserved */
9552 0, /* 39 reserved */
9553 0, /* 40 reserved */
9554 0, /* 41 reserved */
9555 0, /* 42 reserved */
9556 0, /* 43 reserved */
9557 0, /* 44 reserved */
9558 0, /* 45 reserved */
9559 0, /* 46 reserved */
9560 0, /* 47 reserved */
9561 0, /* 48 reserved */
9562 0, /* 49 reserved */
9563 0, /* 50 reserved */
9564 0, /* 51 reserved */
9565 0, /* 52 reserved */
9566 0, /* 53 reserved */
9567 0, /* 54 reserved */
9568 0, /* 55 reserved */
9569 0, /* 56 cisptr_lsw */
9570 0, /* 57 cisprt_msw */
9571 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
9572 PCI_DEVICE_ID_38C0800_REV1, /* 59 subsysid */
9573 0, /* 60 reserved */
9574 0, /* 61 reserved */
9575 0, /* 62 reserved */
9576 0 /* 63 reserved */
9577 };
9578
9579 static ADVEEP_38C0800_CONFIG ADVEEP_38C0800_Config_Field_IsChar = {
9580 0, /* 00 cfg_lsw */
9581 0, /* 01 cfg_msw */
9582 0, /* 02 disc_enable */
9583 0, /* 03 wdtr_able */
9584 0, /* 04 sdtr_speed1 */
9585 0, /* 05 start_motor */
9586 0, /* 06 tagqng_able */
9587 0, /* 07 bios_scan */
9588 0, /* 08 scam_tolerant */
9589 1, /* 09 adapter_scsi_id */
9590 1, /* bios_boot_delay */
9591 1, /* 10 scsi_reset_delay */
9592 1, /* bios_id_lun */
9593 1, /* 11 termination_se */
9594 1, /* termination_lvd */
9595 0, /* 12 bios_ctrl */
9596 0, /* 13 sdtr_speed2 */
9597 0, /* 14 sdtr_speed3 */
9598 1, /* 15 max_host_qng */
9599 1, /* max_dvc_qng */
9600 0, /* 16 dvc_cntl */
9601 0, /* 17 sdtr_speed4 */
9602 0, /* 18 serial_number_word1 */
9603 0, /* 19 serial_number_word2 */
9604 0, /* 20 serial_number_word3 */
9605 0, /* 21 check_sum */
9606 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
9607 , /* 22-29 oem_name[16] */
9608 0, /* 30 dvc_err_code */
9609 0, /* 31 adv_err_code */
9610 0, /* 32 adv_err_addr */
9611 0, /* 33 saved_dvc_err_code */
9612 0, /* 34 saved_adv_err_code */
9613 0, /* 35 saved_adv_err_addr */
9614 0, /* 36 reserved */
9615 0, /* 37 reserved */
9616 0, /* 38 reserved */
9617 0, /* 39 reserved */
9618 0, /* 40 reserved */
9619 0, /* 41 reserved */
9620 0, /* 42 reserved */
9621 0, /* 43 reserved */
9622 0, /* 44 reserved */
9623 0, /* 45 reserved */
9624 0, /* 46 reserved */
9625 0, /* 47 reserved */
9626 0, /* 48 reserved */
9627 0, /* 49 reserved */
9628 0, /* 50 reserved */
9629 0, /* 51 reserved */
9630 0, /* 52 reserved */
9631 0, /* 53 reserved */
9632 0, /* 54 reserved */
9633 0, /* 55 reserved */
9634 0, /* 56 cisptr_lsw */
9635 0, /* 57 cisprt_msw */
9636 0, /* 58 subsysvid */
9637 0, /* 59 subsysid */
9638 0, /* 60 reserved */
9639 0, /* 61 reserved */
9640 0, /* 62 reserved */
9641 0 /* 63 reserved */
9642 };
9643
9644 static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config = {
9645 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
9646 0x0000, /* 01 cfg_msw */
9647 0xFFFF, /* 02 disc_enable */
9648 0xFFFF, /* 03 wdtr_able */
9649 0x5555, /* 04 sdtr_speed1 */
9650 0xFFFF, /* 05 start_motor */
9651 0xFFFF, /* 06 tagqng_able */
9652 0xFFFF, /* 07 bios_scan */
9653 0, /* 08 scam_tolerant */
9654 7, /* 09 adapter_scsi_id */
9655 0, /* bios_boot_delay */
9656 3, /* 10 scsi_reset_delay */
9657 0, /* bios_id_lun */
9658 0, /* 11 termination_se */
9659 0, /* termination_lvd */
9660 0xFFE7, /* 12 bios_ctrl */
9661 0x5555, /* 13 sdtr_speed2 */
9662 0x5555, /* 14 sdtr_speed3 */
9663 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
9664 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
9665 0, /* 16 dvc_cntl */
9666 0x5555, /* 17 sdtr_speed4 */
9667 0, /* 18 serial_number_word1 */
9668 0, /* 19 serial_number_word2 */
9669 0, /* 20 serial_number_word3 */
9670 0, /* 21 check_sum */
9671 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
9672 , /* 22-29 oem_name[16] */
9673 0, /* 30 dvc_err_code */
9674 0, /* 31 adv_err_code */
9675 0, /* 32 adv_err_addr */
9676 0, /* 33 saved_dvc_err_code */
9677 0, /* 34 saved_adv_err_code */
9678 0, /* 35 saved_adv_err_addr */
9679 0, /* 36 reserved */
9680 0, /* 37 reserved */
9681 0, /* 38 reserved */
9682 0, /* 39 reserved */
9683 0, /* 40 reserved */
9684 0, /* 41 reserved */
9685 0, /* 42 reserved */
9686 0, /* 43 reserved */
9687 0, /* 44 reserved */
9688 0, /* 45 reserved */
9689 0, /* 46 reserved */
9690 0, /* 47 reserved */
9691 0, /* 48 reserved */
9692 0, /* 49 reserved */
9693 0, /* 50 reserved */
9694 0, /* 51 reserved */
9695 0, /* 52 reserved */
9696 0, /* 53 reserved */
9697 0, /* 54 reserved */
9698 0, /* 55 reserved */
9699 0, /* 56 cisptr_lsw */
9700 0, /* 57 cisprt_msw */
9701 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
9702 PCI_DEVICE_ID_38C1600_REV1, /* 59 subsysid */
9703 0, /* 60 reserved */
9704 0, /* 61 reserved */
9705 0, /* 62 reserved */
9706 0 /* 63 reserved */
9707 };
9708
9709 static ADVEEP_38C1600_CONFIG ADVEEP_38C1600_Config_Field_IsChar = {
9710 0, /* 00 cfg_lsw */
9711 0, /* 01 cfg_msw */
9712 0, /* 02 disc_enable */
9713 0, /* 03 wdtr_able */
9714 0, /* 04 sdtr_speed1 */
9715 0, /* 05 start_motor */
9716 0, /* 06 tagqng_able */
9717 0, /* 07 bios_scan */
9718 0, /* 08 scam_tolerant */
9719 1, /* 09 adapter_scsi_id */
9720 1, /* bios_boot_delay */
9721 1, /* 10 scsi_reset_delay */
9722 1, /* bios_id_lun */
9723 1, /* 11 termination_se */
9724 1, /* termination_lvd */
9725 0, /* 12 bios_ctrl */
9726 0, /* 13 sdtr_speed2 */
9727 0, /* 14 sdtr_speed3 */
9728 1, /* 15 max_host_qng */
9729 1, /* max_dvc_qng */
9730 0, /* 16 dvc_cntl */
9731 0, /* 17 sdtr_speed4 */
9732 0, /* 18 serial_number_word1 */
9733 0, /* 19 serial_number_word2 */
9734 0, /* 20 serial_number_word3 */
9735 0, /* 21 check_sum */
9736 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
9737 , /* 22-29 oem_name[16] */
9738 0, /* 30 dvc_err_code */
9739 0, /* 31 adv_err_code */
9740 0, /* 32 adv_err_addr */
9741 0, /* 33 saved_dvc_err_code */
9742 0, /* 34 saved_adv_err_code */
9743 0, /* 35 saved_adv_err_addr */
9744 0, /* 36 reserved */
9745 0, /* 37 reserved */
9746 0, /* 38 reserved */
9747 0, /* 39 reserved */
9748 0, /* 40 reserved */
9749 0, /* 41 reserved */
9750 0, /* 42 reserved */
9751 0, /* 43 reserved */
9752 0, /* 44 reserved */
9753 0, /* 45 reserved */
9754 0, /* 46 reserved */
9755 0, /* 47 reserved */
9756 0, /* 48 reserved */
9757 0, /* 49 reserved */
9758 0, /* 50 reserved */
9759 0, /* 51 reserved */
9760 0, /* 52 reserved */
9761 0, /* 53 reserved */
9762 0, /* 54 reserved */
9763 0, /* 55 reserved */
9764 0, /* 56 cisptr_lsw */
9765 0, /* 57 cisprt_msw */
9766 0, /* 58 subsysvid */
9767 0, /* 59 subsysid */
9768 0, /* 60 reserved */
9769 0, /* 61 reserved */
9770 0, /* 62 reserved */
9771 0 /* 63 reserved */
9772 };
9773
9774 #ifdef CONFIG_PCI
9775 /*
9776 * Wait for EEPROM command to complete
9777 */
9778 static void AdvWaitEEPCmd(AdvPortAddr iop_base)
9779 {
9780 int eep_delay_ms;
9781
9782 for (eep_delay_ms = 0; eep_delay_ms < ADV_EEP_DELAY_MS; eep_delay_ms++) {
9783 if (AdvReadWordRegister(iop_base, IOPW_EE_CMD) &
9784 ASC_EEP_CMD_DONE) {
9785 break;
9786 }
9787 mdelay(1);
9788 }
9789 if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) ==
9790 0)
9791 BUG();
9792 }
9793
9794 /*
9795 * Read the EEPROM from specified location
9796 */
9797 static ushort AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr)
9798 {
9799 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
9800 ASC_EEP_CMD_READ | eep_word_addr);
9801 AdvWaitEEPCmd(iop_base);
9802 return AdvReadWordRegister(iop_base, IOPW_EE_DATA);
9803 }
9804
9805 /*
9806 * Write the EEPROM from 'cfg_buf'.
9807 */
9808 static void AdvSet3550EEPConfig(AdvPortAddr iop_base,
9809 ADVEEP_3550_CONFIG *cfg_buf)
9810 {
9811 ushort *wbuf;
9812 ushort addr, chksum;
9813 ushort *charfields;
9814
9815 wbuf = (ushort *)cfg_buf;
9816 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
9817 chksum = 0;
9818
9819 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
9820 AdvWaitEEPCmd(iop_base);
9821
9822 /*
9823 * Write EEPROM from word 0 to word 20.
9824 */
9825 for (addr = ADV_EEP_DVC_CFG_BEGIN;
9826 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
9827 ushort word;
9828
9829 if (*charfields++) {
9830 word = cpu_to_le16(*wbuf);
9831 } else {
9832 word = *wbuf;
9833 }
9834 chksum += *wbuf; /* Checksum is calculated from word values. */
9835 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
9836 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
9837 ASC_EEP_CMD_WRITE | addr);
9838 AdvWaitEEPCmd(iop_base);
9839 mdelay(ADV_EEP_DELAY_MS);
9840 }
9841
9842 /*
9843 * Write EEPROM checksum at word 21.
9844 */
9845 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
9846 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
9847 AdvWaitEEPCmd(iop_base);
9848 wbuf++;
9849 charfields++;
9850
9851 /*
9852 * Write EEPROM OEM name at words 22 to 29.
9853 */
9854 for (addr = ADV_EEP_DVC_CTL_BEGIN;
9855 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
9856 ushort word;
9857
9858 if (*charfields++) {
9859 word = cpu_to_le16(*wbuf);
9860 } else {
9861 word = *wbuf;
9862 }
9863 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
9864 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
9865 ASC_EEP_CMD_WRITE | addr);
9866 AdvWaitEEPCmd(iop_base);
9867 }
9868 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
9869 AdvWaitEEPCmd(iop_base);
9870 }
9871
9872 /*
9873 * Write the EEPROM from 'cfg_buf'.
9874 */
9875 static void AdvSet38C0800EEPConfig(AdvPortAddr iop_base,
9876 ADVEEP_38C0800_CONFIG *cfg_buf)
9877 {
9878 ushort *wbuf;
9879 ushort *charfields;
9880 ushort addr, chksum;
9881
9882 wbuf = (ushort *)cfg_buf;
9883 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
9884 chksum = 0;
9885
9886 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
9887 AdvWaitEEPCmd(iop_base);
9888
9889 /*
9890 * Write EEPROM from word 0 to word 20.
9891 */
9892 for (addr = ADV_EEP_DVC_CFG_BEGIN;
9893 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
9894 ushort word;
9895
9896 if (*charfields++) {
9897 word = cpu_to_le16(*wbuf);
9898 } else {
9899 word = *wbuf;
9900 }
9901 chksum += *wbuf; /* Checksum is calculated from word values. */
9902 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
9903 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
9904 ASC_EEP_CMD_WRITE | addr);
9905 AdvWaitEEPCmd(iop_base);
9906 mdelay(ADV_EEP_DELAY_MS);
9907 }
9908
9909 /*
9910 * Write EEPROM checksum at word 21.
9911 */
9912 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
9913 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
9914 AdvWaitEEPCmd(iop_base);
9915 wbuf++;
9916 charfields++;
9917
9918 /*
9919 * Write EEPROM OEM name at words 22 to 29.
9920 */
9921 for (addr = ADV_EEP_DVC_CTL_BEGIN;
9922 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
9923 ushort word;
9924
9925 if (*charfields++) {
9926 word = cpu_to_le16(*wbuf);
9927 } else {
9928 word = *wbuf;
9929 }
9930 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
9931 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
9932 ASC_EEP_CMD_WRITE | addr);
9933 AdvWaitEEPCmd(iop_base);
9934 }
9935 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
9936 AdvWaitEEPCmd(iop_base);
9937 }
9938
9939 /*
9940 * Write the EEPROM from 'cfg_buf'.
9941 */
9942 static void AdvSet38C1600EEPConfig(AdvPortAddr iop_base,
9943 ADVEEP_38C1600_CONFIG *cfg_buf)
9944 {
9945 ushort *wbuf;
9946 ushort *charfields;
9947 ushort addr, chksum;
9948
9949 wbuf = (ushort *)cfg_buf;
9950 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
9951 chksum = 0;
9952
9953 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
9954 AdvWaitEEPCmd(iop_base);
9955
9956 /*
9957 * Write EEPROM from word 0 to word 20.
9958 */
9959 for (addr = ADV_EEP_DVC_CFG_BEGIN;
9960 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
9961 ushort word;
9962
9963 if (*charfields++) {
9964 word = cpu_to_le16(*wbuf);
9965 } else {
9966 word = *wbuf;
9967 }
9968 chksum += *wbuf; /* Checksum is calculated from word values. */
9969 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
9970 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
9971 ASC_EEP_CMD_WRITE | addr);
9972 AdvWaitEEPCmd(iop_base);
9973 mdelay(ADV_EEP_DELAY_MS);
9974 }
9975
9976 /*
9977 * Write EEPROM checksum at word 21.
9978 */
9979 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
9980 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
9981 AdvWaitEEPCmd(iop_base);
9982 wbuf++;
9983 charfields++;
9984
9985 /*
9986 * Write EEPROM OEM name at words 22 to 29.
9987 */
9988 for (addr = ADV_EEP_DVC_CTL_BEGIN;
9989 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
9990 ushort word;
9991
9992 if (*charfields++) {
9993 word = cpu_to_le16(*wbuf);
9994 } else {
9995 word = *wbuf;
9996 }
9997 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
9998 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
9999 ASC_EEP_CMD_WRITE | addr);
10000 AdvWaitEEPCmd(iop_base);
10001 }
10002 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
10003 AdvWaitEEPCmd(iop_base);
10004 }
10005
10006 /*
10007 * Read EEPROM configuration into the specified buffer.
10008 *
10009 * Return a checksum based on the EEPROM configuration read.
10010 */
10011 static ushort AdvGet3550EEPConfig(AdvPortAddr iop_base,
10012 ADVEEP_3550_CONFIG *cfg_buf)
10013 {
10014 ushort wval, chksum;
10015 ushort *wbuf;
10016 int eep_addr;
10017 ushort *charfields;
10018
10019 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
10020 wbuf = (ushort *)cfg_buf;
10021 chksum = 0;
10022
10023 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10024 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10025 wval = AdvReadEEPWord(iop_base, eep_addr);
10026 chksum += wval; /* Checksum is calculated from word values. */
10027 if (*charfields++) {
10028 *wbuf = le16_to_cpu(wval);
10029 } else {
10030 *wbuf = wval;
10031 }
10032 }
10033 /* Read checksum word. */
10034 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10035 wbuf++;
10036 charfields++;
10037
10038 /* Read rest of EEPROM not covered by the checksum. */
10039 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10040 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10041 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10042 if (*charfields++) {
10043 *wbuf = le16_to_cpu(*wbuf);
10044 }
10045 }
10046 return chksum;
10047 }
10048
10049 /*
10050 * Read EEPROM configuration into the specified buffer.
10051 *
10052 * Return a checksum based on the EEPROM configuration read.
10053 */
10054 static ushort AdvGet38C0800EEPConfig(AdvPortAddr iop_base,
10055 ADVEEP_38C0800_CONFIG *cfg_buf)
10056 {
10057 ushort wval, chksum;
10058 ushort *wbuf;
10059 int eep_addr;
10060 ushort *charfields;
10061
10062 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
10063 wbuf = (ushort *)cfg_buf;
10064 chksum = 0;
10065
10066 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10067 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10068 wval = AdvReadEEPWord(iop_base, eep_addr);
10069 chksum += wval; /* Checksum is calculated from word values. */
10070 if (*charfields++) {
10071 *wbuf = le16_to_cpu(wval);
10072 } else {
10073 *wbuf = wval;
10074 }
10075 }
10076 /* Read checksum word. */
10077 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10078 wbuf++;
10079 charfields++;
10080
10081 /* Read rest of EEPROM not covered by the checksum. */
10082 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10083 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10084 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10085 if (*charfields++) {
10086 *wbuf = le16_to_cpu(*wbuf);
10087 }
10088 }
10089 return chksum;
10090 }
10091
10092 /*
10093 * Read EEPROM configuration into the specified buffer.
10094 *
10095 * Return a checksum based on the EEPROM configuration read.
10096 */
10097 static ushort AdvGet38C1600EEPConfig(AdvPortAddr iop_base,
10098 ADVEEP_38C1600_CONFIG *cfg_buf)
10099 {
10100 ushort wval, chksum;
10101 ushort *wbuf;
10102 int eep_addr;
10103 ushort *charfields;
10104
10105 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
10106 wbuf = (ushort *)cfg_buf;
10107 chksum = 0;
10108
10109 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10110 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10111 wval = AdvReadEEPWord(iop_base, eep_addr);
10112 chksum += wval; /* Checksum is calculated from word values. */
10113 if (*charfields++) {
10114 *wbuf = le16_to_cpu(wval);
10115 } else {
10116 *wbuf = wval;
10117 }
10118 }
10119 /* Read checksum word. */
10120 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10121 wbuf++;
10122 charfields++;
10123
10124 /* Read rest of EEPROM not covered by the checksum. */
10125 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10126 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10127 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10128 if (*charfields++) {
10129 *wbuf = le16_to_cpu(*wbuf);
10130 }
10131 }
10132 return chksum;
10133 }
10134
10135 /*
10136 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
10137 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
10138 * all of this is done.
10139 *
10140 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
10141 *
10142 * For a non-fatal error return a warning code. If there are no warnings
10143 * then 0 is returned.
10144 *
10145 * Note: Chip is stopped on entry.
10146 */
10147 static int AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc)
10148 {
10149 AdvPortAddr iop_base;
10150 ushort warn_code;
10151 ADVEEP_3550_CONFIG eep_config;
10152
10153 iop_base = asc_dvc->iop_base;
10154
10155 warn_code = 0;
10156
10157 /*
10158 * Read the board's EEPROM configuration.
10159 *
10160 * Set default values if a bad checksum is found.
10161 */
10162 if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum) {
10163 warn_code |= ASC_WARN_EEPROM_CHKSUM;
10164
10165 /*
10166 * Set EEPROM default values.
10167 */
10168 memcpy(&eep_config, &Default_3550_EEPROM_Config,
10169 sizeof(ADVEEP_3550_CONFIG));
10170
10171 /*
10172 * Assume the 6 byte board serial number that was read from
10173 * EEPROM is correct even if the EEPROM checksum failed.
10174 */
10175 eep_config.serial_number_word3 =
10176 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
10177
10178 eep_config.serial_number_word2 =
10179 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
10180
10181 eep_config.serial_number_word1 =
10182 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
10183
10184 AdvSet3550EEPConfig(iop_base, &eep_config);
10185 }
10186 /*
10187 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
10188 * EEPROM configuration that was read.
10189 *
10190 * This is the mapping of EEPROM fields to Adv Library fields.
10191 */
10192 asc_dvc->wdtr_able = eep_config.wdtr_able;
10193 asc_dvc->sdtr_able = eep_config.sdtr_able;
10194 asc_dvc->ultra_able = eep_config.ultra_able;
10195 asc_dvc->tagqng_able = eep_config.tagqng_able;
10196 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10197 asc_dvc->max_host_qng = eep_config.max_host_qng;
10198 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10199 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
10200 asc_dvc->start_motor = eep_config.start_motor;
10201 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10202 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10203 asc_dvc->no_scam = eep_config.scam_tolerant;
10204 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
10205 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
10206 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
10207
10208 /*
10209 * Set the host maximum queuing (max. 253, min. 16) and the per device
10210 * maximum queuing (max. 63, min. 4).
10211 */
10212 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10213 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10214 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10215 /* If the value is zero, assume it is uninitialized. */
10216 if (eep_config.max_host_qng == 0) {
10217 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10218 } else {
10219 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
10220 }
10221 }
10222
10223 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10224 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10225 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10226 /* If the value is zero, assume it is uninitialized. */
10227 if (eep_config.max_dvc_qng == 0) {
10228 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10229 } else {
10230 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10231 }
10232 }
10233
10234 /*
10235 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10236 * set 'max_dvc_qng' to 'max_host_qng'.
10237 */
10238 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10239 eep_config.max_dvc_qng = eep_config.max_host_qng;
10240 }
10241
10242 /*
10243 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
10244 * values based on possibly adjusted EEPROM values.
10245 */
10246 asc_dvc->max_host_qng = eep_config.max_host_qng;
10247 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10248
10249 /*
10250 * If the EEPROM 'termination' field is set to automatic (0), then set
10251 * the ADV_DVC_CFG 'termination' field to automatic also.
10252 *
10253 * If the termination is specified with a non-zero 'termination'
10254 * value check that a legal value is set and set the ADV_DVC_CFG
10255 * 'termination' field appropriately.
10256 */
10257 if (eep_config.termination == 0) {
10258 asc_dvc->cfg->termination = 0; /* auto termination */
10259 } else {
10260 /* Enable manual control with low off / high off. */
10261 if (eep_config.termination == 1) {
10262 asc_dvc->cfg->termination = TERM_CTL_SEL;
10263
10264 /* Enable manual control with low off / high on. */
10265 } else if (eep_config.termination == 2) {
10266 asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H;
10267
10268 /* Enable manual control with low on / high on. */
10269 } else if (eep_config.termination == 3) {
10270 asc_dvc->cfg->termination =
10271 TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L;
10272 } else {
10273 /*
10274 * The EEPROM 'termination' field contains a bad value. Use
10275 * automatic termination instead.
10276 */
10277 asc_dvc->cfg->termination = 0;
10278 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10279 }
10280 }
10281
10282 return warn_code;
10283 }
10284
10285 /*
10286 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
10287 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
10288 * all of this is done.
10289 *
10290 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
10291 *
10292 * For a non-fatal error return a warning code. If there are no warnings
10293 * then 0 is returned.
10294 *
10295 * Note: Chip is stopped on entry.
10296 */
10297 static int AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc)
10298 {
10299 AdvPortAddr iop_base;
10300 ushort warn_code;
10301 ADVEEP_38C0800_CONFIG eep_config;
10302 uchar tid, termination;
10303 ushort sdtr_speed = 0;
10304
10305 iop_base = asc_dvc->iop_base;
10306
10307 warn_code = 0;
10308
10309 /*
10310 * Read the board's EEPROM configuration.
10311 *
10312 * Set default values if a bad checksum is found.
10313 */
10314 if (AdvGet38C0800EEPConfig(iop_base, &eep_config) !=
10315 eep_config.check_sum) {
10316 warn_code |= ASC_WARN_EEPROM_CHKSUM;
10317
10318 /*
10319 * Set EEPROM default values.
10320 */
10321 memcpy(&eep_config, &Default_38C0800_EEPROM_Config,
10322 sizeof(ADVEEP_38C0800_CONFIG));
10323
10324 /*
10325 * Assume the 6 byte board serial number that was read from
10326 * EEPROM is correct even if the EEPROM checksum failed.
10327 */
10328 eep_config.serial_number_word3 =
10329 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
10330
10331 eep_config.serial_number_word2 =
10332 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
10333
10334 eep_config.serial_number_word1 =
10335 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
10336
10337 AdvSet38C0800EEPConfig(iop_base, &eep_config);
10338 }
10339 /*
10340 * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the
10341 * EEPROM configuration that was read.
10342 *
10343 * This is the mapping of EEPROM fields to Adv Library fields.
10344 */
10345 asc_dvc->wdtr_able = eep_config.wdtr_able;
10346 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
10347 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
10348 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
10349 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
10350 asc_dvc->tagqng_able = eep_config.tagqng_able;
10351 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10352 asc_dvc->max_host_qng = eep_config.max_host_qng;
10353 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10354 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
10355 asc_dvc->start_motor = eep_config.start_motor;
10356 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10357 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10358 asc_dvc->no_scam = eep_config.scam_tolerant;
10359 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
10360 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
10361 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
10362
10363 /*
10364 * For every Target ID if any of its 'sdtr_speed[1234]' bits
10365 * are set, then set an 'sdtr_able' bit for it.
10366 */
10367 asc_dvc->sdtr_able = 0;
10368 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
10369 if (tid == 0) {
10370 sdtr_speed = asc_dvc->sdtr_speed1;
10371 } else if (tid == 4) {
10372 sdtr_speed = asc_dvc->sdtr_speed2;
10373 } else if (tid == 8) {
10374 sdtr_speed = asc_dvc->sdtr_speed3;
10375 } else if (tid == 12) {
10376 sdtr_speed = asc_dvc->sdtr_speed4;
10377 }
10378 if (sdtr_speed & ADV_MAX_TID) {
10379 asc_dvc->sdtr_able |= (1 << tid);
10380 }
10381 sdtr_speed >>= 4;
10382 }
10383
10384 /*
10385 * Set the host maximum queuing (max. 253, min. 16) and the per device
10386 * maximum queuing (max. 63, min. 4).
10387 */
10388 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10389 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10390 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10391 /* If the value is zero, assume it is uninitialized. */
10392 if (eep_config.max_host_qng == 0) {
10393 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10394 } else {
10395 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
10396 }
10397 }
10398
10399 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10400 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10401 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10402 /* If the value is zero, assume it is uninitialized. */
10403 if (eep_config.max_dvc_qng == 0) {
10404 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10405 } else {
10406 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10407 }
10408 }
10409
10410 /*
10411 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10412 * set 'max_dvc_qng' to 'max_host_qng'.
10413 */
10414 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10415 eep_config.max_dvc_qng = eep_config.max_host_qng;
10416 }
10417
10418 /*
10419 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
10420 * values based on possibly adjusted EEPROM values.
10421 */
10422 asc_dvc->max_host_qng = eep_config.max_host_qng;
10423 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10424
10425 /*
10426 * If the EEPROM 'termination' field is set to automatic (0), then set
10427 * the ADV_DVC_CFG 'termination' field to automatic also.
10428 *
10429 * If the termination is specified with a non-zero 'termination'
10430 * value check that a legal value is set and set the ADV_DVC_CFG
10431 * 'termination' field appropriately.
10432 */
10433 if (eep_config.termination_se == 0) {
10434 termination = 0; /* auto termination for SE */
10435 } else {
10436 /* Enable manual control with low off / high off. */
10437 if (eep_config.termination_se == 1) {
10438 termination = 0;
10439
10440 /* Enable manual control with low off / high on. */
10441 } else if (eep_config.termination_se == 2) {
10442 termination = TERM_SE_HI;
10443
10444 /* Enable manual control with low on / high on. */
10445 } else if (eep_config.termination_se == 3) {
10446 termination = TERM_SE;
10447 } else {
10448 /*
10449 * The EEPROM 'termination_se' field contains a bad value.
10450 * Use automatic termination instead.
10451 */
10452 termination = 0;
10453 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10454 }
10455 }
10456
10457 if (eep_config.termination_lvd == 0) {
10458 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
10459 } else {
10460 /* Enable manual control with low off / high off. */
10461 if (eep_config.termination_lvd == 1) {
10462 asc_dvc->cfg->termination = termination;
10463
10464 /* Enable manual control with low off / high on. */
10465 } else if (eep_config.termination_lvd == 2) {
10466 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
10467
10468 /* Enable manual control with low on / high on. */
10469 } else if (eep_config.termination_lvd == 3) {
10470 asc_dvc->cfg->termination = termination | TERM_LVD;
10471 } else {
10472 /*
10473 * The EEPROM 'termination_lvd' field contains a bad value.
10474 * Use automatic termination instead.
10475 */
10476 asc_dvc->cfg->termination = termination;
10477 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10478 }
10479 }
10480
10481 return warn_code;
10482 }
10483
10484 /*
10485 * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and
10486 * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while
10487 * all of this is done.
10488 *
10489 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
10490 *
10491 * For a non-fatal error return a warning code. If there are no warnings
10492 * then 0 is returned.
10493 *
10494 * Note: Chip is stopped on entry.
10495 */
10496 static int AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc)
10497 {
10498 AdvPortAddr iop_base;
10499 ushort warn_code;
10500 ADVEEP_38C1600_CONFIG eep_config;
10501 uchar tid, termination;
10502 ushort sdtr_speed = 0;
10503
10504 iop_base = asc_dvc->iop_base;
10505
10506 warn_code = 0;
10507
10508 /*
10509 * Read the board's EEPROM configuration.
10510 *
10511 * Set default values if a bad checksum is found.
10512 */
10513 if (AdvGet38C1600EEPConfig(iop_base, &eep_config) !=
10514 eep_config.check_sum) {
10515 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
10516 warn_code |= ASC_WARN_EEPROM_CHKSUM;
10517
10518 /*
10519 * Set EEPROM default values.
10520 */
10521 memcpy(&eep_config, &Default_38C1600_EEPROM_Config,
10522 sizeof(ADVEEP_38C1600_CONFIG));
10523
10524 if (PCI_FUNC(pdev->devfn) != 0) {
10525 u8 ints;
10526 /*
10527 * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60
10528 * and old Mac system booting problem. The Expansion
10529 * ROM must be disabled in Function 1 for these systems
10530 */
10531 eep_config.cfg_lsw &= ~ADV_EEPROM_BIOS_ENABLE;
10532 /*
10533 * Clear the INTAB (bit 11) if the GPIO 0 input
10534 * indicates the Function 1 interrupt line is wired
10535 * to INTB.
10536 *
10537 * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input:
10538 * 1 - Function 1 interrupt line wired to INT A.
10539 * 0 - Function 1 interrupt line wired to INT B.
10540 *
10541 * Note: Function 0 is always wired to INTA.
10542 * Put all 5 GPIO bits in input mode and then read
10543 * their input values.
10544 */
10545 AdvWriteByteRegister(iop_base, IOPB_GPIO_CNTL, 0);
10546 ints = AdvReadByteRegister(iop_base, IOPB_GPIO_DATA);
10547 if ((ints & 0x01) == 0)
10548 eep_config.cfg_lsw &= ~ADV_EEPROM_INTAB;
10549 }
10550
10551 /*
10552 * Assume the 6 byte board serial number that was read from
10553 * EEPROM is correct even if the EEPROM checksum failed.
10554 */
10555 eep_config.serial_number_word3 =
10556 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
10557 eep_config.serial_number_word2 =
10558 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
10559 eep_config.serial_number_word1 =
10560 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
10561
10562 AdvSet38C1600EEPConfig(iop_base, &eep_config);
10563 }
10564
10565 /*
10566 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
10567 * EEPROM configuration that was read.
10568 *
10569 * This is the mapping of EEPROM fields to Adv Library fields.
10570 */
10571 asc_dvc->wdtr_able = eep_config.wdtr_able;
10572 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
10573 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
10574 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
10575 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
10576 asc_dvc->ppr_able = 0;
10577 asc_dvc->tagqng_able = eep_config.tagqng_able;
10578 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10579 asc_dvc->max_host_qng = eep_config.max_host_qng;
10580 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10581 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ASC_MAX_TID);
10582 asc_dvc->start_motor = eep_config.start_motor;
10583 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10584 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10585 asc_dvc->no_scam = eep_config.scam_tolerant;
10586
10587 /*
10588 * For every Target ID if any of its 'sdtr_speed[1234]' bits
10589 * are set, then set an 'sdtr_able' bit for it.
10590 */
10591 asc_dvc->sdtr_able = 0;
10592 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
10593 if (tid == 0) {
10594 sdtr_speed = asc_dvc->sdtr_speed1;
10595 } else if (tid == 4) {
10596 sdtr_speed = asc_dvc->sdtr_speed2;
10597 } else if (tid == 8) {
10598 sdtr_speed = asc_dvc->sdtr_speed3;
10599 } else if (tid == 12) {
10600 sdtr_speed = asc_dvc->sdtr_speed4;
10601 }
10602 if (sdtr_speed & ASC_MAX_TID) {
10603 asc_dvc->sdtr_able |= (1 << tid);
10604 }
10605 sdtr_speed >>= 4;
10606 }
10607
10608 /*
10609 * Set the host maximum queuing (max. 253, min. 16) and the per device
10610 * maximum queuing (max. 63, min. 4).
10611 */
10612 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10613 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10614 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10615 /* If the value is zero, assume it is uninitialized. */
10616 if (eep_config.max_host_qng == 0) {
10617 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10618 } else {
10619 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
10620 }
10621 }
10622
10623 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10624 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10625 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10626 /* If the value is zero, assume it is uninitialized. */
10627 if (eep_config.max_dvc_qng == 0) {
10628 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10629 } else {
10630 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10631 }
10632 }
10633
10634 /*
10635 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10636 * set 'max_dvc_qng' to 'max_host_qng'.
10637 */
10638 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10639 eep_config.max_dvc_qng = eep_config.max_host_qng;
10640 }
10641
10642 /*
10643 * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng'
10644 * values based on possibly adjusted EEPROM values.
10645 */
10646 asc_dvc->max_host_qng = eep_config.max_host_qng;
10647 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10648
10649 /*
10650 * If the EEPROM 'termination' field is set to automatic (0), then set
10651 * the ASC_DVC_CFG 'termination' field to automatic also.
10652 *
10653 * If the termination is specified with a non-zero 'termination'
10654 * value check that a legal value is set and set the ASC_DVC_CFG
10655 * 'termination' field appropriately.
10656 */
10657 if (eep_config.termination_se == 0) {
10658 termination = 0; /* auto termination for SE */
10659 } else {
10660 /* Enable manual control with low off / high off. */
10661 if (eep_config.termination_se == 1) {
10662 termination = 0;
10663
10664 /* Enable manual control with low off / high on. */
10665 } else if (eep_config.termination_se == 2) {
10666 termination = TERM_SE_HI;
10667
10668 /* Enable manual control with low on / high on. */
10669 } else if (eep_config.termination_se == 3) {
10670 termination = TERM_SE;
10671 } else {
10672 /*
10673 * The EEPROM 'termination_se' field contains a bad value.
10674 * Use automatic termination instead.
10675 */
10676 termination = 0;
10677 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10678 }
10679 }
10680
10681 if (eep_config.termination_lvd == 0) {
10682 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
10683 } else {
10684 /* Enable manual control with low off / high off. */
10685 if (eep_config.termination_lvd == 1) {
10686 asc_dvc->cfg->termination = termination;
10687
10688 /* Enable manual control with low off / high on. */
10689 } else if (eep_config.termination_lvd == 2) {
10690 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
10691
10692 /* Enable manual control with low on / high on. */
10693 } else if (eep_config.termination_lvd == 3) {
10694 asc_dvc->cfg->termination = termination | TERM_LVD;
10695 } else {
10696 /*
10697 * The EEPROM 'termination_lvd' field contains a bad value.
10698 * Use automatic termination instead.
10699 */
10700 asc_dvc->cfg->termination = termination;
10701 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10702 }
10703 }
10704
10705 return warn_code;
10706 }
10707
10708 /*
10709 * Initialize the ADV_DVC_VAR structure.
10710 *
10711 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
10712 *
10713 * For a non-fatal error return a warning code. If there are no warnings
10714 * then 0 is returned.
10715 */
10716 static int AdvInitGetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
10717 {
10718 struct asc_board *board = shost_priv(shost);
10719 ADV_DVC_VAR *asc_dvc = &board->dvc_var.adv_dvc_var;
10720 unsigned short warn_code = 0;
10721 AdvPortAddr iop_base = asc_dvc->iop_base;
10722 u16 cmd;
10723 int status;
10724
10725 asc_dvc->err_code = 0;
10726
10727 /*
10728 * Save the state of the PCI Configuration Command Register
10729 * "Parity Error Response Control" Bit. If the bit is clear (0),
10730 * in AdvInitAsc3550/38C0800Driver() tell the microcode to ignore
10731 * DMA parity errors.
10732 */
10733 asc_dvc->cfg->control_flag = 0;
10734 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
10735 if ((cmd & PCI_COMMAND_PARITY) == 0)
10736 asc_dvc->cfg->control_flag |= CONTROL_FLAG_IGNORE_PERR;
10737
10738 asc_dvc->cfg->chip_version =
10739 AdvGetChipVersion(iop_base, asc_dvc->bus_type);
10740
10741 ASC_DBG(1, "iopb_chip_id_1: 0x%x 0x%x\n",
10742 (ushort)AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1),
10743 (ushort)ADV_CHIP_ID_BYTE);
10744
10745 ASC_DBG(1, "iopw_chip_id_0: 0x%x 0x%x\n",
10746 (ushort)AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0),
10747 (ushort)ADV_CHIP_ID_WORD);
10748
10749 /*
10750 * Reset the chip to start and allow register writes.
10751 */
10752 if (AdvFindSignature(iop_base) == 0) {
10753 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
10754 return ADV_ERROR;
10755 } else {
10756 /*
10757 * The caller must set 'chip_type' to a valid setting.
10758 */
10759 if (asc_dvc->chip_type != ADV_CHIP_ASC3550 &&
10760 asc_dvc->chip_type != ADV_CHIP_ASC38C0800 &&
10761 asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
10762 asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE;
10763 return ADV_ERROR;
10764 }
10765
10766 /*
10767 * Reset Chip.
10768 */
10769 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
10770 ADV_CTRL_REG_CMD_RESET);
10771 mdelay(100);
10772 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
10773 ADV_CTRL_REG_CMD_WR_IO_REG);
10774
10775 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
10776 status = AdvInitFrom38C1600EEP(asc_dvc);
10777 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
10778 status = AdvInitFrom38C0800EEP(asc_dvc);
10779 } else {
10780 status = AdvInitFrom3550EEP(asc_dvc);
10781 }
10782 warn_code |= status;
10783 }
10784
10785 if (warn_code != 0)
10786 shost_printk(KERN_WARNING, shost, "warning: 0x%x\n", warn_code);
10787
10788 if (asc_dvc->err_code)
10789 shost_printk(KERN_ERR, shost, "error code 0x%x\n",
10790 asc_dvc->err_code);
10791
10792 return asc_dvc->err_code;
10793 }
10794 #endif
10795
10796 static struct scsi_host_template advansys_template = {
10797 .proc_name = DRV_NAME,
10798 #ifdef CONFIG_PROC_FS
10799 .show_info = advansys_show_info,
10800 #endif
10801 .name = DRV_NAME,
10802 .info = advansys_info,
10803 .queuecommand = advansys_queuecommand,
10804 .eh_host_reset_handler = advansys_reset,
10805 .bios_param = advansys_biosparam,
10806 .slave_configure = advansys_slave_configure,
10807 /*
10808 * Because the driver may control an ISA adapter 'unchecked_isa_dma'
10809 * must be set. The flag will be cleared in advansys_board_found
10810 * for non-ISA adapters.
10811 */
10812 .unchecked_isa_dma = true,
10813 /*
10814 * All adapters controlled by this driver are capable of large
10815 * scatter-gather lists. According to the mid-level SCSI documentation
10816 * this obviates any performance gain provided by setting
10817 * 'use_clustering'. But empirically while CPU utilization is increased
10818 * by enabling clustering, I/O throughput increases as well.
10819 */
10820 .use_clustering = ENABLE_CLUSTERING,
10821 .use_blk_tags = 1,
10822 };
10823
10824 static int advansys_wide_init_chip(struct Scsi_Host *shost)
10825 {
10826 struct asc_board *board = shost_priv(shost);
10827 struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
10828 size_t sgblk_pool_size;
10829 int warn_code, err_code;
10830
10831 /*
10832 * Allocate buffer carrier structures. The total size
10833 * is about 8 KB, so allocate all at once.
10834 */
10835 adv_dvc->carrier = dma_alloc_coherent(board->dev,
10836 ADV_CARRIER_BUFSIZE, &adv_dvc->carrier_addr, GFP_KERNEL);
10837 ASC_DBG(1, "carrier 0x%p\n", adv_dvc->carrier);
10838
10839 if (!adv_dvc->carrier)
10840 goto kmalloc_failed;
10841
10842 /*
10843 * Allocate up to 'max_host_qng' request structures for the Wide
10844 * board. The total size is about 16 KB, so allocate all at once.
10845 * If the allocation fails decrement and try again.
10846 */
10847 board->adv_reqp_size = adv_dvc->max_host_qng * sizeof(adv_req_t);
10848 if (board->adv_reqp_size & 0x1f) {
10849 ASC_DBG(1, "unaligned reqp %lu bytes\n", sizeof(adv_req_t));
10850 board->adv_reqp_size = ADV_32BALIGN(board->adv_reqp_size);
10851 }
10852 board->adv_reqp = dma_alloc_coherent(board->dev, board->adv_reqp_size,
10853 &board->adv_reqp_addr, GFP_KERNEL);
10854
10855 if (!board->adv_reqp)
10856 goto kmalloc_failed;
10857
10858 ASC_DBG(1, "reqp 0x%p, req_cnt %d, bytes %lu\n", board->adv_reqp,
10859 adv_dvc->max_host_qng, board->adv_reqp_size);
10860
10861 /*
10862 * Allocate up to ADV_TOT_SG_BLOCK request structures for
10863 * the Wide board. Each structure is about 136 bytes.
10864 */
10865 sgblk_pool_size = sizeof(adv_sgblk_t) * ADV_TOT_SG_BLOCK;
10866 board->adv_sgblk_pool = dma_pool_create("adv_sgblk", board->dev,
10867 sgblk_pool_size, 32, 0);
10868
10869 ASC_DBG(1, "sg_cnt %d * %lu = %lu bytes\n", ADV_TOT_SG_BLOCK,
10870 sizeof(adv_sgblk_t), sgblk_pool_size);
10871
10872 if (!board->adv_sgblk_pool)
10873 goto kmalloc_failed;
10874
10875 if (adv_dvc->chip_type == ADV_CHIP_ASC3550) {
10876 ASC_DBG(2, "AdvInitAsc3550Driver()\n");
10877 warn_code = AdvInitAsc3550Driver(adv_dvc);
10878 } else if (adv_dvc->chip_type == ADV_CHIP_ASC38C0800) {
10879 ASC_DBG(2, "AdvInitAsc38C0800Driver()\n");
10880 warn_code = AdvInitAsc38C0800Driver(adv_dvc);
10881 } else {
10882 ASC_DBG(2, "AdvInitAsc38C1600Driver()\n");
10883 warn_code = AdvInitAsc38C1600Driver(adv_dvc);
10884 }
10885 err_code = adv_dvc->err_code;
10886
10887 if (warn_code || err_code) {
10888 shost_printk(KERN_WARNING, shost, "error: warn 0x%x, error "
10889 "0x%x\n", warn_code, err_code);
10890 }
10891
10892 goto exit;
10893
10894 kmalloc_failed:
10895 shost_printk(KERN_ERR, shost, "error: kmalloc() failed\n");
10896 err_code = ADV_ERROR;
10897 exit:
10898 return err_code;
10899 }
10900
10901 static void advansys_wide_free_mem(struct asc_board *board)
10902 {
10903 struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
10904
10905 if (adv_dvc->carrier) {
10906 dma_free_coherent(board->dev, ADV_CARRIER_BUFSIZE,
10907 adv_dvc->carrier, adv_dvc->carrier_addr);
10908 adv_dvc->carrier = NULL;
10909 }
10910 if (board->adv_reqp) {
10911 dma_free_coherent(board->dev, board->adv_reqp_size,
10912 board->adv_reqp, board->adv_reqp_addr);
10913 board->adv_reqp = NULL;
10914 }
10915 if (board->adv_sgblk_pool) {
10916 dma_pool_destroy(board->adv_sgblk_pool);
10917 board->adv_sgblk_pool = NULL;
10918 }
10919 }
10920
10921 static int advansys_board_found(struct Scsi_Host *shost, unsigned int iop,
10922 int bus_type)
10923 {
10924 struct pci_dev *pdev;
10925 struct asc_board *boardp = shost_priv(shost);
10926 ASC_DVC_VAR *asc_dvc_varp = NULL;
10927 ADV_DVC_VAR *adv_dvc_varp = NULL;
10928 int share_irq, warn_code, ret;
10929
10930 pdev = (bus_type == ASC_IS_PCI) ? to_pci_dev(boardp->dev) : NULL;
10931
10932 if (ASC_NARROW_BOARD(boardp)) {
10933 ASC_DBG(1, "narrow board\n");
10934 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
10935 asc_dvc_varp->bus_type = bus_type;
10936 asc_dvc_varp->drv_ptr = boardp;
10937 asc_dvc_varp->cfg = &boardp->dvc_cfg.asc_dvc_cfg;
10938 asc_dvc_varp->iop_base = iop;
10939 } else {
10940 #ifdef CONFIG_PCI
10941 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
10942 adv_dvc_varp->drv_ptr = boardp;
10943 adv_dvc_varp->cfg = &boardp->dvc_cfg.adv_dvc_cfg;
10944 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW) {
10945 ASC_DBG(1, "wide board ASC-3550\n");
10946 adv_dvc_varp->chip_type = ADV_CHIP_ASC3550;
10947 } else if (pdev->device == PCI_DEVICE_ID_38C0800_REV1) {
10948 ASC_DBG(1, "wide board ASC-38C0800\n");
10949 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C0800;
10950 } else {
10951 ASC_DBG(1, "wide board ASC-38C1600\n");
10952 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C1600;
10953 }
10954
10955 boardp->asc_n_io_port = pci_resource_len(pdev, 1);
10956 boardp->ioremap_addr = pci_ioremap_bar(pdev, 1);
10957 if (!boardp->ioremap_addr) {
10958 shost_printk(KERN_ERR, shost, "ioremap(%lx, %d) "
10959 "returned NULL\n",
10960 (long)pci_resource_start(pdev, 1),
10961 boardp->asc_n_io_port);
10962 ret = -ENODEV;
10963 goto err_shost;
10964 }
10965 adv_dvc_varp->iop_base = (AdvPortAddr)boardp->ioremap_addr;
10966 ASC_DBG(1, "iop_base: 0x%p\n", adv_dvc_varp->iop_base);
10967
10968 /*
10969 * Even though it isn't used to access wide boards, other
10970 * than for the debug line below, save I/O Port address so
10971 * that it can be reported.
10972 */
10973 boardp->ioport = iop;
10974
10975 ASC_DBG(1, "iopb_chip_id_1 0x%x, iopw_chip_id_0 0x%x\n",
10976 (ushort)inp(iop + 1), (ushort)inpw(iop));
10977 #endif /* CONFIG_PCI */
10978 }
10979
10980 if (ASC_NARROW_BOARD(boardp)) {
10981 /*
10982 * Set the board bus type and PCI IRQ before
10983 * calling AscInitGetConfig().
10984 */
10985 switch (asc_dvc_varp->bus_type) {
10986 #ifdef CONFIG_ISA
10987 case ASC_IS_ISA:
10988 shost->unchecked_isa_dma = true;
10989 share_irq = 0;
10990 break;
10991 case ASC_IS_VL:
10992 shost->unchecked_isa_dma = false;
10993 share_irq = 0;
10994 break;
10995 case ASC_IS_EISA:
10996 shost->unchecked_isa_dma = false;
10997 share_irq = IRQF_SHARED;
10998 break;
10999 #endif /* CONFIG_ISA */
11000 #ifdef CONFIG_PCI
11001 case ASC_IS_PCI:
11002 shost->unchecked_isa_dma = false;
11003 share_irq = IRQF_SHARED;
11004 break;
11005 #endif /* CONFIG_PCI */
11006 default:
11007 shost_printk(KERN_ERR, shost, "unknown adapter type: "
11008 "%d\n", asc_dvc_varp->bus_type);
11009 shost->unchecked_isa_dma = false;
11010 share_irq = 0;
11011 break;
11012 }
11013
11014 /*
11015 * NOTE: AscInitGetConfig() may change the board's
11016 * bus_type value. The bus_type value should no
11017 * longer be used. If the bus_type field must be
11018 * referenced only use the bit-wise AND operator "&".
11019 */
11020 ASC_DBG(2, "AscInitGetConfig()\n");
11021 ret = AscInitGetConfig(shost) ? -ENODEV : 0;
11022 } else {
11023 #ifdef CONFIG_PCI
11024 /*
11025 * For Wide boards set PCI information before calling
11026 * AdvInitGetConfig().
11027 */
11028 shost->unchecked_isa_dma = false;
11029 share_irq = IRQF_SHARED;
11030 ASC_DBG(2, "AdvInitGetConfig()\n");
11031
11032 ret = AdvInitGetConfig(pdev, shost) ? -ENODEV : 0;
11033 #endif /* CONFIG_PCI */
11034 }
11035
11036 if (ret)
11037 goto err_unmap;
11038
11039 /*
11040 * Save the EEPROM configuration so that it can be displayed
11041 * from /proc/scsi/advansys/[0...].
11042 */
11043 if (ASC_NARROW_BOARD(boardp)) {
11044
11045 ASCEEP_CONFIG *ep;
11046
11047 /*
11048 * Set the adapter's target id bit in the 'init_tidmask' field.
11049 */
11050 boardp->init_tidmask |=
11051 ADV_TID_TO_TIDMASK(asc_dvc_varp->cfg->chip_scsi_id);
11052
11053 /*
11054 * Save EEPROM settings for the board.
11055 */
11056 ep = &boardp->eep_config.asc_eep;
11057
11058 ep->init_sdtr = asc_dvc_varp->cfg->sdtr_enable;
11059 ep->disc_enable = asc_dvc_varp->cfg->disc_enable;
11060 ep->use_cmd_qng = asc_dvc_varp->cfg->cmd_qng_enabled;
11061 ASC_EEP_SET_DMA_SPD(ep, asc_dvc_varp->cfg->isa_dma_speed);
11062 ep->start_motor = asc_dvc_varp->start_motor;
11063 ep->cntl = asc_dvc_varp->dvc_cntl;
11064 ep->no_scam = asc_dvc_varp->no_scam;
11065 ep->max_total_qng = asc_dvc_varp->max_total_qng;
11066 ASC_EEP_SET_CHIP_ID(ep, asc_dvc_varp->cfg->chip_scsi_id);
11067 /* 'max_tag_qng' is set to the same value for every device. */
11068 ep->max_tag_qng = asc_dvc_varp->cfg->max_tag_qng[0];
11069 ep->adapter_info[0] = asc_dvc_varp->cfg->adapter_info[0];
11070 ep->adapter_info[1] = asc_dvc_varp->cfg->adapter_info[1];
11071 ep->adapter_info[2] = asc_dvc_varp->cfg->adapter_info[2];
11072 ep->adapter_info[3] = asc_dvc_varp->cfg->adapter_info[3];
11073 ep->adapter_info[4] = asc_dvc_varp->cfg->adapter_info[4];
11074 ep->adapter_info[5] = asc_dvc_varp->cfg->adapter_info[5];
11075
11076 /*
11077 * Modify board configuration.
11078 */
11079 ASC_DBG(2, "AscInitSetConfig()\n");
11080 ret = AscInitSetConfig(pdev, shost) ? -ENODEV : 0;
11081 if (ret)
11082 goto err_unmap;
11083 } else {
11084 ADVEEP_3550_CONFIG *ep_3550;
11085 ADVEEP_38C0800_CONFIG *ep_38C0800;
11086 ADVEEP_38C1600_CONFIG *ep_38C1600;
11087
11088 /*
11089 * Save Wide EEP Configuration Information.
11090 */
11091 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
11092 ep_3550 = &boardp->eep_config.adv_3550_eep;
11093
11094 ep_3550->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
11095 ep_3550->max_host_qng = adv_dvc_varp->max_host_qng;
11096 ep_3550->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11097 ep_3550->termination = adv_dvc_varp->cfg->termination;
11098 ep_3550->disc_enable = adv_dvc_varp->cfg->disc_enable;
11099 ep_3550->bios_ctrl = adv_dvc_varp->bios_ctrl;
11100 ep_3550->wdtr_able = adv_dvc_varp->wdtr_able;
11101 ep_3550->sdtr_able = adv_dvc_varp->sdtr_able;
11102 ep_3550->ultra_able = adv_dvc_varp->ultra_able;
11103 ep_3550->tagqng_able = adv_dvc_varp->tagqng_able;
11104 ep_3550->start_motor = adv_dvc_varp->start_motor;
11105 ep_3550->scsi_reset_delay =
11106 adv_dvc_varp->scsi_reset_wait;
11107 ep_3550->serial_number_word1 =
11108 adv_dvc_varp->cfg->serial1;
11109 ep_3550->serial_number_word2 =
11110 adv_dvc_varp->cfg->serial2;
11111 ep_3550->serial_number_word3 =
11112 adv_dvc_varp->cfg->serial3;
11113 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
11114 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
11115
11116 ep_38C0800->adapter_scsi_id =
11117 adv_dvc_varp->chip_scsi_id;
11118 ep_38C0800->max_host_qng = adv_dvc_varp->max_host_qng;
11119 ep_38C0800->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11120 ep_38C0800->termination_lvd =
11121 adv_dvc_varp->cfg->termination;
11122 ep_38C0800->disc_enable =
11123 adv_dvc_varp->cfg->disc_enable;
11124 ep_38C0800->bios_ctrl = adv_dvc_varp->bios_ctrl;
11125 ep_38C0800->wdtr_able = adv_dvc_varp->wdtr_able;
11126 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
11127 ep_38C0800->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
11128 ep_38C0800->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
11129 ep_38C0800->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
11130 ep_38C0800->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
11131 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
11132 ep_38C0800->start_motor = adv_dvc_varp->start_motor;
11133 ep_38C0800->scsi_reset_delay =
11134 adv_dvc_varp->scsi_reset_wait;
11135 ep_38C0800->serial_number_word1 =
11136 adv_dvc_varp->cfg->serial1;
11137 ep_38C0800->serial_number_word2 =
11138 adv_dvc_varp->cfg->serial2;
11139 ep_38C0800->serial_number_word3 =
11140 adv_dvc_varp->cfg->serial3;
11141 } else {
11142 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
11143
11144 ep_38C1600->adapter_scsi_id =
11145 adv_dvc_varp->chip_scsi_id;
11146 ep_38C1600->max_host_qng = adv_dvc_varp->max_host_qng;
11147 ep_38C1600->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11148 ep_38C1600->termination_lvd =
11149 adv_dvc_varp->cfg->termination;
11150 ep_38C1600->disc_enable =
11151 adv_dvc_varp->cfg->disc_enable;
11152 ep_38C1600->bios_ctrl = adv_dvc_varp->bios_ctrl;
11153 ep_38C1600->wdtr_able = adv_dvc_varp->wdtr_able;
11154 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
11155 ep_38C1600->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
11156 ep_38C1600->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
11157 ep_38C1600->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
11158 ep_38C1600->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
11159 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
11160 ep_38C1600->start_motor = adv_dvc_varp->start_motor;
11161 ep_38C1600->scsi_reset_delay =
11162 adv_dvc_varp->scsi_reset_wait;
11163 ep_38C1600->serial_number_word1 =
11164 adv_dvc_varp->cfg->serial1;
11165 ep_38C1600->serial_number_word2 =
11166 adv_dvc_varp->cfg->serial2;
11167 ep_38C1600->serial_number_word3 =
11168 adv_dvc_varp->cfg->serial3;
11169 }
11170
11171 /*
11172 * Set the adapter's target id bit in the 'init_tidmask' field.
11173 */
11174 boardp->init_tidmask |=
11175 ADV_TID_TO_TIDMASK(adv_dvc_varp->chip_scsi_id);
11176 }
11177
11178 /*
11179 * Channels are numbered beginning with 0. For AdvanSys one host
11180 * structure supports one channel. Multi-channel boards have a
11181 * separate host structure for each channel.
11182 */
11183 shost->max_channel = 0;
11184 if (ASC_NARROW_BOARD(boardp)) {
11185 shost->max_id = ASC_MAX_TID + 1;
11186 shost->max_lun = ASC_MAX_LUN + 1;
11187 shost->max_cmd_len = ASC_MAX_CDB_LEN;
11188
11189 shost->io_port = asc_dvc_varp->iop_base;
11190 boardp->asc_n_io_port = ASC_IOADR_GAP;
11191 shost->this_id = asc_dvc_varp->cfg->chip_scsi_id;
11192
11193 /* Set maximum number of queues the adapter can handle. */
11194 shost->can_queue = asc_dvc_varp->max_total_qng;
11195 } else {
11196 shost->max_id = ADV_MAX_TID + 1;
11197 shost->max_lun = ADV_MAX_LUN + 1;
11198 shost->max_cmd_len = ADV_MAX_CDB_LEN;
11199
11200 /*
11201 * Save the I/O Port address and length even though
11202 * I/O ports are not used to access Wide boards.
11203 * Instead the Wide boards are accessed with
11204 * PCI Memory Mapped I/O.
11205 */
11206 shost->io_port = iop;
11207
11208 shost->this_id = adv_dvc_varp->chip_scsi_id;
11209
11210 /* Set maximum number of queues the adapter can handle. */
11211 shost->can_queue = adv_dvc_varp->max_host_qng;
11212 }
11213 ret = scsi_init_shared_tag_map(shost, shost->can_queue);
11214 if (ret) {
11215 shost_printk(KERN_ERR, shost, "init tag map failed\n");
11216 goto err_free_dma;
11217 }
11218
11219 /*
11220 * Set the maximum number of scatter-gather elements the
11221 * adapter can handle.
11222 */
11223 if (ASC_NARROW_BOARD(boardp)) {
11224 /*
11225 * Allow two commands with 'sg_tablesize' scatter-gather
11226 * elements to be executed simultaneously. This value is
11227 * the theoretical hardware limit. It may be decreased
11228 * below.
11229 */
11230 shost->sg_tablesize =
11231 (((asc_dvc_varp->max_total_qng - 2) / 2) *
11232 ASC_SG_LIST_PER_Q) + 1;
11233 } else {
11234 shost->sg_tablesize = ADV_MAX_SG_LIST;
11235 }
11236
11237 /*
11238 * The value of 'sg_tablesize' can not exceed the SCSI
11239 * mid-level driver definition of SG_ALL. SG_ALL also
11240 * must not be exceeded, because it is used to define the
11241 * size of the scatter-gather table in 'struct asc_sg_head'.
11242 */
11243 if (shost->sg_tablesize > SG_ALL) {
11244 shost->sg_tablesize = SG_ALL;
11245 }
11246
11247 ASC_DBG(1, "sg_tablesize: %d\n", shost->sg_tablesize);
11248
11249 /* BIOS start address. */
11250 if (ASC_NARROW_BOARD(boardp)) {
11251 shost->base = AscGetChipBiosAddress(asc_dvc_varp->iop_base,
11252 asc_dvc_varp->bus_type);
11253 } else {
11254 /*
11255 * Fill-in BIOS board variables. The Wide BIOS saves
11256 * information in LRAM that is used by the driver.
11257 */
11258 AdvReadWordLram(adv_dvc_varp->iop_base,
11259 BIOS_SIGNATURE, boardp->bios_signature);
11260 AdvReadWordLram(adv_dvc_varp->iop_base,
11261 BIOS_VERSION, boardp->bios_version);
11262 AdvReadWordLram(adv_dvc_varp->iop_base,
11263 BIOS_CODESEG, boardp->bios_codeseg);
11264 AdvReadWordLram(adv_dvc_varp->iop_base,
11265 BIOS_CODELEN, boardp->bios_codelen);
11266
11267 ASC_DBG(1, "bios_signature 0x%x, bios_version 0x%x\n",
11268 boardp->bios_signature, boardp->bios_version);
11269
11270 ASC_DBG(1, "bios_codeseg 0x%x, bios_codelen 0x%x\n",
11271 boardp->bios_codeseg, boardp->bios_codelen);
11272
11273 /*
11274 * If the BIOS saved a valid signature, then fill in
11275 * the BIOS code segment base address.
11276 */
11277 if (boardp->bios_signature == 0x55AA) {
11278 /*
11279 * Convert x86 realmode code segment to a linear
11280 * address by shifting left 4.
11281 */
11282 shost->base = ((ulong)boardp->bios_codeseg << 4);
11283 } else {
11284 shost->base = 0;
11285 }
11286 }
11287
11288 /*
11289 * Register Board Resources - I/O Port, DMA, IRQ
11290 */
11291
11292 /* Register DMA Channel for Narrow boards. */
11293 shost->dma_channel = NO_ISA_DMA; /* Default to no ISA DMA. */
11294 #ifdef CONFIG_ISA
11295 if (ASC_NARROW_BOARD(boardp)) {
11296 /* Register DMA channel for ISA bus. */
11297 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
11298 shost->dma_channel = asc_dvc_varp->cfg->isa_dma_channel;
11299 ret = request_dma(shost->dma_channel, DRV_NAME);
11300 if (ret) {
11301 shost_printk(KERN_ERR, shost, "request_dma() "
11302 "%d failed %d\n",
11303 shost->dma_channel, ret);
11304 goto err_unmap;
11305 }
11306 AscEnableIsaDma(shost->dma_channel);
11307 }
11308 }
11309 #endif /* CONFIG_ISA */
11310
11311 /* Register IRQ Number. */
11312 ASC_DBG(2, "request_irq(%d, %p)\n", boardp->irq, shost);
11313
11314 ret = request_irq(boardp->irq, advansys_interrupt, share_irq,
11315 DRV_NAME, shost);
11316
11317 if (ret) {
11318 if (ret == -EBUSY) {
11319 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11320 "already in use\n", boardp->irq);
11321 } else if (ret == -EINVAL) {
11322 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11323 "not valid\n", boardp->irq);
11324 } else {
11325 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11326 "failed with %d\n", boardp->irq, ret);
11327 }
11328 goto err_free_dma;
11329 }
11330
11331 /*
11332 * Initialize board RISC chip and enable interrupts.
11333 */
11334 if (ASC_NARROW_BOARD(boardp)) {
11335 ASC_DBG(2, "AscInitAsc1000Driver()\n");
11336
11337 asc_dvc_varp->overrun_buf = kzalloc(ASC_OVERRUN_BSIZE, GFP_KERNEL);
11338 if (!asc_dvc_varp->overrun_buf) {
11339 ret = -ENOMEM;
11340 goto err_free_irq;
11341 }
11342 warn_code = AscInitAsc1000Driver(asc_dvc_varp);
11343
11344 if (warn_code || asc_dvc_varp->err_code) {
11345 shost_printk(KERN_ERR, shost, "error: init_state 0x%x, "
11346 "warn 0x%x, error 0x%x\n",
11347 asc_dvc_varp->init_state, warn_code,
11348 asc_dvc_varp->err_code);
11349 if (!asc_dvc_varp->overrun_dma) {
11350 ret = -ENODEV;
11351 goto err_free_mem;
11352 }
11353 }
11354 } else {
11355 if (advansys_wide_init_chip(shost)) {
11356 ret = -ENODEV;
11357 goto err_free_mem;
11358 }
11359 }
11360
11361 ASC_DBG_PRT_SCSI_HOST(2, shost);
11362
11363 ret = scsi_add_host(shost, boardp->dev);
11364 if (ret)
11365 goto err_free_mem;
11366
11367 scsi_scan_host(shost);
11368 return 0;
11369
11370 err_free_mem:
11371 if (ASC_NARROW_BOARD(boardp)) {
11372 if (asc_dvc_varp->overrun_dma)
11373 dma_unmap_single(boardp->dev, asc_dvc_varp->overrun_dma,
11374 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
11375 kfree(asc_dvc_varp->overrun_buf);
11376 } else
11377 advansys_wide_free_mem(boardp);
11378 err_free_irq:
11379 free_irq(boardp->irq, shost);
11380 err_free_dma:
11381 #ifdef CONFIG_ISA
11382 if (shost->dma_channel != NO_ISA_DMA)
11383 free_dma(shost->dma_channel);
11384 #endif
11385 err_unmap:
11386 if (boardp->ioremap_addr)
11387 iounmap(boardp->ioremap_addr);
11388 err_shost:
11389 return ret;
11390 }
11391
11392 /*
11393 * advansys_release()
11394 *
11395 * Release resources allocated for a single AdvanSys adapter.
11396 */
11397 static int advansys_release(struct Scsi_Host *shost)
11398 {
11399 struct asc_board *board = shost_priv(shost);
11400 ASC_DBG(1, "begin\n");
11401 scsi_remove_host(shost);
11402 free_irq(board->irq, shost);
11403 #ifdef CONFIG_ISA
11404 if (shost->dma_channel != NO_ISA_DMA) {
11405 ASC_DBG(1, "free_dma()\n");
11406 free_dma(shost->dma_channel);
11407 }
11408 #endif
11409 if (ASC_NARROW_BOARD(board)) {
11410 dma_unmap_single(board->dev,
11411 board->dvc_var.asc_dvc_var.overrun_dma,
11412 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
11413 kfree(board->dvc_var.asc_dvc_var.overrun_buf);
11414 } else {
11415 iounmap(board->ioremap_addr);
11416 advansys_wide_free_mem(board);
11417 }
11418 scsi_host_put(shost);
11419 ASC_DBG(1, "end\n");
11420 return 0;
11421 }
11422
11423 #define ASC_IOADR_TABLE_MAX_IX 11
11424
11425 static PortAddr _asc_def_iop_base[ASC_IOADR_TABLE_MAX_IX] = {
11426 0x100, 0x0110, 0x120, 0x0130, 0x140, 0x0150, 0x0190,
11427 0x0210, 0x0230, 0x0250, 0x0330
11428 };
11429
11430 /*
11431 * The ISA IRQ number is found in bits 2 and 3 of the CfgLsw. It decodes as:
11432 * 00: 10
11433 * 01: 11
11434 * 10: 12
11435 * 11: 15
11436 */
11437 static unsigned int advansys_isa_irq_no(PortAddr iop_base)
11438 {
11439 unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
11440 unsigned int chip_irq = ((cfg_lsw >> 2) & 0x03) + 10;
11441 if (chip_irq == 13)
11442 chip_irq = 15;
11443 return chip_irq;
11444 }
11445
11446 static int advansys_isa_probe(struct device *dev, unsigned int id)
11447 {
11448 int err = -ENODEV;
11449 PortAddr iop_base = _asc_def_iop_base[id];
11450 struct Scsi_Host *shost;
11451 struct asc_board *board;
11452
11453 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
11454 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
11455 return -ENODEV;
11456 }
11457 ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
11458 if (!AscFindSignature(iop_base))
11459 goto release_region;
11460 if (!(AscGetChipVersion(iop_base, ASC_IS_ISA) & ASC_CHIP_VER_ISA_BIT))
11461 goto release_region;
11462
11463 err = -ENOMEM;
11464 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
11465 if (!shost)
11466 goto release_region;
11467
11468 board = shost_priv(shost);
11469 board->irq = advansys_isa_irq_no(iop_base);
11470 board->dev = dev;
11471 board->shost = shost;
11472
11473 err = advansys_board_found(shost, iop_base, ASC_IS_ISA);
11474 if (err)
11475 goto free_host;
11476
11477 dev_set_drvdata(dev, shost);
11478 return 0;
11479
11480 free_host:
11481 scsi_host_put(shost);
11482 release_region:
11483 release_region(iop_base, ASC_IOADR_GAP);
11484 return err;
11485 }
11486
11487 static int advansys_isa_remove(struct device *dev, unsigned int id)
11488 {
11489 int ioport = _asc_def_iop_base[id];
11490 advansys_release(dev_get_drvdata(dev));
11491 release_region(ioport, ASC_IOADR_GAP);
11492 return 0;
11493 }
11494
11495 static struct isa_driver advansys_isa_driver = {
11496 .probe = advansys_isa_probe,
11497 .remove = advansys_isa_remove,
11498 .driver = {
11499 .owner = THIS_MODULE,
11500 .name = DRV_NAME,
11501 },
11502 };
11503
11504 /*
11505 * The VLB IRQ number is found in bits 2 to 4 of the CfgLsw. It decodes as:
11506 * 000: invalid
11507 * 001: 10
11508 * 010: 11
11509 * 011: 12
11510 * 100: invalid
11511 * 101: 14
11512 * 110: 15
11513 * 111: invalid
11514 */
11515 static unsigned int advansys_vlb_irq_no(PortAddr iop_base)
11516 {
11517 unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
11518 unsigned int chip_irq = ((cfg_lsw >> 2) & 0x07) + 9;
11519 if ((chip_irq < 10) || (chip_irq == 13) || (chip_irq > 15))
11520 return 0;
11521 return chip_irq;
11522 }
11523
11524 static int advansys_vlb_probe(struct device *dev, unsigned int id)
11525 {
11526 int err = -ENODEV;
11527 PortAddr iop_base = _asc_def_iop_base[id];
11528 struct Scsi_Host *shost;
11529 struct asc_board *board;
11530
11531 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
11532 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
11533 return -ENODEV;
11534 }
11535 ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
11536 if (!AscFindSignature(iop_base))
11537 goto release_region;
11538 /*
11539 * I don't think this condition can actually happen, but the old
11540 * driver did it, and the chances of finding a VLB setup in 2007
11541 * to do testing with is slight to none.
11542 */
11543 if (AscGetChipVersion(iop_base, ASC_IS_VL) > ASC_CHIP_MAX_VER_VL)
11544 goto release_region;
11545
11546 err = -ENOMEM;
11547 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
11548 if (!shost)
11549 goto release_region;
11550
11551 board = shost_priv(shost);
11552 board->irq = advansys_vlb_irq_no(iop_base);
11553 board->dev = dev;
11554 board->shost = shost;
11555
11556 err = advansys_board_found(shost, iop_base, ASC_IS_VL);
11557 if (err)
11558 goto free_host;
11559
11560 dev_set_drvdata(dev, shost);
11561 return 0;
11562
11563 free_host:
11564 scsi_host_put(shost);
11565 release_region:
11566 release_region(iop_base, ASC_IOADR_GAP);
11567 return -ENODEV;
11568 }
11569
11570 static struct isa_driver advansys_vlb_driver = {
11571 .probe = advansys_vlb_probe,
11572 .remove = advansys_isa_remove,
11573 .driver = {
11574 .owner = THIS_MODULE,
11575 .name = "advansys_vlb",
11576 },
11577 };
11578
11579 static struct eisa_device_id advansys_eisa_table[] = {
11580 { "ABP7401" },
11581 { "ABP7501" },
11582 { "" }
11583 };
11584
11585 MODULE_DEVICE_TABLE(eisa, advansys_eisa_table);
11586
11587 /*
11588 * EISA is a little more tricky than PCI; each EISA device may have two
11589 * channels, and this driver is written to make each channel its own Scsi_Host
11590 */
11591 struct eisa_scsi_data {
11592 struct Scsi_Host *host[2];
11593 };
11594
11595 /*
11596 * The EISA IRQ number is found in bits 8 to 10 of the CfgLsw. It decodes as:
11597 * 000: 10
11598 * 001: 11
11599 * 010: 12
11600 * 011: invalid
11601 * 100: 14
11602 * 101: 15
11603 * 110: invalid
11604 * 111: invalid
11605 */
11606 static unsigned int advansys_eisa_irq_no(struct eisa_device *edev)
11607 {
11608 unsigned short cfg_lsw = inw(edev->base_addr + 0xc86);
11609 unsigned int chip_irq = ((cfg_lsw >> 8) & 0x07) + 10;
11610 if ((chip_irq == 13) || (chip_irq > 15))
11611 return 0;
11612 return chip_irq;
11613 }
11614
11615 static int advansys_eisa_probe(struct device *dev)
11616 {
11617 int i, ioport, irq = 0;
11618 int err;
11619 struct eisa_device *edev = to_eisa_device(dev);
11620 struct eisa_scsi_data *data;
11621
11622 err = -ENOMEM;
11623 data = kzalloc(sizeof(*data), GFP_KERNEL);
11624 if (!data)
11625 goto fail;
11626 ioport = edev->base_addr + 0xc30;
11627
11628 err = -ENODEV;
11629 for (i = 0; i < 2; i++, ioport += 0x20) {
11630 struct asc_board *board;
11631 struct Scsi_Host *shost;
11632 if (!request_region(ioport, ASC_IOADR_GAP, DRV_NAME)) {
11633 printk(KERN_WARNING "Region %x-%x busy\n", ioport,
11634 ioport + ASC_IOADR_GAP - 1);
11635 continue;
11636 }
11637 if (!AscFindSignature(ioport)) {
11638 release_region(ioport, ASC_IOADR_GAP);
11639 continue;
11640 }
11641
11642 /*
11643 * I don't know why we need to do this for EISA chips, but
11644 * not for any others. It looks to be equivalent to
11645 * AscGetChipCfgMsw, but I may have overlooked something,
11646 * so I'm not converting it until I get an EISA board to
11647 * test with.
11648 */
11649 inw(ioport + 4);
11650
11651 if (!irq)
11652 irq = advansys_eisa_irq_no(edev);
11653
11654 err = -ENOMEM;
11655 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
11656 if (!shost)
11657 goto release_region;
11658
11659 board = shost_priv(shost);
11660 board->irq = irq;
11661 board->dev = dev;
11662 board->shost = shost;
11663
11664 err = advansys_board_found(shost, ioport, ASC_IS_EISA);
11665 if (!err) {
11666 data->host[i] = shost;
11667 continue;
11668 }
11669
11670 scsi_host_put(shost);
11671 release_region:
11672 release_region(ioport, ASC_IOADR_GAP);
11673 break;
11674 }
11675
11676 if (err)
11677 goto free_data;
11678 dev_set_drvdata(dev, data);
11679 return 0;
11680
11681 free_data:
11682 kfree(data->host[0]);
11683 kfree(data->host[1]);
11684 kfree(data);
11685 fail:
11686 return err;
11687 }
11688
11689 static int advansys_eisa_remove(struct device *dev)
11690 {
11691 int i;
11692 struct eisa_scsi_data *data = dev_get_drvdata(dev);
11693
11694 for (i = 0; i < 2; i++) {
11695 int ioport;
11696 struct Scsi_Host *shost = data->host[i];
11697 if (!shost)
11698 continue;
11699 ioport = shost->io_port;
11700 advansys_release(shost);
11701 release_region(ioport, ASC_IOADR_GAP);
11702 }
11703
11704 kfree(data);
11705 return 0;
11706 }
11707
11708 static struct eisa_driver advansys_eisa_driver = {
11709 .id_table = advansys_eisa_table,
11710 .driver = {
11711 .name = DRV_NAME,
11712 .probe = advansys_eisa_probe,
11713 .remove = advansys_eisa_remove,
11714 }
11715 };
11716
11717 /* PCI Devices supported by this driver */
11718 static struct pci_device_id advansys_pci_tbl[] = {
11719 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_1200A,
11720 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
11721 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940,
11722 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
11723 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940U,
11724 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
11725 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940UW,
11726 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
11727 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C0800_REV1,
11728 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
11729 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C1600_REV1,
11730 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
11731 {}
11732 };
11733
11734 MODULE_DEVICE_TABLE(pci, advansys_pci_tbl);
11735
11736 static void advansys_set_latency(struct pci_dev *pdev)
11737 {
11738 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
11739 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
11740 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0);
11741 } else {
11742 u8 latency;
11743 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency);
11744 if (latency < 0x20)
11745 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20);
11746 }
11747 }
11748
11749 static int advansys_pci_probe(struct pci_dev *pdev,
11750 const struct pci_device_id *ent)
11751 {
11752 int err, ioport;
11753 struct Scsi_Host *shost;
11754 struct asc_board *board;
11755
11756 err = pci_enable_device(pdev);
11757 if (err)
11758 goto fail;
11759 err = pci_request_regions(pdev, DRV_NAME);
11760 if (err)
11761 goto disable_device;
11762 pci_set_master(pdev);
11763 advansys_set_latency(pdev);
11764
11765 err = -ENODEV;
11766 if (pci_resource_len(pdev, 0) == 0)
11767 goto release_region;
11768
11769 ioport = pci_resource_start(pdev, 0);
11770
11771 err = -ENOMEM;
11772 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
11773 if (!shost)
11774 goto release_region;
11775
11776 board = shost_priv(shost);
11777 board->irq = pdev->irq;
11778 board->dev = &pdev->dev;
11779 board->shost = shost;
11780
11781 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW ||
11782 pdev->device == PCI_DEVICE_ID_38C0800_REV1 ||
11783 pdev->device == PCI_DEVICE_ID_38C1600_REV1) {
11784 board->flags |= ASC_IS_WIDE_BOARD;
11785 }
11786
11787 err = advansys_board_found(shost, ioport, ASC_IS_PCI);
11788 if (err)
11789 goto free_host;
11790
11791 pci_set_drvdata(pdev, shost);
11792 return 0;
11793
11794 free_host:
11795 scsi_host_put(shost);
11796 release_region:
11797 pci_release_regions(pdev);
11798 disable_device:
11799 pci_disable_device(pdev);
11800 fail:
11801 return err;
11802 }
11803
11804 static void advansys_pci_remove(struct pci_dev *pdev)
11805 {
11806 advansys_release(pci_get_drvdata(pdev));
11807 pci_release_regions(pdev);
11808 pci_disable_device(pdev);
11809 }
11810
11811 static struct pci_driver advansys_pci_driver = {
11812 .name = DRV_NAME,
11813 .id_table = advansys_pci_tbl,
11814 .probe = advansys_pci_probe,
11815 .remove = advansys_pci_remove,
11816 };
11817
11818 static int __init advansys_init(void)
11819 {
11820 int error;
11821
11822 error = isa_register_driver(&advansys_isa_driver,
11823 ASC_IOADR_TABLE_MAX_IX);
11824 if (error)
11825 goto fail;
11826
11827 error = isa_register_driver(&advansys_vlb_driver,
11828 ASC_IOADR_TABLE_MAX_IX);
11829 if (error)
11830 goto unregister_isa;
11831
11832 error = eisa_driver_register(&advansys_eisa_driver);
11833 if (error)
11834 goto unregister_vlb;
11835
11836 error = pci_register_driver(&advansys_pci_driver);
11837 if (error)
11838 goto unregister_eisa;
11839
11840 return 0;
11841
11842 unregister_eisa:
11843 eisa_driver_unregister(&advansys_eisa_driver);
11844 unregister_vlb:
11845 isa_unregister_driver(&advansys_vlb_driver);
11846 unregister_isa:
11847 isa_unregister_driver(&advansys_isa_driver);
11848 fail:
11849 return error;
11850 }
11851
11852 static void __exit advansys_exit(void)
11853 {
11854 pci_unregister_driver(&advansys_pci_driver);
11855 eisa_driver_unregister(&advansys_eisa_driver);
11856 isa_unregister_driver(&advansys_vlb_driver);
11857 isa_unregister_driver(&advansys_isa_driver);
11858 }
11859
11860 module_init(advansys_init);
11861 module_exit(advansys_exit);
11862
11863 MODULE_LICENSE("GPL");
11864 MODULE_FIRMWARE("advansys/mcode.bin");
11865 MODULE_FIRMWARE("advansys/3550.bin");
11866 MODULE_FIRMWARE("advansys/38C0800.bin");
11867 MODULE_FIRMWARE("advansys/38C1600.bin");
(deprecated) Btrfs devel tree