2 * Derived from "arch/i386/kernel/process.c"
3 * Copyright (C) 1995 Linus Torvalds
5 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
6 * Paul Mackerras (paulus@cs.anu.edu.au)
9 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
17 #include <linux/errno.h>
18 #include <linux/sched.h>
19 #include <linux/kernel.h>
21 #include <linux/smp.h>
22 #include <linux/stddef.h>
23 #include <linux/unistd.h>
24 #include <linux/ptrace.h>
25 #include <linux/slab.h>
26 #include <linux/user.h>
27 #include <linux/elf.h>
28 #include <linux/prctl.h>
29 #include <linux/init_task.h>
30 #include <linux/export.h>
31 #include <linux/kallsyms.h>
32 #include <linux/mqueue.h>
33 #include <linux/hardirq.h>
34 #include <linux/utsname.h>
35 #include <linux/ftrace.h>
36 #include <linux/kernel_stat.h>
37 #include <linux/personality.h>
38 #include <linux/random.h>
39 #include <linux/hw_breakpoint.h>
40 #include <linux/uaccess.h>
41 #include <linux/elf-randomize.h>
43 #include <asm/pgtable.h>
45 #include <asm/processor.h>
48 #include <asm/machdep.h>
50 #include <asm/runlatch.h>
51 #include <asm/syscalls.h>
52 #include <asm/switch_to.h>
54 #include <asm/debug.h>
56 #include <asm/firmware.h>
58 #include <asm/code-patching.h>
60 #include <asm/livepatch.h>
62 #include <linux/kprobes.h>
63 #include <linux/kdebug.h>
65 /* Transactional Memory debug */
67 #define TM_DEBUG(x...) printk(KERN_INFO x)
69 #define TM_DEBUG(x...) do { } while(0)
72 extern unsigned long _get_SP(void);
74 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
75 static void check_if_tm_restore_required(struct task_struct
*tsk
)
78 * If we are saving the current thread's registers, and the
79 * thread is in a transactional state, set the TIF_RESTORE_TM
80 * bit so that we know to restore the registers before
81 * returning to userspace.
83 if (tsk
== current
&& tsk
->thread
.regs
&&
84 MSR_TM_ACTIVE(tsk
->thread
.regs
->msr
) &&
85 !test_thread_flag(TIF_RESTORE_TM
)) {
86 tsk
->thread
.ckpt_regs
.msr
= tsk
->thread
.regs
->msr
;
87 set_thread_flag(TIF_RESTORE_TM
);
91 static inline void check_if_tm_restore_required(struct task_struct
*tsk
) { }
92 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
94 bool strict_msr_control
;
95 EXPORT_SYMBOL(strict_msr_control
);
97 static int __init
enable_strict_msr_control(char *str
)
99 strict_msr_control
= true;
100 pr_info("Enabling strict facility control\n");
104 early_param("ppc_strict_facility_enable", enable_strict_msr_control
);
106 void msr_check_and_set(unsigned long bits
)
108 unsigned long oldmsr
= mfmsr();
109 unsigned long newmsr
;
111 newmsr
= oldmsr
| bits
;
114 if (cpu_has_feature(CPU_FTR_VSX
) && (bits
& MSR_FP
))
118 if (oldmsr
!= newmsr
)
122 void __msr_check_and_clear(unsigned long bits
)
124 unsigned long oldmsr
= mfmsr();
125 unsigned long newmsr
;
127 newmsr
= oldmsr
& ~bits
;
130 if (cpu_has_feature(CPU_FTR_VSX
) && (bits
& MSR_FP
))
134 if (oldmsr
!= newmsr
)
137 EXPORT_SYMBOL(__msr_check_and_clear
);
139 #ifdef CONFIG_PPC_FPU
140 void __giveup_fpu(struct task_struct
*tsk
)
145 msr
= tsk
->thread
.regs
->msr
;
148 if (cpu_has_feature(CPU_FTR_VSX
))
151 tsk
->thread
.regs
->msr
= msr
;
154 void giveup_fpu(struct task_struct
*tsk
)
156 check_if_tm_restore_required(tsk
);
158 msr_check_and_set(MSR_FP
);
160 msr_check_and_clear(MSR_FP
);
162 EXPORT_SYMBOL(giveup_fpu
);
165 * Make sure the floating-point register state in the
166 * the thread_struct is up to date for task tsk.
168 void flush_fp_to_thread(struct task_struct
*tsk
)
170 if (tsk
->thread
.regs
) {
172 * We need to disable preemption here because if we didn't,
173 * another process could get scheduled after the regs->msr
174 * test but before we have finished saving the FP registers
175 * to the thread_struct. That process could take over the
176 * FPU, and then when we get scheduled again we would store
177 * bogus values for the remaining FP registers.
180 if (tsk
->thread
.regs
->msr
& MSR_FP
) {
182 * This should only ever be called for current or
183 * for a stopped child process. Since we save away
184 * the FP register state on context switch,
185 * there is something wrong if a stopped child appears
186 * to still have its FP state in the CPU registers.
188 BUG_ON(tsk
!= current
);
194 EXPORT_SYMBOL_GPL(flush_fp_to_thread
);
196 void enable_kernel_fp(void)
198 WARN_ON(preemptible());
200 msr_check_and_set(MSR_FP
);
202 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_FP
)) {
203 check_if_tm_restore_required(current
);
204 __giveup_fpu(current
);
207 EXPORT_SYMBOL(enable_kernel_fp
);
209 static int restore_fp(struct task_struct
*tsk
) {
210 if (tsk
->thread
.load_fp
) {
211 load_fp_state(¤t
->thread
.fp_state
);
212 current
->thread
.load_fp
++;
218 static int restore_fp(struct task_struct
*tsk
) { return 0; }
219 #endif /* CONFIG_PPC_FPU */
221 #ifdef CONFIG_ALTIVEC
222 #define loadvec(thr) ((thr).load_vec)
224 static void __giveup_altivec(struct task_struct
*tsk
)
229 msr
= tsk
->thread
.regs
->msr
;
232 if (cpu_has_feature(CPU_FTR_VSX
))
235 tsk
->thread
.regs
->msr
= msr
;
238 void giveup_altivec(struct task_struct
*tsk
)
240 check_if_tm_restore_required(tsk
);
242 msr_check_and_set(MSR_VEC
);
243 __giveup_altivec(tsk
);
244 msr_check_and_clear(MSR_VEC
);
246 EXPORT_SYMBOL(giveup_altivec
);
248 void enable_kernel_altivec(void)
250 WARN_ON(preemptible());
252 msr_check_and_set(MSR_VEC
);
254 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_VEC
)) {
255 check_if_tm_restore_required(current
);
256 __giveup_altivec(current
);
259 EXPORT_SYMBOL(enable_kernel_altivec
);
262 * Make sure the VMX/Altivec register state in the
263 * the thread_struct is up to date for task tsk.
265 void flush_altivec_to_thread(struct task_struct
*tsk
)
267 if (tsk
->thread
.regs
) {
269 if (tsk
->thread
.regs
->msr
& MSR_VEC
) {
270 BUG_ON(tsk
!= current
);
276 EXPORT_SYMBOL_GPL(flush_altivec_to_thread
);
278 static int restore_altivec(struct task_struct
*tsk
)
280 if (cpu_has_feature(CPU_FTR_ALTIVEC
) && tsk
->thread
.load_vec
) {
281 load_vr_state(&tsk
->thread
.vr_state
);
282 tsk
->thread
.used_vr
= 1;
283 tsk
->thread
.load_vec
++;
290 #define loadvec(thr) 0
291 static inline int restore_altivec(struct task_struct
*tsk
) { return 0; }
292 #endif /* CONFIG_ALTIVEC */
295 static void __giveup_vsx(struct task_struct
*tsk
)
297 if (tsk
->thread
.regs
->msr
& MSR_FP
)
299 if (tsk
->thread
.regs
->msr
& MSR_VEC
)
300 __giveup_altivec(tsk
);
301 tsk
->thread
.regs
->msr
&= ~MSR_VSX
;
304 static void giveup_vsx(struct task_struct
*tsk
)
306 check_if_tm_restore_required(tsk
);
308 msr_check_and_set(MSR_FP
|MSR_VEC
|MSR_VSX
);
310 msr_check_and_clear(MSR_FP
|MSR_VEC
|MSR_VSX
);
313 static void save_vsx(struct task_struct
*tsk
)
315 if (tsk
->thread
.regs
->msr
& MSR_FP
)
317 if (tsk
->thread
.regs
->msr
& MSR_VEC
)
321 void enable_kernel_vsx(void)
323 WARN_ON(preemptible());
325 msr_check_and_set(MSR_FP
|MSR_VEC
|MSR_VSX
);
327 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_VSX
)) {
328 check_if_tm_restore_required(current
);
329 if (current
->thread
.regs
->msr
& MSR_FP
)
330 __giveup_fpu(current
);
331 if (current
->thread
.regs
->msr
& MSR_VEC
)
332 __giveup_altivec(current
);
333 __giveup_vsx(current
);
336 EXPORT_SYMBOL(enable_kernel_vsx
);
338 void flush_vsx_to_thread(struct task_struct
*tsk
)
340 if (tsk
->thread
.regs
) {
342 if (tsk
->thread
.regs
->msr
& MSR_VSX
) {
343 BUG_ON(tsk
!= current
);
349 EXPORT_SYMBOL_GPL(flush_vsx_to_thread
);
351 static int restore_vsx(struct task_struct
*tsk
)
353 if (cpu_has_feature(CPU_FTR_VSX
)) {
354 tsk
->thread
.used_vsr
= 1;
361 static inline int restore_vsx(struct task_struct
*tsk
) { return 0; }
362 static inline void save_vsx(struct task_struct
*tsk
) { }
363 #endif /* CONFIG_VSX */
366 void giveup_spe(struct task_struct
*tsk
)
368 check_if_tm_restore_required(tsk
);
370 msr_check_and_set(MSR_SPE
);
372 msr_check_and_clear(MSR_SPE
);
374 EXPORT_SYMBOL(giveup_spe
);
376 void enable_kernel_spe(void)
378 WARN_ON(preemptible());
380 msr_check_and_set(MSR_SPE
);
382 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_SPE
)) {
383 check_if_tm_restore_required(current
);
384 __giveup_spe(current
);
387 EXPORT_SYMBOL(enable_kernel_spe
);
389 void flush_spe_to_thread(struct task_struct
*tsk
)
391 if (tsk
->thread
.regs
) {
393 if (tsk
->thread
.regs
->msr
& MSR_SPE
) {
394 BUG_ON(tsk
!= current
);
395 tsk
->thread
.spefscr
= mfspr(SPRN_SPEFSCR
);
401 #endif /* CONFIG_SPE */
403 static unsigned long msr_all_available
;
405 static int __init
init_msr_all_available(void)
407 #ifdef CONFIG_PPC_FPU
408 msr_all_available
|= MSR_FP
;
410 #ifdef CONFIG_ALTIVEC
411 if (cpu_has_feature(CPU_FTR_ALTIVEC
))
412 msr_all_available
|= MSR_VEC
;
415 if (cpu_has_feature(CPU_FTR_VSX
))
416 msr_all_available
|= MSR_VSX
;
419 if (cpu_has_feature(CPU_FTR_SPE
))
420 msr_all_available
|= MSR_SPE
;
425 early_initcall(init_msr_all_available
);
427 void giveup_all(struct task_struct
*tsk
)
429 unsigned long usermsr
;
431 if (!tsk
->thread
.regs
)
434 usermsr
= tsk
->thread
.regs
->msr
;
436 if ((usermsr
& msr_all_available
) == 0)
439 msr_check_and_set(msr_all_available
);
441 #ifdef CONFIG_PPC_FPU
442 if (usermsr
& MSR_FP
)
445 #ifdef CONFIG_ALTIVEC
446 if (usermsr
& MSR_VEC
)
447 __giveup_altivec(tsk
);
450 if (usermsr
& MSR_VSX
)
454 if (usermsr
& MSR_SPE
)
458 msr_check_and_clear(msr_all_available
);
460 EXPORT_SYMBOL(giveup_all
);
462 void restore_math(struct pt_regs
*regs
)
466 if (!current
->thread
.load_fp
&& !loadvec(current
->thread
))
470 msr_check_and_set(msr_all_available
);
473 * Only reload if the bit is not set in the user MSR, the bit BEING set
474 * indicates that the registers are hot
476 if ((!(msr
& MSR_FP
)) && restore_fp(current
))
477 msr
|= MSR_FP
| current
->thread
.fpexc_mode
;
479 if ((!(msr
& MSR_VEC
)) && restore_altivec(current
))
482 if ((msr
& (MSR_FP
| MSR_VEC
)) == (MSR_FP
| MSR_VEC
) &&
483 restore_vsx(current
)) {
487 msr_check_and_clear(msr_all_available
);
492 void save_all(struct task_struct
*tsk
)
494 unsigned long usermsr
;
496 if (!tsk
->thread
.regs
)
499 usermsr
= tsk
->thread
.regs
->msr
;
501 if ((usermsr
& msr_all_available
) == 0)
504 msr_check_and_set(msr_all_available
);
507 * Saving the way the register space is in hardware, save_vsx boils
508 * down to a save_fpu() and save_altivec()
510 if (usermsr
& MSR_VSX
) {
513 if (usermsr
& MSR_FP
)
516 if (usermsr
& MSR_VEC
)
520 if (usermsr
& MSR_SPE
)
523 msr_check_and_clear(msr_all_available
);
526 void flush_all_to_thread(struct task_struct
*tsk
)
528 if (tsk
->thread
.regs
) {
530 BUG_ON(tsk
!= current
);
534 if (tsk
->thread
.regs
->msr
& MSR_SPE
)
535 tsk
->thread
.spefscr
= mfspr(SPRN_SPEFSCR
);
541 EXPORT_SYMBOL(flush_all_to_thread
);
543 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
544 void do_send_trap(struct pt_regs
*regs
, unsigned long address
,
545 unsigned long error_code
, int signal_code
, int breakpt
)
549 current
->thread
.trap_nr
= signal_code
;
550 if (notify_die(DIE_DABR_MATCH
, "dabr_match", regs
, error_code
,
551 11, SIGSEGV
) == NOTIFY_STOP
)
554 /* Deliver the signal to userspace */
555 info
.si_signo
= SIGTRAP
;
556 info
.si_errno
= breakpt
; /* breakpoint or watchpoint id */
557 info
.si_code
= signal_code
;
558 info
.si_addr
= (void __user
*)address
;
559 force_sig_info(SIGTRAP
, &info
, current
);
561 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
562 void do_break (struct pt_regs
*regs
, unsigned long address
,
563 unsigned long error_code
)
567 current
->thread
.trap_nr
= TRAP_HWBKPT
;
568 if (notify_die(DIE_DABR_MATCH
, "dabr_match", regs
, error_code
,
569 11, SIGSEGV
) == NOTIFY_STOP
)
572 if (debugger_break_match(regs
))
575 /* Clear the breakpoint */
576 hw_breakpoint_disable();
578 /* Deliver the signal to userspace */
579 info
.si_signo
= SIGTRAP
;
581 info
.si_code
= TRAP_HWBKPT
;
582 info
.si_addr
= (void __user
*)address
;
583 force_sig_info(SIGTRAP
, &info
, current
);
585 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
587 static DEFINE_PER_CPU(struct arch_hw_breakpoint
, current_brk
);
589 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
591 * Set the debug registers back to their default "safe" values.
593 static void set_debug_reg_defaults(struct thread_struct
*thread
)
595 thread
->debug
.iac1
= thread
->debug
.iac2
= 0;
596 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
597 thread
->debug
.iac3
= thread
->debug
.iac4
= 0;
599 thread
->debug
.dac1
= thread
->debug
.dac2
= 0;
600 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
601 thread
->debug
.dvc1
= thread
->debug
.dvc2
= 0;
603 thread
->debug
.dbcr0
= 0;
606 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
608 thread
->debug
.dbcr1
= DBCR1_IAC1US
| DBCR1_IAC2US
|
609 DBCR1_IAC3US
| DBCR1_IAC4US
;
611 * Force Data Address Compare User/Supervisor bits to be User-only
612 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
614 thread
->debug
.dbcr2
= DBCR2_DAC1US
| DBCR2_DAC2US
;
616 thread
->debug
.dbcr1
= 0;
620 static void prime_debug_regs(struct debug_reg
*debug
)
623 * We could have inherited MSR_DE from userspace, since
624 * it doesn't get cleared on exception entry. Make sure
625 * MSR_DE is clear before we enable any debug events.
627 mtmsr(mfmsr() & ~MSR_DE
);
629 mtspr(SPRN_IAC1
, debug
->iac1
);
630 mtspr(SPRN_IAC2
, debug
->iac2
);
631 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
632 mtspr(SPRN_IAC3
, debug
->iac3
);
633 mtspr(SPRN_IAC4
, debug
->iac4
);
635 mtspr(SPRN_DAC1
, debug
->dac1
);
636 mtspr(SPRN_DAC2
, debug
->dac2
);
637 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
638 mtspr(SPRN_DVC1
, debug
->dvc1
);
639 mtspr(SPRN_DVC2
, debug
->dvc2
);
641 mtspr(SPRN_DBCR0
, debug
->dbcr0
);
642 mtspr(SPRN_DBCR1
, debug
->dbcr1
);
644 mtspr(SPRN_DBCR2
, debug
->dbcr2
);
648 * Unless neither the old or new thread are making use of the
649 * debug registers, set the debug registers from the values
650 * stored in the new thread.
652 void switch_booke_debug_regs(struct debug_reg
*new_debug
)
654 if ((current
->thread
.debug
.dbcr0
& DBCR0_IDM
)
655 || (new_debug
->dbcr0
& DBCR0_IDM
))
656 prime_debug_regs(new_debug
);
658 EXPORT_SYMBOL_GPL(switch_booke_debug_regs
);
659 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
660 #ifndef CONFIG_HAVE_HW_BREAKPOINT
661 static void set_debug_reg_defaults(struct thread_struct
*thread
)
663 thread
->hw_brk
.address
= 0;
664 thread
->hw_brk
.type
= 0;
665 set_breakpoint(&thread
->hw_brk
);
667 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
668 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
670 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
671 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
673 mtspr(SPRN_DAC1
, dabr
);
674 #ifdef CONFIG_PPC_47x
679 #elif defined(CONFIG_PPC_BOOK3S)
680 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
682 mtspr(SPRN_DABR
, dabr
);
683 if (cpu_has_feature(CPU_FTR_DABRX
))
684 mtspr(SPRN_DABRX
, dabrx
);
688 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
694 static inline int set_dabr(struct arch_hw_breakpoint
*brk
)
696 unsigned long dabr
, dabrx
;
698 dabr
= brk
->address
| (brk
->type
& HW_BRK_TYPE_DABR
);
699 dabrx
= ((brk
->type
>> 3) & 0x7);
702 return ppc_md
.set_dabr(dabr
, dabrx
);
704 return __set_dabr(dabr
, dabrx
);
707 static inline int set_dawr(struct arch_hw_breakpoint
*brk
)
709 unsigned long dawr
, dawrx
, mrd
;
713 dawrx
= (brk
->type
& (HW_BRK_TYPE_READ
| HW_BRK_TYPE_WRITE
)) \
714 << (63 - 58); //* read/write bits */
715 dawrx
|= ((brk
->type
& (HW_BRK_TYPE_TRANSLATE
)) >> 2) \
716 << (63 - 59); //* translate */
717 dawrx
|= (brk
->type
& (HW_BRK_TYPE_PRIV_ALL
)) \
718 >> 3; //* PRIM bits */
719 /* dawr length is stored in field MDR bits 48:53. Matches range in
720 doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
722 brk->len is in bytes.
723 This aligns up to double word size, shifts and does the bias.
725 mrd
= ((brk
->len
+ 7) >> 3) - 1;
726 dawrx
|= (mrd
& 0x3f) << (63 - 53);
729 return ppc_md
.set_dawr(dawr
, dawrx
);
730 mtspr(SPRN_DAWR
, dawr
);
731 mtspr(SPRN_DAWRX
, dawrx
);
735 void __set_breakpoint(struct arch_hw_breakpoint
*brk
)
737 memcpy(this_cpu_ptr(¤t_brk
), brk
, sizeof(*brk
));
739 if (cpu_has_feature(CPU_FTR_DAWR
))
745 void set_breakpoint(struct arch_hw_breakpoint
*brk
)
748 __set_breakpoint(brk
);
753 DEFINE_PER_CPU(struct cpu_usage
, cpu_usage_array
);
756 static inline bool hw_brk_match(struct arch_hw_breakpoint
*a
,
757 struct arch_hw_breakpoint
*b
)
759 if (a
->address
!= b
->address
)
761 if (a
->type
!= b
->type
)
763 if (a
->len
!= b
->len
)
768 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
769 static void tm_reclaim_thread(struct thread_struct
*thr
,
770 struct thread_info
*ti
, uint8_t cause
)
772 unsigned long msr_diff
= 0;
775 * If FP/VSX registers have been already saved to the
776 * thread_struct, move them to the transact_fp array.
777 * We clear the TIF_RESTORE_TM bit since after the reclaim
778 * the thread will no longer be transactional.
780 if (test_ti_thread_flag(ti
, TIF_RESTORE_TM
)) {
781 msr_diff
= thr
->ckpt_regs
.msr
& ~thr
->regs
->msr
;
782 if (msr_diff
& MSR_FP
)
783 memcpy(&thr
->transact_fp
, &thr
->fp_state
,
784 sizeof(struct thread_fp_state
));
785 if (msr_diff
& MSR_VEC
)
786 memcpy(&thr
->transact_vr
, &thr
->vr_state
,
787 sizeof(struct thread_vr_state
));
788 clear_ti_thread_flag(ti
, TIF_RESTORE_TM
);
789 msr_diff
&= MSR_FP
| MSR_VEC
| MSR_VSX
| MSR_FE0
| MSR_FE1
;
793 * Use the current MSR TM suspended bit to track if we have
794 * checkpointed state outstanding.
795 * On signal delivery, we'd normally reclaim the checkpointed
796 * state to obtain stack pointer (see:get_tm_stackpointer()).
797 * This will then directly return to userspace without going
798 * through __switch_to(). However, if the stack frame is bad,
799 * we need to exit this thread which calls __switch_to() which
800 * will again attempt to reclaim the already saved tm state.
801 * Hence we need to check that we've not already reclaimed
803 * We do this using the current MSR, rather tracking it in
804 * some specific thread_struct bit, as it has the additional
805 * benefit of checking for a potential TM bad thing exception.
807 if (!MSR_TM_SUSPENDED(mfmsr()))
810 tm_reclaim(thr
, thr
->regs
->msr
, cause
);
812 /* Having done the reclaim, we now have the checkpointed
813 * FP/VSX values in the registers. These might be valid
814 * even if we have previously called enable_kernel_fp() or
815 * flush_fp_to_thread(), so update thr->regs->msr to
816 * indicate their current validity.
818 thr
->regs
->msr
|= msr_diff
;
821 void tm_reclaim_current(uint8_t cause
)
824 tm_reclaim_thread(¤t
->thread
, current_thread_info(), cause
);
827 static inline void tm_reclaim_task(struct task_struct
*tsk
)
829 /* We have to work out if we're switching from/to a task that's in the
830 * middle of a transaction.
832 * In switching we need to maintain a 2nd register state as
833 * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the
834 * checkpointed (tbegin) state in ckpt_regs and saves the transactional
835 * (current) FPRs into oldtask->thread.transact_fpr[].
837 * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
839 struct thread_struct
*thr
= &tsk
->thread
;
844 if (!MSR_TM_ACTIVE(thr
->regs
->msr
))
845 goto out_and_saveregs
;
847 /* Stash the original thread MSR, as giveup_fpu et al will
848 * modify it. We hold onto it to see whether the task used
849 * FP & vector regs. If the TIF_RESTORE_TM flag is set,
850 * ckpt_regs.msr is already set.
852 if (!test_ti_thread_flag(task_thread_info(tsk
), TIF_RESTORE_TM
))
853 thr
->ckpt_regs
.msr
= thr
->regs
->msr
;
855 TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
856 "ccr=%lx, msr=%lx, trap=%lx)\n",
857 tsk
->pid
, thr
->regs
->nip
,
858 thr
->regs
->ccr
, thr
->regs
->msr
,
861 tm_reclaim_thread(thr
, task_thread_info(tsk
), TM_CAUSE_RESCHED
);
863 TM_DEBUG("--- tm_reclaim on pid %d complete\n",
867 /* Always save the regs here, even if a transaction's not active.
868 * This context-switches a thread's TM info SPRs. We do it here to
869 * be consistent with the restore path (in recheckpoint) which
870 * cannot happen later in _switch().
875 extern void __tm_recheckpoint(struct thread_struct
*thread
,
876 unsigned long orig_msr
);
878 void tm_recheckpoint(struct thread_struct
*thread
,
879 unsigned long orig_msr
)
883 /* We really can't be interrupted here as the TEXASR registers can't
884 * change and later in the trecheckpoint code, we have a userspace R1.
885 * So let's hard disable over this region.
887 local_irq_save(flags
);
890 /* The TM SPRs are restored here, so that TEXASR.FS can be set
891 * before the trecheckpoint and no explosion occurs.
893 tm_restore_sprs(thread
);
895 __tm_recheckpoint(thread
, orig_msr
);
897 local_irq_restore(flags
);
900 static inline void tm_recheckpoint_new_task(struct task_struct
*new)
904 if (!cpu_has_feature(CPU_FTR_TM
))
907 /* Recheckpoint the registers of the thread we're about to switch to.
909 * If the task was using FP, we non-lazily reload both the original and
910 * the speculative FP register states. This is because the kernel
911 * doesn't see if/when a TM rollback occurs, so if we take an FP
912 * unavoidable later, we are unable to determine which set of FP regs
913 * need to be restored.
915 if (!new->thread
.regs
)
918 if (!MSR_TM_ACTIVE(new->thread
.regs
->msr
)){
919 tm_restore_sprs(&new->thread
);
922 msr
= new->thread
.ckpt_regs
.msr
;
923 /* Recheckpoint to restore original checkpointed register state. */
924 TM_DEBUG("*** tm_recheckpoint of pid %d "
925 "(new->msr 0x%lx, new->origmsr 0x%lx)\n",
926 new->pid
, new->thread
.regs
->msr
, msr
);
928 /* This loads the checkpointed FP/VEC state, if used */
929 tm_recheckpoint(&new->thread
, msr
);
931 /* This loads the speculative FP/VEC state, if used */
933 do_load_up_transact_fpu(&new->thread
);
934 new->thread
.regs
->msr
|=
935 (MSR_FP
| new->thread
.fpexc_mode
);
937 #ifdef CONFIG_ALTIVEC
939 do_load_up_transact_altivec(&new->thread
);
940 new->thread
.regs
->msr
|= MSR_VEC
;
943 /* We may as well turn on VSX too since all the state is restored now */
945 new->thread
.regs
->msr
|= MSR_VSX
;
947 TM_DEBUG("*** tm_recheckpoint of pid %d complete "
948 "(kernel msr 0x%lx)\n",
952 static inline void __switch_to_tm(struct task_struct
*prev
)
954 if (cpu_has_feature(CPU_FTR_TM
)) {
956 tm_reclaim_task(prev
);
961 * This is called if we are on the way out to userspace and the
962 * TIF_RESTORE_TM flag is set. It checks if we need to reload
963 * FP and/or vector state and does so if necessary.
964 * If userspace is inside a transaction (whether active or
965 * suspended) and FP/VMX/VSX instructions have ever been enabled
966 * inside that transaction, then we have to keep them enabled
967 * and keep the FP/VMX/VSX state loaded while ever the transaction
968 * continues. The reason is that if we didn't, and subsequently
969 * got a FP/VMX/VSX unavailable interrupt inside a transaction,
970 * we don't know whether it's the same transaction, and thus we
971 * don't know which of the checkpointed state and the transactional
974 void restore_tm_state(struct pt_regs
*regs
)
976 unsigned long msr_diff
;
978 clear_thread_flag(TIF_RESTORE_TM
);
979 if (!MSR_TM_ACTIVE(regs
->msr
))
982 msr_diff
= current
->thread
.ckpt_regs
.msr
& ~regs
->msr
;
983 msr_diff
&= MSR_FP
| MSR_VEC
| MSR_VSX
;
987 regs
->msr
|= msr_diff
;
991 #define tm_recheckpoint_new_task(new)
992 #define __switch_to_tm(prev)
993 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
995 static inline void save_sprs(struct thread_struct
*t
)
997 #ifdef CONFIG_ALTIVEC
998 if (cpu_has_feature(CPU_FTR_ALTIVEC
))
999 t
->vrsave
= mfspr(SPRN_VRSAVE
);
1001 #ifdef CONFIG_PPC_BOOK3S_64
1002 if (cpu_has_feature(CPU_FTR_DSCR
))
1003 t
->dscr
= mfspr(SPRN_DSCR
);
1005 if (cpu_has_feature(CPU_FTR_ARCH_207S
)) {
1006 t
->bescr
= mfspr(SPRN_BESCR
);
1007 t
->ebbhr
= mfspr(SPRN_EBBHR
);
1008 t
->ebbrr
= mfspr(SPRN_EBBRR
);
1010 t
->fscr
= mfspr(SPRN_FSCR
);
1013 * Note that the TAR is not available for use in the kernel.
1014 * (To provide this, the TAR should be backed up/restored on
1015 * exception entry/exit instead, and be in pt_regs. FIXME,
1016 * this should be in pt_regs anyway (for debug).)
1018 t
->tar
= mfspr(SPRN_TAR
);
1021 if (cpu_has_feature(CPU_FTR_ARCH_300
)) {
1022 /* Conditionally save Load Monitor registers, if enabled */
1023 if (t
->fscr
& FSCR_LM
) {
1024 t
->lmrr
= mfspr(SPRN_LMRR
);
1025 t
->lmser
= mfspr(SPRN_LMSER
);
1031 static inline void restore_sprs(struct thread_struct
*old_thread
,
1032 struct thread_struct
*new_thread
)
1034 #ifdef CONFIG_ALTIVEC
1035 if (cpu_has_feature(CPU_FTR_ALTIVEC
) &&
1036 old_thread
->vrsave
!= new_thread
->vrsave
)
1037 mtspr(SPRN_VRSAVE
, new_thread
->vrsave
);
1039 #ifdef CONFIG_PPC_BOOK3S_64
1040 if (cpu_has_feature(CPU_FTR_DSCR
)) {
1041 u64 dscr
= get_paca()->dscr_default
;
1042 if (new_thread
->dscr_inherit
)
1043 dscr
= new_thread
->dscr
;
1045 if (old_thread
->dscr
!= dscr
)
1046 mtspr(SPRN_DSCR
, dscr
);
1049 if (cpu_has_feature(CPU_FTR_ARCH_207S
)) {
1050 if (old_thread
->bescr
!= new_thread
->bescr
)
1051 mtspr(SPRN_BESCR
, new_thread
->bescr
);
1052 if (old_thread
->ebbhr
!= new_thread
->ebbhr
)
1053 mtspr(SPRN_EBBHR
, new_thread
->ebbhr
);
1054 if (old_thread
->ebbrr
!= new_thread
->ebbrr
)
1055 mtspr(SPRN_EBBRR
, new_thread
->ebbrr
);
1057 if (old_thread
->fscr
!= new_thread
->fscr
)
1058 mtspr(SPRN_FSCR
, new_thread
->fscr
);
1060 if (old_thread
->tar
!= new_thread
->tar
)
1061 mtspr(SPRN_TAR
, new_thread
->tar
);
1064 if (cpu_has_feature(CPU_FTR_ARCH_300
)) {
1065 /* Conditionally restore Load Monitor registers, if enabled */
1066 if (new_thread
->fscr
& FSCR_LM
) {
1067 if (old_thread
->lmrr
!= new_thread
->lmrr
)
1068 mtspr(SPRN_LMRR
, new_thread
->lmrr
);
1069 if (old_thread
->lmser
!= new_thread
->lmser
)
1070 mtspr(SPRN_LMSER
, new_thread
->lmser
);
1076 struct task_struct
*__switch_to(struct task_struct
*prev
,
1077 struct task_struct
*new)
1079 struct thread_struct
*new_thread
, *old_thread
;
1080 struct task_struct
*last
;
1081 #ifdef CONFIG_PPC_BOOK3S_64
1082 struct ppc64_tlb_batch
*batch
;
1085 new_thread
= &new->thread
;
1086 old_thread
= ¤t
->thread
;
1088 WARN_ON(!irqs_disabled());
1092 * Collect processor utilization data per process
1094 if (firmware_has_feature(FW_FEATURE_SPLPAR
)) {
1095 struct cpu_usage
*cu
= this_cpu_ptr(&cpu_usage_array
);
1096 long unsigned start_tb
, current_tb
;
1097 start_tb
= old_thread
->start_tb
;
1098 cu
->current_tb
= current_tb
= mfspr(SPRN_PURR
);
1099 old_thread
->accum_tb
+= (current_tb
- start_tb
);
1100 new_thread
->start_tb
= current_tb
;
1102 #endif /* CONFIG_PPC64 */
1104 #ifdef CONFIG_PPC_STD_MMU_64
1105 batch
= this_cpu_ptr(&ppc64_tlb_batch
);
1106 if (batch
->active
) {
1107 current_thread_info()->local_flags
|= _TLF_LAZY_MMU
;
1109 __flush_tlb_pending(batch
);
1112 #endif /* CONFIG_PPC_STD_MMU_64 */
1114 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1115 switch_booke_debug_regs(&new->thread
.debug
);
1118 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
1121 #ifndef CONFIG_HAVE_HW_BREAKPOINT
1122 if (unlikely(!hw_brk_match(this_cpu_ptr(¤t_brk
), &new->thread
.hw_brk
)))
1123 __set_breakpoint(&new->thread
.hw_brk
);
1124 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1128 * We need to save SPRs before treclaim/trecheckpoint as these will
1129 * change a number of them.
1131 save_sprs(&prev
->thread
);
1133 __switch_to_tm(prev
);
1135 /* Save FPU, Altivec, VSX and SPE state */
1139 * We can't take a PMU exception inside _switch() since there is a
1140 * window where the kernel stack SLB and the kernel stack are out
1141 * of sync. Hard disable here.
1145 tm_recheckpoint_new_task(new);
1148 * Call restore_sprs() before calling _switch(). If we move it after
1149 * _switch() then we miss out on calling it for new tasks. The reason
1150 * for this is we manually create a stack frame for new tasks that
1151 * directly returns through ret_from_fork() or
1152 * ret_from_kernel_thread(). See copy_thread() for details.
1154 restore_sprs(old_thread
, new_thread
);
1156 last
= _switch(old_thread
, new_thread
);
1158 #ifdef CONFIG_PPC_STD_MMU_64
1159 if (current_thread_info()->local_flags
& _TLF_LAZY_MMU
) {
1160 current_thread_info()->local_flags
&= ~_TLF_LAZY_MMU
;
1161 batch
= this_cpu_ptr(&ppc64_tlb_batch
);
1165 if (current_thread_info()->task
->thread
.regs
)
1166 restore_math(current_thread_info()->task
->thread
.regs
);
1167 #endif /* CONFIG_PPC_STD_MMU_64 */
1172 static int instructions_to_print
= 16;
1174 static void show_instructions(struct pt_regs
*regs
)
1177 unsigned long pc
= regs
->nip
- (instructions_to_print
* 3 / 4 *
1180 printk("Instruction dump:");
1182 for (i
= 0; i
< instructions_to_print
; i
++) {
1188 #if !defined(CONFIG_BOOKE)
1189 /* If executing with the IMMU off, adjust pc rather
1190 * than print XXXXXXXX.
1192 if (!(regs
->msr
& MSR_IR
))
1193 pc
= (unsigned long)phys_to_virt(pc
);
1196 if (!__kernel_text_address(pc
) ||
1197 probe_kernel_address((unsigned int __user
*)pc
, instr
)) {
1198 printk(KERN_CONT
"XXXXXXXX ");
1200 if (regs
->nip
== pc
)
1201 printk(KERN_CONT
"<%08x> ", instr
);
1203 printk(KERN_CONT
"%08x ", instr
);
1217 static struct regbit msr_bits
[] = {
1218 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1240 #ifndef CONFIG_BOOKE
1247 static void print_bits(unsigned long val
, struct regbit
*bits
, const char *sep
)
1251 for (; bits
->bit
; ++bits
)
1252 if (val
& bits
->bit
) {
1253 printk("%s%s", s
, bits
->name
);
1258 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1259 static struct regbit msr_tm_bits
[] = {
1266 static void print_tm_bits(unsigned long val
)
1269 * This only prints something if at least one of the TM bit is set.
1270 * Inside the TM[], the output means:
1271 * E: Enabled (bit 32)
1272 * S: Suspended (bit 33)
1273 * T: Transactional (bit 34)
1275 if (val
& (MSR_TM
| MSR_TS_S
| MSR_TS_T
)) {
1277 print_bits(val
, msr_tm_bits
, "");
1282 static void print_tm_bits(unsigned long val
) {}
1285 static void print_msr_bits(unsigned long val
)
1288 print_bits(val
, msr_bits
, ",");
1294 #define REG "%016lx"
1295 #define REGS_PER_LINE 4
1296 #define LAST_VOLATILE 13
1299 #define REGS_PER_LINE 8
1300 #define LAST_VOLATILE 12
1303 void show_regs(struct pt_regs
* regs
)
1307 show_regs_print_info(KERN_DEFAULT
);
1309 printk("NIP: "REG
" LR: "REG
" CTR: "REG
"\n",
1310 regs
->nip
, regs
->link
, regs
->ctr
);
1311 printk("REGS: %p TRAP: %04lx %s (%s)\n",
1312 regs
, regs
->trap
, print_tainted(), init_utsname()->release
);
1313 printk("MSR: "REG
" ", regs
->msr
);
1314 print_msr_bits(regs
->msr
);
1315 printk(" CR: %08lx XER: %08lx\n", regs
->ccr
, regs
->xer
);
1317 if ((regs
->trap
!= 0xc00) && cpu_has_feature(CPU_FTR_CFAR
))
1318 printk("CFAR: "REG
" ", regs
->orig_gpr3
);
1319 if (trap
== 0x200 || trap
== 0x300 || trap
== 0x600)
1320 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1321 printk("DEAR: "REG
" ESR: "REG
" ", regs
->dar
, regs
->dsisr
);
1323 printk("DAR: "REG
" DSISR: %08lx ", regs
->dar
, regs
->dsisr
);
1326 printk("SOFTE: %ld ", regs
->softe
);
1328 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1329 if (MSR_TM_ACTIVE(regs
->msr
))
1330 printk("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch
);
1333 for (i
= 0; i
< 32; i
++) {
1334 if ((i
% REGS_PER_LINE
) == 0)
1335 printk("\nGPR%02d: ", i
);
1336 printk(REG
" ", regs
->gpr
[i
]);
1337 if (i
== LAST_VOLATILE
&& !FULL_REGS(regs
))
1341 #ifdef CONFIG_KALLSYMS
1343 * Lookup NIP late so we have the best change of getting the
1344 * above info out without failing
1346 printk("NIP ["REG
"] %pS\n", regs
->nip
, (void *)regs
->nip
);
1347 printk("LR ["REG
"] %pS\n", regs
->link
, (void *)regs
->link
);
1349 show_stack(current
, (unsigned long *) regs
->gpr
[1]);
1350 if (!user_mode(regs
))
1351 show_instructions(regs
);
1354 void flush_thread(void)
1356 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1357 flush_ptrace_hw_breakpoint(current
);
1358 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1359 set_debug_reg_defaults(¤t
->thread
);
1360 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1364 release_thread(struct task_struct
*t
)
1369 * this gets called so that we can store coprocessor state into memory and
1370 * copy the current task into the new thread.
1372 int arch_dup_task_struct(struct task_struct
*dst
, struct task_struct
*src
)
1374 flush_all_to_thread(src
);
1376 * Flush TM state out so we can copy it. __switch_to_tm() does this
1377 * flush but it removes the checkpointed state from the current CPU and
1378 * transitions the CPU out of TM mode. Hence we need to call
1379 * tm_recheckpoint_new_task() (on the same task) to restore the
1380 * checkpointed state back and the TM mode.
1382 __switch_to_tm(src
);
1383 tm_recheckpoint_new_task(src
);
1387 clear_task_ebb(dst
);
1392 static void setup_ksp_vsid(struct task_struct
*p
, unsigned long sp
)
1394 #ifdef CONFIG_PPC_STD_MMU_64
1395 unsigned long sp_vsid
;
1396 unsigned long llp
= mmu_psize_defs
[mmu_linear_psize
].sllp
;
1398 if (radix_enabled())
1401 if (mmu_has_feature(MMU_FTR_1T_SEGMENT
))
1402 sp_vsid
= get_kernel_vsid(sp
, MMU_SEGSIZE_1T
)
1403 << SLB_VSID_SHIFT_1T
;
1405 sp_vsid
= get_kernel_vsid(sp
, MMU_SEGSIZE_256M
)
1407 sp_vsid
|= SLB_VSID_KERNEL
| llp
;
1408 p
->thread
.ksp_vsid
= sp_vsid
;
1417 * Copy architecture-specific thread state
1419 int copy_thread(unsigned long clone_flags
, unsigned long usp
,
1420 unsigned long kthread_arg
, struct task_struct
*p
)
1422 struct pt_regs
*childregs
, *kregs
;
1423 extern void ret_from_fork(void);
1424 extern void ret_from_kernel_thread(void);
1426 unsigned long sp
= (unsigned long)task_stack_page(p
) + THREAD_SIZE
;
1427 struct thread_info
*ti
= task_thread_info(p
);
1429 klp_init_thread_info(ti
);
1431 /* Copy registers */
1432 sp
-= sizeof(struct pt_regs
);
1433 childregs
= (struct pt_regs
*) sp
;
1434 if (unlikely(p
->flags
& PF_KTHREAD
)) {
1436 memset(childregs
, 0, sizeof(struct pt_regs
));
1437 childregs
->gpr
[1] = sp
+ sizeof(struct pt_regs
);
1440 childregs
->gpr
[14] = ppc_function_entry((void *)usp
);
1442 clear_tsk_thread_flag(p
, TIF_32BIT
);
1443 childregs
->softe
= 1;
1445 childregs
->gpr
[15] = kthread_arg
;
1446 p
->thread
.regs
= NULL
; /* no user register state */
1447 ti
->flags
|= _TIF_RESTOREALL
;
1448 f
= ret_from_kernel_thread
;
1451 struct pt_regs
*regs
= current_pt_regs();
1452 CHECK_FULL_REGS(regs
);
1455 childregs
->gpr
[1] = usp
;
1456 p
->thread
.regs
= childregs
;
1457 childregs
->gpr
[3] = 0; /* Result from fork() */
1458 if (clone_flags
& CLONE_SETTLS
) {
1460 if (!is_32bit_task())
1461 childregs
->gpr
[13] = childregs
->gpr
[6];
1464 childregs
->gpr
[2] = childregs
->gpr
[6];
1469 childregs
->msr
&= ~(MSR_FP
|MSR_VEC
|MSR_VSX
);
1470 sp
-= STACK_FRAME_OVERHEAD
;
1473 * The way this works is that at some point in the future
1474 * some task will call _switch to switch to the new task.
1475 * That will pop off the stack frame created below and start
1476 * the new task running at ret_from_fork. The new task will
1477 * do some house keeping and then return from the fork or clone
1478 * system call, using the stack frame created above.
1480 ((unsigned long *)sp
)[0] = 0;
1481 sp
-= sizeof(struct pt_regs
);
1482 kregs
= (struct pt_regs
*) sp
;
1483 sp
-= STACK_FRAME_OVERHEAD
;
1486 p
->thread
.ksp_limit
= (unsigned long)task_stack_page(p
) +
1487 _ALIGN_UP(sizeof(struct thread_info
), 16);
1489 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1490 p
->thread
.ptrace_bps
[0] = NULL
;
1493 p
->thread
.fp_save_area
= NULL
;
1494 #ifdef CONFIG_ALTIVEC
1495 p
->thread
.vr_save_area
= NULL
;
1498 setup_ksp_vsid(p
, sp
);
1501 if (cpu_has_feature(CPU_FTR_DSCR
)) {
1502 p
->thread
.dscr_inherit
= current
->thread
.dscr_inherit
;
1503 p
->thread
.dscr
= mfspr(SPRN_DSCR
);
1505 if (cpu_has_feature(CPU_FTR_HAS_PPR
))
1506 p
->thread
.ppr
= INIT_PPR
;
1508 kregs
->nip
= ppc_function_entry(f
);
1513 * Set up a thread for executing a new program
1515 void start_thread(struct pt_regs
*regs
, unsigned long start
, unsigned long sp
)
1518 unsigned long load_addr
= regs
->gpr
[2]; /* saved by ELF_PLAT_INIT */
1522 * If we exec out of a kernel thread then thread.regs will not be
1525 if (!current
->thread
.regs
) {
1526 struct pt_regs
*regs
= task_stack_page(current
) + THREAD_SIZE
;
1527 current
->thread
.regs
= regs
- 1;
1530 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1532 * Clear any transactional state, we're exec()ing. The cause is
1533 * not important as there will never be a recheckpoint so it's not
1536 if (MSR_TM_SUSPENDED(mfmsr()))
1537 tm_reclaim_current(0);
1540 memset(regs
->gpr
, 0, sizeof(regs
->gpr
));
1548 * We have just cleared all the nonvolatile GPRs, so make
1549 * FULL_REGS(regs) return true. This is necessary to allow
1550 * ptrace to examine the thread immediately after exec.
1557 regs
->msr
= MSR_USER
;
1559 if (!is_32bit_task()) {
1560 unsigned long entry
;
1562 if (is_elf2_task()) {
1563 /* Look ma, no function descriptors! */
1568 * The latest iteration of the ABI requires that when
1569 * calling a function (at its global entry point),
1570 * the caller must ensure r12 holds the entry point
1571 * address (so that the function can quickly
1572 * establish addressability).
1574 regs
->gpr
[12] = start
;
1575 /* Make sure that's restored on entry to userspace. */
1576 set_thread_flag(TIF_RESTOREALL
);
1580 /* start is a relocated pointer to the function
1581 * descriptor for the elf _start routine. The first
1582 * entry in the function descriptor is the entry
1583 * address of _start and the second entry is the TOC
1584 * value we need to use.
1586 __get_user(entry
, (unsigned long __user
*)start
);
1587 __get_user(toc
, (unsigned long __user
*)start
+1);
1589 /* Check whether the e_entry function descriptor entries
1590 * need to be relocated before we can use them.
1592 if (load_addr
!= 0) {
1599 regs
->msr
= MSR_USER64
;
1603 regs
->msr
= MSR_USER32
;
1607 current
->thread
.used_vsr
= 0;
1609 memset(¤t
->thread
.fp_state
, 0, sizeof(current
->thread
.fp_state
));
1610 current
->thread
.fp_save_area
= NULL
;
1611 #ifdef CONFIG_ALTIVEC
1612 memset(¤t
->thread
.vr_state
, 0, sizeof(current
->thread
.vr_state
));
1613 current
->thread
.vr_state
.vscr
.u
[3] = 0x00010000; /* Java mode disabled */
1614 current
->thread
.vr_save_area
= NULL
;
1615 current
->thread
.vrsave
= 0;
1616 current
->thread
.used_vr
= 0;
1617 #endif /* CONFIG_ALTIVEC */
1619 memset(current
->thread
.evr
, 0, sizeof(current
->thread
.evr
));
1620 current
->thread
.acc
= 0;
1621 current
->thread
.spefscr
= 0;
1622 current
->thread
.used_spe
= 0;
1623 #endif /* CONFIG_SPE */
1624 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1625 if (cpu_has_feature(CPU_FTR_TM
))
1626 regs
->msr
|= MSR_TM
;
1627 current
->thread
.tm_tfhar
= 0;
1628 current
->thread
.tm_texasr
= 0;
1629 current
->thread
.tm_tfiar
= 0;
1630 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1632 EXPORT_SYMBOL(start_thread
);
1634 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1635 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1637 int set_fpexc_mode(struct task_struct
*tsk
, unsigned int val
)
1639 struct pt_regs
*regs
= tsk
->thread
.regs
;
1641 /* This is a bit hairy. If we are an SPE enabled processor
1642 * (have embedded fp) we store the IEEE exception enable flags in
1643 * fpexc_mode. fpexc_mode is also used for setting FP exception
1644 * mode (asyn, precise, disabled) for 'Classic' FP. */
1645 if (val
& PR_FP_EXC_SW_ENABLE
) {
1647 if (cpu_has_feature(CPU_FTR_SPE
)) {
1649 * When the sticky exception bits are set
1650 * directly by userspace, it must call prctl
1651 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1652 * in the existing prctl settings) or
1653 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1654 * the bits being set). <fenv.h> functions
1655 * saving and restoring the whole
1656 * floating-point environment need to do so
1657 * anyway to restore the prctl settings from
1658 * the saved environment.
1660 tsk
->thread
.spefscr_last
= mfspr(SPRN_SPEFSCR
);
1661 tsk
->thread
.fpexc_mode
= val
&
1662 (PR_FP_EXC_SW_ENABLE
| PR_FP_ALL_EXCEPT
);
1672 /* on a CONFIG_SPE this does not hurt us. The bits that
1673 * __pack_fe01 use do not overlap with bits used for
1674 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits
1675 * on CONFIG_SPE implementations are reserved so writing to
1676 * them does not change anything */
1677 if (val
> PR_FP_EXC_PRECISE
)
1679 tsk
->thread
.fpexc_mode
= __pack_fe01(val
);
1680 if (regs
!= NULL
&& (regs
->msr
& MSR_FP
) != 0)
1681 regs
->msr
= (regs
->msr
& ~(MSR_FE0
|MSR_FE1
))
1682 | tsk
->thread
.fpexc_mode
;
1686 int get_fpexc_mode(struct task_struct
*tsk
, unsigned long adr
)
1690 if (tsk
->thread
.fpexc_mode
& PR_FP_EXC_SW_ENABLE
)
1692 if (cpu_has_feature(CPU_FTR_SPE
)) {
1694 * When the sticky exception bits are set
1695 * directly by userspace, it must call prctl
1696 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1697 * in the existing prctl settings) or
1698 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1699 * the bits being set). <fenv.h> functions
1700 * saving and restoring the whole
1701 * floating-point environment need to do so
1702 * anyway to restore the prctl settings from
1703 * the saved environment.
1705 tsk
->thread
.spefscr_last
= mfspr(SPRN_SPEFSCR
);
1706 val
= tsk
->thread
.fpexc_mode
;
1713 val
= __unpack_fe01(tsk
->thread
.fpexc_mode
);
1714 return put_user(val
, (unsigned int __user
*) adr
);
1717 int set_endian(struct task_struct
*tsk
, unsigned int val
)
1719 struct pt_regs
*regs
= tsk
->thread
.regs
;
1721 if ((val
== PR_ENDIAN_LITTLE
&& !cpu_has_feature(CPU_FTR_REAL_LE
)) ||
1722 (val
== PR_ENDIAN_PPC_LITTLE
&& !cpu_has_feature(CPU_FTR_PPC_LE
)))
1728 if (val
== PR_ENDIAN_BIG
)
1729 regs
->msr
&= ~MSR_LE
;
1730 else if (val
== PR_ENDIAN_LITTLE
|| val
== PR_ENDIAN_PPC_LITTLE
)
1731 regs
->msr
|= MSR_LE
;
1738 int get_endian(struct task_struct
*tsk
, unsigned long adr
)
1740 struct pt_regs
*regs
= tsk
->thread
.regs
;
1743 if (!cpu_has_feature(CPU_FTR_PPC_LE
) &&
1744 !cpu_has_feature(CPU_FTR_REAL_LE
))
1750 if (regs
->msr
& MSR_LE
) {
1751 if (cpu_has_feature(CPU_FTR_REAL_LE
))
1752 val
= PR_ENDIAN_LITTLE
;
1754 val
= PR_ENDIAN_PPC_LITTLE
;
1756 val
= PR_ENDIAN_BIG
;
1758 return put_user(val
, (unsigned int __user
*)adr
);
1761 int set_unalign_ctl(struct task_struct
*tsk
, unsigned int val
)
1763 tsk
->thread
.align_ctl
= val
;
1767 int get_unalign_ctl(struct task_struct
*tsk
, unsigned long adr
)
1769 return put_user(tsk
->thread
.align_ctl
, (unsigned int __user
*)adr
);
1772 static inline int valid_irq_stack(unsigned long sp
, struct task_struct
*p
,
1773 unsigned long nbytes
)
1775 unsigned long stack_page
;
1776 unsigned long cpu
= task_cpu(p
);
1779 * Avoid crashing if the stack has overflowed and corrupted
1780 * task_cpu(p), which is in the thread_info struct.
1782 if (cpu
< NR_CPUS
&& cpu_possible(cpu
)) {
1783 stack_page
= (unsigned long) hardirq_ctx
[cpu
];
1784 if (sp
>= stack_page
+ sizeof(struct thread_struct
)
1785 && sp
<= stack_page
+ THREAD_SIZE
- nbytes
)
1788 stack_page
= (unsigned long) softirq_ctx
[cpu
];
1789 if (sp
>= stack_page
+ sizeof(struct thread_struct
)
1790 && sp
<= stack_page
+ THREAD_SIZE
- nbytes
)
1796 int validate_sp(unsigned long sp
, struct task_struct
*p
,
1797 unsigned long nbytes
)
1799 unsigned long stack_page
= (unsigned long)task_stack_page(p
);
1801 if (sp
>= stack_page
+ sizeof(struct thread_struct
)
1802 && sp
<= stack_page
+ THREAD_SIZE
- nbytes
)
1805 return valid_irq_stack(sp
, p
, nbytes
);
1808 EXPORT_SYMBOL(validate_sp
);
1810 unsigned long get_wchan(struct task_struct
*p
)
1812 unsigned long ip
, sp
;
1815 if (!p
|| p
== current
|| p
->state
== TASK_RUNNING
)
1819 if (!validate_sp(sp
, p
, STACK_FRAME_OVERHEAD
))
1823 sp
= *(unsigned long *)sp
;
1824 if (!validate_sp(sp
, p
, STACK_FRAME_OVERHEAD
))
1827 ip
= ((unsigned long *)sp
)[STACK_FRAME_LR_SAVE
];
1828 if (!in_sched_functions(ip
))
1831 } while (count
++ < 16);
1835 static int kstack_depth_to_print
= CONFIG_PRINT_STACK_DEPTH
;
1837 void show_stack(struct task_struct
*tsk
, unsigned long *stack
)
1839 unsigned long sp
, ip
, lr
, newsp
;
1842 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1843 int curr_frame
= current
->curr_ret_stack
;
1844 extern void return_to_handler(void);
1845 unsigned long rth
= (unsigned long)return_to_handler
;
1848 sp
= (unsigned long) stack
;
1853 sp
= current_stack_pointer();
1855 sp
= tsk
->thread
.ksp
;
1859 printk("Call Trace:\n");
1861 if (!validate_sp(sp
, tsk
, STACK_FRAME_OVERHEAD
))
1864 stack
= (unsigned long *) sp
;
1866 ip
= stack
[STACK_FRAME_LR_SAVE
];
1867 if (!firstframe
|| ip
!= lr
) {
1868 printk("["REG
"] ["REG
"] %pS", sp
, ip
, (void *)ip
);
1869 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1870 if ((ip
== rth
) && curr_frame
>= 0) {
1872 (void *)current
->ret_stack
[curr_frame
].ret
);
1877 printk(" (unreliable)");
1883 * See if this is an exception frame.
1884 * We look for the "regshere" marker in the current frame.
1886 if (validate_sp(sp
, tsk
, STACK_INT_FRAME_SIZE
)
1887 && stack
[STACK_FRAME_MARKER
] == STACK_FRAME_REGS_MARKER
) {
1888 struct pt_regs
*regs
= (struct pt_regs
*)
1889 (sp
+ STACK_FRAME_OVERHEAD
);
1891 printk("--- interrupt: %lx at %pS\n LR = %pS\n",
1892 regs
->trap
, (void *)regs
->nip
, (void *)lr
);
1897 } while (count
++ < kstack_depth_to_print
);
1901 /* Called with hard IRQs off */
1902 void notrace
__ppc64_runlatch_on(void)
1904 struct thread_info
*ti
= current_thread_info();
1907 ctrl
= mfspr(SPRN_CTRLF
);
1908 ctrl
|= CTRL_RUNLATCH
;
1909 mtspr(SPRN_CTRLT
, ctrl
);
1911 ti
->local_flags
|= _TLF_RUNLATCH
;
1914 /* Called with hard IRQs off */
1915 void notrace
__ppc64_runlatch_off(void)
1917 struct thread_info
*ti
= current_thread_info();
1920 ti
->local_flags
&= ~_TLF_RUNLATCH
;
1922 ctrl
= mfspr(SPRN_CTRLF
);
1923 ctrl
&= ~CTRL_RUNLATCH
;
1924 mtspr(SPRN_CTRLT
, ctrl
);
1926 #endif /* CONFIG_PPC64 */
1928 unsigned long arch_align_stack(unsigned long sp
)
1930 if (!(current
->personality
& ADDR_NO_RANDOMIZE
) && randomize_va_space
)
1931 sp
-= get_random_int() & ~PAGE_MASK
;
1935 static inline unsigned long brk_rnd(void)
1937 unsigned long rnd
= 0;
1939 /* 8MB for 32bit, 1GB for 64bit */
1940 if (is_32bit_task())
1941 rnd
= (get_random_long() % (1UL<<(23-PAGE_SHIFT
)));
1943 rnd
= (get_random_long() % (1UL<<(30-PAGE_SHIFT
)));
1945 return rnd
<< PAGE_SHIFT
;
1948 unsigned long arch_randomize_brk(struct mm_struct
*mm
)
1950 unsigned long base
= mm
->brk
;
1953 #ifdef CONFIG_PPC_STD_MMU_64
1955 * If we are using 1TB segments and we are allowed to randomise
1956 * the heap, we can put it above 1TB so it is backed by a 1TB
1957 * segment. Otherwise the heap will be in the bottom 1TB
1958 * which always uses 256MB segments and this may result in a
1959 * performance penalty. We don't need to worry about radix. For
1960 * radix, mmu_highuser_ssize remains unchanged from 256MB.
1962 if (!is_32bit_task() && (mmu_highuser_ssize
== MMU_SEGSIZE_1T
))
1963 base
= max_t(unsigned long, mm
->brk
, 1UL << SID_SHIFT_1T
);
1966 ret
= PAGE_ALIGN(base
+ brk_rnd());