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staging: rtl8188eu: Remove unused function rtl8188eu_ps_func()
[linux-2.6/btrfs-unstable.git] / drivers / staging / rtl8188eu / hal / usb_halinit.c
blob141f85ae5618b2fd6ff8c5cf4aa7a2e313938aa5
1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 *
19 ******************************************************************************/
20 #define _HCI_HAL_INIT_C_
21
22 #include <osdep_service.h>
23 #include <drv_types.h>
24 #include <rtw_efuse.h>
25
26 #include <rtl8188e_hal.h>
27 #include <rtl8188e_led.h>
28 #include <rtw_iol.h>
29 #include <usb_ops.h>
30 #include <usb_hal.h>
31 #include <usb_osintf.h>
32
33 #define HAL_MAC_ENABLE 1
34 #define HAL_BB_ENABLE 1
35 #define HAL_RF_ENABLE 1
36
37 static void _ConfigNormalChipOutEP_8188E(struct adapter *adapt, u8 NumOutPipe)
38 {
39 struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
40
41 switch (NumOutPipe) {
42 case 3:
43 haldata->OutEpQueueSel = TX_SELE_HQ | TX_SELE_LQ | TX_SELE_NQ;
44 haldata->OutEpNumber = 3;
45 break;
46 case 2:
47 haldata->OutEpQueueSel = TX_SELE_HQ | TX_SELE_NQ;
48 haldata->OutEpNumber = 2;
49 break;
50 case 1:
51 haldata->OutEpQueueSel = TX_SELE_HQ;
52 haldata->OutEpNumber = 1;
53 break;
54 default:
55 break;
56 }
57 DBG_88E("%s OutEpQueueSel(0x%02x), OutEpNumber(%d)\n", __func__, haldata->OutEpQueueSel, haldata->OutEpNumber);
58 }
59
60 static bool HalUsbSetQueuePipeMapping8188EUsb(struct adapter *adapt, u8 NumInPipe, u8 NumOutPipe)
61 {
62 struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
63 bool result = false;
64
65 _ConfigNormalChipOutEP_8188E(adapt, NumOutPipe);
66
67 /* Normal chip with one IN and one OUT doesn't have interrupt IN EP. */
68 if (1 == haldata->OutEpNumber) {
69 if (1 != NumInPipe)
70 return result;
71 }
72
73 /* All config other than above support one Bulk IN and one Interrupt IN. */
74
75 result = Hal_MappingOutPipe(adapt, NumOutPipe);
76
77 return result;
78 }
79
80 static void rtl8188eu_interface_configure(struct adapter *adapt)
81 {
82 struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
83 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(adapt);
84
85 if (pdvobjpriv->ishighspeed)
86 haldata->UsbBulkOutSize = USB_HIGH_SPEED_BULK_SIZE;/* 512 bytes */
87 else
88 haldata->UsbBulkOutSize = USB_FULL_SPEED_BULK_SIZE;/* 64 bytes */
89
90 haldata->interfaceIndex = pdvobjpriv->InterfaceNumber;
91
92 haldata->UsbTxAggMode = 1;
93 haldata->UsbTxAggDescNum = 0x6; /* only 4 bits */
94
95 haldata->UsbRxAggMode = USB_RX_AGG_DMA;/* USB_RX_AGG_DMA; */
96 haldata->UsbRxAggBlockCount = 8; /* unit : 512b */
97 haldata->UsbRxAggBlockTimeout = 0x6;
98 haldata->UsbRxAggPageCount = 48; /* uint :128 b 0x0A; 10 = MAX_RX_DMA_BUFFER_SIZE/2/haldata->UsbBulkOutSize */
99 haldata->UsbRxAggPageTimeout = 0x4; /* 6, absolute time = 34ms/(2^6) */
100
101 HalUsbSetQueuePipeMapping8188EUsb(adapt,
102 pdvobjpriv->RtNumInPipes, pdvobjpriv->RtNumOutPipes);
103 }
104
105 static u32 rtl8188eu_InitPowerOn(struct adapter *adapt)
106 {
107 u16 value16;
108 /* HW Power on sequence */
109 struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
110 if (haldata->bMacPwrCtrlOn)
111 return _SUCCESS;
112
113 if (!HalPwrSeqCmdParsing(adapt, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, Rtl8188E_NIC_PWR_ON_FLOW)) {
114 DBG_88E(KERN_ERR "%s: run power on flow fail\n", __func__);
115 return _FAIL;
116 }
117
118 /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
119 /* Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31. */
120 rtw_write16(adapt, REG_CR, 0x00); /* suggseted by zhouzhou, by page, 20111230 */
121
122 /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
123 value16 = rtw_read16(adapt, REG_CR);
124 value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN
125 | PROTOCOL_EN | SCHEDULE_EN | ENSEC | CALTMR_EN);
126 /* for SDIO - Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31. */
127
128 rtw_write16(adapt, REG_CR, value16);
129 haldata->bMacPwrCtrlOn = true;
130
131 return _SUCCESS;
132 }
133
134 /* Shall USB interface init this? */
135 static void _InitInterrupt(struct adapter *Adapter)
136 {
137 u32 imr, imr_ex;
138 u8 usb_opt;
139 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
140
141 /* HISR write one to clear */
142 rtw_write32(Adapter, REG_HISR_88E, 0xFFFFFFFF);
143 /* HIMR - */
144 imr = IMR_PSTIMEOUT_88E | IMR_TBDER_88E | IMR_CPWM_88E | IMR_CPWM2_88E;
145 rtw_write32(Adapter, REG_HIMR_88E, imr);
146 haldata->IntrMask[0] = imr;
147
148 imr_ex = IMR_TXERR_88E | IMR_RXERR_88E | IMR_TXFOVW_88E | IMR_RXFOVW_88E;
149 rtw_write32(Adapter, REG_HIMRE_88E, imr_ex);
150 haldata->IntrMask[1] = imr_ex;
151
152 /* REG_USB_SPECIAL_OPTION - BIT(4) */
153 /* 0; Use interrupt endpoint to upload interrupt pkt */
154 /* 1; Use bulk endpoint to upload interrupt pkt, */
155 usb_opt = rtw_read8(Adapter, REG_USB_SPECIAL_OPTION);
156
157 if (!adapter_to_dvobj(Adapter)->ishighspeed)
158 usb_opt = usb_opt & (~INT_BULK_SEL);
159 else
160 usb_opt = usb_opt | (INT_BULK_SEL);
161
162 rtw_write8(Adapter, REG_USB_SPECIAL_OPTION, usb_opt);
163 }
164
165 static void _InitQueueReservedPage(struct adapter *Adapter)
166 {
167 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
168 struct registry_priv *pregistrypriv = &Adapter->registrypriv;
169 u32 numHQ = 0;
170 u32 numLQ = 0;
171 u32 numNQ = 0;
172 u32 numPubQ;
173 u32 value32;
174 u8 value8;
175 bool bWiFiConfig = pregistrypriv->wifi_spec;
176
177 if (bWiFiConfig) {
178 if (haldata->OutEpQueueSel & TX_SELE_HQ)
179 numHQ = 0x29;
180
181 if (haldata->OutEpQueueSel & TX_SELE_LQ)
182 numLQ = 0x1C;
183
184 /* NOTE: This step shall be proceed before writting REG_RQPN. */
185 if (haldata->OutEpQueueSel & TX_SELE_NQ)
186 numNQ = 0x1C;
187 value8 = (u8)_NPQ(numNQ);
188 rtw_write8(Adapter, REG_RQPN_NPQ, value8);
189
190 numPubQ = 0xA8 - numHQ - numLQ - numNQ;
191
192 /* TX DMA */
193 value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
194 rtw_write32(Adapter, REG_RQPN, value32);
195 } else {
196 rtw_write16(Adapter, REG_RQPN_NPQ, 0x0000);/* Just follow MP Team,??? Georgia 03/28 */
197 rtw_write16(Adapter, REG_RQPN_NPQ, 0x0d);
198 rtw_write32(Adapter, REG_RQPN, 0x808E000d);/* reserve 7 page for LPS */
199 }
200 }
201
202 static void _InitTxBufferBoundary(struct adapter *Adapter, u8 txpktbuf_bndy)
203 {
204 rtw_write8(Adapter, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
205 rtw_write8(Adapter, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
206 rtw_write8(Adapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
207 rtw_write8(Adapter, REG_TRXFF_BNDY, txpktbuf_bndy);
208 rtw_write8(Adapter, REG_TDECTRL+1, txpktbuf_bndy);
209 }
210
211 static void _InitPageBoundary(struct adapter *Adapter)
212 {
213 /* RX Page Boundary */
214 /* */
215 u16 rxff_bndy = MAX_RX_DMA_BUFFER_SIZE_88E-1;
216
217 rtw_write16(Adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
218 }
219
220 static void _InitNormalChipRegPriority(struct adapter *Adapter, u16 beQ,
221 u16 bkQ, u16 viQ, u16 voQ, u16 mgtQ,
222 u16 hiQ)
223 {
224 u16 value16 = (rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7);
225
226 value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
227 _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
228 _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
229
230 rtw_write16(Adapter, REG_TRXDMA_CTRL, value16);
231 }
232
233 static void _InitNormalChipOneOutEpPriority(struct adapter *Adapter)
234 {
235 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
236
237 u16 value = 0;
238 switch (haldata->OutEpQueueSel) {
239 case TX_SELE_HQ:
240 value = QUEUE_HIGH;
241 break;
242 case TX_SELE_LQ:
243 value = QUEUE_LOW;
244 break;
245 case TX_SELE_NQ:
246 value = QUEUE_NORMAL;
247 break;
248 default:
249 break;
250 }
251 _InitNormalChipRegPriority(Adapter, value, value, value, value,
252 value, value);
253 }
254
255 static void _InitNormalChipTwoOutEpPriority(struct adapter *Adapter)
256 {
257 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
258 struct registry_priv *pregistrypriv = &Adapter->registrypriv;
259 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
260 u16 valueHi = 0;
261 u16 valueLow = 0;
262
263 switch (haldata->OutEpQueueSel) {
264 case (TX_SELE_HQ | TX_SELE_LQ):
265 valueHi = QUEUE_HIGH;
266 valueLow = QUEUE_LOW;
267 break;
268 case (TX_SELE_NQ | TX_SELE_LQ):
269 valueHi = QUEUE_NORMAL;
270 valueLow = QUEUE_LOW;
271 break;
272 case (TX_SELE_HQ | TX_SELE_NQ):
273 valueHi = QUEUE_HIGH;
274 valueLow = QUEUE_NORMAL;
275 break;
276 default:
277 break;
278 }
279
280 if (!pregistrypriv->wifi_spec) {
281 beQ = valueLow;
282 bkQ = valueLow;
283 viQ = valueHi;
284 voQ = valueHi;
285 mgtQ = valueHi;
286 hiQ = valueHi;
287 } else {/* for WMM ,CONFIG_OUT_EP_WIFI_MODE */
288 beQ = valueLow;
289 bkQ = valueHi;
290 viQ = valueHi;
291 voQ = valueLow;
292 mgtQ = valueHi;
293 hiQ = valueHi;
294 }
295 _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
296 }
297
298 static void _InitNormalChipThreeOutEpPriority(struct adapter *Adapter)
299 {
300 struct registry_priv *pregistrypriv = &Adapter->registrypriv;
301 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
302
303 if (!pregistrypriv->wifi_spec) {/* typical setting */
304 beQ = QUEUE_LOW;
305 bkQ = QUEUE_LOW;
306 viQ = QUEUE_NORMAL;
307 voQ = QUEUE_HIGH;
308 mgtQ = QUEUE_HIGH;
309 hiQ = QUEUE_HIGH;
310 } else {/* for WMM */
311 beQ = QUEUE_LOW;
312 bkQ = QUEUE_NORMAL;
313 viQ = QUEUE_NORMAL;
314 voQ = QUEUE_HIGH;
315 mgtQ = QUEUE_HIGH;
316 hiQ = QUEUE_HIGH;
317 }
318 _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
319 }
320
321 static void _InitQueuePriority(struct adapter *Adapter)
322 {
323 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
324
325 switch (haldata->OutEpNumber) {
326 case 1:
327 _InitNormalChipOneOutEpPriority(Adapter);
328 break;
329 case 2:
330 _InitNormalChipTwoOutEpPriority(Adapter);
331 break;
332 case 3:
333 _InitNormalChipThreeOutEpPriority(Adapter);
334 break;
335 default:
336 break;
337 }
338 }
339
340 static void _InitNetworkType(struct adapter *Adapter)
341 {
342 u32 value32;
343
344 value32 = rtw_read32(Adapter, REG_CR);
345 /* TODO: use the other function to set network type */
346 value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP);
347
348 rtw_write32(Adapter, REG_CR, value32);
349 }
350
351 static void _InitTransferPageSize(struct adapter *Adapter)
352 {
353 /* Tx page size is always 128. */
354
355 u8 value8;
356 value8 = _PSRX(PBP_128) | _PSTX(PBP_128);
357 rtw_write8(Adapter, REG_PBP, value8);
358 }
359
360 static void _InitDriverInfoSize(struct adapter *Adapter, u8 drvInfoSize)
361 {
362 rtw_write8(Adapter, REG_RX_DRVINFO_SZ, drvInfoSize);
363 }
364
365 static void _InitWMACSetting(struct adapter *Adapter)
366 {
367 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
368
369 haldata->ReceiveConfig = RCR_AAP | RCR_APM | RCR_AM | RCR_AB |
370 RCR_CBSSID_DATA | RCR_CBSSID_BCN |
371 RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL |
372 RCR_APP_MIC | RCR_APP_PHYSTS;
373
374 /* some REG_RCR will be modified later by phy_ConfigMACWithHeaderFile() */
375 rtw_write32(Adapter, REG_RCR, haldata->ReceiveConfig);
376
377 /* Accept all multicast address */
378 rtw_write32(Adapter, REG_MAR, 0xFFFFFFFF);
379 rtw_write32(Adapter, REG_MAR + 4, 0xFFFFFFFF);
380 }
381
382 static void _InitAdaptiveCtrl(struct adapter *Adapter)
383 {
384 u16 value16;
385 u32 value32;
386
387 /* Response Rate Set */
388 value32 = rtw_read32(Adapter, REG_RRSR);
389 value32 &= ~RATE_BITMAP_ALL;
390 value32 |= RATE_RRSR_CCK_ONLY_1M;
391 rtw_write32(Adapter, REG_RRSR, value32);
392
393 /* CF-END Threshold */
394
395 /* SIFS (used in NAV) */
396 value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
397 rtw_write16(Adapter, REG_SPEC_SIFS, value16);
398
399 /* Retry Limit */
400 value16 = _LRL(0x30) | _SRL(0x30);
401 rtw_write16(Adapter, REG_RL, value16);
402 }
403
404 static void _InitEDCA(struct adapter *Adapter)
405 {
406 /* Set Spec SIFS (used in NAV) */
407 rtw_write16(Adapter, REG_SPEC_SIFS, 0x100a);
408 rtw_write16(Adapter, REG_MAC_SPEC_SIFS, 0x100a);
409
410 /* Set SIFS for CCK */
411 rtw_write16(Adapter, REG_SIFS_CTX, 0x100a);
412
413 /* Set SIFS for OFDM */
414 rtw_write16(Adapter, REG_SIFS_TRX, 0x100a);
415
416 /* TXOP */
417 rtw_write32(Adapter, REG_EDCA_BE_PARAM, 0x005EA42B);
418 rtw_write32(Adapter, REG_EDCA_BK_PARAM, 0x0000A44F);
419 rtw_write32(Adapter, REG_EDCA_VI_PARAM, 0x005EA324);
420 rtw_write32(Adapter, REG_EDCA_VO_PARAM, 0x002FA226);
421 }
422
423 static void _InitRDGSetting(struct adapter *Adapter)
424 {
425 rtw_write8(Adapter, REG_RD_CTRL, 0xFF);
426 rtw_write16(Adapter, REG_RD_NAV_NXT, 0x200);
427 rtw_write8(Adapter, REG_RD_RESP_PKT_TH, 0x05);
428 }
429
430 static void _InitRxSetting(struct adapter *Adapter)
431 {
432 rtw_write32(Adapter, REG_MACID, 0x87654321);
433 rtw_write32(Adapter, 0x0700, 0x87654321);
434 }
435
436 static void _InitRetryFunction(struct adapter *Adapter)
437 {
438 u8 value8;
439
440 value8 = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL);
441 value8 |= EN_AMPDU_RTY_NEW;
442 rtw_write8(Adapter, REG_FWHW_TXQ_CTRL, value8);
443
444 /* Set ACK timeout */
445 rtw_write8(Adapter, REG_ACKTO, 0x40);
446 }
447
448 /*-----------------------------------------------------------------------------
449 * Function: usb_AggSettingTxUpdate()
450 *
451 * Overview: Separate TX/RX parameters update independent for TP detection and
452 * dynamic TX/RX aggreagtion parameters update.
453 *
454 * Input: struct adapter *
455 *
456 * Output/Return: NONE
457 *
458 * Revised History:
459 * When Who Remark
460 * 12/10/2010 MHC Separate to smaller function.
461 *
462 *---------------------------------------------------------------------------*/
463 static void usb_AggSettingTxUpdate(struct adapter *Adapter)
464 {
465 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
466 u32 value32;
467
468 if (Adapter->registrypriv.wifi_spec)
469 haldata->UsbTxAggMode = false;
470
471 if (haldata->UsbTxAggMode) {
472 value32 = rtw_read32(Adapter, REG_TDECTRL);
473 value32 = value32 & ~(BLK_DESC_NUM_MASK << BLK_DESC_NUM_SHIFT);
474 value32 |= ((haldata->UsbTxAggDescNum & BLK_DESC_NUM_MASK) << BLK_DESC_NUM_SHIFT);
475
476 rtw_write32(Adapter, REG_TDECTRL, value32);
477 }
478 } /* usb_AggSettingTxUpdate */
479
480 /*-----------------------------------------------------------------------------
481 * Function: usb_AggSettingRxUpdate()
482 *
483 * Overview: Separate TX/RX parameters update independent for TP detection and
484 * dynamic TX/RX aggreagtion parameters update.
485 *
486 * Input: struct adapter *
487 *
488 * Output/Return: NONE
489 *
490 * Revised History:
491 * When Who Remark
492 * 12/10/2010 MHC Separate to smaller function.
493 *
494 *---------------------------------------------------------------------------*/
495 static void
496 usb_AggSettingRxUpdate(
497 struct adapter *Adapter
498 )
499 {
500 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
501 u8 valueDMA;
502 u8 valueUSB;
503
504 valueDMA = rtw_read8(Adapter, REG_TRXDMA_CTRL);
505 valueUSB = rtw_read8(Adapter, REG_USB_SPECIAL_OPTION);
506
507 switch (haldata->UsbRxAggMode) {
508 case USB_RX_AGG_DMA:
509 valueDMA |= RXDMA_AGG_EN;
510 valueUSB &= ~USB_AGG_EN;
511 break;
512 case USB_RX_AGG_USB:
513 valueDMA &= ~RXDMA_AGG_EN;
514 valueUSB |= USB_AGG_EN;
515 break;
516 case USB_RX_AGG_MIX:
517 valueDMA |= RXDMA_AGG_EN;
518 valueUSB |= USB_AGG_EN;
519 break;
520 case USB_RX_AGG_DISABLE:
521 default:
522 valueDMA &= ~RXDMA_AGG_EN;
523 valueUSB &= ~USB_AGG_EN;
524 break;
525 }
526
527 rtw_write8(Adapter, REG_TRXDMA_CTRL, valueDMA);
528 rtw_write8(Adapter, REG_USB_SPECIAL_OPTION, valueUSB);
529
530 switch (haldata->UsbRxAggMode) {
531 case USB_RX_AGG_DMA:
532 rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, haldata->UsbRxAggPageCount);
533 rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH+1, haldata->UsbRxAggPageTimeout);
534 break;
535 case USB_RX_AGG_USB:
536 rtw_write8(Adapter, REG_USB_AGG_TH, haldata->UsbRxAggBlockCount);
537 rtw_write8(Adapter, REG_USB_AGG_TO, haldata->UsbRxAggBlockTimeout);
538 break;
539 case USB_RX_AGG_MIX:
540 rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, haldata->UsbRxAggPageCount);
541 rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH+1, (haldata->UsbRxAggPageTimeout & 0x1F));/* 0x280[12:8] */
542 rtw_write8(Adapter, REG_USB_AGG_TH, haldata->UsbRxAggBlockCount);
543 rtw_write8(Adapter, REG_USB_AGG_TO, haldata->UsbRxAggBlockTimeout);
544 break;
545 case USB_RX_AGG_DISABLE:
546 default:
547 /* TODO: */
548 break;
549 }
550
551 switch (PBP_128) {
552 case PBP_128:
553 haldata->HwRxPageSize = 128;
554 break;
555 case PBP_64:
556 haldata->HwRxPageSize = 64;
557 break;
558 case PBP_256:
559 haldata->HwRxPageSize = 256;
560 break;
561 case PBP_512:
562 haldata->HwRxPageSize = 512;
563 break;
564 case PBP_1024:
565 haldata->HwRxPageSize = 1024;
566 break;
567 default:
568 break;
569 }
570 } /* usb_AggSettingRxUpdate */
571
572 static void InitUsbAggregationSetting(struct adapter *Adapter)
573 {
574 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
575
576 /* Tx aggregation setting */
577 usb_AggSettingTxUpdate(Adapter);
578
579 /* Rx aggregation setting */
580 usb_AggSettingRxUpdate(Adapter);
581
582 /* 201/12/10 MH Add for USB agg mode dynamic switch. */
583 haldata->UsbRxHighSpeedMode = false;
584 }
585
586 static void _InitBeaconParameters(struct adapter *Adapter)
587 {
588 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
589
590 rtw_write16(Adapter, REG_BCN_CTRL, 0x1010);
591
592 /* TODO: Remove these magic number */
593 rtw_write16(Adapter, REG_TBTT_PROHIBIT, 0x6404);/* ms */
594 rtw_write8(Adapter, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);/* 5ms */
595 rtw_write8(Adapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME); /* 2ms */
596
597 /* Suggested by designer timchen. Change beacon AIFS to the largest number */
598 /* beacause test chip does not contension before sending beacon. by tynli. 2009.11.03 */
599 rtw_write16(Adapter, REG_BCNTCFG, 0x660F);
600
601 haldata->RegBcnCtrlVal = rtw_read8(Adapter, REG_BCN_CTRL);
602 haldata->RegTxPause = rtw_read8(Adapter, REG_TXPAUSE);
603 haldata->RegFwHwTxQCtrl = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL+2);
604 haldata->RegReg542 = rtw_read8(Adapter, REG_TBTT_PROHIBIT+2);
605 haldata->RegCR_1 = rtw_read8(Adapter, REG_CR+1);
606 }
607
608 static void _BeaconFunctionEnable(struct adapter *Adapter,
609 bool Enable, bool Linked)
610 {
611 rtw_write8(Adapter, REG_BCN_CTRL, (BIT4 | BIT3 | BIT1));
612
613 rtw_write8(Adapter, REG_RD_CTRL+1, 0x6F);
614 }
615
616 /* Set CCK and OFDM Block "ON" */
617 static void _BBTurnOnBlock(struct adapter *Adapter)
618 {
619 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1);
620 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
621 }
622
623 enum {
624 Antenna_Lfet = 1,
625 Antenna_Right = 2,
626 };
627
628 static void _InitAntenna_Selection(struct adapter *Adapter)
629 {
630 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
631
632 if (haldata->AntDivCfg == 0)
633 return;
634 DBG_88E("==> %s ....\n", __func__);
635
636 rtw_write32(Adapter, REG_LEDCFG0, rtw_read32(Adapter, REG_LEDCFG0)|BIT23);
637 PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, BIT13, 0x01);
638
639 if (PHY_QueryBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300) == Antenna_A)
640 haldata->CurAntenna = Antenna_A;
641 else
642 haldata->CurAntenna = Antenna_B;
643 DBG_88E("%s,Cur_ant:(%x)%s\n", __func__, haldata->CurAntenna, (haldata->CurAntenna == Antenna_A) ? "Antenna_A" : "Antenna_B");
644 }
645
646 /*-----------------------------------------------------------------------------
647 * Function: HwSuspendModeEnable92Cu()
648 *
649 * Overview: HW suspend mode switch.
650 *
651 * Input: NONE
652 *
653 * Output: NONE
654 *
655 * Return: NONE
656 *
657 * Revised History:
658 * When Who Remark
659 * 08/23/2010 MHC HW suspend mode switch test..
660 *---------------------------------------------------------------------------*/
661 enum rt_rf_power_state RfOnOffDetect(struct adapter *adapt)
662 {
663 u8 val8;
664 enum rt_rf_power_state rfpowerstate = rf_off;
665
666 if (adapt->pwrctrlpriv.bHWPowerdown) {
667 val8 = rtw_read8(adapt, REG_HSISR);
668 DBG_88E("pwrdown, 0x5c(BIT7)=%02x\n", val8);
669 rfpowerstate = (val8 & BIT7) ? rf_off : rf_on;
670 } else { /* rf on/off */
671 rtw_write8(adapt, REG_MAC_PINMUX_CFG, rtw_read8(adapt, REG_MAC_PINMUX_CFG)&~(BIT3));
672 val8 = rtw_read8(adapt, REG_GPIO_IO_SEL);
673 DBG_88E("GPIO_IN=%02x\n", val8);
674 rfpowerstate = (val8 & BIT3) ? rf_on : rf_off;
675 }
676 return rfpowerstate;
677 } /* HalDetectPwrDownMode */
678
679 static u32 rtl8188eu_hal_init(struct adapter *Adapter)
680 {
681 u8 value8 = 0;
682 u16 value16;
683 u8 txpktbuf_bndy;
684 u32 status = _SUCCESS;
685 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
686 struct pwrctrl_priv *pwrctrlpriv = &Adapter->pwrctrlpriv;
687 struct registry_priv *pregistrypriv = &Adapter->registrypriv;
688 u32 init_start_time = jiffies;
689
690 #define HAL_INIT_PROFILE_TAG(stage) do {} while (0)
691
692
693 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BEGIN);
694
695 if (Adapter->pwrctrlpriv.bkeepfwalive) {
696
697 if (haldata->odmpriv.RFCalibrateInfo.bIQKInitialized) {
698 PHY_IQCalibrate_8188E(Adapter, true);
699 } else {
700 PHY_IQCalibrate_8188E(Adapter, false);
701 haldata->odmpriv.RFCalibrateInfo.bIQKInitialized = true;
702 }
703
704 ODM_TXPowerTrackingCheck(&haldata->odmpriv);
705 PHY_LCCalibrate_8188E(Adapter);
706
707 goto exit;
708 }
709
710 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PW_ON);
711 status = rtl8188eu_InitPowerOn(Adapter);
712 if (status == _FAIL) {
713 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init power on!\n"));
714 goto exit;
715 }
716
717 /* Save target channel */
718 haldata->CurrentChannel = 6;/* default set to 6 */
719
720 if (pwrctrlpriv->reg_rfoff) {
721 pwrctrlpriv->rf_pwrstate = rf_off;
722 }
723
724 /* 2010/08/09 MH We need to check if we need to turnon or off RF after detecting */
725 /* HW GPIO pin. Before PHY_RFConfig8192C. */
726 /* 2010/08/26 MH If Efuse does not support sective suspend then disable the function. */
727
728 if (!pregistrypriv->wifi_spec) {
729 txpktbuf_bndy = TX_PAGE_BOUNDARY_88E;
730 } else {
731 /* for WMM */
732 txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY_88E;
733 }
734
735 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC01);
736 _InitQueueReservedPage(Adapter);
737 _InitQueuePriority(Adapter);
738 _InitPageBoundary(Adapter);
739 _InitTransferPageSize(Adapter);
740
741 _InitTxBufferBoundary(Adapter, 0);
742
743 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW);
744 if (Adapter->registrypriv.mp_mode == 1) {
745 _InitRxSetting(Adapter);
746 Adapter->bFWReady = false;
747 haldata->fw_ractrl = false;
748 } else {
749 status = rtl8188e_FirmwareDownload(Adapter);
750
751 if (status != _SUCCESS) {
752 DBG_88E("%s: Download Firmware failed!!\n", __func__);
753 Adapter->bFWReady = false;
754 haldata->fw_ractrl = false;
755 return status;
756 } else {
757 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Initializeadapt8192CSdio(): Download Firmware Success!!\n"));
758 Adapter->bFWReady = true;
759 haldata->fw_ractrl = false;
760 }
761 }
762 rtl8188e_InitializeFirmwareVars(Adapter);
763
764 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MAC);
765 #if (HAL_MAC_ENABLE == 1)
766 status = PHY_MACConfig8188E(Adapter);
767 if (status == _FAIL) {
768 DBG_88E(" ### Failed to init MAC ......\n ");
769 goto exit;
770 }
771 #endif
772
773 /* */
774 /* d. Initialize BB related configurations. */
775 /* */
776 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BB);
777 #if (HAL_BB_ENABLE == 1)
778 status = PHY_BBConfig8188E(Adapter);
779 if (status == _FAIL) {
780 DBG_88E(" ### Failed to init BB ......\n ");
781 goto exit;
782 }
783 #endif
784
785 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_RF);
786 #if (HAL_RF_ENABLE == 1)
787 status = PHY_RFConfig8188E(Adapter);
788 if (status == _FAIL) {
789 DBG_88E(" ### Failed to init RF ......\n ");
790 goto exit;
791 }
792 #endif
793
794 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_EFUSE_PATCH);
795 status = rtl8188e_iol_efuse_patch(Adapter);
796 if (status == _FAIL) {
797 DBG_88E("%s rtl8188e_iol_efuse_patch failed\n", __func__);
798 goto exit;
799 }
800
801 _InitTxBufferBoundary(Adapter, txpktbuf_bndy);
802
803 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_LLTT);
804 status = InitLLTTable(Adapter, txpktbuf_bndy);
805 if (status == _FAIL) {
806 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init LLT table\n"));
807 goto exit;
808 }
809
810 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02);
811 /* Get Rx PHY status in order to report RSSI and others. */
812 _InitDriverInfoSize(Adapter, DRVINFO_SZ);
813
814 _InitInterrupt(Adapter);
815 hal_init_macaddr(Adapter);/* set mac_address */
816 _InitNetworkType(Adapter);/* set msr */
817 _InitWMACSetting(Adapter);
818 _InitAdaptiveCtrl(Adapter);
819 _InitEDCA(Adapter);
820 _InitRetryFunction(Adapter);
821 InitUsbAggregationSetting(Adapter);
822 _InitBeaconParameters(Adapter);
823 /* Init CR MACTXEN, MACRXEN after setting RxFF boundary REG_TRXFF_BNDY to patch */
824 /* Hw bug which Hw initials RxFF boundary size to a value which is larger than the real Rx buffer size in 88E. */
825 /* Enable MACTXEN/MACRXEN block */
826 value16 = rtw_read16(Adapter, REG_CR);
827 value16 |= (MACTXEN | MACRXEN);
828 rtw_write8(Adapter, REG_CR, value16);
829
830 if (haldata->bRDGEnable)
831 _InitRDGSetting(Adapter);
832
833 /* Enable TX Report */
834 /* Enable Tx Report Timer */
835 value8 = rtw_read8(Adapter, REG_TX_RPT_CTRL);
836 rtw_write8(Adapter, REG_TX_RPT_CTRL, (value8|BIT1|BIT0));
837 /* Set MAX RPT MACID */
838 rtw_write8(Adapter, REG_TX_RPT_CTRL+1, 2);/* FOR sta mode ,0: bc/mc ,1:AP */
839 /* Tx RPT Timer. Unit: 32us */
840 rtw_write16(Adapter, REG_TX_RPT_TIME, 0xCdf0);
841
842 rtw_write8(Adapter, REG_EARLY_MODE_CONTROL, 0);
843
844 rtw_write16(Adapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */
845 rtw_write16(Adapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */
846
847 /* Keep RfRegChnlVal for later use. */
848 haldata->RfRegChnlVal[0] = PHY_QueryRFReg(Adapter, (enum rf_radio_path)0, RF_CHNLBW, bRFRegOffsetMask);
849 haldata->RfRegChnlVal[1] = PHY_QueryRFReg(Adapter, (enum rf_radio_path)1, RF_CHNLBW, bRFRegOffsetMask);
850
851 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_TURN_ON_BLOCK);
852 _BBTurnOnBlock(Adapter);
853
854 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_SECURITY);
855 invalidate_cam_all(Adapter);
856
857 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC11);
858 /* 2010/12/17 MH We need to set TX power according to EFUSE content at first. */
859 PHY_SetTxPowerLevel8188E(Adapter, haldata->CurrentChannel);
860
861 /* Move by Neo for USB SS to below setp */
862 /* _RfPowerSave(Adapter); */
863
864 _InitAntenna_Selection(Adapter);
865
866 /* */
867 /* Disable BAR, suggested by Scott */
868 /* 2010.04.09 add by hpfan */
869 /* */
870 rtw_write32(Adapter, REG_BAR_MODE_CTRL, 0x0201ffff);
871
872 /* HW SEQ CTRL */
873 /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
874 rtw_write8(Adapter, REG_HWSEQ_CTRL, 0xFF);
875
876 if (pregistrypriv->wifi_spec)
877 rtw_write16(Adapter, REG_FAST_EDCA_CTRL, 0);
878
879 /* Nav limit , suggest by scott */
880 rtw_write8(Adapter, 0x652, 0x0);
881
882 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM);
883 rtl8188e_InitHalDm(Adapter);
884
885 if (Adapter->registrypriv.mp_mode == 1) {
886 Adapter->mppriv.channel = haldata->CurrentChannel;
887 MPT_InitializeAdapter(Adapter, Adapter->mppriv.channel);
888 } else {
889 /* 2010/08/11 MH Merge from 8192SE for Minicard init. We need to confirm current radio status */
890 /* and then decide to enable RF or not.!!!??? For Selective suspend mode. We may not */
891 /* call initstruct adapter. May cause some problem?? */
892 /* Fix the bug that Hw/Sw radio off before S3/S4, the RF off action will not be executed */
893 /* in MgntActSet_RF_State() after wake up, because the value of haldata->eRFPowerState */
894 /* is the same as eRfOff, we should change it to eRfOn after we config RF parameters. */
895 /* Added by tynli. 2010.03.30. */
896 pwrctrlpriv->rf_pwrstate = rf_on;
897
898 /* enable Tx report. */
899 rtw_write8(Adapter, REG_FWHW_TXQ_CTRL+1, 0x0F);
900
901 /* Suggested by SD1 pisa. Added by tynli. 2011.10.21. */
902 rtw_write8(Adapter, REG_EARLY_MODE_CONTROL+3, 0x01);/* Pretx_en, for WEP/TKIP SEC */
903
904 /* tynli_test_tx_report. */
905 rtw_write16(Adapter, REG_TX_RPT_TIME, 0x3DF0);
906
907 /* enable tx DMA to drop the redundate data of packet */
908 rtw_write16(Adapter, REG_TXDMA_OFFSET_CHK, (rtw_read16(Adapter, REG_TXDMA_OFFSET_CHK) | DROP_DATA_EN));
909
910 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_IQK);
911 /* 2010/08/26 MH Merge from 8192CE. */
912 if (pwrctrlpriv->rf_pwrstate == rf_on) {
913 if (haldata->odmpriv.RFCalibrateInfo.bIQKInitialized) {
914 PHY_IQCalibrate_8188E(Adapter, true);
915 } else {
916 PHY_IQCalibrate_8188E(Adapter, false);
917 haldata->odmpriv.RFCalibrateInfo.bIQKInitialized = true;
918 }
919
920 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_PW_TRACK);
921
922 ODM_TXPowerTrackingCheck(&haldata->odmpriv);
923
924 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_LCK);
925 PHY_LCCalibrate_8188E(Adapter);
926 }
927 }
928
929 /* HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PABIAS); */
930 /* _InitPABias(Adapter); */
931 rtw_write8(Adapter, REG_USB_HRPWM, 0);
932
933 /* ack for xmit mgmt frames. */
934 rtw_write32(Adapter, REG_FWHW_TXQ_CTRL, rtw_read32(Adapter, REG_FWHW_TXQ_CTRL)|BIT(12));
935
936 exit:
937 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_END);
938
939 DBG_88E("%s in %dms\n", __func__, rtw_get_passing_time_ms(init_start_time));
940
941
942 return status;
943 }
944
945 static void CardDisableRTL8188EU(struct adapter *Adapter)
946 {
947 u8 val8;
948 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
949
950 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("CardDisableRTL8188EU\n"));
951
952 /* Stop Tx Report Timer. 0x4EC[Bit1]=b'0 */
953 val8 = rtw_read8(Adapter, REG_TX_RPT_CTRL);
954 rtw_write8(Adapter, REG_TX_RPT_CTRL, val8&(~BIT1));
955
956 /* stop rx */
957 rtw_write8(Adapter, REG_CR, 0x0);
958
959 /* Run LPS WL RFOFF flow */
960 HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, Rtl8188E_NIC_LPS_ENTER_FLOW);
961
962 /* 2. 0x1F[7:0] = 0 turn off RF */
963
964 val8 = rtw_read8(Adapter, REG_MCUFWDL);
965 if ((val8 & RAM_DL_SEL) && Adapter->bFWReady) { /* 8051 RAM code */
966 /* Reset MCU 0x2[10]=0. */
967 val8 = rtw_read8(Adapter, REG_SYS_FUNC_EN+1);
968 val8 &= ~BIT(2); /* 0x2[10], FEN_CPUEN */
969 rtw_write8(Adapter, REG_SYS_FUNC_EN+1, val8);
970 }
971
972 /* reset MCU ready status */
973 rtw_write8(Adapter, REG_MCUFWDL, 0);
974
975 /* YJ,add,111212 */
976 /* Disable 32k */
977 val8 = rtw_read8(Adapter, REG_32K_CTRL);
978 rtw_write8(Adapter, REG_32K_CTRL, val8&(~BIT0));
979
980 /* Card disable power action flow */
981 HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, Rtl8188E_NIC_DISABLE_FLOW);
982
983 /* Reset MCU IO Wrapper */
984 val8 = rtw_read8(Adapter, REG_RSV_CTRL+1);
985 rtw_write8(Adapter, REG_RSV_CTRL+1, (val8&(~BIT3)));
986 val8 = rtw_read8(Adapter, REG_RSV_CTRL+1);
987 rtw_write8(Adapter, REG_RSV_CTRL+1, val8|BIT3);
988
989 /* YJ,test add, 111207. For Power Consumption. */
990 val8 = rtw_read8(Adapter, GPIO_IN);
991 rtw_write8(Adapter, GPIO_OUT, val8);
992 rtw_write8(Adapter, GPIO_IO_SEL, 0xFF);/* Reg0x46 */
993
994 val8 = rtw_read8(Adapter, REG_GPIO_IO_SEL);
995 rtw_write8(Adapter, REG_GPIO_IO_SEL, (val8<<4));
996 val8 = rtw_read8(Adapter, REG_GPIO_IO_SEL+1);
997 rtw_write8(Adapter, REG_GPIO_IO_SEL+1, val8|0x0F);/* Reg0x43 */
998 rtw_write32(Adapter, REG_BB_PAD_CTRL, 0x00080808);/* set LNA ,TRSW,EX_PA Pin to output mode */
999 haldata->bMacPwrCtrlOn = false;
1000 Adapter->bFWReady = false;
1001 }
1002 static void rtl8192cu_hw_power_down(struct adapter *adapt)
1003 {
1004 /* 2010/-8/09 MH For power down module, we need to enable register block contrl reg at 0x1c. */
1005 /* Then enable power down control bit of register 0x04 BIT4 and BIT15 as 1. */
1006
1007 /* Enable register area 0x0-0xc. */
1008 rtw_write8(adapt, REG_RSV_CTRL, 0x0);
1009 rtw_write16(adapt, REG_APS_FSMCO, 0x8812);
1010 }
1011
1012 static u32 rtl8188eu_hal_deinit(struct adapter *Adapter)
1013 {
1014
1015 DBG_88E("==> %s\n", __func__);
1016
1017 rtw_write32(Adapter, REG_HIMR_88E, IMR_DISABLED_88E);
1018 rtw_write32(Adapter, REG_HIMRE_88E, IMR_DISABLED_88E);
1019
1020 DBG_88E("bkeepfwalive(%x)\n", Adapter->pwrctrlpriv.bkeepfwalive);
1021 if (Adapter->pwrctrlpriv.bkeepfwalive) {
1022 if ((Adapter->pwrctrlpriv.bHWPwrPindetect) && (Adapter->pwrctrlpriv.bHWPowerdown))
1023 rtl8192cu_hw_power_down(Adapter);
1024 } else {
1025 if (Adapter->hw_init_completed) {
1026 CardDisableRTL8188EU(Adapter);
1027
1028 if ((Adapter->pwrctrlpriv.bHWPwrPindetect) && (Adapter->pwrctrlpriv.bHWPowerdown))
1029 rtl8192cu_hw_power_down(Adapter);
1030 }
1031 }
1032 return _SUCCESS;
1033 }
1034
1035 static unsigned int rtl8188eu_inirp_init(struct adapter *Adapter)
1036 {
1037 u8 i;
1038 struct recv_buf *precvbuf;
1039 uint status;
1040 struct intf_hdl *pintfhdl = &Adapter->iopriv.intf;
1041 struct recv_priv *precvpriv = &(Adapter->recvpriv);
1042 u32 (*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
1043
1044
1045 _read_port = pintfhdl->io_ops._read_port;
1046
1047 status = _SUCCESS;
1048
1049 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1050 ("===> usb_inirp_init\n"));
1051
1052 precvpriv->ff_hwaddr = RECV_BULK_IN_ADDR;
1053
1054 /* issue Rx irp to receive data */
1055 precvbuf = (struct recv_buf *)precvpriv->precv_buf;
1056 for (i = 0; i < NR_RECVBUFF; i++) {
1057 if (_read_port(pintfhdl, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf) == false) {
1058 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("usb_rx_init: usb_read_port error\n"));
1059 status = _FAIL;
1060 goto exit;
1061 }
1062
1063 precvbuf++;
1064 precvpriv->free_recv_buf_queue_cnt--;
1065 }
1066
1067 exit:
1068
1069 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("<=== usb_inirp_init\n"));
1070
1071
1072 return status;
1073 }
1074
1075 static unsigned int rtl8188eu_inirp_deinit(struct adapter *Adapter)
1076 {
1077 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("\n ===> usb_rx_deinit\n"));
1078
1079 rtw_read_port_cancel(Adapter);
1080
1081 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("\n <=== usb_rx_deinit\n"));
1082
1083 return _SUCCESS;
1084 }
1085
1086 /* */
1087 /* */
1088 /* EEPROM/EFUSE Content Parsing */
1089 /* */
1090 /* */
1091 static void Hal_EfuseParsePIDVID_8188EU(struct adapter *adapt, u8 *hwinfo, bool AutoLoadFail)
1092 {
1093 struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
1094
1095 if (!AutoLoadFail) {
1096 /* VID, PID */
1097 haldata->EEPROMVID = EF2BYTE(*(__le16 *)&hwinfo[EEPROM_VID_88EU]);
1098 haldata->EEPROMPID = EF2BYTE(*(__le16 *)&hwinfo[EEPROM_PID_88EU]);
1099
1100 /* Customer ID, 0x00 and 0xff are reserved for Realtek. */
1101 haldata->EEPROMCustomerID = *(u8 *)&hwinfo[EEPROM_CUSTOMERID_88E];
1102 haldata->EEPROMSubCustomerID = EEPROM_Default_SubCustomerID;
1103 } else {
1104 haldata->EEPROMVID = EEPROM_Default_VID;
1105 haldata->EEPROMPID = EEPROM_Default_PID;
1106
1107 /* Customer ID, 0x00 and 0xff are reserved for Realtek. */
1108 haldata->EEPROMCustomerID = EEPROM_Default_CustomerID;
1109 haldata->EEPROMSubCustomerID = EEPROM_Default_SubCustomerID;
1110 }
1111
1112 DBG_88E("VID = 0x%04X, PID = 0x%04X\n", haldata->EEPROMVID, haldata->EEPROMPID);
1113 DBG_88E("Customer ID: 0x%02X, SubCustomer ID: 0x%02X\n", haldata->EEPROMCustomerID, haldata->EEPROMSubCustomerID);
1114 }
1115
1116 static void Hal_EfuseParseMACAddr_8188EU(struct adapter *adapt, u8 *hwinfo, bool AutoLoadFail)
1117 {
1118 u16 i;
1119 u8 sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x81, 0x88, 0x02};
1120 struct eeprom_priv *eeprom = GET_EEPROM_EFUSE_PRIV(adapt);
1121
1122 if (AutoLoadFail) {
1123 for (i = 0; i < 6; i++)
1124 eeprom->mac_addr[i] = sMacAddr[i];
1125 } else {
1126 /* Read Permanent MAC address */
1127 memcpy(eeprom->mac_addr, &hwinfo[EEPROM_MAC_ADDR_88EU], ETH_ALEN);
1128 }
1129 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_,
1130 ("Hal_EfuseParseMACAddr_8188EU: Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n",
1131 eeprom->mac_addr[0], eeprom->mac_addr[1],
1132 eeprom->mac_addr[2], eeprom->mac_addr[3],
1133 eeprom->mac_addr[4], eeprom->mac_addr[5]));
1134 }
1135
1136 static void
1137 readAdapterInfo_8188EU(
1138 struct adapter *adapt
1139 )
1140 {
1141 struct eeprom_priv *eeprom = GET_EEPROM_EFUSE_PRIV(adapt);
1142
1143 /* parse the eeprom/efuse content */
1144 Hal_EfuseParseIDCode88E(adapt, eeprom->efuse_eeprom_data);
1145 Hal_EfuseParsePIDVID_8188EU(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1146 Hal_EfuseParseMACAddr_8188EU(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1147
1148 Hal_ReadPowerSavingMode88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1149 Hal_ReadTxPowerInfo88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1150 Hal_EfuseParseEEPROMVer88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1151 rtl8188e_EfuseParseChnlPlan(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1152 Hal_EfuseParseXtal_8188E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1153 Hal_EfuseParseCustomerID88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1154 Hal_ReadAntennaDiversity88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1155 Hal_EfuseParseBoardType88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1156 Hal_ReadThermalMeter_88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1157
1158 /* */
1159 /* The following part initialize some vars by PG info. */
1160 /* */
1161 Hal_InitChannelPlan(adapt);
1162 }
1163
1164 static void _ReadPROMContent(
1165 struct adapter *Adapter
1166 )
1167 {
1168 struct eeprom_priv *eeprom = GET_EEPROM_EFUSE_PRIV(Adapter);
1169 u8 eeValue;
1170
1171 /* check system boot selection */
1172 eeValue = rtw_read8(Adapter, REG_9346CR);
1173 eeprom->EepromOrEfuse = (eeValue & BOOT_FROM_EEPROM) ? true : false;
1174 eeprom->bautoload_fail_flag = (eeValue & EEPROM_EN) ? false : true;
1175
1176 DBG_88E("Boot from %s, Autoload %s !\n", (eeprom->EepromOrEfuse ? "EEPROM" : "EFUSE"),
1177 (eeprom->bautoload_fail_flag ? "Fail" : "OK"));
1178
1179 Hal_InitPGData88E(Adapter);
1180 readAdapterInfo_8188EU(Adapter);
1181 }
1182
1183 static void _ReadRFType(struct adapter *Adapter)
1184 {
1185 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
1186
1187 haldata->rf_chip = RF_6052;
1188 }
1189
1190 static int _ReadAdapterInfo8188EU(struct adapter *Adapter)
1191 {
1192 u32 start = jiffies;
1193
1194 MSG_88E("====> %s\n", __func__);
1195
1196 _ReadRFType(Adapter);/* rf_chip -> _InitRFType() */
1197 _ReadPROMContent(Adapter);
1198
1199 MSG_88E("<==== %s in %d ms\n", __func__, rtw_get_passing_time_ms(start));
1200
1201 return _SUCCESS;
1202 }
1203
1204 static void ReadAdapterInfo8188EU(struct adapter *Adapter)
1205 {
1206 /* Read EEPROM size before call any EEPROM function */
1207 Adapter->EepromAddressSize = GetEEPROMSize8188E(Adapter);
1208
1209 _ReadAdapterInfo8188EU(Adapter);
1210 }
1211
1212 #define GPIO_DEBUG_PORT_NUM 0
1213 static void rtl8192cu_trigger_gpio_0(struct adapter *adapt)
1214 {
1215 }
1216
1217 static void ResumeTxBeacon(struct adapter *adapt)
1218 {
1219 struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
1220
1221 /* 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value */
1222 /* which should be read from register to a global variable. */
1223
1224 rtw_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl) | BIT6);
1225 haldata->RegFwHwTxQCtrl |= BIT6;
1226 rtw_write8(adapt, REG_TBTT_PROHIBIT+1, 0xff);
1227 haldata->RegReg542 |= BIT0;
1228 rtw_write8(adapt, REG_TBTT_PROHIBIT+2, haldata->RegReg542);
1229 }
1230
1231 static void StopTxBeacon(struct adapter *adapt)
1232 {
1233 struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
1234
1235 /* 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value */
1236 /* which should be read from register to a global variable. */
1237
1238 rtw_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl) & (~BIT6));
1239 haldata->RegFwHwTxQCtrl &= (~BIT6);
1240 rtw_write8(adapt, REG_TBTT_PROHIBIT+1, 0x64);
1241 haldata->RegReg542 &= ~(BIT0);
1242 rtw_write8(adapt, REG_TBTT_PROHIBIT+2, haldata->RegReg542);
1243
1244 /* todo: CheckFwRsvdPageContent(Adapter); 2010.06.23. Added by tynli. */
1245 }
1246
1247 static void hw_var_set_opmode(struct adapter *Adapter, u8 variable, u8 *val)
1248 {
1249 u8 val8;
1250 u8 mode = *((u8 *)val);
1251
1252 /* disable Port0 TSF update */
1253 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));
1254
1255 /* set net_type */
1256 val8 = rtw_read8(Adapter, MSR)&0x0c;
1257 val8 |= mode;
1258 rtw_write8(Adapter, MSR, val8);
1259
1260 DBG_88E("%s()-%d mode = %d\n", __func__, __LINE__, mode);
1261
1262 if ((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) {
1263 StopTxBeacon(Adapter);
1264
1265 rtw_write8(Adapter, REG_BCN_CTRL, 0x19);/* disable atim wnd */
1266 } else if ((mode == _HW_STATE_ADHOC_)) {
1267 ResumeTxBeacon(Adapter);
1268 rtw_write8(Adapter, REG_BCN_CTRL, 0x1a);
1269 } else if (mode == _HW_STATE_AP_) {
1270 ResumeTxBeacon(Adapter);
1271
1272 rtw_write8(Adapter, REG_BCN_CTRL, 0x12);
1273
1274 /* Set RCR */
1275 rtw_write32(Adapter, REG_RCR, 0x7000208e);/* CBSSID_DATA must set to 0,reject ICV_ERR packet */
1276 /* enable to rx data frame */
1277 rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
1278 /* enable to rx ps-poll */
1279 rtw_write16(Adapter, REG_RXFLTMAP1, 0x0400);
1280
1281 /* Beacon Control related register for first time */
1282 rtw_write8(Adapter, REG_BCNDMATIM, 0x02); /* 2ms */
1283
1284 rtw_write8(Adapter, REG_ATIMWND, 0x0a); /* 10ms */
1285 rtw_write16(Adapter, REG_BCNTCFG, 0x00);
1286 rtw_write16(Adapter, REG_TBTT_PROHIBIT, 0xff04);
1287 rtw_write16(Adapter, REG_TSFTR_SYN_OFFSET, 0x7fff);/* +32767 (~32ms) */
1288
1289 /* reset TSF */
1290 rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(0));
1291
1292 /* BIT3 - If set 0, hw will clr bcnq when tx becon ok/fail or port 0 */
1293 rtw_write8(Adapter, REG_MBID_NUM, rtw_read8(Adapter, REG_MBID_NUM) | BIT(3) | BIT(4));
1294
1295 /* enable BCN0 Function for if1 */
1296 /* don't enable update TSF0 for if1 (due to TSF update when beacon/probe rsp are received) */
1297 rtw_write8(Adapter, REG_BCN_CTRL, (DIS_TSF_UDT0_NORMAL_CHIP|EN_BCN_FUNCTION | BIT(1)));
1298
1299 /* dis BCN1 ATIM WND if if2 is station */
1300 rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1) | BIT(0));
1301 }
1302 }
1303
1304 static void hw_var_set_macaddr(struct adapter *Adapter, u8 variable, u8 *val)
1305 {
1306 u8 idx = 0;
1307 u32 reg_macid;
1308
1309 reg_macid = REG_MACID;
1310
1311 for (idx = 0; idx < 6; idx++)
1312 rtw_write8(Adapter, (reg_macid+idx), val[idx]);
1313 }
1314
1315 static void hw_var_set_bssid(struct adapter *Adapter, u8 variable, u8 *val)
1316 {
1317 u8 idx = 0;
1318 u32 reg_bssid;
1319
1320 reg_bssid = REG_BSSID;
1321
1322 for (idx = 0; idx < 6; idx++)
1323 rtw_write8(Adapter, (reg_bssid+idx), val[idx]);
1324 }
1325
1326 static void hw_var_set_bcn_func(struct adapter *Adapter, u8 variable, u8 *val)
1327 {
1328 u32 bcn_ctrl_reg;
1329
1330 bcn_ctrl_reg = REG_BCN_CTRL;
1331
1332 if (*((u8 *)val))
1333 rtw_write8(Adapter, bcn_ctrl_reg, (EN_BCN_FUNCTION | EN_TXBCN_RPT));
1334 else
1335 rtw_write8(Adapter, bcn_ctrl_reg, rtw_read8(Adapter, bcn_ctrl_reg)&(~(EN_BCN_FUNCTION | EN_TXBCN_RPT)));
1336 }
1337
1338 static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8 *val)
1339 {
1340 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
1341 struct dm_priv *pdmpriv = &haldata->dmpriv;
1342 struct odm_dm_struct *podmpriv = &haldata->odmpriv;
1343
1344 switch (variable) {
1345 case HW_VAR_MEDIA_STATUS:
1346 {
1347 u8 val8;
1348
1349 val8 = rtw_read8(Adapter, MSR)&0x0c;
1350 val8 |= *((u8 *)val);
1351 rtw_write8(Adapter, MSR, val8);
1352 }
1353 break;
1354 case HW_VAR_MEDIA_STATUS1:
1355 {
1356 u8 val8;
1357
1358 val8 = rtw_read8(Adapter, MSR) & 0x03;
1359 val8 |= *((u8 *)val) << 2;
1360 rtw_write8(Adapter, MSR, val8);
1361 }
1362 break;
1363 case HW_VAR_SET_OPMODE:
1364 hw_var_set_opmode(Adapter, variable, val);
1365 break;
1366 case HW_VAR_MAC_ADDR:
1367 hw_var_set_macaddr(Adapter, variable, val);
1368 break;
1369 case HW_VAR_BSSID:
1370 hw_var_set_bssid(Adapter, variable, val);
1371 break;
1372 case HW_VAR_BASIC_RATE:
1373 {
1374 u16 BrateCfg = 0;
1375 u8 RateIndex = 0;
1376
1377 /* 2007.01.16, by Emily */
1378 /* Select RRSR (in Legacy-OFDM and CCK) */
1379 /* For 8190, we select only 24M, 12M, 6M, 11M, 5.5M, 2M, and 1M from the Basic rate. */
1380 /* We do not use other rates. */
1381 HalSetBrateCfg(Adapter, val, &BrateCfg);
1382 DBG_88E("HW_VAR_BASIC_RATE: BrateCfg(%#x)\n", BrateCfg);
1383
1384 /* 2011.03.30 add by Luke Lee */
1385 /* CCK 2M ACK should be disabled for some BCM and Atheros AP IOT */
1386 /* because CCK 2M has poor TXEVM */
1387 /* CCK 5.5M & 11M ACK should be enabled for better performance */
1388
1389 BrateCfg = (BrateCfg | 0xd) & 0x15d;
1390 haldata->BasicRateSet = BrateCfg;
1391
1392 BrateCfg |= 0x01; /* default enable 1M ACK rate */
1393 /* Set RRSR rate table. */
1394 rtw_write8(Adapter, REG_RRSR, BrateCfg & 0xff);
1395 rtw_write8(Adapter, REG_RRSR+1, (BrateCfg >> 8) & 0xff);
1396 rtw_write8(Adapter, REG_RRSR+2, rtw_read8(Adapter, REG_RRSR+2)&0xf0);
1397
1398 /* Set RTS initial rate */
1399 while (BrateCfg > 0x1) {
1400 BrateCfg = (BrateCfg >> 1);
1401 RateIndex++;
1402 }
1403 /* Ziv - Check */
1404 rtw_write8(Adapter, REG_INIRTS_RATE_SEL, RateIndex);
1405 }
1406 break;
1407 case HW_VAR_TXPAUSE:
1408 rtw_write8(Adapter, REG_TXPAUSE, *((u8 *)val));
1409 break;
1410 case HW_VAR_BCN_FUNC:
1411 hw_var_set_bcn_func(Adapter, variable, val);
1412 break;
1413 case HW_VAR_CORRECT_TSF:
1414 {
1415 u64 tsf;
1416 struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
1417 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
1418
1419 tsf = pmlmeext->TSFValue - rtw_modular64(pmlmeext->TSFValue, (pmlmeinfo->bcn_interval*1024)) - 1024; /* us */
1420
1421 if (((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
1422 StopTxBeacon(Adapter);
1423
1424 /* disable related TSF function */
1425 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(3)));
1426
1427 rtw_write32(Adapter, REG_TSFTR, tsf);
1428 rtw_write32(Adapter, REG_TSFTR+4, tsf>>32);
1429
1430 /* enable related TSF function */
1431 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(3));
1432
1433 if (((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
1434 ResumeTxBeacon(Adapter);
1435 }
1436 break;
1437 case HW_VAR_CHECK_BSSID:
1438 if (*((u8 *)val)) {
1439 rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN);
1440 } else {
1441 u32 val32;
1442
1443 val32 = rtw_read32(Adapter, REG_RCR);
1444
1445 val32 &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1446
1447 rtw_write32(Adapter, REG_RCR, val32);
1448 }
1449 break;
1450 case HW_VAR_MLME_DISCONNECT:
1451 /* Set RCR to not to receive data frame when NO LINK state */
1452 /* reject all data frames */
1453 rtw_write16(Adapter, REG_RXFLTMAP2, 0x00);
1454
1455 /* reset TSF */
1456 rtw_write8(Adapter, REG_DUAL_TSF_RST, (BIT(0)|BIT(1)));
1457
1458 /* disable update TSF */
1459 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));
1460 break;
1461 case HW_VAR_MLME_SITESURVEY:
1462 if (*((u8 *)val)) { /* under sitesurvey */
1463 /* config RCR to receive different BSSID & not to receive data frame */
1464 u32 v = rtw_read32(Adapter, REG_RCR);
1465 v &= ~(RCR_CBSSID_BCN);
1466 rtw_write32(Adapter, REG_RCR, v);
1467 /* reject all data frame */
1468 rtw_write16(Adapter, REG_RXFLTMAP2, 0x00);
1469
1470 /* disable update TSF */
1471 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));
1472 } else { /* sitesurvey done */
1473 struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
1474 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
1475
1476 if ((is_client_associated_to_ap(Adapter)) ||
1477 ((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE)) {
1478 /* enable to rx data frame */
1479 rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
1480
1481 /* enable update TSF */
1482 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
1483 } else if ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) {
1484 rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
1485 /* enable update TSF */
1486 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
1487 }
1488 if ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) {
1489 rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_BCN);
1490 } else {
1491 if (Adapter->in_cta_test) {
1492 u32 v = rtw_read32(Adapter, REG_RCR);
1493 v &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);/* RCR_ADF */
1494 rtw_write32(Adapter, REG_RCR, v);
1495 } else {
1496 rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_BCN);
1497 }
1498 }
1499 }
1500 break;
1501 case HW_VAR_MLME_JOIN:
1502 {
1503 u8 RetryLimit = 0x30;
1504 u8 type = *((u8 *)val);
1505 struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
1506
1507 if (type == 0) { /* prepare to join */
1508 /* enable to rx data frame.Accept all data frame */
1509 rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
1510
1511 if (Adapter->in_cta_test) {
1512 u32 v = rtw_read32(Adapter, REG_RCR);
1513 v &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);/* RCR_ADF */
1514 rtw_write32(Adapter, REG_RCR, v);
1515 } else {
1516 rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN);
1517 }
1518
1519 if (check_fwstate(pmlmepriv, WIFI_STATION_STATE))
1520 RetryLimit = (haldata->CustomerID == RT_CID_CCX) ? 7 : 48;
1521 else /* Ad-hoc Mode */
1522 RetryLimit = 0x7;
1523 } else if (type == 1) {
1524 /* joinbss_event call back when join res < 0 */
1525 rtw_write16(Adapter, REG_RXFLTMAP2, 0x00);
1526 } else if (type == 2) {
1527 /* sta add event call back */
1528 /* enable update TSF */
1529 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
1530
1531 if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE))
1532 RetryLimit = 0x7;
1533 }
1534 rtw_write16(Adapter, REG_RL, RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT);
1535 }
1536 break;
1537 case HW_VAR_BEACON_INTERVAL:
1538 rtw_write16(Adapter, REG_BCN_INTERVAL, *((u16 *)val));
1539 break;
1540 case HW_VAR_SLOT_TIME:
1541 {
1542 u8 u1bAIFS, aSifsTime;
1543 struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
1544 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
1545
1546 rtw_write8(Adapter, REG_SLOT, val[0]);
1547
1548 if (pmlmeinfo->WMM_enable == 0) {
1549 if (pmlmeext->cur_wireless_mode == WIRELESS_11B)
1550 aSifsTime = 10;
1551 else
1552 aSifsTime = 16;
1553
1554 u1bAIFS = aSifsTime + (2 * pmlmeinfo->slotTime);
1555
1556 /* <Roger_EXP> Temporary removed, 2008.06.20. */
1557 rtw_write8(Adapter, REG_EDCA_VO_PARAM, u1bAIFS);
1558 rtw_write8(Adapter, REG_EDCA_VI_PARAM, u1bAIFS);
1559 rtw_write8(Adapter, REG_EDCA_BE_PARAM, u1bAIFS);
1560 rtw_write8(Adapter, REG_EDCA_BK_PARAM, u1bAIFS);
1561 }
1562 }
1563 break;
1564 case HW_VAR_RESP_SIFS:
1565 /* RESP_SIFS for CCK */
1566 rtw_write8(Adapter, REG_R2T_SIFS, val[0]); /* SIFS_T2T_CCK (0x08) */
1567 rtw_write8(Adapter, REG_R2T_SIFS+1, val[1]); /* SIFS_R2T_CCK(0x08) */
1568 /* RESP_SIFS for OFDM */
1569 rtw_write8(Adapter, REG_T2T_SIFS, val[2]); /* SIFS_T2T_OFDM (0x0a) */
1570 rtw_write8(Adapter, REG_T2T_SIFS+1, val[3]); /* SIFS_R2T_OFDM(0x0a) */
1571 break;
1572 case HW_VAR_ACK_PREAMBLE:
1573 {
1574 u8 regTmp;
1575 u8 bShortPreamble = *((bool *)val);
1576 /* Joseph marked out for Netgear 3500 TKIP channel 7 issue.(Temporarily) */
1577 regTmp = (haldata->nCur40MhzPrimeSC)<<5;
1578 if (bShortPreamble)
1579 regTmp |= 0x80;
1580
1581 rtw_write8(Adapter, REG_RRSR+2, regTmp);
1582 }
1583 break;
1584 case HW_VAR_SEC_CFG:
1585 rtw_write8(Adapter, REG_SECCFG, *((u8 *)val));
1586 break;
1587 case HW_VAR_DM_FLAG:
1588 podmpriv->SupportAbility = *((u8 *)val);
1589 break;
1590 case HW_VAR_DM_FUNC_OP:
1591 if (val[0])
1592 podmpriv->BK_SupportAbility = podmpriv->SupportAbility;
1593 else
1594 podmpriv->SupportAbility = podmpriv->BK_SupportAbility;
1595 break;
1596 case HW_VAR_DM_FUNC_SET:
1597 if (*((u32 *)val) == DYNAMIC_ALL_FUNC_ENABLE) {
1598 pdmpriv->DMFlag = pdmpriv->InitDMFlag;
1599 podmpriv->SupportAbility = pdmpriv->InitODMFlag;
1600 } else {
1601 podmpriv->SupportAbility |= *((u32 *)val);
1602 }
1603 break;
1604 case HW_VAR_DM_FUNC_CLR:
1605 podmpriv->SupportAbility &= *((u32 *)val);
1606 break;
1607 case HW_VAR_CAM_EMPTY_ENTRY:
1608 {
1609 u8 ucIndex = *((u8 *)val);
1610 u8 i;
1611 u32 ulCommand = 0;
1612 u32 ulContent = 0;
1613 u32 ulEncAlgo = CAM_AES;
1614
1615 for (i = 0; i < CAM_CONTENT_COUNT; i++) {
1616 /* filled id in CAM config 2 byte */
1617 if (i == 0)
1618 ulContent |= (ucIndex & 0x03) | ((u16)(ulEncAlgo)<<2);
1619 else
1620 ulContent = 0;
1621 /* polling bit, and No Write enable, and address */
1622 ulCommand = CAM_CONTENT_COUNT*ucIndex+i;
1623 ulCommand = ulCommand | CAM_POLLINIG|CAM_WRITE;
1624 /* write content 0 is equall to mark invalid */
1625 rtw_write32(Adapter, WCAMI, ulContent); /* delay_ms(40); */
1626 rtw_write32(Adapter, RWCAM, ulCommand); /* delay_ms(40); */
1627 }
1628 }
1629 break;
1630 case HW_VAR_CAM_INVALID_ALL:
1631 rtw_write32(Adapter, RWCAM, BIT(31)|BIT(30));
1632 break;
1633 case HW_VAR_CAM_WRITE:
1634 {
1635 u32 cmd;
1636 u32 *cam_val = (u32 *)val;
1637 rtw_write32(Adapter, WCAMI, cam_val[0]);
1638
1639 cmd = CAM_POLLINIG | CAM_WRITE | cam_val[1];
1640 rtw_write32(Adapter, RWCAM, cmd);
1641 }
1642 break;
1643 case HW_VAR_AC_PARAM_VO:
1644 rtw_write32(Adapter, REG_EDCA_VO_PARAM, ((u32 *)(val))[0]);
1645 break;
1646 case HW_VAR_AC_PARAM_VI:
1647 rtw_write32(Adapter, REG_EDCA_VI_PARAM, ((u32 *)(val))[0]);
1648 break;
1649 case HW_VAR_AC_PARAM_BE:
1650 haldata->AcParam_BE = ((u32 *)(val))[0];
1651 rtw_write32(Adapter, REG_EDCA_BE_PARAM, ((u32 *)(val))[0]);
1652 break;
1653 case HW_VAR_AC_PARAM_BK:
1654 rtw_write32(Adapter, REG_EDCA_BK_PARAM, ((u32 *)(val))[0]);
1655 break;
1656 case HW_VAR_ACM_CTRL:
1657 {
1658 u8 acm_ctrl = *((u8 *)val);
1659 u8 AcmCtrl = rtw_read8(Adapter, REG_ACMHWCTRL);
1660
1661 if (acm_ctrl > 1)
1662 AcmCtrl = AcmCtrl | 0x1;
1663
1664 if (acm_ctrl & BIT(3))
1665 AcmCtrl |= AcmHw_VoqEn;
1666 else
1667 AcmCtrl &= (~AcmHw_VoqEn);
1668
1669 if (acm_ctrl & BIT(2))
1670 AcmCtrl |= AcmHw_ViqEn;
1671 else
1672 AcmCtrl &= (~AcmHw_ViqEn);
1673
1674 if (acm_ctrl & BIT(1))
1675 AcmCtrl |= AcmHw_BeqEn;
1676 else
1677 AcmCtrl &= (~AcmHw_BeqEn);
1678
1679 DBG_88E("[HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl);
1680 rtw_write8(Adapter, REG_ACMHWCTRL, AcmCtrl);
1681 }
1682 break;
1683 case HW_VAR_AMPDU_MIN_SPACE:
1684 {
1685 u8 MinSpacingToSet;
1686 u8 SecMinSpace;
1687
1688 MinSpacingToSet = *((u8 *)val);
1689 if (MinSpacingToSet <= 7) {
1690 switch (Adapter->securitypriv.dot11PrivacyAlgrthm) {
1691 case _NO_PRIVACY_:
1692 case _AES_:
1693 SecMinSpace = 0;
1694 break;
1695 case _WEP40_:
1696 case _WEP104_:
1697 case _TKIP_:
1698 case _TKIP_WTMIC_:
1699 SecMinSpace = 6;
1700 break;
1701 default:
1702 SecMinSpace = 7;
1703 break;
1704 }
1705 if (MinSpacingToSet < SecMinSpace)
1706 MinSpacingToSet = SecMinSpace;
1707 rtw_write8(Adapter, REG_AMPDU_MIN_SPACE, (rtw_read8(Adapter, REG_AMPDU_MIN_SPACE) & 0xf8) | MinSpacingToSet);
1708 }
1709 }
1710 break;
1711 case HW_VAR_AMPDU_FACTOR:
1712 {
1713 u8 RegToSet_Normal[4] = {0x41, 0xa8, 0x72, 0xb9};
1714 u8 FactorToSet;
1715 u8 *pRegToSet;
1716 u8 index = 0;
1717
1718 pRegToSet = RegToSet_Normal; /* 0xb972a841; */
1719 FactorToSet = *((u8 *)val);
1720 if (FactorToSet <= 3) {
1721 FactorToSet = (1<<(FactorToSet + 2));
1722 if (FactorToSet > 0xf)
1723 FactorToSet = 0xf;
1724
1725 for (index = 0; index < 4; index++) {
1726 if ((pRegToSet[index] & 0xf0) > (FactorToSet<<4))
1727 pRegToSet[index] = (pRegToSet[index] & 0x0f) | (FactorToSet<<4);
1728
1729 if ((pRegToSet[index] & 0x0f) > FactorToSet)
1730 pRegToSet[index] = (pRegToSet[index] & 0xf0) | (FactorToSet);
1731
1732 rtw_write8(Adapter, (REG_AGGLEN_LMT+index), pRegToSet[index]);
1733 }
1734 }
1735 }
1736 break;
1737 case HW_VAR_RXDMA_AGG_PG_TH:
1738 {
1739 u8 threshold = *((u8 *)val);
1740 if (threshold == 0)
1741 threshold = haldata->UsbRxAggPageCount;
1742 rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, threshold);
1743 }
1744 break;
1745 case HW_VAR_SET_RPWM:
1746 break;
1747 case HW_VAR_H2C_FW_PWRMODE:
1748 {
1749 u8 psmode = (*(u8 *)val);
1750
1751 /* Forece leave RF low power mode for 1T1R to prevent conficting setting in Fw power */
1752 /* saving sequence. 2010.06.07. Added by tynli. Suggested by SD3 yschang. */
1753 if ((psmode != PS_MODE_ACTIVE) && (!IS_92C_SERIAL(haldata->VersionID)))
1754 ODM_RF_Saving(podmpriv, true);
1755 rtl8188e_set_FwPwrMode_cmd(Adapter, psmode);
1756 }
1757 break;
1758 case HW_VAR_H2C_FW_JOINBSSRPT:
1759 {
1760 u8 mstatus = (*(u8 *)val);
1761 rtl8188e_set_FwJoinBssReport_cmd(Adapter, mstatus);
1762 }
1763 break;
1764 #ifdef CONFIG_88EU_P2P
1765 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
1766 {
1767 u8 p2p_ps_state = (*(u8 *)val);
1768 rtl8188e_set_p2p_ps_offload_cmd(Adapter, p2p_ps_state);
1769 }
1770 break;
1771 #endif
1772 case HW_VAR_INITIAL_GAIN:
1773 {
1774 struct rtw_dig *pDigTable = &podmpriv->DM_DigTable;
1775 u32 rx_gain = ((u32 *)(val))[0];
1776
1777 if (rx_gain == 0xff) {/* restore rx gain */
1778 ODM_Write_DIG(podmpriv, pDigTable->BackupIGValue);
1779 } else {
1780 pDigTable->BackupIGValue = pDigTable->CurIGValue;
1781 ODM_Write_DIG(podmpriv, rx_gain);
1782 }
1783 }
1784 break;
1785 case HW_VAR_TRIGGER_GPIO_0:
1786 rtl8192cu_trigger_gpio_0(Adapter);
1787 break;
1788 case HW_VAR_RPT_TIMER_SETTING:
1789 {
1790 u16 min_rpt_time = (*(u16 *)val);
1791 ODM_RA_Set_TxRPT_Time(podmpriv, min_rpt_time);
1792 }
1793 break;
1794 case HW_VAR_ANTENNA_DIVERSITY_SELECT:
1795 {
1796 u8 Optimum_antenna = (*(u8 *)val);
1797 u8 Ant;
1798 /* switch antenna to Optimum_antenna */
1799 if (haldata->CurAntenna != Optimum_antenna) {
1800 Ant = (Optimum_antenna == 2) ? MAIN_ANT : AUX_ANT;
1801 ODM_UpdateRxIdleAnt_88E(&haldata->odmpriv, Ant);
1802
1803 haldata->CurAntenna = Optimum_antenna;
1804 }
1805 }
1806 break;
1807 case HW_VAR_EFUSE_BYTES: /* To set EFUE total used bytes, added by Roger, 2008.12.22. */
1808 haldata->EfuseUsedBytes = *((u16 *)val);
1809 break;
1810 case HW_VAR_FIFO_CLEARN_UP:
1811 {
1812 struct pwrctrl_priv *pwrpriv = &Adapter->pwrctrlpriv;
1813 u8 trycnt = 100;
1814
1815 /* pause tx */
1816 rtw_write8(Adapter, REG_TXPAUSE, 0xff);
1817
1818 /* keep sn */
1819 Adapter->xmitpriv.nqos_ssn = rtw_read16(Adapter, REG_NQOS_SEQ);
1820
1821 if (!pwrpriv->bkeepfwalive) {
1822 /* RX DMA stop */
1823 rtw_write32(Adapter, REG_RXPKT_NUM, (rtw_read32(Adapter, REG_RXPKT_NUM)|RW_RELEASE_EN));
1824 do {
1825 if (!(rtw_read32(Adapter, REG_RXPKT_NUM)&RXDMA_IDLE))
1826 break;
1827 } while (trycnt--);
1828 if (trycnt == 0)
1829 DBG_88E("Stop RX DMA failed......\n");
1830
1831 /* RQPN Load 0 */
1832 rtw_write16(Adapter, REG_RQPN_NPQ, 0x0);
1833 rtw_write32(Adapter, REG_RQPN, 0x80000000);
1834 mdelay(10);
1835 }
1836 }
1837 break;
1838 case HW_VAR_CHECK_TXBUF:
1839 break;
1840 case HW_VAR_APFM_ON_MAC:
1841 haldata->bMacPwrCtrlOn = *val;
1842 DBG_88E("%s: bMacPwrCtrlOn=%d\n", __func__, haldata->bMacPwrCtrlOn);
1843 break;
1844 case HW_VAR_TX_RPT_MAX_MACID:
1845 {
1846 u8 maxMacid = *val;
1847 DBG_88E("### MacID(%d),Set Max Tx RPT MID(%d)\n", maxMacid, maxMacid+1);
1848 rtw_write8(Adapter, REG_TX_RPT_CTRL+1, maxMacid+1);
1849 }
1850 break;
1851 case HW_VAR_H2C_MEDIA_STATUS_RPT:
1852 rtl8188e_set_FwMediaStatus_cmd(Adapter , (*(__le16 *)val));
1853 break;
1854 case HW_VAR_BCN_VALID:
1855 /* BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2, write 1 to clear, Clear by sw */
1856 rtw_write8(Adapter, REG_TDECTRL+2, rtw_read8(Adapter, REG_TDECTRL+2) | BIT0);
1857 break;
1858 default:
1859 break;
1860 }
1861 }
1862
1863 static void GetHwReg8188EU(struct adapter *Adapter, u8 variable, u8 *val)
1864 {
1865 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
1866 struct odm_dm_struct *podmpriv = &haldata->odmpriv;
1867
1868 switch (variable) {
1869 case HW_VAR_BASIC_RATE:
1870 *((u16 *)(val)) = haldata->BasicRateSet;
1871 case HW_VAR_TXPAUSE:
1872 val[0] = rtw_read8(Adapter, REG_TXPAUSE);
1873 break;
1874 case HW_VAR_BCN_VALID:
1875 /* BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2 */
1876 val[0] = (BIT0 & rtw_read8(Adapter, REG_TDECTRL+2)) ? true : false;
1877 break;
1878 case HW_VAR_DM_FLAG:
1879 val[0] = podmpriv->SupportAbility;
1880 break;
1881 case HW_VAR_RF_TYPE:
1882 val[0] = haldata->rf_type;
1883 break;
1884 case HW_VAR_FWLPS_RF_ON:
1885 {
1886 /* When we halt NIC, we should check if FW LPS is leave. */
1887 if (Adapter->pwrctrlpriv.rf_pwrstate == rf_off) {
1888 /* If it is in HW/SW Radio OFF or IPS state, we do not check Fw LPS Leave, */
1889 /* because Fw is unload. */
1890 val[0] = true;
1891 } else {
1892 u32 valRCR;
1893 valRCR = rtw_read32(Adapter, REG_RCR);
1894 valRCR &= 0x00070000;
1895 if (valRCR)
1896 val[0] = false;
1897 else
1898 val[0] = true;
1899 }
1900 }
1901 break;
1902 case HW_VAR_CURRENT_ANTENNA:
1903 val[0] = haldata->CurAntenna;
1904 break;
1905 case HW_VAR_EFUSE_BYTES: /* To get EFUE total used bytes, added by Roger, 2008.12.22. */
1906 *((u16 *)(val)) = haldata->EfuseUsedBytes;
1907 break;
1908 case HW_VAR_APFM_ON_MAC:
1909 *val = haldata->bMacPwrCtrlOn;
1910 break;
1911 case HW_VAR_CHK_HI_QUEUE_EMPTY:
1912 *val = ((rtw_read32(Adapter, REG_HGQ_INFORMATION)&0x0000ff00) == 0) ? true : false;
1913 break;
1914 default:
1915 break;
1916 }
1917
1918 }
1919
1920 /* */
1921 /* Description: */
1922 /* Query setting of specified variable. */
1923 /* */
1924 static u8
1925 GetHalDefVar8188EUsb(
1926 struct adapter *Adapter,
1927 enum hal_def_variable eVariable,
1928 void *pValue
1929 )
1930 {
1931 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
1932 u8 bResult = _SUCCESS;
1933
1934 switch (eVariable) {
1935 case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB:
1936 {
1937 struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
1938 struct sta_priv *pstapriv = &Adapter->stapriv;
1939 struct sta_info *psta;
1940 psta = rtw_get_stainfo(pstapriv, pmlmepriv->cur_network.network.MacAddress);
1941 if (psta)
1942 *((int *)pValue) = psta->rssi_stat.UndecoratedSmoothedPWDB;
1943 }
1944 break;
1945 case HAL_DEF_IS_SUPPORT_ANT_DIV:
1946 *((u8 *)pValue) = (haldata->AntDivCfg == 0) ? false : true;
1947 break;
1948 case HAL_DEF_CURRENT_ANTENNA:
1949 *((u8 *)pValue) = haldata->CurAntenna;
1950 break;
1951 case HAL_DEF_DRVINFO_SZ:
1952 *((u32 *)pValue) = DRVINFO_SZ;
1953 break;
1954 case HAL_DEF_MAX_RECVBUF_SZ:
1955 *((u32 *)pValue) = MAX_RECVBUF_SZ;
1956 break;
1957 case HAL_DEF_RX_PACKET_OFFSET:
1958 *((u32 *)pValue) = RXDESC_SIZE + DRVINFO_SZ;
1959 break;
1960 case HAL_DEF_DBG_DM_FUNC:
1961 *((u32 *)pValue) = haldata->odmpriv.SupportAbility;
1962 break;
1963 case HAL_DEF_RA_DECISION_RATE:
1964 {
1965 u8 MacID = *((u8 *)pValue);
1966 *((u8 *)pValue) = ODM_RA_GetDecisionRate_8188E(&(haldata->odmpriv), MacID);
1967 }
1968 break;
1969 case HAL_DEF_RA_SGI:
1970 {
1971 u8 MacID = *((u8 *)pValue);
1972 *((u8 *)pValue) = ODM_RA_GetShortGI_8188E(&(haldata->odmpriv), MacID);
1973 }
1974 break;
1975 case HAL_DEF_PT_PWR_STATUS:
1976 {
1977 u8 MacID = *((u8 *)pValue);
1978 *((u8 *)pValue) = ODM_RA_GetHwPwrStatus_8188E(&(haldata->odmpriv), MacID);
1979 }
1980 break;
1981 case HW_VAR_MAX_RX_AMPDU_FACTOR:
1982 *((u32 *)pValue) = MAX_AMPDU_FACTOR_64K;
1983 break;
1984 case HW_DEF_RA_INFO_DUMP:
1985 {
1986 u8 entry_id = *((u8 *)pValue);
1987 if (check_fwstate(&Adapter->mlmepriv, _FW_LINKED)) {
1988 DBG_88E("============ RA status check ===================\n");
1989 DBG_88E("Mac_id:%d , RateID = %d, RAUseRate = 0x%08x, RateSGI = %d, DecisionRate = 0x%02x ,PTStage = %d\n",
1990 entry_id,
1991 haldata->odmpriv.RAInfo[entry_id].RateID,
1992 haldata->odmpriv.RAInfo[entry_id].RAUseRate,
1993 haldata->odmpriv.RAInfo[entry_id].RateSGI,
1994 haldata->odmpriv.RAInfo[entry_id].DecisionRate,
1995 haldata->odmpriv.RAInfo[entry_id].PTStage);
1996 }
1997 }
1998 break;
1999 case HW_DEF_ODM_DBG_FLAG:
2000 {
2001 struct odm_dm_struct *dm_ocm = &(haldata->odmpriv);
2002 pr_info("dm_ocm->DebugComponents = 0x%llx\n", dm_ocm->DebugComponents);
2003 }
2004 break;
2005 case HAL_DEF_DBG_DUMP_RXPKT:
2006 *((u8 *)pValue) = haldata->bDumpRxPkt;
2007 break;
2008 case HAL_DEF_DBG_DUMP_TXPKT:
2009 *((u8 *)pValue) = haldata->bDumpTxPkt;
2010 break;
2011 default:
2012 bResult = _FAIL;
2013 break;
2014 }
2015
2016 return bResult;
2017 }
2018
2019 /* */
2020 /* Description: */
2021 /* Change default setting of specified variable. */
2022 /* */
2023 static u8 SetHalDefVar8188EUsb(struct adapter *Adapter, enum hal_def_variable eVariable, void *pValue)
2024 {
2025 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
2026 u8 bResult = _SUCCESS;
2027
2028 switch (eVariable) {
2029 case HAL_DEF_DBG_DM_FUNC:
2030 {
2031 u8 dm_func = *((u8 *)pValue);
2032 struct odm_dm_struct *podmpriv = &haldata->odmpriv;
2033
2034 if (dm_func == 0) { /* disable all dynamic func */
2035 podmpriv->SupportAbility = DYNAMIC_FUNC_DISABLE;
2036 DBG_88E("==> Disable all dynamic function...\n");
2037 } else if (dm_func == 1) {/* disable DIG */
2038 podmpriv->SupportAbility &= (~DYNAMIC_BB_DIG);
2039 DBG_88E("==> Disable DIG...\n");
2040 } else if (dm_func == 2) {/* disable High power */
2041 podmpriv->SupportAbility &= (~DYNAMIC_BB_DYNAMIC_TXPWR);
2042 } else if (dm_func == 3) {/* disable tx power tracking */
2043 podmpriv->SupportAbility &= (~DYNAMIC_RF_CALIBRATION);
2044 DBG_88E("==> Disable tx power tracking...\n");
2045 } else if (dm_func == 5) {/* disable antenna diversity */
2046 podmpriv->SupportAbility &= (~DYNAMIC_BB_ANT_DIV);
2047 } else if (dm_func == 6) {/* turn on all dynamic func */
2048 if (!(podmpriv->SupportAbility & DYNAMIC_BB_DIG)) {
2049 struct rtw_dig *pDigTable = &podmpriv->DM_DigTable;
2050 pDigTable->CurIGValue = rtw_read8(Adapter, 0xc50);
2051 }
2052 podmpriv->SupportAbility = DYNAMIC_ALL_FUNC_ENABLE;
2053 DBG_88E("==> Turn on all dynamic function...\n");
2054 }
2055 }
2056 break;
2057 case HAL_DEF_DBG_DUMP_RXPKT:
2058 haldata->bDumpRxPkt = *((u8 *)pValue);
2059 break;
2060 case HAL_DEF_DBG_DUMP_TXPKT:
2061 haldata->bDumpTxPkt = *((u8 *)pValue);
2062 break;
2063 case HW_DEF_FA_CNT_DUMP:
2064 {
2065 u8 bRSSIDump = *((u8 *)pValue);
2066 struct odm_dm_struct *dm_ocm = &(haldata->odmpriv);
2067 if (bRSSIDump)
2068 dm_ocm->DebugComponents = ODM_COMP_DIG|ODM_COMP_FA_CNT ;
2069 else
2070 dm_ocm->DebugComponents = 0;
2071 }
2072 break;
2073 case HW_DEF_ODM_DBG_FLAG:
2074 {
2075 u64 DebugComponents = *((u64 *)pValue);
2076 struct odm_dm_struct *dm_ocm = &(haldata->odmpriv);
2077 dm_ocm->DebugComponents = DebugComponents;
2078 }
2079 break;
2080 default:
2081 bResult = _FAIL;
2082 break;
2083 }
2084
2085 return bResult;
2086 }
2087
2088 static void UpdateHalRAMask8188EUsb(struct adapter *adapt, u32 mac_id, u8 rssi_level)
2089 {
2090 u8 init_rate = 0;
2091 u8 networkType, raid;
2092 u32 mask, rate_bitmap;
2093 u8 shortGIrate = false;
2094 int supportRateNum = 0;
2095 struct sta_info *psta;
2096 struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
2097 struct mlme_ext_priv *pmlmeext = &adapt->mlmeextpriv;
2098 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
2099 struct wlan_bssid_ex *cur_network = &(pmlmeinfo->network);
2100
2101 if (mac_id >= NUM_STA) /* CAM_SIZE */
2102 return;
2103 psta = pmlmeinfo->FW_sta_info[mac_id].psta;
2104 if (psta == NULL)
2105 return;
2106 switch (mac_id) {
2107 case 0:/* for infra mode */
2108 supportRateNum = rtw_get_rateset_len(cur_network->SupportedRates);
2109 networkType = judge_network_type(adapt, cur_network->SupportedRates, supportRateNum) & 0xf;
2110 raid = networktype_to_raid(networkType);
2111 mask = update_supported_rate(cur_network->SupportedRates, supportRateNum);
2112 mask |= (pmlmeinfo->HT_enable) ? update_MSC_rate(&(pmlmeinfo->HT_caps)) : 0;
2113 if (support_short_GI(adapt, &(pmlmeinfo->HT_caps)))
2114 shortGIrate = true;
2115 break;
2116 case 1:/* for broadcast/multicast */
2117 supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates);
2118 if (pmlmeext->cur_wireless_mode & WIRELESS_11B)
2119 networkType = WIRELESS_11B;
2120 else
2121 networkType = WIRELESS_11G;
2122 raid = networktype_to_raid(networkType);
2123 mask = update_basic_rate(cur_network->SupportedRates, supportRateNum);
2124 break;
2125 default: /* for each sta in IBSS */
2126 supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates);
2127 networkType = judge_network_type(adapt, pmlmeinfo->FW_sta_info[mac_id].SupportedRates, supportRateNum) & 0xf;
2128 raid = networktype_to_raid(networkType);
2129 mask = update_supported_rate(cur_network->SupportedRates, supportRateNum);
2130
2131 /* todo: support HT in IBSS */
2132 break;
2133 }
2134
2135 rate_bitmap = 0x0fffffff;
2136 rate_bitmap = ODM_Get_Rate_Bitmap(&haldata->odmpriv, mac_id, mask, rssi_level);
2137 DBG_88E("%s => mac_id:%d, networkType:0x%02x, mask:0x%08x\n\t ==> rssi_level:%d, rate_bitmap:0x%08x\n",
2138 __func__, mac_id, networkType, mask, rssi_level, rate_bitmap);
2139
2140 mask &= rate_bitmap;
2141
2142 init_rate = get_highest_rate_idx(mask)&0x3f;
2143
2144 if (haldata->fw_ractrl) {
2145 u8 arg;
2146
2147 arg = mac_id & 0x1f;/* MACID */
2148 arg |= BIT(7);
2149 if (shortGIrate)
2150 arg |= BIT(5);
2151 mask |= ((raid << 28) & 0xf0000000);
2152 DBG_88E("update raid entry, mask=0x%x, arg=0x%x\n", mask, arg);
2153 psta->ra_mask = mask;
2154 mask |= ((raid << 28) & 0xf0000000);
2155
2156 /* to do ,for 8188E-SMIC */
2157 rtl8188e_set_raid_cmd(adapt, mask);
2158 } else {
2159 ODM_RA_UpdateRateInfo_8188E(&(haldata->odmpriv),
2160 mac_id,
2161 raid,
2162 mask,
2163 shortGIrate
2164 );
2165 }
2166 /* set ra_id */
2167 psta->raid = raid;
2168 psta->init_rate = init_rate;
2169 }
2170
2171 static void SetBeaconRelatedRegisters8188EUsb(struct adapter *adapt)
2172 {
2173 u32 value32;
2174 struct mlme_ext_priv *pmlmeext = &(adapt->mlmeextpriv);
2175 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
2176 u32 bcn_ctrl_reg = REG_BCN_CTRL;
2177 /* reset TSF, enable update TSF, correcting TSF On Beacon */
2178
2179 /* BCN interval */
2180 rtw_write16(adapt, REG_BCN_INTERVAL, pmlmeinfo->bcn_interval);
2181 rtw_write8(adapt, REG_ATIMWND, 0x02);/* 2ms */
2182
2183 _InitBeaconParameters(adapt);
2184
2185 rtw_write8(adapt, REG_SLOT, 0x09);
2186
2187 value32 = rtw_read32(adapt, REG_TCR);
2188 value32 &= ~TSFRST;
2189 rtw_write32(adapt, REG_TCR, value32);
2190
2191 value32 |= TSFRST;
2192 rtw_write32(adapt, REG_TCR, value32);
2193
2194 /* NOTE: Fix test chip's bug (about contention windows's randomness) */
2195 rtw_write8(adapt, REG_RXTSF_OFFSET_CCK, 0x50);
2196 rtw_write8(adapt, REG_RXTSF_OFFSET_OFDM, 0x50);
2197
2198 _BeaconFunctionEnable(adapt, true, true);
2199
2200 ResumeTxBeacon(adapt);
2201
2202 rtw_write8(adapt, bcn_ctrl_reg, rtw_read8(adapt, bcn_ctrl_reg)|BIT(1));
2203 }
2204
2205 static void rtl8188eu_init_default_value(struct adapter *adapt)
2206 {
2207 struct hal_data_8188e *haldata;
2208 struct pwrctrl_priv *pwrctrlpriv;
2209 u8 i;
2210
2211 haldata = GET_HAL_DATA(adapt);
2212 pwrctrlpriv = &adapt->pwrctrlpriv;
2213
2214 /* init default value */
2215 haldata->fw_ractrl = false;
2216 if (!pwrctrlpriv->bkeepfwalive)
2217 haldata->LastHMEBoxNum = 0;
2218
2219 /* init dm default value */
2220 haldata->odmpriv.RFCalibrateInfo.bIQKInitialized = false;
2221 haldata->odmpriv.RFCalibrateInfo.TM_Trigger = 0;/* for IQK */
2222 haldata->pwrGroupCnt = 0;
2223 haldata->PGMaxGroup = 13;
2224 haldata->odmpriv.RFCalibrateInfo.ThermalValue_HP_index = 0;
2225 for (i = 0; i < HP_THERMAL_NUM; i++)
2226 haldata->odmpriv.RFCalibrateInfo.ThermalValue_HP[i] = 0;
2227 }
2228
2229 void rtl8188eu_set_hal_ops(struct adapter *adapt)
2230 {
2231 struct hal_ops *halfunc = &adapt->HalFunc;
2232
2233
2234 adapt->HalData = rtw_zmalloc(sizeof(struct hal_data_8188e));
2235 if (adapt->HalData == NULL)
2236 DBG_88E("cant not alloc memory for HAL DATA\n");
2237 adapt->hal_data_sz = sizeof(struct hal_data_8188e);
2238
2239 halfunc->hal_power_on = rtl8188eu_InitPowerOn;
2240 halfunc->hal_init = &rtl8188eu_hal_init;
2241 halfunc->hal_deinit = &rtl8188eu_hal_deinit;
2242
2243 halfunc->inirp_init = &rtl8188eu_inirp_init;
2244 halfunc->inirp_deinit = &rtl8188eu_inirp_deinit;
2245
2246 halfunc->init_xmit_priv = &rtl8188eu_init_xmit_priv;
2247 halfunc->free_xmit_priv = &rtl8188eu_free_xmit_priv;
2248
2249 halfunc->init_recv_priv = &rtl8188eu_init_recv_priv;
2250 halfunc->free_recv_priv = &rtl8188eu_free_recv_priv;
2251 halfunc->InitSwLeds = &rtl8188eu_InitSwLeds;
2252 halfunc->DeInitSwLeds = &rtl8188eu_DeInitSwLeds;
2253
2254 halfunc->init_default_value = &rtl8188eu_init_default_value;
2255 halfunc->intf_chip_configure = &rtl8188eu_interface_configure;
2256 halfunc->read_adapter_info = &ReadAdapterInfo8188EU;
2257
2258 halfunc->SetHwRegHandler = &SetHwReg8188EU;
2259 halfunc->GetHwRegHandler = &GetHwReg8188EU;
2260 halfunc->GetHalDefVarHandler = &GetHalDefVar8188EUsb;
2261 halfunc->SetHalDefVarHandler = &SetHalDefVar8188EUsb;
2262
2263 halfunc->UpdateRAMaskHandler = &UpdateHalRAMask8188EUsb;
2264 halfunc->SetBeaconRelatedRegistersHandler = &SetBeaconRelatedRegisters8188EUsb;
2265
2266 halfunc->hal_xmit = &rtl8188eu_hal_xmit;
2267 halfunc->mgnt_xmit = &rtl8188eu_mgnt_xmit;
2268
2269 rtl8188e_set_hal_ops(halfunc);
2270 }
(deprecated) Btrfs devel tree