include/asm-m32r/system.h

   1 #ifndef _ASM_M32R_SYSTEM_H
   2 #define _ASM_M32R_SYSTEM_H
   3
   4 /*
   5  * This file is subject to the terms and conditions of the GNU General Public
   6  * License.  See the file "COPYING" in the main directory of this archive
   7  * for more details.
   8  *
   9  * Copyright (C) 2001  by Hiroyuki Kondo, Hirokazu Takata, and Hitoshi Yamamoto
  10  * Copyright (C) 2004  Hirokazu Takata <takata at linux-m32r.org>
  11  */
  12
  13 #include <linux/config.h>
  14 #include <asm/assembler.h>
  15
  16 #ifdef __KERNEL__
  17
  18 /*
  19  * switch_to(prev, next) should switch from task `prev' to `next'
  20  * `prev' will never be the same as `next'.
  21  *
  22  * `next' and `prev' should be struct task_struct, but it isn't always defined
  23  */
  24
  25 #define switch_to(prev, next, last)  do { \
  26         register unsigned long  arg0 __asm__ ("r0") = (unsigned long)prev; \
  27         register unsigned long  arg1 __asm__ ("r1") = (unsigned long)next; \
  28         register unsigned long  *oldsp __asm__ ("r2") = &(prev->thread.sp); \
  29         register unsigned long  *newsp __asm__ ("r3") = &(next->thread.sp); \
  30         register unsigned long  *oldlr __asm__ ("r4") = &(prev->thread.lr); \
  31         register unsigned long  *newlr __asm__ ("r5") = &(next->thread.lr); \
  32         register struct task_struct  *__last __asm__ ("r6"); \
  33         __asm__ __volatile__ ( \
  34                 "st     r8, @-r15                                 \n\t" \
  35                 "st     r9, @-r15                                 \n\t" \
  36                 "st    r10, @-r15                                 \n\t" \
  37                 "st    r11, @-r15                                 \n\t" \
  38                 "st    r12, @-r15                                 \n\t" \
  39                 "st    r13, @-r15                                 \n\t" \
  40                 "st    r14, @-r15                                 \n\t" \
  41                 "seth  r14, #high(1f)                             \n\t" \
  42                 "or3   r14, r14, #low(1f)                         \n\t" \
  43                 "st    r14, @r4    ; store old LR                 \n\t" \
  44                 "st    r15, @r2    ; store old SP                 \n\t" \
  45                 "ld    r15, @r3    ; load new SP                  \n\t" \
  46                 "st     r0, @-r15  ; store 'prev' onto new stack  \n\t" \
  47                 "ld    r14, @r5    ; load new LR                  \n\t" \
  48                 "jmp   r14                                        \n\t" \
  49                 ".fillinsn                                        \n  " \
  50                 "1:                                               \n\t" \
  51                 "ld     r6, @r15+  ; load 'prev' from new stack   \n\t" \
  52                 "ld    r14, @r15+                                 \n\t" \
  53                 "ld    r13, @r15+                                 \n\t" \
  54                 "ld    r12, @r15+                                 \n\t" \
  55                 "ld    r11, @r15+                                 \n\t" \
  56                 "ld    r10, @r15+                                 \n\t" \
  57                 "ld     r9, @r15+                                 \n\t" \
  58                 "ld     r8, @r15+                                 \n\t" \
  59                 : "=&r" (__last) \
  60                 : "r" (arg0), "r" (arg1), "r" (oldsp), "r" (newsp), \
  61                   "r" (oldlr), "r" (newlr) \
  62                 : "memory" \
  63         ); \
  64         last = __last; \
  65 } while(0)
  66
  67 /*
  68  * On SMP systems, when the scheduler does migration-cost autodetection,
  69  * it needs a way to flush as much of the CPU's caches as possible.
  70  *
  71  * TODO: fill this in!
  72  */
  73 static inline void sched_cacheflush(void)
  74 {
  75 }
  76
  77 /* Interrupt Control */
  78 #if !defined(CONFIG_CHIP_M32102) && !defined(CONFIG_CHIP_M32104)
  79 #define local_irq_enable() \
  80         __asm__ __volatile__ ("setpsw #0x40 -> nop": : :"memory")
  81 #define local_irq_disable() \
  82         __asm__ __volatile__ ("clrpsw #0x40 -> nop": : :"memory")
  83 #else   /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
  84 static inline void local_irq_enable(void)
  85 {
  86         unsigned long tmpreg;
  87         __asm__ __volatile__(
  88                 "mvfc   %0, psw;                \n\t"
  89                 "or3    %0, %0, #0x0040;        \n\t"
  90                 "mvtc   %0, psw;                \n\t"
  91         : "=&r" (tmpreg) : : "cbit", "memory");
  92 }
  93
  94 static inline void local_irq_disable(void)
  95 {
  96         unsigned long tmpreg0, tmpreg1;
  97         __asm__ __volatile__(
  98                 "ld24   %0, #0  ; Use 32-bit insn. \n\t"
  99                 "mvfc   %1, psw ; No interrupt can be accepted here. \n\t"
 100                 "mvtc   %0, psw \n\t"
 101                 "and3   %0, %1, #0xffbf \n\t"
 102                 "mvtc   %0, psw \n\t"
 103         : "=&r" (tmpreg0), "=&r" (tmpreg1) : : "cbit", "memory");
 104 }
 105 #endif  /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
 106
 107 #define local_save_flags(x) \
 108         __asm__ __volatile__("mvfc %0,psw" : "=r"(x) : /* no input */)
 109
 110 #define local_irq_restore(x) \
 111         __asm__ __volatile__("mvtc %0,psw" : /* no outputs */ \
 112                 : "r" (x) : "cbit", "memory")
 113
 114 #if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104))
 115 #define local_irq_save(x)                               \
 116         __asm__ __volatile__(                           \
 117                 "mvfc   %0, psw;                \n\t"   \
 118                 "clrpsw #0x40 -> nop;           \n\t"   \
 119                 : "=r" (x) : /* no input */ : "memory")
 120 #else   /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
 121 #define local_irq_save(x)                               \
 122         ({                                              \
 123                 unsigned long tmpreg;                   \
 124                 __asm__ __volatile__(                   \
 125                         "ld24   %1, #0 \n\t"            \
 126                         "mvfc   %0, psw \n\t"           \
 127                         "mvtc   %1, psw \n\t"           \
 128                         "and3   %1, %0, #0xffbf \n\t"   \
 129                         "mvtc   %1, psw \n\t"           \
 130                         : "=r" (x), "=&r" (tmpreg)      \
 131                         : : "cbit", "memory");          \
 132         })
 133 #endif  /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
 134
 135 #define irqs_disabled()                                 \
 136         ({                                              \
 137                 unsigned long flags;                    \
 138                 local_save_flags(flags);                \
 139                 !(flags & 0x40);                        \
 140         })
 141
 142 #define nop()   __asm__ __volatile__ ("nop" : : )
 143
 144 #define xchg(ptr,x) \
 145         ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
 146
 147 #define tas(ptr)        (xchg((ptr),1))
 148
 149 #ifdef CONFIG_SMP
 150 extern void  __xchg_called_with_bad_pointer(void);
 151 #endif
 152
 153 #ifdef CONFIG_CHIP_M32700_TS1
 154 #define DCACHE_CLEAR(reg0, reg1, addr)                          \
 155         "seth   "reg1", #high(dcache_dummy);            \n\t"   \
 156         "or3    "reg1", "reg1", #low(dcache_dummy);     \n\t"   \
 157         "lock   "reg0", @"reg1";                        \n\t"   \
 158         "add3   "reg0", "addr", #0x1000;                \n\t"   \
 159         "ld     "reg0", @"reg0";                        \n\t"   \
 160         "add3   "reg0", "addr", #0x2000;                \n\t"   \
 161         "ld     "reg0", @"reg0";                        \n\t"   \
 162         "unlock "reg0", @"reg1";                        \n\t"
 163         /* FIXME: This workaround code cannot handle kenrel modules
 164          * correctly under SMP environment.
 165          */
 166 #else   /* CONFIG_CHIP_M32700_TS1 */
 167 #define DCACHE_CLEAR(reg0, reg1, addr)
 168 #endif  /* CONFIG_CHIP_M32700_TS1 */
 169
 170 static __inline__ unsigned long __xchg(unsigned long x, volatile void * ptr,
 171         int size)
 172 {
 173         unsigned long flags;
 174         unsigned long tmp = 0;
 175
 176         local_irq_save(flags);
 177
 178         switch (size) {
 179 #ifndef CONFIG_SMP
 180         case 1:
 181                 __asm__ __volatile__ (
 182                         "ldb    %0, @%2 \n\t"
 183                         "stb    %1, @%2 \n\t"
 184                         : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
 185                 break;
 186         case 2:
 187                 __asm__ __volatile__ (
 188                         "ldh    %0, @%2 \n\t"
 189                         "sth    %1, @%2 \n\t"
 190                         : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
 191                 break;
 192         case 4:
 193                 __asm__ __volatile__ (
 194                         "ld     %0, @%2 \n\t"
 195                         "st     %1, @%2 \n\t"
 196                         : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
 197                 break;
 198 #else  /* CONFIG_SMP */
 199         case 4:
 200                 __asm__ __volatile__ (
 201                         DCACHE_CLEAR("%0", "r4", "%2")
 202                         "lock   %0, @%2;        \n\t"
 203                         "unlock %1, @%2;        \n\t"
 204                         : "=&r" (tmp) : "r" (x), "r" (ptr)
 205                         : "memory"
 206 #ifdef CONFIG_CHIP_M32700_TS1
 207                         , "r4"
 208 #endif  /* CONFIG_CHIP_M32700_TS1 */
 209                 );
 210                 break;
 211         default:
 212                 __xchg_called_with_bad_pointer();
 213 #endif  /* CONFIG_SMP */
 214         }
 215
 216         local_irq_restore(flags);
 217
 218         return (tmp);
 219 }
 220
 221 #define __HAVE_ARCH_CMPXCHG     1
 222
 223 static __inline__ unsigned long
 224 __cmpxchg_u32(volatile unsigned int *p, unsigned int old, unsigned int new)
 225 {
 226         unsigned long flags;
 227         unsigned int retval;
 228
 229         local_irq_save(flags);
 230         __asm__ __volatile__ (
 231                         DCACHE_CLEAR("%0", "r4", "%1")
 232                         M32R_LOCK" %0, @%1;     \n"
 233                 "       bne     %0, %2, 1f;     \n"
 234                         M32R_UNLOCK" %3, @%1;   \n"
 235                 "       bra     2f;             \n"
 236                 "       .fillinsn               \n"
 237                 "1:"
 238                         M32R_UNLOCK" %0, @%1;   \n"
 239                 "       .fillinsn               \n"
 240                 "2:"
 241                         : "=&r" (retval)
 242                         : "r" (p), "r" (old), "r" (new)
 243                         : "cbit", "memory"
 244 #ifdef CONFIG_CHIP_M32700_TS1
 245                         , "r4"
 246 #endif  /* CONFIG_CHIP_M32700_TS1 */
 247                 );
 248         local_irq_restore(flags);
 249
 250         return retval;
 251 }
 252
 253 /* This function doesn't exist, so you'll get a linker error
 254    if something tries to do an invalid cmpxchg().  */
 255 extern void __cmpxchg_called_with_bad_pointer(void);
 256
 257 static __inline__ unsigned long
 258 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
 259 {
 260         switch (size) {
 261         case 4:
 262                 return __cmpxchg_u32(ptr, old, new);
 263 #if 0   /* we don't have __cmpxchg_u64 */
 264         case 8:
 265                 return __cmpxchg_u64(ptr, old, new);
 266 #endif /* 0 */
 267         }
 268         __cmpxchg_called_with_bad_pointer();
 269         return old;
 270 }
 271
 272 #define cmpxchg(ptr,o,n)                                                 \
 273   ({                                                                     \
 274      __typeof__(*(ptr)) _o_ = (o);                                       \
 275      __typeof__(*(ptr)) _n_ = (n);                                       \
 276      (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,           \
 277                                     (unsigned long)_n_, sizeof(*(ptr))); \
 278   })
 279
 280 #endif  /* __KERNEL__ */
 281
 282 /*
 283  * Memory barrier.
 284  *
 285  * mb() prevents loads and stores being reordered across this point.
 286  * rmb() prevents loads being reordered across this point.
 287  * wmb() prevents stores being reordered across this point.
 288  */
 289 #define mb()   barrier()
 290 #define rmb()  mb()
 291 #define wmb()  mb()
 292
 293 /**
 294  * read_barrier_depends - Flush all pending reads that subsequents reads
 295  * depend on.
 296  *
 297  * No data-dependent reads from memory-like regions are ever reordered
 298  * over this barrier.  All reads preceding this primitive are guaranteed
 299  * to access memory (but not necessarily other CPUs' caches) before any
 300  * reads following this primitive that depend on the data return by
 301  * any of the preceding reads.  This primitive is much lighter weight than
 302  * rmb() on most CPUs, and is never heavier weight than is
 303  * rmb().
 304  *
 305  * These ordering constraints are respected by both the local CPU
 306  * and the compiler.
 307  *
 308  * Ordering is not guaranteed by anything other than these primitives,
 309  * not even by data dependencies.  See the documentation for
 310  * memory_barrier() for examples and URLs to more information.
 311  *
 312  * For example, the following code would force ordering (the initial
 313  * value of "a" is zero, "b" is one, and "p" is "&a"):
 314  *
 315  * <programlisting>
 316  *      CPU 0                           CPU 1
 317  *
 318  *      b = 2;
 319  *      memory_barrier();
 320  *      p = &b;                         q = p;
 321  *                                      read_barrier_depends();
 322  *                                      d = *q;
 323  * </programlisting>
 324  *
 325  *
 326  * because the read of "*q" depends on the read of "p" and these
 327  * two reads are separated by a read_barrier_depends().  However,
 328  * the following code, with the same initial values for "a" and "b":
 329  *
 330  * <programlisting>
 331  *      CPU 0                           CPU 1
 332  *
 333  *      a = 2;
 334  *      memory_barrier();
 335  *      b = 3;                          y = b;
 336  *                                      read_barrier_depends();
 337  *                                      x = a;
 338  * </programlisting>
 339  *
 340  * does not enforce ordering, since there is no data dependency between
 341  * the read of "a" and the read of "b".  Therefore, on some CPUs, such
 342  * as Alpha, "y" could be set to 3 and "x" to 0.  Use rmb()
 343  * in cases like thiswhere there are no data dependencies.
 344  **/
 345
 346 #define read_barrier_depends()  do { } while (0)
 347
 348 #ifdef CONFIG_SMP
 349 #define smp_mb()        mb()
 350 #define smp_rmb()       rmb()
 351 #define smp_wmb()       wmb()
 352 #define smp_read_barrier_depends()      read_barrier_depends()
 353 #else
 354 #define smp_mb()        barrier()
 355 #define smp_rmb()       barrier()
 356 #define smp_wmb()       barrier()
 357 #define smp_read_barrier_depends()      do { } while (0)
 358 #endif
 359
 360 #define set_mb(var, value) do { xchg(&var, value); } while (0)
 361 #define set_wmb(var, value) do { var = value; wmb(); } while (0)
 362
 363 #define arch_align_stack(x) (x)
 364
 365 #endif  /* _ASM_M32R_SYSTEM_H */