5 * Please do not include this file in generic code. There is currently
6 * no requirement for any architecture to implement anything held
12 #include <linux/smp.h>
13 #include <linux/linkage.h>
14 #include <linux/cache.h>
15 #include <linux/spinlock.h>
16 #include <linux/cpumask.h>
17 #include <linux/gfp.h>
18 #include <linux/irqreturn.h>
19 #include <linux/irqnr.h>
20 #include <linux/errno.h>
21 #include <linux/topology.h>
22 #include <linux/wait.h>
25 #include <asm/ptrace.h>
26 #include <asm/irq_regs.h>
32 typedef void (*irq_flow_handler_t
)(unsigned int irq
,
33 struct irq_desc
*desc
);
34 typedef void (*irq_preflow_handler_t
)(struct irq_data
*data
);
39 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
41 * IRQ_TYPE_NONE - default, unspecified type
42 * IRQ_TYPE_EDGE_RISING - rising edge triggered
43 * IRQ_TYPE_EDGE_FALLING - falling edge triggered
44 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered
45 * IRQ_TYPE_LEVEL_HIGH - high level triggered
46 * IRQ_TYPE_LEVEL_LOW - low level triggered
47 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits
48 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits
49 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type
50 * to setup the HW to a sane default (used
51 * by irqdomain map() callbacks to synchronize
52 * the HW state and SW flags for a newly
53 * allocated descriptor).
55 * IRQ_TYPE_PROBE - Special flag for probing in progress
57 * Bits which can be modified via irq_set/clear/modify_status_flags()
58 * IRQ_LEVEL - Interrupt is level type. Will be also
59 * updated in the code when the above trigger
60 * bits are modified via irq_set_irq_type()
61 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect
62 * it from affinity setting
63 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing
64 * IRQ_NOREQUEST - Interrupt cannot be requested via
66 * IRQ_NOTHREAD - Interrupt cannot be threaded
67 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in
69 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set)
70 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context
71 * IRQ_NESTED_TRHEAD - Interrupt nests into another thread
72 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable
73 * IRQ_IS_POLLED - Always polled by another interrupt. Exclude
74 * it from the spurious interrupt detection
75 * mechanism and from core side polling.
78 IRQ_TYPE_NONE
= 0x00000000,
79 IRQ_TYPE_EDGE_RISING
= 0x00000001,
80 IRQ_TYPE_EDGE_FALLING
= 0x00000002,
81 IRQ_TYPE_EDGE_BOTH
= (IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
),
82 IRQ_TYPE_LEVEL_HIGH
= 0x00000004,
83 IRQ_TYPE_LEVEL_LOW
= 0x00000008,
84 IRQ_TYPE_LEVEL_MASK
= (IRQ_TYPE_LEVEL_LOW
| IRQ_TYPE_LEVEL_HIGH
),
85 IRQ_TYPE_SENSE_MASK
= 0x0000000f,
86 IRQ_TYPE_DEFAULT
= IRQ_TYPE_SENSE_MASK
,
88 IRQ_TYPE_PROBE
= 0x00000010,
91 IRQ_PER_CPU
= (1 << 9),
92 IRQ_NOPROBE
= (1 << 10),
93 IRQ_NOREQUEST
= (1 << 11),
94 IRQ_NOAUTOEN
= (1 << 12),
95 IRQ_NO_BALANCING
= (1 << 13),
96 IRQ_MOVE_PCNTXT
= (1 << 14),
97 IRQ_NESTED_THREAD
= (1 << 15),
98 IRQ_NOTHREAD
= (1 << 16),
99 IRQ_PER_CPU_DEVID
= (1 << 17),
100 IRQ_IS_POLLED
= (1 << 18),
103 #define IRQF_MODIFY_MASK \
104 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \
105 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \
106 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \
109 #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING)
112 * Return value for chip->irq_set_affinity()
114 * IRQ_SET_MASK_OK - OK, core updates irq_data.affinity
115 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_data.affinity
119 IRQ_SET_MASK_OK_NOCOPY
,
126 * struct irq_data - per irq and irq chip data passed down to chip functions
127 * @mask: precomputed bitmask for accessing the chip registers
128 * @irq: interrupt number
129 * @hwirq: hardware interrupt number, local to the interrupt domain
130 * @node: node index useful for balancing
131 * @state_use_accessors: status information for irq chip functions.
132 * Use accessor functions to deal with it
133 * @chip: low level interrupt hardware access
134 * @domain: Interrupt translation domain; responsible for mapping
135 * between hwirq number and linux irq number.
136 * @handler_data: per-IRQ data for the irq_chip methods
137 * @chip_data: platform-specific per-chip private data for the chip
138 * methods, to allow shared chip implementations
139 * @msi_desc: MSI descriptor
140 * @affinity: IRQ affinity on SMP
142 * The fields here need to overlay the ones in irq_desc until we
143 * cleaned up the direct references and switched everything over to
151 unsigned int state_use_accessors
;
152 struct irq_chip
*chip
;
153 struct irq_domain
*domain
;
156 struct msi_desc
*msi_desc
;
157 cpumask_var_t affinity
;
161 * Bit masks for irq_data.state
163 * IRQD_TRIGGER_MASK - Mask for the trigger type bits
164 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending
165 * IRQD_NO_BALANCING - Balancing disabled for this IRQ
166 * IRQD_PER_CPU - Interrupt is per cpu
167 * IRQD_AFFINITY_SET - Interrupt affinity was set
168 * IRQD_LEVEL - Interrupt is level triggered
169 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup
171 * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process
173 * IRQD_IRQ_DISABLED - Disabled state of the interrupt
174 * IRQD_IRQ_MASKED - Masked state of the interrupt
175 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt
178 IRQD_TRIGGER_MASK
= 0xf,
179 IRQD_SETAFFINITY_PENDING
= (1 << 8),
180 IRQD_NO_BALANCING
= (1 << 10),
181 IRQD_PER_CPU
= (1 << 11),
182 IRQD_AFFINITY_SET
= (1 << 12),
183 IRQD_LEVEL
= (1 << 13),
184 IRQD_WAKEUP_STATE
= (1 << 14),
185 IRQD_MOVE_PCNTXT
= (1 << 15),
186 IRQD_IRQ_DISABLED
= (1 << 16),
187 IRQD_IRQ_MASKED
= (1 << 17),
188 IRQD_IRQ_INPROGRESS
= (1 << 18),
191 static inline bool irqd_is_setaffinity_pending(struct irq_data
*d
)
193 return d
->state_use_accessors
& IRQD_SETAFFINITY_PENDING
;
196 static inline bool irqd_is_per_cpu(struct irq_data
*d
)
198 return d
->state_use_accessors
& IRQD_PER_CPU
;
201 static inline bool irqd_can_balance(struct irq_data
*d
)
203 return !(d
->state_use_accessors
& (IRQD_PER_CPU
| IRQD_NO_BALANCING
));
206 static inline bool irqd_affinity_was_set(struct irq_data
*d
)
208 return d
->state_use_accessors
& IRQD_AFFINITY_SET
;
211 static inline void irqd_mark_affinity_was_set(struct irq_data
*d
)
213 d
->state_use_accessors
|= IRQD_AFFINITY_SET
;
216 static inline u32
irqd_get_trigger_type(struct irq_data
*d
)
218 return d
->state_use_accessors
& IRQD_TRIGGER_MASK
;
222 * Must only be called inside irq_chip.irq_set_type() functions.
224 static inline void irqd_set_trigger_type(struct irq_data
*d
, u32 type
)
226 d
->state_use_accessors
&= ~IRQD_TRIGGER_MASK
;
227 d
->state_use_accessors
|= type
& IRQD_TRIGGER_MASK
;
230 static inline bool irqd_is_level_type(struct irq_data
*d
)
232 return d
->state_use_accessors
& IRQD_LEVEL
;
235 static inline bool irqd_is_wakeup_set(struct irq_data
*d
)
237 return d
->state_use_accessors
& IRQD_WAKEUP_STATE
;
240 static inline bool irqd_can_move_in_process_context(struct irq_data
*d
)
242 return d
->state_use_accessors
& IRQD_MOVE_PCNTXT
;
245 static inline bool irqd_irq_disabled(struct irq_data
*d
)
247 return d
->state_use_accessors
& IRQD_IRQ_DISABLED
;
250 static inline bool irqd_irq_masked(struct irq_data
*d
)
252 return d
->state_use_accessors
& IRQD_IRQ_MASKED
;
255 static inline bool irqd_irq_inprogress(struct irq_data
*d
)
257 return d
->state_use_accessors
& IRQD_IRQ_INPROGRESS
;
261 * Functions for chained handlers which can be enabled/disabled by the
262 * standard disable_irq/enable_irq calls. Must be called with
263 * irq_desc->lock held.
265 static inline void irqd_set_chained_irq_inprogress(struct irq_data
*d
)
267 d
->state_use_accessors
|= IRQD_IRQ_INPROGRESS
;
270 static inline void irqd_clr_chained_irq_inprogress(struct irq_data
*d
)
272 d
->state_use_accessors
&= ~IRQD_IRQ_INPROGRESS
;
275 static inline irq_hw_number_t
irqd_to_hwirq(struct irq_data
*d
)
281 * struct irq_chip - hardware interrupt chip descriptor
283 * @name: name for /proc/interrupts
284 * @irq_startup: start up the interrupt (defaults to ->enable if NULL)
285 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL)
286 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL)
287 * @irq_disable: disable the interrupt
288 * @irq_ack: start of a new interrupt
289 * @irq_mask: mask an interrupt source
290 * @irq_mask_ack: ack and mask an interrupt source
291 * @irq_unmask: unmask an interrupt source
292 * @irq_eoi: end of interrupt
293 * @irq_set_affinity: set the CPU affinity on SMP machines
294 * @irq_retrigger: resend an IRQ to the CPU
295 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
296 * @irq_set_wake: enable/disable power-management wake-on of an IRQ
297 * @irq_bus_lock: function to lock access to slow bus (i2c) chips
298 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips
299 * @irq_cpu_online: configure an interrupt source for a secondary CPU
300 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU
301 * @irq_suspend: function called from core code on suspend once per chip
302 * @irq_resume: function called from core code on resume once per chip
303 * @irq_pm_shutdown: function called from core code on shutdown once per chip
304 * @irq_calc_mask: Optional function to set irq_data.mask for special cases
305 * @irq_print_chip: optional to print special chip info in show_interrupts
306 * @irq_request_resources: optional to request resources before calling
307 * any other callback related to this irq
308 * @irq_release_resources: optional to release resources acquired with
309 * irq_request_resources
310 * @flags: chip specific flags
314 unsigned int (*irq_startup
)(struct irq_data
*data
);
315 void (*irq_shutdown
)(struct irq_data
*data
);
316 void (*irq_enable
)(struct irq_data
*data
);
317 void (*irq_disable
)(struct irq_data
*data
);
319 void (*irq_ack
)(struct irq_data
*data
);
320 void (*irq_mask
)(struct irq_data
*data
);
321 void (*irq_mask_ack
)(struct irq_data
*data
);
322 void (*irq_unmask
)(struct irq_data
*data
);
323 void (*irq_eoi
)(struct irq_data
*data
);
325 int (*irq_set_affinity
)(struct irq_data
*data
, const struct cpumask
*dest
, bool force
);
326 int (*irq_retrigger
)(struct irq_data
*data
);
327 int (*irq_set_type
)(struct irq_data
*data
, unsigned int flow_type
);
328 int (*irq_set_wake
)(struct irq_data
*data
, unsigned int on
);
330 void (*irq_bus_lock
)(struct irq_data
*data
);
331 void (*irq_bus_sync_unlock
)(struct irq_data
*data
);
333 void (*irq_cpu_online
)(struct irq_data
*data
);
334 void (*irq_cpu_offline
)(struct irq_data
*data
);
336 void (*irq_suspend
)(struct irq_data
*data
);
337 void (*irq_resume
)(struct irq_data
*data
);
338 void (*irq_pm_shutdown
)(struct irq_data
*data
);
340 void (*irq_calc_mask
)(struct irq_data
*data
);
342 void (*irq_print_chip
)(struct irq_data
*data
, struct seq_file
*p
);
343 int (*irq_request_resources
)(struct irq_data
*data
);
344 void (*irq_release_resources
)(struct irq_data
*data
);
350 * irq_chip specific flags
352 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type()
353 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled
354 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path
355 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks
357 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip
358 * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask
359 * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode
362 IRQCHIP_SET_TYPE_MASKED
= (1 << 0),
363 IRQCHIP_EOI_IF_HANDLED
= (1 << 1),
364 IRQCHIP_MASK_ON_SUSPEND
= (1 << 2),
365 IRQCHIP_ONOFFLINE_ENABLED
= (1 << 3),
366 IRQCHIP_SKIP_SET_WAKE
= (1 << 4),
367 IRQCHIP_ONESHOT_SAFE
= (1 << 5),
368 IRQCHIP_EOI_THREADED
= (1 << 6),
371 /* This include will go away once we isolated irq_desc usage to core code */
372 #include <linux/irqdesc.h>
375 * Pick up the arch-dependent methods:
377 #include <asm/hw_irq.h>
379 #ifndef NR_IRQS_LEGACY
380 # define NR_IRQS_LEGACY 0
383 #ifndef ARCH_IRQ_INIT_FLAGS
384 # define ARCH_IRQ_INIT_FLAGS 0
387 #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS
390 extern int setup_irq(unsigned int irq
, struct irqaction
*new);
391 extern void remove_irq(unsigned int irq
, struct irqaction
*act
);
392 extern int setup_percpu_irq(unsigned int irq
, struct irqaction
*new);
393 extern void remove_percpu_irq(unsigned int irq
, struct irqaction
*act
);
395 extern void irq_cpu_online(void);
396 extern void irq_cpu_offline(void);
397 extern int irq_set_affinity_locked(struct irq_data
*data
,
398 const struct cpumask
*cpumask
, bool force
);
400 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
401 void irq_move_irq(struct irq_data
*data
);
402 void irq_move_masked_irq(struct irq_data
*data
);
404 static inline void irq_move_irq(struct irq_data
*data
) { }
405 static inline void irq_move_masked_irq(struct irq_data
*data
) { }
408 extern int no_irq_affinity
;
410 #ifdef CONFIG_HARDIRQS_SW_RESEND
411 int irq_set_parent(int irq
, int parent_irq
);
413 static inline int irq_set_parent(int irq
, int parent_irq
)
420 * Built-in IRQ handlers for various IRQ types,
421 * callable via desc->handle_irq()
423 extern void handle_level_irq(unsigned int irq
, struct irq_desc
*desc
);
424 extern void handle_fasteoi_irq(unsigned int irq
, struct irq_desc
*desc
);
425 extern void handle_edge_irq(unsigned int irq
, struct irq_desc
*desc
);
426 extern void handle_edge_eoi_irq(unsigned int irq
, struct irq_desc
*desc
);
427 extern void handle_simple_irq(unsigned int irq
, struct irq_desc
*desc
);
428 extern void handle_percpu_irq(unsigned int irq
, struct irq_desc
*desc
);
429 extern void handle_percpu_devid_irq(unsigned int irq
, struct irq_desc
*desc
);
430 extern void handle_bad_irq(unsigned int irq
, struct irq_desc
*desc
);
431 extern void handle_nested_irq(unsigned int irq
);
433 /* Handling of unhandled and spurious interrupts: */
434 extern void note_interrupt(unsigned int irq
, struct irq_desc
*desc
,
435 irqreturn_t action_ret
);
438 /* Enable/disable irq debugging output: */
439 extern int noirqdebug_setup(char *str
);
441 /* Checks whether the interrupt can be requested by request_irq(): */
442 extern int can_request_irq(unsigned int irq
, unsigned long irqflags
);
444 /* Dummy irq-chip implementations: */
445 extern struct irq_chip no_irq_chip
;
446 extern struct irq_chip dummy_irq_chip
;
449 irq_set_chip_and_handler_name(unsigned int irq
, struct irq_chip
*chip
,
450 irq_flow_handler_t handle
, const char *name
);
452 static inline void irq_set_chip_and_handler(unsigned int irq
, struct irq_chip
*chip
,
453 irq_flow_handler_t handle
)
455 irq_set_chip_and_handler_name(irq
, chip
, handle
, NULL
);
458 extern int irq_set_percpu_devid(unsigned int irq
);
461 __irq_set_handler(unsigned int irq
, irq_flow_handler_t handle
, int is_chained
,
465 irq_set_handler(unsigned int irq
, irq_flow_handler_t handle
)
467 __irq_set_handler(irq
, handle
, 0, NULL
);
471 * Set a highlevel chained flow handler for a given IRQ.
472 * (a chained handler is automatically enabled and set to
473 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
476 irq_set_chained_handler(unsigned int irq
, irq_flow_handler_t handle
)
478 __irq_set_handler(irq
, handle
, 1, NULL
);
481 void irq_modify_status(unsigned int irq
, unsigned long clr
, unsigned long set
);
483 static inline void irq_set_status_flags(unsigned int irq
, unsigned long set
)
485 irq_modify_status(irq
, 0, set
);
488 static inline void irq_clear_status_flags(unsigned int irq
, unsigned long clr
)
490 irq_modify_status(irq
, clr
, 0);
493 static inline void irq_set_noprobe(unsigned int irq
)
495 irq_modify_status(irq
, 0, IRQ_NOPROBE
);
498 static inline void irq_set_probe(unsigned int irq
)
500 irq_modify_status(irq
, IRQ_NOPROBE
, 0);
503 static inline void irq_set_nothread(unsigned int irq
)
505 irq_modify_status(irq
, 0, IRQ_NOTHREAD
);
508 static inline void irq_set_thread(unsigned int irq
)
510 irq_modify_status(irq
, IRQ_NOTHREAD
, 0);
513 static inline void irq_set_nested_thread(unsigned int irq
, bool nest
)
516 irq_set_status_flags(irq
, IRQ_NESTED_THREAD
);
518 irq_clear_status_flags(irq
, IRQ_NESTED_THREAD
);
521 static inline void irq_set_percpu_devid_flags(unsigned int irq
)
523 irq_set_status_flags(irq
,
524 IRQ_NOAUTOEN
| IRQ_PER_CPU
| IRQ_NOTHREAD
|
525 IRQ_NOPROBE
| IRQ_PER_CPU_DEVID
);
528 /* Set/get chip/data for an IRQ: */
529 extern int irq_set_chip(unsigned int irq
, struct irq_chip
*chip
);
530 extern int irq_set_handler_data(unsigned int irq
, void *data
);
531 extern int irq_set_chip_data(unsigned int irq
, void *data
);
532 extern int irq_set_irq_type(unsigned int irq
, unsigned int type
);
533 extern int irq_set_msi_desc(unsigned int irq
, struct msi_desc
*entry
);
534 extern int irq_set_msi_desc_off(unsigned int irq_base
, unsigned int irq_offset
,
535 struct msi_desc
*entry
);
536 extern struct irq_data
*irq_get_irq_data(unsigned int irq
);
538 static inline struct irq_chip
*irq_get_chip(unsigned int irq
)
540 struct irq_data
*d
= irq_get_irq_data(irq
);
541 return d
? d
->chip
: NULL
;
544 static inline struct irq_chip
*irq_data_get_irq_chip(struct irq_data
*d
)
549 static inline void *irq_get_chip_data(unsigned int irq
)
551 struct irq_data
*d
= irq_get_irq_data(irq
);
552 return d
? d
->chip_data
: NULL
;
555 static inline void *irq_data_get_irq_chip_data(struct irq_data
*d
)
560 static inline void *irq_get_handler_data(unsigned int irq
)
562 struct irq_data
*d
= irq_get_irq_data(irq
);
563 return d
? d
->handler_data
: NULL
;
566 static inline void *irq_data_get_irq_handler_data(struct irq_data
*d
)
568 return d
->handler_data
;
571 static inline struct msi_desc
*irq_get_msi_desc(unsigned int irq
)
573 struct irq_data
*d
= irq_get_irq_data(irq
);
574 return d
? d
->msi_desc
: NULL
;
577 static inline struct msi_desc
*irq_data_get_msi(struct irq_data
*d
)
582 static inline u32
irq_get_trigger_type(unsigned int irq
)
584 struct irq_data
*d
= irq_get_irq_data(irq
);
585 return d
? irqd_get_trigger_type(d
) : 0;
588 unsigned int arch_dynirq_lower_bound(unsigned int from
);
590 int __irq_alloc_descs(int irq
, unsigned int from
, unsigned int cnt
, int node
,
591 struct module
*owner
);
593 /* use macros to avoid needing export.h for THIS_MODULE */
594 #define irq_alloc_descs(irq, from, cnt, node) \
595 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE)
597 #define irq_alloc_desc(node) \
598 irq_alloc_descs(-1, 0, 1, node)
600 #define irq_alloc_desc_at(at, node) \
601 irq_alloc_descs(at, at, 1, node)
603 #define irq_alloc_desc_from(from, node) \
604 irq_alloc_descs(-1, from, 1, node)
606 #define irq_alloc_descs_from(from, cnt, node) \
607 irq_alloc_descs(-1, from, cnt, node)
609 void irq_free_descs(unsigned int irq
, unsigned int cnt
);
610 static inline void irq_free_desc(unsigned int irq
)
612 irq_free_descs(irq
, 1);
615 #ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ
616 unsigned int irq_alloc_hwirqs(int cnt
, int node
);
617 static inline unsigned int irq_alloc_hwirq(int node
)
619 return irq_alloc_hwirqs(1, node
);
621 void irq_free_hwirqs(unsigned int from
, int cnt
);
622 static inline void irq_free_hwirq(unsigned int irq
)
624 return irq_free_hwirqs(irq
, 1);
626 int arch_setup_hwirq(unsigned int irq
, int node
);
627 void arch_teardown_hwirq(unsigned int irq
);
630 #ifdef CONFIG_GENERIC_IRQ_LEGACY
631 void irq_init_desc(unsigned int irq
);
634 #ifndef irq_reg_writel
635 # define irq_reg_writel(val, addr) writel(val, addr)
637 #ifndef irq_reg_readl
638 # define irq_reg_readl(addr) readl(addr)
642 * struct irq_chip_regs - register offsets for struct irq_gci
643 * @enable: Enable register offset to reg_base
644 * @disable: Disable register offset to reg_base
645 * @mask: Mask register offset to reg_base
646 * @ack: Ack register offset to reg_base
647 * @eoi: Eoi register offset to reg_base
648 * @type: Type configuration register offset to reg_base
649 * @polarity: Polarity configuration register offset to reg_base
651 struct irq_chip_regs
{
652 unsigned long enable
;
653 unsigned long disable
;
658 unsigned long polarity
;
662 * struct irq_chip_type - Generic interrupt chip instance for a flow type
663 * @chip: The real interrupt chip which provides the callbacks
664 * @regs: Register offsets for this chip
665 * @handler: Flow handler associated with this chip
666 * @type: Chip can handle these flow types
667 * @mask_cache_priv: Cached mask register private to the chip type
668 * @mask_cache: Pointer to cached mask register
670 * A irq_generic_chip can have several instances of irq_chip_type when
671 * it requires different functions and register offsets for different
674 struct irq_chip_type
{
675 struct irq_chip chip
;
676 struct irq_chip_regs regs
;
677 irq_flow_handler_t handler
;
684 * struct irq_chip_generic - Generic irq chip data structure
685 * @lock: Lock to protect register and cache data access
686 * @reg_base: Register base address (virtual)
687 * @irq_base: Interrupt base nr for this chip
688 * @irq_cnt: Number of interrupts handled by this chip
689 * @mask_cache: Cached mask register shared between all chip types
690 * @type_cache: Cached type register
691 * @polarity_cache: Cached polarity register
692 * @wake_enabled: Interrupt can wakeup from suspend
693 * @wake_active: Interrupt is marked as an wakeup from suspend source
694 * @num_ct: Number of available irq_chip_type instances (usually 1)
695 * @private: Private data for non generic chip callbacks
696 * @installed: bitfield to denote installed interrupts
697 * @unused: bitfield to denote unused interrupts
698 * @domain: irq domain pointer
699 * @list: List head for keeping track of instances
700 * @chip_types: Array of interrupt irq_chip_types
702 * Note, that irq_chip_generic can have multiple irq_chip_type
703 * implementations which can be associated to a particular irq line of
704 * an irq_chip_generic instance. That allows to share and protect
705 * state in an irq_chip_generic instance when we need to implement
706 * different flow mechanisms (level/edge) for it.
708 struct irq_chip_generic
{
710 void __iomem
*reg_base
;
711 unsigned int irq_base
;
712 unsigned int irq_cnt
;
720 unsigned long installed
;
721 unsigned long unused
;
722 struct irq_domain
*domain
;
723 struct list_head list
;
724 struct irq_chip_type chip_types
[0];
728 * enum irq_gc_flags - Initialization flags for generic irq chips
729 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg
730 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for
731 * irq chips which need to call irq_set_wake() on
732 * the parent irq. Usually GPIO implementations
733 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private
734 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask
737 IRQ_GC_INIT_MASK_CACHE
= 1 << 0,
738 IRQ_GC_INIT_NESTED_LOCK
= 1 << 1,
739 IRQ_GC_MASK_CACHE_PER_TYPE
= 1 << 2,
740 IRQ_GC_NO_MASK
= 1 << 3,
744 * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains
745 * @irqs_per_chip: Number of interrupts per chip
746 * @num_chips: Number of chips
747 * @irq_flags_to_set: IRQ* flags to set on irq setup
748 * @irq_flags_to_clear: IRQ* flags to clear on irq setup
749 * @gc_flags: Generic chip specific setup flags
750 * @gc: Array of pointers to generic interrupt chips
752 struct irq_domain_chip_generic
{
753 unsigned int irqs_per_chip
;
754 unsigned int num_chips
;
755 unsigned int irq_flags_to_clear
;
756 unsigned int irq_flags_to_set
;
757 enum irq_gc_flags gc_flags
;
758 struct irq_chip_generic
*gc
[0];
761 /* Generic chip callback functions */
762 void irq_gc_noop(struct irq_data
*d
);
763 void irq_gc_mask_disable_reg(struct irq_data
*d
);
764 void irq_gc_mask_set_bit(struct irq_data
*d
);
765 void irq_gc_mask_clr_bit(struct irq_data
*d
);
766 void irq_gc_unmask_enable_reg(struct irq_data
*d
);
767 void irq_gc_ack_set_bit(struct irq_data
*d
);
768 void irq_gc_ack_clr_bit(struct irq_data
*d
);
769 void irq_gc_mask_disable_reg_and_ack(struct irq_data
*d
);
770 void irq_gc_eoi(struct irq_data
*d
);
771 int irq_gc_set_wake(struct irq_data
*d
, unsigned int on
);
773 /* Setup functions for irq_chip_generic */
774 int irq_map_generic_chip(struct irq_domain
*d
, unsigned int virq
,
775 irq_hw_number_t hw_irq
);
776 struct irq_chip_generic
*
777 irq_alloc_generic_chip(const char *name
, int nr_ct
, unsigned int irq_base
,
778 void __iomem
*reg_base
, irq_flow_handler_t handler
);
779 void irq_setup_generic_chip(struct irq_chip_generic
*gc
, u32 msk
,
780 enum irq_gc_flags flags
, unsigned int clr
,
782 int irq_setup_alt_chip(struct irq_data
*d
, unsigned int type
);
783 void irq_remove_generic_chip(struct irq_chip_generic
*gc
, u32 msk
,
784 unsigned int clr
, unsigned int set
);
786 struct irq_chip_generic
*irq_get_domain_generic_chip(struct irq_domain
*d
, unsigned int hw_irq
);
787 int irq_alloc_domain_generic_chips(struct irq_domain
*d
, int irqs_per_chip
,
788 int num_ct
, const char *name
,
789 irq_flow_handler_t handler
,
790 unsigned int clr
, unsigned int set
,
791 enum irq_gc_flags flags
);
794 static inline struct irq_chip_type
*irq_data_get_chip_type(struct irq_data
*d
)
796 return container_of(d
->chip
, struct irq_chip_type
, chip
);
799 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
802 static inline void irq_gc_lock(struct irq_chip_generic
*gc
)
804 raw_spin_lock(&gc
->lock
);
807 static inline void irq_gc_unlock(struct irq_chip_generic
*gc
)
809 raw_spin_unlock(&gc
->lock
);
812 static inline void irq_gc_lock(struct irq_chip_generic
*gc
) { }
813 static inline void irq_gc_unlock(struct irq_chip_generic
*gc
) { }
816 #endif /* _LINUX_IRQ_H */