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[ARM] S3C24XX: Split serial driver into core and per-cpu drivers
[linux-2.6/btrfs-unstable.git] / drivers / ata / ahci.c
blob6a4a2a25d97a6bd258f1fee4c7cad287d7ef8c0d
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
48
49 #define DRV_NAME "ahci"
50 #define DRV_VERSION "3.0"
51
52 static int ahci_skip_host_reset;
53 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
54 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
55
56 static int ahci_enable_alpm(struct ata_port *ap,
57 enum link_pm policy);
58 static void ahci_disable_alpm(struct ata_port *ap);
59
60 enum {
61 AHCI_PCI_BAR = 5,
62 AHCI_MAX_PORTS = 32,
63 AHCI_MAX_SG = 168, /* hardware max is 64K */
64 AHCI_DMA_BOUNDARY = 0xffffffff,
65 AHCI_MAX_CMDS = 32,
66 AHCI_CMD_SZ = 32,
67 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
68 AHCI_RX_FIS_SZ = 256,
69 AHCI_CMD_TBL_CDB = 0x40,
70 AHCI_CMD_TBL_HDR_SZ = 0x80,
71 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
72 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
73 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
74 AHCI_RX_FIS_SZ,
75 AHCI_IRQ_ON_SG = (1 << 31),
76 AHCI_CMD_ATAPI = (1 << 5),
77 AHCI_CMD_WRITE = (1 << 6),
78 AHCI_CMD_PREFETCH = (1 << 7),
79 AHCI_CMD_RESET = (1 << 8),
80 AHCI_CMD_CLR_BUSY = (1 << 10),
81
82 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
83 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
84 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
85
86 board_ahci = 0,
87 board_ahci_vt8251 = 1,
88 board_ahci_ign_iferr = 2,
89 board_ahci_sb600 = 3,
90 board_ahci_mv = 4,
91 board_ahci_sb700 = 5,
92 board_ahci_mcp65 = 6,
93 board_ahci_nopmp = 7,
94
95 /* global controller registers */
96 HOST_CAP = 0x00, /* host capabilities */
97 HOST_CTL = 0x04, /* global host control */
98 HOST_IRQ_STAT = 0x08, /* interrupt status */
99 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
100 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
101
102 /* HOST_CTL bits */
103 HOST_RESET = (1 << 0), /* reset controller; self-clear */
104 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
105 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
106
107 /* HOST_CAP bits */
108 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
109 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
110 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
111 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
112 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
113 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
114 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
115 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
116
117 /* registers for each SATA port */
118 PORT_LST_ADDR = 0x00, /* command list DMA addr */
119 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
120 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
121 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
122 PORT_IRQ_STAT = 0x10, /* interrupt status */
123 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
124 PORT_CMD = 0x18, /* port command */
125 PORT_TFDATA = 0x20, /* taskfile data */
126 PORT_SIG = 0x24, /* device TF signature */
127 PORT_CMD_ISSUE = 0x38, /* command issue */
128 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
129 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
130 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
131 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
132 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
133
134 /* PORT_IRQ_{STAT,MASK} bits */
135 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
136 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
137 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
138 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
139 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
140 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
141 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
142 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
143
144 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
145 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
146 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
147 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
148 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
149 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
150 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
151 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
152 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
153
154 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
155 PORT_IRQ_IF_ERR |
156 PORT_IRQ_CONNECT |
157 PORT_IRQ_PHYRDY |
158 PORT_IRQ_UNK_FIS |
159 PORT_IRQ_BAD_PMP,
160 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
161 PORT_IRQ_TF_ERR |
162 PORT_IRQ_HBUS_DATA_ERR,
163 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
164 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
165 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
166
167 /* PORT_CMD bits */
168 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
169 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
170 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
171 PORT_CMD_PMP = (1 << 17), /* PMP attached */
172 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
173 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
174 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
175 PORT_CMD_CLO = (1 << 3), /* Command list override */
176 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
177 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
178 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
179
180 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
181 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
182 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
183 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
184
185 /* hpriv->flags bits */
186 AHCI_HFLAG_NO_NCQ = (1 << 0),
187 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
188 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
189 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
190 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
191 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
192 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
193 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
194 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
195 AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */
196
197 /* ap->flags bits */
198
199 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
200 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
201 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
202 ATA_FLAG_IPM,
203
204 ICH_MAP = 0x90, /* ICH MAP register */
205 };
206
207 struct ahci_cmd_hdr {
208 __le32 opts;
209 __le32 status;
210 __le32 tbl_addr;
211 __le32 tbl_addr_hi;
212 __le32 reserved[4];
213 };
214
215 struct ahci_sg {
216 __le32 addr;
217 __le32 addr_hi;
218 __le32 reserved;
219 __le32 flags_size;
220 };
221
222 struct ahci_host_priv {
223 unsigned int flags; /* AHCI_HFLAG_* */
224 u32 cap; /* cap to use */
225 u32 port_map; /* port map to use */
226 u32 saved_cap; /* saved initial cap */
227 u32 saved_port_map; /* saved initial port_map */
228 };
229
230 struct ahci_port_priv {
231 struct ata_link *active_link;
232 struct ahci_cmd_hdr *cmd_slot;
233 dma_addr_t cmd_slot_dma;
234 void *cmd_tbl;
235 dma_addr_t cmd_tbl_dma;
236 void *rx_fis;
237 dma_addr_t rx_fis_dma;
238 /* for NCQ spurious interrupt analysis */
239 unsigned int ncq_saw_d2h:1;
240 unsigned int ncq_saw_dmas:1;
241 unsigned int ncq_saw_sdb:1;
242 u32 intr_mask; /* interrupts to enable */
243 };
244
245 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
246 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
247 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
248 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
249 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
250 static int ahci_port_start(struct ata_port *ap);
251 static void ahci_port_stop(struct ata_port *ap);
252 static void ahci_qc_prep(struct ata_queued_cmd *qc);
253 static void ahci_freeze(struct ata_port *ap);
254 static void ahci_thaw(struct ata_port *ap);
255 static void ahci_pmp_attach(struct ata_port *ap);
256 static void ahci_pmp_detach(struct ata_port *ap);
257 static int ahci_softreset(struct ata_link *link, unsigned int *class,
258 unsigned long deadline);
259 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
260 unsigned long deadline);
261 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
262 unsigned long deadline);
263 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
264 unsigned long deadline);
265 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
266 unsigned long deadline);
267 static void ahci_postreset(struct ata_link *link, unsigned int *class);
268 static void ahci_error_handler(struct ata_port *ap);
269 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
270 static int ahci_port_resume(struct ata_port *ap);
271 static void ahci_dev_config(struct ata_device *dev);
272 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
273 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
274 u32 opts);
275 #ifdef CONFIG_PM
276 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
277 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
278 static int ahci_pci_device_resume(struct pci_dev *pdev);
279 #endif
280
281 static struct device_attribute *ahci_shost_attrs[] = {
282 &dev_attr_link_power_management_policy,
283 NULL
284 };
285
286 static struct scsi_host_template ahci_sht = {
287 ATA_NCQ_SHT(DRV_NAME),
288 .can_queue = AHCI_MAX_CMDS - 1,
289 .sg_tablesize = AHCI_MAX_SG,
290 .dma_boundary = AHCI_DMA_BOUNDARY,
291 .shost_attrs = ahci_shost_attrs,
292 };
293
294 static struct ata_port_operations ahci_ops = {
295 .inherits = &sata_pmp_port_ops,
296
297 .qc_defer = sata_pmp_qc_defer_cmd_switch,
298 .qc_prep = ahci_qc_prep,
299 .qc_issue = ahci_qc_issue,
300 .qc_fill_rtf = ahci_qc_fill_rtf,
301
302 .freeze = ahci_freeze,
303 .thaw = ahci_thaw,
304 .softreset = ahci_softreset,
305 .hardreset = ahci_hardreset,
306 .postreset = ahci_postreset,
307 .pmp_softreset = ahci_softreset,
308 .error_handler = ahci_error_handler,
309 .post_internal_cmd = ahci_post_internal_cmd,
310 .dev_config = ahci_dev_config,
311
312 .scr_read = ahci_scr_read,
313 .scr_write = ahci_scr_write,
314 .pmp_attach = ahci_pmp_attach,
315 .pmp_detach = ahci_pmp_detach,
316
317 .enable_pm = ahci_enable_alpm,
318 .disable_pm = ahci_disable_alpm,
319 #ifdef CONFIG_PM
320 .port_suspend = ahci_port_suspend,
321 .port_resume = ahci_port_resume,
322 #endif
323 .port_start = ahci_port_start,
324 .port_stop = ahci_port_stop,
325 };
326
327 static struct ata_port_operations ahci_vt8251_ops = {
328 .inherits = &ahci_ops,
329 .hardreset = ahci_vt8251_hardreset,
330 };
331
332 static struct ata_port_operations ahci_p5wdh_ops = {
333 .inherits = &ahci_ops,
334 .hardreset = ahci_p5wdh_hardreset,
335 };
336
337 static struct ata_port_operations ahci_sb600_ops = {
338 .inherits = &ahci_ops,
339 .softreset = ahci_sb600_softreset,
340 .pmp_softreset = ahci_sb600_softreset,
341 };
342
343 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
344
345 static const struct ata_port_info ahci_port_info[] = {
346 /* board_ahci */
347 {
348 .flags = AHCI_FLAG_COMMON,
349 .pio_mask = 0x1f, /* pio0-4 */
350 .udma_mask = ATA_UDMA6,
351 .port_ops = &ahci_ops,
352 },
353 /* board_ahci_vt8251 */
354 {
355 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
356 .flags = AHCI_FLAG_COMMON,
357 .pio_mask = 0x1f, /* pio0-4 */
358 .udma_mask = ATA_UDMA6,
359 .port_ops = &ahci_vt8251_ops,
360 },
361 /* board_ahci_ign_iferr */
362 {
363 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
364 .flags = AHCI_FLAG_COMMON,
365 .pio_mask = 0x1f, /* pio0-4 */
366 .udma_mask = ATA_UDMA6,
367 .port_ops = &ahci_ops,
368 },
369 /* board_ahci_sb600 */
370 {
371 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
372 AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI |
373 AHCI_HFLAG_SECT255),
374 .flags = AHCI_FLAG_COMMON,
375 .pio_mask = 0x1f, /* pio0-4 */
376 .udma_mask = ATA_UDMA6,
377 .port_ops = &ahci_sb600_ops,
378 },
379 /* board_ahci_mv */
380 {
381 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
382 AHCI_HFLAG_MV_PATA),
383 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
384 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
385 .pio_mask = 0x1f, /* pio0-4 */
386 .udma_mask = ATA_UDMA6,
387 .port_ops = &ahci_ops,
388 },
389 /* board_ahci_sb700 */
390 {
391 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
392 .flags = AHCI_FLAG_COMMON,
393 .pio_mask = 0x1f, /* pio0-4 */
394 .udma_mask = ATA_UDMA6,
395 .port_ops = &ahci_sb600_ops,
396 },
397 /* board_ahci_mcp65 */
398 {
399 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
400 .flags = AHCI_FLAG_COMMON,
401 .pio_mask = 0x1f, /* pio0-4 */
402 .udma_mask = ATA_UDMA6,
403 .port_ops = &ahci_ops,
404 },
405 /* board_ahci_nopmp */
406 {
407 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP),
408 .flags = AHCI_FLAG_COMMON,
409 .pio_mask = 0x1f, /* pio0-4 */
410 .udma_mask = ATA_UDMA6,
411 .port_ops = &ahci_ops,
412 },
413 };
414
415 static const struct pci_device_id ahci_pci_tbl[] = {
416 /* Intel */
417 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
418 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
419 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
420 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
421 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
422 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
423 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
424 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
425 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
426 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
427 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
428 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
429 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
430 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
431 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
432 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
433 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
434 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
435 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
436 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
437 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
438 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
439 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
440 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
441 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
442 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
443 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
444 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
445 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
446 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
447 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
448
449 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
450 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
451 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
452
453 /* ATI */
454 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
455 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
456 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
457 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
458 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
459 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
460 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
461
462 /* VIA */
463 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
464 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
465
466 /* NVIDIA */
467 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
468 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
469 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
470 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
471 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
472 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
473 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
474 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
475 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
476 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
477 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
478 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
479 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
480 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
481 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
482 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
483 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
484 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
485 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
486 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
487 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
488 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
489 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
490 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
491 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
492 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
493 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
494 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
495 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
496 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
497 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
498 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
499 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
500 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
501 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
502 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
503 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
504 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
505 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
506 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
507 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
508 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
509 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
510 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
511 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
512 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
513 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
514 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
515 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
516 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
517 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
518 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
519 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
520 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
521 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
522 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
523 { PCI_VDEVICE(NVIDIA, 0x0bc8), board_ahci }, /* MCP7B */
524 { PCI_VDEVICE(NVIDIA, 0x0bc9), board_ahci }, /* MCP7B */
525 { PCI_VDEVICE(NVIDIA, 0x0bca), board_ahci }, /* MCP7B */
526 { PCI_VDEVICE(NVIDIA, 0x0bcb), board_ahci }, /* MCP7B */
527 { PCI_VDEVICE(NVIDIA, 0x0bcc), board_ahci }, /* MCP7B */
528 { PCI_VDEVICE(NVIDIA, 0x0bcd), board_ahci }, /* MCP7B */
529 { PCI_VDEVICE(NVIDIA, 0x0bce), board_ahci }, /* MCP7B */
530 { PCI_VDEVICE(NVIDIA, 0x0bcf), board_ahci }, /* MCP7B */
531 { PCI_VDEVICE(NVIDIA, 0x0bc4), board_ahci }, /* MCP7B */
532 { PCI_VDEVICE(NVIDIA, 0x0bc5), board_ahci }, /* MCP7B */
533 { PCI_VDEVICE(NVIDIA, 0x0bc6), board_ahci }, /* MCP7B */
534 { PCI_VDEVICE(NVIDIA, 0x0bc7), board_ahci }, /* MCP7B */
535
536 /* SiS */
537 { PCI_VDEVICE(SI, 0x1184), board_ahci_nopmp }, /* SiS 966 */
538 { PCI_VDEVICE(SI, 0x1185), board_ahci_nopmp }, /* SiS 968 */
539 { PCI_VDEVICE(SI, 0x0186), board_ahci_nopmp }, /* SiS 968 */
540
541 /* Marvell */
542 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
543 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
544
545 /* Generic, PCI class code for AHCI */
546 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
547 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
548
549 { } /* terminate list */
550 };
551
552
553 static struct pci_driver ahci_pci_driver = {
554 .name = DRV_NAME,
555 .id_table = ahci_pci_tbl,
556 .probe = ahci_init_one,
557 .remove = ata_pci_remove_one,
558 #ifdef CONFIG_PM
559 .suspend = ahci_pci_device_suspend,
560 .resume = ahci_pci_device_resume,
561 #endif
562 };
563
564
565 static inline int ahci_nr_ports(u32 cap)
566 {
567 return (cap & 0x1f) + 1;
568 }
569
570 static inline void __iomem *__ahci_port_base(struct ata_host *host,
571 unsigned int port_no)
572 {
573 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
574
575 return mmio + 0x100 + (port_no * 0x80);
576 }
577
578 static inline void __iomem *ahci_port_base(struct ata_port *ap)
579 {
580 return __ahci_port_base(ap->host, ap->port_no);
581 }
582
583 static void ahci_enable_ahci(void __iomem *mmio)
584 {
585 int i;
586 u32 tmp;
587
588 /* turn on AHCI_EN */
589 tmp = readl(mmio + HOST_CTL);
590 if (tmp & HOST_AHCI_EN)
591 return;
592
593 /* Some controllers need AHCI_EN to be written multiple times.
594 * Try a few times before giving up.
595 */
596 for (i = 0; i < 5; i++) {
597 tmp |= HOST_AHCI_EN;
598 writel(tmp, mmio + HOST_CTL);
599 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
600 if (tmp & HOST_AHCI_EN)
601 return;
602 msleep(10);
603 }
604
605 WARN_ON(1);
606 }
607
608 /**
609 * ahci_save_initial_config - Save and fixup initial config values
610 * @pdev: target PCI device
611 * @hpriv: host private area to store config values
612 *
613 * Some registers containing configuration info might be setup by
614 * BIOS and might be cleared on reset. This function saves the
615 * initial values of those registers into @hpriv such that they
616 * can be restored after controller reset.
617 *
618 * If inconsistent, config values are fixed up by this function.
619 *
620 * LOCKING:
621 * None.
622 */
623 static void ahci_save_initial_config(struct pci_dev *pdev,
624 struct ahci_host_priv *hpriv)
625 {
626 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
627 u32 cap, port_map;
628 int i;
629 int mv;
630
631 /* make sure AHCI mode is enabled before accessing CAP */
632 ahci_enable_ahci(mmio);
633
634 /* Values prefixed with saved_ are written back to host after
635 * reset. Values without are used for driver operation.
636 */
637 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
638 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
639
640 /* some chips have errata preventing 64bit use */
641 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
642 dev_printk(KERN_INFO, &pdev->dev,
643 "controller can't do 64bit DMA, forcing 32bit\n");
644 cap &= ~HOST_CAP_64;
645 }
646
647 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
648 dev_printk(KERN_INFO, &pdev->dev,
649 "controller can't do NCQ, turning off CAP_NCQ\n");
650 cap &= ~HOST_CAP_NCQ;
651 }
652
653 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
654 dev_printk(KERN_INFO, &pdev->dev,
655 "controller can do NCQ, turning on CAP_NCQ\n");
656 cap |= HOST_CAP_NCQ;
657 }
658
659 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
660 dev_printk(KERN_INFO, &pdev->dev,
661 "controller can't do PMP, turning off CAP_PMP\n");
662 cap &= ~HOST_CAP_PMP;
663 }
664
665 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 &&
666 port_map != 1) {
667 dev_printk(KERN_INFO, &pdev->dev,
668 "JMB361 has only one port, port_map 0x%x -> 0x%x\n",
669 port_map, 1);
670 port_map = 1;
671 }
672
673 /*
674 * Temporary Marvell 6145 hack: PATA port presence
675 * is asserted through the standard AHCI port
676 * presence register, as bit 4 (counting from 0)
677 */
678 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
679 if (pdev->device == 0x6121)
680 mv = 0x3;
681 else
682 mv = 0xf;
683 dev_printk(KERN_ERR, &pdev->dev,
684 "MV_AHCI HACK: port_map %x -> %x\n",
685 port_map,
686 port_map & mv);
687
688 port_map &= mv;
689 }
690
691 /* cross check port_map and cap.n_ports */
692 if (port_map) {
693 int map_ports = 0;
694
695 for (i = 0; i < AHCI_MAX_PORTS; i++)
696 if (port_map & (1 << i))
697 map_ports++;
698
699 /* If PI has more ports than n_ports, whine, clear
700 * port_map and let it be generated from n_ports.
701 */
702 if (map_ports > ahci_nr_ports(cap)) {
703 dev_printk(KERN_WARNING, &pdev->dev,
704 "implemented port map (0x%x) contains more "
705 "ports than nr_ports (%u), using nr_ports\n",
706 port_map, ahci_nr_ports(cap));
707 port_map = 0;
708 }
709 }
710
711 /* fabricate port_map from cap.nr_ports */
712 if (!port_map) {
713 port_map = (1 << ahci_nr_ports(cap)) - 1;
714 dev_printk(KERN_WARNING, &pdev->dev,
715 "forcing PORTS_IMPL to 0x%x\n", port_map);
716
717 /* write the fixed up value to the PI register */
718 hpriv->saved_port_map = port_map;
719 }
720
721 /* record values to use during operation */
722 hpriv->cap = cap;
723 hpriv->port_map = port_map;
724 }
725
726 /**
727 * ahci_restore_initial_config - Restore initial config
728 * @host: target ATA host
729 *
730 * Restore initial config stored by ahci_save_initial_config().
731 *
732 * LOCKING:
733 * None.
734 */
735 static void ahci_restore_initial_config(struct ata_host *host)
736 {
737 struct ahci_host_priv *hpriv = host->private_data;
738 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
739
740 writel(hpriv->saved_cap, mmio + HOST_CAP);
741 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
742 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
743 }
744
745 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
746 {
747 static const int offset[] = {
748 [SCR_STATUS] = PORT_SCR_STAT,
749 [SCR_CONTROL] = PORT_SCR_CTL,
750 [SCR_ERROR] = PORT_SCR_ERR,
751 [SCR_ACTIVE] = PORT_SCR_ACT,
752 [SCR_NOTIFICATION] = PORT_SCR_NTF,
753 };
754 struct ahci_host_priv *hpriv = ap->host->private_data;
755
756 if (sc_reg < ARRAY_SIZE(offset) &&
757 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
758 return offset[sc_reg];
759 return 0;
760 }
761
762 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
763 {
764 void __iomem *port_mmio = ahci_port_base(ap);
765 int offset = ahci_scr_offset(ap, sc_reg);
766
767 if (offset) {
768 *val = readl(port_mmio + offset);
769 return 0;
770 }
771 return -EINVAL;
772 }
773
774 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
775 {
776 void __iomem *port_mmio = ahci_port_base(ap);
777 int offset = ahci_scr_offset(ap, sc_reg);
778
779 if (offset) {
780 writel(val, port_mmio + offset);
781 return 0;
782 }
783 return -EINVAL;
784 }
785
786 static void ahci_start_engine(struct ata_port *ap)
787 {
788 void __iomem *port_mmio = ahci_port_base(ap);
789 u32 tmp;
790
791 /* start DMA */
792 tmp = readl(port_mmio + PORT_CMD);
793 tmp |= PORT_CMD_START;
794 writel(tmp, port_mmio + PORT_CMD);
795 readl(port_mmio + PORT_CMD); /* flush */
796 }
797
798 static int ahci_stop_engine(struct ata_port *ap)
799 {
800 void __iomem *port_mmio = ahci_port_base(ap);
801 u32 tmp;
802
803 tmp = readl(port_mmio + PORT_CMD);
804
805 /* check if the HBA is idle */
806 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
807 return 0;
808
809 /* setting HBA to idle */
810 tmp &= ~PORT_CMD_START;
811 writel(tmp, port_mmio + PORT_CMD);
812
813 /* wait for engine to stop. This could be as long as 500 msec */
814 tmp = ata_wait_register(port_mmio + PORT_CMD,
815 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
816 if (tmp & PORT_CMD_LIST_ON)
817 return -EIO;
818
819 return 0;
820 }
821
822 static void ahci_start_fis_rx(struct ata_port *ap)
823 {
824 void __iomem *port_mmio = ahci_port_base(ap);
825 struct ahci_host_priv *hpriv = ap->host->private_data;
826 struct ahci_port_priv *pp = ap->private_data;
827 u32 tmp;
828
829 /* set FIS registers */
830 if (hpriv->cap & HOST_CAP_64)
831 writel((pp->cmd_slot_dma >> 16) >> 16,
832 port_mmio + PORT_LST_ADDR_HI);
833 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
834
835 if (hpriv->cap & HOST_CAP_64)
836 writel((pp->rx_fis_dma >> 16) >> 16,
837 port_mmio + PORT_FIS_ADDR_HI);
838 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
839
840 /* enable FIS reception */
841 tmp = readl(port_mmio + PORT_CMD);
842 tmp |= PORT_CMD_FIS_RX;
843 writel(tmp, port_mmio + PORT_CMD);
844
845 /* flush */
846 readl(port_mmio + PORT_CMD);
847 }
848
849 static int ahci_stop_fis_rx(struct ata_port *ap)
850 {
851 void __iomem *port_mmio = ahci_port_base(ap);
852 u32 tmp;
853
854 /* disable FIS reception */
855 tmp = readl(port_mmio + PORT_CMD);
856 tmp &= ~PORT_CMD_FIS_RX;
857 writel(tmp, port_mmio + PORT_CMD);
858
859 /* wait for completion, spec says 500ms, give it 1000 */
860 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
861 PORT_CMD_FIS_ON, 10, 1000);
862 if (tmp & PORT_CMD_FIS_ON)
863 return -EBUSY;
864
865 return 0;
866 }
867
868 static void ahci_power_up(struct ata_port *ap)
869 {
870 struct ahci_host_priv *hpriv = ap->host->private_data;
871 void __iomem *port_mmio = ahci_port_base(ap);
872 u32 cmd;
873
874 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
875
876 /* spin up device */
877 if (hpriv->cap & HOST_CAP_SSS) {
878 cmd |= PORT_CMD_SPIN_UP;
879 writel(cmd, port_mmio + PORT_CMD);
880 }
881
882 /* wake up link */
883 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
884 }
885
886 static void ahci_disable_alpm(struct ata_port *ap)
887 {
888 struct ahci_host_priv *hpriv = ap->host->private_data;
889 void __iomem *port_mmio = ahci_port_base(ap);
890 u32 cmd;
891 struct ahci_port_priv *pp = ap->private_data;
892
893 /* IPM bits should be disabled by libata-core */
894 /* get the existing command bits */
895 cmd = readl(port_mmio + PORT_CMD);
896
897 /* disable ALPM and ASP */
898 cmd &= ~PORT_CMD_ASP;
899 cmd &= ~PORT_CMD_ALPE;
900
901 /* force the interface back to active */
902 cmd |= PORT_CMD_ICC_ACTIVE;
903
904 /* write out new cmd value */
905 writel(cmd, port_mmio + PORT_CMD);
906 cmd = readl(port_mmio + PORT_CMD);
907
908 /* wait 10ms to be sure we've come out of any low power state */
909 msleep(10);
910
911 /* clear out any PhyRdy stuff from interrupt status */
912 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
913
914 /* go ahead and clean out PhyRdy Change from Serror too */
915 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
916
917 /*
918 * Clear flag to indicate that we should ignore all PhyRdy
919 * state changes
920 */
921 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
922
923 /*
924 * Enable interrupts on Phy Ready.
925 */
926 pp->intr_mask |= PORT_IRQ_PHYRDY;
927 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
928
929 /*
930 * don't change the link pm policy - we can be called
931 * just to turn of link pm temporarily
932 */
933 }
934
935 static int ahci_enable_alpm(struct ata_port *ap,
936 enum link_pm policy)
937 {
938 struct ahci_host_priv *hpriv = ap->host->private_data;
939 void __iomem *port_mmio = ahci_port_base(ap);
940 u32 cmd;
941 struct ahci_port_priv *pp = ap->private_data;
942 u32 asp;
943
944 /* Make sure the host is capable of link power management */
945 if (!(hpriv->cap & HOST_CAP_ALPM))
946 return -EINVAL;
947
948 switch (policy) {
949 case MAX_PERFORMANCE:
950 case NOT_AVAILABLE:
951 /*
952 * if we came here with NOT_AVAILABLE,
953 * it just means this is the first time we
954 * have tried to enable - default to max performance,
955 * and let the user go to lower power modes on request.
956 */
957 ahci_disable_alpm(ap);
958 return 0;
959 case MIN_POWER:
960 /* configure HBA to enter SLUMBER */
961 asp = PORT_CMD_ASP;
962 break;
963 case MEDIUM_POWER:
964 /* configure HBA to enter PARTIAL */
965 asp = 0;
966 break;
967 default:
968 return -EINVAL;
969 }
970
971 /*
972 * Disable interrupts on Phy Ready. This keeps us from
973 * getting woken up due to spurious phy ready interrupts
974 * TBD - Hot plug should be done via polling now, is
975 * that even supported?
976 */
977 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
978 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
979
980 /*
981 * Set a flag to indicate that we should ignore all PhyRdy
982 * state changes since these can happen now whenever we
983 * change link state
984 */
985 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
986
987 /* get the existing command bits */
988 cmd = readl(port_mmio + PORT_CMD);
989
990 /*
991 * Set ASP based on Policy
992 */
993 cmd |= asp;
994
995 /*
996 * Setting this bit will instruct the HBA to aggressively
997 * enter a lower power link state when it's appropriate and
998 * based on the value set above for ASP
999 */
1000 cmd |= PORT_CMD_ALPE;
1001
1002 /* write out new cmd value */
1003 writel(cmd, port_mmio + PORT_CMD);
1004 cmd = readl(port_mmio + PORT_CMD);
1005
1006 /* IPM bits should be set by libata-core */
1007 return 0;
1008 }
1009
1010 #ifdef CONFIG_PM
1011 static void ahci_power_down(struct ata_port *ap)
1012 {
1013 struct ahci_host_priv *hpriv = ap->host->private_data;
1014 void __iomem *port_mmio = ahci_port_base(ap);
1015 u32 cmd, scontrol;
1016
1017 if (!(hpriv->cap & HOST_CAP_SSS))
1018 return;
1019
1020 /* put device into listen mode, first set PxSCTL.DET to 0 */
1021 scontrol = readl(port_mmio + PORT_SCR_CTL);
1022 scontrol &= ~0xf;
1023 writel(scontrol, port_mmio + PORT_SCR_CTL);
1024
1025 /* then set PxCMD.SUD to 0 */
1026 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1027 cmd &= ~PORT_CMD_SPIN_UP;
1028 writel(cmd, port_mmio + PORT_CMD);
1029 }
1030 #endif
1031
1032 static void ahci_start_port(struct ata_port *ap)
1033 {
1034 /* enable FIS reception */
1035 ahci_start_fis_rx(ap);
1036
1037 /* enable DMA */
1038 ahci_start_engine(ap);
1039 }
1040
1041 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
1042 {
1043 int rc;
1044
1045 /* disable DMA */
1046 rc = ahci_stop_engine(ap);
1047 if (rc) {
1048 *emsg = "failed to stop engine";
1049 return rc;
1050 }
1051
1052 /* disable FIS reception */
1053 rc = ahci_stop_fis_rx(ap);
1054 if (rc) {
1055 *emsg = "failed stop FIS RX";
1056 return rc;
1057 }
1058
1059 return 0;
1060 }
1061
1062 static int ahci_reset_controller(struct ata_host *host)
1063 {
1064 struct pci_dev *pdev = to_pci_dev(host->dev);
1065 struct ahci_host_priv *hpriv = host->private_data;
1066 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1067 u32 tmp;
1068
1069 /* we must be in AHCI mode, before using anything
1070 * AHCI-specific, such as HOST_RESET.
1071 */
1072 ahci_enable_ahci(mmio);
1073
1074 /* global controller reset */
1075 if (!ahci_skip_host_reset) {
1076 tmp = readl(mmio + HOST_CTL);
1077 if ((tmp & HOST_RESET) == 0) {
1078 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1079 readl(mmio + HOST_CTL); /* flush */
1080 }
1081
1082 /* reset must complete within 1 second, or
1083 * the hardware should be considered fried.
1084 */
1085 ssleep(1);
1086
1087 tmp = readl(mmio + HOST_CTL);
1088 if (tmp & HOST_RESET) {
1089 dev_printk(KERN_ERR, host->dev,
1090 "controller reset failed (0x%x)\n", tmp);
1091 return -EIO;
1092 }
1093
1094 /* turn on AHCI mode */
1095 ahci_enable_ahci(mmio);
1096
1097 /* Some registers might be cleared on reset. Restore
1098 * initial values.
1099 */
1100 ahci_restore_initial_config(host);
1101 } else
1102 dev_printk(KERN_INFO, host->dev,
1103 "skipping global host reset\n");
1104
1105 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1106 u16 tmp16;
1107
1108 /* configure PCS */
1109 pci_read_config_word(pdev, 0x92, &tmp16);
1110 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1111 tmp16 |= hpriv->port_map;
1112 pci_write_config_word(pdev, 0x92, tmp16);
1113 }
1114 }
1115
1116 return 0;
1117 }
1118
1119 static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1120 int port_no, void __iomem *mmio,
1121 void __iomem *port_mmio)
1122 {
1123 const char *emsg = NULL;
1124 int rc;
1125 u32 tmp;
1126
1127 /* make sure port is not active */
1128 rc = ahci_deinit_port(ap, &emsg);
1129 if (rc)
1130 dev_printk(KERN_WARNING, &pdev->dev,
1131 "%s (%d)\n", emsg, rc);
1132
1133 /* clear SError */
1134 tmp = readl(port_mmio + PORT_SCR_ERR);
1135 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1136 writel(tmp, port_mmio + PORT_SCR_ERR);
1137
1138 /* clear port IRQ */
1139 tmp = readl(port_mmio + PORT_IRQ_STAT);
1140 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1141 if (tmp)
1142 writel(tmp, port_mmio + PORT_IRQ_STAT);
1143
1144 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1145 }
1146
1147 static void ahci_init_controller(struct ata_host *host)
1148 {
1149 struct ahci_host_priv *hpriv = host->private_data;
1150 struct pci_dev *pdev = to_pci_dev(host->dev);
1151 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1152 int i;
1153 void __iomem *port_mmio;
1154 u32 tmp;
1155 int mv;
1156
1157 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
1158 if (pdev->device == 0x6121)
1159 mv = 2;
1160 else
1161 mv = 4;
1162 port_mmio = __ahci_port_base(host, mv);
1163
1164 writel(0, port_mmio + PORT_IRQ_MASK);
1165
1166 /* clear port IRQ */
1167 tmp = readl(port_mmio + PORT_IRQ_STAT);
1168 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1169 if (tmp)
1170 writel(tmp, port_mmio + PORT_IRQ_STAT);
1171 }
1172
1173 for (i = 0; i < host->n_ports; i++) {
1174 struct ata_port *ap = host->ports[i];
1175
1176 port_mmio = ahci_port_base(ap);
1177 if (ata_port_is_dummy(ap))
1178 continue;
1179
1180 ahci_port_init(pdev, ap, i, mmio, port_mmio);
1181 }
1182
1183 tmp = readl(mmio + HOST_CTL);
1184 VPRINTK("HOST_CTL 0x%x\n", tmp);
1185 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1186 tmp = readl(mmio + HOST_CTL);
1187 VPRINTK("HOST_CTL 0x%x\n", tmp);
1188 }
1189
1190 static void ahci_dev_config(struct ata_device *dev)
1191 {
1192 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1193
1194 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1195 dev->max_sectors = 255;
1196 ata_dev_printk(dev, KERN_INFO,
1197 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1198 }
1199 }
1200
1201 static unsigned int ahci_dev_classify(struct ata_port *ap)
1202 {
1203 void __iomem *port_mmio = ahci_port_base(ap);
1204 struct ata_taskfile tf;
1205 u32 tmp;
1206
1207 tmp = readl(port_mmio + PORT_SIG);
1208 tf.lbah = (tmp >> 24) & 0xff;
1209 tf.lbam = (tmp >> 16) & 0xff;
1210 tf.lbal = (tmp >> 8) & 0xff;
1211 tf.nsect = (tmp) & 0xff;
1212
1213 return ata_dev_classify(&tf);
1214 }
1215
1216 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1217 u32 opts)
1218 {
1219 dma_addr_t cmd_tbl_dma;
1220
1221 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1222
1223 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1224 pp->cmd_slot[tag].status = 0;
1225 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1226 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1227 }
1228
1229 static int ahci_kick_engine(struct ata_port *ap, int force_restart)
1230 {
1231 void __iomem *port_mmio = ahci_port_base(ap);
1232 struct ahci_host_priv *hpriv = ap->host->private_data;
1233 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1234 u32 tmp;
1235 int busy, rc;
1236
1237 /* do we need to kick the port? */
1238 busy = status & (ATA_BUSY | ATA_DRQ);
1239 if (!busy && !force_restart)
1240 return 0;
1241
1242 /* stop engine */
1243 rc = ahci_stop_engine(ap);
1244 if (rc)
1245 goto out_restart;
1246
1247 /* need to do CLO? */
1248 if (!busy) {
1249 rc = 0;
1250 goto out_restart;
1251 }
1252
1253 if (!(hpriv->cap & HOST_CAP_CLO)) {
1254 rc = -EOPNOTSUPP;
1255 goto out_restart;
1256 }
1257
1258 /* perform CLO */
1259 tmp = readl(port_mmio + PORT_CMD);
1260 tmp |= PORT_CMD_CLO;
1261 writel(tmp, port_mmio + PORT_CMD);
1262
1263 rc = 0;
1264 tmp = ata_wait_register(port_mmio + PORT_CMD,
1265 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1266 if (tmp & PORT_CMD_CLO)
1267 rc = -EIO;
1268
1269 /* restart engine */
1270 out_restart:
1271 ahci_start_engine(ap);
1272 return rc;
1273 }
1274
1275 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1276 struct ata_taskfile *tf, int is_cmd, u16 flags,
1277 unsigned long timeout_msec)
1278 {
1279 const u32 cmd_fis_len = 5; /* five dwords */
1280 struct ahci_port_priv *pp = ap->private_data;
1281 void __iomem *port_mmio = ahci_port_base(ap);
1282 u8 *fis = pp->cmd_tbl;
1283 u32 tmp;
1284
1285 /* prep the command */
1286 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1287 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1288
1289 /* issue & wait */
1290 writel(1, port_mmio + PORT_CMD_ISSUE);
1291
1292 if (timeout_msec) {
1293 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1294 1, timeout_msec);
1295 if (tmp & 0x1) {
1296 ahci_kick_engine(ap, 1);
1297 return -EBUSY;
1298 }
1299 } else
1300 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1301
1302 return 0;
1303 }
1304
1305 static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1306 int pmp, unsigned long deadline,
1307 int (*check_ready)(struct ata_link *link))
1308 {
1309 struct ata_port *ap = link->ap;
1310 const char *reason = NULL;
1311 unsigned long now, msecs;
1312 struct ata_taskfile tf;
1313 int rc;
1314
1315 DPRINTK("ENTER\n");
1316
1317 /* prepare for SRST (AHCI-1.1 10.4.1) */
1318 rc = ahci_kick_engine(ap, 1);
1319 if (rc && rc != -EOPNOTSUPP)
1320 ata_link_printk(link, KERN_WARNING,
1321 "failed to reset engine (errno=%d)\n", rc);
1322
1323 ata_tf_init(link->device, &tf);
1324
1325 /* issue the first D2H Register FIS */
1326 msecs = 0;
1327 now = jiffies;
1328 if (time_after(now, deadline))
1329 msecs = jiffies_to_msecs(deadline - now);
1330
1331 tf.ctl |= ATA_SRST;
1332 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1333 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1334 rc = -EIO;
1335 reason = "1st FIS failed";
1336 goto fail;
1337 }
1338
1339 /* spec says at least 5us, but be generous and sleep for 1ms */
1340 msleep(1);
1341
1342 /* issue the second D2H Register FIS */
1343 tf.ctl &= ~ATA_SRST;
1344 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1345
1346 /* wait for link to become ready */
1347 rc = ata_wait_after_reset(link, deadline, check_ready);
1348 /* link occupied, -ENODEV too is an error */
1349 if (rc) {
1350 reason = "device not ready";
1351 goto fail;
1352 }
1353 *class = ahci_dev_classify(ap);
1354
1355 DPRINTK("EXIT, class=%u\n", *class);
1356 return 0;
1357
1358 fail:
1359 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1360 return rc;
1361 }
1362
1363 static int ahci_check_ready(struct ata_link *link)
1364 {
1365 void __iomem *port_mmio = ahci_port_base(link->ap);
1366 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1367
1368 return ata_check_ready(status);
1369 }
1370
1371 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1372 unsigned long deadline)
1373 {
1374 int pmp = sata_srst_pmp(link);
1375
1376 DPRINTK("ENTER\n");
1377
1378 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1379 }
1380
1381 static int ahci_sb600_check_ready(struct ata_link *link)
1382 {
1383 void __iomem *port_mmio = ahci_port_base(link->ap);
1384 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1385 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1386
1387 /*
1388 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1389 * which can save timeout delay.
1390 */
1391 if (irq_status & PORT_IRQ_BAD_PMP)
1392 return -EIO;
1393
1394 return ata_check_ready(status);
1395 }
1396
1397 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
1398 unsigned long deadline)
1399 {
1400 struct ata_port *ap = link->ap;
1401 void __iomem *port_mmio = ahci_port_base(ap);
1402 int pmp = sata_srst_pmp(link);
1403 int rc;
1404 u32 irq_sts;
1405
1406 DPRINTK("ENTER\n");
1407
1408 rc = ahci_do_softreset(link, class, pmp, deadline,
1409 ahci_sb600_check_ready);
1410
1411 /*
1412 * Soft reset fails on some ATI chips with IPMS set when PMP
1413 * is enabled but SATA HDD/ODD is connected to SATA port,
1414 * do soft reset again to port 0.
1415 */
1416 if (rc == -EIO) {
1417 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1418 if (irq_sts & PORT_IRQ_BAD_PMP) {
1419 ata_link_printk(link, KERN_WARNING,
1420 "failed due to HW bug, retry pmp=0\n");
1421 rc = ahci_do_softreset(link, class, 0, deadline,
1422 ahci_check_ready);
1423 }
1424 }
1425
1426 return rc;
1427 }
1428
1429 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1430 unsigned long deadline)
1431 {
1432 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1433 struct ata_port *ap = link->ap;
1434 struct ahci_port_priv *pp = ap->private_data;
1435 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1436 struct ata_taskfile tf;
1437 bool online;
1438 int rc;
1439
1440 DPRINTK("ENTER\n");
1441
1442 ahci_stop_engine(ap);
1443
1444 /* clear D2H reception area to properly wait for D2H FIS */
1445 ata_tf_init(link->device, &tf);
1446 tf.command = 0x80;
1447 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1448
1449 rc = sata_link_hardreset(link, timing, deadline, &online,
1450 ahci_check_ready);
1451
1452 ahci_start_engine(ap);
1453
1454 if (online)
1455 *class = ahci_dev_classify(ap);
1456
1457 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1458 return rc;
1459 }
1460
1461 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
1462 unsigned long deadline)
1463 {
1464 struct ata_port *ap = link->ap;
1465 bool online;
1466 int rc;
1467
1468 DPRINTK("ENTER\n");
1469
1470 ahci_stop_engine(ap);
1471
1472 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1473 deadline, &online, NULL);
1474
1475 ahci_start_engine(ap);
1476
1477 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1478
1479 /* vt8251 doesn't clear BSY on signature FIS reception,
1480 * request follow-up softreset.
1481 */
1482 return online ? -EAGAIN : rc;
1483 }
1484
1485 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1486 unsigned long deadline)
1487 {
1488 struct ata_port *ap = link->ap;
1489 struct ahci_port_priv *pp = ap->private_data;
1490 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1491 struct ata_taskfile tf;
1492 bool online;
1493 int rc;
1494
1495 ahci_stop_engine(ap);
1496
1497 /* clear D2H reception area to properly wait for D2H FIS */
1498 ata_tf_init(link->device, &tf);
1499 tf.command = 0x80;
1500 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1501
1502 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1503 deadline, &online, NULL);
1504
1505 ahci_start_engine(ap);
1506
1507 /* The pseudo configuration device on SIMG4726 attached to
1508 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1509 * hardreset if no device is attached to the first downstream
1510 * port && the pseudo device locks up on SRST w/ PMP==0. To
1511 * work around this, wait for !BSY only briefly. If BSY isn't
1512 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1513 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1514 *
1515 * Wait for two seconds. Devices attached to downstream port
1516 * which can't process the following IDENTIFY after this will
1517 * have to be reset again. For most cases, this should
1518 * suffice while making probing snappish enough.
1519 */
1520 if (online) {
1521 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
1522 ahci_check_ready);
1523 if (rc)
1524 ahci_kick_engine(ap, 0);
1525 }
1526 return rc;
1527 }
1528
1529 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1530 {
1531 struct ata_port *ap = link->ap;
1532 void __iomem *port_mmio = ahci_port_base(ap);
1533 u32 new_tmp, tmp;
1534
1535 ata_std_postreset(link, class);
1536
1537 /* Make sure port's ATAPI bit is set appropriately */
1538 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1539 if (*class == ATA_DEV_ATAPI)
1540 new_tmp |= PORT_CMD_ATAPI;
1541 else
1542 new_tmp &= ~PORT_CMD_ATAPI;
1543 if (new_tmp != tmp) {
1544 writel(new_tmp, port_mmio + PORT_CMD);
1545 readl(port_mmio + PORT_CMD); /* flush */
1546 }
1547 }
1548
1549 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1550 {
1551 struct scatterlist *sg;
1552 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1553 unsigned int si;
1554
1555 VPRINTK("ENTER\n");
1556
1557 /*
1558 * Next, the S/G list.
1559 */
1560 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1561 dma_addr_t addr = sg_dma_address(sg);
1562 u32 sg_len = sg_dma_len(sg);
1563
1564 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1565 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1566 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1567 }
1568
1569 return si;
1570 }
1571
1572 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1573 {
1574 struct ata_port *ap = qc->ap;
1575 struct ahci_port_priv *pp = ap->private_data;
1576 int is_atapi = ata_is_atapi(qc->tf.protocol);
1577 void *cmd_tbl;
1578 u32 opts;
1579 const u32 cmd_fis_len = 5; /* five dwords */
1580 unsigned int n_elem;
1581
1582 /*
1583 * Fill in command table information. First, the header,
1584 * a SATA Register - Host to Device command FIS.
1585 */
1586 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1587
1588 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1589 if (is_atapi) {
1590 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1591 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1592 }
1593
1594 n_elem = 0;
1595 if (qc->flags & ATA_QCFLAG_DMAMAP)
1596 n_elem = ahci_fill_sg(qc, cmd_tbl);
1597
1598 /*
1599 * Fill in command slot information.
1600 */
1601 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1602 if (qc->tf.flags & ATA_TFLAG_WRITE)
1603 opts |= AHCI_CMD_WRITE;
1604 if (is_atapi)
1605 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1606
1607 ahci_fill_cmd_slot(pp, qc->tag, opts);
1608 }
1609
1610 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1611 {
1612 struct ahci_host_priv *hpriv = ap->host->private_data;
1613 struct ahci_port_priv *pp = ap->private_data;
1614 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1615 struct ata_link *link = NULL;
1616 struct ata_queued_cmd *active_qc;
1617 struct ata_eh_info *active_ehi;
1618 u32 serror;
1619
1620 /* determine active link */
1621 ata_port_for_each_link(link, ap)
1622 if (ata_link_active(link))
1623 break;
1624 if (!link)
1625 link = &ap->link;
1626
1627 active_qc = ata_qc_from_tag(ap, link->active_tag);
1628 active_ehi = &link->eh_info;
1629
1630 /* record irq stat */
1631 ata_ehi_clear_desc(host_ehi);
1632 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1633
1634 /* AHCI needs SError cleared; otherwise, it might lock up */
1635 ahci_scr_read(ap, SCR_ERROR, &serror);
1636 ahci_scr_write(ap, SCR_ERROR, serror);
1637 host_ehi->serror |= serror;
1638
1639 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1640 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1641 irq_stat &= ~PORT_IRQ_IF_ERR;
1642
1643 if (irq_stat & PORT_IRQ_TF_ERR) {
1644 /* If qc is active, charge it; otherwise, the active
1645 * link. There's no active qc on NCQ errors. It will
1646 * be determined by EH by reading log page 10h.
1647 */
1648 if (active_qc)
1649 active_qc->err_mask |= AC_ERR_DEV;
1650 else
1651 active_ehi->err_mask |= AC_ERR_DEV;
1652
1653 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1654 host_ehi->serror &= ~SERR_INTERNAL;
1655 }
1656
1657 if (irq_stat & PORT_IRQ_UNK_FIS) {
1658 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1659
1660 active_ehi->err_mask |= AC_ERR_HSM;
1661 active_ehi->action |= ATA_EH_RESET;
1662 ata_ehi_push_desc(active_ehi,
1663 "unknown FIS %08x %08x %08x %08x" ,
1664 unk[0], unk[1], unk[2], unk[3]);
1665 }
1666
1667 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1668 active_ehi->err_mask |= AC_ERR_HSM;
1669 active_ehi->action |= ATA_EH_RESET;
1670 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1671 }
1672
1673 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1674 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1675 host_ehi->action |= ATA_EH_RESET;
1676 ata_ehi_push_desc(host_ehi, "host bus error");
1677 }
1678
1679 if (irq_stat & PORT_IRQ_IF_ERR) {
1680 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1681 host_ehi->action |= ATA_EH_RESET;
1682 ata_ehi_push_desc(host_ehi, "interface fatal error");
1683 }
1684
1685 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1686 ata_ehi_hotplugged(host_ehi);
1687 ata_ehi_push_desc(host_ehi, "%s",
1688 irq_stat & PORT_IRQ_CONNECT ?
1689 "connection status changed" : "PHY RDY changed");
1690 }
1691
1692 /* okay, let's hand over to EH */
1693
1694 if (irq_stat & PORT_IRQ_FREEZE)
1695 ata_port_freeze(ap);
1696 else
1697 ata_port_abort(ap);
1698 }
1699
1700 static void ahci_port_intr(struct ata_port *ap)
1701 {
1702 void __iomem *port_mmio = ahci_port_base(ap);
1703 struct ata_eh_info *ehi = &ap->link.eh_info;
1704 struct ahci_port_priv *pp = ap->private_data;
1705 struct ahci_host_priv *hpriv = ap->host->private_data;
1706 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1707 u32 status, qc_active;
1708 int rc;
1709
1710 status = readl(port_mmio + PORT_IRQ_STAT);
1711 writel(status, port_mmio + PORT_IRQ_STAT);
1712
1713 /* ignore BAD_PMP while resetting */
1714 if (unlikely(resetting))
1715 status &= ~PORT_IRQ_BAD_PMP;
1716
1717 /* If we are getting PhyRdy, this is
1718 * just a power state change, we should
1719 * clear out this, plus the PhyRdy/Comm
1720 * Wake bits from Serror
1721 */
1722 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
1723 (status & PORT_IRQ_PHYRDY)) {
1724 status &= ~PORT_IRQ_PHYRDY;
1725 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
1726 }
1727
1728 if (unlikely(status & PORT_IRQ_ERROR)) {
1729 ahci_error_intr(ap, status);
1730 return;
1731 }
1732
1733 if (status & PORT_IRQ_SDB_FIS) {
1734 /* If SNotification is available, leave notification
1735 * handling to sata_async_notification(). If not,
1736 * emulate it by snooping SDB FIS RX area.
1737 *
1738 * Snooping FIS RX area is probably cheaper than
1739 * poking SNotification but some constrollers which
1740 * implement SNotification, ICH9 for example, don't
1741 * store AN SDB FIS into receive area.
1742 */
1743 if (hpriv->cap & HOST_CAP_SNTF)
1744 sata_async_notification(ap);
1745 else {
1746 /* If the 'N' bit in word 0 of the FIS is set,
1747 * we just received asynchronous notification.
1748 * Tell libata about it.
1749 */
1750 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1751 u32 f0 = le32_to_cpu(f[0]);
1752
1753 if (f0 & (1 << 15))
1754 sata_async_notification(ap);
1755 }
1756 }
1757
1758 /* pp->active_link is valid iff any command is in flight */
1759 if (ap->qc_active && pp->active_link->sactive)
1760 qc_active = readl(port_mmio + PORT_SCR_ACT);
1761 else
1762 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1763
1764 rc = ata_qc_complete_multiple(ap, qc_active);
1765
1766 /* while resetting, invalid completions are expected */
1767 if (unlikely(rc < 0 && !resetting)) {
1768 ehi->err_mask |= AC_ERR_HSM;
1769 ehi->action |= ATA_EH_RESET;
1770 ata_port_freeze(ap);
1771 }
1772 }
1773
1774 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1775 {
1776 struct ata_host *host = dev_instance;
1777 struct ahci_host_priv *hpriv;
1778 unsigned int i, handled = 0;
1779 void __iomem *mmio;
1780 u32 irq_stat, irq_ack = 0;
1781
1782 VPRINTK("ENTER\n");
1783
1784 hpriv = host->private_data;
1785 mmio = host->iomap[AHCI_PCI_BAR];
1786
1787 /* sigh. 0xffffffff is a valid return from h/w */
1788 irq_stat = readl(mmio + HOST_IRQ_STAT);
1789 irq_stat &= hpriv->port_map;
1790 if (!irq_stat)
1791 return IRQ_NONE;
1792
1793 spin_lock(&host->lock);
1794
1795 for (i = 0; i < host->n_ports; i++) {
1796 struct ata_port *ap;
1797
1798 if (!(irq_stat & (1 << i)))
1799 continue;
1800
1801 ap = host->ports[i];
1802 if (ap) {
1803 ahci_port_intr(ap);
1804 VPRINTK("port %u\n", i);
1805 } else {
1806 VPRINTK("port %u (no irq)\n", i);
1807 if (ata_ratelimit())
1808 dev_printk(KERN_WARNING, host->dev,
1809 "interrupt on disabled port %u\n", i);
1810 }
1811
1812 irq_ack |= (1 << i);
1813 }
1814
1815 if (irq_ack) {
1816 writel(irq_ack, mmio + HOST_IRQ_STAT);
1817 handled = 1;
1818 }
1819
1820 spin_unlock(&host->lock);
1821
1822 VPRINTK("EXIT\n");
1823
1824 return IRQ_RETVAL(handled);
1825 }
1826
1827 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1828 {
1829 struct ata_port *ap = qc->ap;
1830 void __iomem *port_mmio = ahci_port_base(ap);
1831 struct ahci_port_priv *pp = ap->private_data;
1832
1833 /* Keep track of the currently active link. It will be used
1834 * in completion path to determine whether NCQ phase is in
1835 * progress.
1836 */
1837 pp->active_link = qc->dev->link;
1838
1839 if (qc->tf.protocol == ATA_PROT_NCQ)
1840 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1841 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1842 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1843
1844 return 0;
1845 }
1846
1847 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
1848 {
1849 struct ahci_port_priv *pp = qc->ap->private_data;
1850 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1851
1852 ata_tf_from_fis(d2h_fis, &qc->result_tf);
1853 return true;
1854 }
1855
1856 static void ahci_freeze(struct ata_port *ap)
1857 {
1858 void __iomem *port_mmio = ahci_port_base(ap);
1859
1860 /* turn IRQ off */
1861 writel(0, port_mmio + PORT_IRQ_MASK);
1862 }
1863
1864 static void ahci_thaw(struct ata_port *ap)
1865 {
1866 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1867 void __iomem *port_mmio = ahci_port_base(ap);
1868 u32 tmp;
1869 struct ahci_port_priv *pp = ap->private_data;
1870
1871 /* clear IRQ */
1872 tmp = readl(port_mmio + PORT_IRQ_STAT);
1873 writel(tmp, port_mmio + PORT_IRQ_STAT);
1874 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1875
1876 /* turn IRQ back on */
1877 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1878 }
1879
1880 static void ahci_error_handler(struct ata_port *ap)
1881 {
1882 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1883 /* restart engine */
1884 ahci_stop_engine(ap);
1885 ahci_start_engine(ap);
1886 }
1887
1888 sata_pmp_error_handler(ap);
1889 }
1890
1891 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1892 {
1893 struct ata_port *ap = qc->ap;
1894
1895 /* make DMA engine forget about the failed command */
1896 if (qc->flags & ATA_QCFLAG_FAILED)
1897 ahci_kick_engine(ap, 1);
1898 }
1899
1900 static void ahci_pmp_attach(struct ata_port *ap)
1901 {
1902 void __iomem *port_mmio = ahci_port_base(ap);
1903 struct ahci_port_priv *pp = ap->private_data;
1904 u32 cmd;
1905
1906 cmd = readl(port_mmio + PORT_CMD);
1907 cmd |= PORT_CMD_PMP;
1908 writel(cmd, port_mmio + PORT_CMD);
1909
1910 pp->intr_mask |= PORT_IRQ_BAD_PMP;
1911 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1912 }
1913
1914 static void ahci_pmp_detach(struct ata_port *ap)
1915 {
1916 void __iomem *port_mmio = ahci_port_base(ap);
1917 struct ahci_port_priv *pp = ap->private_data;
1918 u32 cmd;
1919
1920 cmd = readl(port_mmio + PORT_CMD);
1921 cmd &= ~PORT_CMD_PMP;
1922 writel(cmd, port_mmio + PORT_CMD);
1923
1924 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
1925 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1926 }
1927
1928 static int ahci_port_resume(struct ata_port *ap)
1929 {
1930 ahci_power_up(ap);
1931 ahci_start_port(ap);
1932
1933 if (sata_pmp_attached(ap))
1934 ahci_pmp_attach(ap);
1935 else
1936 ahci_pmp_detach(ap);
1937
1938 return 0;
1939 }
1940
1941 #ifdef CONFIG_PM
1942 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1943 {
1944 const char *emsg = NULL;
1945 int rc;
1946
1947 rc = ahci_deinit_port(ap, &emsg);
1948 if (rc == 0)
1949 ahci_power_down(ap);
1950 else {
1951 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1952 ahci_start_port(ap);
1953 }
1954
1955 return rc;
1956 }
1957
1958 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1959 {
1960 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1961 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1962 u32 ctl;
1963
1964 if (mesg.event & PM_EVENT_SLEEP) {
1965 /* AHCI spec rev1.1 section 8.3.3:
1966 * Software must disable interrupts prior to requesting a
1967 * transition of the HBA to D3 state.
1968 */
1969 ctl = readl(mmio + HOST_CTL);
1970 ctl &= ~HOST_IRQ_EN;
1971 writel(ctl, mmio + HOST_CTL);
1972 readl(mmio + HOST_CTL); /* flush */
1973 }
1974
1975 return ata_pci_device_suspend(pdev, mesg);
1976 }
1977
1978 static int ahci_pci_device_resume(struct pci_dev *pdev)
1979 {
1980 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1981 int rc;
1982
1983 rc = ata_pci_device_do_resume(pdev);
1984 if (rc)
1985 return rc;
1986
1987 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1988 rc = ahci_reset_controller(host);
1989 if (rc)
1990 return rc;
1991
1992 ahci_init_controller(host);
1993 }
1994
1995 ata_host_resume(host);
1996
1997 return 0;
1998 }
1999 #endif
2000
2001 static int ahci_port_start(struct ata_port *ap)
2002 {
2003 struct device *dev = ap->host->dev;
2004 struct ahci_port_priv *pp;
2005 void *mem;
2006 dma_addr_t mem_dma;
2007
2008 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2009 if (!pp)
2010 return -ENOMEM;
2011
2012 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
2013 GFP_KERNEL);
2014 if (!mem)
2015 return -ENOMEM;
2016 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
2017
2018 /*
2019 * First item in chunk of DMA memory: 32-slot command table,
2020 * 32 bytes each in size
2021 */
2022 pp->cmd_slot = mem;
2023 pp->cmd_slot_dma = mem_dma;
2024
2025 mem += AHCI_CMD_SLOT_SZ;
2026 mem_dma += AHCI_CMD_SLOT_SZ;
2027
2028 /*
2029 * Second item: Received-FIS area
2030 */
2031 pp->rx_fis = mem;
2032 pp->rx_fis_dma = mem_dma;
2033
2034 mem += AHCI_RX_FIS_SZ;
2035 mem_dma += AHCI_RX_FIS_SZ;
2036
2037 /*
2038 * Third item: data area for storing a single command
2039 * and its scatter-gather table
2040 */
2041 pp->cmd_tbl = mem;
2042 pp->cmd_tbl_dma = mem_dma;
2043
2044 /*
2045 * Save off initial list of interrupts to be enabled.
2046 * This could be changed later
2047 */
2048 pp->intr_mask = DEF_PORT_IRQ;
2049
2050 ap->private_data = pp;
2051
2052 /* engage engines, captain */
2053 return ahci_port_resume(ap);
2054 }
2055
2056 static void ahci_port_stop(struct ata_port *ap)
2057 {
2058 const char *emsg = NULL;
2059 int rc;
2060
2061 /* de-initialize port */
2062 rc = ahci_deinit_port(ap, &emsg);
2063 if (rc)
2064 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
2065 }
2066
2067 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
2068 {
2069 int rc;
2070
2071 if (using_dac &&
2072 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
2073 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
2074 if (rc) {
2075 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2076 if (rc) {
2077 dev_printk(KERN_ERR, &pdev->dev,
2078 "64-bit DMA enable failed\n");
2079 return rc;
2080 }
2081 }
2082 } else {
2083 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2084 if (rc) {
2085 dev_printk(KERN_ERR, &pdev->dev,
2086 "32-bit DMA enable failed\n");
2087 return rc;
2088 }
2089 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2090 if (rc) {
2091 dev_printk(KERN_ERR, &pdev->dev,
2092 "32-bit consistent DMA enable failed\n");
2093 return rc;
2094 }
2095 }
2096 return 0;
2097 }
2098
2099 static void ahci_print_info(struct ata_host *host)
2100 {
2101 struct ahci_host_priv *hpriv = host->private_data;
2102 struct pci_dev *pdev = to_pci_dev(host->dev);
2103 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2104 u32 vers, cap, impl, speed;
2105 const char *speed_s;
2106 u16 cc;
2107 const char *scc_s;
2108
2109 vers = readl(mmio + HOST_VERSION);
2110 cap = hpriv->cap;
2111 impl = hpriv->port_map;
2112
2113 speed = (cap >> 20) & 0xf;
2114 if (speed == 1)
2115 speed_s = "1.5";
2116 else if (speed == 2)
2117 speed_s = "3";
2118 else
2119 speed_s = "?";
2120
2121 pci_read_config_word(pdev, 0x0a, &cc);
2122 if (cc == PCI_CLASS_STORAGE_IDE)
2123 scc_s = "IDE";
2124 else if (cc == PCI_CLASS_STORAGE_SATA)
2125 scc_s = "SATA";
2126 else if (cc == PCI_CLASS_STORAGE_RAID)
2127 scc_s = "RAID";
2128 else
2129 scc_s = "unknown";
2130
2131 dev_printk(KERN_INFO, &pdev->dev,
2132 "AHCI %02x%02x.%02x%02x "
2133 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2134 ,
2135
2136 (vers >> 24) & 0xff,
2137 (vers >> 16) & 0xff,
2138 (vers >> 8) & 0xff,
2139 vers & 0xff,
2140
2141 ((cap >> 8) & 0x1f) + 1,
2142 (cap & 0x1f) + 1,
2143 speed_s,
2144 impl,
2145 scc_s);
2146
2147 dev_printk(KERN_INFO, &pdev->dev,
2148 "flags: "
2149 "%s%s%s%s%s%s%s"
2150 "%s%s%s%s%s%s%s\n"
2151 ,
2152
2153 cap & (1 << 31) ? "64bit " : "",
2154 cap & (1 << 30) ? "ncq " : "",
2155 cap & (1 << 29) ? "sntf " : "",
2156 cap & (1 << 28) ? "ilck " : "",
2157 cap & (1 << 27) ? "stag " : "",
2158 cap & (1 << 26) ? "pm " : "",
2159 cap & (1 << 25) ? "led " : "",
2160
2161 cap & (1 << 24) ? "clo " : "",
2162 cap & (1 << 19) ? "nz " : "",
2163 cap & (1 << 18) ? "only " : "",
2164 cap & (1 << 17) ? "pmp " : "",
2165 cap & (1 << 15) ? "pio " : "",
2166 cap & (1 << 14) ? "slum " : "",
2167 cap & (1 << 13) ? "part " : ""
2168 );
2169 }
2170
2171 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2172 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2173 * support PMP and the 4726 either directly exports the device
2174 * attached to the first downstream port or acts as a hardware storage
2175 * controller and emulate a single ATA device (can be RAID 0/1 or some
2176 * other configuration).
2177 *
2178 * When there's no device attached to the first downstream port of the
2179 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2180 * configure the 4726. However, ATA emulation of the device is very
2181 * lame. It doesn't send signature D2H Reg FIS after the initial
2182 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2183 *
2184 * The following function works around the problem by always using
2185 * hardreset on the port and not depending on receiving signature FIS
2186 * afterward. If signature FIS isn't received soon, ATA class is
2187 * assumed without follow-up softreset.
2188 */
2189 static void ahci_p5wdh_workaround(struct ata_host *host)
2190 {
2191 static struct dmi_system_id sysids[] = {
2192 {
2193 .ident = "P5W DH Deluxe",
2194 .matches = {
2195 DMI_MATCH(DMI_SYS_VENDOR,
2196 "ASUSTEK COMPUTER INC"),
2197 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2198 },
2199 },
2200 { }
2201 };
2202 struct pci_dev *pdev = to_pci_dev(host->dev);
2203
2204 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2205 dmi_check_system(sysids)) {
2206 struct ata_port *ap = host->ports[1];
2207
2208 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2209 "Deluxe on-board SIMG4726 workaround\n");
2210
2211 ap->ops = &ahci_p5wdh_ops;
2212 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2213 }
2214 }
2215
2216 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2217 {
2218 static int printed_version;
2219 unsigned int board_id = ent->driver_data;
2220 struct ata_port_info pi = ahci_port_info[board_id];
2221 const struct ata_port_info *ppi[] = { &pi, NULL };
2222 struct device *dev = &pdev->dev;
2223 struct ahci_host_priv *hpriv;
2224 struct ata_host *host;
2225 int n_ports, i, rc;
2226
2227 VPRINTK("ENTER\n");
2228
2229 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2230
2231 if (!printed_version++)
2232 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
2233
2234 /* acquire resources */
2235 rc = pcim_enable_device(pdev);
2236 if (rc)
2237 return rc;
2238
2239 /* AHCI controllers often implement SFF compatible interface.
2240 * Grab all PCI BARs just in case.
2241 */
2242 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
2243 if (rc == -EBUSY)
2244 pcim_pin_device(pdev);
2245 if (rc)
2246 return rc;
2247
2248 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
2249 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
2250 u8 map;
2251
2252 /* ICH6s share the same PCI ID for both piix and ahci
2253 * modes. Enabling ahci mode while MAP indicates
2254 * combined mode is a bad idea. Yield to ata_piix.
2255 */
2256 pci_read_config_byte(pdev, ICH_MAP, &map);
2257 if (map & 0x3) {
2258 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
2259 "combined mode, can't enable AHCI mode\n");
2260 return -ENODEV;
2261 }
2262 }
2263
2264 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2265 if (!hpriv)
2266 return -ENOMEM;
2267 hpriv->flags |= (unsigned long)pi.private_data;
2268
2269 /* MCP65 revision A1 and A2 can't do MSI */
2270 if (board_id == board_ahci_mcp65 &&
2271 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
2272 hpriv->flags |= AHCI_HFLAG_NO_MSI;
2273
2274 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
2275 pci_intx(pdev, 1);
2276
2277 /* save initial config */
2278 ahci_save_initial_config(pdev, hpriv);
2279
2280 /* prepare host */
2281 if (hpriv->cap & HOST_CAP_NCQ)
2282 pi.flags |= ATA_FLAG_NCQ;
2283
2284 if (hpriv->cap & HOST_CAP_PMP)
2285 pi.flags |= ATA_FLAG_PMP;
2286
2287 /* CAP.NP sometimes indicate the index of the last enabled
2288 * port, at other times, that of the last possible port, so
2289 * determining the maximum port number requires looking at
2290 * both CAP.NP and port_map.
2291 */
2292 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
2293
2294 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
2295 if (!host)
2296 return -ENOMEM;
2297 host->iomap = pcim_iomap_table(pdev);
2298 host->private_data = hpriv;
2299
2300 for (i = 0; i < host->n_ports; i++) {
2301 struct ata_port *ap = host->ports[i];
2302
2303 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2304 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2305 0x100 + ap->port_no * 0x80, "port");
2306
2307 /* set initial link pm policy */
2308 ap->pm_policy = NOT_AVAILABLE;
2309
2310 /* disabled/not-implemented port */
2311 if (!(hpriv->port_map & (1 << i)))
2312 ap->ops = &ata_dummy_port_ops;
2313 }
2314
2315 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2316 ahci_p5wdh_workaround(host);
2317
2318 /* initialize adapter */
2319 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
2320 if (rc)
2321 return rc;
2322
2323 rc = ahci_reset_controller(host);
2324 if (rc)
2325 return rc;
2326
2327 ahci_init_controller(host);
2328 ahci_print_info(host);
2329
2330 pci_set_master(pdev);
2331 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2332 &ahci_sht);
2333 }
2334
2335 static int __init ahci_init(void)
2336 {
2337 return pci_register_driver(&ahci_pci_driver);
2338 }
2339
2340 static void __exit ahci_exit(void)
2341 {
2342 pci_unregister_driver(&ahci_pci_driver);
2343 }
2344
2345
2346 MODULE_AUTHOR("Jeff Garzik");
2347 MODULE_DESCRIPTION("AHCI SATA low-level driver");
2348 MODULE_LICENSE("GPL");
2349 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
2350 MODULE_VERSION(DRV_VERSION);
2351
2352 module_init(ahci_init);
2353 module_exit(ahci_exit);
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