2 * Copyright (C) STMicroelectronics 2009
3 * Copyright (C) ST-Ericsson SA 2010
5 * License Terms: GNU General Public License v2
6 * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
7 * Author: Sundar Iyer <sundar.iyer@stericsson.com>
8 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
10 * U8500 PRCM Unit interface driver
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/delay.h>
16 #include <linux/errno.h>
17 #include <linux/err.h>
18 #include <linux/spinlock.h>
20 #include <linux/slab.h>
21 #include <linux/mutex.h>
22 #include <linux/completion.h>
23 #include <linux/irq.h>
24 #include <linux/jiffies.h>
25 #include <linux/bitops.h>
27 #include <linux/platform_device.h>
28 #include <linux/uaccess.h>
29 #include <linux/mfd/core.h>
30 #include <linux/mfd/dbx500-prcmu.h>
31 #include <linux/mfd/abx500/ab8500.h>
32 #include <linux/regulator/db8500-prcmu.h>
33 #include <linux/regulator/machine.h>
34 #include <linux/cpufreq.h>
35 #include <linux/platform_data/ux500_wdt.h>
36 #include <asm/hardware/gic.h>
37 #include <mach/hardware.h>
38 #include <mach/irqs.h>
39 #include <mach/db8500-regs.h>
41 #include "dbx500-prcmu-regs.h"
43 /* Offset for the firmware version within the TCPM */
44 #define PRCMU_FW_VERSION_OFFSET 0xA4
46 /* Index of different voltages to be used when accessing AVSData */
47 #define PRCM_AVS_BASE 0x2FC
48 #define PRCM_AVS_VBB_RET (PRCM_AVS_BASE + 0x0)
49 #define PRCM_AVS_VBB_MAX_OPP (PRCM_AVS_BASE + 0x1)
50 #define PRCM_AVS_VBB_100_OPP (PRCM_AVS_BASE + 0x2)
51 #define PRCM_AVS_VBB_50_OPP (PRCM_AVS_BASE + 0x3)
52 #define PRCM_AVS_VARM_MAX_OPP (PRCM_AVS_BASE + 0x4)
53 #define PRCM_AVS_VARM_100_OPP (PRCM_AVS_BASE + 0x5)
54 #define PRCM_AVS_VARM_50_OPP (PRCM_AVS_BASE + 0x6)
55 #define PRCM_AVS_VARM_RET (PRCM_AVS_BASE + 0x7)
56 #define PRCM_AVS_VAPE_100_OPP (PRCM_AVS_BASE + 0x8)
57 #define PRCM_AVS_VAPE_50_OPP (PRCM_AVS_BASE + 0x9)
58 #define PRCM_AVS_VMOD_100_OPP (PRCM_AVS_BASE + 0xA)
59 #define PRCM_AVS_VMOD_50_OPP (PRCM_AVS_BASE + 0xB)
60 #define PRCM_AVS_VSAFE (PRCM_AVS_BASE + 0xC)
62 #define PRCM_AVS_VOLTAGE 0
63 #define PRCM_AVS_VOLTAGE_MASK 0x3f
64 #define PRCM_AVS_ISSLOWSTARTUP 6
65 #define PRCM_AVS_ISSLOWSTARTUP_MASK (1 << PRCM_AVS_ISSLOWSTARTUP)
66 #define PRCM_AVS_ISMODEENABLE 7
67 #define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE)
69 #define PRCM_BOOT_STATUS 0xFFF
70 #define PRCM_ROMCODE_A2P 0xFFE
71 #define PRCM_ROMCODE_P2A 0xFFD
72 #define PRCM_XP70_CUR_PWR_STATE 0xFFC /* 4 BYTES */
74 #define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */
76 #define _PRCM_MBOX_HEADER 0xFE8 /* 16 bytes */
77 #define PRCM_MBOX_HEADER_REQ_MB0 (_PRCM_MBOX_HEADER + 0x0)
78 #define PRCM_MBOX_HEADER_REQ_MB1 (_PRCM_MBOX_HEADER + 0x1)
79 #define PRCM_MBOX_HEADER_REQ_MB2 (_PRCM_MBOX_HEADER + 0x2)
80 #define PRCM_MBOX_HEADER_REQ_MB3 (_PRCM_MBOX_HEADER + 0x3)
81 #define PRCM_MBOX_HEADER_REQ_MB4 (_PRCM_MBOX_HEADER + 0x4)
82 #define PRCM_MBOX_HEADER_REQ_MB5 (_PRCM_MBOX_HEADER + 0x5)
83 #define PRCM_MBOX_HEADER_ACK_MB0 (_PRCM_MBOX_HEADER + 0x8)
86 #define PRCM_REQ_MB0 0xFDC /* 12 bytes */
87 #define PRCM_REQ_MB1 0xFD0 /* 12 bytes */
88 #define PRCM_REQ_MB2 0xFC0 /* 16 bytes */
89 #define PRCM_REQ_MB3 0xE4C /* 372 bytes */
90 #define PRCM_REQ_MB4 0xE48 /* 4 bytes */
91 #define PRCM_REQ_MB5 0xE44 /* 4 bytes */
94 #define PRCM_ACK_MB0 0xE08 /* 52 bytes */
95 #define PRCM_ACK_MB1 0xE04 /* 4 bytes */
96 #define PRCM_ACK_MB2 0xE00 /* 4 bytes */
97 #define PRCM_ACK_MB3 0xDFC /* 4 bytes */
98 #define PRCM_ACK_MB4 0xDF8 /* 4 bytes */
99 #define PRCM_ACK_MB5 0xDF4 /* 4 bytes */
101 /* Mailbox 0 headers */
102 #define MB0H_POWER_STATE_TRANS 0
103 #define MB0H_CONFIG_WAKEUPS_EXE 1
104 #define MB0H_READ_WAKEUP_ACK 3
105 #define MB0H_CONFIG_WAKEUPS_SLEEP 4
107 #define MB0H_WAKEUP_EXE 2
108 #define MB0H_WAKEUP_SLEEP 5
111 #define PRCM_REQ_MB0_AP_POWER_STATE (PRCM_REQ_MB0 + 0x0)
112 #define PRCM_REQ_MB0_AP_PLL_STATE (PRCM_REQ_MB0 + 0x1)
113 #define PRCM_REQ_MB0_ULP_CLOCK_STATE (PRCM_REQ_MB0 + 0x2)
114 #define PRCM_REQ_MB0_DO_NOT_WFI (PRCM_REQ_MB0 + 0x3)
115 #define PRCM_REQ_MB0_WAKEUP_8500 (PRCM_REQ_MB0 + 0x4)
116 #define PRCM_REQ_MB0_WAKEUP_4500 (PRCM_REQ_MB0 + 0x8)
119 #define PRCM_ACK_MB0_AP_PWRSTTR_STATUS (PRCM_ACK_MB0 + 0x0)
120 #define PRCM_ACK_MB0_READ_POINTER (PRCM_ACK_MB0 + 0x1)
121 #define PRCM_ACK_MB0_WAKEUP_0_8500 (PRCM_ACK_MB0 + 0x4)
122 #define PRCM_ACK_MB0_WAKEUP_0_4500 (PRCM_ACK_MB0 + 0x8)
123 #define PRCM_ACK_MB0_WAKEUP_1_8500 (PRCM_ACK_MB0 + 0x1C)
124 #define PRCM_ACK_MB0_WAKEUP_1_4500 (PRCM_ACK_MB0 + 0x20)
125 #define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20
127 /* Mailbox 1 headers */
128 #define MB1H_ARM_APE_OPP 0x0
129 #define MB1H_RESET_MODEM 0x2
130 #define MB1H_REQUEST_APE_OPP_100_VOLT 0x3
131 #define MB1H_RELEASE_APE_OPP_100_VOLT 0x4
132 #define MB1H_RELEASE_USB_WAKEUP 0x5
133 #define MB1H_PLL_ON_OFF 0x6
135 /* Mailbox 1 Requests */
136 #define PRCM_REQ_MB1_ARM_OPP (PRCM_REQ_MB1 + 0x0)
137 #define PRCM_REQ_MB1_APE_OPP (PRCM_REQ_MB1 + 0x1)
138 #define PRCM_REQ_MB1_PLL_ON_OFF (PRCM_REQ_MB1 + 0x4)
139 #define PLL_SOC0_OFF 0x1
140 #define PLL_SOC0_ON 0x2
141 #define PLL_SOC1_OFF 0x4
142 #define PLL_SOC1_ON 0x8
145 #define PRCM_ACK_MB1_CURRENT_ARM_OPP (PRCM_ACK_MB1 + 0x0)
146 #define PRCM_ACK_MB1_CURRENT_APE_OPP (PRCM_ACK_MB1 + 0x1)
147 #define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2)
148 #define PRCM_ACK_MB1_DVFS_STATUS (PRCM_ACK_MB1 + 0x3)
150 /* Mailbox 2 headers */
152 #define MB2H_AUTO_PWR 0x1
155 #define PRCM_REQ_MB2_SVA_MMDSP (PRCM_REQ_MB2 + 0x0)
156 #define PRCM_REQ_MB2_SVA_PIPE (PRCM_REQ_MB2 + 0x1)
157 #define PRCM_REQ_MB2_SIA_MMDSP (PRCM_REQ_MB2 + 0x2)
158 #define PRCM_REQ_MB2_SIA_PIPE (PRCM_REQ_MB2 + 0x3)
159 #define PRCM_REQ_MB2_SGA (PRCM_REQ_MB2 + 0x4)
160 #define PRCM_REQ_MB2_B2R2_MCDE (PRCM_REQ_MB2 + 0x5)
161 #define PRCM_REQ_MB2_ESRAM12 (PRCM_REQ_MB2 + 0x6)
162 #define PRCM_REQ_MB2_ESRAM34 (PRCM_REQ_MB2 + 0x7)
163 #define PRCM_REQ_MB2_AUTO_PM_SLEEP (PRCM_REQ_MB2 + 0x8)
164 #define PRCM_REQ_MB2_AUTO_PM_IDLE (PRCM_REQ_MB2 + 0xC)
167 #define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0)
168 #define HWACC_PWR_ST_OK 0xFE
170 /* Mailbox 3 headers */
172 #define MB3H_SIDETONE 0x1
173 #define MB3H_SYSCLK 0xE
175 /* Mailbox 3 Requests */
176 #define PRCM_REQ_MB3_ANC_FIR_COEFF (PRCM_REQ_MB3 + 0x0)
177 #define PRCM_REQ_MB3_ANC_IIR_COEFF (PRCM_REQ_MB3 + 0x20)
178 #define PRCM_REQ_MB3_ANC_SHIFTER (PRCM_REQ_MB3 + 0x60)
179 #define PRCM_REQ_MB3_ANC_WARP (PRCM_REQ_MB3 + 0x64)
180 #define PRCM_REQ_MB3_SIDETONE_FIR_GAIN (PRCM_REQ_MB3 + 0x68)
181 #define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C)
182 #define PRCM_REQ_MB3_SYSCLK_MGT (PRCM_REQ_MB3 + 0x16C)
184 /* Mailbox 4 headers */
185 #define MB4H_DDR_INIT 0x0
186 #define MB4H_MEM_ST 0x1
187 #define MB4H_HOTDOG 0x12
188 #define MB4H_HOTMON 0x13
189 #define MB4H_HOT_PERIOD 0x14
190 #define MB4H_A9WDOG_CONF 0x16
191 #define MB4H_A9WDOG_EN 0x17
192 #define MB4H_A9WDOG_DIS 0x18
193 #define MB4H_A9WDOG_LOAD 0x19
194 #define MB4H_A9WDOG_KICK 0x20
196 /* Mailbox 4 Requests */
197 #define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE (PRCM_REQ_MB4 + 0x0)
198 #define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE (PRCM_REQ_MB4 + 0x1)
199 #define PRCM_REQ_MB4_ESRAM0_ST (PRCM_REQ_MB4 + 0x3)
200 #define PRCM_REQ_MB4_HOTDOG_THRESHOLD (PRCM_REQ_MB4 + 0x0)
201 #define PRCM_REQ_MB4_HOTMON_LOW (PRCM_REQ_MB4 + 0x0)
202 #define PRCM_REQ_MB4_HOTMON_HIGH (PRCM_REQ_MB4 + 0x1)
203 #define PRCM_REQ_MB4_HOTMON_CONFIG (PRCM_REQ_MB4 + 0x2)
204 #define PRCM_REQ_MB4_HOT_PERIOD (PRCM_REQ_MB4 + 0x0)
205 #define HOTMON_CONFIG_LOW BIT(0)
206 #define HOTMON_CONFIG_HIGH BIT(1)
207 #define PRCM_REQ_MB4_A9WDOG_0 (PRCM_REQ_MB4 + 0x0)
208 #define PRCM_REQ_MB4_A9WDOG_1 (PRCM_REQ_MB4 + 0x1)
209 #define PRCM_REQ_MB4_A9WDOG_2 (PRCM_REQ_MB4 + 0x2)
210 #define PRCM_REQ_MB4_A9WDOG_3 (PRCM_REQ_MB4 + 0x3)
211 #define A9WDOG_AUTO_OFF_EN BIT(7)
212 #define A9WDOG_AUTO_OFF_DIS 0
213 #define A9WDOG_ID_MASK 0xf
215 /* Mailbox 5 Requests */
216 #define PRCM_REQ_MB5_I2C_SLAVE_OP (PRCM_REQ_MB5 + 0x0)
217 #define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1)
218 #define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2)
219 #define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3)
220 #define PRCMU_I2C_WRITE(slave) \
221 (((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0))
222 #define PRCMU_I2C_READ(slave) \
223 (((slave) << 1) | BIT(0) | (cpu_is_u8500v2() ? BIT(6) : 0))
224 #define PRCMU_I2C_STOP_EN BIT(3)
227 #define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1)
228 #define PRCM_ACK_MB5_I2C_VAL (PRCM_ACK_MB5 + 0x3)
229 #define I2C_WR_OK 0x1
230 #define I2C_RD_OK 0x2
234 #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
240 #define WAKEUP_BIT_RTC BIT(0)
241 #define WAKEUP_BIT_RTT0 BIT(1)
242 #define WAKEUP_BIT_RTT1 BIT(2)
243 #define WAKEUP_BIT_HSI0 BIT(3)
244 #define WAKEUP_BIT_HSI1 BIT(4)
245 #define WAKEUP_BIT_CA_WAKE BIT(5)
246 #define WAKEUP_BIT_USB BIT(6)
247 #define WAKEUP_BIT_ABB BIT(7)
248 #define WAKEUP_BIT_ABB_FIFO BIT(8)
249 #define WAKEUP_BIT_SYSCLK_OK BIT(9)
250 #define WAKEUP_BIT_CA_SLEEP BIT(10)
251 #define WAKEUP_BIT_AC_WAKE_ACK BIT(11)
252 #define WAKEUP_BIT_SIDE_TONE_OK BIT(12)
253 #define WAKEUP_BIT_ANC_OK BIT(13)
254 #define WAKEUP_BIT_SW_ERROR BIT(14)
255 #define WAKEUP_BIT_AC_SLEEP_ACK BIT(15)
256 #define WAKEUP_BIT_ARM BIT(17)
257 #define WAKEUP_BIT_HOTMON_LOW BIT(18)
258 #define WAKEUP_BIT_HOTMON_HIGH BIT(19)
259 #define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20)
260 #define WAKEUP_BIT_GPIO0 BIT(23)
261 #define WAKEUP_BIT_GPIO1 BIT(24)
262 #define WAKEUP_BIT_GPIO2 BIT(25)
263 #define WAKEUP_BIT_GPIO3 BIT(26)
264 #define WAKEUP_BIT_GPIO4 BIT(27)
265 #define WAKEUP_BIT_GPIO5 BIT(28)
266 #define WAKEUP_BIT_GPIO6 BIT(29)
267 #define WAKEUP_BIT_GPIO7 BIT(30)
268 #define WAKEUP_BIT_GPIO8 BIT(31)
272 struct prcmu_fw_version version
;
275 static struct irq_domain
*db8500_irq_domain
;
278 * This vector maps irq numbers to the bits in the bit field used in
279 * communication with the PRCMU firmware.
281 * The reason for having this is to keep the irq numbers contiguous even though
282 * the bits in the bit field are not. (The bits also have a tendency to move
283 * around, to further complicate matters.)
285 #define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name) - IRQ_PRCMU_BASE)
286 #define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name)
287 static u32 prcmu_irq_bit
[NUM_PRCMU_WAKEUPS
] = {
299 IRQ_ENTRY(HOTMON_LOW
),
300 IRQ_ENTRY(HOTMON_HIGH
),
301 IRQ_ENTRY(MODEM_SW_RESET_REQ
),
313 #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1)
314 #define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name)
315 static u32 prcmu_wakeup_bit
[NUM_PRCMU_WAKEUP_INDICES
] = {
323 WAKEUP_ENTRY(ABB_FIFO
),
328 * mb0_transfer - state needed for mailbox 0 communication.
329 * @lock: The transaction lock.
330 * @dbb_events_lock: A lock used to handle concurrent access to (parts of)
332 * @mask_work: Work structure used for (un)masking wakeup interrupts.
333 * @req: Request data that need to persist between requests.
337 spinlock_t dbb_irqs_lock
;
338 struct work_struct mask_work
;
339 struct mutex ac_wake_lock
;
340 struct completion ac_wake_work
;
349 * mb1_transfer - state needed for mailbox 1 communication.
350 * @lock: The transaction lock.
351 * @work: The transaction completion structure.
352 * @ape_opp: The current APE OPP.
353 * @ack: Reply ("acknowledge") data.
357 struct completion work
;
363 u8 ape_voltage_status
;
368 * mb2_transfer - state needed for mailbox 2 communication.
369 * @lock: The transaction lock.
370 * @work: The transaction completion structure.
371 * @auto_pm_lock: The autonomous power management configuration lock.
372 * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled.
373 * @req: Request data that need to persist between requests.
374 * @ack: Reply ("acknowledge") data.
378 struct completion work
;
379 spinlock_t auto_pm_lock
;
380 bool auto_pm_enabled
;
387 * mb3_transfer - state needed for mailbox 3 communication.
388 * @lock: The request lock.
389 * @sysclk_lock: A lock used to handle concurrent sysclk requests.
390 * @sysclk_work: Work structure used for sysclk requests.
394 struct mutex sysclk_lock
;
395 struct completion sysclk_work
;
399 * mb4_transfer - state needed for mailbox 4 communication.
400 * @lock: The transaction lock.
401 * @work: The transaction completion structure.
405 struct completion work
;
409 * mb5_transfer - state needed for mailbox 5 communication.
410 * @lock: The transaction lock.
411 * @work: The transaction completion structure.
412 * @ack: Reply ("acknowledge") data.
416 struct completion work
;
423 static atomic_t ac_wake_req_state
= ATOMIC_INIT(0);
426 static DEFINE_SPINLOCK(prcmu_lock
);
427 static DEFINE_SPINLOCK(clkout_lock
);
429 /* Global var to runtime determine TCDM base for v2 or v1 */
430 static __iomem
void *tcdm_base
;
445 static DEFINE_SPINLOCK(clk_mgt_lock
);
447 #define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \
448 { (PRCM_##_name##_MGT), 0 , _branch, _clk38div}
449 struct clk_mgt clk_mgt
[PRCMU_NUM_REG_CLOCKS
] = {
450 CLK_MGT_ENTRY(SGACLK
, PLL_DIV
, false),
451 CLK_MGT_ENTRY(UARTCLK
, PLL_FIX
, true),
452 CLK_MGT_ENTRY(MSP02CLK
, PLL_FIX
, true),
453 CLK_MGT_ENTRY(MSP1CLK
, PLL_FIX
, true),
454 CLK_MGT_ENTRY(I2CCLK
, PLL_FIX
, true),
455 CLK_MGT_ENTRY(SDMMCCLK
, PLL_DIV
, true),
456 CLK_MGT_ENTRY(SLIMCLK
, PLL_FIX
, true),
457 CLK_MGT_ENTRY(PER1CLK
, PLL_DIV
, true),
458 CLK_MGT_ENTRY(PER2CLK
, PLL_DIV
, true),
459 CLK_MGT_ENTRY(PER3CLK
, PLL_DIV
, true),
460 CLK_MGT_ENTRY(PER5CLK
, PLL_DIV
, true),
461 CLK_MGT_ENTRY(PER6CLK
, PLL_DIV
, true),
462 CLK_MGT_ENTRY(PER7CLK
, PLL_DIV
, true),
463 CLK_MGT_ENTRY(LCDCLK
, PLL_FIX
, true),
464 CLK_MGT_ENTRY(BMLCLK
, PLL_DIV
, true),
465 CLK_MGT_ENTRY(HSITXCLK
, PLL_DIV
, true),
466 CLK_MGT_ENTRY(HSIRXCLK
, PLL_DIV
, true),
467 CLK_MGT_ENTRY(HDMICLK
, PLL_FIX
, false),
468 CLK_MGT_ENTRY(APEATCLK
, PLL_DIV
, true),
469 CLK_MGT_ENTRY(APETRACECLK
, PLL_DIV
, true),
470 CLK_MGT_ENTRY(MCDECLK
, PLL_DIV
, true),
471 CLK_MGT_ENTRY(IPI2CCLK
, PLL_FIX
, true),
472 CLK_MGT_ENTRY(DSIALTCLK
, PLL_FIX
, false),
473 CLK_MGT_ENTRY(DMACLK
, PLL_DIV
, true),
474 CLK_MGT_ENTRY(B2R2CLK
, PLL_DIV
, true),
475 CLK_MGT_ENTRY(TVCLK
, PLL_FIX
, true),
476 CLK_MGT_ENTRY(SSPCLK
, PLL_FIX
, true),
477 CLK_MGT_ENTRY(RNGCLK
, PLL_FIX
, true),
478 CLK_MGT_ENTRY(UICCCLK
, PLL_FIX
, false),
487 static struct dsiclk dsiclk
[2] = {
489 .divsel_mask
= PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK
,
490 .divsel_shift
= PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT
,
491 .divsel
= PRCM_DSI_PLLOUT_SEL_PHI
,
494 .divsel_mask
= PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK
,
495 .divsel_shift
= PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT
,
496 .divsel
= PRCM_DSI_PLLOUT_SEL_PHI
,
506 static struct dsiescclk dsiescclk
[3] = {
508 .en
= PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN
,
509 .div_mask
= PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK
,
510 .div_shift
= PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT
,
513 .en
= PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN
,
514 .div_mask
= PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK
,
515 .div_shift
= PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT
,
518 .en
= PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN
,
519 .div_mask
= PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK
,
520 .div_shift
= PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT
,
526 * Used by MCDE to setup all necessary PRCMU registers
528 #define PRCMU_RESET_DSIPLL 0x00004000
529 #define PRCMU_UNCLAMP_DSIPLL 0x00400800
531 #define PRCMU_CLK_PLL_DIV_SHIFT 0
532 #define PRCMU_CLK_PLL_SW_SHIFT 5
533 #define PRCMU_CLK_38 (1 << 9)
534 #define PRCMU_CLK_38_SRC (1 << 10)
535 #define PRCMU_CLK_38_DIV (1 << 11)
537 /* PLLDIV=12, PLLSW=4 (PLLDDR) */
538 #define PRCMU_DSI_CLOCK_SETTING 0x0000008C
540 /* DPI 50000000 Hz */
541 #define PRCMU_DPI_CLOCK_SETTING ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \
542 (16 << PRCMU_CLK_PLL_DIV_SHIFT))
543 #define PRCMU_DSI_LP_CLOCK_SETTING 0x00000E00
545 /* D=101, N=1, R=4, SELDIV2=0 */
546 #define PRCMU_PLLDSI_FREQ_SETTING 0x00040165
548 #define PRCMU_ENABLE_PLLDSI 0x00000001
549 #define PRCMU_DISABLE_PLLDSI 0x00000000
550 #define PRCMU_RELEASE_RESET_DSS 0x0000400C
551 #define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000202
552 /* ESC clk, div0=1, div1=1, div2=3 */
553 #define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x07030101
554 #define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00030101
555 #define PRCMU_DSI_RESET_SW 0x00000007
557 #define PRCMU_PLLDSI_LOCKP_LOCKED 0x3
559 int db8500_prcmu_enable_dsipll(void)
563 /* Clear DSIPLL_RESETN */
564 writel(PRCMU_RESET_DSIPLL
, PRCM_APE_RESETN_CLR
);
565 /* Unclamp DSIPLL in/out */
566 writel(PRCMU_UNCLAMP_DSIPLL
, PRCM_MMIP_LS_CLAMP_CLR
);
568 /* Set DSI PLL FREQ */
569 writel(PRCMU_PLLDSI_FREQ_SETTING
, PRCM_PLLDSI_FREQ
);
570 writel(PRCMU_DSI_PLLOUT_SEL_SETTING
, PRCM_DSI_PLLOUT_SEL
);
571 /* Enable Escape clocks */
572 writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV
, PRCM_DSITVCLK_DIV
);
575 writel(PRCMU_ENABLE_PLLDSI
, PRCM_PLLDSI_ENABLE
);
577 writel(PRCMU_DSI_RESET_SW
, PRCM_DSI_SW_RESET
);
578 for (i
= 0; i
< 10; i
++) {
579 if ((readl(PRCM_PLLDSI_LOCKP
) & PRCMU_PLLDSI_LOCKP_LOCKED
)
580 == PRCMU_PLLDSI_LOCKP_LOCKED
)
584 /* Set DSIPLL_RESETN */
585 writel(PRCMU_RESET_DSIPLL
, PRCM_APE_RESETN_SET
);
589 int db8500_prcmu_disable_dsipll(void)
591 /* Disable dsi pll */
592 writel(PRCMU_DISABLE_PLLDSI
, PRCM_PLLDSI_ENABLE
);
593 /* Disable escapeclock */
594 writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV
, PRCM_DSITVCLK_DIV
);
598 int db8500_prcmu_set_display_clocks(void)
602 spin_lock_irqsave(&clk_mgt_lock
, flags
);
604 /* Grab the HW semaphore. */
605 while ((readl(PRCM_SEM
) & PRCM_SEM_PRCM_SEM
) != 0)
608 writel(PRCMU_DSI_CLOCK_SETTING
, PRCM_HDMICLK_MGT
);
609 writel(PRCMU_DSI_LP_CLOCK_SETTING
, PRCM_TVCLK_MGT
);
610 writel(PRCMU_DPI_CLOCK_SETTING
, PRCM_LCDCLK_MGT
);
612 /* Release the HW semaphore. */
615 spin_unlock_irqrestore(&clk_mgt_lock
, flags
);
620 u32
db8500_prcmu_read(unsigned int reg
)
622 return readl(_PRCMU_BASE
+ reg
);
625 void db8500_prcmu_write(unsigned int reg
, u32 value
)
629 spin_lock_irqsave(&prcmu_lock
, flags
);
630 writel(value
, (_PRCMU_BASE
+ reg
));
631 spin_unlock_irqrestore(&prcmu_lock
, flags
);
634 void db8500_prcmu_write_masked(unsigned int reg
, u32 mask
, u32 value
)
639 spin_lock_irqsave(&prcmu_lock
, flags
);
640 val
= readl(_PRCMU_BASE
+ reg
);
641 val
= ((val
& ~mask
) | (value
& mask
));
642 writel(val
, (_PRCMU_BASE
+ reg
));
643 spin_unlock_irqrestore(&prcmu_lock
, flags
);
646 struct prcmu_fw_version
*prcmu_get_fw_version(void)
648 return fw_info
.valid
? &fw_info
.version
: NULL
;
651 bool prcmu_has_arm_maxopp(void)
653 return (readb(tcdm_base
+ PRCM_AVS_VARM_MAX_OPP
) &
654 PRCM_AVS_ISMODEENABLE_MASK
) == PRCM_AVS_ISMODEENABLE_MASK
;
658 * prcmu_get_boot_status - PRCMU boot status checking
659 * Returns: the current PRCMU boot status
661 int prcmu_get_boot_status(void)
663 return readb(tcdm_base
+ PRCM_BOOT_STATUS
);
667 * prcmu_set_rc_a2p - This function is used to run few power state sequences
668 * @val: Value to be set, i.e. transition requested
669 * Returns: 0 on success, -EINVAL on invalid argument
671 * This function is used to run the following power state sequences -
672 * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
674 int prcmu_set_rc_a2p(enum romcode_write val
)
676 if (val
< RDY_2_DS
|| val
> RDY_2_XP70_RST
)
678 writeb(val
, (tcdm_base
+ PRCM_ROMCODE_A2P
));
683 * prcmu_get_rc_p2a - This function is used to get power state sequences
684 * Returns: the power transition that has last happened
686 * This function can return the following transitions-
687 * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
689 enum romcode_read
prcmu_get_rc_p2a(void)
691 return readb(tcdm_base
+ PRCM_ROMCODE_P2A
);
695 * prcmu_get_current_mode - Return the current XP70 power mode
696 * Returns: Returns the current AP(ARM) power mode: init,
697 * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset
699 enum ap_pwrst
prcmu_get_xp70_current_state(void)
701 return readb(tcdm_base
+ PRCM_XP70_CUR_PWR_STATE
);
705 * prcmu_config_clkout - Configure one of the programmable clock outputs.
706 * @clkout: The CLKOUT number (0 or 1).
707 * @source: The clock to be used (one of the PRCMU_CLKSRC_*).
708 * @div: The divider to be applied.
710 * Configures one of the programmable clock outputs (CLKOUTs).
711 * @div should be in the range [1,63] to request a configuration, or 0 to
712 * inform that the configuration is no longer requested.
714 int prcmu_config_clkout(u8 clkout
, u8 source
, u8 div
)
716 static int requests
[2];
726 BUG_ON((clkout
== 0) && (source
> PRCMU_CLKSRC_CLK009
));
728 if (!div
&& !requests
[clkout
])
733 div_mask
= PRCM_CLKOCR_CLKODIV0_MASK
;
734 mask
= (PRCM_CLKOCR_CLKODIV0_MASK
| PRCM_CLKOCR_CLKOSEL0_MASK
);
735 bits
= ((source
<< PRCM_CLKOCR_CLKOSEL0_SHIFT
) |
736 (div
<< PRCM_CLKOCR_CLKODIV0_SHIFT
));
739 div_mask
= PRCM_CLKOCR_CLKODIV1_MASK
;
740 mask
= (PRCM_CLKOCR_CLKODIV1_MASK
| PRCM_CLKOCR_CLKOSEL1_MASK
|
741 PRCM_CLKOCR_CLK1TYPE
);
742 bits
= ((source
<< PRCM_CLKOCR_CLKOSEL1_SHIFT
) |
743 (div
<< PRCM_CLKOCR_CLKODIV1_SHIFT
));
748 spin_lock_irqsave(&clkout_lock
, flags
);
750 val
= readl(PRCM_CLKOCR
);
751 if (val
& div_mask
) {
753 if ((val
& mask
) != bits
) {
755 goto unlock_and_return
;
758 if ((val
& mask
& ~div_mask
) != bits
) {
760 goto unlock_and_return
;
764 writel((bits
| (val
& ~mask
)), PRCM_CLKOCR
);
765 requests
[clkout
] += (div
? 1 : -1);
768 spin_unlock_irqrestore(&clkout_lock
, flags
);
773 int db8500_prcmu_set_power_state(u8 state
, bool keep_ulp_clk
, bool keep_ap_pll
)
777 BUG_ON((state
< PRCMU_AP_SLEEP
) || (PRCMU_AP_DEEP_IDLE
< state
));
779 spin_lock_irqsave(&mb0_transfer
.lock
, flags
);
781 while (readl(PRCM_MBOX_CPU_VAL
) & MBOX_BIT(0))
784 writeb(MB0H_POWER_STATE_TRANS
, (tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB0
));
785 writeb(state
, (tcdm_base
+ PRCM_REQ_MB0_AP_POWER_STATE
));
786 writeb((keep_ap_pll
? 1 : 0), (tcdm_base
+ PRCM_REQ_MB0_AP_PLL_STATE
));
787 writeb((keep_ulp_clk
? 1 : 0),
788 (tcdm_base
+ PRCM_REQ_MB0_ULP_CLOCK_STATE
));
789 writeb(0, (tcdm_base
+ PRCM_REQ_MB0_DO_NOT_WFI
));
790 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET
);
792 spin_unlock_irqrestore(&mb0_transfer
.lock
, flags
);
797 u8
db8500_prcmu_get_power_state_result(void)
799 return readb(tcdm_base
+ PRCM_ACK_MB0_AP_PWRSTTR_STATUS
);
802 /* This function decouple the gic from the prcmu */
803 int db8500_prcmu_gic_decouple(void)
805 u32 val
= readl(PRCM_A9_MASK_REQ
);
807 /* Set bit 0 register value to 1 */
808 writel(val
| PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ
,
811 /* Make sure the register is updated */
812 readl(PRCM_A9_MASK_REQ
);
814 /* Wait a few cycles for the gic mask completion */
820 /* This function recouple the gic with the prcmu */
821 int db8500_prcmu_gic_recouple(void)
823 u32 val
= readl(PRCM_A9_MASK_REQ
);
825 /* Set bit 0 register value to 0 */
826 writel(val
& ~PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ
, PRCM_A9_MASK_REQ
);
831 #define PRCMU_GIC_NUMBER_REGS 5
834 * This function checks if there are pending irq on the gic. It only
835 * makes sense if the gic has been decoupled before with the
836 * db8500_prcmu_gic_decouple function. Disabling an interrupt only
837 * disables the forwarding of the interrupt to any CPU interface. It
838 * does not prevent the interrupt from changing state, for example
839 * becoming pending, or active and pending if it is already
840 * active. Hence, we have to check the interrupt is pending *and* is
843 bool db8500_prcmu_gic_pending_irq(void)
845 u32 pr
; /* Pending register */
846 u32 er
; /* Enable register */
847 void __iomem
*dist_base
= __io_address(U8500_GIC_DIST_BASE
);
850 /* 5 registers. STI & PPI not skipped */
851 for (i
= 0; i
< PRCMU_GIC_NUMBER_REGS
; i
++) {
853 pr
= readl_relaxed(dist_base
+ GIC_DIST_PENDING_SET
+ i
* 4);
854 er
= readl_relaxed(dist_base
+ GIC_DIST_ENABLE_SET
+ i
* 4);
857 return true; /* There is a pending interrupt */
864 * This function checks if there are pending interrupt on the
865 * prcmu which has been delegated to monitor the irqs with the
866 * db8500_prcmu_copy_gic_settings function.
868 bool db8500_prcmu_pending_irq(void)
873 for (i
= 0; i
< PRCMU_GIC_NUMBER_REGS
- 1; i
++) {
874 it
= readl(PRCM_ARMITVAL31TO0
+ i
* 4);
875 im
= readl(PRCM_ARMITMSK31TO0
+ i
* 4);
877 return true; /* There is a pending interrupt */
884 * This function checks if the specified cpu is in in WFI. It's usage
885 * makes sense only if the gic is decoupled with the db8500_prcmu_gic_decouple
886 * function. Of course passing smp_processor_id() to this function will
887 * always return false...
889 bool db8500_prcmu_is_cpu_in_wfi(int cpu
)
891 return readl(PRCM_ARM_WFI_STANDBY
) & cpu
? PRCM_ARM_WFI_STANDBY_WFI1
:
892 PRCM_ARM_WFI_STANDBY_WFI0
;
896 * This function copies the gic SPI settings to the prcmu in order to
897 * monitor them and abort/finish the retention/off sequence or state.
899 int db8500_prcmu_copy_gic_settings(void)
901 u32 er
; /* Enable register */
902 void __iomem
*dist_base
= __io_address(U8500_GIC_DIST_BASE
);
905 /* We skip the STI and PPI */
906 for (i
= 0; i
< PRCMU_GIC_NUMBER_REGS
- 1; i
++) {
907 er
= readl_relaxed(dist_base
+
908 GIC_DIST_ENABLE_SET
+ (i
+ 1) * 4);
909 writel(er
, PRCM_ARMITMSK31TO0
+ i
* 4);
915 /* This function should only be called while mb0_transfer.lock is held. */
916 static void config_wakeups(void)
918 const u8 header
[2] = {
919 MB0H_CONFIG_WAKEUPS_EXE
,
920 MB0H_CONFIG_WAKEUPS_SLEEP
922 static u32 last_dbb_events
;
923 static u32 last_abb_events
;
928 dbb_events
= mb0_transfer
.req
.dbb_irqs
| mb0_transfer
.req
.dbb_wakeups
;
929 dbb_events
|= (WAKEUP_BIT_AC_WAKE_ACK
| WAKEUP_BIT_AC_SLEEP_ACK
);
931 abb_events
= mb0_transfer
.req
.abb_events
;
933 if ((dbb_events
== last_dbb_events
) && (abb_events
== last_abb_events
))
936 for (i
= 0; i
< 2; i
++) {
937 while (readl(PRCM_MBOX_CPU_VAL
) & MBOX_BIT(0))
939 writel(dbb_events
, (tcdm_base
+ PRCM_REQ_MB0_WAKEUP_8500
));
940 writel(abb_events
, (tcdm_base
+ PRCM_REQ_MB0_WAKEUP_4500
));
941 writeb(header
[i
], (tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB0
));
942 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET
);
944 last_dbb_events
= dbb_events
;
945 last_abb_events
= abb_events
;
948 void db8500_prcmu_enable_wakeups(u32 wakeups
)
954 BUG_ON(wakeups
!= (wakeups
& VALID_WAKEUPS
));
956 for (i
= 0, bits
= 0; i
< NUM_PRCMU_WAKEUP_INDICES
; i
++) {
957 if (wakeups
& BIT(i
))
958 bits
|= prcmu_wakeup_bit
[i
];
961 spin_lock_irqsave(&mb0_transfer
.lock
, flags
);
963 mb0_transfer
.req
.dbb_wakeups
= bits
;
966 spin_unlock_irqrestore(&mb0_transfer
.lock
, flags
);
969 void db8500_prcmu_config_abb_event_readout(u32 abb_events
)
973 spin_lock_irqsave(&mb0_transfer
.lock
, flags
);
975 mb0_transfer
.req
.abb_events
= abb_events
;
978 spin_unlock_irqrestore(&mb0_transfer
.lock
, flags
);
981 void db8500_prcmu_get_abb_event_buffer(void __iomem
**buf
)
983 if (readb(tcdm_base
+ PRCM_ACK_MB0_READ_POINTER
) & 1)
984 *buf
= (tcdm_base
+ PRCM_ACK_MB0_WAKEUP_1_4500
);
986 *buf
= (tcdm_base
+ PRCM_ACK_MB0_WAKEUP_0_4500
);
990 * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP
991 * @opp: The new ARM operating point to which transition is to be made
992 * Returns: 0 on success, non-zero on failure
994 * This function sets the the operating point of the ARM.
996 int db8500_prcmu_set_arm_opp(u8 opp
)
1000 if (opp
< ARM_NO_CHANGE
|| opp
> ARM_EXTCLK
)
1005 mutex_lock(&mb1_transfer
.lock
);
1007 while (readl(PRCM_MBOX_CPU_VAL
) & MBOX_BIT(1))
1010 writeb(MB1H_ARM_APE_OPP
, (tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB1
));
1011 writeb(opp
, (tcdm_base
+ PRCM_REQ_MB1_ARM_OPP
));
1012 writeb(APE_NO_CHANGE
, (tcdm_base
+ PRCM_REQ_MB1_APE_OPP
));
1014 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET
);
1015 wait_for_completion(&mb1_transfer
.work
);
1017 if ((mb1_transfer
.ack
.header
!= MB1H_ARM_APE_OPP
) ||
1018 (mb1_transfer
.ack
.arm_opp
!= opp
))
1021 mutex_unlock(&mb1_transfer
.lock
);
1027 * db8500_prcmu_get_arm_opp - get the current ARM OPP
1029 * Returns: the current ARM OPP
1031 int db8500_prcmu_get_arm_opp(void)
1033 return readb(tcdm_base
+ PRCM_ACK_MB1_CURRENT_ARM_OPP
);
1037 * db8500_prcmu_get_ddr_opp - get the current DDR OPP
1039 * Returns: the current DDR OPP
1041 int db8500_prcmu_get_ddr_opp(void)
1043 return readb(PRCM_DDR_SUBSYS_APE_MINBW
);
1047 * db8500_set_ddr_opp - set the appropriate DDR OPP
1048 * @opp: The new DDR operating point to which transition is to be made
1049 * Returns: 0 on success, non-zero on failure
1051 * This function sets the operating point of the DDR.
1053 int db8500_prcmu_set_ddr_opp(u8 opp
)
1055 if (opp
< DDR_100_OPP
|| opp
> DDR_25_OPP
)
1057 /* Changing the DDR OPP can hang the hardware pre-v21 */
1058 if (cpu_is_u8500v20_or_later() && !cpu_is_u8500v20())
1059 writeb(opp
, PRCM_DDR_SUBSYS_APE_MINBW
);
1064 /* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */
1065 static void request_even_slower_clocks(bool enable
)
1067 void __iomem
*clock_reg
[] = {
1071 unsigned long flags
;
1074 spin_lock_irqsave(&clk_mgt_lock
, flags
);
1076 /* Grab the HW semaphore. */
1077 while ((readl(PRCM_SEM
) & PRCM_SEM_PRCM_SEM
) != 0)
1080 for (i
= 0; i
< ARRAY_SIZE(clock_reg
); i
++) {
1084 val
= readl(clock_reg
[i
]);
1085 div
= (val
& PRCM_CLK_MGT_CLKPLLDIV_MASK
);
1087 if ((div
<= 1) || (div
> 15)) {
1088 pr_err("prcmu: Bad clock divider %d in %s\n",
1090 goto unlock_and_return
;
1095 goto unlock_and_return
;
1098 val
= ((val
& ~PRCM_CLK_MGT_CLKPLLDIV_MASK
) |
1099 (div
& PRCM_CLK_MGT_CLKPLLDIV_MASK
));
1100 writel(val
, clock_reg
[i
]);
1104 /* Release the HW semaphore. */
1105 writel(0, PRCM_SEM
);
1107 spin_unlock_irqrestore(&clk_mgt_lock
, flags
);
1111 * db8500_set_ape_opp - set the appropriate APE OPP
1112 * @opp: The new APE operating point to which transition is to be made
1113 * Returns: 0 on success, non-zero on failure
1115 * This function sets the operating point of the APE.
1117 int db8500_prcmu_set_ape_opp(u8 opp
)
1121 if (opp
== mb1_transfer
.ape_opp
)
1124 mutex_lock(&mb1_transfer
.lock
);
1126 if (mb1_transfer
.ape_opp
== APE_50_PARTLY_25_OPP
)
1127 request_even_slower_clocks(false);
1129 if ((opp
!= APE_100_OPP
) && (mb1_transfer
.ape_opp
!= APE_100_OPP
))
1132 while (readl(PRCM_MBOX_CPU_VAL
) & MBOX_BIT(1))
1135 writeb(MB1H_ARM_APE_OPP
, (tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB1
));
1136 writeb(ARM_NO_CHANGE
, (tcdm_base
+ PRCM_REQ_MB1_ARM_OPP
));
1137 writeb(((opp
== APE_50_PARTLY_25_OPP
) ? APE_50_OPP
: opp
),
1138 (tcdm_base
+ PRCM_REQ_MB1_APE_OPP
));
1140 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET
);
1141 wait_for_completion(&mb1_transfer
.work
);
1143 if ((mb1_transfer
.ack
.header
!= MB1H_ARM_APE_OPP
) ||
1144 (mb1_transfer
.ack
.ape_opp
!= opp
))
1148 if ((!r
&& (opp
== APE_50_PARTLY_25_OPP
)) ||
1149 (r
&& (mb1_transfer
.ape_opp
== APE_50_PARTLY_25_OPP
)))
1150 request_even_slower_clocks(true);
1152 mb1_transfer
.ape_opp
= opp
;
1154 mutex_unlock(&mb1_transfer
.lock
);
1160 * db8500_prcmu_get_ape_opp - get the current APE OPP
1162 * Returns: the current APE OPP
1164 int db8500_prcmu_get_ape_opp(void)
1166 return readb(tcdm_base
+ PRCM_ACK_MB1_CURRENT_APE_OPP
);
1170 * db8500_prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage
1171 * @enable: true to request the higher voltage, false to drop a request.
1173 * Calls to this function to enable and disable requests must be balanced.
1175 int db8500_prcmu_request_ape_opp_100_voltage(bool enable
)
1179 static unsigned int requests
;
1181 mutex_lock(&mb1_transfer
.lock
);
1184 if (0 != requests
++)
1185 goto unlock_and_return
;
1186 header
= MB1H_REQUEST_APE_OPP_100_VOLT
;
1188 if (requests
== 0) {
1190 goto unlock_and_return
;
1191 } else if (1 != requests
--) {
1192 goto unlock_and_return
;
1194 header
= MB1H_RELEASE_APE_OPP_100_VOLT
;
1197 while (readl(PRCM_MBOX_CPU_VAL
) & MBOX_BIT(1))
1200 writeb(header
, (tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB1
));
1202 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET
);
1203 wait_for_completion(&mb1_transfer
.work
);
1205 if ((mb1_transfer
.ack
.header
!= header
) ||
1206 ((mb1_transfer
.ack
.ape_voltage_status
& BIT(0)) != 0))
1210 mutex_unlock(&mb1_transfer
.lock
);
1216 * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup
1218 * This function releases the power state requirements of a USB wakeup.
1220 int prcmu_release_usb_wakeup_state(void)
1224 mutex_lock(&mb1_transfer
.lock
);
1226 while (readl(PRCM_MBOX_CPU_VAL
) & MBOX_BIT(1))
1229 writeb(MB1H_RELEASE_USB_WAKEUP
,
1230 (tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB1
));
1232 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET
);
1233 wait_for_completion(&mb1_transfer
.work
);
1235 if ((mb1_transfer
.ack
.header
!= MB1H_RELEASE_USB_WAKEUP
) ||
1236 ((mb1_transfer
.ack
.ape_voltage_status
& BIT(0)) != 0))
1239 mutex_unlock(&mb1_transfer
.lock
);
1244 static int request_pll(u8 clock
, bool enable
)
1248 if (clock
== PRCMU_PLLSOC0
)
1249 clock
= (enable
? PLL_SOC0_ON
: PLL_SOC0_OFF
);
1250 else if (clock
== PRCMU_PLLSOC1
)
1251 clock
= (enable
? PLL_SOC1_ON
: PLL_SOC1_OFF
);
1255 mutex_lock(&mb1_transfer
.lock
);
1257 while (readl(PRCM_MBOX_CPU_VAL
) & MBOX_BIT(1))
1260 writeb(MB1H_PLL_ON_OFF
, (tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB1
));
1261 writeb(clock
, (tcdm_base
+ PRCM_REQ_MB1_PLL_ON_OFF
));
1263 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET
);
1264 wait_for_completion(&mb1_transfer
.work
);
1266 if (mb1_transfer
.ack
.header
!= MB1H_PLL_ON_OFF
)
1269 mutex_unlock(&mb1_transfer
.lock
);
1275 * db8500_prcmu_set_epod - set the state of a EPOD (power domain)
1276 * @epod_id: The EPOD to set
1277 * @epod_state: The new EPOD state
1279 * This function sets the state of a EPOD (power domain). It may not be called
1280 * from interrupt context.
1282 int db8500_prcmu_set_epod(u16 epod_id
, u8 epod_state
)
1285 bool ram_retention
= false;
1288 /* check argument */
1289 BUG_ON(epod_id
>= NUM_EPOD_ID
);
1291 /* set flag if retention is possible */
1293 case EPOD_ID_SVAMMDSP
:
1294 case EPOD_ID_SIAMMDSP
:
1295 case EPOD_ID_ESRAM12
:
1296 case EPOD_ID_ESRAM34
:
1297 ram_retention
= true;
1301 /* check argument */
1302 BUG_ON(epod_state
> EPOD_STATE_ON
);
1303 BUG_ON(epod_state
== EPOD_STATE_RAMRET
&& !ram_retention
);
1306 mutex_lock(&mb2_transfer
.lock
);
1308 /* wait for mailbox */
1309 while (readl(PRCM_MBOX_CPU_VAL
) & MBOX_BIT(2))
1312 /* fill in mailbox */
1313 for (i
= 0; i
< NUM_EPOD_ID
; i
++)
1314 writeb(EPOD_STATE_NO_CHANGE
, (tcdm_base
+ PRCM_REQ_MB2
+ i
));
1315 writeb(epod_state
, (tcdm_base
+ PRCM_REQ_MB2
+ epod_id
));
1317 writeb(MB2H_DPS
, (tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB2
));
1319 writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET
);
1322 * The current firmware version does not handle errors correctly,
1323 * and we cannot recover if there is an error.
1324 * This is expected to change when the firmware is updated.
1326 if (!wait_for_completion_timeout(&mb2_transfer
.work
,
1327 msecs_to_jiffies(20000))) {
1328 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1331 goto unlock_and_return
;
1334 if (mb2_transfer
.ack
.status
!= HWACC_PWR_ST_OK
)
1338 mutex_unlock(&mb2_transfer
.lock
);
1343 * prcmu_configure_auto_pm - Configure autonomous power management.
1344 * @sleep: Configuration for ApSleep.
1345 * @idle: Configuration for ApIdle.
1347 void prcmu_configure_auto_pm(struct prcmu_auto_pm_config
*sleep
,
1348 struct prcmu_auto_pm_config
*idle
)
1352 unsigned long flags
;
1354 BUG_ON((sleep
== NULL
) || (idle
== NULL
));
1356 sleep_cfg
= (sleep
->sva_auto_pm_enable
& 0xF);
1357 sleep_cfg
= ((sleep_cfg
<< 4) | (sleep
->sia_auto_pm_enable
& 0xF));
1358 sleep_cfg
= ((sleep_cfg
<< 8) | (sleep
->sva_power_on
& 0xFF));
1359 sleep_cfg
= ((sleep_cfg
<< 8) | (sleep
->sia_power_on
& 0xFF));
1360 sleep_cfg
= ((sleep_cfg
<< 4) | (sleep
->sva_policy
& 0xF));
1361 sleep_cfg
= ((sleep_cfg
<< 4) | (sleep
->sia_policy
& 0xF));
1363 idle_cfg
= (idle
->sva_auto_pm_enable
& 0xF);
1364 idle_cfg
= ((idle_cfg
<< 4) | (idle
->sia_auto_pm_enable
& 0xF));
1365 idle_cfg
= ((idle_cfg
<< 8) | (idle
->sva_power_on
& 0xFF));
1366 idle_cfg
= ((idle_cfg
<< 8) | (idle
->sia_power_on
& 0xFF));
1367 idle_cfg
= ((idle_cfg
<< 4) | (idle
->sva_policy
& 0xF));
1368 idle_cfg
= ((idle_cfg
<< 4) | (idle
->sia_policy
& 0xF));
1370 spin_lock_irqsave(&mb2_transfer
.auto_pm_lock
, flags
);
1373 * The autonomous power management configuration is done through
1374 * fields in mailbox 2, but these fields are only used as shared
1375 * variables - i.e. there is no need to send a message.
1377 writel(sleep_cfg
, (tcdm_base
+ PRCM_REQ_MB2_AUTO_PM_SLEEP
));
1378 writel(idle_cfg
, (tcdm_base
+ PRCM_REQ_MB2_AUTO_PM_IDLE
));
1380 mb2_transfer
.auto_pm_enabled
=
1381 ((sleep
->sva_auto_pm_enable
== PRCMU_AUTO_PM_ON
) ||
1382 (sleep
->sia_auto_pm_enable
== PRCMU_AUTO_PM_ON
) ||
1383 (idle
->sva_auto_pm_enable
== PRCMU_AUTO_PM_ON
) ||
1384 (idle
->sia_auto_pm_enable
== PRCMU_AUTO_PM_ON
));
1386 spin_unlock_irqrestore(&mb2_transfer
.auto_pm_lock
, flags
);
1388 EXPORT_SYMBOL(prcmu_configure_auto_pm
);
1390 bool prcmu_is_auto_pm_enabled(void)
1392 return mb2_transfer
.auto_pm_enabled
;
1395 static int request_sysclk(bool enable
)
1398 unsigned long flags
;
1402 mutex_lock(&mb3_transfer
.sysclk_lock
);
1404 spin_lock_irqsave(&mb3_transfer
.lock
, flags
);
1406 while (readl(PRCM_MBOX_CPU_VAL
) & MBOX_BIT(3))
1409 writeb((enable
? ON
: OFF
), (tcdm_base
+ PRCM_REQ_MB3_SYSCLK_MGT
));
1411 writeb(MB3H_SYSCLK
, (tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB3
));
1412 writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET
);
1414 spin_unlock_irqrestore(&mb3_transfer
.lock
, flags
);
1417 * The firmware only sends an ACK if we want to enable the
1418 * SysClk, and it succeeds.
1420 if (enable
&& !wait_for_completion_timeout(&mb3_transfer
.sysclk_work
,
1421 msecs_to_jiffies(20000))) {
1422 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1427 mutex_unlock(&mb3_transfer
.sysclk_lock
);
1432 static int request_timclk(bool enable
)
1434 u32 val
= (PRCM_TCR_DOZE_MODE
| PRCM_TCR_TENSEL_MASK
);
1437 val
|= PRCM_TCR_STOP_TIMERS
;
1438 writel(val
, PRCM_TCR
);
1443 static int request_clock(u8 clock
, bool enable
)
1446 unsigned long flags
;
1448 spin_lock_irqsave(&clk_mgt_lock
, flags
);
1450 /* Grab the HW semaphore. */
1451 while ((readl(PRCM_SEM
) & PRCM_SEM_PRCM_SEM
) != 0)
1454 val
= readl(clk_mgt
[clock
].reg
);
1456 val
|= (PRCM_CLK_MGT_CLKEN
| clk_mgt
[clock
].pllsw
);
1458 clk_mgt
[clock
].pllsw
= (val
& PRCM_CLK_MGT_CLKPLLSW_MASK
);
1459 val
&= ~(PRCM_CLK_MGT_CLKEN
| PRCM_CLK_MGT_CLKPLLSW_MASK
);
1461 writel(val
, clk_mgt
[clock
].reg
);
1463 /* Release the HW semaphore. */
1464 writel(0, PRCM_SEM
);
1466 spin_unlock_irqrestore(&clk_mgt_lock
, flags
);
1471 static int request_sga_clock(u8 clock
, bool enable
)
1477 val
= readl(PRCM_CGATING_BYPASS
);
1478 writel(val
| PRCM_CGATING_BYPASS_ICN2
, PRCM_CGATING_BYPASS
);
1481 ret
= request_clock(clock
, enable
);
1483 if (!ret
&& !enable
) {
1484 val
= readl(PRCM_CGATING_BYPASS
);
1485 writel(val
& ~PRCM_CGATING_BYPASS_ICN2
, PRCM_CGATING_BYPASS
);
1491 static inline bool plldsi_locked(void)
1493 return (readl(PRCM_PLLDSI_LOCKP
) &
1494 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10
|
1495 PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3
)) ==
1496 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10
|
1497 PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3
);
1500 static int request_plldsi(bool enable
)
1505 writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP
|
1506 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI
), (enable
?
1507 PRCM_MMIP_LS_CLAMP_CLR
: PRCM_MMIP_LS_CLAMP_SET
));
1509 val
= readl(PRCM_PLLDSI_ENABLE
);
1511 val
|= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE
;
1513 val
&= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE
;
1514 writel(val
, PRCM_PLLDSI_ENABLE
);
1518 bool locked
= plldsi_locked();
1520 for (i
= 10; !locked
&& (i
> 0); --i
) {
1522 locked
= plldsi_locked();
1525 writel(PRCM_APE_RESETN_DSIPLL_RESETN
,
1526 PRCM_APE_RESETN_SET
);
1528 writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP
|
1529 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI
),
1530 PRCM_MMIP_LS_CLAMP_SET
);
1531 val
&= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE
;
1532 writel(val
, PRCM_PLLDSI_ENABLE
);
1536 writel(PRCM_APE_RESETN_DSIPLL_RESETN
, PRCM_APE_RESETN_CLR
);
1541 static int request_dsiclk(u8 n
, bool enable
)
1545 val
= readl(PRCM_DSI_PLLOUT_SEL
);
1546 val
&= ~dsiclk
[n
].divsel_mask
;
1547 val
|= ((enable
? dsiclk
[n
].divsel
: PRCM_DSI_PLLOUT_SEL_OFF
) <<
1548 dsiclk
[n
].divsel_shift
);
1549 writel(val
, PRCM_DSI_PLLOUT_SEL
);
1553 static int request_dsiescclk(u8 n
, bool enable
)
1557 val
= readl(PRCM_DSITVCLK_DIV
);
1558 enable
? (val
|= dsiescclk
[n
].en
) : (val
&= ~dsiescclk
[n
].en
);
1559 writel(val
, PRCM_DSITVCLK_DIV
);
1564 * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled.
1565 * @clock: The clock for which the request is made.
1566 * @enable: Whether the clock should be enabled (true) or disabled (false).
1568 * This function should only be used by the clock implementation.
1569 * Do not use it from any other place!
1571 int db8500_prcmu_request_clock(u8 clock
, bool enable
)
1573 if (clock
== PRCMU_SGACLK
)
1574 return request_sga_clock(clock
, enable
);
1575 else if (clock
< PRCMU_NUM_REG_CLOCKS
)
1576 return request_clock(clock
, enable
);
1577 else if (clock
== PRCMU_TIMCLK
)
1578 return request_timclk(enable
);
1579 else if ((clock
== PRCMU_DSI0CLK
) || (clock
== PRCMU_DSI1CLK
))
1580 return request_dsiclk((clock
- PRCMU_DSI0CLK
), enable
);
1581 else if ((PRCMU_DSI0ESCCLK
<= clock
) && (clock
<= PRCMU_DSI2ESCCLK
))
1582 return request_dsiescclk((clock
- PRCMU_DSI0ESCCLK
), enable
);
1583 else if (clock
== PRCMU_PLLDSI
)
1584 return request_plldsi(enable
);
1585 else if (clock
== PRCMU_SYSCLK
)
1586 return request_sysclk(enable
);
1587 else if ((clock
== PRCMU_PLLSOC0
) || (clock
== PRCMU_PLLSOC1
))
1588 return request_pll(clock
, enable
);
1593 static unsigned long pll_rate(void __iomem
*reg
, unsigned long src_rate
,
1604 rate
*= ((val
& PRCM_PLL_FREQ_D_MASK
) >> PRCM_PLL_FREQ_D_SHIFT
);
1606 d
= ((val
& PRCM_PLL_FREQ_N_MASK
) >> PRCM_PLL_FREQ_N_SHIFT
);
1610 d
= ((val
& PRCM_PLL_FREQ_R_MASK
) >> PRCM_PLL_FREQ_R_SHIFT
);
1614 if (val
& PRCM_PLL_FREQ_SELDIV2
)
1617 if ((branch
== PLL_FIX
) || ((branch
== PLL_DIV
) &&
1618 (val
& PRCM_PLL_FREQ_DIV2EN
) &&
1619 ((reg
== PRCM_PLLSOC0_FREQ
) ||
1620 (reg
== PRCM_PLLARM_FREQ
) ||
1621 (reg
== PRCM_PLLDDR_FREQ
))))
1624 (void)do_div(rate
, div
);
1626 return (unsigned long)rate
;
1629 #define ROOT_CLOCK_RATE 38400000
1631 static unsigned long clock_rate(u8 clock
)
1635 unsigned long rate
= ROOT_CLOCK_RATE
;
1637 val
= readl(clk_mgt
[clock
].reg
);
1639 if (val
& PRCM_CLK_MGT_CLK38
) {
1640 if (clk_mgt
[clock
].clk38div
&& (val
& PRCM_CLK_MGT_CLK38DIV
))
1645 val
|= clk_mgt
[clock
].pllsw
;
1646 pllsw
= (val
& PRCM_CLK_MGT_CLKPLLSW_MASK
);
1648 if (pllsw
== PRCM_CLK_MGT_CLKPLLSW_SOC0
)
1649 rate
= pll_rate(PRCM_PLLSOC0_FREQ
, rate
, clk_mgt
[clock
].branch
);
1650 else if (pllsw
== PRCM_CLK_MGT_CLKPLLSW_SOC1
)
1651 rate
= pll_rate(PRCM_PLLSOC1_FREQ
, rate
, clk_mgt
[clock
].branch
);
1652 else if (pllsw
== PRCM_CLK_MGT_CLKPLLSW_DDR
)
1653 rate
= pll_rate(PRCM_PLLDDR_FREQ
, rate
, clk_mgt
[clock
].branch
);
1657 if ((clock
== PRCMU_SGACLK
) &&
1658 (val
& PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN
)) {
1659 u64 r
= (rate
* 10);
1661 (void)do_div(r
, 25);
1662 return (unsigned long)r
;
1664 val
&= PRCM_CLK_MGT_CLKPLLDIV_MASK
;
1671 static unsigned long armss_rate(void)
1676 r
= readl(PRCM_ARM_CHGCLKREQ
);
1678 if (r
& PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ
) {
1679 /* External ARMCLKFIX clock */
1681 rate
= pll_rate(PRCM_PLLDDR_FREQ
, ROOT_CLOCK_RATE
, PLL_FIX
);
1683 /* Check PRCM_ARM_CHGCLKREQ divider */
1684 if (!(r
& PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL
))
1687 /* Check PRCM_ARMCLKFIX_MGT divider */
1688 r
= readl(PRCM_ARMCLKFIX_MGT
);
1689 r
&= PRCM_CLK_MGT_CLKPLLDIV_MASK
;
1692 } else {/* ARM PLL */
1693 rate
= pll_rate(PRCM_PLLARM_FREQ
, ROOT_CLOCK_RATE
, PLL_DIV
);
1699 static unsigned long dsiclk_rate(u8 n
)
1704 divsel
= readl(PRCM_DSI_PLLOUT_SEL
);
1705 divsel
= ((divsel
& dsiclk
[n
].divsel_mask
) >> dsiclk
[n
].divsel_shift
);
1707 if (divsel
== PRCM_DSI_PLLOUT_SEL_OFF
)
1708 divsel
= dsiclk
[n
].divsel
;
1711 case PRCM_DSI_PLLOUT_SEL_PHI_4
:
1713 case PRCM_DSI_PLLOUT_SEL_PHI_2
:
1715 case PRCM_DSI_PLLOUT_SEL_PHI
:
1716 return pll_rate(PRCM_PLLDSI_FREQ
, clock_rate(PRCMU_HDMICLK
),
1723 static unsigned long dsiescclk_rate(u8 n
)
1727 div
= readl(PRCM_DSITVCLK_DIV
);
1728 div
= ((div
& dsiescclk
[n
].div_mask
) >> (dsiescclk
[n
].div_shift
));
1729 return clock_rate(PRCMU_TVCLK
) / max((u32
)1, div
);
1732 unsigned long prcmu_clock_rate(u8 clock
)
1734 if (clock
< PRCMU_NUM_REG_CLOCKS
)
1735 return clock_rate(clock
);
1736 else if (clock
== PRCMU_TIMCLK
)
1737 return ROOT_CLOCK_RATE
/ 16;
1738 else if (clock
== PRCMU_SYSCLK
)
1739 return ROOT_CLOCK_RATE
;
1740 else if (clock
== PRCMU_PLLSOC0
)
1741 return pll_rate(PRCM_PLLSOC0_FREQ
, ROOT_CLOCK_RATE
, PLL_RAW
);
1742 else if (clock
== PRCMU_PLLSOC1
)
1743 return pll_rate(PRCM_PLLSOC1_FREQ
, ROOT_CLOCK_RATE
, PLL_RAW
);
1744 else if (clock
== PRCMU_ARMSS
)
1745 return armss_rate();
1746 else if (clock
== PRCMU_PLLDDR
)
1747 return pll_rate(PRCM_PLLDDR_FREQ
, ROOT_CLOCK_RATE
, PLL_RAW
);
1748 else if (clock
== PRCMU_PLLDSI
)
1749 return pll_rate(PRCM_PLLDSI_FREQ
, clock_rate(PRCMU_HDMICLK
),
1751 else if ((clock
== PRCMU_DSI0CLK
) || (clock
== PRCMU_DSI1CLK
))
1752 return dsiclk_rate(clock
- PRCMU_DSI0CLK
);
1753 else if ((PRCMU_DSI0ESCCLK
<= clock
) && (clock
<= PRCMU_DSI2ESCCLK
))
1754 return dsiescclk_rate(clock
- PRCMU_DSI0ESCCLK
);
1759 static unsigned long clock_source_rate(u32 clk_mgt_val
, int branch
)
1761 if (clk_mgt_val
& PRCM_CLK_MGT_CLK38
)
1762 return ROOT_CLOCK_RATE
;
1763 clk_mgt_val
&= PRCM_CLK_MGT_CLKPLLSW_MASK
;
1764 if (clk_mgt_val
== PRCM_CLK_MGT_CLKPLLSW_SOC0
)
1765 return pll_rate(PRCM_PLLSOC0_FREQ
, ROOT_CLOCK_RATE
, branch
);
1766 else if (clk_mgt_val
== PRCM_CLK_MGT_CLKPLLSW_SOC1
)
1767 return pll_rate(PRCM_PLLSOC1_FREQ
, ROOT_CLOCK_RATE
, branch
);
1768 else if (clk_mgt_val
== PRCM_CLK_MGT_CLKPLLSW_DDR
)
1769 return pll_rate(PRCM_PLLDDR_FREQ
, ROOT_CLOCK_RATE
, branch
);
1774 static u32
clock_divider(unsigned long src_rate
, unsigned long rate
)
1778 div
= (src_rate
/ rate
);
1781 if (rate
< (src_rate
/ div
))
1786 static long round_clock_rate(u8 clock
, unsigned long rate
)
1790 unsigned long src_rate
;
1793 val
= readl(clk_mgt
[clock
].reg
);
1794 src_rate
= clock_source_rate((val
| clk_mgt
[clock
].pllsw
),
1795 clk_mgt
[clock
].branch
);
1796 div
= clock_divider(src_rate
, rate
);
1797 if (val
& PRCM_CLK_MGT_CLK38
) {
1798 if (clk_mgt
[clock
].clk38div
) {
1804 } else if ((clock
== PRCMU_SGACLK
) && (div
== 3)) {
1805 u64 r
= (src_rate
* 10);
1807 (void)do_div(r
, 25);
1809 return (unsigned long)r
;
1811 rounded_rate
= (src_rate
/ min(div
, (u32
)31));
1813 return rounded_rate
;
1816 /* CPU FREQ table, may be changed due to if MAX_OPP is supported. */
1817 static struct cpufreq_frequency_table db8500_cpufreq_table
[] = {
1818 { .frequency
= 200000, .index
= ARM_EXTCLK
,},
1819 { .frequency
= 400000, .index
= ARM_50_OPP
,},
1820 { .frequency
= 800000, .index
= ARM_100_OPP
,},
1821 { .frequency
= CPUFREQ_TABLE_END
,}, /* To be used for MAX_OPP. */
1822 { .frequency
= CPUFREQ_TABLE_END
,},
1825 static long round_armss_rate(unsigned long rate
)
1830 /* cpufreq table frequencies is in KHz. */
1833 /* Find the corresponding arm opp from the cpufreq table. */
1834 while (db8500_cpufreq_table
[i
].frequency
!= CPUFREQ_TABLE_END
) {
1835 freq
= db8500_cpufreq_table
[i
].frequency
;
1841 /* Return the last valid value, even if a match was not found. */
1845 #define MIN_PLL_VCO_RATE 600000000ULL
1846 #define MAX_PLL_VCO_RATE 1680640000ULL
1848 static long round_plldsi_rate(unsigned long rate
)
1850 long rounded_rate
= 0;
1851 unsigned long src_rate
;
1855 src_rate
= clock_rate(PRCMU_HDMICLK
);
1858 for (r
= 7; (rem
> 0) && (r
> 0); r
--) {
1862 (void)do_div(d
, src_rate
);
1868 if (((2 * d
) < (r
* MIN_PLL_VCO_RATE
)) ||
1869 ((r
* MAX_PLL_VCO_RATE
) < (2 * d
)))
1873 if (rounded_rate
== 0)
1874 rounded_rate
= (long)d
;
1877 if ((rate
- d
) < rem
) {
1879 rounded_rate
= (long)d
;
1882 return rounded_rate
;
1885 static long round_dsiclk_rate(unsigned long rate
)
1888 unsigned long src_rate
;
1891 src_rate
= pll_rate(PRCM_PLLDSI_FREQ
, clock_rate(PRCMU_HDMICLK
),
1893 div
= clock_divider(src_rate
, rate
);
1894 rounded_rate
= (src_rate
/ ((div
> 2) ? 4 : div
));
1896 return rounded_rate
;
1899 static long round_dsiescclk_rate(unsigned long rate
)
1902 unsigned long src_rate
;
1905 src_rate
= clock_rate(PRCMU_TVCLK
);
1906 div
= clock_divider(src_rate
, rate
);
1907 rounded_rate
= (src_rate
/ min(div
, (u32
)255));
1909 return rounded_rate
;
1912 long prcmu_round_clock_rate(u8 clock
, unsigned long rate
)
1914 if (clock
< PRCMU_NUM_REG_CLOCKS
)
1915 return round_clock_rate(clock
, rate
);
1916 else if (clock
== PRCMU_ARMSS
)
1917 return round_armss_rate(rate
);
1918 else if (clock
== PRCMU_PLLDSI
)
1919 return round_plldsi_rate(rate
);
1920 else if ((clock
== PRCMU_DSI0CLK
) || (clock
== PRCMU_DSI1CLK
))
1921 return round_dsiclk_rate(rate
);
1922 else if ((PRCMU_DSI0ESCCLK
<= clock
) && (clock
<= PRCMU_DSI2ESCCLK
))
1923 return round_dsiescclk_rate(rate
);
1925 return (long)prcmu_clock_rate(clock
);
1928 static void set_clock_rate(u8 clock
, unsigned long rate
)
1932 unsigned long src_rate
;
1933 unsigned long flags
;
1935 spin_lock_irqsave(&clk_mgt_lock
, flags
);
1937 /* Grab the HW semaphore. */
1938 while ((readl(PRCM_SEM
) & PRCM_SEM_PRCM_SEM
) != 0)
1941 val
= readl(clk_mgt
[clock
].reg
);
1942 src_rate
= clock_source_rate((val
| clk_mgt
[clock
].pllsw
),
1943 clk_mgt
[clock
].branch
);
1944 div
= clock_divider(src_rate
, rate
);
1945 if (val
& PRCM_CLK_MGT_CLK38
) {
1946 if (clk_mgt
[clock
].clk38div
) {
1948 val
|= PRCM_CLK_MGT_CLK38DIV
;
1950 val
&= ~PRCM_CLK_MGT_CLK38DIV
;
1952 } else if (clock
== PRCMU_SGACLK
) {
1953 val
&= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK
|
1954 PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN
);
1956 u64 r
= (src_rate
* 10);
1958 (void)do_div(r
, 25);
1960 val
|= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN
;
1964 val
|= min(div
, (u32
)31);
1966 val
&= ~PRCM_CLK_MGT_CLKPLLDIV_MASK
;
1967 val
|= min(div
, (u32
)31);
1969 writel(val
, clk_mgt
[clock
].reg
);
1971 /* Release the HW semaphore. */
1972 writel(0, PRCM_SEM
);
1974 spin_unlock_irqrestore(&clk_mgt_lock
, flags
);
1977 static int set_armss_rate(unsigned long rate
)
1981 /* cpufreq table frequencies is in KHz. */
1984 /* Find the corresponding arm opp from the cpufreq table. */
1985 while (db8500_cpufreq_table
[i
].frequency
!= CPUFREQ_TABLE_END
) {
1986 if (db8500_cpufreq_table
[i
].frequency
== rate
)
1991 if (db8500_cpufreq_table
[i
].frequency
!= rate
)
1994 /* Set the new arm opp. */
1995 return db8500_prcmu_set_arm_opp(db8500_cpufreq_table
[i
].index
);
1998 static int set_plldsi_rate(unsigned long rate
)
2000 unsigned long src_rate
;
2005 src_rate
= clock_rate(PRCMU_HDMICLK
);
2008 for (r
= 7; (rem
> 0) && (r
> 0); r
--) {
2013 (void)do_div(d
, src_rate
);
2018 hwrate
= (d
* src_rate
);
2019 if (((2 * hwrate
) < (r
* MIN_PLL_VCO_RATE
)) ||
2020 ((r
* MAX_PLL_VCO_RATE
) < (2 * hwrate
)))
2022 (void)do_div(hwrate
, r
);
2023 if (rate
< hwrate
) {
2025 pll_freq
= (((u32
)d
<< PRCM_PLL_FREQ_D_SHIFT
) |
2026 (r
<< PRCM_PLL_FREQ_R_SHIFT
));
2029 if ((rate
- hwrate
) < rem
) {
2030 rem
= (rate
- hwrate
);
2031 pll_freq
= (((u32
)d
<< PRCM_PLL_FREQ_D_SHIFT
) |
2032 (r
<< PRCM_PLL_FREQ_R_SHIFT
));
2038 pll_freq
|= (1 << PRCM_PLL_FREQ_N_SHIFT
);
2039 writel(pll_freq
, PRCM_PLLDSI_FREQ
);
2044 static void set_dsiclk_rate(u8 n
, unsigned long rate
)
2049 div
= clock_divider(pll_rate(PRCM_PLLDSI_FREQ
,
2050 clock_rate(PRCMU_HDMICLK
), PLL_RAW
), rate
);
2052 dsiclk
[n
].divsel
= (div
== 1) ? PRCM_DSI_PLLOUT_SEL_PHI
:
2053 (div
== 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2
:
2054 /* else */ PRCM_DSI_PLLOUT_SEL_PHI_4
;
2056 val
= readl(PRCM_DSI_PLLOUT_SEL
);
2057 val
&= ~dsiclk
[n
].divsel_mask
;
2058 val
|= (dsiclk
[n
].divsel
<< dsiclk
[n
].divsel_shift
);
2059 writel(val
, PRCM_DSI_PLLOUT_SEL
);
2062 static void set_dsiescclk_rate(u8 n
, unsigned long rate
)
2067 div
= clock_divider(clock_rate(PRCMU_TVCLK
), rate
);
2068 val
= readl(PRCM_DSITVCLK_DIV
);
2069 val
&= ~dsiescclk
[n
].div_mask
;
2070 val
|= (min(div
, (u32
)255) << dsiescclk
[n
].div_shift
);
2071 writel(val
, PRCM_DSITVCLK_DIV
);
2074 int prcmu_set_clock_rate(u8 clock
, unsigned long rate
)
2076 if (clock
< PRCMU_NUM_REG_CLOCKS
)
2077 set_clock_rate(clock
, rate
);
2078 else if (clock
== PRCMU_ARMSS
)
2079 return set_armss_rate(rate
);
2080 else if (clock
== PRCMU_PLLDSI
)
2081 return set_plldsi_rate(rate
);
2082 else if ((clock
== PRCMU_DSI0CLK
) || (clock
== PRCMU_DSI1CLK
))
2083 set_dsiclk_rate((clock
- PRCMU_DSI0CLK
), rate
);
2084 else if ((PRCMU_DSI0ESCCLK
<= clock
) && (clock
<= PRCMU_DSI2ESCCLK
))
2085 set_dsiescclk_rate((clock
- PRCMU_DSI0ESCCLK
), rate
);
2089 int db8500_prcmu_config_esram0_deep_sleep(u8 state
)
2091 if ((state
> ESRAM0_DEEP_SLEEP_STATE_RET
) ||
2092 (state
< ESRAM0_DEEP_SLEEP_STATE_OFF
))
2095 mutex_lock(&mb4_transfer
.lock
);
2097 while (readl(PRCM_MBOX_CPU_VAL
) & MBOX_BIT(4))
2100 writeb(MB4H_MEM_ST
, (tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB4
));
2101 writeb(((DDR_PWR_STATE_OFFHIGHLAT
<< 4) | DDR_PWR_STATE_ON
),
2102 (tcdm_base
+ PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE
));
2103 writeb(DDR_PWR_STATE_ON
,
2104 (tcdm_base
+ PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE
));
2105 writeb(state
, (tcdm_base
+ PRCM_REQ_MB4_ESRAM0_ST
));
2107 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET
);
2108 wait_for_completion(&mb4_transfer
.work
);
2110 mutex_unlock(&mb4_transfer
.lock
);
2115 int db8500_prcmu_config_hotdog(u8 threshold
)
2117 mutex_lock(&mb4_transfer
.lock
);
2119 while (readl(PRCM_MBOX_CPU_VAL
) & MBOX_BIT(4))
2122 writeb(threshold
, (tcdm_base
+ PRCM_REQ_MB4_HOTDOG_THRESHOLD
));
2123 writeb(MB4H_HOTDOG
, (tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB4
));
2125 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET
);
2126 wait_for_completion(&mb4_transfer
.work
);
2128 mutex_unlock(&mb4_transfer
.lock
);
2133 int db8500_prcmu_config_hotmon(u8 low
, u8 high
)
2135 mutex_lock(&mb4_transfer
.lock
);
2137 while (readl(PRCM_MBOX_CPU_VAL
) & MBOX_BIT(4))
2140 writeb(low
, (tcdm_base
+ PRCM_REQ_MB4_HOTMON_LOW
));
2141 writeb(high
, (tcdm_base
+ PRCM_REQ_MB4_HOTMON_HIGH
));
2142 writeb((HOTMON_CONFIG_LOW
| HOTMON_CONFIG_HIGH
),
2143 (tcdm_base
+ PRCM_REQ_MB4_HOTMON_CONFIG
));
2144 writeb(MB4H_HOTMON
, (tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB4
));
2146 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET
);
2147 wait_for_completion(&mb4_transfer
.work
);
2149 mutex_unlock(&mb4_transfer
.lock
);
2154 static int config_hot_period(u16 val
)
2156 mutex_lock(&mb4_transfer
.lock
);
2158 while (readl(PRCM_MBOX_CPU_VAL
) & MBOX_BIT(4))
2161 writew(val
, (tcdm_base
+ PRCM_REQ_MB4_HOT_PERIOD
));
2162 writeb(MB4H_HOT_PERIOD
, (tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB4
));
2164 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET
);
2165 wait_for_completion(&mb4_transfer
.work
);
2167 mutex_unlock(&mb4_transfer
.lock
);
2172 int db8500_prcmu_start_temp_sense(u16 cycles32k
)
2174 if (cycles32k
== 0xFFFF)
2177 return config_hot_period(cycles32k
);
2180 int db8500_prcmu_stop_temp_sense(void)
2182 return config_hot_period(0xFFFF);
2185 static int prcmu_a9wdog(u8 cmd
, u8 d0
, u8 d1
, u8 d2
, u8 d3
)
2188 mutex_lock(&mb4_transfer
.lock
);
2190 while (readl(PRCM_MBOX_CPU_VAL
) & MBOX_BIT(4))
2193 writeb(d0
, (tcdm_base
+ PRCM_REQ_MB4_A9WDOG_0
));
2194 writeb(d1
, (tcdm_base
+ PRCM_REQ_MB4_A9WDOG_1
));
2195 writeb(d2
, (tcdm_base
+ PRCM_REQ_MB4_A9WDOG_2
));
2196 writeb(d3
, (tcdm_base
+ PRCM_REQ_MB4_A9WDOG_3
));
2198 writeb(cmd
, (tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB4
));
2200 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET
);
2201 wait_for_completion(&mb4_transfer
.work
);
2203 mutex_unlock(&mb4_transfer
.lock
);
2209 int db8500_prcmu_config_a9wdog(u8 num
, bool sleep_auto_off
)
2211 BUG_ON(num
== 0 || num
> 0xf);
2212 return prcmu_a9wdog(MB4H_A9WDOG_CONF
, num
, 0, 0,
2213 sleep_auto_off
? A9WDOG_AUTO_OFF_EN
:
2214 A9WDOG_AUTO_OFF_DIS
);
2216 EXPORT_SYMBOL(db8500_prcmu_config_a9wdog
);
2218 int db8500_prcmu_enable_a9wdog(u8 id
)
2220 return prcmu_a9wdog(MB4H_A9WDOG_EN
, id
, 0, 0, 0);
2222 EXPORT_SYMBOL(db8500_prcmu_enable_a9wdog
);
2224 int db8500_prcmu_disable_a9wdog(u8 id
)
2226 return prcmu_a9wdog(MB4H_A9WDOG_DIS
, id
, 0, 0, 0);
2228 EXPORT_SYMBOL(db8500_prcmu_disable_a9wdog
);
2230 int db8500_prcmu_kick_a9wdog(u8 id
)
2232 return prcmu_a9wdog(MB4H_A9WDOG_KICK
, id
, 0, 0, 0);
2234 EXPORT_SYMBOL(db8500_prcmu_kick_a9wdog
);
2237 * timeout is 28 bit, in ms.
2239 int db8500_prcmu_load_a9wdog(u8 id
, u32 timeout
)
2241 return prcmu_a9wdog(MB4H_A9WDOG_LOAD
,
2242 (id
& A9WDOG_ID_MASK
) |
2244 * Put the lowest 28 bits of timeout at
2245 * offset 4. Four first bits are used for id.
2247 (u8
)((timeout
<< 4) & 0xf0),
2248 (u8
)((timeout
>> 4) & 0xff),
2249 (u8
)((timeout
>> 12) & 0xff),
2250 (u8
)((timeout
>> 20) & 0xff));
2252 EXPORT_SYMBOL(db8500_prcmu_load_a9wdog
);
2255 * prcmu_abb_read() - Read register value(s) from the ABB.
2256 * @slave: The I2C slave address.
2257 * @reg: The (start) register address.
2258 * @value: The read out value(s).
2259 * @size: The number of registers to read.
2261 * Reads register value(s) from the ABB.
2262 * @size has to be 1 for the current firmware version.
2264 int prcmu_abb_read(u8 slave
, u8 reg
, u8
*value
, u8 size
)
2271 mutex_lock(&mb5_transfer
.lock
);
2273 while (readl(PRCM_MBOX_CPU_VAL
) & MBOX_BIT(5))
2276 writeb(0, (tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB5
));
2277 writeb(PRCMU_I2C_READ(slave
), (tcdm_base
+ PRCM_REQ_MB5_I2C_SLAVE_OP
));
2278 writeb(PRCMU_I2C_STOP_EN
, (tcdm_base
+ PRCM_REQ_MB5_I2C_HW_BITS
));
2279 writeb(reg
, (tcdm_base
+ PRCM_REQ_MB5_I2C_REG
));
2280 writeb(0, (tcdm_base
+ PRCM_REQ_MB5_I2C_VAL
));
2282 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET
);
2284 if (!wait_for_completion_timeout(&mb5_transfer
.work
,
2285 msecs_to_jiffies(20000))) {
2286 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2290 r
= ((mb5_transfer
.ack
.status
== I2C_RD_OK
) ? 0 : -EIO
);
2294 *value
= mb5_transfer
.ack
.value
;
2296 mutex_unlock(&mb5_transfer
.lock
);
2302 * prcmu_abb_write_masked() - Write masked register value(s) to the ABB.
2303 * @slave: The I2C slave address.
2304 * @reg: The (start) register address.
2305 * @value: The value(s) to write.
2306 * @mask: The mask(s) to use.
2307 * @size: The number of registers to write.
2309 * Writes masked register value(s) to the ABB.
2310 * For each @value, only the bits set to 1 in the corresponding @mask
2311 * will be written. The other bits are not changed.
2312 * @size has to be 1 for the current firmware version.
2314 int prcmu_abb_write_masked(u8 slave
, u8 reg
, u8
*value
, u8
*mask
, u8 size
)
2321 mutex_lock(&mb5_transfer
.lock
);
2323 while (readl(PRCM_MBOX_CPU_VAL
) & MBOX_BIT(5))
2326 writeb(~*mask
, (tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB5
));
2327 writeb(PRCMU_I2C_WRITE(slave
), (tcdm_base
+ PRCM_REQ_MB5_I2C_SLAVE_OP
));
2328 writeb(PRCMU_I2C_STOP_EN
, (tcdm_base
+ PRCM_REQ_MB5_I2C_HW_BITS
));
2329 writeb(reg
, (tcdm_base
+ PRCM_REQ_MB5_I2C_REG
));
2330 writeb(*value
, (tcdm_base
+ PRCM_REQ_MB5_I2C_VAL
));
2332 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET
);
2334 if (!wait_for_completion_timeout(&mb5_transfer
.work
,
2335 msecs_to_jiffies(20000))) {
2336 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2340 r
= ((mb5_transfer
.ack
.status
== I2C_WR_OK
) ? 0 : -EIO
);
2343 mutex_unlock(&mb5_transfer
.lock
);
2349 * prcmu_abb_write() - Write register value(s) to the ABB.
2350 * @slave: The I2C slave address.
2351 * @reg: The (start) register address.
2352 * @value: The value(s) to write.
2353 * @size: The number of registers to write.
2355 * Writes register value(s) to the ABB.
2356 * @size has to be 1 for the current firmware version.
2358 int prcmu_abb_write(u8 slave
, u8 reg
, u8
*value
, u8 size
)
2362 return prcmu_abb_write_masked(slave
, reg
, value
, &mask
, size
);
2366 * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem
2368 int prcmu_ac_wake_req(void)
2373 mutex_lock(&mb0_transfer
.ac_wake_lock
);
2375 val
= readl(PRCM_HOSTACCESS_REQ
);
2376 if (val
& PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ
)
2377 goto unlock_and_return
;
2379 atomic_set(&ac_wake_req_state
, 1);
2382 * Force Modem Wake-up before hostaccess_req ping-pong.
2383 * It prevents Modem to enter in Sleep while acking the hostaccess
2384 * request. The 31us delay has been calculated by HWI.
2386 val
|= PRCM_HOSTACCESS_REQ_WAKE_REQ
;
2387 writel(val
, PRCM_HOSTACCESS_REQ
);
2391 val
|= PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ
;
2392 writel(val
, PRCM_HOSTACCESS_REQ
);
2394 if (!wait_for_completion_timeout(&mb0_transfer
.ac_wake_work
,
2395 msecs_to_jiffies(5000))) {
2396 #if defined(CONFIG_DBX500_PRCMU_DEBUG)
2397 db8500_prcmu_debug_dump(__func__
, true, true);
2399 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2405 mutex_unlock(&mb0_transfer
.ac_wake_lock
);
2410 * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem
2412 void prcmu_ac_sleep_req()
2416 mutex_lock(&mb0_transfer
.ac_wake_lock
);
2418 val
= readl(PRCM_HOSTACCESS_REQ
);
2419 if (!(val
& PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ
))
2420 goto unlock_and_return
;
2422 writel((val
& ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ
),
2423 PRCM_HOSTACCESS_REQ
);
2425 if (!wait_for_completion_timeout(&mb0_transfer
.ac_wake_work
,
2426 msecs_to_jiffies(5000))) {
2427 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2431 atomic_set(&ac_wake_req_state
, 0);
2434 mutex_unlock(&mb0_transfer
.ac_wake_lock
);
2437 bool db8500_prcmu_is_ac_wake_requested(void)
2439 return (atomic_read(&ac_wake_req_state
) != 0);
2443 * db8500_prcmu_system_reset - System reset
2445 * Saves the reset reason code and then sets the APE_SOFTRST register which
2446 * fires interrupt to fw
2448 void db8500_prcmu_system_reset(u16 reset_code
)
2450 writew(reset_code
, (tcdm_base
+ PRCM_SW_RST_REASON
));
2451 writel(1, PRCM_APE_SOFTRST
);
2455 * db8500_prcmu_get_reset_code - Retrieve SW reset reason code
2457 * Retrieves the reset reason code stored by prcmu_system_reset() before
2460 u16
db8500_prcmu_get_reset_code(void)
2462 return readw(tcdm_base
+ PRCM_SW_RST_REASON
);
2466 * db8500_prcmu_reset_modem - ask the PRCMU to reset modem
2468 void db8500_prcmu_modem_reset(void)
2470 mutex_lock(&mb1_transfer
.lock
);
2472 while (readl(PRCM_MBOX_CPU_VAL
) & MBOX_BIT(1))
2475 writeb(MB1H_RESET_MODEM
, (tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB1
));
2476 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET
);
2477 wait_for_completion(&mb1_transfer
.work
);
2480 * No need to check return from PRCMU as modem should go in reset state
2481 * This state is already managed by upper layer
2484 mutex_unlock(&mb1_transfer
.lock
);
2487 static void ack_dbb_wakeup(void)
2489 unsigned long flags
;
2491 spin_lock_irqsave(&mb0_transfer
.lock
, flags
);
2493 while (readl(PRCM_MBOX_CPU_VAL
) & MBOX_BIT(0))
2496 writeb(MB0H_READ_WAKEUP_ACK
, (tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB0
));
2497 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET
);
2499 spin_unlock_irqrestore(&mb0_transfer
.lock
, flags
);
2502 static inline void print_unknown_header_warning(u8 n
, u8 header
)
2504 pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n",
2508 static bool read_mailbox_0(void)
2515 header
= readb(tcdm_base
+ PRCM_MBOX_HEADER_ACK_MB0
);
2517 case MB0H_WAKEUP_EXE
:
2518 case MB0H_WAKEUP_SLEEP
:
2519 if (readb(tcdm_base
+ PRCM_ACK_MB0_READ_POINTER
) & 1)
2520 ev
= readl(tcdm_base
+ PRCM_ACK_MB0_WAKEUP_1_8500
);
2522 ev
= readl(tcdm_base
+ PRCM_ACK_MB0_WAKEUP_0_8500
);
2524 if (ev
& (WAKEUP_BIT_AC_WAKE_ACK
| WAKEUP_BIT_AC_SLEEP_ACK
))
2525 complete(&mb0_transfer
.ac_wake_work
);
2526 if (ev
& WAKEUP_BIT_SYSCLK_OK
)
2527 complete(&mb3_transfer
.sysclk_work
);
2529 ev
&= mb0_transfer
.req
.dbb_irqs
;
2531 for (n
= 0; n
< NUM_PRCMU_WAKEUPS
; n
++) {
2532 if (ev
& prcmu_irq_bit
[n
])
2533 generic_handle_irq(irq_find_mapping(db8500_irq_domain
, n
));
2538 print_unknown_header_warning(0, header
);
2542 writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR
);
2546 static bool read_mailbox_1(void)
2548 mb1_transfer
.ack
.header
= readb(tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB1
);
2549 mb1_transfer
.ack
.arm_opp
= readb(tcdm_base
+
2550 PRCM_ACK_MB1_CURRENT_ARM_OPP
);
2551 mb1_transfer
.ack
.ape_opp
= readb(tcdm_base
+
2552 PRCM_ACK_MB1_CURRENT_APE_OPP
);
2553 mb1_transfer
.ack
.ape_voltage_status
= readb(tcdm_base
+
2554 PRCM_ACK_MB1_APE_VOLTAGE_STATUS
);
2555 writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR
);
2556 complete(&mb1_transfer
.work
);
2560 static bool read_mailbox_2(void)
2562 mb2_transfer
.ack
.status
= readb(tcdm_base
+ PRCM_ACK_MB2_DPS_STATUS
);
2563 writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR
);
2564 complete(&mb2_transfer
.work
);
2568 static bool read_mailbox_3(void)
2570 writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR
);
2574 static bool read_mailbox_4(void)
2577 bool do_complete
= true;
2579 header
= readb(tcdm_base
+ PRCM_MBOX_HEADER_REQ_MB4
);
2584 case MB4H_HOT_PERIOD
:
2585 case MB4H_A9WDOG_CONF
:
2586 case MB4H_A9WDOG_EN
:
2587 case MB4H_A9WDOG_DIS
:
2588 case MB4H_A9WDOG_LOAD
:
2589 case MB4H_A9WDOG_KICK
:
2592 print_unknown_header_warning(4, header
);
2593 do_complete
= false;
2597 writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR
);
2600 complete(&mb4_transfer
.work
);
2605 static bool read_mailbox_5(void)
2607 mb5_transfer
.ack
.status
= readb(tcdm_base
+ PRCM_ACK_MB5_I2C_STATUS
);
2608 mb5_transfer
.ack
.value
= readb(tcdm_base
+ PRCM_ACK_MB5_I2C_VAL
);
2609 writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR
);
2610 complete(&mb5_transfer
.work
);
2614 static bool read_mailbox_6(void)
2616 writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR
);
2620 static bool read_mailbox_7(void)
2622 writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR
);
2626 static bool (* const read_mailbox
[NUM_MB
])(void) = {
2637 static irqreturn_t
prcmu_irq_handler(int irq
, void *data
)
2643 bits
= (readl(PRCM_ARM_IT1_VAL
) & ALL_MBOX_BITS
);
2644 if (unlikely(!bits
))
2648 for (n
= 0; bits
; n
++) {
2649 if (bits
& MBOX_BIT(n
)) {
2650 bits
-= MBOX_BIT(n
);
2651 if (read_mailbox
[n
]())
2652 r
= IRQ_WAKE_THREAD
;
2658 static irqreturn_t
prcmu_irq_thread_fn(int irq
, void *data
)
2664 static void prcmu_mask_work(struct work_struct
*work
)
2666 unsigned long flags
;
2668 spin_lock_irqsave(&mb0_transfer
.lock
, flags
);
2672 spin_unlock_irqrestore(&mb0_transfer
.lock
, flags
);
2675 static void prcmu_irq_mask(struct irq_data
*d
)
2677 unsigned long flags
;
2679 spin_lock_irqsave(&mb0_transfer
.dbb_irqs_lock
, flags
);
2681 mb0_transfer
.req
.dbb_irqs
&= ~prcmu_irq_bit
[d
->hwirq
];
2683 spin_unlock_irqrestore(&mb0_transfer
.dbb_irqs_lock
, flags
);
2685 if (d
->irq
!= IRQ_PRCMU_CA_SLEEP
)
2686 schedule_work(&mb0_transfer
.mask_work
);
2689 static void prcmu_irq_unmask(struct irq_data
*d
)
2691 unsigned long flags
;
2693 spin_lock_irqsave(&mb0_transfer
.dbb_irqs_lock
, flags
);
2695 mb0_transfer
.req
.dbb_irqs
|= prcmu_irq_bit
[d
->hwirq
];
2697 spin_unlock_irqrestore(&mb0_transfer
.dbb_irqs_lock
, flags
);
2699 if (d
->irq
!= IRQ_PRCMU_CA_SLEEP
)
2700 schedule_work(&mb0_transfer
.mask_work
);
2703 static void noop(struct irq_data
*d
)
2707 static struct irq_chip prcmu_irq_chip
= {
2709 .irq_disable
= prcmu_irq_mask
,
2711 .irq_mask
= prcmu_irq_mask
,
2712 .irq_unmask
= prcmu_irq_unmask
,
2715 static char *fw_project_name(u8 project
)
2718 case PRCMU_FW_PROJECT_U8500
:
2720 case PRCMU_FW_PROJECT_U8500_C2
:
2722 case PRCMU_FW_PROJECT_U9500
:
2724 case PRCMU_FW_PROJECT_U9500_C2
:
2726 case PRCMU_FW_PROJECT_U8520
:
2728 case PRCMU_FW_PROJECT_U8420
:
2735 static int db8500_irq_map(struct irq_domain
*d
, unsigned int virq
,
2736 irq_hw_number_t hwirq
)
2738 irq_set_chip_and_handler(virq
, &prcmu_irq_chip
,
2740 set_irq_flags(virq
, IRQF_VALID
);
2745 static struct irq_domain_ops db8500_irq_ops
= {
2746 .map
= db8500_irq_map
,
2747 .xlate
= irq_domain_xlate_twocell
,
2750 static int db8500_irq_init(struct device_node
*np
)
2755 /* In the device tree case, just take some IRQs */
2757 irq_base
= IRQ_PRCMU_BASE
;
2759 db8500_irq_domain
= irq_domain_add_simple(
2760 np
, NUM_PRCMU_WAKEUPS
, irq_base
,
2761 &db8500_irq_ops
, NULL
);
2763 if (!db8500_irq_domain
) {
2764 pr_err("Failed to create irqdomain\n");
2768 /* All wakeups will be used, so create mappings for all */
2769 for (i
= 0; i
< NUM_PRCMU_WAKEUPS
; i
++)
2770 irq_create_mapping(db8500_irq_domain
, i
);
2775 void __init
db8500_prcmu_early_init(void)
2777 if (cpu_is_u8500v2() || cpu_is_u9540()) {
2778 void *tcpm_base
= ioremap_nocache(U8500_PRCMU_TCPM_BASE
, SZ_4K
);
2780 if (tcpm_base
!= NULL
) {
2782 version
= readl(tcpm_base
+ PRCMU_FW_VERSION_OFFSET
);
2783 fw_info
.version
.project
= version
& 0xFF;
2784 fw_info
.version
.api_version
= (version
>> 8) & 0xFF;
2785 fw_info
.version
.func_version
= (version
>> 16) & 0xFF;
2786 fw_info
.version
.errata
= (version
>> 24) & 0xFF;
2787 fw_info
.valid
= true;
2788 pr_info("PRCMU firmware: %s, version %d.%d.%d\n",
2789 fw_project_name(fw_info
.version
.project
),
2790 (version
>> 8) & 0xFF, (version
>> 16) & 0xFF,
2791 (version
>> 24) & 0xFF);
2796 tcdm_base
= ioremap_nocache(U8500_PRCMU_TCDM_BASE
,
2797 SZ_4K
+ SZ_8K
) + SZ_8K
;
2799 tcdm_base
= __io_address(U8500_PRCMU_TCDM_BASE
);
2801 pr_err("prcmu: Unsupported chip version\n");
2805 spin_lock_init(&mb0_transfer
.lock
);
2806 spin_lock_init(&mb0_transfer
.dbb_irqs_lock
);
2807 mutex_init(&mb0_transfer
.ac_wake_lock
);
2808 init_completion(&mb0_transfer
.ac_wake_work
);
2809 mutex_init(&mb1_transfer
.lock
);
2810 init_completion(&mb1_transfer
.work
);
2811 mb1_transfer
.ape_opp
= APE_NO_CHANGE
;
2812 mutex_init(&mb2_transfer
.lock
);
2813 init_completion(&mb2_transfer
.work
);
2814 spin_lock_init(&mb2_transfer
.auto_pm_lock
);
2815 spin_lock_init(&mb3_transfer
.lock
);
2816 mutex_init(&mb3_transfer
.sysclk_lock
);
2817 init_completion(&mb3_transfer
.sysclk_work
);
2818 mutex_init(&mb4_transfer
.lock
);
2819 init_completion(&mb4_transfer
.work
);
2820 mutex_init(&mb5_transfer
.lock
);
2821 init_completion(&mb5_transfer
.work
);
2823 INIT_WORK(&mb0_transfer
.mask_work
, prcmu_mask_work
);
2826 static void __init
init_prcm_registers(void)
2830 val
= readl(PRCM_A9PL_FORCE_CLKEN
);
2831 val
&= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN
|
2832 PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN
);
2833 writel(val
, (PRCM_A9PL_FORCE_CLKEN
));
2837 * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC
2839 static struct regulator_consumer_supply db8500_vape_consumers
[] = {
2840 REGULATOR_SUPPLY("v-ape", NULL
),
2841 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"),
2842 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"),
2843 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"),
2844 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"),
2845 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.4"),
2846 /* "v-mmc" changed to "vcore" in the mainline kernel */
2847 REGULATOR_SUPPLY("vcore", "sdi0"),
2848 REGULATOR_SUPPLY("vcore", "sdi1"),
2849 REGULATOR_SUPPLY("vcore", "sdi2"),
2850 REGULATOR_SUPPLY("vcore", "sdi3"),
2851 REGULATOR_SUPPLY("vcore", "sdi4"),
2852 REGULATOR_SUPPLY("v-dma", "dma40.0"),
2853 REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"),
2854 /* "v-uart" changed to "vcore" in the mainline kernel */
2855 REGULATOR_SUPPLY("vcore", "uart0"),
2856 REGULATOR_SUPPLY("vcore", "uart1"),
2857 REGULATOR_SUPPLY("vcore", "uart2"),
2858 REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"),
2859 REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"),
2860 REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
2863 static struct regulator_consumer_supply db8500_vsmps2_consumers
[] = {
2864 REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"),
2865 /* AV8100 regulator */
2866 REGULATOR_SUPPLY("hdmi_1v8", "0-0070"),
2869 static struct regulator_consumer_supply db8500_b2r2_mcde_consumers
[] = {
2870 REGULATOR_SUPPLY("vsupply", "b2r2_bus"),
2871 REGULATOR_SUPPLY("vsupply", "mcde"),
2874 /* SVA MMDSP regulator switch */
2875 static struct regulator_consumer_supply db8500_svammdsp_consumers
[] = {
2876 REGULATOR_SUPPLY("sva-mmdsp", "cm_control"),
2879 /* SVA pipe regulator switch */
2880 static struct regulator_consumer_supply db8500_svapipe_consumers
[] = {
2881 REGULATOR_SUPPLY("sva-pipe", "cm_control"),
2884 /* SIA MMDSP regulator switch */
2885 static struct regulator_consumer_supply db8500_siammdsp_consumers
[] = {
2886 REGULATOR_SUPPLY("sia-mmdsp", "cm_control"),
2889 /* SIA pipe regulator switch */
2890 static struct regulator_consumer_supply db8500_siapipe_consumers
[] = {
2891 REGULATOR_SUPPLY("sia-pipe", "cm_control"),
2894 static struct regulator_consumer_supply db8500_sga_consumers
[] = {
2895 REGULATOR_SUPPLY("v-mali", NULL
),
2898 /* ESRAM1 and 2 regulator switch */
2899 static struct regulator_consumer_supply db8500_esram12_consumers
[] = {
2900 REGULATOR_SUPPLY("esram12", "cm_control"),
2903 /* ESRAM3 and 4 regulator switch */
2904 static struct regulator_consumer_supply db8500_esram34_consumers
[] = {
2905 REGULATOR_SUPPLY("v-esram34", "mcde"),
2906 REGULATOR_SUPPLY("esram34", "cm_control"),
2907 REGULATOR_SUPPLY("lcla_esram", "dma40.0"),
2910 static struct regulator_init_data db8500_regulators
[DB8500_NUM_REGULATORS
] = {
2911 [DB8500_REGULATOR_VAPE
] = {
2913 .name
= "db8500-vape",
2914 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
2917 .consumer_supplies
= db8500_vape_consumers
,
2918 .num_consumer_supplies
= ARRAY_SIZE(db8500_vape_consumers
),
2920 [DB8500_REGULATOR_VARM
] = {
2922 .name
= "db8500-varm",
2923 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
2926 [DB8500_REGULATOR_VMODEM
] = {
2928 .name
= "db8500-vmodem",
2929 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
2932 [DB8500_REGULATOR_VPLL
] = {
2934 .name
= "db8500-vpll",
2935 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
2938 [DB8500_REGULATOR_VSMPS1
] = {
2940 .name
= "db8500-vsmps1",
2941 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
2944 [DB8500_REGULATOR_VSMPS2
] = {
2946 .name
= "db8500-vsmps2",
2947 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
2949 .consumer_supplies
= db8500_vsmps2_consumers
,
2950 .num_consumer_supplies
= ARRAY_SIZE(db8500_vsmps2_consumers
),
2952 [DB8500_REGULATOR_VSMPS3
] = {
2954 .name
= "db8500-vsmps3",
2955 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
2958 [DB8500_REGULATOR_VRF1
] = {
2960 .name
= "db8500-vrf1",
2961 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
2964 [DB8500_REGULATOR_SWITCH_SVAMMDSP
] = {
2965 /* dependency to u8500-vape is handled outside regulator framework */
2967 .name
= "db8500-sva-mmdsp",
2968 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
2970 .consumer_supplies
= db8500_svammdsp_consumers
,
2971 .num_consumer_supplies
= ARRAY_SIZE(db8500_svammdsp_consumers
),
2973 [DB8500_REGULATOR_SWITCH_SVAMMDSPRET
] = {
2975 /* "ret" means "retention" */
2976 .name
= "db8500-sva-mmdsp-ret",
2977 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
2980 [DB8500_REGULATOR_SWITCH_SVAPIPE
] = {
2981 /* dependency to u8500-vape is handled outside regulator framework */
2983 .name
= "db8500-sva-pipe",
2984 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
2986 .consumer_supplies
= db8500_svapipe_consumers
,
2987 .num_consumer_supplies
= ARRAY_SIZE(db8500_svapipe_consumers
),
2989 [DB8500_REGULATOR_SWITCH_SIAMMDSP
] = {
2990 /* dependency to u8500-vape is handled outside regulator framework */
2992 .name
= "db8500-sia-mmdsp",
2993 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
2995 .consumer_supplies
= db8500_siammdsp_consumers
,
2996 .num_consumer_supplies
= ARRAY_SIZE(db8500_siammdsp_consumers
),
2998 [DB8500_REGULATOR_SWITCH_SIAMMDSPRET
] = {
3000 .name
= "db8500-sia-mmdsp-ret",
3001 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
3004 [DB8500_REGULATOR_SWITCH_SIAPIPE
] = {
3005 /* dependency to u8500-vape is handled outside regulator framework */
3007 .name
= "db8500-sia-pipe",
3008 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
3010 .consumer_supplies
= db8500_siapipe_consumers
,
3011 .num_consumer_supplies
= ARRAY_SIZE(db8500_siapipe_consumers
),
3013 [DB8500_REGULATOR_SWITCH_SGA
] = {
3014 .supply_regulator
= "db8500-vape",
3016 .name
= "db8500-sga",
3017 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
3019 .consumer_supplies
= db8500_sga_consumers
,
3020 .num_consumer_supplies
= ARRAY_SIZE(db8500_sga_consumers
),
3023 [DB8500_REGULATOR_SWITCH_B2R2_MCDE
] = {
3024 .supply_regulator
= "db8500-vape",
3026 .name
= "db8500-b2r2-mcde",
3027 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
3029 .consumer_supplies
= db8500_b2r2_mcde_consumers
,
3030 .num_consumer_supplies
= ARRAY_SIZE(db8500_b2r2_mcde_consumers
),
3032 [DB8500_REGULATOR_SWITCH_ESRAM12
] = {
3034 * esram12 is set in retention and supplied by Vsafe when Vape is off,
3035 * no need to hold Vape
3038 .name
= "db8500-esram12",
3039 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
3041 .consumer_supplies
= db8500_esram12_consumers
,
3042 .num_consumer_supplies
= ARRAY_SIZE(db8500_esram12_consumers
),
3044 [DB8500_REGULATOR_SWITCH_ESRAM12RET
] = {
3046 .name
= "db8500-esram12-ret",
3047 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
3050 [DB8500_REGULATOR_SWITCH_ESRAM34
] = {
3052 * esram34 is set in retention and supplied by Vsafe when Vape is off,
3053 * no need to hold Vape
3056 .name
= "db8500-esram34",
3057 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
3059 .consumer_supplies
= db8500_esram34_consumers
,
3060 .num_consumer_supplies
= ARRAY_SIZE(db8500_esram34_consumers
),
3062 [DB8500_REGULATOR_SWITCH_ESRAM34RET
] = {
3064 .name
= "db8500-esram34-ret",
3065 .valid_ops_mask
= REGULATOR_CHANGE_STATUS
,
3070 static struct resource ab8500_resources
[] = {
3072 .start
= IRQ_DB8500_AB8500
,
3073 .end
= IRQ_DB8500_AB8500
,
3074 .flags
= IORESOURCE_IRQ
3078 static struct ux500_wdt_data db8500_wdt_pdata
= {
3079 .timeout
= 600, /* 10 minutes */
3080 .has_28_bits_resolution
= true,
3083 static struct mfd_cell db8500_prcmu_devs
[] = {
3085 .name
= "db8500-prcmu-regulators",
3086 .of_compatible
= "stericsson,db8500-prcmu-regulator",
3087 .platform_data
= &db8500_regulators
,
3088 .pdata_size
= sizeof(db8500_regulators
),
3091 .name
= "cpufreq-u8500",
3092 .of_compatible
= "stericsson,cpufreq-u8500",
3093 .platform_data
= &db8500_cpufreq_table
,
3094 .pdata_size
= sizeof(db8500_cpufreq_table
),
3097 .name
= "ux500_wdt",
3098 .platform_data
= &db8500_wdt_pdata
,
3099 .pdata_size
= sizeof(db8500_wdt_pdata
),
3103 .name
= "ab8500-core",
3104 .of_compatible
= "stericsson,ab8500",
3105 .num_resources
= ARRAY_SIZE(ab8500_resources
),
3106 .resources
= ab8500_resources
,
3107 .id
= AB8500_VERSION_AB8500
,
3111 static void db8500_prcmu_update_cpufreq(void)
3113 if (prcmu_has_arm_maxopp()) {
3114 db8500_cpufreq_table
[3].frequency
= 1000000;
3115 db8500_cpufreq_table
[3].index
= ARM_MAX_OPP
;
3120 * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic
3123 static int db8500_prcmu_probe(struct platform_device
*pdev
)
3125 struct ab8500_platform_data
*ab8500_platdata
= pdev
->dev
.platform_data
;
3126 struct device_node
*np
= pdev
->dev
.of_node
;
3127 int irq
= 0, err
= 0, i
;
3132 init_prcm_registers();
3134 /* Clean up the mailbox interrupts after pre-kernel code. */
3135 writel(ALL_MBOX_BITS
, PRCM_ARM_IT1_CLR
);
3138 irq
= platform_get_irq(pdev
, 0);
3140 if (!np
|| irq
<= 0)
3141 irq
= IRQ_DB8500_PRCMU1
;
3143 err
= request_threaded_irq(irq
, prcmu_irq_handler
,
3144 prcmu_irq_thread_fn
, IRQF_NO_SUSPEND
, "prcmu", NULL
);
3146 pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n");
3151 db8500_irq_init(np
);
3153 for (i
= 0; i
< ARRAY_SIZE(db8500_prcmu_devs
); i
++) {
3154 if (!strcmp(db8500_prcmu_devs
[i
].name
, "ab8500-core")) {
3155 db8500_prcmu_devs
[i
].platform_data
= ab8500_platdata
;
3156 db8500_prcmu_devs
[i
].pdata_size
= sizeof(struct ab8500_platform_data
);
3160 if (cpu_is_u8500v20_or_later())
3161 prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET
);
3163 db8500_prcmu_update_cpufreq();
3165 err
= mfd_add_devices(&pdev
->dev
, 0, db8500_prcmu_devs
,
3166 ARRAY_SIZE(db8500_prcmu_devs
), NULL
, 0, NULL
);
3168 pr_err("prcmu: Failed to add subdevices\n");
3172 pr_info("DB8500 PRCMU initialized\n");
3177 static const struct of_device_id db8500_prcmu_match
[] = {
3178 { .compatible
= "stericsson,db8500-prcmu"},
3182 static struct platform_driver db8500_prcmu_driver
= {
3184 .name
= "db8500-prcmu",
3185 .owner
= THIS_MODULE
,
3186 .of_match_table
= db8500_prcmu_match
,
3188 .probe
= db8500_prcmu_probe
,
3191 static int __init
db8500_prcmu_init(void)
3193 return platform_driver_register(&db8500_prcmu_driver
);
3196 core_initcall(db8500_prcmu_init
);
3198 MODULE_AUTHOR("Mattias Nilsson <mattias.i.nilsson@stericsson.com>");
3199 MODULE_DESCRIPTION("DB8500 PRCM Unit driver");
3200 MODULE_LICENSE("GPL v2");