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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[linux-2.6/btrfs-unstable.git] / drivers / net / wireless / ath / ath9k / hw.c
blob1b5bd13b0a6c12ced3bda55c186fdf29475dbda2
1 /*
2 * Copyright (c) 2008-2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <linux/slab.h>
19 #include <asm/unaligned.h>
20
21 #include "hw.h"
22 #include "hw-ops.h"
23 #include "rc.h"
24 #include "ar9003_mac.h"
25
26 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
27
28 MODULE_AUTHOR("Atheros Communications");
29 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
30 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
31 MODULE_LICENSE("Dual BSD/GPL");
32
33 static int __init ath9k_init(void)
34 {
35 return 0;
36 }
37 module_init(ath9k_init);
38
39 static void __exit ath9k_exit(void)
40 {
41 return;
42 }
43 module_exit(ath9k_exit);
44
45 /* Private hardware callbacks */
46
47 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
48 {
49 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
50 }
51
52 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
53 {
54 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
55 }
56
57 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
58 struct ath9k_channel *chan)
59 {
60 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
61 }
62
63 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
64 {
65 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
66 return;
67
68 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
69 }
70
71 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
72 {
73 /* You will not have this callback if using the old ANI */
74 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
75 return;
76
77 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
78 }
79
80 /********************/
81 /* Helper Functions */
82 /********************/
83
84 static void ath9k_hw_set_clockrate(struct ath_hw *ah)
85 {
86 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
87 struct ath_common *common = ath9k_hw_common(ah);
88 unsigned int clockrate;
89
90 if (!ah->curchan) /* should really check for CCK instead */
91 clockrate = ATH9K_CLOCK_RATE_CCK;
92 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
93 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
94 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
95 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
96 else
97 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
98
99 if (conf_is_ht40(conf))
100 clockrate *= 2;
101
102 common->clockrate = clockrate;
103 }
104
105 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
106 {
107 struct ath_common *common = ath9k_hw_common(ah);
108
109 return usecs * common->clockrate;
110 }
111
112 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
113 {
114 int i;
115
116 BUG_ON(timeout < AH_TIME_QUANTUM);
117
118 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
119 if ((REG_READ(ah, reg) & mask) == val)
120 return true;
121
122 udelay(AH_TIME_QUANTUM);
123 }
124
125 ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY,
126 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
127 timeout, reg, REG_READ(ah, reg), mask, val);
128
129 return false;
130 }
131 EXPORT_SYMBOL(ath9k_hw_wait);
132
133 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
134 int column, unsigned int *writecnt)
135 {
136 int r;
137
138 ENABLE_REGWRITE_BUFFER(ah);
139 for (r = 0; r < array->ia_rows; r++) {
140 REG_WRITE(ah, INI_RA(array, r, 0),
141 INI_RA(array, r, column));
142 DO_DELAY(*writecnt);
143 }
144 REGWRITE_BUFFER_FLUSH(ah);
145 }
146
147 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
148 {
149 u32 retval;
150 int i;
151
152 for (i = 0, retval = 0; i < n; i++) {
153 retval = (retval << 1) | (val & 1);
154 val >>= 1;
155 }
156 return retval;
157 }
158
159 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
160 u8 phy, int kbps,
161 u32 frameLen, u16 rateix,
162 bool shortPreamble)
163 {
164 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
165
166 if (kbps == 0)
167 return 0;
168
169 switch (phy) {
170 case WLAN_RC_PHY_CCK:
171 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
172 if (shortPreamble)
173 phyTime >>= 1;
174 numBits = frameLen << 3;
175 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
176 break;
177 case WLAN_RC_PHY_OFDM:
178 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
179 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
180 numBits = OFDM_PLCP_BITS + (frameLen << 3);
181 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
182 txTime = OFDM_SIFS_TIME_QUARTER
183 + OFDM_PREAMBLE_TIME_QUARTER
184 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
185 } else if (ah->curchan &&
186 IS_CHAN_HALF_RATE(ah->curchan)) {
187 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
188 numBits = OFDM_PLCP_BITS + (frameLen << 3);
189 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
190 txTime = OFDM_SIFS_TIME_HALF +
191 OFDM_PREAMBLE_TIME_HALF
192 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
193 } else {
194 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
195 numBits = OFDM_PLCP_BITS + (frameLen << 3);
196 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
197 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
198 + (numSymbols * OFDM_SYMBOL_TIME);
199 }
200 break;
201 default:
202 ath_err(ath9k_hw_common(ah),
203 "Unknown phy %u (rate ix %u)\n", phy, rateix);
204 txTime = 0;
205 break;
206 }
207
208 return txTime;
209 }
210 EXPORT_SYMBOL(ath9k_hw_computetxtime);
211
212 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
213 struct ath9k_channel *chan,
214 struct chan_centers *centers)
215 {
216 int8_t extoff;
217
218 if (!IS_CHAN_HT40(chan)) {
219 centers->ctl_center = centers->ext_center =
220 centers->synth_center = chan->channel;
221 return;
222 }
223
224 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
225 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
226 centers->synth_center =
227 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
228 extoff = 1;
229 } else {
230 centers->synth_center =
231 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
232 extoff = -1;
233 }
234
235 centers->ctl_center =
236 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
237 /* 25 MHz spacing is supported by hw but not on upper layers */
238 centers->ext_center =
239 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
240 }
241
242 /******************/
243 /* Chip Revisions */
244 /******************/
245
246 static void ath9k_hw_read_revisions(struct ath_hw *ah)
247 {
248 u32 val;
249
250 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
251
252 if (val == 0xFF) {
253 val = REG_READ(ah, AR_SREV);
254 ah->hw_version.macVersion =
255 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
256 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
257 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
258 } else {
259 if (!AR_SREV_9100(ah))
260 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
261
262 ah->hw_version.macRev = val & AR_SREV_REVISION;
263
264 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
265 ah->is_pciexpress = true;
266 }
267 }
268
269 /************************************/
270 /* HW Attach, Detach, Init Routines */
271 /************************************/
272
273 static void ath9k_hw_disablepcie(struct ath_hw *ah)
274 {
275 if (!AR_SREV_5416(ah))
276 return;
277
278 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
279 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
280 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
281 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
282 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
283 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
284 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
285 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
286 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
287
288 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
289 }
290
291 /* This should work for all families including legacy */
292 static bool ath9k_hw_chip_test(struct ath_hw *ah)
293 {
294 struct ath_common *common = ath9k_hw_common(ah);
295 u32 regAddr[2] = { AR_STA_ID0 };
296 u32 regHold[2];
297 static const u32 patternData[4] = {
298 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
299 };
300 int i, j, loop_max;
301
302 if (!AR_SREV_9300_20_OR_LATER(ah)) {
303 loop_max = 2;
304 regAddr[1] = AR_PHY_BASE + (8 << 2);
305 } else
306 loop_max = 1;
307
308 for (i = 0; i < loop_max; i++) {
309 u32 addr = regAddr[i];
310 u32 wrData, rdData;
311
312 regHold[i] = REG_READ(ah, addr);
313 for (j = 0; j < 0x100; j++) {
314 wrData = (j << 16) | j;
315 REG_WRITE(ah, addr, wrData);
316 rdData = REG_READ(ah, addr);
317 if (rdData != wrData) {
318 ath_err(common,
319 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
320 addr, wrData, rdData);
321 return false;
322 }
323 }
324 for (j = 0; j < 4; j++) {
325 wrData = patternData[j];
326 REG_WRITE(ah, addr, wrData);
327 rdData = REG_READ(ah, addr);
328 if (wrData != rdData) {
329 ath_err(common,
330 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
331 addr, wrData, rdData);
332 return false;
333 }
334 }
335 REG_WRITE(ah, regAddr[i], regHold[i]);
336 }
337 udelay(100);
338
339 return true;
340 }
341
342 static void ath9k_hw_init_config(struct ath_hw *ah)
343 {
344 int i;
345
346 ah->config.dma_beacon_response_time = 2;
347 ah->config.sw_beacon_response_time = 10;
348 ah->config.additional_swba_backoff = 0;
349 ah->config.ack_6mb = 0x0;
350 ah->config.cwm_ignore_extcca = 0;
351 ah->config.pcie_powersave_enable = 0;
352 ah->config.pcie_clock_req = 0;
353 ah->config.pcie_waen = 0;
354 ah->config.analog_shiftreg = 1;
355 ah->config.enable_ani = true;
356
357 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
358 ah->config.spurchans[i][0] = AR_NO_SPUR;
359 ah->config.spurchans[i][1] = AR_NO_SPUR;
360 }
361
362 /* PAPRD needs some more work to be enabled */
363 ah->config.paprd_disable = 1;
364
365 ah->config.rx_intr_mitigation = true;
366 ah->config.pcieSerDesWrite = true;
367
368 /*
369 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
370 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
371 * This means we use it for all AR5416 devices, and the few
372 * minor PCI AR9280 devices out there.
373 *
374 * Serialization is required because these devices do not handle
375 * well the case of two concurrent reads/writes due to the latency
376 * involved. During one read/write another read/write can be issued
377 * on another CPU while the previous read/write may still be working
378 * on our hardware, if we hit this case the hardware poops in a loop.
379 * We prevent this by serializing reads and writes.
380 *
381 * This issue is not present on PCI-Express devices or pre-AR5416
382 * devices (legacy, 802.11abg).
383 */
384 if (num_possible_cpus() > 1)
385 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
386 }
387
388 static void ath9k_hw_init_defaults(struct ath_hw *ah)
389 {
390 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
391
392 regulatory->country_code = CTRY_DEFAULT;
393 regulatory->power_limit = MAX_RATE_POWER;
394 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
395
396 ah->hw_version.magic = AR5416_MAGIC;
397 ah->hw_version.subvendorid = 0;
398
399 ah->atim_window = 0;
400 ah->sta_id1_defaults =
401 AR_STA_ID1_CRPT_MIC_ENABLE |
402 AR_STA_ID1_MCAST_KSRCH;
403 if (AR_SREV_9100(ah))
404 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
405 ah->enable_32kHz_clock = DONT_USE_32KHZ;
406 ah->slottime = 20;
407 ah->globaltxtimeout = (u32) -1;
408 ah->power_mode = ATH9K_PM_UNDEFINED;
409 }
410
411 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
412 {
413 struct ath_common *common = ath9k_hw_common(ah);
414 u32 sum;
415 int i;
416 u16 eeval;
417 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
418
419 sum = 0;
420 for (i = 0; i < 3; i++) {
421 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
422 sum += eeval;
423 common->macaddr[2 * i] = eeval >> 8;
424 common->macaddr[2 * i + 1] = eeval & 0xff;
425 }
426 if (sum == 0 || sum == 0xffff * 3)
427 return -EADDRNOTAVAIL;
428
429 return 0;
430 }
431
432 static int ath9k_hw_post_init(struct ath_hw *ah)
433 {
434 struct ath_common *common = ath9k_hw_common(ah);
435 int ecode;
436
437 if (common->bus_ops->ath_bus_type != ATH_USB) {
438 if (!ath9k_hw_chip_test(ah))
439 return -ENODEV;
440 }
441
442 if (!AR_SREV_9300_20_OR_LATER(ah)) {
443 ecode = ar9002_hw_rf_claim(ah);
444 if (ecode != 0)
445 return ecode;
446 }
447
448 ecode = ath9k_hw_eeprom_init(ah);
449 if (ecode != 0)
450 return ecode;
451
452 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG,
453 "Eeprom VER: %d, REV: %d\n",
454 ah->eep_ops->get_eeprom_ver(ah),
455 ah->eep_ops->get_eeprom_rev(ah));
456
457 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
458 if (ecode) {
459 ath_err(ath9k_hw_common(ah),
460 "Failed allocating banks for external radio\n");
461 ath9k_hw_rf_free_ext_banks(ah);
462 return ecode;
463 }
464
465 if (!AR_SREV_9100(ah)) {
466 ath9k_hw_ani_setup(ah);
467 ath9k_hw_ani_init(ah);
468 }
469
470 return 0;
471 }
472
473 static void ath9k_hw_attach_ops(struct ath_hw *ah)
474 {
475 if (AR_SREV_9300_20_OR_LATER(ah))
476 ar9003_hw_attach_ops(ah);
477 else
478 ar9002_hw_attach_ops(ah);
479 }
480
481 /* Called for all hardware families */
482 static int __ath9k_hw_init(struct ath_hw *ah)
483 {
484 struct ath_common *common = ath9k_hw_common(ah);
485 int r = 0;
486
487 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
488 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
489
490 ath9k_hw_read_revisions(ah);
491
492 /*
493 * Read back AR_WA into a permanent copy and set bits 14 and 17.
494 * We need to do this to avoid RMW of this register. We cannot
495 * read the reg when chip is asleep.
496 */
497 ah->WARegVal = REG_READ(ah, AR_WA);
498 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
499 AR_WA_ASPM_TIMER_BASED_DISABLE);
500
501 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
502 ath_err(common, "Couldn't reset chip\n");
503 return -EIO;
504 }
505
506 ath9k_hw_init_defaults(ah);
507 ath9k_hw_init_config(ah);
508
509 ath9k_hw_attach_ops(ah);
510
511 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
512 ath_err(common, "Couldn't wakeup chip\n");
513 return -EIO;
514 }
515
516 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
517 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
518 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
519 !ah->is_pciexpress)) {
520 ah->config.serialize_regmode =
521 SER_REG_MODE_ON;
522 } else {
523 ah->config.serialize_regmode =
524 SER_REG_MODE_OFF;
525 }
526 }
527
528 ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
529 ah->config.serialize_regmode);
530
531 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
532 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
533 else
534 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
535
536 switch (ah->hw_version.macVersion) {
537 case AR_SREV_VERSION_5416_PCI:
538 case AR_SREV_VERSION_5416_PCIE:
539 case AR_SREV_VERSION_9160:
540 case AR_SREV_VERSION_9100:
541 case AR_SREV_VERSION_9280:
542 case AR_SREV_VERSION_9285:
543 case AR_SREV_VERSION_9287:
544 case AR_SREV_VERSION_9271:
545 case AR_SREV_VERSION_9300:
546 case AR_SREV_VERSION_9485:
547 break;
548 default:
549 ath_err(common,
550 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
551 ah->hw_version.macVersion, ah->hw_version.macRev);
552 return -EOPNOTSUPP;
553 }
554
555 if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
556 ah->is_pciexpress = false;
557
558 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
559 ath9k_hw_init_cal_settings(ah);
560
561 ah->ani_function = ATH9K_ANI_ALL;
562 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
563 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
564 if (!AR_SREV_9300_20_OR_LATER(ah))
565 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
566
567 ath9k_hw_init_mode_regs(ah);
568
569
570 if (ah->is_pciexpress)
571 ath9k_hw_configpcipowersave(ah, 0, 0);
572 else
573 ath9k_hw_disablepcie(ah);
574
575 if (!AR_SREV_9300_20_OR_LATER(ah))
576 ar9002_hw_cck_chan14_spread(ah);
577
578 r = ath9k_hw_post_init(ah);
579 if (r)
580 return r;
581
582 ath9k_hw_init_mode_gain_regs(ah);
583 r = ath9k_hw_fill_cap_info(ah);
584 if (r)
585 return r;
586
587 r = ath9k_hw_init_macaddr(ah);
588 if (r) {
589 ath_err(common, "Failed to initialize MAC address\n");
590 return r;
591 }
592
593 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
594 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
595 else
596 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
597
598 ah->bb_watchdog_timeout_ms = 25;
599
600 common->state = ATH_HW_INITIALIZED;
601
602 return 0;
603 }
604
605 int ath9k_hw_init(struct ath_hw *ah)
606 {
607 int ret;
608 struct ath_common *common = ath9k_hw_common(ah);
609
610 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
611 switch (ah->hw_version.devid) {
612 case AR5416_DEVID_PCI:
613 case AR5416_DEVID_PCIE:
614 case AR5416_AR9100_DEVID:
615 case AR9160_DEVID_PCI:
616 case AR9280_DEVID_PCI:
617 case AR9280_DEVID_PCIE:
618 case AR9285_DEVID_PCIE:
619 case AR9287_DEVID_PCI:
620 case AR9287_DEVID_PCIE:
621 case AR2427_DEVID_PCIE:
622 case AR9300_DEVID_PCIE:
623 case AR9300_DEVID_AR9485_PCIE:
624 break;
625 default:
626 if (common->bus_ops->ath_bus_type == ATH_USB)
627 break;
628 ath_err(common, "Hardware device ID 0x%04x not supported\n",
629 ah->hw_version.devid);
630 return -EOPNOTSUPP;
631 }
632
633 ret = __ath9k_hw_init(ah);
634 if (ret) {
635 ath_err(common,
636 "Unable to initialize hardware; initialization status: %d\n",
637 ret);
638 return ret;
639 }
640
641 return 0;
642 }
643 EXPORT_SYMBOL(ath9k_hw_init);
644
645 static void ath9k_hw_init_qos(struct ath_hw *ah)
646 {
647 ENABLE_REGWRITE_BUFFER(ah);
648
649 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
650 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
651
652 REG_WRITE(ah, AR_QOS_NO_ACK,
653 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
654 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
655 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
656
657 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
658 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
659 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
660 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
661 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
662
663 REGWRITE_BUFFER_FLUSH(ah);
664 }
665
666 unsigned long ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
667 {
668 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
669 udelay(100);
670 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
671
672 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
673 udelay(100);
674
675 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
676 }
677 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
678
679 #define DPLL2_KD_VAL 0x3D
680 #define DPLL2_KI_VAL 0x06
681 #define DPLL3_PHASE_SHIFT_VAL 0x1
682
683 static void ath9k_hw_init_pll(struct ath_hw *ah,
684 struct ath9k_channel *chan)
685 {
686 u32 pll;
687
688 if (AR_SREV_9485(ah)) {
689 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, 0x886666);
690 REG_WRITE(ah, AR_CH0_DDR_DPLL2, 0x19e82f01);
691
692 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
693 AR_CH0_DPLL3_PHASE_SHIFT, DPLL3_PHASE_SHIFT_VAL);
694
695 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
696 udelay(1000);
697
698 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, 0x886666);
699
700 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
701 AR_CH0_DPLL2_KD, DPLL2_KD_VAL);
702 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
703 AR_CH0_DPLL2_KI, DPLL2_KI_VAL);
704
705 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
706 AR_CH0_DPLL3_PHASE_SHIFT, DPLL3_PHASE_SHIFT_VAL);
707 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x142c);
708 udelay(1000);
709 }
710
711 pll = ath9k_hw_compute_pll_control(ah, chan);
712
713 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
714
715 /* Switch the core clock for ar9271 to 117Mhz */
716 if (AR_SREV_9271(ah)) {
717 udelay(500);
718 REG_WRITE(ah, 0x50040, 0x304);
719 }
720
721 udelay(RTC_PLL_SETTLE_DELAY);
722
723 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
724 }
725
726 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
727 enum nl80211_iftype opmode)
728 {
729 u32 imr_reg = AR_IMR_TXERR |
730 AR_IMR_TXURN |
731 AR_IMR_RXERR |
732 AR_IMR_RXORN |
733 AR_IMR_BCNMISC;
734
735 if (AR_SREV_9300_20_OR_LATER(ah)) {
736 imr_reg |= AR_IMR_RXOK_HP;
737 if (ah->config.rx_intr_mitigation)
738 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
739 else
740 imr_reg |= AR_IMR_RXOK_LP;
741
742 } else {
743 if (ah->config.rx_intr_mitigation)
744 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
745 else
746 imr_reg |= AR_IMR_RXOK;
747 }
748
749 if (ah->config.tx_intr_mitigation)
750 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
751 else
752 imr_reg |= AR_IMR_TXOK;
753
754 if (opmode == NL80211_IFTYPE_AP)
755 imr_reg |= AR_IMR_MIB;
756
757 ENABLE_REGWRITE_BUFFER(ah);
758
759 REG_WRITE(ah, AR_IMR, imr_reg);
760 ah->imrs2_reg |= AR_IMR_S2_GTT;
761 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
762
763 if (!AR_SREV_9100(ah)) {
764 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
765 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
766 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
767 }
768
769 REGWRITE_BUFFER_FLUSH(ah);
770
771 if (AR_SREV_9300_20_OR_LATER(ah)) {
772 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
773 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
774 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
775 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
776 }
777 }
778
779 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
780 {
781 u32 val = ath9k_hw_mac_to_clks(ah, us);
782 val = min(val, (u32) 0xFFFF);
783 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
784 }
785
786 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
787 {
788 u32 val = ath9k_hw_mac_to_clks(ah, us);
789 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
790 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
791 }
792
793 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
794 {
795 u32 val = ath9k_hw_mac_to_clks(ah, us);
796 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
797 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
798 }
799
800 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
801 {
802 if (tu > 0xFFFF) {
803 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
804 "bad global tx timeout %u\n", tu);
805 ah->globaltxtimeout = (u32) -1;
806 return false;
807 } else {
808 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
809 ah->globaltxtimeout = tu;
810 return true;
811 }
812 }
813
814 void ath9k_hw_init_global_settings(struct ath_hw *ah)
815 {
816 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
817 int acktimeout;
818 int slottime;
819 int sifstime;
820
821 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
822 ah->misc_mode);
823
824 if (ah->misc_mode != 0)
825 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
826
827 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
828 sifstime = 16;
829 else
830 sifstime = 10;
831
832 /* As defined by IEEE 802.11-2007 17.3.8.6 */
833 slottime = ah->slottime + 3 * ah->coverage_class;
834 acktimeout = slottime + sifstime;
835
836 /*
837 * Workaround for early ACK timeouts, add an offset to match the
838 * initval's 64us ack timeout value.
839 * This was initially only meant to work around an issue with delayed
840 * BA frames in some implementations, but it has been found to fix ACK
841 * timeout issues in other cases as well.
842 */
843 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
844 acktimeout += 64 - sifstime - ah->slottime;
845
846 ath9k_hw_setslottime(ah, ah->slottime);
847 ath9k_hw_set_ack_timeout(ah, acktimeout);
848 ath9k_hw_set_cts_timeout(ah, acktimeout);
849 if (ah->globaltxtimeout != (u32) -1)
850 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
851 }
852 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
853
854 void ath9k_hw_deinit(struct ath_hw *ah)
855 {
856 struct ath_common *common = ath9k_hw_common(ah);
857
858 if (common->state < ATH_HW_INITIALIZED)
859 goto free_hw;
860
861 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
862
863 free_hw:
864 ath9k_hw_rf_free_ext_banks(ah);
865 }
866 EXPORT_SYMBOL(ath9k_hw_deinit);
867
868 /*******/
869 /* INI */
870 /*******/
871
872 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
873 {
874 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
875
876 if (IS_CHAN_B(chan))
877 ctl |= CTL_11B;
878 else if (IS_CHAN_G(chan))
879 ctl |= CTL_11G;
880 else
881 ctl |= CTL_11A;
882
883 return ctl;
884 }
885
886 /****************************************/
887 /* Reset and Channel Switching Routines */
888 /****************************************/
889
890 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
891 {
892 struct ath_common *common = ath9k_hw_common(ah);
893
894 ENABLE_REGWRITE_BUFFER(ah);
895
896 /*
897 * set AHB_MODE not to do cacheline prefetches
898 */
899 if (!AR_SREV_9300_20_OR_LATER(ah))
900 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
901
902 /*
903 * let mac dma reads be in 128 byte chunks
904 */
905 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
906
907 REGWRITE_BUFFER_FLUSH(ah);
908
909 /*
910 * Restore TX Trigger Level to its pre-reset value.
911 * The initial value depends on whether aggregation is enabled, and is
912 * adjusted whenever underruns are detected.
913 */
914 if (!AR_SREV_9300_20_OR_LATER(ah))
915 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
916
917 ENABLE_REGWRITE_BUFFER(ah);
918
919 /*
920 * let mac dma writes be in 128 byte chunks
921 */
922 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
923
924 /*
925 * Setup receive FIFO threshold to hold off TX activities
926 */
927 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
928
929 if (AR_SREV_9300_20_OR_LATER(ah)) {
930 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
931 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
932
933 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
934 ah->caps.rx_status_len);
935 }
936
937 /*
938 * reduce the number of usable entries in PCU TXBUF to avoid
939 * wrap around issues.
940 */
941 if (AR_SREV_9285(ah)) {
942 /* For AR9285 the number of Fifos are reduced to half.
943 * So set the usable tx buf size also to half to
944 * avoid data/delimiter underruns
945 */
946 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
947 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
948 } else if (!AR_SREV_9271(ah)) {
949 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
950 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
951 }
952
953 REGWRITE_BUFFER_FLUSH(ah);
954
955 if (AR_SREV_9300_20_OR_LATER(ah))
956 ath9k_hw_reset_txstatus_ring(ah);
957 }
958
959 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
960 {
961 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
962 u32 set = AR_STA_ID1_KSRCH_MODE;
963
964 switch (opmode) {
965 case NL80211_IFTYPE_ADHOC:
966 case NL80211_IFTYPE_MESH_POINT:
967 set |= AR_STA_ID1_ADHOC;
968 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
969 break;
970 case NL80211_IFTYPE_AP:
971 set |= AR_STA_ID1_STA_AP;
972 /* fall through */
973 case NL80211_IFTYPE_STATION:
974 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
975 break;
976 default:
977 if (!ah->is_monitoring)
978 set = 0;
979 break;
980 }
981 REG_RMW(ah, AR_STA_ID1, set, mask);
982 }
983
984 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
985 u32 *coef_mantissa, u32 *coef_exponent)
986 {
987 u32 coef_exp, coef_man;
988
989 for (coef_exp = 31; coef_exp > 0; coef_exp--)
990 if ((coef_scaled >> coef_exp) & 0x1)
991 break;
992
993 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
994
995 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
996
997 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
998 *coef_exponent = coef_exp - 16;
999 }
1000
1001 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1002 {
1003 u32 rst_flags;
1004 u32 tmpReg;
1005
1006 if (AR_SREV_9100(ah)) {
1007 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1008 AR_RTC_DERIVED_CLK_PERIOD, 1);
1009 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1010 }
1011
1012 ENABLE_REGWRITE_BUFFER(ah);
1013
1014 if (AR_SREV_9300_20_OR_LATER(ah)) {
1015 REG_WRITE(ah, AR_WA, ah->WARegVal);
1016 udelay(10);
1017 }
1018
1019 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1020 AR_RTC_FORCE_WAKE_ON_INT);
1021
1022 if (AR_SREV_9100(ah)) {
1023 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1024 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1025 } else {
1026 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1027 if (tmpReg &
1028 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1029 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1030 u32 val;
1031 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1032
1033 val = AR_RC_HOSTIF;
1034 if (!AR_SREV_9300_20_OR_LATER(ah))
1035 val |= AR_RC_AHB;
1036 REG_WRITE(ah, AR_RC, val);
1037
1038 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1039 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1040
1041 rst_flags = AR_RTC_RC_MAC_WARM;
1042 if (type == ATH9K_RESET_COLD)
1043 rst_flags |= AR_RTC_RC_MAC_COLD;
1044 }
1045
1046 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1047
1048 REGWRITE_BUFFER_FLUSH(ah);
1049
1050 udelay(50);
1051
1052 REG_WRITE(ah, AR_RTC_RC, 0);
1053 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1054 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1055 "RTC stuck in MAC reset\n");
1056 return false;
1057 }
1058
1059 if (!AR_SREV_9100(ah))
1060 REG_WRITE(ah, AR_RC, 0);
1061
1062 if (AR_SREV_9100(ah))
1063 udelay(50);
1064
1065 return true;
1066 }
1067
1068 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1069 {
1070 ENABLE_REGWRITE_BUFFER(ah);
1071
1072 if (AR_SREV_9300_20_OR_LATER(ah)) {
1073 REG_WRITE(ah, AR_WA, ah->WARegVal);
1074 udelay(10);
1075 }
1076
1077 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1078 AR_RTC_FORCE_WAKE_ON_INT);
1079
1080 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1081 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1082
1083 REG_WRITE(ah, AR_RTC_RESET, 0);
1084
1085 REGWRITE_BUFFER_FLUSH(ah);
1086
1087 if (!AR_SREV_9300_20_OR_LATER(ah))
1088 udelay(2);
1089
1090 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1091 REG_WRITE(ah, AR_RC, 0);
1092
1093 REG_WRITE(ah, AR_RTC_RESET, 1);
1094
1095 if (!ath9k_hw_wait(ah,
1096 AR_RTC_STATUS,
1097 AR_RTC_STATUS_M,
1098 AR_RTC_STATUS_ON,
1099 AH_WAIT_TIMEOUT)) {
1100 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1101 "RTC not waking up\n");
1102 return false;
1103 }
1104
1105 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1106 }
1107
1108 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1109 {
1110 if (AR_SREV_9300_20_OR_LATER(ah)) {
1111 REG_WRITE(ah, AR_WA, ah->WARegVal);
1112 udelay(10);
1113 }
1114
1115 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1116 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1117
1118 switch (type) {
1119 case ATH9K_RESET_POWER_ON:
1120 return ath9k_hw_set_reset_power_on(ah);
1121 case ATH9K_RESET_WARM:
1122 case ATH9K_RESET_COLD:
1123 return ath9k_hw_set_reset(ah, type);
1124 default:
1125 return false;
1126 }
1127 }
1128
1129 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1130 struct ath9k_channel *chan)
1131 {
1132 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1133 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1134 return false;
1135 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1136 return false;
1137
1138 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1139 return false;
1140
1141 ah->chip_fullsleep = false;
1142 ath9k_hw_init_pll(ah, chan);
1143 ath9k_hw_set_rfmode(ah, chan);
1144
1145 return true;
1146 }
1147
1148 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1149 struct ath9k_channel *chan)
1150 {
1151 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1152 struct ath_common *common = ath9k_hw_common(ah);
1153 struct ieee80211_channel *channel = chan->chan;
1154 u32 qnum;
1155 int r;
1156
1157 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1158 if (ath9k_hw_numtxpending(ah, qnum)) {
1159 ath_dbg(common, ATH_DBG_QUEUE,
1160 "Transmit frames pending on queue %d\n", qnum);
1161 return false;
1162 }
1163 }
1164
1165 if (!ath9k_hw_rfbus_req(ah)) {
1166 ath_err(common, "Could not kill baseband RX\n");
1167 return false;
1168 }
1169
1170 ath9k_hw_set_channel_regs(ah, chan);
1171
1172 r = ath9k_hw_rf_set_freq(ah, chan);
1173 if (r) {
1174 ath_err(common, "Failed to set channel\n");
1175 return false;
1176 }
1177 ath9k_hw_set_clockrate(ah);
1178
1179 ah->eep_ops->set_txpower(ah, chan,
1180 ath9k_regd_get_ctl(regulatory, chan),
1181 channel->max_antenna_gain * 2,
1182 channel->max_power * 2,
1183 min((u32) MAX_RATE_POWER,
1184 (u32) regulatory->power_limit), false);
1185
1186 ath9k_hw_rfbus_done(ah);
1187
1188 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1189 ath9k_hw_set_delta_slope(ah, chan);
1190
1191 ath9k_hw_spur_mitigate_freq(ah, chan);
1192
1193 return true;
1194 }
1195
1196 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1197 {
1198 u32 gpio_mask = ah->gpio_mask;
1199 int i;
1200
1201 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1202 if (!(gpio_mask & 1))
1203 continue;
1204
1205 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1206 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1207 }
1208 }
1209
1210 bool ath9k_hw_check_alive(struct ath_hw *ah)
1211 {
1212 int count = 50;
1213 u32 reg;
1214
1215 if (AR_SREV_9285_12_OR_LATER(ah))
1216 return true;
1217
1218 do {
1219 reg = REG_READ(ah, AR_OBS_BUS_1);
1220
1221 if ((reg & 0x7E7FFFEF) == 0x00702400)
1222 continue;
1223
1224 switch (reg & 0x7E000B00) {
1225 case 0x1E000000:
1226 case 0x52000B00:
1227 case 0x18000B00:
1228 continue;
1229 default:
1230 return true;
1231 }
1232 } while (count-- > 0);
1233
1234 return false;
1235 }
1236 EXPORT_SYMBOL(ath9k_hw_check_alive);
1237
1238 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1239 struct ath9k_hw_cal_data *caldata, bool bChannelChange)
1240 {
1241 struct ath_common *common = ath9k_hw_common(ah);
1242 u32 saveLedState;
1243 struct ath9k_channel *curchan = ah->curchan;
1244 u32 saveDefAntenna;
1245 u32 macStaId1;
1246 u64 tsf = 0;
1247 int i, r;
1248
1249 ah->txchainmask = common->tx_chainmask;
1250 ah->rxchainmask = common->rx_chainmask;
1251
1252 if ((common->bus_ops->ath_bus_type != ATH_USB) && !ah->chip_fullsleep) {
1253 ath9k_hw_abortpcurecv(ah);
1254 if (!ath9k_hw_stopdmarecv(ah)) {
1255 ath_dbg(common, ATH_DBG_XMIT,
1256 "Failed to stop receive dma\n");
1257 bChannelChange = false;
1258 }
1259 }
1260
1261 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1262 return -EIO;
1263
1264 if (curchan && !ah->chip_fullsleep)
1265 ath9k_hw_getnf(ah, curchan);
1266
1267 ah->caldata = caldata;
1268 if (caldata &&
1269 (chan->channel != caldata->channel ||
1270 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1271 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1272 /* Operating channel changed, reset channel calibration data */
1273 memset(caldata, 0, sizeof(*caldata));
1274 ath9k_init_nfcal_hist_buffer(ah, chan);
1275 }
1276
1277 if (bChannelChange &&
1278 (ah->chip_fullsleep != true) &&
1279 (ah->curchan != NULL) &&
1280 (chan->channel != ah->curchan->channel) &&
1281 ((chan->channelFlags & CHANNEL_ALL) ==
1282 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1283 (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) {
1284
1285 if (ath9k_hw_channel_change(ah, chan)) {
1286 ath9k_hw_loadnf(ah, ah->curchan);
1287 ath9k_hw_start_nfcal(ah, true);
1288 if (AR_SREV_9271(ah))
1289 ar9002_hw_load_ani_reg(ah, chan);
1290 return 0;
1291 }
1292 }
1293
1294 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1295 if (saveDefAntenna == 0)
1296 saveDefAntenna = 1;
1297
1298 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1299
1300 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1301 if (AR_SREV_9100(ah) ||
1302 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
1303 tsf = ath9k_hw_gettsf64(ah);
1304
1305 saveLedState = REG_READ(ah, AR_CFG_LED) &
1306 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1307 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1308
1309 ath9k_hw_mark_phy_inactive(ah);
1310
1311 ah->paprd_table_write_done = false;
1312
1313 /* Only required on the first reset */
1314 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1315 REG_WRITE(ah,
1316 AR9271_RESET_POWER_DOWN_CONTROL,
1317 AR9271_RADIO_RF_RST);
1318 udelay(50);
1319 }
1320
1321 if (!ath9k_hw_chip_reset(ah, chan)) {
1322 ath_err(common, "Chip reset failed\n");
1323 return -EINVAL;
1324 }
1325
1326 /* Only required on the first reset */
1327 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1328 ah->htc_reset_init = false;
1329 REG_WRITE(ah,
1330 AR9271_RESET_POWER_DOWN_CONTROL,
1331 AR9271_GATE_MAC_CTL);
1332 udelay(50);
1333 }
1334
1335 /* Restore TSF */
1336 if (tsf)
1337 ath9k_hw_settsf64(ah, tsf);
1338
1339 if (AR_SREV_9280_20_OR_LATER(ah))
1340 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1341
1342 if (!AR_SREV_9300_20_OR_LATER(ah))
1343 ar9002_hw_enable_async_fifo(ah);
1344
1345 r = ath9k_hw_process_ini(ah, chan);
1346 if (r)
1347 return r;
1348
1349 /*
1350 * Some AR91xx SoC devices frequently fail to accept TSF writes
1351 * right after the chip reset. When that happens, write a new
1352 * value after the initvals have been applied, with an offset
1353 * based on measured time difference
1354 */
1355 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1356 tsf += 1500;
1357 ath9k_hw_settsf64(ah, tsf);
1358 }
1359
1360 /* Setup MFP options for CCMP */
1361 if (AR_SREV_9280_20_OR_LATER(ah)) {
1362 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1363 * frames when constructing CCMP AAD. */
1364 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1365 0xc7ff);
1366 ah->sw_mgmt_crypto = false;
1367 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1368 /* Disable hardware crypto for management frames */
1369 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1370 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1371 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1372 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1373 ah->sw_mgmt_crypto = true;
1374 } else
1375 ah->sw_mgmt_crypto = true;
1376
1377 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1378 ath9k_hw_set_delta_slope(ah, chan);
1379
1380 ath9k_hw_spur_mitigate_freq(ah, chan);
1381 ah->eep_ops->set_board_values(ah, chan);
1382
1383 ENABLE_REGWRITE_BUFFER(ah);
1384
1385 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1386 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1387 | macStaId1
1388 | AR_STA_ID1_RTS_USE_DEF
1389 | (ah->config.
1390 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1391 | ah->sta_id1_defaults);
1392 ath_hw_setbssidmask(common);
1393 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1394 ath9k_hw_write_associd(ah);
1395 REG_WRITE(ah, AR_ISR, ~0);
1396 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1397
1398 REGWRITE_BUFFER_FLUSH(ah);
1399
1400 ath9k_hw_set_operating_mode(ah, ah->opmode);
1401
1402 r = ath9k_hw_rf_set_freq(ah, chan);
1403 if (r)
1404 return r;
1405
1406 ath9k_hw_set_clockrate(ah);
1407
1408 ENABLE_REGWRITE_BUFFER(ah);
1409
1410 for (i = 0; i < AR_NUM_DCU; i++)
1411 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1412
1413 REGWRITE_BUFFER_FLUSH(ah);
1414
1415 ah->intr_txqs = 0;
1416 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1417 ath9k_hw_resettxqueue(ah, i);
1418
1419 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1420 ath9k_hw_ani_cache_ini_regs(ah);
1421 ath9k_hw_init_qos(ah);
1422
1423 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1424 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1425
1426 ath9k_hw_init_global_settings(ah);
1427
1428 if (!AR_SREV_9300_20_OR_LATER(ah)) {
1429 ar9002_hw_update_async_fifo(ah);
1430 ar9002_hw_enable_wep_aggregation(ah);
1431 }
1432
1433 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
1434
1435 ath9k_hw_set_dma(ah);
1436
1437 REG_WRITE(ah, AR_OBS, 8);
1438
1439 if (ah->config.rx_intr_mitigation) {
1440 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1441 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1442 }
1443
1444 if (ah->config.tx_intr_mitigation) {
1445 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1446 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1447 }
1448
1449 ath9k_hw_init_bb(ah, chan);
1450
1451 if (!ath9k_hw_init_cal(ah, chan))
1452 return -EIO;
1453
1454 ENABLE_REGWRITE_BUFFER(ah);
1455
1456 ath9k_hw_restore_chainmask(ah);
1457 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1458
1459 REGWRITE_BUFFER_FLUSH(ah);
1460
1461 /*
1462 * For big endian systems turn on swapping for descriptors
1463 */
1464 if (AR_SREV_9100(ah)) {
1465 u32 mask;
1466 mask = REG_READ(ah, AR_CFG);
1467 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1468 ath_dbg(common, ATH_DBG_RESET,
1469 "CFG Byte Swap Set 0x%x\n", mask);
1470 } else {
1471 mask =
1472 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1473 REG_WRITE(ah, AR_CFG, mask);
1474 ath_dbg(common, ATH_DBG_RESET,
1475 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1476 }
1477 } else {
1478 if (common->bus_ops->ath_bus_type == ATH_USB) {
1479 /* Configure AR9271 target WLAN */
1480 if (AR_SREV_9271(ah))
1481 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1482 else
1483 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1484 }
1485 #ifdef __BIG_ENDIAN
1486 else
1487 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1488 #endif
1489 }
1490
1491 if (ah->btcoex_hw.enabled)
1492 ath9k_hw_btcoex_enable(ah);
1493
1494 if (AR_SREV_9300_20_OR_LATER(ah))
1495 ar9003_hw_bb_watchdog_config(ah);
1496
1497 ath9k_hw_apply_gpio_override(ah);
1498
1499 return 0;
1500 }
1501 EXPORT_SYMBOL(ath9k_hw_reset);
1502
1503 /******************************/
1504 /* Power Management (Chipset) */
1505 /******************************/
1506
1507 /*
1508 * Notify Power Mgt is disabled in self-generated frames.
1509 * If requested, force chip to sleep.
1510 */
1511 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1512 {
1513 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1514 if (setChip) {
1515 /*
1516 * Clear the RTC force wake bit to allow the
1517 * mac to go to sleep.
1518 */
1519 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1520 AR_RTC_FORCE_WAKE_EN);
1521 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1522 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1523
1524 /* Shutdown chip. Active low */
1525 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
1526 REG_CLR_BIT(ah, (AR_RTC_RESET),
1527 AR_RTC_RESET_EN);
1528 }
1529
1530 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
1531 if (AR_SREV_9300_20_OR_LATER(ah))
1532 REG_WRITE(ah, AR_WA,
1533 ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1534 }
1535
1536 /*
1537 * Notify Power Management is enabled in self-generating
1538 * frames. If request, set power mode of chip to
1539 * auto/normal. Duration in units of 128us (1/8 TU).
1540 */
1541 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1542 {
1543 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1544 if (setChip) {
1545 struct ath9k_hw_capabilities *pCap = &ah->caps;
1546
1547 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1548 /* Set WakeOnInterrupt bit; clear ForceWake bit */
1549 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1550 AR_RTC_FORCE_WAKE_ON_INT);
1551 } else {
1552 /*
1553 * Clear the RTC force wake bit to allow the
1554 * mac to go to sleep.
1555 */
1556 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1557 AR_RTC_FORCE_WAKE_EN);
1558 }
1559 }
1560
1561 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
1562 if (AR_SREV_9300_20_OR_LATER(ah))
1563 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1564 }
1565
1566 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1567 {
1568 u32 val;
1569 int i;
1570
1571 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
1572 if (AR_SREV_9300_20_OR_LATER(ah)) {
1573 REG_WRITE(ah, AR_WA, ah->WARegVal);
1574 udelay(10);
1575 }
1576
1577 if (setChip) {
1578 if ((REG_READ(ah, AR_RTC_STATUS) &
1579 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1580 if (ath9k_hw_set_reset_reg(ah,
1581 ATH9K_RESET_POWER_ON) != true) {
1582 return false;
1583 }
1584 if (!AR_SREV_9300_20_OR_LATER(ah))
1585 ath9k_hw_init_pll(ah, NULL);
1586 }
1587 if (AR_SREV_9100(ah))
1588 REG_SET_BIT(ah, AR_RTC_RESET,
1589 AR_RTC_RESET_EN);
1590
1591 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1592 AR_RTC_FORCE_WAKE_EN);
1593 udelay(50);
1594
1595 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1596 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1597 if (val == AR_RTC_STATUS_ON)
1598 break;
1599 udelay(50);
1600 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1601 AR_RTC_FORCE_WAKE_EN);
1602 }
1603 if (i == 0) {
1604 ath_err(ath9k_hw_common(ah),
1605 "Failed to wakeup in %uus\n",
1606 POWER_UP_TIME / 20);
1607 return false;
1608 }
1609 }
1610
1611 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1612
1613 return true;
1614 }
1615
1616 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1617 {
1618 struct ath_common *common = ath9k_hw_common(ah);
1619 int status = true, setChip = true;
1620 static const char *modes[] = {
1621 "AWAKE",
1622 "FULL-SLEEP",
1623 "NETWORK SLEEP",
1624 "UNDEFINED"
1625 };
1626
1627 if (ah->power_mode == mode)
1628 return status;
1629
1630 ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n",
1631 modes[ah->power_mode], modes[mode]);
1632
1633 switch (mode) {
1634 case ATH9K_PM_AWAKE:
1635 status = ath9k_hw_set_power_awake(ah, setChip);
1636 break;
1637 case ATH9K_PM_FULL_SLEEP:
1638 ath9k_set_power_sleep(ah, setChip);
1639 ah->chip_fullsleep = true;
1640 break;
1641 case ATH9K_PM_NETWORK_SLEEP:
1642 ath9k_set_power_network_sleep(ah, setChip);
1643 break;
1644 default:
1645 ath_err(common, "Unknown power mode %u\n", mode);
1646 return false;
1647 }
1648 ah->power_mode = mode;
1649
1650 /*
1651 * XXX: If this warning never comes up after a while then
1652 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
1653 * ath9k_hw_setpower() return type void.
1654 */
1655
1656 if (!(ah->ah_flags & AH_UNPLUGGED))
1657 ATH_DBG_WARN_ON_ONCE(!status);
1658
1659 return status;
1660 }
1661 EXPORT_SYMBOL(ath9k_hw_setpower);
1662
1663 /*******************/
1664 /* Beacon Handling */
1665 /*******************/
1666
1667 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1668 {
1669 int flags = 0;
1670
1671 ENABLE_REGWRITE_BUFFER(ah);
1672
1673 switch (ah->opmode) {
1674 case NL80211_IFTYPE_ADHOC:
1675 case NL80211_IFTYPE_MESH_POINT:
1676 REG_SET_BIT(ah, AR_TXCFG,
1677 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1678 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
1679 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
1680 flags |= AR_NDP_TIMER_EN;
1681 case NL80211_IFTYPE_AP:
1682 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
1683 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
1684 TU_TO_USEC(ah->config.dma_beacon_response_time));
1685 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
1686 TU_TO_USEC(ah->config.sw_beacon_response_time));
1687 flags |=
1688 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1689 break;
1690 default:
1691 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON,
1692 "%s: unsupported opmode: %d\n",
1693 __func__, ah->opmode);
1694 return;
1695 break;
1696 }
1697
1698 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
1699 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
1700 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
1701 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
1702
1703 REGWRITE_BUFFER_FLUSH(ah);
1704
1705 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1706 }
1707 EXPORT_SYMBOL(ath9k_hw_beaconinit);
1708
1709 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1710 const struct ath9k_beacon_state *bs)
1711 {
1712 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
1713 struct ath9k_hw_capabilities *pCap = &ah->caps;
1714 struct ath_common *common = ath9k_hw_common(ah);
1715
1716 ENABLE_REGWRITE_BUFFER(ah);
1717
1718 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1719
1720 REG_WRITE(ah, AR_BEACON_PERIOD,
1721 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1722 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1723 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1724
1725 REGWRITE_BUFFER_FLUSH(ah);
1726
1727 REG_RMW_FIELD(ah, AR_RSSI_THR,
1728 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1729
1730 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1731
1732 if (bs->bs_sleepduration > beaconintval)
1733 beaconintval = bs->bs_sleepduration;
1734
1735 dtimperiod = bs->bs_dtimperiod;
1736 if (bs->bs_sleepduration > dtimperiod)
1737 dtimperiod = bs->bs_sleepduration;
1738
1739 if (beaconintval == dtimperiod)
1740 nextTbtt = bs->bs_nextdtim;
1741 else
1742 nextTbtt = bs->bs_nexttbtt;
1743
1744 ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1745 ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1746 ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1747 ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
1748
1749 ENABLE_REGWRITE_BUFFER(ah);
1750
1751 REG_WRITE(ah, AR_NEXT_DTIM,
1752 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1753 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
1754
1755 REG_WRITE(ah, AR_SLEEP1,
1756 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1757 | AR_SLEEP1_ASSUME_DTIM);
1758
1759 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1760 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1761 else
1762 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
1763
1764 REG_WRITE(ah, AR_SLEEP2,
1765 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
1766
1767 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1768 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
1769
1770 REGWRITE_BUFFER_FLUSH(ah);
1771
1772 REG_SET_BIT(ah, AR_TIMER_MODE,
1773 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
1774 AR_DTIM_TIMER_EN);
1775
1776 /* TSF Out of Range Threshold */
1777 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
1778 }
1779 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
1780
1781 /*******************/
1782 /* HW Capabilities */
1783 /*******************/
1784
1785 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1786 {
1787 struct ath9k_hw_capabilities *pCap = &ah->caps;
1788 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1789 struct ath_common *common = ath9k_hw_common(ah);
1790 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
1791
1792 u16 capField = 0, eeval;
1793 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
1794
1795 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
1796 regulatory->current_rd = eeval;
1797
1798 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
1799 if (AR_SREV_9285_12_OR_LATER(ah))
1800 eeval |= AR9285_RDEXT_DEFAULT;
1801 regulatory->current_rd_ext = eeval;
1802
1803 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
1804
1805 if (ah->opmode != NL80211_IFTYPE_AP &&
1806 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
1807 if (regulatory->current_rd == 0x64 ||
1808 regulatory->current_rd == 0x65)
1809 regulatory->current_rd += 5;
1810 else if (regulatory->current_rd == 0x41)
1811 regulatory->current_rd = 0x43;
1812 ath_dbg(common, ATH_DBG_REGULATORY,
1813 "regdomain mapped to 0x%x\n", regulatory->current_rd);
1814 }
1815
1816 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
1817 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
1818 ath_err(common,
1819 "no band has been marked as supported in EEPROM\n");
1820 return -EINVAL;
1821 }
1822
1823 if (eeval & AR5416_OPFLAGS_11A)
1824 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
1825
1826 if (eeval & AR5416_OPFLAGS_11G)
1827 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
1828
1829 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
1830 /*
1831 * For AR9271 we will temporarilly uses the rx chainmax as read from
1832 * the EEPROM.
1833 */
1834 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
1835 !(eeval & AR5416_OPFLAGS_11A) &&
1836 !(AR_SREV_9271(ah)))
1837 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
1838 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
1839 else if (AR_SREV_9100(ah))
1840 pCap->rx_chainmask = 0x7;
1841 else
1842 /* Use rx_chainmask from EEPROM. */
1843 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
1844
1845 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
1846
1847 /* enable key search for every frame in an aggregate */
1848 if (AR_SREV_9300_20_OR_LATER(ah))
1849 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
1850
1851 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
1852
1853 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
1854 pCap->hw_caps |= ATH9K_HW_CAP_HT;
1855 else
1856 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
1857
1858 if (AR_SREV_9271(ah))
1859 pCap->num_gpio_pins = AR9271_NUM_GPIO;
1860 else if (AR_DEVID_7010(ah))
1861 pCap->num_gpio_pins = AR7010_NUM_GPIO;
1862 else if (AR_SREV_9285_12_OR_LATER(ah))
1863 pCap->num_gpio_pins = AR9285_NUM_GPIO;
1864 else if (AR_SREV_9280_20_OR_LATER(ah))
1865 pCap->num_gpio_pins = AR928X_NUM_GPIO;
1866 else
1867 pCap->num_gpio_pins = AR_NUM_GPIO;
1868
1869 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
1870 pCap->hw_caps |= ATH9K_HW_CAP_CST;
1871 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
1872 } else {
1873 pCap->rts_aggr_limit = (8 * 1024);
1874 }
1875
1876 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1877 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
1878 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
1879 ah->rfkill_gpio =
1880 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
1881 ah->rfkill_polarity =
1882 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
1883
1884 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
1885 }
1886 #endif
1887 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
1888 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
1889 else
1890 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
1891
1892 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
1893 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
1894 else
1895 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
1896
1897 if (AR_SREV_9280_20_OR_LATER(ah) && common->btcoex_enabled) {
1898 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
1899 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
1900
1901 if (AR_SREV_9285(ah)) {
1902 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
1903 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
1904 } else {
1905 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
1906 }
1907 } else {
1908 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
1909 }
1910
1911 if (AR_SREV_9300_20_OR_LATER(ah)) {
1912 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
1913 if (!AR_SREV_9485(ah))
1914 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
1915
1916 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
1917 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
1918 pCap->rx_status_len = sizeof(struct ar9003_rxs);
1919 pCap->tx_desc_len = sizeof(struct ar9003_txc);
1920 pCap->txs_len = sizeof(struct ar9003_txs);
1921 if (!ah->config.paprd_disable &&
1922 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
1923 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
1924 } else {
1925 pCap->tx_desc_len = sizeof(struct ath_desc);
1926 if (AR_SREV_9280_20(ah) &&
1927 ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
1928 AR5416_EEP_MINOR_VER_16) ||
1929 ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
1930 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
1931 }
1932
1933 if (AR_SREV_9300_20_OR_LATER(ah))
1934 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
1935
1936 if (AR_SREV_9300_20_OR_LATER(ah))
1937 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
1938
1939 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
1940 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
1941
1942 if (AR_SREV_9285(ah))
1943 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
1944 ant_div_ctl1 =
1945 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
1946 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
1947 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
1948 }
1949 if (AR_SREV_9300_20_OR_LATER(ah)) {
1950 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
1951 pCap->hw_caps |= ATH9K_HW_CAP_APM;
1952 }
1953
1954
1955
1956 if (AR_SREV_9485_10(ah)) {
1957 pCap->pcie_lcr_extsync_en = true;
1958 pCap->pcie_lcr_offset = 0x80;
1959 }
1960
1961 tx_chainmask = pCap->tx_chainmask;
1962 rx_chainmask = pCap->rx_chainmask;
1963 while (tx_chainmask || rx_chainmask) {
1964 if (tx_chainmask & BIT(0))
1965 pCap->max_txchains++;
1966 if (rx_chainmask & BIT(0))
1967 pCap->max_rxchains++;
1968
1969 tx_chainmask >>= 1;
1970 rx_chainmask >>= 1;
1971 }
1972
1973 return 0;
1974 }
1975
1976 /****************************/
1977 /* GPIO / RFKILL / Antennae */
1978 /****************************/
1979
1980 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
1981 u32 gpio, u32 type)
1982 {
1983 int addr;
1984 u32 gpio_shift, tmp;
1985
1986 if (gpio > 11)
1987 addr = AR_GPIO_OUTPUT_MUX3;
1988 else if (gpio > 5)
1989 addr = AR_GPIO_OUTPUT_MUX2;
1990 else
1991 addr = AR_GPIO_OUTPUT_MUX1;
1992
1993 gpio_shift = (gpio % 6) * 5;
1994
1995 if (AR_SREV_9280_20_OR_LATER(ah)
1996 || (addr != AR_GPIO_OUTPUT_MUX1)) {
1997 REG_RMW(ah, addr, (type << gpio_shift),
1998 (0x1f << gpio_shift));
1999 } else {
2000 tmp = REG_READ(ah, addr);
2001 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2002 tmp &= ~(0x1f << gpio_shift);
2003 tmp |= (type << gpio_shift);
2004 REG_WRITE(ah, addr, tmp);
2005 }
2006 }
2007
2008 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2009 {
2010 u32 gpio_shift;
2011
2012 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2013
2014 if (AR_DEVID_7010(ah)) {
2015 gpio_shift = gpio;
2016 REG_RMW(ah, AR7010_GPIO_OE,
2017 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2018 (AR7010_GPIO_OE_MASK << gpio_shift));
2019 return;
2020 }
2021
2022 gpio_shift = gpio << 1;
2023 REG_RMW(ah,
2024 AR_GPIO_OE_OUT,
2025 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2026 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2027 }
2028 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2029
2030 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2031 {
2032 #define MS_REG_READ(x, y) \
2033 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2034
2035 if (gpio >= ah->caps.num_gpio_pins)
2036 return 0xffffffff;
2037
2038 if (AR_DEVID_7010(ah)) {
2039 u32 val;
2040 val = REG_READ(ah, AR7010_GPIO_IN);
2041 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2042 } else if (AR_SREV_9300_20_OR_LATER(ah))
2043 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2044 AR_GPIO_BIT(gpio)) != 0;
2045 else if (AR_SREV_9271(ah))
2046 return MS_REG_READ(AR9271, gpio) != 0;
2047 else if (AR_SREV_9287_11_OR_LATER(ah))
2048 return MS_REG_READ(AR9287, gpio) != 0;
2049 else if (AR_SREV_9285_12_OR_LATER(ah))
2050 return MS_REG_READ(AR9285, gpio) != 0;
2051 else if (AR_SREV_9280_20_OR_LATER(ah))
2052 return MS_REG_READ(AR928X, gpio) != 0;
2053 else
2054 return MS_REG_READ(AR, gpio) != 0;
2055 }
2056 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2057
2058 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2059 u32 ah_signal_type)
2060 {
2061 u32 gpio_shift;
2062
2063 if (AR_DEVID_7010(ah)) {
2064 gpio_shift = gpio;
2065 REG_RMW(ah, AR7010_GPIO_OE,
2066 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2067 (AR7010_GPIO_OE_MASK << gpio_shift));
2068 return;
2069 }
2070
2071 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2072 gpio_shift = 2 * gpio;
2073 REG_RMW(ah,
2074 AR_GPIO_OE_OUT,
2075 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2076 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2077 }
2078 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2079
2080 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2081 {
2082 if (AR_DEVID_7010(ah)) {
2083 val = val ? 0 : 1;
2084 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2085 AR_GPIO_BIT(gpio));
2086 return;
2087 }
2088
2089 if (AR_SREV_9271(ah))
2090 val = ~val;
2091
2092 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2093 AR_GPIO_BIT(gpio));
2094 }
2095 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2096
2097 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2098 {
2099 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2100 }
2101 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2102
2103 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2104 {
2105 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2106 }
2107 EXPORT_SYMBOL(ath9k_hw_setantenna);
2108
2109 /*********************/
2110 /* General Operation */
2111 /*********************/
2112
2113 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2114 {
2115 u32 bits = REG_READ(ah, AR_RX_FILTER);
2116 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2117
2118 if (phybits & AR_PHY_ERR_RADAR)
2119 bits |= ATH9K_RX_FILTER_PHYRADAR;
2120 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2121 bits |= ATH9K_RX_FILTER_PHYERR;
2122
2123 return bits;
2124 }
2125 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2126
2127 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2128 {
2129 u32 phybits;
2130
2131 ENABLE_REGWRITE_BUFFER(ah);
2132
2133 REG_WRITE(ah, AR_RX_FILTER, bits);
2134
2135 phybits = 0;
2136 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2137 phybits |= AR_PHY_ERR_RADAR;
2138 if (bits & ATH9K_RX_FILTER_PHYERR)
2139 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2140 REG_WRITE(ah, AR_PHY_ERR, phybits);
2141
2142 if (phybits)
2143 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2144 else
2145 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2146
2147 REGWRITE_BUFFER_FLUSH(ah);
2148 }
2149 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2150
2151 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2152 {
2153 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2154 return false;
2155
2156 ath9k_hw_init_pll(ah, NULL);
2157 return true;
2158 }
2159 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2160
2161 bool ath9k_hw_disable(struct ath_hw *ah)
2162 {
2163 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2164 return false;
2165
2166 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2167 return false;
2168
2169 ath9k_hw_init_pll(ah, NULL);
2170 return true;
2171 }
2172 EXPORT_SYMBOL(ath9k_hw_disable);
2173
2174 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2175 {
2176 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2177 struct ath9k_channel *chan = ah->curchan;
2178 struct ieee80211_channel *channel = chan->chan;
2179
2180 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
2181
2182 ah->eep_ops->set_txpower(ah, chan,
2183 ath9k_regd_get_ctl(regulatory, chan),
2184 channel->max_antenna_gain * 2,
2185 channel->max_power * 2,
2186 min((u32) MAX_RATE_POWER,
2187 (u32) regulatory->power_limit), test);
2188 }
2189 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2190
2191 void ath9k_hw_setopmode(struct ath_hw *ah)
2192 {
2193 ath9k_hw_set_operating_mode(ah, ah->opmode);
2194 }
2195 EXPORT_SYMBOL(ath9k_hw_setopmode);
2196
2197 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2198 {
2199 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2200 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2201 }
2202 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2203
2204 void ath9k_hw_write_associd(struct ath_hw *ah)
2205 {
2206 struct ath_common *common = ath9k_hw_common(ah);
2207
2208 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2209 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2210 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2211 }
2212 EXPORT_SYMBOL(ath9k_hw_write_associd);
2213
2214 #define ATH9K_MAX_TSF_READ 10
2215
2216 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2217 {
2218 u32 tsf_lower, tsf_upper1, tsf_upper2;
2219 int i;
2220
2221 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2222 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2223 tsf_lower = REG_READ(ah, AR_TSF_L32);
2224 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2225 if (tsf_upper2 == tsf_upper1)
2226 break;
2227 tsf_upper1 = tsf_upper2;
2228 }
2229
2230 WARN_ON( i == ATH9K_MAX_TSF_READ );
2231
2232 return (((u64)tsf_upper1 << 32) | tsf_lower);
2233 }
2234 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2235
2236 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2237 {
2238 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2239 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2240 }
2241 EXPORT_SYMBOL(ath9k_hw_settsf64);
2242
2243 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2244 {
2245 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2246 AH_TSF_WRITE_TIMEOUT))
2247 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
2248 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2249
2250 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2251 }
2252 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2253
2254 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2255 {
2256 if (setting)
2257 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2258 else
2259 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2260 }
2261 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2262
2263 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2264 {
2265 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2266 u32 macmode;
2267
2268 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2269 macmode = AR_2040_JOINED_RX_CLEAR;
2270 else
2271 macmode = 0;
2272
2273 REG_WRITE(ah, AR_2040_MODE, macmode);
2274 }
2275
2276 /* HW Generic timers configuration */
2277
2278 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2279 {
2280 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2281 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2282 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2283 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2284 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2285 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2286 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2287 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2288 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2289 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2290 AR_NDP2_TIMER_MODE, 0x0002},
2291 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2292 AR_NDP2_TIMER_MODE, 0x0004},
2293 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2294 AR_NDP2_TIMER_MODE, 0x0008},
2295 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2296 AR_NDP2_TIMER_MODE, 0x0010},
2297 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2298 AR_NDP2_TIMER_MODE, 0x0020},
2299 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2300 AR_NDP2_TIMER_MODE, 0x0040},
2301 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2302 AR_NDP2_TIMER_MODE, 0x0080}
2303 };
2304
2305 /* HW generic timer primitives */
2306
2307 /* compute and clear index of rightmost 1 */
2308 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2309 {
2310 u32 b;
2311
2312 b = *mask;
2313 b &= (0-b);
2314 *mask &= ~b;
2315 b *= debruijn32;
2316 b >>= 27;
2317
2318 return timer_table->gen_timer_index[b];
2319 }
2320
2321 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2322 {
2323 return REG_READ(ah, AR_TSF_L32);
2324 }
2325 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2326
2327 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2328 void (*trigger)(void *),
2329 void (*overflow)(void *),
2330 void *arg,
2331 u8 timer_index)
2332 {
2333 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2334 struct ath_gen_timer *timer;
2335
2336 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2337
2338 if (timer == NULL) {
2339 ath_err(ath9k_hw_common(ah),
2340 "Failed to allocate memory for hw timer[%d]\n",
2341 timer_index);
2342 return NULL;
2343 }
2344
2345 /* allocate a hardware generic timer slot */
2346 timer_table->timers[timer_index] = timer;
2347 timer->index = timer_index;
2348 timer->trigger = trigger;
2349 timer->overflow = overflow;
2350 timer->arg = arg;
2351
2352 return timer;
2353 }
2354 EXPORT_SYMBOL(ath_gen_timer_alloc);
2355
2356 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2357 struct ath_gen_timer *timer,
2358 u32 timer_next,
2359 u32 timer_period)
2360 {
2361 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2362 u32 tsf;
2363
2364 BUG_ON(!timer_period);
2365
2366 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2367
2368 tsf = ath9k_hw_gettsf32(ah);
2369
2370 ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2371 "current tsf %x period %x timer_next %x\n",
2372 tsf, timer_period, timer_next);
2373
2374 /*
2375 * Pull timer_next forward if the current TSF already passed it
2376 * because of software latency
2377 */
2378 if (timer_next < tsf)
2379 timer_next = tsf + timer_period;
2380
2381 /*
2382 * Program generic timer registers
2383 */
2384 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2385 timer_next);
2386 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2387 timer_period);
2388 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2389 gen_tmr_configuration[timer->index].mode_mask);
2390
2391 /* Enable both trigger and thresh interrupt masks */
2392 REG_SET_BIT(ah, AR_IMR_S5,
2393 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2394 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2395 }
2396 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2397
2398 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2399 {
2400 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2401
2402 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2403 (timer->index >= ATH_MAX_GEN_TIMER)) {
2404 return;
2405 }
2406
2407 /* Clear generic timer enable bits. */
2408 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2409 gen_tmr_configuration[timer->index].mode_mask);
2410
2411 /* Disable both trigger and thresh interrupt masks */
2412 REG_CLR_BIT(ah, AR_IMR_S5,
2413 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2414 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2415
2416 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2417 }
2418 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2419
2420 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2421 {
2422 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2423
2424 /* free the hardware generic timer slot */
2425 timer_table->timers[timer->index] = NULL;
2426 kfree(timer);
2427 }
2428 EXPORT_SYMBOL(ath_gen_timer_free);
2429
2430 /*
2431 * Generic Timer Interrupts handling
2432 */
2433 void ath_gen_timer_isr(struct ath_hw *ah)
2434 {
2435 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2436 struct ath_gen_timer *timer;
2437 struct ath_common *common = ath9k_hw_common(ah);
2438 u32 trigger_mask, thresh_mask, index;
2439
2440 /* get hardware generic timer interrupt status */
2441 trigger_mask = ah->intr_gen_timer_trigger;
2442 thresh_mask = ah->intr_gen_timer_thresh;
2443 trigger_mask &= timer_table->timer_mask.val;
2444 thresh_mask &= timer_table->timer_mask.val;
2445
2446 trigger_mask &= ~thresh_mask;
2447
2448 while (thresh_mask) {
2449 index = rightmost_index(timer_table, &thresh_mask);
2450 timer = timer_table->timers[index];
2451 BUG_ON(!timer);
2452 ath_dbg(common, ATH_DBG_HWTIMER,
2453 "TSF overflow for Gen timer %d\n", index);
2454 timer->overflow(timer->arg);
2455 }
2456
2457 while (trigger_mask) {
2458 index = rightmost_index(timer_table, &trigger_mask);
2459 timer = timer_table->timers[index];
2460 BUG_ON(!timer);
2461 ath_dbg(common, ATH_DBG_HWTIMER,
2462 "Gen timer[%d] trigger\n", index);
2463 timer->trigger(timer->arg);
2464 }
2465 }
2466 EXPORT_SYMBOL(ath_gen_timer_isr);
2467
2468 /********/
2469 /* HTC */
2470 /********/
2471
2472 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2473 {
2474 ah->htc_reset_init = true;
2475 }
2476 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2477
2478 static struct {
2479 u32 version;
2480 const char * name;
2481 } ath_mac_bb_names[] = {
2482 /* Devices with external radios */
2483 { AR_SREV_VERSION_5416_PCI, "5416" },
2484 { AR_SREV_VERSION_5416_PCIE, "5418" },
2485 { AR_SREV_VERSION_9100, "9100" },
2486 { AR_SREV_VERSION_9160, "9160" },
2487 /* Single-chip solutions */
2488 { AR_SREV_VERSION_9280, "9280" },
2489 { AR_SREV_VERSION_9285, "9285" },
2490 { AR_SREV_VERSION_9287, "9287" },
2491 { AR_SREV_VERSION_9271, "9271" },
2492 { AR_SREV_VERSION_9300, "9300" },
2493 { AR_SREV_VERSION_9485, "9485" },
2494 };
2495
2496 /* For devices with external radios */
2497 static struct {
2498 u16 version;
2499 const char * name;
2500 } ath_rf_names[] = {
2501 { 0, "5133" },
2502 { AR_RAD5133_SREV_MAJOR, "5133" },
2503 { AR_RAD5122_SREV_MAJOR, "5122" },
2504 { AR_RAD2133_SREV_MAJOR, "2133" },
2505 { AR_RAD2122_SREV_MAJOR, "2122" }
2506 };
2507
2508 /*
2509 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2510 */
2511 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2512 {
2513 int i;
2514
2515 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2516 if (ath_mac_bb_names[i].version == mac_bb_version) {
2517 return ath_mac_bb_names[i].name;
2518 }
2519 }
2520
2521 return "????";
2522 }
2523
2524 /*
2525 * Return the RF name. "????" is returned if the RF is unknown.
2526 * Used for devices with external radios.
2527 */
2528 static const char *ath9k_hw_rf_name(u16 rf_version)
2529 {
2530 int i;
2531
2532 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2533 if (ath_rf_names[i].version == rf_version) {
2534 return ath_rf_names[i].name;
2535 }
2536 }
2537
2538 return "????";
2539 }
2540
2541 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2542 {
2543 int used;
2544
2545 /* chipsets >= AR9280 are single-chip */
2546 if (AR_SREV_9280_20_OR_LATER(ah)) {
2547 used = snprintf(hw_name, len,
2548 "Atheros AR%s Rev:%x",
2549 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2550 ah->hw_version.macRev);
2551 }
2552 else {
2553 used = snprintf(hw_name, len,
2554 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2555 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2556 ah->hw_version.macRev,
2557 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2558 AR_RADIO_SREV_MAJOR)),
2559 ah->hw_version.phyRev);
2560 }
2561
2562 hw_name[used] = '\0';
2563 }
2564 EXPORT_SYMBOL(ath9k_hw_name);
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