drivers/pci/host/pcie-iproc.c

   1 /*
   2  * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
   3  * Copyright (C) 2015 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation version 2.
   8  *
   9  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  10  * kind, whether express or implied; without even the implied warranty
  11  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/pci.h>
  17 #include <linux/msi.h>
  18 #include <linux/clk.h>
  19 #include <linux/module.h>
  20 #include <linux/mbus.h>
  21 #include <linux/slab.h>
  22 #include <linux/delay.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/of_address.h>
  26 #include <linux/of_pci.h>
  27 #include <linux/of_irq.h>
  28 #include <linux/of_platform.h>
  29 #include <linux/phy/phy.h>
  30
  31 #include "pcie-iproc.h"
  32
  33 #define EP_PERST_SOURCE_SELECT_SHIFT 2
  34 #define EP_PERST_SOURCE_SELECT       BIT(EP_PERST_SOURCE_SELECT_SHIFT)
  35 #define EP_MODE_SURVIVE_PERST_SHIFT  1
  36 #define EP_MODE_SURVIVE_PERST        BIT(EP_MODE_SURVIVE_PERST_SHIFT)
  37 #define RC_PCIE_RST_OUTPUT_SHIFT     0
  38 #define RC_PCIE_RST_OUTPUT           BIT(RC_PCIE_RST_OUTPUT_SHIFT)
  39 #define PAXC_RESET_MASK              0x7f
  40
  41 #define CFG_IND_ADDR_MASK            0x00001ffc
  42
  43 #define CFG_ADDR_BUS_NUM_SHIFT       20
  44 #define CFG_ADDR_BUS_NUM_MASK        0x0ff00000
  45 #define CFG_ADDR_DEV_NUM_SHIFT       15
  46 #define CFG_ADDR_DEV_NUM_MASK        0x000f8000
  47 #define CFG_ADDR_FUNC_NUM_SHIFT      12
  48 #define CFG_ADDR_FUNC_NUM_MASK       0x00007000
  49 #define CFG_ADDR_REG_NUM_SHIFT       2
  50 #define CFG_ADDR_REG_NUM_MASK        0x00000ffc
  51 #define CFG_ADDR_CFG_TYPE_SHIFT      0
  52 #define CFG_ADDR_CFG_TYPE_MASK       0x00000003
  53
  54 #define SYS_RC_INTX_MASK             0xf
  55
  56 #define PCIE_PHYLINKUP_SHIFT         3
  57 #define PCIE_PHYLINKUP               BIT(PCIE_PHYLINKUP_SHIFT)
  58 #define PCIE_DL_ACTIVE_SHIFT         2
  59 #define PCIE_DL_ACTIVE               BIT(PCIE_DL_ACTIVE_SHIFT)
  60
  61 #define OARR_VALID_SHIFT             0
  62 #define OARR_VALID                   BIT(OARR_VALID_SHIFT)
  63 #define OARR_SIZE_CFG_SHIFT          1
  64 #define OARR_SIZE_CFG                BIT(OARR_SIZE_CFG_SHIFT)
  65
  66 #define MAX_NUM_OB_WINDOWS           2
  67 #define MAX_NUM_PAXC_PF              4
  68
  69 #define IPROC_PCIE_REG_INVALID 0xffff
  70
  71 enum iproc_pcie_reg {
  72         IPROC_PCIE_CLK_CTRL = 0,
  73         IPROC_PCIE_CFG_IND_ADDR,
  74         IPROC_PCIE_CFG_IND_DATA,
  75         IPROC_PCIE_CFG_ADDR,
  76         IPROC_PCIE_CFG_DATA,
  77         IPROC_PCIE_INTX_EN,
  78         IPROC_PCIE_OARR_LO,
  79         IPROC_PCIE_OARR_HI,
  80         IPROC_PCIE_OMAP_LO,
  81         IPROC_PCIE_OMAP_HI,
  82         IPROC_PCIE_LINK_STATUS,
  83 };
  84
  85 /* iProc PCIe PAXB registers */
  86 static const u16 iproc_pcie_reg_paxb[] = {
  87         [IPROC_PCIE_CLK_CTRL]     = 0x000,
  88         [IPROC_PCIE_CFG_IND_ADDR] = 0x120,
  89         [IPROC_PCIE_CFG_IND_DATA] = 0x124,
  90         [IPROC_PCIE_CFG_ADDR]     = 0x1f8,
  91         [IPROC_PCIE_CFG_DATA]     = 0x1fc,
  92         [IPROC_PCIE_INTX_EN]      = 0x330,
  93         [IPROC_PCIE_OARR_LO]      = 0xd20,
  94         [IPROC_PCIE_OARR_HI]      = 0xd24,
  95         [IPROC_PCIE_OMAP_LO]      = 0xd40,
  96         [IPROC_PCIE_OMAP_HI]      = 0xd44,
  97         [IPROC_PCIE_LINK_STATUS]  = 0xf0c,
  98 };
  99
 100 /* iProc PCIe PAXC v1 registers */
 101 static const u16 iproc_pcie_reg_paxc[] = {
 102         [IPROC_PCIE_CLK_CTRL]     = 0x000,
 103         [IPROC_PCIE_CFG_IND_ADDR] = 0x1f0,
 104         [IPROC_PCIE_CFG_IND_DATA] = 0x1f4,
 105         [IPROC_PCIE_CFG_ADDR]     = 0x1f8,
 106         [IPROC_PCIE_CFG_DATA]     = 0x1fc,
 107         [IPROC_PCIE_INTX_EN]      = IPROC_PCIE_REG_INVALID,
 108         [IPROC_PCIE_OARR_LO]      = IPROC_PCIE_REG_INVALID,
 109         [IPROC_PCIE_OARR_HI]      = IPROC_PCIE_REG_INVALID,
 110         [IPROC_PCIE_OMAP_LO]      = IPROC_PCIE_REG_INVALID,
 111         [IPROC_PCIE_OMAP_HI]      = IPROC_PCIE_REG_INVALID,
 112         [IPROC_PCIE_LINK_STATUS]  = IPROC_PCIE_REG_INVALID,
 113 };
 114
 115 static inline struct iproc_pcie *iproc_data(struct pci_bus *bus)
 116 {
 117         struct iproc_pcie *pcie;
 118 #ifdef CONFIG_ARM
 119         struct pci_sys_data *sys = bus->sysdata;
 120
 121         pcie = sys->private_data;
 122 #else
 123         pcie = bus->sysdata;
 124 #endif
 125         return pcie;
 126 }
 127
 128 static inline bool iproc_pcie_reg_is_invalid(u16 reg_offset)
 129 {
 130         return !!(reg_offset == IPROC_PCIE_REG_INVALID);
 131 }
 132
 133 static inline u16 iproc_pcie_reg_offset(struct iproc_pcie *pcie,
 134                                         enum iproc_pcie_reg reg)
 135 {
 136         return pcie->reg_offsets[reg];
 137 }
 138
 139 static inline u32 iproc_pcie_read_reg(struct iproc_pcie *pcie,
 140                                       enum iproc_pcie_reg reg)
 141 {
 142         u16 offset = iproc_pcie_reg_offset(pcie, reg);
 143
 144         if (iproc_pcie_reg_is_invalid(offset))
 145                 return 0;
 146
 147         return readl(pcie->base + offset);
 148 }
 149
 150 static inline void iproc_pcie_write_reg(struct iproc_pcie *pcie,
 151                                         enum iproc_pcie_reg reg, u32 val)
 152 {
 153         u16 offset = iproc_pcie_reg_offset(pcie, reg);
 154
 155         if (iproc_pcie_reg_is_invalid(offset))
 156                 return;
 157
 158         writel(val, pcie->base + offset);
 159 }
 160
 161 static inline void iproc_pcie_ob_write(struct iproc_pcie *pcie,
 162                                        enum iproc_pcie_reg reg,
 163                                        unsigned window, u32 val)
 164 {
 165         u16 offset = iproc_pcie_reg_offset(pcie, reg);
 166
 167         if (iproc_pcie_reg_is_invalid(offset))
 168                 return;
 169
 170         writel(val, pcie->base + offset + (window * 8));
 171 }
 172
 173 static inline bool iproc_pcie_device_is_valid(struct iproc_pcie *pcie,
 174                                               unsigned int slot,
 175                                               unsigned int fn)
 176 {
 177         if (slot > 0)
 178                 return false;
 179
 180         /* PAXC can only support limited number of functions */
 181         if (pcie->type == IPROC_PCIE_PAXC && fn >= MAX_NUM_PAXC_PF)
 182                 return false;
 183
 184         return true;
 185 }
 186
 187 /**
 188  * Note access to the configuration registers are protected at the higher layer
 189  * by 'pci_lock' in drivers/pci/access.c
 190  */
 191 static void __iomem *iproc_pcie_map_cfg_bus(struct pci_bus *bus,
 192                                             unsigned int devfn,
 193                                             int where)
 194 {
 195         struct iproc_pcie *pcie = iproc_data(bus);
 196         unsigned slot = PCI_SLOT(devfn);
 197         unsigned fn = PCI_FUNC(devfn);
 198         unsigned busno = bus->number;
 199         u32 val;
 200         u16 offset;
 201
 202         if (!iproc_pcie_device_is_valid(pcie, slot, fn))
 203                 return NULL;
 204
 205         /* root complex access */
 206         if (busno == 0) {
 207                 iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_IND_ADDR,
 208                                      where & CFG_IND_ADDR_MASK);
 209                 offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_IND_DATA);
 210                 if (iproc_pcie_reg_is_invalid(offset))
 211                         return NULL;
 212                 else
 213                         return (pcie->base + offset);
 214         }
 215
 216         /* EP device access */
 217         val = (busno << CFG_ADDR_BUS_NUM_SHIFT) |
 218                 (slot << CFG_ADDR_DEV_NUM_SHIFT) |
 219                 (fn << CFG_ADDR_FUNC_NUM_SHIFT) |
 220                 (where & CFG_ADDR_REG_NUM_MASK) |
 221                 (1 & CFG_ADDR_CFG_TYPE_MASK);
 222         iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_ADDR, val);
 223         offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_DATA);
 224         if (iproc_pcie_reg_is_invalid(offset))
 225                 return NULL;
 226         else
 227                 return (pcie->base + offset);
 228 }
 229
 230 static struct pci_ops iproc_pcie_ops = {
 231         .map_bus = iproc_pcie_map_cfg_bus,
 232         .read = pci_generic_config_read32,
 233         .write = pci_generic_config_write32,
 234 };
 235
 236 static void iproc_pcie_reset(struct iproc_pcie *pcie)
 237 {
 238         u32 val;
 239
 240         if (pcie->type == IPROC_PCIE_PAXC) {
 241                 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL);
 242                 val &= ~PAXC_RESET_MASK;
 243                 iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
 244                 udelay(100);
 245                 val |= PAXC_RESET_MASK;
 246                 iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
 247                 udelay(100);
 248                 return;
 249         }
 250
 251         /*
 252          * Select perst_b signal as reset source. Put the device into reset,
 253          * and then bring it out of reset
 254          */
 255         val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL);
 256         val &= ~EP_PERST_SOURCE_SELECT & ~EP_MODE_SURVIVE_PERST &
 257                 ~RC_PCIE_RST_OUTPUT;
 258         iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
 259         udelay(250);
 260
 261         val |= RC_PCIE_RST_OUTPUT;
 262         iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
 263         msleep(100);
 264 }
 265
 266 static int iproc_pcie_check_link(struct iproc_pcie *pcie, struct pci_bus *bus)
 267 {
 268         u8 hdr_type;
 269         u32 link_ctrl, class, val;
 270         u16 pos, link_status;
 271         bool link_is_active = false;
 272
 273         /*
 274          * PAXC connects to emulated endpoint devices directly and does not
 275          * have a Serdes.  Therefore skip the link detection logic here.
 276          */
 277         if (pcie->type == IPROC_PCIE_PAXC)
 278                 return 0;
 279
 280         val = iproc_pcie_read_reg(pcie, IPROC_PCIE_LINK_STATUS);
 281         if (!(val & PCIE_PHYLINKUP) || !(val & PCIE_DL_ACTIVE)) {
 282                 dev_err(pcie->dev, "PHY or data link is INACTIVE!\n");
 283                 return -ENODEV;
 284         }
 285
 286         /* make sure we are not in EP mode */
 287         pci_bus_read_config_byte(bus, 0, PCI_HEADER_TYPE, &hdr_type);
 288         if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) {
 289                 dev_err(pcie->dev, "in EP mode, hdr=%#02x\n", hdr_type);
 290                 return -EFAULT;
 291         }
 292
 293         /* force class to PCI_CLASS_BRIDGE_PCI (0x0604) */
 294 #define PCI_BRIDGE_CTRL_REG_OFFSET 0x43c
 295 #define PCI_CLASS_BRIDGE_MASK      0xffff00
 296 #define PCI_CLASS_BRIDGE_SHIFT     8
 297         pci_bus_read_config_dword(bus, 0, PCI_BRIDGE_CTRL_REG_OFFSET, &class);
 298         class &= ~PCI_CLASS_BRIDGE_MASK;
 299         class |= (PCI_CLASS_BRIDGE_PCI << PCI_CLASS_BRIDGE_SHIFT);
 300         pci_bus_write_config_dword(bus, 0, PCI_BRIDGE_CTRL_REG_OFFSET, class);
 301
 302         /* check link status to see if link is active */
 303         pos = pci_bus_find_capability(bus, 0, PCI_CAP_ID_EXP);
 304         pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA, &link_status);
 305         if (link_status & PCI_EXP_LNKSTA_NLW)
 306                 link_is_active = true;
 307
 308         if (!link_is_active) {
 309                 /* try GEN 1 link speed */
 310 #define PCI_LINK_STATUS_CTRL_2_OFFSET 0x0dc
 311 #define PCI_TARGET_LINK_SPEED_MASK    0xf
 312 #define PCI_TARGET_LINK_SPEED_GEN2    0x2
 313 #define PCI_TARGET_LINK_SPEED_GEN1    0x1
 314                 pci_bus_read_config_dword(bus, 0,
 315                                           PCI_LINK_STATUS_CTRL_2_OFFSET,
 316                                           &link_ctrl);
 317                 if ((link_ctrl & PCI_TARGET_LINK_SPEED_MASK) ==
 318                     PCI_TARGET_LINK_SPEED_GEN2) {
 319                         link_ctrl &= ~PCI_TARGET_LINK_SPEED_MASK;
 320                         link_ctrl |= PCI_TARGET_LINK_SPEED_GEN1;
 321                         pci_bus_write_config_dword(bus, 0,
 322                                            PCI_LINK_STATUS_CTRL_2_OFFSET,
 323                                            link_ctrl);
 324                         msleep(100);
 325
 326                         pos = pci_bus_find_capability(bus, 0, PCI_CAP_ID_EXP);
 327                         pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA,
 328                                                  &link_status);
 329                         if (link_status & PCI_EXP_LNKSTA_NLW)
 330                                 link_is_active = true;
 331                 }
 332         }
 333
 334         dev_info(pcie->dev, "link: %s\n", link_is_active ? "UP" : "DOWN");
 335
 336         return link_is_active ? 0 : -ENODEV;
 337 }
 338
 339 static void iproc_pcie_enable(struct iproc_pcie *pcie)
 340 {
 341         iproc_pcie_write_reg(pcie, IPROC_PCIE_INTX_EN, SYS_RC_INTX_MASK);
 342 }
 343
 344 /**
 345  * Some iProc SoCs require the SW to configure the outbound address mapping
 346  *
 347  * Outbound address translation:
 348  *
 349  * iproc_pcie_address = axi_address - axi_offset
 350  * OARR = iproc_pcie_address
 351  * OMAP = pci_addr
 352  *
 353  * axi_addr -> iproc_pcie_address -> OARR -> OMAP -> pci_address
 354  */
 355 static int iproc_pcie_setup_ob(struct iproc_pcie *pcie, u64 axi_addr,
 356                                u64 pci_addr, resource_size_t size)
 357 {
 358         struct iproc_pcie_ob *ob = &pcie->ob;
 359         unsigned i;
 360         u64 max_size = (u64)ob->window_size * MAX_NUM_OB_WINDOWS;
 361         u64 remainder;
 362
 363         if (size > max_size) {
 364                 dev_err(pcie->dev,
 365                         "res size %pap exceeds max supported size 0x%llx\n",
 366                         &size, max_size);
 367                 return -EINVAL;
 368         }
 369
 370         div64_u64_rem(size, ob->window_size, &remainder);
 371         if (remainder) {
 372                 dev_err(pcie->dev,
 373                         "res size %pap needs to be multiple of window size %pap\n",
 374                         &size, &ob->window_size);
 375                 return -EINVAL;
 376         }
 377
 378         if (axi_addr < ob->axi_offset) {
 379                 dev_err(pcie->dev,
 380                         "axi address %pap less than offset %pap\n",
 381                         &axi_addr, &ob->axi_offset);
 382                 return -EINVAL;
 383         }
 384
 385         /*
 386          * Translate the AXI address to the internal address used by the iProc
 387          * PCIe core before programming the OARR
 388          */
 389         axi_addr -= ob->axi_offset;
 390
 391         for (i = 0; i < MAX_NUM_OB_WINDOWS; i++) {
 392                 iproc_pcie_ob_write(pcie, IPROC_PCIE_OARR_LO, i,
 393                                     lower_32_bits(axi_addr) | OARR_VALID |
 394                                     (ob->set_oarr_size ? 1 : 0));
 395                 iproc_pcie_ob_write(pcie, IPROC_PCIE_OARR_HI, i,
 396                                     upper_32_bits(axi_addr));
 397                 iproc_pcie_ob_write(pcie, IPROC_PCIE_OMAP_LO, i,
 398                                     lower_32_bits(pci_addr));
 399                 iproc_pcie_ob_write(pcie, IPROC_PCIE_OMAP_HI, i,
 400                                     upper_32_bits(pci_addr));
 401
 402                 size -= ob->window_size;
 403                 if (size == 0)
 404                         break;
 405
 406                 axi_addr += ob->window_size;
 407                 pci_addr += ob->window_size;
 408         }
 409
 410         return 0;
 411 }
 412
 413 static int iproc_pcie_map_ranges(struct iproc_pcie *pcie,
 414                                  struct list_head *resources)
 415 {
 416         struct resource_entry *window;
 417         int ret;
 418
 419         resource_list_for_each_entry(window, resources) {
 420                 struct resource *res = window->res;
 421                 u64 res_type = resource_type(res);
 422
 423                 switch (res_type) {
 424                 case IORESOURCE_IO:
 425                 case IORESOURCE_BUS:
 426                         break;
 427                 case IORESOURCE_MEM:
 428                         ret = iproc_pcie_setup_ob(pcie, res->start,
 429                                                   res->start - window->offset,
 430                                                   resource_size(res));
 431                         if (ret)
 432                                 return ret;
 433                         break;
 434                 default:
 435                         dev_err(pcie->dev, "invalid resource %pR\n", res);
 436                         return -EINVAL;
 437                 }
 438         }
 439
 440         return 0;
 441 }
 442
 443 static int iproc_pcie_msi_enable(struct iproc_pcie *pcie)
 444 {
 445         struct device_node *msi_node;
 446
 447         msi_node = of_parse_phandle(pcie->dev->of_node, "msi-parent", 0);
 448         if (!msi_node)
 449                 return -ENODEV;
 450
 451         /*
 452          * If another MSI controller is being used, the call below should fail
 453          * but that is okay
 454          */
 455         return iproc_msi_init(pcie, msi_node);
 456 }
 457
 458 static void iproc_pcie_msi_disable(struct iproc_pcie *pcie)
 459 {
 460         iproc_msi_exit(pcie);
 461 }
 462
 463 int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res)
 464 {
 465         int ret;
 466         void *sysdata;
 467         struct pci_bus *bus;
 468
 469         if (!pcie || !pcie->dev || !pcie->base)
 470                 return -EINVAL;
 471
 472         ret = phy_init(pcie->phy);
 473         if (ret) {
 474                 dev_err(pcie->dev, "unable to initialize PCIe PHY\n");
 475                 return ret;
 476         }
 477
 478         ret = phy_power_on(pcie->phy);
 479         if (ret) {
 480                 dev_err(pcie->dev, "unable to power on PCIe PHY\n");
 481                 goto err_exit_phy;
 482         }
 483
 484         switch (pcie->type) {
 485         case IPROC_PCIE_PAXB:
 486                 pcie->reg_offsets = iproc_pcie_reg_paxb;
 487                 break;
 488         case IPROC_PCIE_PAXC:
 489                 pcie->reg_offsets = iproc_pcie_reg_paxc;
 490                 break;
 491         default:
 492                 dev_err(pcie->dev, "incompatible iProc PCIe interface\n");
 493                 ret = -EINVAL;
 494                 goto err_power_off_phy;
 495         }
 496
 497         iproc_pcie_reset(pcie);
 498
 499         if (pcie->need_ob_cfg) {
 500                 ret = iproc_pcie_map_ranges(pcie, res);
 501                 if (ret) {
 502                         dev_err(pcie->dev, "map failed\n");
 503                         goto err_power_off_phy;
 504                 }
 505         }
 506
 507 #ifdef CONFIG_ARM
 508         pcie->sysdata.private_data = pcie;
 509         sysdata = &pcie->sysdata;
 510 #else
 511         sysdata = pcie;
 512 #endif
 513
 514         bus = pci_create_root_bus(pcie->dev, 0, &iproc_pcie_ops, sysdata, res);
 515         if (!bus) {
 516                 dev_err(pcie->dev, "unable to create PCI root bus\n");
 517                 ret = -ENOMEM;
 518                 goto err_power_off_phy;
 519         }
 520         pcie->root_bus = bus;
 521
 522         ret = iproc_pcie_check_link(pcie, bus);
 523         if (ret) {
 524                 dev_err(pcie->dev, "no PCIe EP device detected\n");
 525                 goto err_rm_root_bus;
 526         }
 527
 528         iproc_pcie_enable(pcie);
 529
 530         if (IS_ENABLED(CONFIG_PCI_MSI))
 531                 if (iproc_pcie_msi_enable(pcie))
 532                         dev_info(pcie->dev, "not using iProc MSI\n");
 533
 534         pci_scan_child_bus(bus);
 535         pci_assign_unassigned_bus_resources(bus);
 536         pci_fixup_irqs(pci_common_swizzle, pcie->map_irq);
 537         pci_bus_add_devices(bus);
 538
 539         return 0;
 540
 541 err_rm_root_bus:
 542         pci_stop_root_bus(bus);
 543         pci_remove_root_bus(bus);
 544
 545 err_power_off_phy:
 546         phy_power_off(pcie->phy);
 547 err_exit_phy:
 548         phy_exit(pcie->phy);
 549         return ret;
 550 }
 551 EXPORT_SYMBOL(iproc_pcie_setup);
 552
 553 int iproc_pcie_remove(struct iproc_pcie *pcie)
 554 {
 555         pci_stop_root_bus(pcie->root_bus);
 556         pci_remove_root_bus(pcie->root_bus);
 557
 558         iproc_pcie_msi_disable(pcie);
 559
 560         phy_power_off(pcie->phy);
 561         phy_exit(pcie->phy);
 562
 563         return 0;
 564 }
 565 EXPORT_SYMBOL(iproc_pcie_remove);
 566
 567 MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
 568 MODULE_DESCRIPTION("Broadcom iPROC PCIe common driver");
 569 MODULE_LICENSE("GPL v2");