arch/arm/boot/dts/r8a7779.dtsi

   1 /*
   2  * Device Tree Source for Renesas r8a7779
   3  *
   4  * Copyright (C) 2013 Renesas Solutions Corp.
   5  * Copyright (C) 2013 Simon Horman
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 /include/ "skeleton.dtsi"
  13
  14 #include <dt-bindings/clock/r8a7779-clock.h>
  15 #include <dt-bindings/interrupt-controller/arm-gic.h>
  16 #include <dt-bindings/interrupt-controller/irq.h>
  17
  18 / {
  19         compatible = "renesas,r8a7779";
  20         interrupt-parent = <&gic>;
  21
  22         cpus {
  23                 #address-cells = <1>;
  24                 #size-cells = <0>;
  25
  26                 cpu@0 {
  27                         device_type = "cpu";
  28                         compatible = "arm,cortex-a9";
  29                         reg = <0>;
  30                         clock-frequency = <1000000000>;
  31                 };
  32                 cpu@1 {
  33                         device_type = "cpu";
  34                         compatible = "arm,cortex-a9";
  35                         reg = <1>;
  36                         clock-frequency = <1000000000>;
  37                 };
  38                 cpu@2 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a9";
  41                         reg = <2>;
  42                         clock-frequency = <1000000000>;
  43                 };
  44                 cpu@3 {
  45                         device_type = "cpu";
  46                         compatible = "arm,cortex-a9";
  47                         reg = <3>;
  48                         clock-frequency = <1000000000>;
  49                 };
  50         };
  51
  52         aliases {
  53                 spi0 = &hspi0;
  54                 spi1 = &hspi1;
  55                 spi2 = &hspi2;
  56         };
  57
  58         gic: interrupt-controller@f0001000 {
  59                 compatible = "arm,cortex-a9-gic";
  60                 #interrupt-cells = <3>;
  61                 interrupt-controller;
  62                 reg = <0xf0001000 0x1000>,
  63                       <0xf0000100 0x100>;
  64         };
  65
  66         timer@f0000600 {
  67                 compatible = "arm,cortex-a9-twd-timer";
  68                 reg = <0xf0000600 0x20>;
  69                 interrupts = <GIC_PPI 13
  70                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  71                 clocks = <&cpg_clocks R8A7779_CLK_ZS>;
  72         };
  73
  74         gpio0: gpio@ffc40000 {
  75                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
  76                 reg = <0xffc40000 0x2c>;
  77                 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
  78                 #gpio-cells = <2>;
  79                 gpio-controller;
  80                 gpio-ranges = <&pfc 0 0 32>;
  81                 #interrupt-cells = <2>;
  82                 interrupt-controller;
  83         };
  84
  85         gpio1: gpio@ffc41000 {
  86                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
  87                 reg = <0xffc41000 0x2c>;
  88                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
  89                 #gpio-cells = <2>;
  90                 gpio-controller;
  91                 gpio-ranges = <&pfc 0 32 32>;
  92                 #interrupt-cells = <2>;
  93                 interrupt-controller;
  94         };
  95
  96         gpio2: gpio@ffc42000 {
  97                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
  98                 reg = <0xffc42000 0x2c>;
  99                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 100                 #gpio-cells = <2>;
 101                 gpio-controller;
 102                 gpio-ranges = <&pfc 0 64 32>;
 103                 #interrupt-cells = <2>;
 104                 interrupt-controller;
 105         };
 106
 107         gpio3: gpio@ffc43000 {
 108                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
 109                 reg = <0xffc43000 0x2c>;
 110                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 111                 #gpio-cells = <2>;
 112                 gpio-controller;
 113                 gpio-ranges = <&pfc 0 96 32>;
 114                 #interrupt-cells = <2>;
 115                 interrupt-controller;
 116         };
 117
 118         gpio4: gpio@ffc44000 {
 119                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
 120                 reg = <0xffc44000 0x2c>;
 121                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 122                 #gpio-cells = <2>;
 123                 gpio-controller;
 124                 gpio-ranges = <&pfc 0 128 32>;
 125                 #interrupt-cells = <2>;
 126                 interrupt-controller;
 127         };
 128
 129         gpio5: gpio@ffc45000 {
 130                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
 131                 reg = <0xffc45000 0x2c>;
 132                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 133                 #gpio-cells = <2>;
 134                 gpio-controller;
 135                 gpio-ranges = <&pfc 0 160 32>;
 136                 #interrupt-cells = <2>;
 137                 interrupt-controller;
 138         };
 139
 140         gpio6: gpio@ffc46000 {
 141                 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
 142                 reg = <0xffc46000 0x2c>;
 143                 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 144                 #gpio-cells = <2>;
 145                 gpio-controller;
 146                 gpio-ranges = <&pfc 0 192 9>;
 147                 #interrupt-cells = <2>;
 148                 interrupt-controller;
 149         };
 150
 151         irqpin0: interrupt-controller@fe78001c {
 152                 compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
 153                 #interrupt-cells = <2>;
 154                 status = "disabled";
 155                 interrupt-controller;
 156                 reg = <0xfe78001c 4>,
 157                         <0xfe780010 4>,
 158                         <0xfe780024 4>,
 159                         <0xfe780044 4>,
 160                         <0xfe780064 4>,
 161                         <0xfe780000 4>;
 162                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
 163                               GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
 164                               GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
 165                               GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 166                 sense-bitfield-width = <2>;
 167         };
 168
 169         i2c0: i2c@ffc70000 {
 170                 #address-cells = <1>;
 171                 #size-cells = <0>;
 172                 compatible = "renesas,i2c-r8a7779";
 173                 reg = <0xffc70000 0x1000>;
 174                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 175                 clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
 176                 power-domains = <&cpg_clocks>;
 177                 status = "disabled";
 178         };
 179
 180         i2c1: i2c@ffc71000 {
 181                 #address-cells = <1>;
 182                 #size-cells = <0>;
 183                 compatible = "renesas,i2c-r8a7779";
 184                 reg = <0xffc71000 0x1000>;
 185                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 186                 clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
 187                 power-domains = <&cpg_clocks>;
 188                 status = "disabled";
 189         };
 190
 191         i2c2: i2c@ffc72000 {
 192                 #address-cells = <1>;
 193                 #size-cells = <0>;
 194                 compatible = "renesas,i2c-r8a7779";
 195                 reg = <0xffc72000 0x1000>;
 196                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 197                 clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
 198                 power-domains = <&cpg_clocks>;
 199                 status = "disabled";
 200         };
 201
 202         i2c3: i2c@ffc73000 {
 203                 #address-cells = <1>;
 204                 #size-cells = <0>;
 205                 compatible = "renesas,i2c-r8a7779";
 206                 reg = <0xffc73000 0x1000>;
 207                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 208                 clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
 209                 power-domains = <&cpg_clocks>;
 210                 status = "disabled";
 211         };
 212
 213         scif0: serial@ffe40000 {
 214                 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
 215                              "renesas,scif";
 216                 reg = <0xffe40000 0x100>;
 217                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 218                 clocks = <&mstp0_clks R8A7779_CLK_SCIF0>;
 219                 clock-names = "sci_ick";
 220                 power-domains = <&cpg_clocks>;
 221                 status = "disabled";
 222         };
 223
 224         scif1: serial@ffe41000 {
 225                 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
 226                              "renesas,scif";
 227                 reg = <0xffe41000 0x100>;
 228                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 229                 clocks = <&mstp0_clks R8A7779_CLK_SCIF1>;
 230                 clock-names = "sci_ick";
 231                 power-domains = <&cpg_clocks>;
 232                 status = "disabled";
 233         };
 234
 235         scif2: serial@ffe42000 {
 236                 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
 237                              "renesas,scif";
 238                 reg = <0xffe42000 0x100>;
 239                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 240                 clocks = <&mstp0_clks R8A7779_CLK_SCIF2>;
 241                 clock-names = "sci_ick";
 242                 power-domains = <&cpg_clocks>;
 243                 status = "disabled";
 244         };
 245
 246         scif3: serial@ffe43000 {
 247                 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
 248                              "renesas,scif";
 249                 reg = <0xffe43000 0x100>;
 250                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 251                 clocks = <&mstp0_clks R8A7779_CLK_SCIF3>;
 252                 clock-names = "sci_ick";
 253                 power-domains = <&cpg_clocks>;
 254                 status = "disabled";
 255         };
 256
 257         scif4: serial@ffe44000 {
 258                 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
 259                              "renesas,scif";
 260                 reg = <0xffe44000 0x100>;
 261                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 262                 clocks = <&mstp0_clks R8A7779_CLK_SCIF4>;
 263                 clock-names = "sci_ick";
 264                 power-domains = <&cpg_clocks>;
 265                 status = "disabled";
 266         };
 267
 268         scif5: serial@ffe45000 {
 269                 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
 270                              "renesas,scif";
 271                 reg = <0xffe45000 0x100>;
 272                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 273                 clocks = <&mstp0_clks R8A7779_CLK_SCIF5>;
 274                 clock-names = "sci_ick";
 275                 power-domains = <&cpg_clocks>;
 276                 status = "disabled";
 277         };
 278
 279         pfc: pfc@fffc0000 {
 280                 compatible = "renesas,pfc-r8a7779";
 281                 reg = <0xfffc0000 0x23c>;
 282         };
 283
 284         thermal@ffc48000 {
 285                 compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal";
 286                 reg = <0xffc48000 0x38>;
 287         };
 288
 289         tmu0: timer@ffd80000 {
 290                 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
 291                 reg = <0xffd80000 0x30>;
 292                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 293                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 294                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 295                 clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
 296                 clock-names = "fck";
 297                 power-domains = <&cpg_clocks>;
 298
 299                 #renesas,channels = <3>;
 300
 301                 status = "disabled";
 302         };
 303
 304         tmu1: timer@ffd81000 {
 305                 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
 306                 reg = <0xffd81000 0x30>;
 307                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
 308                              <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
 309                              <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 310                 clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
 311                 clock-names = "fck";
 312                 power-domains = <&cpg_clocks>;
 313
 314                 #renesas,channels = <3>;
 315
 316                 status = "disabled";
 317         };
 318
 319         tmu2: timer@ffd82000 {
 320                 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
 321                 reg = <0xffd82000 0x30>;
 322                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 323                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 324                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 325                 clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
 326                 clock-names = "fck";
 327                 power-domains = <&cpg_clocks>;
 328
 329                 #renesas,channels = <3>;
 330
 331                 status = "disabled";
 332         };
 333
 334         sata: sata@fc600000 {
 335                 compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
 336                 reg = <0xfc600000 0x2000>;
 337                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 338                 clocks = <&mstp1_clks R8A7779_CLK_SATA>;
 339                 power-domains = <&cpg_clocks>;
 340         };
 341
 342         sdhi0: sd@ffe4c000 {
 343                 compatible = "renesas,sdhi-r8a7779";
 344                 reg = <0xffe4c000 0x100>;
 345                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 346                 clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
 347                 power-domains = <&cpg_clocks>;
 348                 status = "disabled";
 349         };
 350
 351         sdhi1: sd@ffe4d000 {
 352                 compatible = "renesas,sdhi-r8a7779";
 353                 reg = <0xffe4d000 0x100>;
 354                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 355                 clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
 356                 power-domains = <&cpg_clocks>;
 357                 status = "disabled";
 358         };
 359
 360         sdhi2: sd@ffe4e000 {
 361                 compatible = "renesas,sdhi-r8a7779";
 362                 reg = <0xffe4e000 0x100>;
 363                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 364                 clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
 365                 power-domains = <&cpg_clocks>;
 366                 status = "disabled";
 367         };
 368
 369         sdhi3: sd@ffe4f000 {
 370                 compatible = "renesas,sdhi-r8a7779";
 371                 reg = <0xffe4f000 0x100>;
 372                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 373                 clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
 374                 power-domains = <&cpg_clocks>;
 375                 status = "disabled";
 376         };
 377
 378         hspi0: spi@fffc7000 {
 379                 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
 380                 reg = <0xfffc7000 0x18>;
 381                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 382                 #address-cells = <1>;
 383                 #size-cells = <0>;
 384                 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
 385                 power-domains = <&cpg_clocks>;
 386                 status = "disabled";
 387         };
 388
 389         hspi1: spi@fffc8000 {
 390                 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
 391                 reg = <0xfffc8000 0x18>;
 392                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 393                 #address-cells = <1>;
 394                 #size-cells = <0>;
 395                 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
 396                 power-domains = <&cpg_clocks>;
 397                 status = "disabled";
 398         };
 399
 400         hspi2: spi@fffc6000 {
 401                 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
 402                 reg = <0xfffc6000 0x18>;
 403                 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 404                 #address-cells = <1>;
 405                 #size-cells = <0>;
 406                 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
 407                 power-domains = <&cpg_clocks>;
 408                 status = "disabled";
 409         };
 410
 411         du: display@fff80000 {
 412                 compatible = "renesas,du-r8a7779";
 413                 reg = <0 0xfff80000 0 0x40000>;
 414                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 415                 clocks = <&mstp1_clks R8A7779_CLK_DU>;
 416                 power-domains = <&cpg_clocks>;
 417                 status = "disabled";
 418
 419                 ports {
 420                         #address-cells = <1>;
 421                         #size-cells = <0>;
 422
 423                         port@0 {
 424                                 reg = <0>;
 425                                 du_out_rgb0: endpoint {
 426                                 };
 427                         };
 428                         port@1 {
 429                                 reg = <1>;
 430                                 du_out_rgb1: endpoint {
 431                                 };
 432                         };
 433                 };
 434         };
 435
 436         clocks {
 437                 #address-cells = <1>;
 438                 #size-cells = <1>;
 439                 ranges;
 440
 441                 /* External root clock */
 442                 extal_clk: extal_clk {
 443                         compatible = "fixed-clock";
 444                         #clock-cells = <0>;
 445                         /* This value must be overriden by the board. */
 446                         clock-frequency = <0>;
 447                         clock-output-names = "extal";
 448                 };
 449
 450                 /* Special CPG clocks */
 451                 cpg_clocks: clocks@ffc80000 {
 452                         compatible = "renesas,r8a7779-cpg-clocks";
 453                         reg = <0xffc80000 0x30>;
 454                         clocks = <&extal_clk>;
 455                         #clock-cells = <1>;
 456                         clock-output-names = "plla", "z", "zs", "s",
 457                                              "s1", "p", "b", "out";
 458                         #power-domain-cells = <0>;
 459                 };
 460
 461                 /* Fixed factor clocks */
 462                 i_clk: i_clk {
 463                         compatible = "fixed-factor-clock";
 464                         clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
 465                         #clock-cells = <0>;
 466                         clock-div = <2>;
 467                         clock-mult = <1>;
 468                         clock-output-names = "i";
 469                 };
 470                 s3_clk: s3_clk {
 471                         compatible = "fixed-factor-clock";
 472                         clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
 473                         #clock-cells = <0>;
 474                         clock-div = <8>;
 475                         clock-mult = <1>;
 476                         clock-output-names = "s3";
 477                 };
 478                 s4_clk: s4_clk {
 479                         compatible = "fixed-factor-clock";
 480                         clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
 481                         #clock-cells = <0>;
 482                         clock-div = <16>;
 483                         clock-mult = <1>;
 484                         clock-output-names = "s4";
 485                 };
 486                 g_clk: g_clk {
 487                         compatible = "fixed-factor-clock";
 488                         clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
 489                         #clock-cells = <0>;
 490                         clock-div = <24>;
 491                         clock-mult = <1>;
 492                         clock-output-names = "g";
 493                 };
 494
 495                 /* Gate clocks */
 496                 mstp0_clks: clocks@ffc80030 {
 497                         compatible = "renesas,r8a7779-mstp-clocks",
 498                                      "renesas,cpg-mstp-clocks";
 499                         reg = <0xffc80030 4>;
 500                         clocks = <&cpg_clocks R8A7779_CLK_S>,
 501                                  <&cpg_clocks R8A7779_CLK_P>,
 502                                  <&cpg_clocks R8A7779_CLK_P>,
 503                                  <&cpg_clocks R8A7779_CLK_P>,
 504                                  <&cpg_clocks R8A7779_CLK_S>,
 505                                  <&cpg_clocks R8A7779_CLK_S>,
 506                                  <&cpg_clocks R8A7779_CLK_P>,
 507                                  <&cpg_clocks R8A7779_CLK_P>,
 508                                  <&cpg_clocks R8A7779_CLK_P>,
 509                                  <&cpg_clocks R8A7779_CLK_P>,
 510                                  <&cpg_clocks R8A7779_CLK_P>,
 511                                  <&cpg_clocks R8A7779_CLK_P>,
 512                                  <&cpg_clocks R8A7779_CLK_P>,
 513                                  <&cpg_clocks R8A7779_CLK_P>,
 514                                  <&cpg_clocks R8A7779_CLK_P>,
 515                                  <&cpg_clocks R8A7779_CLK_P>;
 516                         #clock-cells = <1>;
 517                         clock-indices = <
 518                                 R8A7779_CLK_HSPI R8A7779_CLK_TMU2
 519                                 R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
 520                                 R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
 521                                 R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
 522                                 R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
 523                                 R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
 524                                 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
 525                                 R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
 526                         >;
 527                         clock-output-names =
 528                                 "hspi", "tmu2", "tmu1", "tmu0", "hscif1",
 529                                 "hscif0", "scif5", "scif4", "scif3", "scif2",
 530                                 "scif1", "scif0", "i2c3", "i2c2", "i2c1",
 531                                 "i2c0";
 532                 };
 533                 mstp1_clks: clocks@ffc80034 {
 534                         compatible = "renesas,r8a7779-mstp-clocks",
 535                                      "renesas,cpg-mstp-clocks";
 536                         reg = <0xffc80034 4>, <0xffc80044 4>;
 537                         clocks = <&cpg_clocks R8A7779_CLK_P>,
 538                                  <&cpg_clocks R8A7779_CLK_P>,
 539                                  <&cpg_clocks R8A7779_CLK_S>,
 540                                  <&cpg_clocks R8A7779_CLK_S>,
 541                                  <&cpg_clocks R8A7779_CLK_S>,
 542                                  <&cpg_clocks R8A7779_CLK_S>,
 543                                  <&cpg_clocks R8A7779_CLK_P>,
 544                                  <&cpg_clocks R8A7779_CLK_P>,
 545                                  <&cpg_clocks R8A7779_CLK_P>,
 546                                  <&cpg_clocks R8A7779_CLK_S>;
 547                         #clock-cells = <1>;
 548                         clock-indices = <
 549                                 R8A7779_CLK_USB01 R8A7779_CLK_USB2
 550                                 R8A7779_CLK_DU R8A7779_CLK_VIN2
 551                                 R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
 552                                 R8A7779_CLK_ETHER R8A7779_CLK_SATA
 553                                 R8A7779_CLK_PCIE R8A7779_CLK_VIN3
 554                         >;
 555                         clock-output-names =
 556                                 "usb01", "usb2",
 557                                 "du", "vin2",
 558                                 "vin1", "vin0",
 559                                 "ether", "sata",
 560                                 "pcie", "vin3";
 561                 };
 562                 mstp3_clks: clocks@ffc8003c {
 563                         compatible = "renesas,r8a7779-mstp-clocks",
 564                                      "renesas,cpg-mstp-clocks";
 565                         reg = <0xffc8003c 4>;
 566                         clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
 567                                  <&s4_clk>, <&s4_clk>;
 568                         #clock-cells = <1>;
 569                         clock-indices = <
 570                                 R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
 571                                 R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
 572                                 R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
 573                         >;
 574                         clock-output-names =
 575                                 "sdhi3", "sdhi2", "sdhi1", "sdhi0",
 576                                 "mmc1", "mmc0";
 577                 };
 578         };
 579 };