?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
i40e: Add define for interrupt name string len
[linux-2.6/btrfs-unstable.git] / drivers / video / fbdev / mxsfb.c
blobf8ac4a452f26d5346613dc981e4eb25ed3992cef
1 /*
2 * Copyright (C) 2010 Juergen Beisert, Pengutronix
3 *
4 * This code is based on:
5 * Author: Vitaly Wool <vital@embeddedalley.com>
6 *
7 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
8 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20 #define DRIVER_NAME "mxsfb"
21
22 /**
23 * @file
24 * @brief LCDIF driver for i.MX23 and i.MX28
25 *
26 * The LCDIF support four modes of operation
27 * - MPU interface (to drive smart displays) -> not supported yet
28 * - VSYNC interface (like MPU interface plus Vsync) -> not supported yet
29 * - Dotclock interface (to drive LC displays with RGB data and sync signals)
30 * - DVI (to drive ITU-R BT656) -> not supported yet
31 *
32 * This driver depends on a correct setup of the pins used for this purpose
33 * (platform specific).
34 *
35 * For the developer: Don't forget to set the data bus width to the display
36 * in the imx_fb_videomode structure. You will else end up with ugly colours.
37 * If you fight against jitter you can vary the clock delay. This is a feature
38 * of the i.MX28 and you can vary it between 2 ns ... 8 ns in 2 ns steps. Give
39 * the required value in the imx_fb_videomode structure.
40 */
41
42 #include <linux/module.h>
43 #include <linux/kernel.h>
44 #include <linux/of_device.h>
45 #include <linux/platform_device.h>
46 #include <linux/clk.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/io.h>
49 #include <linux/fb.h>
50 #include <linux/regulator/consumer.h>
51 #include <video/of_display_timing.h>
52 #include <video/of_videomode.h>
53 #include <video/videomode.h>
54
55 #define REG_SET 4
56 #define REG_CLR 8
57
58 #define LCDC_CTRL 0x00
59 #define LCDC_CTRL1 0x10
60 #define LCDC_V4_CTRL2 0x20
61 #define LCDC_V3_TRANSFER_COUNT 0x20
62 #define LCDC_V4_TRANSFER_COUNT 0x30
63 #define LCDC_V4_CUR_BUF 0x40
64 #define LCDC_V4_NEXT_BUF 0x50
65 #define LCDC_V3_CUR_BUF 0x30
66 #define LCDC_V3_NEXT_BUF 0x40
67 #define LCDC_TIMING 0x60
68 #define LCDC_VDCTRL0 0x70
69 #define LCDC_VDCTRL1 0x80
70 #define LCDC_VDCTRL2 0x90
71 #define LCDC_VDCTRL3 0xa0
72 #define LCDC_VDCTRL4 0xb0
73 #define LCDC_DVICTRL0 0xc0
74 #define LCDC_DVICTRL1 0xd0
75 #define LCDC_DVICTRL2 0xe0
76 #define LCDC_DVICTRL3 0xf0
77 #define LCDC_DVICTRL4 0x100
78 #define LCDC_V4_DATA 0x180
79 #define LCDC_V3_DATA 0x1b0
80 #define LCDC_V4_DEBUG0 0x1d0
81 #define LCDC_V3_DEBUG0 0x1f0
82
83 #define CTRL_SFTRST (1 << 31)
84 #define CTRL_CLKGATE (1 << 30)
85 #define CTRL_BYPASS_COUNT (1 << 19)
86 #define CTRL_VSYNC_MODE (1 << 18)
87 #define CTRL_DOTCLK_MODE (1 << 17)
88 #define CTRL_DATA_SELECT (1 << 16)
89 #define CTRL_SET_BUS_WIDTH(x) (((x) & 0x3) << 10)
90 #define CTRL_GET_BUS_WIDTH(x) (((x) >> 10) & 0x3)
91 #define CTRL_SET_WORD_LENGTH(x) (((x) & 0x3) << 8)
92 #define CTRL_GET_WORD_LENGTH(x) (((x) >> 8) & 0x3)
93 #define CTRL_MASTER (1 << 5)
94 #define CTRL_DF16 (1 << 3)
95 #define CTRL_DF18 (1 << 2)
96 #define CTRL_DF24 (1 << 1)
97 #define CTRL_RUN (1 << 0)
98
99 #define CTRL1_FIFO_CLEAR (1 << 21)
100 #define CTRL1_SET_BYTE_PACKAGING(x) (((x) & 0xf) << 16)
101 #define CTRL1_GET_BYTE_PACKAGING(x) (((x) >> 16) & 0xf)
102
103 #define TRANSFER_COUNT_SET_VCOUNT(x) (((x) & 0xffff) << 16)
104 #define TRANSFER_COUNT_GET_VCOUNT(x) (((x) >> 16) & 0xffff)
105 #define TRANSFER_COUNT_SET_HCOUNT(x) ((x) & 0xffff)
106 #define TRANSFER_COUNT_GET_HCOUNT(x) ((x) & 0xffff)
107
108
109 #define VDCTRL0_ENABLE_PRESENT (1 << 28)
110 #define VDCTRL0_VSYNC_ACT_HIGH (1 << 27)
111 #define VDCTRL0_HSYNC_ACT_HIGH (1 << 26)
112 #define VDCTRL0_DOTCLK_ACT_FALLING (1 << 25)
113 #define VDCTRL0_ENABLE_ACT_HIGH (1 << 24)
114 #define VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21)
115 #define VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20)
116 #define VDCTRL0_HALF_LINE (1 << 19)
117 #define VDCTRL0_HALF_LINE_MODE (1 << 18)
118 #define VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff)
119 #define VDCTRL0_GET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff)
120
121 #define VDCTRL2_SET_HSYNC_PERIOD(x) ((x) & 0x3ffff)
122 #define VDCTRL2_GET_HSYNC_PERIOD(x) ((x) & 0x3ffff)
123
124 #define VDCTRL3_MUX_SYNC_SIGNALS (1 << 29)
125 #define VDCTRL3_VSYNC_ONLY (1 << 28)
126 #define SET_HOR_WAIT_CNT(x) (((x) & 0xfff) << 16)
127 #define GET_HOR_WAIT_CNT(x) (((x) >> 16) & 0xfff)
128 #define SET_VERT_WAIT_CNT(x) ((x) & 0xffff)
129 #define GET_VERT_WAIT_CNT(x) ((x) & 0xffff)
130
131 #define VDCTRL4_SET_DOTCLK_DLY(x) (((x) & 0x7) << 29) /* v4 only */
132 #define VDCTRL4_GET_DOTCLK_DLY(x) (((x) >> 29) & 0x7) /* v4 only */
133 #define VDCTRL4_SYNC_SIGNALS_ON (1 << 18)
134 #define SET_DOTCLK_H_VALID_DATA_CNT(x) ((x) & 0x3ffff)
135
136 #define DEBUG0_HSYNC (1 < 26)
137 #define DEBUG0_VSYNC (1 < 25)
138
139 #define MIN_XRES 120
140 #define MIN_YRES 120
141
142 #define RED 0
143 #define GREEN 1
144 #define BLUE 2
145 #define TRANSP 3
146
147 #define STMLCDIF_8BIT 1 /** pixel data bus to the display is of 8 bit width */
148 #define STMLCDIF_16BIT 0 /** pixel data bus to the display is of 16 bit width */
149 #define STMLCDIF_18BIT 2 /** pixel data bus to the display is of 18 bit width */
150 #define STMLCDIF_24BIT 3 /** pixel data bus to the display is of 24 bit width */
151
152 #define MXSFB_SYNC_DATA_ENABLE_HIGH_ACT (1 << 6)
153 #define MXSFB_SYNC_DOTCLK_FALLING_ACT (1 << 7) /* negtive edge sampling */
154
155 enum mxsfb_devtype {
156 MXSFB_V3,
157 MXSFB_V4,
158 };
159
160 /* CPU dependent register offsets */
161 struct mxsfb_devdata {
162 unsigned transfer_count;
163 unsigned cur_buf;
164 unsigned next_buf;
165 unsigned debug0;
166 unsigned hs_wdth_mask;
167 unsigned hs_wdth_shift;
168 unsigned ipversion;
169 };
170
171 struct mxsfb_info {
172 struct fb_info fb_info;
173 struct platform_device *pdev;
174 struct clk *clk;
175 struct clk *clk_axi;
176 struct clk *clk_disp_axi;
177 void __iomem *base; /* registers */
178 unsigned allocated_size;
179 int enabled;
180 unsigned ld_intf_width;
181 unsigned dotclk_delay;
182 const struct mxsfb_devdata *devdata;
183 u32 sync;
184 struct regulator *reg_lcd;
185 };
186
187 #define mxsfb_is_v3(host) (host->devdata->ipversion == 3)
188 #define mxsfb_is_v4(host) (host->devdata->ipversion == 4)
189
190 static const struct mxsfb_devdata mxsfb_devdata[] = {
191 [MXSFB_V3] = {
192 .transfer_count = LCDC_V3_TRANSFER_COUNT,
193 .cur_buf = LCDC_V3_CUR_BUF,
194 .next_buf = LCDC_V3_NEXT_BUF,
195 .debug0 = LCDC_V3_DEBUG0,
196 .hs_wdth_mask = 0xff,
197 .hs_wdth_shift = 24,
198 .ipversion = 3,
199 },
200 [MXSFB_V4] = {
201 .transfer_count = LCDC_V4_TRANSFER_COUNT,
202 .cur_buf = LCDC_V4_CUR_BUF,
203 .next_buf = LCDC_V4_NEXT_BUF,
204 .debug0 = LCDC_V4_DEBUG0,
205 .hs_wdth_mask = 0x3fff,
206 .hs_wdth_shift = 18,
207 .ipversion = 4,
208 },
209 };
210
211 #define to_imxfb_host(x) (container_of(x, struct mxsfb_info, fb_info))
212
213 /* mask and shift depends on architecture */
214 static inline u32 set_hsync_pulse_width(struct mxsfb_info *host, unsigned val)
215 {
216 return (val & host->devdata->hs_wdth_mask) <<
217 host->devdata->hs_wdth_shift;
218 }
219
220 static inline u32 get_hsync_pulse_width(struct mxsfb_info *host, unsigned val)
221 {
222 return (val >> host->devdata->hs_wdth_shift) &
223 host->devdata->hs_wdth_mask;
224 }
225
226 static const struct fb_bitfield def_rgb565[] = {
227 [RED] = {
228 .offset = 11,
229 .length = 5,
230 },
231 [GREEN] = {
232 .offset = 5,
233 .length = 6,
234 },
235 [BLUE] = {
236 .offset = 0,
237 .length = 5,
238 },
239 [TRANSP] = { /* no support for transparency */
240 .length = 0,
241 }
242 };
243
244 static const struct fb_bitfield def_rgb888[] = {
245 [RED] = {
246 .offset = 16,
247 .length = 8,
248 },
249 [GREEN] = {
250 .offset = 8,
251 .length = 8,
252 },
253 [BLUE] = {
254 .offset = 0,
255 .length = 8,
256 },
257 [TRANSP] = { /* no support for transparency */
258 .length = 0,
259 }
260 };
261
262 static inline unsigned chan_to_field(unsigned chan, struct fb_bitfield *bf)
263 {
264 chan &= 0xffff;
265 chan >>= 16 - bf->length;
266 return chan << bf->offset;
267 }
268
269 static int mxsfb_check_var(struct fb_var_screeninfo *var,
270 struct fb_info *fb_info)
271 {
272 struct mxsfb_info *host = to_imxfb_host(fb_info);
273 const struct fb_bitfield *rgb = NULL;
274
275 if (var->xres < MIN_XRES)
276 var->xres = MIN_XRES;
277 if (var->yres < MIN_YRES)
278 var->yres = MIN_YRES;
279
280 var->xres_virtual = var->xres;
281
282 var->yres_virtual = var->yres;
283
284 switch (var->bits_per_pixel) {
285 case 16:
286 /* always expect RGB 565 */
287 rgb = def_rgb565;
288 break;
289 case 32:
290 switch (host->ld_intf_width) {
291 case STMLCDIF_8BIT:
292 pr_debug("Unsupported LCD bus width mapping\n");
293 break;
294 case STMLCDIF_16BIT:
295 case STMLCDIF_18BIT:
296 case STMLCDIF_24BIT:
297 /* real 24 bit */
298 rgb = def_rgb888;
299 break;
300 }
301 break;
302 default:
303 pr_err("Unsupported colour depth: %u\n", var->bits_per_pixel);
304 return -EINVAL;
305 }
306
307 /*
308 * Copy the RGB parameters for this display
309 * from the machine specific parameters.
310 */
311 var->red = rgb[RED];
312 var->green = rgb[GREEN];
313 var->blue = rgb[BLUE];
314 var->transp = rgb[TRANSP];
315
316 return 0;
317 }
318
319 static void mxsfb_enable_controller(struct fb_info *fb_info)
320 {
321 struct mxsfb_info *host = to_imxfb_host(fb_info);
322 u32 reg;
323 int ret;
324
325 dev_dbg(&host->pdev->dev, "%s\n", __func__);
326
327 if (host->reg_lcd) {
328 ret = regulator_enable(host->reg_lcd);
329 if (ret) {
330 dev_err(&host->pdev->dev,
331 "lcd regulator enable failed: %d\n", ret);
332 return;
333 }
334 }
335
336 if (host->clk_axi)
337 clk_prepare_enable(host->clk_axi);
338
339 if (host->clk_disp_axi)
340 clk_prepare_enable(host->clk_disp_axi);
341 clk_prepare_enable(host->clk);
342 clk_set_rate(host->clk, PICOS2KHZ(fb_info->var.pixclock) * 1000U);
343
344 /* if it was disabled, re-enable the mode again */
345 writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_SET);
346
347 /* enable the SYNC signals first, then the DMA engine */
348 reg = readl(host->base + LCDC_VDCTRL4);
349 reg |= VDCTRL4_SYNC_SIGNALS_ON;
350 writel(reg, host->base + LCDC_VDCTRL4);
351
352 writel(CTRL_RUN, host->base + LCDC_CTRL + REG_SET);
353
354 host->enabled = 1;
355 }
356
357 static void mxsfb_disable_controller(struct fb_info *fb_info)
358 {
359 struct mxsfb_info *host = to_imxfb_host(fb_info);
360 unsigned loop;
361 u32 reg;
362 int ret;
363
364 dev_dbg(&host->pdev->dev, "%s\n", __func__);
365
366 /*
367 * Even if we disable the controller here, it will still continue
368 * until its FIFOs are running out of data
369 */
370 writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_CLR);
371
372 loop = 1000;
373 while (loop) {
374 reg = readl(host->base + LCDC_CTRL);
375 if (!(reg & CTRL_RUN))
376 break;
377 loop--;
378 }
379
380 reg = readl(host->base + LCDC_VDCTRL4);
381 writel(reg & ~VDCTRL4_SYNC_SIGNALS_ON, host->base + LCDC_VDCTRL4);
382
383 clk_disable_unprepare(host->clk);
384 if (host->clk_disp_axi)
385 clk_disable_unprepare(host->clk_disp_axi);
386 if (host->clk_axi)
387 clk_disable_unprepare(host->clk_axi);
388
389 host->enabled = 0;
390
391 if (host->reg_lcd) {
392 ret = regulator_disable(host->reg_lcd);
393 if (ret)
394 dev_err(&host->pdev->dev,
395 "lcd regulator disable failed: %d\n", ret);
396 }
397 }
398
399 static int mxsfb_set_par(struct fb_info *fb_info)
400 {
401 struct mxsfb_info *host = to_imxfb_host(fb_info);
402 u32 ctrl, vdctrl0, vdctrl4;
403 int line_size, fb_size;
404 int reenable = 0;
405
406 line_size = fb_info->var.xres * (fb_info->var.bits_per_pixel >> 3);
407 fb_size = fb_info->var.yres_virtual * line_size;
408
409 if (fb_size > fb_info->fix.smem_len)
410 return -ENOMEM;
411
412 fb_info->fix.line_length = line_size;
413
414 /*
415 * It seems, you can't re-program the controller if it is still running.
416 * This may lead into shifted pictures (FIFO issue?).
417 * So, first stop the controller and drain its FIFOs
418 */
419 if (host->enabled) {
420 reenable = 1;
421 mxsfb_disable_controller(fb_info);
422 }
423
424 /* clear the FIFOs */
425 writel(CTRL1_FIFO_CLEAR, host->base + LCDC_CTRL1 + REG_SET);
426
427 ctrl = CTRL_BYPASS_COUNT | CTRL_MASTER |
428 CTRL_SET_BUS_WIDTH(host->ld_intf_width);
429
430 switch (fb_info->var.bits_per_pixel) {
431 case 16:
432 dev_dbg(&host->pdev->dev, "Setting up RGB565 mode\n");
433 ctrl |= CTRL_SET_WORD_LENGTH(0);
434 writel(CTRL1_SET_BYTE_PACKAGING(0xf), host->base + LCDC_CTRL1);
435 break;
436 case 32:
437 dev_dbg(&host->pdev->dev, "Setting up RGB888/666 mode\n");
438 ctrl |= CTRL_SET_WORD_LENGTH(3);
439 switch (host->ld_intf_width) {
440 case STMLCDIF_8BIT:
441 dev_err(&host->pdev->dev,
442 "Unsupported LCD bus width mapping\n");
443 return -EINVAL;
444 case STMLCDIF_16BIT:
445 case STMLCDIF_18BIT:
446 case STMLCDIF_24BIT:
447 /* real 24 bit */
448 break;
449 }
450 /* do not use packed pixels = one pixel per word instead */
451 writel(CTRL1_SET_BYTE_PACKAGING(0x7), host->base + LCDC_CTRL1);
452 break;
453 default:
454 dev_err(&host->pdev->dev, "Unhandled color depth of %u\n",
455 fb_info->var.bits_per_pixel);
456 return -EINVAL;
457 }
458
459 writel(ctrl, host->base + LCDC_CTRL);
460
461 writel(TRANSFER_COUNT_SET_VCOUNT(fb_info->var.yres) |
462 TRANSFER_COUNT_SET_HCOUNT(fb_info->var.xres),
463 host->base + host->devdata->transfer_count);
464
465 vdctrl0 = VDCTRL0_ENABLE_PRESENT | /* always in DOTCLOCK mode */
466 VDCTRL0_VSYNC_PERIOD_UNIT |
467 VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
468 VDCTRL0_SET_VSYNC_PULSE_WIDTH(fb_info->var.vsync_len);
469 if (fb_info->var.sync & FB_SYNC_HOR_HIGH_ACT)
470 vdctrl0 |= VDCTRL0_HSYNC_ACT_HIGH;
471 if (fb_info->var.sync & FB_SYNC_VERT_HIGH_ACT)
472 vdctrl0 |= VDCTRL0_VSYNC_ACT_HIGH;
473 if (host->sync & MXSFB_SYNC_DATA_ENABLE_HIGH_ACT)
474 vdctrl0 |= VDCTRL0_ENABLE_ACT_HIGH;
475 if (host->sync & MXSFB_SYNC_DOTCLK_FALLING_ACT)
476 vdctrl0 |= VDCTRL0_DOTCLK_ACT_FALLING;
477
478 writel(vdctrl0, host->base + LCDC_VDCTRL0);
479
480 /* frame length in lines */
481 writel(fb_info->var.upper_margin + fb_info->var.vsync_len +
482 fb_info->var.lower_margin + fb_info->var.yres,
483 host->base + LCDC_VDCTRL1);
484
485 /* line length in units of clocks or pixels */
486 writel(set_hsync_pulse_width(host, fb_info->var.hsync_len) |
487 VDCTRL2_SET_HSYNC_PERIOD(fb_info->var.left_margin +
488 fb_info->var.hsync_len + fb_info->var.right_margin +
489 fb_info->var.xres),
490 host->base + LCDC_VDCTRL2);
491
492 writel(SET_HOR_WAIT_CNT(fb_info->var.left_margin +
493 fb_info->var.hsync_len) |
494 SET_VERT_WAIT_CNT(fb_info->var.upper_margin +
495 fb_info->var.vsync_len),
496 host->base + LCDC_VDCTRL3);
497
498 vdctrl4 = SET_DOTCLK_H_VALID_DATA_CNT(fb_info->var.xres);
499 if (mxsfb_is_v4(host))
500 vdctrl4 |= VDCTRL4_SET_DOTCLK_DLY(host->dotclk_delay);
501 writel(vdctrl4, host->base + LCDC_VDCTRL4);
502
503 writel(fb_info->fix.smem_start +
504 fb_info->fix.line_length * fb_info->var.yoffset,
505 host->base + host->devdata->next_buf);
506
507 if (reenable)
508 mxsfb_enable_controller(fb_info);
509
510 return 0;
511 }
512
513 static int mxsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
514 u_int transp, struct fb_info *fb_info)
515 {
516 unsigned int val;
517 int ret = -EINVAL;
518
519 /*
520 * If greyscale is true, then we convert the RGB value
521 * to greyscale no matter what visual we are using.
522 */
523 if (fb_info->var.grayscale)
524 red = green = blue = (19595 * red + 38470 * green +
525 7471 * blue) >> 16;
526
527 switch (fb_info->fix.visual) {
528 case FB_VISUAL_TRUECOLOR:
529 /*
530 * 12 or 16-bit True Colour. We encode the RGB value
531 * according to the RGB bitfield information.
532 */
533 if (regno < 16) {
534 u32 *pal = fb_info->pseudo_palette;
535
536 val = chan_to_field(red, &fb_info->var.red);
537 val |= chan_to_field(green, &fb_info->var.green);
538 val |= chan_to_field(blue, &fb_info->var.blue);
539
540 pal[regno] = val;
541 ret = 0;
542 }
543 break;
544
545 case FB_VISUAL_STATIC_PSEUDOCOLOR:
546 case FB_VISUAL_PSEUDOCOLOR:
547 break;
548 }
549
550 return ret;
551 }
552
553 static int mxsfb_blank(int blank, struct fb_info *fb_info)
554 {
555 struct mxsfb_info *host = to_imxfb_host(fb_info);
556
557 switch (blank) {
558 case FB_BLANK_POWERDOWN:
559 case FB_BLANK_VSYNC_SUSPEND:
560 case FB_BLANK_HSYNC_SUSPEND:
561 case FB_BLANK_NORMAL:
562 if (host->enabled)
563 mxsfb_disable_controller(fb_info);
564 break;
565
566 case FB_BLANK_UNBLANK:
567 if (!host->enabled)
568 mxsfb_enable_controller(fb_info);
569 break;
570 }
571 return 0;
572 }
573
574 static int mxsfb_pan_display(struct fb_var_screeninfo *var,
575 struct fb_info *fb_info)
576 {
577 struct mxsfb_info *host = to_imxfb_host(fb_info);
578 unsigned offset;
579
580 if (var->xoffset != 0)
581 return -EINVAL;
582
583 offset = fb_info->fix.line_length * var->yoffset;
584
585 /* update on next VSYNC */
586 writel(fb_info->fix.smem_start + offset,
587 host->base + host->devdata->next_buf);
588
589 return 0;
590 }
591
592 static struct fb_ops mxsfb_ops = {
593 .owner = THIS_MODULE,
594 .fb_check_var = mxsfb_check_var,
595 .fb_set_par = mxsfb_set_par,
596 .fb_setcolreg = mxsfb_setcolreg,
597 .fb_blank = mxsfb_blank,
598 .fb_pan_display = mxsfb_pan_display,
599 .fb_fillrect = cfb_fillrect,
600 .fb_copyarea = cfb_copyarea,
601 .fb_imageblit = cfb_imageblit,
602 };
603
604 static int mxsfb_restore_mode(struct mxsfb_info *host,
605 struct fb_videomode *vmode)
606 {
607 struct fb_info *fb_info = &host->fb_info;
608 unsigned line_count;
609 unsigned period;
610 unsigned long pa, fbsize;
611 int bits_per_pixel, ofs;
612 u32 transfer_count, vdctrl0, vdctrl2, vdctrl3, vdctrl4, ctrl;
613
614 /* Only restore the mode when the controller is running */
615 ctrl = readl(host->base + LCDC_CTRL);
616 if (!(ctrl & CTRL_RUN))
617 return -EINVAL;
618
619 vdctrl0 = readl(host->base + LCDC_VDCTRL0);
620 vdctrl2 = readl(host->base + LCDC_VDCTRL2);
621 vdctrl3 = readl(host->base + LCDC_VDCTRL3);
622 vdctrl4 = readl(host->base + LCDC_VDCTRL4);
623
624 transfer_count = readl(host->base + host->devdata->transfer_count);
625
626 vmode->xres = TRANSFER_COUNT_GET_HCOUNT(transfer_count);
627 vmode->yres = TRANSFER_COUNT_GET_VCOUNT(transfer_count);
628
629 switch (CTRL_GET_WORD_LENGTH(ctrl)) {
630 case 0:
631 bits_per_pixel = 16;
632 break;
633 case 3:
634 bits_per_pixel = 32;
635 break;
636 case 1:
637 default:
638 return -EINVAL;
639 }
640
641 fb_info->var.bits_per_pixel = bits_per_pixel;
642
643 vmode->pixclock = KHZ2PICOS(clk_get_rate(host->clk) / 1000U);
644 vmode->hsync_len = get_hsync_pulse_width(host, vdctrl2);
645 vmode->left_margin = GET_HOR_WAIT_CNT(vdctrl3) - vmode->hsync_len;
646 vmode->right_margin = VDCTRL2_GET_HSYNC_PERIOD(vdctrl2) -
647 vmode->hsync_len - vmode->left_margin - vmode->xres;
648 vmode->vsync_len = VDCTRL0_GET_VSYNC_PULSE_WIDTH(vdctrl0);
649 period = readl(host->base + LCDC_VDCTRL1);
650 vmode->upper_margin = GET_VERT_WAIT_CNT(vdctrl3) - vmode->vsync_len;
651 vmode->lower_margin = period - vmode->vsync_len -
652 vmode->upper_margin - vmode->yres;
653
654 vmode->vmode = FB_VMODE_NONINTERLACED;
655
656 vmode->sync = 0;
657 if (vdctrl0 & VDCTRL0_HSYNC_ACT_HIGH)
658 vmode->sync |= FB_SYNC_HOR_HIGH_ACT;
659 if (vdctrl0 & VDCTRL0_VSYNC_ACT_HIGH)
660 vmode->sync |= FB_SYNC_VERT_HIGH_ACT;
661
662 pr_debug("Reconstructed video mode:\n");
663 pr_debug("%dx%d, hsync: %u left: %u, right: %u, vsync: %u, upper: %u, lower: %u\n",
664 vmode->xres, vmode->yres, vmode->hsync_len, vmode->left_margin,
665 vmode->right_margin, vmode->vsync_len, vmode->upper_margin,
666 vmode->lower_margin);
667 pr_debug("pixclk: %ldkHz\n", PICOS2KHZ(vmode->pixclock));
668
669 host->ld_intf_width = CTRL_GET_BUS_WIDTH(ctrl);
670 host->dotclk_delay = VDCTRL4_GET_DOTCLK_DLY(vdctrl4);
671
672 fb_info->fix.line_length = vmode->xres * (bits_per_pixel >> 3);
673
674 pa = readl(host->base + host->devdata->cur_buf);
675 fbsize = fb_info->fix.line_length * vmode->yres;
676 if (pa < fb_info->fix.smem_start)
677 return -EINVAL;
678 if (pa + fbsize > fb_info->fix.smem_start + fb_info->fix.smem_len)
679 return -EINVAL;
680 ofs = pa - fb_info->fix.smem_start;
681 if (ofs) {
682 memmove(fb_info->screen_base, fb_info->screen_base + ofs, fbsize);
683 writel(fb_info->fix.smem_start, host->base + host->devdata->next_buf);
684 }
685
686 line_count = fb_info->fix.smem_len / fb_info->fix.line_length;
687 fb_info->fix.ypanstep = 1;
688
689 clk_prepare_enable(host->clk);
690 host->enabled = 1;
691
692 return 0;
693 }
694
695 static int mxsfb_init_fbinfo_dt(struct mxsfb_info *host,
696 struct fb_videomode *vmode)
697 {
698 struct fb_info *fb_info = &host->fb_info;
699 struct fb_var_screeninfo *var = &fb_info->var;
700 struct device *dev = &host->pdev->dev;
701 struct device_node *np = host->pdev->dev.of_node;
702 struct device_node *display_np;
703 struct videomode vm;
704 u32 width;
705 int ret;
706
707 display_np = of_parse_phandle(np, "display", 0);
708 if (!display_np) {
709 dev_err(dev, "failed to find display phandle\n");
710 return -ENOENT;
711 }
712
713 ret = of_property_read_u32(display_np, "bus-width", &width);
714 if (ret < 0) {
715 dev_err(dev, "failed to get property bus-width\n");
716 goto put_display_node;
717 }
718
719 switch (width) {
720 case 8:
721 host->ld_intf_width = STMLCDIF_8BIT;
722 break;
723 case 16:
724 host->ld_intf_width = STMLCDIF_16BIT;
725 break;
726 case 18:
727 host->ld_intf_width = STMLCDIF_18BIT;
728 break;
729 case 24:
730 host->ld_intf_width = STMLCDIF_24BIT;
731 break;
732 default:
733 dev_err(dev, "invalid bus-width value\n");
734 ret = -EINVAL;
735 goto put_display_node;
736 }
737
738 ret = of_property_read_u32(display_np, "bits-per-pixel",
739 &var->bits_per_pixel);
740 if (ret < 0) {
741 dev_err(dev, "failed to get property bits-per-pixel\n");
742 goto put_display_node;
743 }
744
745 ret = of_get_videomode(display_np, &vm, OF_USE_NATIVE_MODE);
746 if (ret) {
747 dev_err(dev, "failed to get videomode from DT\n");
748 goto put_display_node;
749 }
750
751 ret = fb_videomode_from_videomode(&vm, vmode);
752 if (ret < 0)
753 goto put_display_node;
754
755 if (vm.flags & DISPLAY_FLAGS_DE_HIGH)
756 host->sync |= MXSFB_SYNC_DATA_ENABLE_HIGH_ACT;
757 if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
758 host->sync |= MXSFB_SYNC_DOTCLK_FALLING_ACT;
759
760 put_display_node:
761 of_node_put(display_np);
762 return ret;
763 }
764
765 static int mxsfb_init_fbinfo(struct mxsfb_info *host,
766 struct fb_videomode *vmode)
767 {
768 int ret;
769 struct fb_info *fb_info = &host->fb_info;
770 struct fb_var_screeninfo *var = &fb_info->var;
771 dma_addr_t fb_phys;
772 void *fb_virt;
773 unsigned fb_size;
774
775 fb_info->fbops = &mxsfb_ops;
776 fb_info->flags = FBINFO_FLAG_DEFAULT | FBINFO_READS_FAST;
777 strlcpy(fb_info->fix.id, "mxs", sizeof(fb_info->fix.id));
778 fb_info->fix.type = FB_TYPE_PACKED_PIXELS;
779 fb_info->fix.ypanstep = 1;
780 fb_info->fix.visual = FB_VISUAL_TRUECOLOR,
781 fb_info->fix.accel = FB_ACCEL_NONE;
782
783 ret = mxsfb_init_fbinfo_dt(host, vmode);
784 if (ret)
785 return ret;
786
787 var->nonstd = 0;
788 var->activate = FB_ACTIVATE_NOW;
789 var->accel_flags = 0;
790 var->vmode = FB_VMODE_NONINTERLACED;
791
792 /* Memory allocation for framebuffer */
793 fb_size = SZ_2M;
794 fb_virt = alloc_pages_exact(fb_size, GFP_DMA);
795 if (!fb_virt)
796 return -ENOMEM;
797
798 fb_phys = virt_to_phys(fb_virt);
799
800 fb_info->fix.smem_start = fb_phys;
801 fb_info->screen_base = fb_virt;
802 fb_info->screen_size = fb_info->fix.smem_len = fb_size;
803
804 if (mxsfb_restore_mode(host, vmode))
805 memset(fb_virt, 0, fb_size);
806
807 return 0;
808 }
809
810 static void mxsfb_free_videomem(struct mxsfb_info *host)
811 {
812 struct fb_info *fb_info = &host->fb_info;
813
814 free_pages_exact(fb_info->screen_base, fb_info->fix.smem_len);
815 }
816
817 static struct platform_device_id mxsfb_devtype[] = {
818 {
819 .name = "imx23-fb",
820 .driver_data = MXSFB_V3,
821 }, {
822 .name = "imx28-fb",
823 .driver_data = MXSFB_V4,
824 }, {
825 /* sentinel */
826 }
827 };
828 MODULE_DEVICE_TABLE(platform, mxsfb_devtype);
829
830 static const struct of_device_id mxsfb_dt_ids[] = {
831 { .compatible = "fsl,imx23-lcdif", .data = &mxsfb_devtype[0], },
832 { .compatible = "fsl,imx28-lcdif", .data = &mxsfb_devtype[1], },
833 { /* sentinel */ }
834 };
835 MODULE_DEVICE_TABLE(of, mxsfb_dt_ids);
836
837 static int mxsfb_probe(struct platform_device *pdev)
838 {
839 const struct of_device_id *of_id =
840 of_match_device(mxsfb_dt_ids, &pdev->dev);
841 struct resource *res;
842 struct mxsfb_info *host;
843 struct fb_info *fb_info;
844 struct fb_videomode *mode;
845 int ret;
846
847 if (of_id)
848 pdev->id_entry = of_id->data;
849
850 fb_info = framebuffer_alloc(sizeof(struct mxsfb_info), &pdev->dev);
851 if (!fb_info) {
852 dev_err(&pdev->dev, "Failed to allocate fbdev\n");
853 return -ENOMEM;
854 }
855
856 mode = devm_kzalloc(&pdev->dev, sizeof(struct fb_videomode),
857 GFP_KERNEL);
858 if (mode == NULL)
859 return -ENOMEM;
860
861 host = to_imxfb_host(fb_info);
862
863 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
864 host->base = devm_ioremap_resource(&pdev->dev, res);
865 if (IS_ERR(host->base)) {
866 ret = PTR_ERR(host->base);
867 goto fb_release;
868 }
869
870 host->pdev = pdev;
871 platform_set_drvdata(pdev, host);
872
873 host->devdata = &mxsfb_devdata[pdev->id_entry->driver_data];
874
875 host->clk = devm_clk_get(&host->pdev->dev, NULL);
876 if (IS_ERR(host->clk)) {
877 ret = PTR_ERR(host->clk);
878 goto fb_release;
879 }
880
881 host->clk_axi = devm_clk_get(&host->pdev->dev, "axi");
882 if (IS_ERR(host->clk_axi))
883 host->clk_axi = NULL;
884
885 host->clk_disp_axi = devm_clk_get(&host->pdev->dev, "disp_axi");
886 if (IS_ERR(host->clk_disp_axi))
887 host->clk_disp_axi = NULL;
888
889 host->reg_lcd = devm_regulator_get(&pdev->dev, "lcd");
890 if (IS_ERR(host->reg_lcd))
891 host->reg_lcd = NULL;
892
893 fb_info->pseudo_palette = devm_kzalloc(&pdev->dev, sizeof(u32) * 16,
894 GFP_KERNEL);
895 if (!fb_info->pseudo_palette) {
896 ret = -ENOMEM;
897 goto fb_release;
898 }
899
900 ret = mxsfb_init_fbinfo(host, mode);
901 if (ret != 0)
902 goto fb_release;
903
904 fb_videomode_to_var(&fb_info->var, mode);
905
906 /* init the color fields */
907 mxsfb_check_var(&fb_info->var, fb_info);
908
909 platform_set_drvdata(pdev, fb_info);
910
911 ret = register_framebuffer(fb_info);
912 if (ret != 0) {
913 dev_err(&pdev->dev,"Failed to register framebuffer\n");
914 goto fb_destroy;
915 }
916
917 if (!host->enabled) {
918 writel(0, host->base + LCDC_CTRL);
919 mxsfb_set_par(fb_info);
920 mxsfb_enable_controller(fb_info);
921 }
922
923 dev_info(&pdev->dev, "initialized\n");
924
925 return 0;
926
927 fb_destroy:
928 if (host->enabled)
929 clk_disable_unprepare(host->clk);
930 fb_release:
931 framebuffer_release(fb_info);
932
933 return ret;
934 }
935
936 static int mxsfb_remove(struct platform_device *pdev)
937 {
938 struct fb_info *fb_info = platform_get_drvdata(pdev);
939 struct mxsfb_info *host = to_imxfb_host(fb_info);
940
941 if (host->enabled)
942 mxsfb_disable_controller(fb_info);
943
944 unregister_framebuffer(fb_info);
945 mxsfb_free_videomem(host);
946
947 framebuffer_release(fb_info);
948
949 return 0;
950 }
951
952 static void mxsfb_shutdown(struct platform_device *pdev)
953 {
954 struct fb_info *fb_info = platform_get_drvdata(pdev);
955 struct mxsfb_info *host = to_imxfb_host(fb_info);
956
957 /*
958 * Force stop the LCD controller as keeping it running during reboot
959 * might interfere with the BootROM's boot mode pads sampling.
960 */
961 writel(CTRL_RUN, host->base + LCDC_CTRL + REG_CLR);
962 }
963
964 static struct platform_driver mxsfb_driver = {
965 .probe = mxsfb_probe,
966 .remove = mxsfb_remove,
967 .shutdown = mxsfb_shutdown,
968 .id_table = mxsfb_devtype,
969 .driver = {
970 .name = DRIVER_NAME,
971 .of_match_table = mxsfb_dt_ids,
972 },
973 };
974
975 module_platform_driver(mxsfb_driver);
976
977 MODULE_DESCRIPTION("Freescale mxs framebuffer driver");
978 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
979 MODULE_LICENSE("GPL");
(deprecated) Btrfs devel tree