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i40e: Add define for interrupt name string len
[linux-2.6/btrfs-unstable.git] / drivers / net / ethernet / intel / i40e / i40e_common.c
blob4f4d9d16bddbe9d871e20d4261de69c7e51f7440
1 /*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27 #include "i40e_type.h"
28 #include "i40e_adminq.h"
29 #include "i40e_prototype.h"
30 #include "i40e_virtchnl.h"
31
32 /**
33 * i40e_set_mac_type - Sets MAC type
34 * @hw: pointer to the HW structure
35 *
36 * This function sets the mac type of the adapter based on the
37 * vendor ID and device ID stored in the hw structure.
38 **/
39 static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
40 {
41 i40e_status status = 0;
42
43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
44 switch (hw->device_id) {
45 case I40E_DEV_ID_SFP_XL710:
46 case I40E_DEV_ID_QEMU:
47 case I40E_DEV_ID_KX_A:
48 case I40E_DEV_ID_KX_B:
49 case I40E_DEV_ID_KX_C:
50 case I40E_DEV_ID_QSFP_A:
51 case I40E_DEV_ID_QSFP_B:
52 case I40E_DEV_ID_QSFP_C:
53 case I40E_DEV_ID_10G_BASE_T:
54 hw->mac.type = I40E_MAC_XL710;
55 break;
56 case I40E_DEV_ID_VF:
57 case I40E_DEV_ID_VF_HV:
58 hw->mac.type = I40E_MAC_VF;
59 break;
60 default:
61 hw->mac.type = I40E_MAC_GENERIC;
62 break;
63 }
64 } else {
65 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
66 }
67
68 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
69 hw->mac.type, status);
70 return status;
71 }
72
73 /**
74 * i40e_debug_aq
75 * @hw: debug mask related to admin queue
76 * @mask: debug mask
77 * @desc: pointer to admin queue descriptor
78 * @buffer: pointer to command buffer
79 * @buf_len: max length of buffer
80 *
81 * Dumps debug log about adminq command with descriptor contents.
82 **/
83 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
84 void *buffer, u16 buf_len)
85 {
86 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
87 u16 len = le16_to_cpu(aq_desc->datalen);
88 u8 *aq_buffer = (u8 *)buffer;
89 u32 data[4];
90 u32 i = 0;
91
92 if ((!(mask & hw->debug_mask)) || (desc == NULL))
93 return;
94
95 i40e_debug(hw, mask,
96 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
97 aq_desc->opcode, aq_desc->flags, aq_desc->datalen,
98 aq_desc->retval);
99 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
100 aq_desc->cookie_high, aq_desc->cookie_low);
101 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
102 aq_desc->params.internal.param0,
103 aq_desc->params.internal.param1);
104 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
105 aq_desc->params.external.addr_high,
106 aq_desc->params.external.addr_low);
107
108 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
109 memset(data, 0, sizeof(data));
110 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
111 if (buf_len < len)
112 len = buf_len;
113 for (i = 0; i < len; i++) {
114 data[((i % 16) / 4)] |=
115 ((u32)aq_buffer[i]) << (8 * (i % 4));
116 if ((i % 16) == 15) {
117 i40e_debug(hw, mask,
118 "\t0x%04X %08X %08X %08X %08X\n",
119 i - 15, data[0], data[1], data[2],
120 data[3]);
121 memset(data, 0, sizeof(data));
122 }
123 }
124 if ((i % 16) != 0)
125 i40e_debug(hw, mask, "\t0x%04X %08X %08X %08X %08X\n",
126 i - (i % 16), data[0], data[1], data[2],
127 data[3]);
128 }
129 }
130
131 /**
132 * i40e_check_asq_alive
133 * @hw: pointer to the hw struct
134 *
135 * Returns true if Queue is enabled else false.
136 **/
137 bool i40e_check_asq_alive(struct i40e_hw *hw)
138 {
139 if (hw->aq.asq.len)
140 return !!(rd32(hw, hw->aq.asq.len) &
141 I40E_PF_ATQLEN_ATQENABLE_MASK);
142 else
143 return false;
144 }
145
146 /**
147 * i40e_aq_queue_shutdown
148 * @hw: pointer to the hw struct
149 * @unloading: is the driver unloading itself
150 *
151 * Tell the Firmware that we're shutting down the AdminQ and whether
152 * or not the driver is unloading as well.
153 **/
154 i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
155 bool unloading)
156 {
157 struct i40e_aq_desc desc;
158 struct i40e_aqc_queue_shutdown *cmd =
159 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
160 i40e_status status;
161
162 i40e_fill_default_direct_cmd_desc(&desc,
163 i40e_aqc_opc_queue_shutdown);
164
165 if (unloading)
166 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
167 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
168
169 return status;
170 }
171
172 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
173 * hardware to a bit-field that can be used by SW to more easily determine the
174 * packet type.
175 *
176 * Macros are used to shorten the table lines and make this table human
177 * readable.
178 *
179 * We store the PTYPE in the top byte of the bit field - this is just so that
180 * we can check that the table doesn't have a row missing, as the index into
181 * the table should be the PTYPE.
182 *
183 * Typical work flow:
184 *
185 * IF NOT i40e_ptype_lookup[ptype].known
186 * THEN
187 * Packet is unknown
188 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
189 * Use the rest of the fields to look at the tunnels, inner protocols, etc
190 * ELSE
191 * Use the enum i40e_rx_l2_ptype to decode the packet type
192 * ENDIF
193 */
194
195 /* macro to make the table lines short */
196 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
197 { PTYPE, \
198 1, \
199 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
200 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
201 I40E_RX_PTYPE_##OUTER_FRAG, \
202 I40E_RX_PTYPE_TUNNEL_##T, \
203 I40E_RX_PTYPE_TUNNEL_END_##TE, \
204 I40E_RX_PTYPE_##TEF, \
205 I40E_RX_PTYPE_INNER_PROT_##I, \
206 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
207
208 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
209 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
210
211 /* shorter macros makes the table fit but are terse */
212 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
213 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
214 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
215
216 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
217 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
218 /* L2 Packet types */
219 I40E_PTT_UNUSED_ENTRY(0),
220 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
221 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
222 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
223 I40E_PTT_UNUSED_ENTRY(4),
224 I40E_PTT_UNUSED_ENTRY(5),
225 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
226 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
227 I40E_PTT_UNUSED_ENTRY(8),
228 I40E_PTT_UNUSED_ENTRY(9),
229 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
230 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
231 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
232 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
233 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
234 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
235 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
236 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
237 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
238 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
239 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
240 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
241
242 /* Non Tunneled IPv4 */
243 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
244 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
245 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
246 I40E_PTT_UNUSED_ENTRY(25),
247 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
248 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
249 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
250
251 /* IPv4 --> IPv4 */
252 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
253 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
254 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
255 I40E_PTT_UNUSED_ENTRY(32),
256 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
257 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
258 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
259
260 /* IPv4 --> IPv6 */
261 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
262 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
263 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
264 I40E_PTT_UNUSED_ENTRY(39),
265 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
266 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
267 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
268
269 /* IPv4 --> GRE/NAT */
270 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
271
272 /* IPv4 --> GRE/NAT --> IPv4 */
273 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
274 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
275 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
276 I40E_PTT_UNUSED_ENTRY(47),
277 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
278 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
279 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
280
281 /* IPv4 --> GRE/NAT --> IPv6 */
282 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
283 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
284 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
285 I40E_PTT_UNUSED_ENTRY(54),
286 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
287 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
288 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
289
290 /* IPv4 --> GRE/NAT --> MAC */
291 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
292
293 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
294 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
295 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
296 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
297 I40E_PTT_UNUSED_ENTRY(62),
298 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
299 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
300 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
301
302 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
303 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
304 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
305 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
306 I40E_PTT_UNUSED_ENTRY(69),
307 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
308 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
309 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
310
311 /* IPv4 --> GRE/NAT --> MAC/VLAN */
312 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
313
314 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
315 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
316 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
317 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
318 I40E_PTT_UNUSED_ENTRY(77),
319 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
320 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
321 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
322
323 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
324 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
325 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
326 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
327 I40E_PTT_UNUSED_ENTRY(84),
328 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
329 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
330 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
331
332 /* Non Tunneled IPv6 */
333 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
334 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
335 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
336 I40E_PTT_UNUSED_ENTRY(91),
337 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
338 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
339 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
340
341 /* IPv6 --> IPv4 */
342 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
343 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
344 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
345 I40E_PTT_UNUSED_ENTRY(98),
346 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
347 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
348 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
349
350 /* IPv6 --> IPv6 */
351 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
352 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
353 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
354 I40E_PTT_UNUSED_ENTRY(105),
355 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
356 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
357 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
358
359 /* IPv6 --> GRE/NAT */
360 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
361
362 /* IPv6 --> GRE/NAT -> IPv4 */
363 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
364 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
365 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
366 I40E_PTT_UNUSED_ENTRY(113),
367 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
368 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
369 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
370
371 /* IPv6 --> GRE/NAT -> IPv6 */
372 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
373 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
374 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
375 I40E_PTT_UNUSED_ENTRY(120),
376 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
377 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
378 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
379
380 /* IPv6 --> GRE/NAT -> MAC */
381 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
382
383 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
384 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
385 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
386 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
387 I40E_PTT_UNUSED_ENTRY(128),
388 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
389 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
390 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
391
392 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
393 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
394 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
395 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
396 I40E_PTT_UNUSED_ENTRY(135),
397 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
398 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
399 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
400
401 /* IPv6 --> GRE/NAT -> MAC/VLAN */
402 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
403
404 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
405 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
406 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
407 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
408 I40E_PTT_UNUSED_ENTRY(143),
409 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
410 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
411 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
412
413 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
414 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
415 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
416 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
417 I40E_PTT_UNUSED_ENTRY(150),
418 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
419 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
420 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
421
422 /* unused entries */
423 I40E_PTT_UNUSED_ENTRY(154),
424 I40E_PTT_UNUSED_ENTRY(155),
425 I40E_PTT_UNUSED_ENTRY(156),
426 I40E_PTT_UNUSED_ENTRY(157),
427 I40E_PTT_UNUSED_ENTRY(158),
428 I40E_PTT_UNUSED_ENTRY(159),
429
430 I40E_PTT_UNUSED_ENTRY(160),
431 I40E_PTT_UNUSED_ENTRY(161),
432 I40E_PTT_UNUSED_ENTRY(162),
433 I40E_PTT_UNUSED_ENTRY(163),
434 I40E_PTT_UNUSED_ENTRY(164),
435 I40E_PTT_UNUSED_ENTRY(165),
436 I40E_PTT_UNUSED_ENTRY(166),
437 I40E_PTT_UNUSED_ENTRY(167),
438 I40E_PTT_UNUSED_ENTRY(168),
439 I40E_PTT_UNUSED_ENTRY(169),
440
441 I40E_PTT_UNUSED_ENTRY(170),
442 I40E_PTT_UNUSED_ENTRY(171),
443 I40E_PTT_UNUSED_ENTRY(172),
444 I40E_PTT_UNUSED_ENTRY(173),
445 I40E_PTT_UNUSED_ENTRY(174),
446 I40E_PTT_UNUSED_ENTRY(175),
447 I40E_PTT_UNUSED_ENTRY(176),
448 I40E_PTT_UNUSED_ENTRY(177),
449 I40E_PTT_UNUSED_ENTRY(178),
450 I40E_PTT_UNUSED_ENTRY(179),
451
452 I40E_PTT_UNUSED_ENTRY(180),
453 I40E_PTT_UNUSED_ENTRY(181),
454 I40E_PTT_UNUSED_ENTRY(182),
455 I40E_PTT_UNUSED_ENTRY(183),
456 I40E_PTT_UNUSED_ENTRY(184),
457 I40E_PTT_UNUSED_ENTRY(185),
458 I40E_PTT_UNUSED_ENTRY(186),
459 I40E_PTT_UNUSED_ENTRY(187),
460 I40E_PTT_UNUSED_ENTRY(188),
461 I40E_PTT_UNUSED_ENTRY(189),
462
463 I40E_PTT_UNUSED_ENTRY(190),
464 I40E_PTT_UNUSED_ENTRY(191),
465 I40E_PTT_UNUSED_ENTRY(192),
466 I40E_PTT_UNUSED_ENTRY(193),
467 I40E_PTT_UNUSED_ENTRY(194),
468 I40E_PTT_UNUSED_ENTRY(195),
469 I40E_PTT_UNUSED_ENTRY(196),
470 I40E_PTT_UNUSED_ENTRY(197),
471 I40E_PTT_UNUSED_ENTRY(198),
472 I40E_PTT_UNUSED_ENTRY(199),
473
474 I40E_PTT_UNUSED_ENTRY(200),
475 I40E_PTT_UNUSED_ENTRY(201),
476 I40E_PTT_UNUSED_ENTRY(202),
477 I40E_PTT_UNUSED_ENTRY(203),
478 I40E_PTT_UNUSED_ENTRY(204),
479 I40E_PTT_UNUSED_ENTRY(205),
480 I40E_PTT_UNUSED_ENTRY(206),
481 I40E_PTT_UNUSED_ENTRY(207),
482 I40E_PTT_UNUSED_ENTRY(208),
483 I40E_PTT_UNUSED_ENTRY(209),
484
485 I40E_PTT_UNUSED_ENTRY(210),
486 I40E_PTT_UNUSED_ENTRY(211),
487 I40E_PTT_UNUSED_ENTRY(212),
488 I40E_PTT_UNUSED_ENTRY(213),
489 I40E_PTT_UNUSED_ENTRY(214),
490 I40E_PTT_UNUSED_ENTRY(215),
491 I40E_PTT_UNUSED_ENTRY(216),
492 I40E_PTT_UNUSED_ENTRY(217),
493 I40E_PTT_UNUSED_ENTRY(218),
494 I40E_PTT_UNUSED_ENTRY(219),
495
496 I40E_PTT_UNUSED_ENTRY(220),
497 I40E_PTT_UNUSED_ENTRY(221),
498 I40E_PTT_UNUSED_ENTRY(222),
499 I40E_PTT_UNUSED_ENTRY(223),
500 I40E_PTT_UNUSED_ENTRY(224),
501 I40E_PTT_UNUSED_ENTRY(225),
502 I40E_PTT_UNUSED_ENTRY(226),
503 I40E_PTT_UNUSED_ENTRY(227),
504 I40E_PTT_UNUSED_ENTRY(228),
505 I40E_PTT_UNUSED_ENTRY(229),
506
507 I40E_PTT_UNUSED_ENTRY(230),
508 I40E_PTT_UNUSED_ENTRY(231),
509 I40E_PTT_UNUSED_ENTRY(232),
510 I40E_PTT_UNUSED_ENTRY(233),
511 I40E_PTT_UNUSED_ENTRY(234),
512 I40E_PTT_UNUSED_ENTRY(235),
513 I40E_PTT_UNUSED_ENTRY(236),
514 I40E_PTT_UNUSED_ENTRY(237),
515 I40E_PTT_UNUSED_ENTRY(238),
516 I40E_PTT_UNUSED_ENTRY(239),
517
518 I40E_PTT_UNUSED_ENTRY(240),
519 I40E_PTT_UNUSED_ENTRY(241),
520 I40E_PTT_UNUSED_ENTRY(242),
521 I40E_PTT_UNUSED_ENTRY(243),
522 I40E_PTT_UNUSED_ENTRY(244),
523 I40E_PTT_UNUSED_ENTRY(245),
524 I40E_PTT_UNUSED_ENTRY(246),
525 I40E_PTT_UNUSED_ENTRY(247),
526 I40E_PTT_UNUSED_ENTRY(248),
527 I40E_PTT_UNUSED_ENTRY(249),
528
529 I40E_PTT_UNUSED_ENTRY(250),
530 I40E_PTT_UNUSED_ENTRY(251),
531 I40E_PTT_UNUSED_ENTRY(252),
532 I40E_PTT_UNUSED_ENTRY(253),
533 I40E_PTT_UNUSED_ENTRY(254),
534 I40E_PTT_UNUSED_ENTRY(255)
535 };
536
537
538 /**
539 * i40e_init_shared_code - Initialize the shared code
540 * @hw: pointer to hardware structure
541 *
542 * This assigns the MAC type and PHY code and inits the NVM.
543 * Does not touch the hardware. This function must be called prior to any
544 * other function in the shared code. The i40e_hw structure should be
545 * memset to 0 prior to calling this function. The following fields in
546 * hw structure should be filled in prior to calling this function:
547 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
548 * subsystem_vendor_id, and revision_id
549 **/
550 i40e_status i40e_init_shared_code(struct i40e_hw *hw)
551 {
552 i40e_status status = 0;
553 u32 port, ari, func_rid;
554
555 i40e_set_mac_type(hw);
556
557 switch (hw->mac.type) {
558 case I40E_MAC_XL710:
559 break;
560 default:
561 return I40E_ERR_DEVICE_NOT_SUPPORTED;
562 }
563
564 hw->phy.get_link_info = true;
565
566 /* Determine port number and PF number*/
567 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
568 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
569 hw->port = (u8)port;
570 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
571 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
572 func_rid = rd32(hw, I40E_PF_FUNC_RID);
573 if (ari)
574 hw->pf_id = (u8)(func_rid & 0xff);
575 else
576 hw->pf_id = (u8)(func_rid & 0x7);
577
578 status = i40e_init_nvm(hw);
579 return status;
580 }
581
582 /**
583 * i40e_aq_mac_address_read - Retrieve the MAC addresses
584 * @hw: pointer to the hw struct
585 * @flags: a return indicator of what addresses were added to the addr store
586 * @addrs: the requestor's mac addr store
587 * @cmd_details: pointer to command details structure or NULL
588 **/
589 static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
590 u16 *flags,
591 struct i40e_aqc_mac_address_read_data *addrs,
592 struct i40e_asq_cmd_details *cmd_details)
593 {
594 struct i40e_aq_desc desc;
595 struct i40e_aqc_mac_address_read *cmd_data =
596 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
597 i40e_status status;
598
599 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
600 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
601
602 status = i40e_asq_send_command(hw, &desc, addrs,
603 sizeof(*addrs), cmd_details);
604 *flags = le16_to_cpu(cmd_data->command_flags);
605
606 return status;
607 }
608
609 /**
610 * i40e_aq_mac_address_write - Change the MAC addresses
611 * @hw: pointer to the hw struct
612 * @flags: indicates which MAC to be written
613 * @mac_addr: address to write
614 * @cmd_details: pointer to command details structure or NULL
615 **/
616 i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
617 u16 flags, u8 *mac_addr,
618 struct i40e_asq_cmd_details *cmd_details)
619 {
620 struct i40e_aq_desc desc;
621 struct i40e_aqc_mac_address_write *cmd_data =
622 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
623 i40e_status status;
624
625 i40e_fill_default_direct_cmd_desc(&desc,
626 i40e_aqc_opc_mac_address_write);
627 cmd_data->command_flags = cpu_to_le16(flags);
628 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
629 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
630 ((u32)mac_addr[3] << 16) |
631 ((u32)mac_addr[4] << 8) |
632 mac_addr[5]);
633
634 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
635
636 return status;
637 }
638
639 /**
640 * i40e_get_mac_addr - get MAC address
641 * @hw: pointer to the HW structure
642 * @mac_addr: pointer to MAC address
643 *
644 * Reads the adapter's MAC address from register
645 **/
646 i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
647 {
648 struct i40e_aqc_mac_address_read_data addrs;
649 i40e_status status;
650 u16 flags = 0;
651
652 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
653
654 if (flags & I40E_AQC_LAN_ADDR_VALID)
655 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
656
657 return status;
658 }
659
660 /**
661 * i40e_get_port_mac_addr - get Port MAC address
662 * @hw: pointer to the HW structure
663 * @mac_addr: pointer to Port MAC address
664 *
665 * Reads the adapter's Port MAC address
666 **/
667 i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
668 {
669 struct i40e_aqc_mac_address_read_data addrs;
670 i40e_status status;
671 u16 flags = 0;
672
673 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
674 if (status)
675 return status;
676
677 if (flags & I40E_AQC_PORT_ADDR_VALID)
678 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
679 else
680 status = I40E_ERR_INVALID_MAC_ADDR;
681
682 return status;
683 }
684
685 /**
686 * i40e_pre_tx_queue_cfg - pre tx queue configure
687 * @hw: pointer to the HW structure
688 * @queue: target pf queue index
689 * @enable: state change request
690 *
691 * Handles hw requirement to indicate intention to enable
692 * or disable target queue.
693 **/
694 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
695 {
696 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
697 u32 reg_block = 0;
698 u32 reg_val;
699
700 if (abs_queue_idx >= 128) {
701 reg_block = abs_queue_idx / 128;
702 abs_queue_idx %= 128;
703 }
704
705 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
706 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
707 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
708
709 if (enable)
710 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
711 else
712 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
713
714 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
715 }
716 #ifdef I40E_FCOE
717
718 /**
719 * i40e_get_san_mac_addr - get SAN MAC address
720 * @hw: pointer to the HW structure
721 * @mac_addr: pointer to SAN MAC address
722 *
723 * Reads the adapter's SAN MAC address from NVM
724 **/
725 i40e_status i40e_get_san_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
726 {
727 struct i40e_aqc_mac_address_read_data addrs;
728 i40e_status status;
729 u16 flags = 0;
730
731 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
732 if (status)
733 return status;
734
735 if (flags & I40E_AQC_SAN_ADDR_VALID)
736 memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac));
737 else
738 status = I40E_ERR_INVALID_MAC_ADDR;
739
740 return status;
741 }
742 #endif
743
744 /**
745 * i40e_read_pba_string - Reads part number string from EEPROM
746 * @hw: pointer to hardware structure
747 * @pba_num: stores the part number string from the EEPROM
748 * @pba_num_size: part number string buffer length
749 *
750 * Reads the part number string from the EEPROM.
751 **/
752 i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
753 u32 pba_num_size)
754 {
755 i40e_status status = 0;
756 u16 pba_word = 0;
757 u16 pba_size = 0;
758 u16 pba_ptr = 0;
759 u16 i = 0;
760
761 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
762 if (status || (pba_word != 0xFAFA)) {
763 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n");
764 return status;
765 }
766
767 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
768 if (status) {
769 hw_dbg(hw, "Failed to read PBA Block pointer.\n");
770 return status;
771 }
772
773 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
774 if (status) {
775 hw_dbg(hw, "Failed to read PBA Block size.\n");
776 return status;
777 }
778
779 /* Subtract one to get PBA word count (PBA Size word is included in
780 * total size)
781 */
782 pba_size--;
783 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
784 hw_dbg(hw, "Buffer to small for PBA data.\n");
785 return I40E_ERR_PARAM;
786 }
787
788 for (i = 0; i < pba_size; i++) {
789 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
790 if (status) {
791 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i);
792 return status;
793 }
794
795 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
796 pba_num[(i * 2) + 1] = pba_word & 0xFF;
797 }
798 pba_num[(pba_size * 2)] = '\0';
799
800 return status;
801 }
802
803 /**
804 * i40e_get_media_type - Gets media type
805 * @hw: pointer to the hardware structure
806 **/
807 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
808 {
809 enum i40e_media_type media;
810
811 switch (hw->phy.link_info.phy_type) {
812 case I40E_PHY_TYPE_10GBASE_SR:
813 case I40E_PHY_TYPE_10GBASE_LR:
814 case I40E_PHY_TYPE_1000BASE_SX:
815 case I40E_PHY_TYPE_1000BASE_LX:
816 case I40E_PHY_TYPE_40GBASE_SR4:
817 case I40E_PHY_TYPE_40GBASE_LR4:
818 media = I40E_MEDIA_TYPE_FIBER;
819 break;
820 case I40E_PHY_TYPE_100BASE_TX:
821 case I40E_PHY_TYPE_1000BASE_T:
822 case I40E_PHY_TYPE_10GBASE_T:
823 media = I40E_MEDIA_TYPE_BASET;
824 break;
825 case I40E_PHY_TYPE_10GBASE_CR1_CU:
826 case I40E_PHY_TYPE_40GBASE_CR4_CU:
827 case I40E_PHY_TYPE_10GBASE_CR1:
828 case I40E_PHY_TYPE_40GBASE_CR4:
829 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
830 media = I40E_MEDIA_TYPE_DA;
831 break;
832 case I40E_PHY_TYPE_1000BASE_KX:
833 case I40E_PHY_TYPE_10GBASE_KX4:
834 case I40E_PHY_TYPE_10GBASE_KR:
835 case I40E_PHY_TYPE_40GBASE_KR4:
836 media = I40E_MEDIA_TYPE_BACKPLANE;
837 break;
838 case I40E_PHY_TYPE_SGMII:
839 case I40E_PHY_TYPE_XAUI:
840 case I40E_PHY_TYPE_XFI:
841 case I40E_PHY_TYPE_XLAUI:
842 case I40E_PHY_TYPE_XLPPI:
843 default:
844 media = I40E_MEDIA_TYPE_UNKNOWN;
845 break;
846 }
847
848 return media;
849 }
850
851 #define I40E_PF_RESET_WAIT_COUNT_A0 200
852 #define I40E_PF_RESET_WAIT_COUNT 110
853 /**
854 * i40e_pf_reset - Reset the PF
855 * @hw: pointer to the hardware structure
856 *
857 * Assuming someone else has triggered a global reset,
858 * assure the global reset is complete and then reset the PF
859 **/
860 i40e_status i40e_pf_reset(struct i40e_hw *hw)
861 {
862 u32 cnt = 0;
863 u32 cnt1 = 0;
864 u32 reg = 0;
865 u32 grst_del;
866
867 /* Poll for Global Reset steady state in case of recent GRST.
868 * The grst delay value is in 100ms units, and we'll wait a
869 * couple counts longer to be sure we don't just miss the end.
870 */
871 grst_del = rd32(hw, I40E_GLGEN_RSTCTL) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK
872 >> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
873 for (cnt = 0; cnt < grst_del + 2; cnt++) {
874 reg = rd32(hw, I40E_GLGEN_RSTAT);
875 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
876 break;
877 msleep(100);
878 }
879 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
880 hw_dbg(hw, "Global reset polling failed to complete.\n");
881 return I40E_ERR_RESET_FAILED;
882 }
883
884 /* Now Wait for the FW to be ready */
885 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
886 reg = rd32(hw, I40E_GLNVM_ULD);
887 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
888 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
889 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
890 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
891 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
892 break;
893 }
894 usleep_range(10000, 20000);
895 }
896 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
897 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
898 hw_dbg(hw, "wait for FW Reset complete timedout\n");
899 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
900 return I40E_ERR_RESET_FAILED;
901 }
902
903 /* If there was a Global Reset in progress when we got here,
904 * we don't need to do the PF Reset
905 */
906 if (!cnt) {
907 if (hw->revision_id == 0)
908 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
909 else
910 cnt = I40E_PF_RESET_WAIT_COUNT;
911 reg = rd32(hw, I40E_PFGEN_CTRL);
912 wr32(hw, I40E_PFGEN_CTRL,
913 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
914 for (; cnt; cnt--) {
915 reg = rd32(hw, I40E_PFGEN_CTRL);
916 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
917 break;
918 usleep_range(1000, 2000);
919 }
920 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
921 hw_dbg(hw, "PF reset polling failed to complete.\n");
922 return I40E_ERR_RESET_FAILED;
923 }
924 }
925
926 i40e_clear_pxe_mode(hw);
927
928 return 0;
929 }
930
931 /**
932 * i40e_clear_hw - clear out any left over hw state
933 * @hw: pointer to the hw struct
934 *
935 * Clear queues and interrupts, typically called at init time,
936 * but after the capabilities have been found so we know how many
937 * queues and msix vectors have been allocated.
938 **/
939 void i40e_clear_hw(struct i40e_hw *hw)
940 {
941 u32 num_queues, base_queue;
942 u32 num_pf_int;
943 u32 num_vf_int;
944 u32 num_vfs;
945 u32 i, j;
946 u32 val;
947 u32 eol = 0x7ff;
948
949 /* get number of interrupts, queues, and vfs */
950 val = rd32(hw, I40E_GLPCI_CNF2);
951 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
952 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
953 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
954 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
955
956 val = rd32(hw, I40E_PFLAN_QALLOC);
957 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
958 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
959 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
960 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
961 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
962 num_queues = (j - base_queue) + 1;
963 else
964 num_queues = 0;
965
966 val = rd32(hw, I40E_PF_VT_PFALLOC);
967 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
968 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
969 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
970 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
971 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
972 num_vfs = (j - i) + 1;
973 else
974 num_vfs = 0;
975
976 /* stop all the interrupts */
977 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
978 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
979 for (i = 0; i < num_pf_int - 2; i++)
980 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
981
982 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
983 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
984 wr32(hw, I40E_PFINT_LNKLST0, val);
985 for (i = 0; i < num_pf_int - 2; i++)
986 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
987 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
988 for (i = 0; i < num_vfs; i++)
989 wr32(hw, I40E_VPINT_LNKLST0(i), val);
990 for (i = 0; i < num_vf_int - 2; i++)
991 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
992
993 /* warn the HW of the coming Tx disables */
994 for (i = 0; i < num_queues; i++) {
995 u32 abs_queue_idx = base_queue + i;
996 u32 reg_block = 0;
997
998 if (abs_queue_idx >= 128) {
999 reg_block = abs_queue_idx / 128;
1000 abs_queue_idx %= 128;
1001 }
1002
1003 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1004 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1005 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1006 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1007
1008 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1009 }
1010 udelay(400);
1011
1012 /* stop all the queues */
1013 for (i = 0; i < num_queues; i++) {
1014 wr32(hw, I40E_QINT_TQCTL(i), 0);
1015 wr32(hw, I40E_QTX_ENA(i), 0);
1016 wr32(hw, I40E_QINT_RQCTL(i), 0);
1017 wr32(hw, I40E_QRX_ENA(i), 0);
1018 }
1019
1020 /* short wait for all queue disables to settle */
1021 udelay(50);
1022 }
1023
1024 /**
1025 * i40e_clear_pxe_mode - clear pxe operations mode
1026 * @hw: pointer to the hw struct
1027 *
1028 * Make sure all PXE mode settings are cleared, including things
1029 * like descriptor fetch/write-back mode.
1030 **/
1031 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1032 {
1033 u32 reg;
1034
1035 if (i40e_check_asq_alive(hw))
1036 i40e_aq_clear_pxe_mode(hw, NULL);
1037
1038 /* Clear single descriptor fetch/write-back mode */
1039 reg = rd32(hw, I40E_GLLAN_RCTL_0);
1040
1041 if (hw->revision_id == 0) {
1042 /* As a work around clear PXE_MODE instead of setting it */
1043 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
1044 } else {
1045 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
1046 }
1047 }
1048
1049 /**
1050 * i40e_led_is_mine - helper to find matching led
1051 * @hw: pointer to the hw struct
1052 * @idx: index into GPIO registers
1053 *
1054 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1055 */
1056 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1057 {
1058 u32 gpio_val = 0;
1059 u32 port;
1060
1061 if (!hw->func_caps.led[idx])
1062 return 0;
1063
1064 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1065 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1066 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1067
1068 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1069 * if it is not our port then ignore
1070 */
1071 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1072 (port != hw->port))
1073 return 0;
1074
1075 return gpio_val;
1076 }
1077
1078 #define I40E_LED0 22
1079 #define I40E_LINK_ACTIVITY 0xC
1080
1081 /**
1082 * i40e_led_get - return current on/off mode
1083 * @hw: pointer to the hw struct
1084 *
1085 * The value returned is the 'mode' field as defined in the
1086 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1087 * values are variations of possible behaviors relating to
1088 * blink, link, and wire.
1089 **/
1090 u32 i40e_led_get(struct i40e_hw *hw)
1091 {
1092 u32 mode = 0;
1093 int i;
1094
1095 /* as per the documentation GPIO 22-29 are the LED
1096 * GPIO pins named LED0..LED7
1097 */
1098 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1099 u32 gpio_val = i40e_led_is_mine(hw, i);
1100
1101 if (!gpio_val)
1102 continue;
1103
1104 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1105 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1106 break;
1107 }
1108
1109 return mode;
1110 }
1111
1112 /**
1113 * i40e_led_set - set new on/off mode
1114 * @hw: pointer to the hw struct
1115 * @mode: 0=off, 0xf=on (else see manual for mode details)
1116 * @blink: true if the LED should blink when on, false if steady
1117 *
1118 * if this function is used to turn on the blink it should
1119 * be used to disable the blink when restoring the original state.
1120 **/
1121 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1122 {
1123 int i;
1124
1125 if (mode & 0xfffffff0)
1126 hw_dbg(hw, "invalid mode passed in %X\n", mode);
1127
1128 /* as per the documentation GPIO 22-29 are the LED
1129 * GPIO pins named LED0..LED7
1130 */
1131 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1132 u32 gpio_val = i40e_led_is_mine(hw, i);
1133
1134 if (!gpio_val)
1135 continue;
1136
1137 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1138 /* this & is a bit of paranoia, but serves as a range check */
1139 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1140 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1141
1142 if (mode == I40E_LINK_ACTIVITY)
1143 blink = false;
1144
1145 gpio_val |= (blink ? 1 : 0) <<
1146 I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT;
1147
1148 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1149 break;
1150 }
1151 }
1152
1153 /* Admin command wrappers */
1154
1155 /**
1156 * i40e_aq_get_phy_capabilities
1157 * @hw: pointer to the hw struct
1158 * @abilities: structure for PHY capabilities to be filled
1159 * @qualified_modules: report Qualified Modules
1160 * @report_init: report init capabilities (active are default)
1161 * @cmd_details: pointer to command details structure or NULL
1162 *
1163 * Returns the various PHY abilities supported on the Port.
1164 **/
1165 i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1166 bool qualified_modules, bool report_init,
1167 struct i40e_aq_get_phy_abilities_resp *abilities,
1168 struct i40e_asq_cmd_details *cmd_details)
1169 {
1170 struct i40e_aq_desc desc;
1171 i40e_status status;
1172 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1173
1174 if (!abilities)
1175 return I40E_ERR_PARAM;
1176
1177 i40e_fill_default_direct_cmd_desc(&desc,
1178 i40e_aqc_opc_get_phy_abilities);
1179
1180 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1181 if (abilities_size > I40E_AQ_LARGE_BUF)
1182 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1183
1184 if (qualified_modules)
1185 desc.params.external.param0 |=
1186 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1187
1188 if (report_init)
1189 desc.params.external.param0 |=
1190 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1191
1192 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1193 cmd_details);
1194
1195 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1196 status = I40E_ERR_UNKNOWN_PHY;
1197
1198 return status;
1199 }
1200
1201 /**
1202 * i40e_aq_set_phy_config
1203 * @hw: pointer to the hw struct
1204 * @config: structure with PHY configuration to be set
1205 * @cmd_details: pointer to command details structure or NULL
1206 *
1207 * Set the various PHY configuration parameters
1208 * supported on the Port.One or more of the Set PHY config parameters may be
1209 * ignored in an MFP mode as the PF may not have the privilege to set some
1210 * of the PHY Config parameters. This status will be indicated by the
1211 * command response.
1212 **/
1213 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1214 struct i40e_aq_set_phy_config *config,
1215 struct i40e_asq_cmd_details *cmd_details)
1216 {
1217 struct i40e_aq_desc desc;
1218 struct i40e_aq_set_phy_config *cmd =
1219 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1220 enum i40e_status_code status;
1221
1222 if (!config)
1223 return I40E_ERR_PARAM;
1224
1225 i40e_fill_default_direct_cmd_desc(&desc,
1226 i40e_aqc_opc_set_phy_config);
1227
1228 *cmd = *config;
1229
1230 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1231
1232 return status;
1233 }
1234
1235 /**
1236 * i40e_set_fc
1237 * @hw: pointer to the hw struct
1238 *
1239 * Set the requested flow control mode using set_phy_config.
1240 **/
1241 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1242 bool atomic_restart)
1243 {
1244 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1245 struct i40e_aq_get_phy_abilities_resp abilities;
1246 struct i40e_aq_set_phy_config config;
1247 enum i40e_status_code status;
1248 u8 pause_mask = 0x0;
1249
1250 *aq_failures = 0x0;
1251
1252 switch (fc_mode) {
1253 case I40E_FC_FULL:
1254 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1255 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1256 break;
1257 case I40E_FC_RX_PAUSE:
1258 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1259 break;
1260 case I40E_FC_TX_PAUSE:
1261 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1262 break;
1263 default:
1264 break;
1265 }
1266
1267 /* Get the current phy config */
1268 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1269 NULL);
1270 if (status) {
1271 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1272 return status;
1273 }
1274
1275 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1276 /* clear the old pause settings */
1277 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1278 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1279 /* set the new abilities */
1280 config.abilities |= pause_mask;
1281 /* If the abilities have changed, then set the new config */
1282 if (config.abilities != abilities.abilities) {
1283 /* Auto restart link so settings take effect */
1284 if (atomic_restart)
1285 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1286 /* Copy over all the old settings */
1287 config.phy_type = abilities.phy_type;
1288 config.link_speed = abilities.link_speed;
1289 config.eee_capability = abilities.eee_capability;
1290 config.eeer = abilities.eeer_val;
1291 config.low_power_ctrl = abilities.d3_lpan;
1292 status = i40e_aq_set_phy_config(hw, &config, NULL);
1293
1294 if (status)
1295 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1296 }
1297 /* Update the link info */
1298 status = i40e_update_link_info(hw, true);
1299 if (status) {
1300 /* Wait a little bit (on 40G cards it sometimes takes a really
1301 * long time for link to come back from the atomic reset)
1302 * and try once more
1303 */
1304 msleep(1000);
1305 status = i40e_update_link_info(hw, true);
1306 }
1307 if (status)
1308 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1309
1310 return status;
1311 }
1312
1313 /**
1314 * i40e_aq_clear_pxe_mode
1315 * @hw: pointer to the hw struct
1316 * @cmd_details: pointer to command details structure or NULL
1317 *
1318 * Tell the firmware that the driver is taking over from PXE
1319 **/
1320 i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1321 struct i40e_asq_cmd_details *cmd_details)
1322 {
1323 i40e_status status;
1324 struct i40e_aq_desc desc;
1325 struct i40e_aqc_clear_pxe *cmd =
1326 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1327
1328 i40e_fill_default_direct_cmd_desc(&desc,
1329 i40e_aqc_opc_clear_pxe_mode);
1330
1331 cmd->rx_cnt = 0x2;
1332
1333 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1334
1335 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1336
1337 return status;
1338 }
1339
1340 /**
1341 * i40e_aq_set_link_restart_an
1342 * @hw: pointer to the hw struct
1343 * @enable_link: if true: enable link, if false: disable link
1344 * @cmd_details: pointer to command details structure or NULL
1345 *
1346 * Sets up the link and restarts the Auto-Negotiation over the link.
1347 **/
1348 i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1349 bool enable_link,
1350 struct i40e_asq_cmd_details *cmd_details)
1351 {
1352 struct i40e_aq_desc desc;
1353 struct i40e_aqc_set_link_restart_an *cmd =
1354 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1355 i40e_status status;
1356
1357 i40e_fill_default_direct_cmd_desc(&desc,
1358 i40e_aqc_opc_set_link_restart_an);
1359
1360 cmd->command = I40E_AQ_PHY_RESTART_AN;
1361 if (enable_link)
1362 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1363 else
1364 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1365
1366 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1367
1368 return status;
1369 }
1370
1371 /**
1372 * i40e_aq_get_link_info
1373 * @hw: pointer to the hw struct
1374 * @enable_lse: enable/disable LinkStatusEvent reporting
1375 * @link: pointer to link status structure - optional
1376 * @cmd_details: pointer to command details structure or NULL
1377 *
1378 * Returns the link status of the adapter.
1379 **/
1380 i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1381 bool enable_lse, struct i40e_link_status *link,
1382 struct i40e_asq_cmd_details *cmd_details)
1383 {
1384 struct i40e_aq_desc desc;
1385 struct i40e_aqc_get_link_status *resp =
1386 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1387 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1388 i40e_status status;
1389 bool tx_pause, rx_pause;
1390 u16 command_flags;
1391
1392 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1393
1394 if (enable_lse)
1395 command_flags = I40E_AQ_LSE_ENABLE;
1396 else
1397 command_flags = I40E_AQ_LSE_DISABLE;
1398 resp->command_flags = cpu_to_le16(command_flags);
1399
1400 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1401
1402 if (status)
1403 goto aq_get_link_info_exit;
1404
1405 /* save off old link status information */
1406 hw->phy.link_info_old = *hw_link_info;
1407
1408 /* update link status */
1409 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1410 hw->phy.media_type = i40e_get_media_type(hw);
1411 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1412 hw_link_info->link_info = resp->link_info;
1413 hw_link_info->an_info = resp->an_info;
1414 hw_link_info->ext_info = resp->ext_info;
1415 hw_link_info->loopback = resp->loopback;
1416 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1417 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1418
1419 /* update fc info */
1420 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1421 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1422 if (tx_pause & rx_pause)
1423 hw->fc.current_mode = I40E_FC_FULL;
1424 else if (tx_pause)
1425 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1426 else if (rx_pause)
1427 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1428 else
1429 hw->fc.current_mode = I40E_FC_NONE;
1430
1431 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1432 hw_link_info->crc_enable = true;
1433 else
1434 hw_link_info->crc_enable = false;
1435
1436 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE))
1437 hw_link_info->lse_enable = true;
1438 else
1439 hw_link_info->lse_enable = false;
1440
1441 /* save link status information */
1442 if (link)
1443 *link = *hw_link_info;
1444
1445 /* flag cleared so helper functions don't call AQ again */
1446 hw->phy.get_link_info = false;
1447
1448 aq_get_link_info_exit:
1449 return status;
1450 }
1451
1452 /**
1453 * i40e_update_link_info
1454 * @hw: pointer to the hw struct
1455 * @enable_lse: enable/disable LinkStatusEvent reporting
1456 *
1457 * Returns the link status of the adapter
1458 **/
1459 i40e_status i40e_update_link_info(struct i40e_hw *hw, bool enable_lse)
1460 {
1461 struct i40e_aq_get_phy_abilities_resp abilities;
1462 i40e_status status;
1463
1464 status = i40e_aq_get_link_info(hw, enable_lse, NULL, NULL);
1465 if (status)
1466 return status;
1467
1468 status = i40e_aq_get_phy_capabilities(hw, false, false,
1469 &abilities, NULL);
1470 if (status)
1471 return status;
1472
1473 if (abilities.abilities & I40E_AQ_PHY_AN_ENABLED)
1474 hw->phy.link_info.an_enabled = true;
1475 else
1476 hw->phy.link_info.an_enabled = false;
1477
1478 return status;
1479 }
1480
1481 /**
1482 * i40e_aq_set_phy_int_mask
1483 * @hw: pointer to the hw struct
1484 * @mask: interrupt mask to be set
1485 * @cmd_details: pointer to command details structure or NULL
1486 *
1487 * Set link interrupt mask.
1488 **/
1489 i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1490 u16 mask,
1491 struct i40e_asq_cmd_details *cmd_details)
1492 {
1493 struct i40e_aq_desc desc;
1494 struct i40e_aqc_set_phy_int_mask *cmd =
1495 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1496 i40e_status status;
1497
1498 i40e_fill_default_direct_cmd_desc(&desc,
1499 i40e_aqc_opc_set_phy_int_mask);
1500
1501 cmd->event_mask = cpu_to_le16(mask);
1502
1503 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1504
1505 return status;
1506 }
1507
1508 /**
1509 * i40e_aq_add_vsi
1510 * @hw: pointer to the hw struct
1511 * @vsi_ctx: pointer to a vsi context struct
1512 * @cmd_details: pointer to command details structure or NULL
1513 *
1514 * Add a VSI context to the hardware.
1515 **/
1516 i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1517 struct i40e_vsi_context *vsi_ctx,
1518 struct i40e_asq_cmd_details *cmd_details)
1519 {
1520 struct i40e_aq_desc desc;
1521 struct i40e_aqc_add_get_update_vsi *cmd =
1522 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1523 struct i40e_aqc_add_get_update_vsi_completion *resp =
1524 (struct i40e_aqc_add_get_update_vsi_completion *)
1525 &desc.params.raw;
1526 i40e_status status;
1527
1528 i40e_fill_default_direct_cmd_desc(&desc,
1529 i40e_aqc_opc_add_vsi);
1530
1531 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1532 cmd->connection_type = vsi_ctx->connection_type;
1533 cmd->vf_id = vsi_ctx->vf_num;
1534 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1535
1536 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1537
1538 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1539 sizeof(vsi_ctx->info), cmd_details);
1540
1541 if (status)
1542 goto aq_add_vsi_exit;
1543
1544 vsi_ctx->seid = le16_to_cpu(resp->seid);
1545 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1546 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1547 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1548
1549 aq_add_vsi_exit:
1550 return status;
1551 }
1552
1553 /**
1554 * i40e_aq_set_vsi_unicast_promiscuous
1555 * @hw: pointer to the hw struct
1556 * @seid: vsi number
1557 * @set: set unicast promiscuous enable/disable
1558 * @cmd_details: pointer to command details structure or NULL
1559 **/
1560 i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
1561 u16 seid, bool set,
1562 struct i40e_asq_cmd_details *cmd_details)
1563 {
1564 struct i40e_aq_desc desc;
1565 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1566 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1567 i40e_status status;
1568 u16 flags = 0;
1569
1570 i40e_fill_default_direct_cmd_desc(&desc,
1571 i40e_aqc_opc_set_vsi_promiscuous_modes);
1572
1573 if (set)
1574 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1575
1576 cmd->promiscuous_flags = cpu_to_le16(flags);
1577
1578 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1579
1580 cmd->seid = cpu_to_le16(seid);
1581 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1582
1583 return status;
1584 }
1585
1586 /**
1587 * i40e_aq_set_vsi_multicast_promiscuous
1588 * @hw: pointer to the hw struct
1589 * @seid: vsi number
1590 * @set: set multicast promiscuous enable/disable
1591 * @cmd_details: pointer to command details structure or NULL
1592 **/
1593 i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1594 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1595 {
1596 struct i40e_aq_desc desc;
1597 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1598 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1599 i40e_status status;
1600 u16 flags = 0;
1601
1602 i40e_fill_default_direct_cmd_desc(&desc,
1603 i40e_aqc_opc_set_vsi_promiscuous_modes);
1604
1605 if (set)
1606 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1607
1608 cmd->promiscuous_flags = cpu_to_le16(flags);
1609
1610 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1611
1612 cmd->seid = cpu_to_le16(seid);
1613 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1614
1615 return status;
1616 }
1617
1618 /**
1619 * i40e_aq_set_vsi_broadcast
1620 * @hw: pointer to the hw struct
1621 * @seid: vsi number
1622 * @set_filter: true to set filter, false to clear filter
1623 * @cmd_details: pointer to command details structure or NULL
1624 *
1625 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1626 **/
1627 i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
1628 u16 seid, bool set_filter,
1629 struct i40e_asq_cmd_details *cmd_details)
1630 {
1631 struct i40e_aq_desc desc;
1632 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1633 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1634 i40e_status status;
1635
1636 i40e_fill_default_direct_cmd_desc(&desc,
1637 i40e_aqc_opc_set_vsi_promiscuous_modes);
1638
1639 if (set_filter)
1640 cmd->promiscuous_flags
1641 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1642 else
1643 cmd->promiscuous_flags
1644 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1645
1646 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1647 cmd->seid = cpu_to_le16(seid);
1648 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1649
1650 return status;
1651 }
1652
1653 /**
1654 * i40e_get_vsi_params - get VSI configuration info
1655 * @hw: pointer to the hw struct
1656 * @vsi_ctx: pointer to a vsi context struct
1657 * @cmd_details: pointer to command details structure or NULL
1658 **/
1659 i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
1660 struct i40e_vsi_context *vsi_ctx,
1661 struct i40e_asq_cmd_details *cmd_details)
1662 {
1663 struct i40e_aq_desc desc;
1664 struct i40e_aqc_add_get_update_vsi *cmd =
1665 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1666 struct i40e_aqc_add_get_update_vsi_completion *resp =
1667 (struct i40e_aqc_add_get_update_vsi_completion *)
1668 &desc.params.raw;
1669 i40e_status status;
1670
1671 i40e_fill_default_direct_cmd_desc(&desc,
1672 i40e_aqc_opc_get_vsi_parameters);
1673
1674 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
1675
1676 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1677
1678 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1679 sizeof(vsi_ctx->info), NULL);
1680
1681 if (status)
1682 goto aq_get_vsi_params_exit;
1683
1684 vsi_ctx->seid = le16_to_cpu(resp->seid);
1685 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1686 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1687 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1688
1689 aq_get_vsi_params_exit:
1690 return status;
1691 }
1692
1693 /**
1694 * i40e_aq_update_vsi_params
1695 * @hw: pointer to the hw struct
1696 * @vsi_ctx: pointer to a vsi context struct
1697 * @cmd_details: pointer to command details structure or NULL
1698 *
1699 * Update a VSI context.
1700 **/
1701 i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
1702 struct i40e_vsi_context *vsi_ctx,
1703 struct i40e_asq_cmd_details *cmd_details)
1704 {
1705 struct i40e_aq_desc desc;
1706 struct i40e_aqc_add_get_update_vsi *cmd =
1707 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1708 i40e_status status;
1709
1710 i40e_fill_default_direct_cmd_desc(&desc,
1711 i40e_aqc_opc_update_vsi_parameters);
1712 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
1713
1714 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1715
1716 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1717 sizeof(vsi_ctx->info), cmd_details);
1718
1719 return status;
1720 }
1721
1722 /**
1723 * i40e_aq_get_switch_config
1724 * @hw: pointer to the hardware structure
1725 * @buf: pointer to the result buffer
1726 * @buf_size: length of input buffer
1727 * @start_seid: seid to start for the report, 0 == beginning
1728 * @cmd_details: pointer to command details structure or NULL
1729 *
1730 * Fill the buf with switch configuration returned from AdminQ command
1731 **/
1732 i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
1733 struct i40e_aqc_get_switch_config_resp *buf,
1734 u16 buf_size, u16 *start_seid,
1735 struct i40e_asq_cmd_details *cmd_details)
1736 {
1737 struct i40e_aq_desc desc;
1738 struct i40e_aqc_switch_seid *scfg =
1739 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1740 i40e_status status;
1741
1742 i40e_fill_default_direct_cmd_desc(&desc,
1743 i40e_aqc_opc_get_switch_config);
1744 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1745 if (buf_size > I40E_AQ_LARGE_BUF)
1746 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1747 scfg->seid = cpu_to_le16(*start_seid);
1748
1749 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
1750 *start_seid = le16_to_cpu(scfg->seid);
1751
1752 return status;
1753 }
1754
1755 /**
1756 * i40e_aq_get_firmware_version
1757 * @hw: pointer to the hw struct
1758 * @fw_major_version: firmware major version
1759 * @fw_minor_version: firmware minor version
1760 * @api_major_version: major queue version
1761 * @api_minor_version: minor queue version
1762 * @cmd_details: pointer to command details structure or NULL
1763 *
1764 * Get the firmware version from the admin queue commands
1765 **/
1766 i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
1767 u16 *fw_major_version, u16 *fw_minor_version,
1768 u16 *api_major_version, u16 *api_minor_version,
1769 struct i40e_asq_cmd_details *cmd_details)
1770 {
1771 struct i40e_aq_desc desc;
1772 struct i40e_aqc_get_version *resp =
1773 (struct i40e_aqc_get_version *)&desc.params.raw;
1774 i40e_status status;
1775
1776 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
1777
1778 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1779
1780 if (!status) {
1781 if (fw_major_version != NULL)
1782 *fw_major_version = le16_to_cpu(resp->fw_major);
1783 if (fw_minor_version != NULL)
1784 *fw_minor_version = le16_to_cpu(resp->fw_minor);
1785 if (api_major_version != NULL)
1786 *api_major_version = le16_to_cpu(resp->api_major);
1787 if (api_minor_version != NULL)
1788 *api_minor_version = le16_to_cpu(resp->api_minor);
1789 }
1790
1791 return status;
1792 }
1793
1794 /**
1795 * i40e_aq_send_driver_version
1796 * @hw: pointer to the hw struct
1797 * @dv: driver's major, minor version
1798 * @cmd_details: pointer to command details structure or NULL
1799 *
1800 * Send the driver version to the firmware
1801 **/
1802 i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
1803 struct i40e_driver_version *dv,
1804 struct i40e_asq_cmd_details *cmd_details)
1805 {
1806 struct i40e_aq_desc desc;
1807 struct i40e_aqc_driver_version *cmd =
1808 (struct i40e_aqc_driver_version *)&desc.params.raw;
1809 i40e_status status;
1810 u16 len;
1811
1812 if (dv == NULL)
1813 return I40E_ERR_PARAM;
1814
1815 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
1816
1817 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_SI);
1818 cmd->driver_major_ver = dv->major_version;
1819 cmd->driver_minor_ver = dv->minor_version;
1820 cmd->driver_build_ver = dv->build_version;
1821 cmd->driver_subbuild_ver = dv->subbuild_version;
1822
1823 len = 0;
1824 while (len < sizeof(dv->driver_string) &&
1825 (dv->driver_string[len] < 0x80) &&
1826 dv->driver_string[len])
1827 len++;
1828 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
1829 len, cmd_details);
1830
1831 return status;
1832 }
1833
1834 /**
1835 * i40e_get_link_status - get status of the HW network link
1836 * @hw: pointer to the hw struct
1837 *
1838 * Returns true if link is up, false if link is down.
1839 *
1840 * Side effect: LinkStatusEvent reporting becomes enabled
1841 **/
1842 bool i40e_get_link_status(struct i40e_hw *hw)
1843 {
1844 i40e_status status = 0;
1845 bool link_status = false;
1846
1847 if (hw->phy.get_link_info) {
1848 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1849
1850 if (status)
1851 goto i40e_get_link_status_exit;
1852 }
1853
1854 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
1855
1856 i40e_get_link_status_exit:
1857 return link_status;
1858 }
1859
1860 /**
1861 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
1862 * @hw: pointer to the hw struct
1863 * @uplink_seid: the MAC or other gizmo SEID
1864 * @downlink_seid: the VSI SEID
1865 * @enabled_tc: bitmap of TCs to be enabled
1866 * @default_port: true for default port VSI, false for control port
1867 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
1868 * @veb_seid: pointer to where to put the resulting VEB SEID
1869 * @cmd_details: pointer to command details structure or NULL
1870 *
1871 * This asks the FW to add a VEB between the uplink and downlink
1872 * elements. If the uplink SEID is 0, this will be a floating VEB.
1873 **/
1874 i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
1875 u16 downlink_seid, u8 enabled_tc,
1876 bool default_port, bool enable_l2_filtering,
1877 u16 *veb_seid,
1878 struct i40e_asq_cmd_details *cmd_details)
1879 {
1880 struct i40e_aq_desc desc;
1881 struct i40e_aqc_add_veb *cmd =
1882 (struct i40e_aqc_add_veb *)&desc.params.raw;
1883 struct i40e_aqc_add_veb_completion *resp =
1884 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
1885 i40e_status status;
1886 u16 veb_flags = 0;
1887
1888 /* SEIDs need to either both be set or both be 0 for floating VEB */
1889 if (!!uplink_seid != !!downlink_seid)
1890 return I40E_ERR_PARAM;
1891
1892 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
1893
1894 cmd->uplink_seid = cpu_to_le16(uplink_seid);
1895 cmd->downlink_seid = cpu_to_le16(downlink_seid);
1896 cmd->enable_tcs = enabled_tc;
1897 if (!uplink_seid)
1898 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
1899 if (default_port)
1900 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
1901 else
1902 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
1903
1904 if (enable_l2_filtering)
1905 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
1906
1907 cmd->veb_flags = cpu_to_le16(veb_flags);
1908
1909 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1910
1911 if (!status && veb_seid)
1912 *veb_seid = le16_to_cpu(resp->veb_seid);
1913
1914 return status;
1915 }
1916
1917 /**
1918 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
1919 * @hw: pointer to the hw struct
1920 * @veb_seid: the SEID of the VEB to query
1921 * @switch_id: the uplink switch id
1922 * @floating: set to true if the VEB is floating
1923 * @statistic_index: index of the stats counter block for this VEB
1924 * @vebs_used: number of VEB's used by function
1925 * @vebs_free: total VEB's not reserved by any function
1926 * @cmd_details: pointer to command details structure or NULL
1927 *
1928 * This retrieves the parameters for a particular VEB, specified by
1929 * uplink_seid, and returns them to the caller.
1930 **/
1931 i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
1932 u16 veb_seid, u16 *switch_id,
1933 bool *floating, u16 *statistic_index,
1934 u16 *vebs_used, u16 *vebs_free,
1935 struct i40e_asq_cmd_details *cmd_details)
1936 {
1937 struct i40e_aq_desc desc;
1938 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
1939 (struct i40e_aqc_get_veb_parameters_completion *)
1940 &desc.params.raw;
1941 i40e_status status;
1942
1943 if (veb_seid == 0)
1944 return I40E_ERR_PARAM;
1945
1946 i40e_fill_default_direct_cmd_desc(&desc,
1947 i40e_aqc_opc_get_veb_parameters);
1948 cmd_resp->seid = cpu_to_le16(veb_seid);
1949
1950 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1951 if (status)
1952 goto get_veb_exit;
1953
1954 if (switch_id)
1955 *switch_id = le16_to_cpu(cmd_resp->switch_id);
1956 if (statistic_index)
1957 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
1958 if (vebs_used)
1959 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
1960 if (vebs_free)
1961 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
1962 if (floating) {
1963 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
1964 if (flags & I40E_AQC_ADD_VEB_FLOATING)
1965 *floating = true;
1966 else
1967 *floating = false;
1968 }
1969
1970 get_veb_exit:
1971 return status;
1972 }
1973
1974 /**
1975 * i40e_aq_add_macvlan
1976 * @hw: pointer to the hw struct
1977 * @seid: VSI for the mac address
1978 * @mv_list: list of macvlans to be added
1979 * @count: length of the list
1980 * @cmd_details: pointer to command details structure or NULL
1981 *
1982 * Add MAC/VLAN addresses to the HW filtering
1983 **/
1984 i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
1985 struct i40e_aqc_add_macvlan_element_data *mv_list,
1986 u16 count, struct i40e_asq_cmd_details *cmd_details)
1987 {
1988 struct i40e_aq_desc desc;
1989 struct i40e_aqc_macvlan *cmd =
1990 (struct i40e_aqc_macvlan *)&desc.params.raw;
1991 i40e_status status;
1992 u16 buf_size;
1993
1994 if (count == 0 || !mv_list || !hw)
1995 return I40E_ERR_PARAM;
1996
1997 buf_size = count * sizeof(struct i40e_aqc_add_macvlan_element_data);
1998
1999 /* prep the rest of the request */
2000 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2001 cmd->num_addresses = cpu_to_le16(count);
2002 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2003 cmd->seid[1] = 0;
2004 cmd->seid[2] = 0;
2005
2006 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2007 if (buf_size > I40E_AQ_LARGE_BUF)
2008 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2009
2010 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2011 cmd_details);
2012
2013 return status;
2014 }
2015
2016 /**
2017 * i40e_aq_remove_macvlan
2018 * @hw: pointer to the hw struct
2019 * @seid: VSI for the mac address
2020 * @mv_list: list of macvlans to be removed
2021 * @count: length of the list
2022 * @cmd_details: pointer to command details structure or NULL
2023 *
2024 * Remove MAC/VLAN addresses from the HW filtering
2025 **/
2026 i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2027 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2028 u16 count, struct i40e_asq_cmd_details *cmd_details)
2029 {
2030 struct i40e_aq_desc desc;
2031 struct i40e_aqc_macvlan *cmd =
2032 (struct i40e_aqc_macvlan *)&desc.params.raw;
2033 i40e_status status;
2034 u16 buf_size;
2035
2036 if (count == 0 || !mv_list || !hw)
2037 return I40E_ERR_PARAM;
2038
2039 buf_size = count * sizeof(struct i40e_aqc_remove_macvlan_element_data);
2040
2041 /* prep the rest of the request */
2042 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2043 cmd->num_addresses = cpu_to_le16(count);
2044 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2045 cmd->seid[1] = 0;
2046 cmd->seid[2] = 0;
2047
2048 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2049 if (buf_size > I40E_AQ_LARGE_BUF)
2050 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2051
2052 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2053 cmd_details);
2054
2055 return status;
2056 }
2057
2058 /**
2059 * i40e_aq_send_msg_to_vf
2060 * @hw: pointer to the hardware structure
2061 * @vfid: vf id to send msg
2062 * @v_opcode: opcodes for VF-PF communication
2063 * @v_retval: return error code
2064 * @msg: pointer to the msg buffer
2065 * @msglen: msg length
2066 * @cmd_details: pointer to command details
2067 *
2068 * send msg to vf
2069 **/
2070 i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2071 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2072 struct i40e_asq_cmd_details *cmd_details)
2073 {
2074 struct i40e_aq_desc desc;
2075 struct i40e_aqc_pf_vf_message *cmd =
2076 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2077 i40e_status status;
2078
2079 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2080 cmd->id = cpu_to_le32(vfid);
2081 desc.cookie_high = cpu_to_le32(v_opcode);
2082 desc.cookie_low = cpu_to_le32(v_retval);
2083 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
2084 if (msglen) {
2085 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2086 I40E_AQ_FLAG_RD));
2087 if (msglen > I40E_AQ_LARGE_BUF)
2088 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2089 desc.datalen = cpu_to_le16(msglen);
2090 }
2091 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2092
2093 return status;
2094 }
2095
2096 /**
2097 * i40e_aq_debug_read_register
2098 * @hw: pointer to the hw struct
2099 * @reg_addr: register address
2100 * @reg_val: register value
2101 * @cmd_details: pointer to command details structure or NULL
2102 *
2103 * Read the register using the admin queue commands
2104 **/
2105 i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw,
2106 u32 reg_addr, u64 *reg_val,
2107 struct i40e_asq_cmd_details *cmd_details)
2108 {
2109 struct i40e_aq_desc desc;
2110 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2111 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2112 i40e_status status;
2113
2114 if (reg_val == NULL)
2115 return I40E_ERR_PARAM;
2116
2117 i40e_fill_default_direct_cmd_desc(&desc,
2118 i40e_aqc_opc_debug_read_reg);
2119
2120 cmd_resp->address = cpu_to_le32(reg_addr);
2121
2122 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2123
2124 if (!status) {
2125 *reg_val = ((u64)cmd_resp->value_high << 32) |
2126 (u64)cmd_resp->value_low;
2127 *reg_val = le64_to_cpu(*reg_val);
2128 }
2129
2130 return status;
2131 }
2132
2133 /**
2134 * i40e_aq_debug_write_register
2135 * @hw: pointer to the hw struct
2136 * @reg_addr: register address
2137 * @reg_val: register value
2138 * @cmd_details: pointer to command details structure or NULL
2139 *
2140 * Write to a register using the admin queue commands
2141 **/
2142 i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw,
2143 u32 reg_addr, u64 reg_val,
2144 struct i40e_asq_cmd_details *cmd_details)
2145 {
2146 struct i40e_aq_desc desc;
2147 struct i40e_aqc_debug_reg_read_write *cmd =
2148 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2149 i40e_status status;
2150
2151 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2152
2153 cmd->address = cpu_to_le32(reg_addr);
2154 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));
2155 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));
2156
2157 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2158
2159 return status;
2160 }
2161
2162 /**
2163 * i40e_aq_set_hmc_resource_profile
2164 * @hw: pointer to the hw struct
2165 * @profile: type of profile the HMC is to be set as
2166 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2167 * @cmd_details: pointer to command details structure or NULL
2168 *
2169 * set the HMC profile of the device.
2170 **/
2171 i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2172 enum i40e_aq_hmc_profile profile,
2173 u8 pe_vf_enabled_count,
2174 struct i40e_asq_cmd_details *cmd_details)
2175 {
2176 struct i40e_aq_desc desc;
2177 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2178 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2179 i40e_status status;
2180
2181 i40e_fill_default_direct_cmd_desc(&desc,
2182 i40e_aqc_opc_set_hmc_resource_profile);
2183
2184 cmd->pm_profile = (u8)profile;
2185 cmd->pe_vf_enabled = pe_vf_enabled_count;
2186
2187 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2188
2189 return status;
2190 }
2191
2192 /**
2193 * i40e_aq_request_resource
2194 * @hw: pointer to the hw struct
2195 * @resource: resource id
2196 * @access: access type
2197 * @sdp_number: resource number
2198 * @timeout: the maximum time in ms that the driver may hold the resource
2199 * @cmd_details: pointer to command details structure or NULL
2200 *
2201 * requests common resource using the admin queue commands
2202 **/
2203 i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
2204 enum i40e_aq_resources_ids resource,
2205 enum i40e_aq_resource_access_type access,
2206 u8 sdp_number, u64 *timeout,
2207 struct i40e_asq_cmd_details *cmd_details)
2208 {
2209 struct i40e_aq_desc desc;
2210 struct i40e_aqc_request_resource *cmd_resp =
2211 (struct i40e_aqc_request_resource *)&desc.params.raw;
2212 i40e_status status;
2213
2214 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2215
2216 cmd_resp->resource_id = cpu_to_le16(resource);
2217 cmd_resp->access_type = cpu_to_le16(access);
2218 cmd_resp->resource_number = cpu_to_le32(sdp_number);
2219
2220 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2221 /* The completion specifies the maximum time in ms that the driver
2222 * may hold the resource in the Timeout field.
2223 * If the resource is held by someone else, the command completes with
2224 * busy return value and the timeout field indicates the maximum time
2225 * the current owner of the resource has to free it.
2226 */
2227 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2228 *timeout = le32_to_cpu(cmd_resp->timeout);
2229
2230 return status;
2231 }
2232
2233 /**
2234 * i40e_aq_release_resource
2235 * @hw: pointer to the hw struct
2236 * @resource: resource id
2237 * @sdp_number: resource number
2238 * @cmd_details: pointer to command details structure or NULL
2239 *
2240 * release common resource using the admin queue commands
2241 **/
2242 i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
2243 enum i40e_aq_resources_ids resource,
2244 u8 sdp_number,
2245 struct i40e_asq_cmd_details *cmd_details)
2246 {
2247 struct i40e_aq_desc desc;
2248 struct i40e_aqc_request_resource *cmd =
2249 (struct i40e_aqc_request_resource *)&desc.params.raw;
2250 i40e_status status;
2251
2252 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2253
2254 cmd->resource_id = cpu_to_le16(resource);
2255 cmd->resource_number = cpu_to_le32(sdp_number);
2256
2257 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2258
2259 return status;
2260 }
2261
2262 /**
2263 * i40e_aq_read_nvm
2264 * @hw: pointer to the hw struct
2265 * @module_pointer: module pointer location in words from the NVM beginning
2266 * @offset: byte offset from the module beginning
2267 * @length: length of the section to be read (in bytes from the offset)
2268 * @data: command buffer (size [bytes] = length)
2269 * @last_command: tells if this is the last command in a series
2270 * @cmd_details: pointer to command details structure or NULL
2271 *
2272 * Read the NVM using the admin queue commands
2273 **/
2274 i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2275 u32 offset, u16 length, void *data,
2276 bool last_command,
2277 struct i40e_asq_cmd_details *cmd_details)
2278 {
2279 struct i40e_aq_desc desc;
2280 struct i40e_aqc_nvm_update *cmd =
2281 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2282 i40e_status status;
2283
2284 /* In offset the highest byte must be zeroed. */
2285 if (offset & 0xFF000000) {
2286 status = I40E_ERR_PARAM;
2287 goto i40e_aq_read_nvm_exit;
2288 }
2289
2290 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2291
2292 /* If this is the last command in a series, set the proper flag. */
2293 if (last_command)
2294 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2295 cmd->module_pointer = module_pointer;
2296 cmd->offset = cpu_to_le32(offset);
2297 cmd->length = cpu_to_le16(length);
2298
2299 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2300 if (length > I40E_AQ_LARGE_BUF)
2301 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2302
2303 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2304
2305 i40e_aq_read_nvm_exit:
2306 return status;
2307 }
2308
2309 /**
2310 * i40e_aq_erase_nvm
2311 * @hw: pointer to the hw struct
2312 * @module_pointer: module pointer location in words from the NVM beginning
2313 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2314 * @length: length of the section to be erased (expressed in 4 KB)
2315 * @last_command: tells if this is the last command in a series
2316 * @cmd_details: pointer to command details structure or NULL
2317 *
2318 * Erase the NVM sector using the admin queue commands
2319 **/
2320 i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2321 u32 offset, u16 length, bool last_command,
2322 struct i40e_asq_cmd_details *cmd_details)
2323 {
2324 struct i40e_aq_desc desc;
2325 struct i40e_aqc_nvm_update *cmd =
2326 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2327 i40e_status status;
2328
2329 /* In offset the highest byte must be zeroed. */
2330 if (offset & 0xFF000000) {
2331 status = I40E_ERR_PARAM;
2332 goto i40e_aq_erase_nvm_exit;
2333 }
2334
2335 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2336
2337 /* If this is the last command in a series, set the proper flag. */
2338 if (last_command)
2339 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2340 cmd->module_pointer = module_pointer;
2341 cmd->offset = cpu_to_le32(offset);
2342 cmd->length = cpu_to_le16(length);
2343
2344 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2345
2346 i40e_aq_erase_nvm_exit:
2347 return status;
2348 }
2349
2350 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
2351 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
2352 #define I40E_DEV_FUNC_CAP_NPAR 0x03
2353 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04
2354 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
2355 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
2356 #define I40E_DEV_FUNC_CAP_VF 0x13
2357 #define I40E_DEV_FUNC_CAP_VMDQ 0x14
2358 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
2359 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
2360 #define I40E_DEV_FUNC_CAP_VSI 0x17
2361 #define I40E_DEV_FUNC_CAP_DCB 0x18
2362 #define I40E_DEV_FUNC_CAP_FCOE 0x21
2363 #define I40E_DEV_FUNC_CAP_RSS 0x40
2364 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
2365 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
2366 #define I40E_DEV_FUNC_CAP_MSIX 0x43
2367 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
2368 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
2369 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
2370 #define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
2371 #define I40E_DEV_FUNC_CAP_CEM 0xF2
2372 #define I40E_DEV_FUNC_CAP_IWARP 0x51
2373 #define I40E_DEV_FUNC_CAP_LED 0x61
2374 #define I40E_DEV_FUNC_CAP_SDP 0x62
2375 #define I40E_DEV_FUNC_CAP_MDIO 0x63
2376
2377 /**
2378 * i40e_parse_discover_capabilities
2379 * @hw: pointer to the hw struct
2380 * @buff: pointer to a buffer containing device/function capability records
2381 * @cap_count: number of capability records in the list
2382 * @list_type_opc: type of capabilities list to parse
2383 *
2384 * Parse the device/function capabilities list.
2385 **/
2386 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2387 u32 cap_count,
2388 enum i40e_admin_queue_opc list_type_opc)
2389 {
2390 struct i40e_aqc_list_capabilities_element_resp *cap;
2391 u32 valid_functions, num_functions;
2392 u32 number, logical_id, phys_id;
2393 struct i40e_hw_capabilities *p;
2394 u32 i = 0;
2395 u16 id;
2396
2397 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2398
2399 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
2400 p = &hw->dev_caps;
2401 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
2402 p = &hw->func_caps;
2403 else
2404 return;
2405
2406 for (i = 0; i < cap_count; i++, cap++) {
2407 id = le16_to_cpu(cap->id);
2408 number = le32_to_cpu(cap->number);
2409 logical_id = le32_to_cpu(cap->logical_id);
2410 phys_id = le32_to_cpu(cap->phys_id);
2411
2412 switch (id) {
2413 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
2414 p->switch_mode = number;
2415 break;
2416 case I40E_DEV_FUNC_CAP_MGMT_MODE:
2417 p->management_mode = number;
2418 break;
2419 case I40E_DEV_FUNC_CAP_NPAR:
2420 p->npar_enable = number;
2421 break;
2422 case I40E_DEV_FUNC_CAP_OS2BMC:
2423 p->os2bmc = number;
2424 break;
2425 case I40E_DEV_FUNC_CAP_VALID_FUNC:
2426 p->valid_functions = number;
2427 break;
2428 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
2429 if (number == 1)
2430 p->sr_iov_1_1 = true;
2431 break;
2432 case I40E_DEV_FUNC_CAP_VF:
2433 p->num_vfs = number;
2434 p->vf_base_id = logical_id;
2435 break;
2436 case I40E_DEV_FUNC_CAP_VMDQ:
2437 if (number == 1)
2438 p->vmdq = true;
2439 break;
2440 case I40E_DEV_FUNC_CAP_802_1_QBG:
2441 if (number == 1)
2442 p->evb_802_1_qbg = true;
2443 break;
2444 case I40E_DEV_FUNC_CAP_802_1_QBH:
2445 if (number == 1)
2446 p->evb_802_1_qbh = true;
2447 break;
2448 case I40E_DEV_FUNC_CAP_VSI:
2449 p->num_vsis = number;
2450 break;
2451 case I40E_DEV_FUNC_CAP_DCB:
2452 if (number == 1) {
2453 p->dcb = true;
2454 p->enabled_tcmap = logical_id;
2455 p->maxtc = phys_id;
2456 }
2457 break;
2458 case I40E_DEV_FUNC_CAP_FCOE:
2459 if (number == 1)
2460 p->fcoe = true;
2461 break;
2462 case I40E_DEV_FUNC_CAP_RSS:
2463 p->rss = true;
2464 p->rss_table_size = number;
2465 p->rss_table_entry_width = logical_id;
2466 break;
2467 case I40E_DEV_FUNC_CAP_RX_QUEUES:
2468 p->num_rx_qp = number;
2469 p->base_queue = phys_id;
2470 break;
2471 case I40E_DEV_FUNC_CAP_TX_QUEUES:
2472 p->num_tx_qp = number;
2473 p->base_queue = phys_id;
2474 break;
2475 case I40E_DEV_FUNC_CAP_MSIX:
2476 p->num_msix_vectors = number;
2477 break;
2478 case I40E_DEV_FUNC_CAP_MSIX_VF:
2479 p->num_msix_vectors_vf = number;
2480 break;
2481 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
2482 if (number == 1)
2483 p->mfp_mode_1 = true;
2484 break;
2485 case I40E_DEV_FUNC_CAP_CEM:
2486 if (number == 1)
2487 p->mgmt_cem = true;
2488 break;
2489 case I40E_DEV_FUNC_CAP_IWARP:
2490 if (number == 1)
2491 p->iwarp = true;
2492 break;
2493 case I40E_DEV_FUNC_CAP_LED:
2494 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2495 p->led[phys_id] = true;
2496 break;
2497 case I40E_DEV_FUNC_CAP_SDP:
2498 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2499 p->sdp[phys_id] = true;
2500 break;
2501 case I40E_DEV_FUNC_CAP_MDIO:
2502 if (number == 1) {
2503 p->mdio_port_num = phys_id;
2504 p->mdio_port_mode = logical_id;
2505 }
2506 break;
2507 case I40E_DEV_FUNC_CAP_IEEE_1588:
2508 if (number == 1)
2509 p->ieee_1588 = true;
2510 break;
2511 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
2512 p->fd = true;
2513 p->fd_filters_guaranteed = number;
2514 p->fd_filters_best_effort = logical_id;
2515 break;
2516 default:
2517 break;
2518 }
2519 }
2520
2521 /* Software override ensuring FCoE is disabled if npar or mfp
2522 * mode because it is not supported in these modes.
2523 */
2524 if (p->npar_enable || p->mfp_mode_1)
2525 p->fcoe = false;
2526
2527 /* count the enabled ports (aka the "not disabled" ports) */
2528 hw->num_ports = 0;
2529 for (i = 0; i < 4; i++) {
2530 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
2531 u64 port_cfg = 0;
2532
2533 /* use AQ read to get the physical register offset instead
2534 * of the port relative offset
2535 */
2536 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
2537 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
2538 hw->num_ports++;
2539 }
2540
2541 valid_functions = p->valid_functions;
2542 num_functions = 0;
2543 while (valid_functions) {
2544 if (valid_functions & 1)
2545 num_functions++;
2546 valid_functions >>= 1;
2547 }
2548
2549 /* partition id is 1-based, and functions are evenly spread
2550 * across the ports as partitions
2551 */
2552 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
2553 hw->num_partitions = num_functions / hw->num_ports;
2554
2555 /* additional HW specific goodies that might
2556 * someday be HW version specific
2557 */
2558 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
2559 }
2560
2561 /**
2562 * i40e_aq_discover_capabilities
2563 * @hw: pointer to the hw struct
2564 * @buff: a virtual buffer to hold the capabilities
2565 * @buff_size: Size of the virtual buffer
2566 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
2567 * @list_type_opc: capabilities type to discover - pass in the command opcode
2568 * @cmd_details: pointer to command details structure or NULL
2569 *
2570 * Get the device capabilities descriptions from the firmware
2571 **/
2572 i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
2573 void *buff, u16 buff_size, u16 *data_size,
2574 enum i40e_admin_queue_opc list_type_opc,
2575 struct i40e_asq_cmd_details *cmd_details)
2576 {
2577 struct i40e_aqc_list_capabilites *cmd;
2578 struct i40e_aq_desc desc;
2579 i40e_status status = 0;
2580
2581 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
2582
2583 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
2584 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
2585 status = I40E_ERR_PARAM;
2586 goto exit;
2587 }
2588
2589 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
2590
2591 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2592 if (buff_size > I40E_AQ_LARGE_BUF)
2593 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2594
2595 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2596 *data_size = le16_to_cpu(desc.datalen);
2597
2598 if (status)
2599 goto exit;
2600
2601 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
2602 list_type_opc);
2603
2604 exit:
2605 return status;
2606 }
2607
2608 /**
2609 * i40e_aq_update_nvm
2610 * @hw: pointer to the hw struct
2611 * @module_pointer: module pointer location in words from the NVM beginning
2612 * @offset: byte offset from the module beginning
2613 * @length: length of the section to be written (in bytes from the offset)
2614 * @data: command buffer (size [bytes] = length)
2615 * @last_command: tells if this is the last command in a series
2616 * @cmd_details: pointer to command details structure or NULL
2617 *
2618 * Update the NVM using the admin queue commands
2619 **/
2620 i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
2621 u32 offset, u16 length, void *data,
2622 bool last_command,
2623 struct i40e_asq_cmd_details *cmd_details)
2624 {
2625 struct i40e_aq_desc desc;
2626 struct i40e_aqc_nvm_update *cmd =
2627 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2628 i40e_status status;
2629
2630 /* In offset the highest byte must be zeroed. */
2631 if (offset & 0xFF000000) {
2632 status = I40E_ERR_PARAM;
2633 goto i40e_aq_update_nvm_exit;
2634 }
2635
2636 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
2637
2638 /* If this is the last command in a series, set the proper flag. */
2639 if (last_command)
2640 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2641 cmd->module_pointer = module_pointer;
2642 cmd->offset = cpu_to_le32(offset);
2643 cmd->length = cpu_to_le16(length);
2644
2645 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2646 if (length > I40E_AQ_LARGE_BUF)
2647 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2648
2649 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2650
2651 i40e_aq_update_nvm_exit:
2652 return status;
2653 }
2654
2655 /**
2656 * i40e_aq_get_lldp_mib
2657 * @hw: pointer to the hw struct
2658 * @bridge_type: type of bridge requested
2659 * @mib_type: Local, Remote or both Local and Remote MIBs
2660 * @buff: pointer to a user supplied buffer to store the MIB block
2661 * @buff_size: size of the buffer (in bytes)
2662 * @local_len : length of the returned Local LLDP MIB
2663 * @remote_len: length of the returned Remote LLDP MIB
2664 * @cmd_details: pointer to command details structure or NULL
2665 *
2666 * Requests the complete LLDP MIB (entire packet).
2667 **/
2668 i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
2669 u8 mib_type, void *buff, u16 buff_size,
2670 u16 *local_len, u16 *remote_len,
2671 struct i40e_asq_cmd_details *cmd_details)
2672 {
2673 struct i40e_aq_desc desc;
2674 struct i40e_aqc_lldp_get_mib *cmd =
2675 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2676 struct i40e_aqc_lldp_get_mib *resp =
2677 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2678 i40e_status status;
2679
2680 if (buff_size == 0 || !buff)
2681 return I40E_ERR_PARAM;
2682
2683 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
2684 /* Indirect Command */
2685 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2686
2687 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
2688 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
2689 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
2690
2691 desc.datalen = cpu_to_le16(buff_size);
2692
2693 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2694 if (buff_size > I40E_AQ_LARGE_BUF)
2695 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2696
2697 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2698 if (!status) {
2699 if (local_len != NULL)
2700 *local_len = le16_to_cpu(resp->local_len);
2701 if (remote_len != NULL)
2702 *remote_len = le16_to_cpu(resp->remote_len);
2703 }
2704
2705 return status;
2706 }
2707
2708 /**
2709 * i40e_aq_cfg_lldp_mib_change_event
2710 * @hw: pointer to the hw struct
2711 * @enable_update: Enable or Disable event posting
2712 * @cmd_details: pointer to command details structure or NULL
2713 *
2714 * Enable or Disable posting of an event on ARQ when LLDP MIB
2715 * associated with the interface changes
2716 **/
2717 i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
2718 bool enable_update,
2719 struct i40e_asq_cmd_details *cmd_details)
2720 {
2721 struct i40e_aq_desc desc;
2722 struct i40e_aqc_lldp_update_mib *cmd =
2723 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
2724 i40e_status status;
2725
2726 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
2727
2728 if (!enable_update)
2729 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
2730
2731 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2732
2733 return status;
2734 }
2735
2736 /**
2737 * i40e_aq_stop_lldp
2738 * @hw: pointer to the hw struct
2739 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
2740 * @cmd_details: pointer to command details structure or NULL
2741 *
2742 * Stop or Shutdown the embedded LLDP Agent
2743 **/
2744 i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
2745 struct i40e_asq_cmd_details *cmd_details)
2746 {
2747 struct i40e_aq_desc desc;
2748 struct i40e_aqc_lldp_stop *cmd =
2749 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
2750 i40e_status status;
2751
2752 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
2753
2754 if (shutdown_agent)
2755 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
2756
2757 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2758
2759 return status;
2760 }
2761
2762 /**
2763 * i40e_aq_start_lldp
2764 * @hw: pointer to the hw struct
2765 * @cmd_details: pointer to command details structure or NULL
2766 *
2767 * Start the embedded LLDP Agent on all ports.
2768 **/
2769 i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
2770 struct i40e_asq_cmd_details *cmd_details)
2771 {
2772 struct i40e_aq_desc desc;
2773 struct i40e_aqc_lldp_start *cmd =
2774 (struct i40e_aqc_lldp_start *)&desc.params.raw;
2775 i40e_status status;
2776
2777 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
2778
2779 cmd->command = I40E_AQ_LLDP_AGENT_START;
2780
2781 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2782
2783 return status;
2784 }
2785
2786 /**
2787 * i40e_aq_get_cee_dcb_config
2788 * @hw: pointer to the hw struct
2789 * @buff: response buffer that stores CEE operational configuration
2790 * @buff_size: size of the buffer passed
2791 * @cmd_details: pointer to command details structure or NULL
2792 *
2793 * Get CEE DCBX mode operational configuration from firmware
2794 **/
2795 i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
2796 void *buff, u16 buff_size,
2797 struct i40e_asq_cmd_details *cmd_details)
2798 {
2799 struct i40e_aq_desc desc;
2800 i40e_status status;
2801
2802 if (buff_size == 0 || !buff)
2803 return I40E_ERR_PARAM;
2804
2805 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
2806
2807 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2808 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
2809 cmd_details);
2810
2811 return status;
2812 }
2813
2814 /**
2815 * i40e_aq_add_udp_tunnel
2816 * @hw: pointer to the hw struct
2817 * @udp_port: the UDP port to add
2818 * @header_len: length of the tunneling header length in DWords
2819 * @protocol_index: protocol index type
2820 * @filter_index: pointer to filter index
2821 * @cmd_details: pointer to command details structure or NULL
2822 **/
2823 i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
2824 u16 udp_port, u8 protocol_index,
2825 u8 *filter_index,
2826 struct i40e_asq_cmd_details *cmd_details)
2827 {
2828 struct i40e_aq_desc desc;
2829 struct i40e_aqc_add_udp_tunnel *cmd =
2830 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
2831 struct i40e_aqc_del_udp_tunnel_completion *resp =
2832 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
2833 i40e_status status;
2834
2835 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
2836
2837 cmd->udp_port = cpu_to_le16(udp_port);
2838 cmd->protocol_type = protocol_index;
2839
2840 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2841
2842 if (!status)
2843 *filter_index = resp->index;
2844
2845 return status;
2846 }
2847
2848 /**
2849 * i40e_aq_del_udp_tunnel
2850 * @hw: pointer to the hw struct
2851 * @index: filter index
2852 * @cmd_details: pointer to command details structure or NULL
2853 **/
2854 i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
2855 struct i40e_asq_cmd_details *cmd_details)
2856 {
2857 struct i40e_aq_desc desc;
2858 struct i40e_aqc_remove_udp_tunnel *cmd =
2859 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
2860 i40e_status status;
2861
2862 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
2863
2864 cmd->index = index;
2865
2866 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2867
2868 return status;
2869 }
2870
2871 /**
2872 * i40e_aq_delete_element - Delete switch element
2873 * @hw: pointer to the hw struct
2874 * @seid: the SEID to delete from the switch
2875 * @cmd_details: pointer to command details structure or NULL
2876 *
2877 * This deletes a switch element from the switch.
2878 **/
2879 i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
2880 struct i40e_asq_cmd_details *cmd_details)
2881 {
2882 struct i40e_aq_desc desc;
2883 struct i40e_aqc_switch_seid *cmd =
2884 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2885 i40e_status status;
2886
2887 if (seid == 0)
2888 return I40E_ERR_PARAM;
2889
2890 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
2891
2892 cmd->seid = cpu_to_le16(seid);
2893
2894 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2895
2896 return status;
2897 }
2898
2899 /**
2900 * i40e_aq_dcb_updated - DCB Updated Command
2901 * @hw: pointer to the hw struct
2902 * @cmd_details: pointer to command details structure or NULL
2903 *
2904 * EMP will return when the shared RPB settings have been
2905 * recomputed and modified. The retval field in the descriptor
2906 * will be set to 0 when RPB is modified.
2907 **/
2908 i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
2909 struct i40e_asq_cmd_details *cmd_details)
2910 {
2911 struct i40e_aq_desc desc;
2912 i40e_status status;
2913
2914 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
2915
2916 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2917
2918 return status;
2919 }
2920
2921 /**
2922 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
2923 * @hw: pointer to the hw struct
2924 * @seid: seid for the physical port/switching component/vsi
2925 * @buff: Indirect buffer to hold data parameters and response
2926 * @buff_size: Indirect buffer size
2927 * @opcode: Tx scheduler AQ command opcode
2928 * @cmd_details: pointer to command details structure or NULL
2929 *
2930 * Generic command handler for Tx scheduler AQ commands
2931 **/
2932 static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
2933 void *buff, u16 buff_size,
2934 enum i40e_admin_queue_opc opcode,
2935 struct i40e_asq_cmd_details *cmd_details)
2936 {
2937 struct i40e_aq_desc desc;
2938 struct i40e_aqc_tx_sched_ind *cmd =
2939 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
2940 i40e_status status;
2941 bool cmd_param_flag = false;
2942
2943 switch (opcode) {
2944 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
2945 case i40e_aqc_opc_configure_vsi_tc_bw:
2946 case i40e_aqc_opc_enable_switching_comp_ets:
2947 case i40e_aqc_opc_modify_switching_comp_ets:
2948 case i40e_aqc_opc_disable_switching_comp_ets:
2949 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
2950 case i40e_aqc_opc_configure_switching_comp_bw_config:
2951 cmd_param_flag = true;
2952 break;
2953 case i40e_aqc_opc_query_vsi_bw_config:
2954 case i40e_aqc_opc_query_vsi_ets_sla_config:
2955 case i40e_aqc_opc_query_switching_comp_ets_config:
2956 case i40e_aqc_opc_query_port_ets_config:
2957 case i40e_aqc_opc_query_switching_comp_bw_config:
2958 cmd_param_flag = false;
2959 break;
2960 default:
2961 return I40E_ERR_PARAM;
2962 }
2963
2964 i40e_fill_default_direct_cmd_desc(&desc, opcode);
2965
2966 /* Indirect command */
2967 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2968 if (cmd_param_flag)
2969 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
2970 if (buff_size > I40E_AQ_LARGE_BUF)
2971 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2972
2973 desc.datalen = cpu_to_le16(buff_size);
2974
2975 cmd->vsi_seid = cpu_to_le16(seid);
2976
2977 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2978
2979 return status;
2980 }
2981
2982 /**
2983 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
2984 * @hw: pointer to the hw struct
2985 * @seid: VSI seid
2986 * @credit: BW limit credits (0 = disabled)
2987 * @max_credit: Max BW limit credits
2988 * @cmd_details: pointer to command details structure or NULL
2989 **/
2990 i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
2991 u16 seid, u16 credit, u8 max_credit,
2992 struct i40e_asq_cmd_details *cmd_details)
2993 {
2994 struct i40e_aq_desc desc;
2995 struct i40e_aqc_configure_vsi_bw_limit *cmd =
2996 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
2997 i40e_status status;
2998
2999 i40e_fill_default_direct_cmd_desc(&desc,
3000 i40e_aqc_opc_configure_vsi_bw_limit);
3001
3002 cmd->vsi_seid = cpu_to_le16(seid);
3003 cmd->credit = cpu_to_le16(credit);
3004 cmd->max_credit = max_credit;
3005
3006 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3007
3008 return status;
3009 }
3010
3011 /**
3012 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3013 * @hw: pointer to the hw struct
3014 * @seid: VSI seid
3015 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
3016 * @cmd_details: pointer to command details structure or NULL
3017 **/
3018 i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
3019 u16 seid,
3020 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
3021 struct i40e_asq_cmd_details *cmd_details)
3022 {
3023 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3024 i40e_aqc_opc_configure_vsi_tc_bw,
3025 cmd_details);
3026 }
3027
3028 /**
3029 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
3030 * @hw: pointer to the hw struct
3031 * @seid: seid of the switching component connected to Physical Port
3032 * @ets_data: Buffer holding ETS parameters
3033 * @cmd_details: pointer to command details structure or NULL
3034 **/
3035 i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
3036 u16 seid,
3037 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
3038 enum i40e_admin_queue_opc opcode,
3039 struct i40e_asq_cmd_details *cmd_details)
3040 {
3041 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
3042 sizeof(*ets_data), opcode, cmd_details);
3043 }
3044
3045 /**
3046 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
3047 * @hw: pointer to the hw struct
3048 * @seid: seid of the switching component
3049 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
3050 * @cmd_details: pointer to command details structure or NULL
3051 **/
3052 i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
3053 u16 seid,
3054 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
3055 struct i40e_asq_cmd_details *cmd_details)
3056 {
3057 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3058 i40e_aqc_opc_configure_switching_comp_bw_config,
3059 cmd_details);
3060 }
3061
3062 /**
3063 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
3064 * @hw: pointer to the hw struct
3065 * @seid: seid of the VSI
3066 * @bw_data: Buffer to hold VSI BW configuration
3067 * @cmd_details: pointer to command details structure or NULL
3068 **/
3069 i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
3070 u16 seid,
3071 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
3072 struct i40e_asq_cmd_details *cmd_details)
3073 {
3074 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3075 i40e_aqc_opc_query_vsi_bw_config,
3076 cmd_details);
3077 }
3078
3079 /**
3080 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
3081 * @hw: pointer to the hw struct
3082 * @seid: seid of the VSI
3083 * @bw_data: Buffer to hold VSI BW configuration per TC
3084 * @cmd_details: pointer to command details structure or NULL
3085 **/
3086 i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
3087 u16 seid,
3088 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
3089 struct i40e_asq_cmd_details *cmd_details)
3090 {
3091 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3092 i40e_aqc_opc_query_vsi_ets_sla_config,
3093 cmd_details);
3094 }
3095
3096 /**
3097 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
3098 * @hw: pointer to the hw struct
3099 * @seid: seid of the switching component
3100 * @bw_data: Buffer to hold switching component's per TC BW config
3101 * @cmd_details: pointer to command details structure or NULL
3102 **/
3103 i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
3104 u16 seid,
3105 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
3106 struct i40e_asq_cmd_details *cmd_details)
3107 {
3108 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3109 i40e_aqc_opc_query_switching_comp_ets_config,
3110 cmd_details);
3111 }
3112
3113 /**
3114 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
3115 * @hw: pointer to the hw struct
3116 * @seid: seid of the VSI or switching component connected to Physical Port
3117 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
3118 * @cmd_details: pointer to command details structure or NULL
3119 **/
3120 i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
3121 u16 seid,
3122 struct i40e_aqc_query_port_ets_config_resp *bw_data,
3123 struct i40e_asq_cmd_details *cmd_details)
3124 {
3125 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3126 i40e_aqc_opc_query_port_ets_config,
3127 cmd_details);
3128 }
3129
3130 /**
3131 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
3132 * @hw: pointer to the hw struct
3133 * @seid: seid of the switching component
3134 * @bw_data: Buffer to hold switching component's BW configuration
3135 * @cmd_details: pointer to command details structure or NULL
3136 **/
3137 i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
3138 u16 seid,
3139 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
3140 struct i40e_asq_cmd_details *cmd_details)
3141 {
3142 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3143 i40e_aqc_opc_query_switching_comp_bw_config,
3144 cmd_details);
3145 }
3146
3147 /**
3148 * i40e_validate_filter_settings
3149 * @hw: pointer to the hardware structure
3150 * @settings: Filter control settings
3151 *
3152 * Check and validate the filter control settings passed.
3153 * The function checks for the valid filter/context sizes being
3154 * passed for FCoE and PE.
3155 *
3156 * Returns 0 if the values passed are valid and within
3157 * range else returns an error.
3158 **/
3159 static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
3160 struct i40e_filter_control_settings *settings)
3161 {
3162 u32 fcoe_cntx_size, fcoe_filt_size;
3163 u32 pe_cntx_size, pe_filt_size;
3164 u32 fcoe_fmax;
3165 u32 val;
3166
3167 /* Validate FCoE settings passed */
3168 switch (settings->fcoe_filt_num) {
3169 case I40E_HASH_FILTER_SIZE_1K:
3170 case I40E_HASH_FILTER_SIZE_2K:
3171 case I40E_HASH_FILTER_SIZE_4K:
3172 case I40E_HASH_FILTER_SIZE_8K:
3173 case I40E_HASH_FILTER_SIZE_16K:
3174 case I40E_HASH_FILTER_SIZE_32K:
3175 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3176 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
3177 break;
3178 default:
3179 return I40E_ERR_PARAM;
3180 }
3181
3182 switch (settings->fcoe_cntx_num) {
3183 case I40E_DMA_CNTX_SIZE_512:
3184 case I40E_DMA_CNTX_SIZE_1K:
3185 case I40E_DMA_CNTX_SIZE_2K:
3186 case I40E_DMA_CNTX_SIZE_4K:
3187 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3188 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
3189 break;
3190 default:
3191 return I40E_ERR_PARAM;
3192 }
3193
3194 /* Validate PE settings passed */
3195 switch (settings->pe_filt_num) {
3196 case I40E_HASH_FILTER_SIZE_1K:
3197 case I40E_HASH_FILTER_SIZE_2K:
3198 case I40E_HASH_FILTER_SIZE_4K:
3199 case I40E_HASH_FILTER_SIZE_8K:
3200 case I40E_HASH_FILTER_SIZE_16K:
3201 case I40E_HASH_FILTER_SIZE_32K:
3202 case I40E_HASH_FILTER_SIZE_64K:
3203 case I40E_HASH_FILTER_SIZE_128K:
3204 case I40E_HASH_FILTER_SIZE_256K:
3205 case I40E_HASH_FILTER_SIZE_512K:
3206 case I40E_HASH_FILTER_SIZE_1M:
3207 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3208 pe_filt_size <<= (u32)settings->pe_filt_num;
3209 break;
3210 default:
3211 return I40E_ERR_PARAM;
3212 }
3213
3214 switch (settings->pe_cntx_num) {
3215 case I40E_DMA_CNTX_SIZE_512:
3216 case I40E_DMA_CNTX_SIZE_1K:
3217 case I40E_DMA_CNTX_SIZE_2K:
3218 case I40E_DMA_CNTX_SIZE_4K:
3219 case I40E_DMA_CNTX_SIZE_8K:
3220 case I40E_DMA_CNTX_SIZE_16K:
3221 case I40E_DMA_CNTX_SIZE_32K:
3222 case I40E_DMA_CNTX_SIZE_64K:
3223 case I40E_DMA_CNTX_SIZE_128K:
3224 case I40E_DMA_CNTX_SIZE_256K:
3225 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3226 pe_cntx_size <<= (u32)settings->pe_cntx_num;
3227 break;
3228 default:
3229 return I40E_ERR_PARAM;
3230 }
3231
3232 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
3233 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
3234 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
3235 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
3236 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
3237 return I40E_ERR_INVALID_SIZE;
3238
3239 return 0;
3240 }
3241
3242 /**
3243 * i40e_set_filter_control
3244 * @hw: pointer to the hardware structure
3245 * @settings: Filter control settings
3246 *
3247 * Set the Queue Filters for PE/FCoE and enable filters required
3248 * for a single PF. It is expected that these settings are programmed
3249 * at the driver initialization time.
3250 **/
3251 i40e_status i40e_set_filter_control(struct i40e_hw *hw,
3252 struct i40e_filter_control_settings *settings)
3253 {
3254 i40e_status ret = 0;
3255 u32 hash_lut_size = 0;
3256 u32 val;
3257
3258 if (!settings)
3259 return I40E_ERR_PARAM;
3260
3261 /* Validate the input settings */
3262 ret = i40e_validate_filter_settings(hw, settings);
3263 if (ret)
3264 return ret;
3265
3266 /* Read the PF Queue Filter control register */
3267 val = rd32(hw, I40E_PFQF_CTL_0);
3268
3269 /* Program required PE hash buckets for the PF */
3270 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
3271 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
3272 I40E_PFQF_CTL_0_PEHSIZE_MASK;
3273 /* Program required PE contexts for the PF */
3274 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
3275 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
3276 I40E_PFQF_CTL_0_PEDSIZE_MASK;
3277
3278 /* Program required FCoE hash buckets for the PF */
3279 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3280 val |= ((u32)settings->fcoe_filt_num <<
3281 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
3282 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3283 /* Program required FCoE DDP contexts for the PF */
3284 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3285 val |= ((u32)settings->fcoe_cntx_num <<
3286 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
3287 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3288
3289 /* Program Hash LUT size for the PF */
3290 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3291 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
3292 hash_lut_size = 1;
3293 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
3294 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3295
3296 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
3297 if (settings->enable_fdir)
3298 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
3299 if (settings->enable_ethtype)
3300 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
3301 if (settings->enable_macvlan)
3302 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
3303
3304 wr32(hw, I40E_PFQF_CTL_0, val);
3305
3306 return 0;
3307 }
3308
3309 /**
3310 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
3311 * @hw: pointer to the hw struct
3312 * @mac_addr: MAC address to use in the filter
3313 * @ethtype: Ethertype to use in the filter
3314 * @flags: Flags that needs to be applied to the filter
3315 * @vsi_seid: seid of the control VSI
3316 * @queue: VSI queue number to send the packet to
3317 * @is_add: Add control packet filter if True else remove
3318 * @stats: Structure to hold information on control filter counts
3319 * @cmd_details: pointer to command details structure or NULL
3320 *
3321 * This command will Add or Remove control packet filter for a control VSI.
3322 * In return it will update the total number of perfect filter count in
3323 * the stats member.
3324 **/
3325 i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
3326 u8 *mac_addr, u16 ethtype, u16 flags,
3327 u16 vsi_seid, u16 queue, bool is_add,
3328 struct i40e_control_filter_stats *stats,
3329 struct i40e_asq_cmd_details *cmd_details)
3330 {
3331 struct i40e_aq_desc desc;
3332 struct i40e_aqc_add_remove_control_packet_filter *cmd =
3333 (struct i40e_aqc_add_remove_control_packet_filter *)
3334 &desc.params.raw;
3335 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
3336 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
3337 &desc.params.raw;
3338 i40e_status status;
3339
3340 if (vsi_seid == 0)
3341 return I40E_ERR_PARAM;
3342
3343 if (is_add) {
3344 i40e_fill_default_direct_cmd_desc(&desc,
3345 i40e_aqc_opc_add_control_packet_filter);
3346 cmd->queue = cpu_to_le16(queue);
3347 } else {
3348 i40e_fill_default_direct_cmd_desc(&desc,
3349 i40e_aqc_opc_remove_control_packet_filter);
3350 }
3351
3352 if (mac_addr)
3353 memcpy(cmd->mac, mac_addr, ETH_ALEN);
3354
3355 cmd->etype = cpu_to_le16(ethtype);
3356 cmd->flags = cpu_to_le16(flags);
3357 cmd->seid = cpu_to_le16(vsi_seid);
3358
3359 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3360
3361 if (!status && stats) {
3362 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
3363 stats->etype_used = le16_to_cpu(resp->etype_used);
3364 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
3365 stats->etype_free = le16_to_cpu(resp->etype_free);
3366 }
3367
3368 return status;
3369 }
3370
3371 /**
3372 * i40e_aq_resume_port_tx
3373 * @hw: pointer to the hardware structure
3374 * @cmd_details: pointer to command details structure or NULL
3375 *
3376 * Resume port's Tx traffic
3377 **/
3378 i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw,
3379 struct i40e_asq_cmd_details *cmd_details)
3380 {
3381 struct i40e_aq_desc desc;
3382 i40e_status status;
3383
3384 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
3385
3386 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3387
3388 return status;
3389 }
3390
3391 /**
3392 * i40e_set_pci_config_data - store PCI bus info
3393 * @hw: pointer to hardware structure
3394 * @link_status: the link status word from PCI config space
3395 *
3396 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
3397 **/
3398 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
3399 {
3400 hw->bus.type = i40e_bus_type_pci_express;
3401
3402 switch (link_status & PCI_EXP_LNKSTA_NLW) {
3403 case PCI_EXP_LNKSTA_NLW_X1:
3404 hw->bus.width = i40e_bus_width_pcie_x1;
3405 break;
3406 case PCI_EXP_LNKSTA_NLW_X2:
3407 hw->bus.width = i40e_bus_width_pcie_x2;
3408 break;
3409 case PCI_EXP_LNKSTA_NLW_X4:
3410 hw->bus.width = i40e_bus_width_pcie_x4;
3411 break;
3412 case PCI_EXP_LNKSTA_NLW_X8:
3413 hw->bus.width = i40e_bus_width_pcie_x8;
3414 break;
3415 default:
3416 hw->bus.width = i40e_bus_width_unknown;
3417 break;
3418 }
3419
3420 switch (link_status & PCI_EXP_LNKSTA_CLS) {
3421 case PCI_EXP_LNKSTA_CLS_2_5GB:
3422 hw->bus.speed = i40e_bus_speed_2500;
3423 break;
3424 case PCI_EXP_LNKSTA_CLS_5_0GB:
3425 hw->bus.speed = i40e_bus_speed_5000;
3426 break;
3427 case PCI_EXP_LNKSTA_CLS_8_0GB:
3428 hw->bus.speed = i40e_bus_speed_8000;
3429 break;
3430 default:
3431 hw->bus.speed = i40e_bus_speed_unknown;
3432 break;
3433 }
3434 }
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