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i40e: Add define for interrupt name string len
[linux-2.6/btrfs-unstable.git] / drivers / dma / sun6i-dma.c
blob159f1736a16f7cbb334bcffbfa1c66d18b22a120
1 /*
2 * Copyright (C) 2013-2014 Allwinner Tech Co., Ltd
3 * Author: Sugar <shuge@allwinnertech.com>
4 *
5 * Copyright (C) 2014 Maxime Ripard
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/dmaengine.h>
17 #include <linux/dmapool.h>
18 #include <linux/interrupt.h>
19 #include <linux/module.h>
20 #include <linux/of_dma.h>
21 #include <linux/of_device.h>
22 #include <linux/platform_device.h>
23 #include <linux/reset.h>
24 #include <linux/slab.h>
25 #include <linux/types.h>
26
27 #include "virt-dma.h"
28
29 /*
30 * Common registers
31 */
32 #define DMA_IRQ_EN(x) ((x) * 0x04)
33 #define DMA_IRQ_HALF BIT(0)
34 #define DMA_IRQ_PKG BIT(1)
35 #define DMA_IRQ_QUEUE BIT(2)
36
37 #define DMA_IRQ_CHAN_NR 8
38 #define DMA_IRQ_CHAN_WIDTH 4
39
40
41 #define DMA_IRQ_STAT(x) ((x) * 0x04 + 0x10)
42
43 #define DMA_STAT 0x30
44
45 /*
46 * sun8i specific registers
47 */
48 #define SUN8I_DMA_GATE 0x20
49 #define SUN8I_DMA_GATE_ENABLE 0x4
50
51 /*
52 * Channels specific registers
53 */
54 #define DMA_CHAN_ENABLE 0x00
55 #define DMA_CHAN_ENABLE_START BIT(0)
56 #define DMA_CHAN_ENABLE_STOP 0
57
58 #define DMA_CHAN_PAUSE 0x04
59 #define DMA_CHAN_PAUSE_PAUSE BIT(1)
60 #define DMA_CHAN_PAUSE_RESUME 0
61
62 #define DMA_CHAN_LLI_ADDR 0x08
63
64 #define DMA_CHAN_CUR_CFG 0x0c
65 #define DMA_CHAN_CFG_SRC_DRQ(x) ((x) & 0x1f)
66 #define DMA_CHAN_CFG_SRC_IO_MODE BIT(5)
67 #define DMA_CHAN_CFG_SRC_LINEAR_MODE (0 << 5)
68 #define DMA_CHAN_CFG_SRC_BURST(x) (((x) & 0x3) << 7)
69 #define DMA_CHAN_CFG_SRC_WIDTH(x) (((x) & 0x3) << 9)
70
71 #define DMA_CHAN_CFG_DST_DRQ(x) (DMA_CHAN_CFG_SRC_DRQ(x) << 16)
72 #define DMA_CHAN_CFG_DST_IO_MODE (DMA_CHAN_CFG_SRC_IO_MODE << 16)
73 #define DMA_CHAN_CFG_DST_LINEAR_MODE (DMA_CHAN_CFG_SRC_LINEAR_MODE << 16)
74 #define DMA_CHAN_CFG_DST_BURST(x) (DMA_CHAN_CFG_SRC_BURST(x) << 16)
75 #define DMA_CHAN_CFG_DST_WIDTH(x) (DMA_CHAN_CFG_SRC_WIDTH(x) << 16)
76
77 #define DMA_CHAN_CUR_SRC 0x10
78
79 #define DMA_CHAN_CUR_DST 0x14
80
81 #define DMA_CHAN_CUR_CNT 0x18
82
83 #define DMA_CHAN_CUR_PARA 0x1c
84
85
86 /*
87 * Various hardware related defines
88 */
89 #define LLI_LAST_ITEM 0xfffff800
90 #define NORMAL_WAIT 8
91 #define DRQ_SDRAM 1
92
93 /*
94 * Hardware channels / ports representation
95 *
96 * The hardware is used in several SoCs, with differing numbers
97 * of channels and endpoints. This structure ties those numbers
98 * to a certain compatible string.
99 */
100 struct sun6i_dma_config {
101 u32 nr_max_channels;
102 u32 nr_max_requests;
103 u32 nr_max_vchans;
104 };
105
106 /*
107 * Hardware representation of the LLI
108 *
109 * The hardware will be fed the physical address of this structure,
110 * and read its content in order to start the transfer.
111 */
112 struct sun6i_dma_lli {
113 u32 cfg;
114 u32 src;
115 u32 dst;
116 u32 len;
117 u32 para;
118 u32 p_lli_next;
119
120 /*
121 * This field is not used by the DMA controller, but will be
122 * used by the CPU to go through the list (mostly for dumping
123 * or freeing it).
124 */
125 struct sun6i_dma_lli *v_lli_next;
126 };
127
128
129 struct sun6i_desc {
130 struct virt_dma_desc vd;
131 dma_addr_t p_lli;
132 struct sun6i_dma_lli *v_lli;
133 };
134
135 struct sun6i_pchan {
136 u32 idx;
137 void __iomem *base;
138 struct sun6i_vchan *vchan;
139 struct sun6i_desc *desc;
140 struct sun6i_desc *done;
141 };
142
143 struct sun6i_vchan {
144 struct virt_dma_chan vc;
145 struct list_head node;
146 struct dma_slave_config cfg;
147 struct sun6i_pchan *phy;
148 u8 port;
149 };
150
151 struct sun6i_dma_dev {
152 struct dma_device slave;
153 void __iomem *base;
154 struct clk *clk;
155 int irq;
156 spinlock_t lock;
157 struct reset_control *rstc;
158 struct tasklet_struct task;
159 atomic_t tasklet_shutdown;
160 struct list_head pending;
161 struct dma_pool *pool;
162 struct sun6i_pchan *pchans;
163 struct sun6i_vchan *vchans;
164 const struct sun6i_dma_config *cfg;
165 };
166
167 static struct device *chan2dev(struct dma_chan *chan)
168 {
169 return &chan->dev->device;
170 }
171
172 static inline struct sun6i_dma_dev *to_sun6i_dma_dev(struct dma_device *d)
173 {
174 return container_of(d, struct sun6i_dma_dev, slave);
175 }
176
177 static inline struct sun6i_vchan *to_sun6i_vchan(struct dma_chan *chan)
178 {
179 return container_of(chan, struct sun6i_vchan, vc.chan);
180 }
181
182 static inline struct sun6i_desc *
183 to_sun6i_desc(struct dma_async_tx_descriptor *tx)
184 {
185 return container_of(tx, struct sun6i_desc, vd.tx);
186 }
187
188 static inline void sun6i_dma_dump_com_regs(struct sun6i_dma_dev *sdev)
189 {
190 dev_dbg(sdev->slave.dev, "Common register:\n"
191 "\tmask0(%04x): 0x%08x\n"
192 "\tmask1(%04x): 0x%08x\n"
193 "\tpend0(%04x): 0x%08x\n"
194 "\tpend1(%04x): 0x%08x\n"
195 "\tstats(%04x): 0x%08x\n",
196 DMA_IRQ_EN(0), readl(sdev->base + DMA_IRQ_EN(0)),
197 DMA_IRQ_EN(1), readl(sdev->base + DMA_IRQ_EN(1)),
198 DMA_IRQ_STAT(0), readl(sdev->base + DMA_IRQ_STAT(0)),
199 DMA_IRQ_STAT(1), readl(sdev->base + DMA_IRQ_STAT(1)),
200 DMA_STAT, readl(sdev->base + DMA_STAT));
201 }
202
203 static inline void sun6i_dma_dump_chan_regs(struct sun6i_dma_dev *sdev,
204 struct sun6i_pchan *pchan)
205 {
206 phys_addr_t reg = virt_to_phys(pchan->base);
207
208 dev_dbg(sdev->slave.dev, "Chan %d reg: %pa\n"
209 "\t___en(%04x): \t0x%08x\n"
210 "\tpause(%04x): \t0x%08x\n"
211 "\tstart(%04x): \t0x%08x\n"
212 "\t__cfg(%04x): \t0x%08x\n"
213 "\t__src(%04x): \t0x%08x\n"
214 "\t__dst(%04x): \t0x%08x\n"
215 "\tcount(%04x): \t0x%08x\n"
216 "\t_para(%04x): \t0x%08x\n\n",
217 pchan->idx, &reg,
218 DMA_CHAN_ENABLE,
219 readl(pchan->base + DMA_CHAN_ENABLE),
220 DMA_CHAN_PAUSE,
221 readl(pchan->base + DMA_CHAN_PAUSE),
222 DMA_CHAN_LLI_ADDR,
223 readl(pchan->base + DMA_CHAN_LLI_ADDR),
224 DMA_CHAN_CUR_CFG,
225 readl(pchan->base + DMA_CHAN_CUR_CFG),
226 DMA_CHAN_CUR_SRC,
227 readl(pchan->base + DMA_CHAN_CUR_SRC),
228 DMA_CHAN_CUR_DST,
229 readl(pchan->base + DMA_CHAN_CUR_DST),
230 DMA_CHAN_CUR_CNT,
231 readl(pchan->base + DMA_CHAN_CUR_CNT),
232 DMA_CHAN_CUR_PARA,
233 readl(pchan->base + DMA_CHAN_CUR_PARA));
234 }
235
236 static inline s8 convert_burst(u32 maxburst)
237 {
238 switch (maxburst) {
239 case 1:
240 return 0;
241 case 8:
242 return 2;
243 default:
244 return -EINVAL;
245 }
246 }
247
248 static inline s8 convert_buswidth(enum dma_slave_buswidth addr_width)
249 {
250 if ((addr_width < DMA_SLAVE_BUSWIDTH_1_BYTE) ||
251 (addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES))
252 return -EINVAL;
253
254 return addr_width >> 1;
255 }
256
257 static void *sun6i_dma_lli_add(struct sun6i_dma_lli *prev,
258 struct sun6i_dma_lli *next,
259 dma_addr_t next_phy,
260 struct sun6i_desc *txd)
261 {
262 if ((!prev && !txd) || !next)
263 return NULL;
264
265 if (!prev) {
266 txd->p_lli = next_phy;
267 txd->v_lli = next;
268 } else {
269 prev->p_lli_next = next_phy;
270 prev->v_lli_next = next;
271 }
272
273 next->p_lli_next = LLI_LAST_ITEM;
274 next->v_lli_next = NULL;
275
276 return next;
277 }
278
279 static inline int sun6i_dma_cfg_lli(struct sun6i_dma_lli *lli,
280 dma_addr_t src,
281 dma_addr_t dst, u32 len,
282 struct dma_slave_config *config)
283 {
284 u8 src_width, dst_width, src_burst, dst_burst;
285
286 if (!config)
287 return -EINVAL;
288
289 src_burst = convert_burst(config->src_maxburst);
290 if (src_burst)
291 return src_burst;
292
293 dst_burst = convert_burst(config->dst_maxburst);
294 if (dst_burst)
295 return dst_burst;
296
297 src_width = convert_buswidth(config->src_addr_width);
298 if (src_width)
299 return src_width;
300
301 dst_width = convert_buswidth(config->dst_addr_width);
302 if (dst_width)
303 return dst_width;
304
305 lli->cfg = DMA_CHAN_CFG_SRC_BURST(src_burst) |
306 DMA_CHAN_CFG_SRC_WIDTH(src_width) |
307 DMA_CHAN_CFG_DST_BURST(dst_burst) |
308 DMA_CHAN_CFG_DST_WIDTH(dst_width);
309
310 lli->src = src;
311 lli->dst = dst;
312 lli->len = len;
313 lli->para = NORMAL_WAIT;
314
315 return 0;
316 }
317
318 static inline void sun6i_dma_dump_lli(struct sun6i_vchan *vchan,
319 struct sun6i_dma_lli *lli)
320 {
321 phys_addr_t p_lli = virt_to_phys(lli);
322
323 dev_dbg(chan2dev(&vchan->vc.chan),
324 "\n\tdesc: p - %pa v - 0x%p\n"
325 "\t\tc - 0x%08x s - 0x%08x d - 0x%08x\n"
326 "\t\tl - 0x%08x p - 0x%08x n - 0x%08x\n",
327 &p_lli, lli,
328 lli->cfg, lli->src, lli->dst,
329 lli->len, lli->para, lli->p_lli_next);
330 }
331
332 static void sun6i_dma_free_desc(struct virt_dma_desc *vd)
333 {
334 struct sun6i_desc *txd = to_sun6i_desc(&vd->tx);
335 struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(vd->tx.chan->device);
336 struct sun6i_dma_lli *v_lli, *v_next;
337 dma_addr_t p_lli, p_next;
338
339 if (unlikely(!txd))
340 return;
341
342 p_lli = txd->p_lli;
343 v_lli = txd->v_lli;
344
345 while (v_lli) {
346 v_next = v_lli->v_lli_next;
347 p_next = v_lli->p_lli_next;
348
349 dma_pool_free(sdev->pool, v_lli, p_lli);
350
351 v_lli = v_next;
352 p_lli = p_next;
353 }
354
355 kfree(txd);
356 }
357
358 static int sun6i_dma_terminate_all(struct sun6i_vchan *vchan)
359 {
360 struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(vchan->vc.chan.device);
361 struct sun6i_pchan *pchan = vchan->phy;
362 unsigned long flags;
363 LIST_HEAD(head);
364
365 spin_lock(&sdev->lock);
366 list_del_init(&vchan->node);
367 spin_unlock(&sdev->lock);
368
369 spin_lock_irqsave(&vchan->vc.lock, flags);
370
371 vchan_get_all_descriptors(&vchan->vc, &head);
372
373 if (pchan) {
374 writel(DMA_CHAN_ENABLE_STOP, pchan->base + DMA_CHAN_ENABLE);
375 writel(DMA_CHAN_PAUSE_RESUME, pchan->base + DMA_CHAN_PAUSE);
376
377 vchan->phy = NULL;
378 pchan->vchan = NULL;
379 pchan->desc = NULL;
380 pchan->done = NULL;
381 }
382
383 spin_unlock_irqrestore(&vchan->vc.lock, flags);
384
385 vchan_dma_desc_free_list(&vchan->vc, &head);
386
387 return 0;
388 }
389
390 static int sun6i_dma_start_desc(struct sun6i_vchan *vchan)
391 {
392 struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(vchan->vc.chan.device);
393 struct virt_dma_desc *desc = vchan_next_desc(&vchan->vc);
394 struct sun6i_pchan *pchan = vchan->phy;
395 u32 irq_val, irq_reg, irq_offset;
396
397 if (!pchan)
398 return -EAGAIN;
399
400 if (!desc) {
401 pchan->desc = NULL;
402 pchan->done = NULL;
403 return -EAGAIN;
404 }
405
406 list_del(&desc->node);
407
408 pchan->desc = to_sun6i_desc(&desc->tx);
409 pchan->done = NULL;
410
411 sun6i_dma_dump_lli(vchan, pchan->desc->v_lli);
412
413 irq_reg = pchan->idx / DMA_IRQ_CHAN_NR;
414 irq_offset = pchan->idx % DMA_IRQ_CHAN_NR;
415
416 irq_val = readl(sdev->base + DMA_IRQ_EN(irq_offset));
417 irq_val |= DMA_IRQ_QUEUE << (irq_offset * DMA_IRQ_CHAN_WIDTH);
418 writel(irq_val, sdev->base + DMA_IRQ_EN(irq_offset));
419
420 writel(pchan->desc->p_lli, pchan->base + DMA_CHAN_LLI_ADDR);
421 writel(DMA_CHAN_ENABLE_START, pchan->base + DMA_CHAN_ENABLE);
422
423 sun6i_dma_dump_com_regs(sdev);
424 sun6i_dma_dump_chan_regs(sdev, pchan);
425
426 return 0;
427 }
428
429 static void sun6i_dma_tasklet(unsigned long data)
430 {
431 struct sun6i_dma_dev *sdev = (struct sun6i_dma_dev *)data;
432 const struct sun6i_dma_config *cfg = sdev->cfg;
433 struct sun6i_vchan *vchan;
434 struct sun6i_pchan *pchan;
435 unsigned int pchan_alloc = 0;
436 unsigned int pchan_idx;
437
438 list_for_each_entry(vchan, &sdev->slave.channels, vc.chan.device_node) {
439 spin_lock_irq(&vchan->vc.lock);
440
441 pchan = vchan->phy;
442
443 if (pchan && pchan->done) {
444 if (sun6i_dma_start_desc(vchan)) {
445 /*
446 * No current txd associated with this channel
447 */
448 dev_dbg(sdev->slave.dev, "pchan %u: free\n",
449 pchan->idx);
450
451 /* Mark this channel free */
452 vchan->phy = NULL;
453 pchan->vchan = NULL;
454 }
455 }
456 spin_unlock_irq(&vchan->vc.lock);
457 }
458
459 spin_lock_irq(&sdev->lock);
460 for (pchan_idx = 0; pchan_idx < cfg->nr_max_channels; pchan_idx++) {
461 pchan = &sdev->pchans[pchan_idx];
462
463 if (pchan->vchan || list_empty(&sdev->pending))
464 continue;
465
466 vchan = list_first_entry(&sdev->pending,
467 struct sun6i_vchan, node);
468
469 /* Remove from pending channels */
470 list_del_init(&vchan->node);
471 pchan_alloc |= BIT(pchan_idx);
472
473 /* Mark this channel allocated */
474 pchan->vchan = vchan;
475 vchan->phy = pchan;
476 dev_dbg(sdev->slave.dev, "pchan %u: alloc vchan %p\n",
477 pchan->idx, &vchan->vc);
478 }
479 spin_unlock_irq(&sdev->lock);
480
481 for (pchan_idx = 0; pchan_idx < cfg->nr_max_channels; pchan_idx++) {
482 if (!(pchan_alloc & BIT(pchan_idx)))
483 continue;
484
485 pchan = sdev->pchans + pchan_idx;
486 vchan = pchan->vchan;
487 if (vchan) {
488 spin_lock_irq(&vchan->vc.lock);
489 sun6i_dma_start_desc(vchan);
490 spin_unlock_irq(&vchan->vc.lock);
491 }
492 }
493 }
494
495 static irqreturn_t sun6i_dma_interrupt(int irq, void *dev_id)
496 {
497 struct sun6i_dma_dev *sdev = dev_id;
498 struct sun6i_vchan *vchan;
499 struct sun6i_pchan *pchan;
500 int i, j, ret = IRQ_NONE;
501 u32 status;
502
503 for (i = 0; i < sdev->cfg->nr_max_channels / DMA_IRQ_CHAN_NR; i++) {
504 status = readl(sdev->base + DMA_IRQ_STAT(i));
505 if (!status)
506 continue;
507
508 dev_dbg(sdev->slave.dev, "DMA irq status %s: 0x%x\n",
509 i ? "high" : "low", status);
510
511 writel(status, sdev->base + DMA_IRQ_STAT(i));
512
513 for (j = 0; (j < DMA_IRQ_CHAN_NR) && status; j++) {
514 if (status & DMA_IRQ_QUEUE) {
515 pchan = sdev->pchans + j;
516 vchan = pchan->vchan;
517
518 if (vchan) {
519 spin_lock(&vchan->vc.lock);
520 vchan_cookie_complete(&pchan->desc->vd);
521 pchan->done = pchan->desc;
522 spin_unlock(&vchan->vc.lock);
523 }
524 }
525
526 status = status >> DMA_IRQ_CHAN_WIDTH;
527 }
528
529 if (!atomic_read(&sdev->tasklet_shutdown))
530 tasklet_schedule(&sdev->task);
531 ret = IRQ_HANDLED;
532 }
533
534 return ret;
535 }
536
537 static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_memcpy(
538 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
539 size_t len, unsigned long flags)
540 {
541 struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
542 struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
543 struct sun6i_dma_lli *v_lli;
544 struct sun6i_desc *txd;
545 dma_addr_t p_lli;
546 s8 burst, width;
547
548 dev_dbg(chan2dev(chan),
549 "%s; chan: %d, dest: %pad, src: %pad, len: %zu. flags: 0x%08lx\n",
550 __func__, vchan->vc.chan.chan_id, &dest, &src, len, flags);
551
552 if (!len)
553 return NULL;
554
555 txd = kzalloc(sizeof(*txd), GFP_NOWAIT);
556 if (!txd)
557 return NULL;
558
559 v_lli = dma_pool_alloc(sdev->pool, GFP_NOWAIT, &p_lli);
560 if (!v_lli) {
561 dev_err(sdev->slave.dev, "Failed to alloc lli memory\n");
562 goto err_txd_free;
563 }
564
565 v_lli->src = src;
566 v_lli->dst = dest;
567 v_lli->len = len;
568 v_lli->para = NORMAL_WAIT;
569
570 burst = convert_burst(8);
571 width = convert_buswidth(DMA_SLAVE_BUSWIDTH_4_BYTES);
572 v_lli->cfg |= DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) |
573 DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) |
574 DMA_CHAN_CFG_DST_LINEAR_MODE |
575 DMA_CHAN_CFG_SRC_LINEAR_MODE |
576 DMA_CHAN_CFG_SRC_BURST(burst) |
577 DMA_CHAN_CFG_SRC_WIDTH(width) |
578 DMA_CHAN_CFG_DST_BURST(burst) |
579 DMA_CHAN_CFG_DST_WIDTH(width);
580
581 sun6i_dma_lli_add(NULL, v_lli, p_lli, txd);
582
583 sun6i_dma_dump_lli(vchan, v_lli);
584
585 return vchan_tx_prep(&vchan->vc, &txd->vd, flags);
586
587 err_txd_free:
588 kfree(txd);
589 return NULL;
590 }
591
592 static struct dma_async_tx_descriptor *sun6i_dma_prep_slave_sg(
593 struct dma_chan *chan, struct scatterlist *sgl,
594 unsigned int sg_len, enum dma_transfer_direction dir,
595 unsigned long flags, void *context)
596 {
597 struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
598 struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
599 struct dma_slave_config *sconfig = &vchan->cfg;
600 struct sun6i_dma_lli *v_lli, *prev = NULL;
601 struct sun6i_desc *txd;
602 struct scatterlist *sg;
603 dma_addr_t p_lli;
604 int i, ret;
605
606 if (!sgl)
607 return NULL;
608
609 if (!is_slave_direction(dir)) {
610 dev_err(chan2dev(chan), "Invalid DMA direction\n");
611 return NULL;
612 }
613
614 txd = kzalloc(sizeof(*txd), GFP_NOWAIT);
615 if (!txd)
616 return NULL;
617
618 for_each_sg(sgl, sg, sg_len, i) {
619 v_lli = dma_pool_alloc(sdev->pool, GFP_NOWAIT, &p_lli);
620 if (!v_lli)
621 goto err_lli_free;
622
623 if (dir == DMA_MEM_TO_DEV) {
624 ret = sun6i_dma_cfg_lli(v_lli, sg_dma_address(sg),
625 sconfig->dst_addr, sg_dma_len(sg),
626 sconfig);
627 if (ret)
628 goto err_cur_lli_free;
629
630 v_lli->cfg |= DMA_CHAN_CFG_DST_IO_MODE |
631 DMA_CHAN_CFG_SRC_LINEAR_MODE |
632 DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) |
633 DMA_CHAN_CFG_DST_DRQ(vchan->port);
634
635 dev_dbg(chan2dev(chan),
636 "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n",
637 __func__, vchan->vc.chan.chan_id,
638 &sconfig->dst_addr, &sg_dma_address(sg),
639 sg_dma_len(sg), flags);
640
641 } else {
642 ret = sun6i_dma_cfg_lli(v_lli, sconfig->src_addr,
643 sg_dma_address(sg), sg_dma_len(sg),
644 sconfig);
645 if (ret)
646 goto err_cur_lli_free;
647
648 v_lli->cfg |= DMA_CHAN_CFG_DST_LINEAR_MODE |
649 DMA_CHAN_CFG_SRC_IO_MODE |
650 DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) |
651 DMA_CHAN_CFG_SRC_DRQ(vchan->port);
652
653 dev_dbg(chan2dev(chan),
654 "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n",
655 __func__, vchan->vc.chan.chan_id,
656 &sg_dma_address(sg), &sconfig->src_addr,
657 sg_dma_len(sg), flags);
658 }
659
660 prev = sun6i_dma_lli_add(prev, v_lli, p_lli, txd);
661 }
662
663 dev_dbg(chan2dev(chan), "First: %pad\n", &txd->p_lli);
664 for (prev = txd->v_lli; prev; prev = prev->v_lli_next)
665 sun6i_dma_dump_lli(vchan, prev);
666
667 return vchan_tx_prep(&vchan->vc, &txd->vd, flags);
668
669 err_cur_lli_free:
670 dma_pool_free(sdev->pool, v_lli, p_lli);
671 err_lli_free:
672 for (prev = txd->v_lli; prev; prev = prev->v_lli_next)
673 dma_pool_free(sdev->pool, prev, virt_to_phys(prev));
674 kfree(txd);
675 return NULL;
676 }
677
678 static int sun6i_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
679 unsigned long arg)
680 {
681 struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
682 struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
683 struct sun6i_pchan *pchan = vchan->phy;
684 unsigned long flags;
685 int ret = 0;
686
687 switch (cmd) {
688 case DMA_RESUME:
689 dev_dbg(chan2dev(chan), "vchan %p: resume\n", &vchan->vc);
690
691 spin_lock_irqsave(&vchan->vc.lock, flags);
692
693 if (pchan) {
694 writel(DMA_CHAN_PAUSE_RESUME,
695 pchan->base + DMA_CHAN_PAUSE);
696 } else if (!list_empty(&vchan->vc.desc_issued)) {
697 spin_lock(&sdev->lock);
698 list_add_tail(&vchan->node, &sdev->pending);
699 spin_unlock(&sdev->lock);
700 }
701
702 spin_unlock_irqrestore(&vchan->vc.lock, flags);
703 break;
704
705 case DMA_PAUSE:
706 dev_dbg(chan2dev(chan), "vchan %p: pause\n", &vchan->vc);
707
708 if (pchan) {
709 writel(DMA_CHAN_PAUSE_PAUSE,
710 pchan->base + DMA_CHAN_PAUSE);
711 } else {
712 spin_lock(&sdev->lock);
713 list_del_init(&vchan->node);
714 spin_unlock(&sdev->lock);
715 }
716 break;
717
718 case DMA_TERMINATE_ALL:
719 ret = sun6i_dma_terminate_all(vchan);
720 break;
721 case DMA_SLAVE_CONFIG:
722 memcpy(&vchan->cfg, (void *)arg, sizeof(struct dma_slave_config));
723 break;
724 default:
725 ret = -ENXIO;
726 break;
727 }
728 return ret;
729 }
730
731 static enum dma_status sun6i_dma_tx_status(struct dma_chan *chan,
732 dma_cookie_t cookie,
733 struct dma_tx_state *state)
734 {
735 struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
736 struct sun6i_pchan *pchan = vchan->phy;
737 struct sun6i_dma_lli *lli;
738 struct virt_dma_desc *vd;
739 struct sun6i_desc *txd;
740 enum dma_status ret;
741 unsigned long flags;
742 size_t bytes = 0;
743
744 ret = dma_cookie_status(chan, cookie, state);
745 if (ret == DMA_COMPLETE)
746 return ret;
747
748 spin_lock_irqsave(&vchan->vc.lock, flags);
749
750 vd = vchan_find_desc(&vchan->vc, cookie);
751 txd = to_sun6i_desc(&vd->tx);
752
753 if (vd) {
754 for (lli = txd->v_lli; lli != NULL; lli = lli->v_lli_next)
755 bytes += lli->len;
756 } else if (!pchan || !pchan->desc) {
757 bytes = 0;
758 } else {
759 bytes = readl(pchan->base + DMA_CHAN_CUR_CNT);
760 }
761
762 spin_unlock_irqrestore(&vchan->vc.lock, flags);
763
764 dma_set_residue(state, bytes);
765
766 return ret;
767 }
768
769 static void sun6i_dma_issue_pending(struct dma_chan *chan)
770 {
771 struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
772 struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
773 unsigned long flags;
774
775 spin_lock_irqsave(&vchan->vc.lock, flags);
776
777 if (vchan_issue_pending(&vchan->vc)) {
778 spin_lock(&sdev->lock);
779
780 if (!vchan->phy && list_empty(&vchan->node)) {
781 list_add_tail(&vchan->node, &sdev->pending);
782 tasklet_schedule(&sdev->task);
783 dev_dbg(chan2dev(chan), "vchan %p: issued\n",
784 &vchan->vc);
785 }
786
787 spin_unlock(&sdev->lock);
788 } else {
789 dev_dbg(chan2dev(chan), "vchan %p: nothing to issue\n",
790 &vchan->vc);
791 }
792
793 spin_unlock_irqrestore(&vchan->vc.lock, flags);
794 }
795
796 static int sun6i_dma_alloc_chan_resources(struct dma_chan *chan)
797 {
798 return 0;
799 }
800
801 static void sun6i_dma_free_chan_resources(struct dma_chan *chan)
802 {
803 struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
804 struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
805 unsigned long flags;
806
807 spin_lock_irqsave(&sdev->lock, flags);
808 list_del_init(&vchan->node);
809 spin_unlock_irqrestore(&sdev->lock, flags);
810
811 vchan_free_chan_resources(&vchan->vc);
812 }
813
814 static struct dma_chan *sun6i_dma_of_xlate(struct of_phandle_args *dma_spec,
815 struct of_dma *ofdma)
816 {
817 struct sun6i_dma_dev *sdev = ofdma->of_dma_data;
818 struct sun6i_vchan *vchan;
819 struct dma_chan *chan;
820 u8 port = dma_spec->args[0];
821
822 if (port > sdev->cfg->nr_max_requests)
823 return NULL;
824
825 chan = dma_get_any_slave_channel(&sdev->slave);
826 if (!chan)
827 return NULL;
828
829 vchan = to_sun6i_vchan(chan);
830 vchan->port = port;
831
832 return chan;
833 }
834
835 static inline void sun6i_kill_tasklet(struct sun6i_dma_dev *sdev)
836 {
837 /* Disable all interrupts from DMA */
838 writel(0, sdev->base + DMA_IRQ_EN(0));
839 writel(0, sdev->base + DMA_IRQ_EN(1));
840
841 /* Prevent spurious interrupts from scheduling the tasklet */
842 atomic_inc(&sdev->tasklet_shutdown);
843
844 /* Make sure we won't have any further interrupts */
845 devm_free_irq(sdev->slave.dev, sdev->irq, sdev);
846
847 /* Actually prevent the tasklet from being scheduled */
848 tasklet_kill(&sdev->task);
849 }
850
851 static inline void sun6i_dma_free(struct sun6i_dma_dev *sdev)
852 {
853 int i;
854
855 for (i = 0; i < sdev->cfg->nr_max_vchans; i++) {
856 struct sun6i_vchan *vchan = &sdev->vchans[i];
857
858 list_del(&vchan->vc.chan.device_node);
859 tasklet_kill(&vchan->vc.task);
860 }
861 }
862
863 /*
864 * For A31:
865 *
866 * There's 16 physical channels that can work in parallel.
867 *
868 * However we have 30 different endpoints for our requests.
869 *
870 * Since the channels are able to handle only an unidirectional
871 * transfer, we need to allocate more virtual channels so that
872 * everyone can grab one channel.
873 *
874 * Some devices can't work in both direction (mostly because it
875 * wouldn't make sense), so we have a bit fewer virtual channels than
876 * 2 channels per endpoints.
877 */
878
879 static struct sun6i_dma_config sun6i_a31_dma_cfg = {
880 .nr_max_channels = 16,
881 .nr_max_requests = 30,
882 .nr_max_vchans = 53,
883 };
884
885 /*
886 * The A23 only has 8 physical channels, a maximum DRQ port id of 24,
887 * and a total of 37 usable source and destination endpoints.
888 */
889
890 static struct sun6i_dma_config sun8i_a23_dma_cfg = {
891 .nr_max_channels = 8,
892 .nr_max_requests = 24,
893 .nr_max_vchans = 37,
894 };
895
896 static struct of_device_id sun6i_dma_match[] = {
897 { .compatible = "allwinner,sun6i-a31-dma", .data = &sun6i_a31_dma_cfg },
898 { .compatible = "allwinner,sun8i-a23-dma", .data = &sun8i_a23_dma_cfg },
899 { /* sentinel */ }
900 };
901
902 static int sun6i_dma_probe(struct platform_device *pdev)
903 {
904 const struct of_device_id *device;
905 struct sun6i_dma_dev *sdc;
906 struct resource *res;
907 int ret, i;
908
909 sdc = devm_kzalloc(&pdev->dev, sizeof(*sdc), GFP_KERNEL);
910 if (!sdc)
911 return -ENOMEM;
912
913 device = of_match_device(sun6i_dma_match, &pdev->dev);
914 if (!device)
915 return -ENODEV;
916 sdc->cfg = device->data;
917
918 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
919 sdc->base = devm_ioremap_resource(&pdev->dev, res);
920 if (IS_ERR(sdc->base))
921 return PTR_ERR(sdc->base);
922
923 sdc->irq = platform_get_irq(pdev, 0);
924 if (sdc->irq < 0) {
925 dev_err(&pdev->dev, "Cannot claim IRQ\n");
926 return sdc->irq;
927 }
928
929 sdc->clk = devm_clk_get(&pdev->dev, NULL);
930 if (IS_ERR(sdc->clk)) {
931 dev_err(&pdev->dev, "No clock specified\n");
932 return PTR_ERR(sdc->clk);
933 }
934
935 sdc->rstc = devm_reset_control_get(&pdev->dev, NULL);
936 if (IS_ERR(sdc->rstc)) {
937 dev_err(&pdev->dev, "No reset controller specified\n");
938 return PTR_ERR(sdc->rstc);
939 }
940
941 sdc->pool = dmam_pool_create(dev_name(&pdev->dev), &pdev->dev,
942 sizeof(struct sun6i_dma_lli), 4, 0);
943 if (!sdc->pool) {
944 dev_err(&pdev->dev, "No memory for descriptors dma pool\n");
945 return -ENOMEM;
946 }
947
948 platform_set_drvdata(pdev, sdc);
949 INIT_LIST_HEAD(&sdc->pending);
950 spin_lock_init(&sdc->lock);
951
952 dma_cap_set(DMA_PRIVATE, sdc->slave.cap_mask);
953 dma_cap_set(DMA_MEMCPY, sdc->slave.cap_mask);
954 dma_cap_set(DMA_SLAVE, sdc->slave.cap_mask);
955
956 INIT_LIST_HEAD(&sdc->slave.channels);
957 sdc->slave.device_alloc_chan_resources = sun6i_dma_alloc_chan_resources;
958 sdc->slave.device_free_chan_resources = sun6i_dma_free_chan_resources;
959 sdc->slave.device_tx_status = sun6i_dma_tx_status;
960 sdc->slave.device_issue_pending = sun6i_dma_issue_pending;
961 sdc->slave.device_prep_slave_sg = sun6i_dma_prep_slave_sg;
962 sdc->slave.device_prep_dma_memcpy = sun6i_dma_prep_dma_memcpy;
963 sdc->slave.device_control = sun6i_dma_control;
964 sdc->slave.copy_align = 4;
965
966 sdc->slave.dev = &pdev->dev;
967
968 sdc->pchans = devm_kcalloc(&pdev->dev, sdc->cfg->nr_max_channels,
969 sizeof(struct sun6i_pchan), GFP_KERNEL);
970 if (!sdc->pchans)
971 return -ENOMEM;
972
973 sdc->vchans = devm_kcalloc(&pdev->dev, sdc->cfg->nr_max_vchans,
974 sizeof(struct sun6i_vchan), GFP_KERNEL);
975 if (!sdc->vchans)
976 return -ENOMEM;
977
978 tasklet_init(&sdc->task, sun6i_dma_tasklet, (unsigned long)sdc);
979
980 for (i = 0; i < sdc->cfg->nr_max_channels; i++) {
981 struct sun6i_pchan *pchan = &sdc->pchans[i];
982
983 pchan->idx = i;
984 pchan->base = sdc->base + 0x100 + i * 0x40;
985 }
986
987 for (i = 0; i < sdc->cfg->nr_max_vchans; i++) {
988 struct sun6i_vchan *vchan = &sdc->vchans[i];
989
990 INIT_LIST_HEAD(&vchan->node);
991 vchan->vc.desc_free = sun6i_dma_free_desc;
992 vchan_init(&vchan->vc, &sdc->slave);
993 }
994
995 ret = reset_control_deassert(sdc->rstc);
996 if (ret) {
997 dev_err(&pdev->dev, "Couldn't deassert the device from reset\n");
998 goto err_chan_free;
999 }
1000
1001 ret = clk_prepare_enable(sdc->clk);
1002 if (ret) {
1003 dev_err(&pdev->dev, "Couldn't enable the clock\n");
1004 goto err_reset_assert;
1005 }
1006
1007 ret = devm_request_irq(&pdev->dev, sdc->irq, sun6i_dma_interrupt, 0,
1008 dev_name(&pdev->dev), sdc);
1009 if (ret) {
1010 dev_err(&pdev->dev, "Cannot request IRQ\n");
1011 goto err_clk_disable;
1012 }
1013
1014 ret = dma_async_device_register(&sdc->slave);
1015 if (ret) {
1016 dev_warn(&pdev->dev, "Failed to register DMA engine device\n");
1017 goto err_irq_disable;
1018 }
1019
1020 ret = of_dma_controller_register(pdev->dev.of_node, sun6i_dma_of_xlate,
1021 sdc);
1022 if (ret) {
1023 dev_err(&pdev->dev, "of_dma_controller_register failed\n");
1024 goto err_dma_unregister;
1025 }
1026
1027 /*
1028 * sun8i variant requires us to toggle a dma gating register,
1029 * as seen in Allwinner's SDK. This register is not documented
1030 * in the A23 user manual.
1031 */
1032 if (of_device_is_compatible(pdev->dev.of_node,
1033 "allwinner,sun8i-a23-dma"))
1034 writel(SUN8I_DMA_GATE_ENABLE, sdc->base + SUN8I_DMA_GATE);
1035
1036 return 0;
1037
1038 err_dma_unregister:
1039 dma_async_device_unregister(&sdc->slave);
1040 err_irq_disable:
1041 sun6i_kill_tasklet(sdc);
1042 err_clk_disable:
1043 clk_disable_unprepare(sdc->clk);
1044 err_reset_assert:
1045 reset_control_assert(sdc->rstc);
1046 err_chan_free:
1047 sun6i_dma_free(sdc);
1048 return ret;
1049 }
1050
1051 static int sun6i_dma_remove(struct platform_device *pdev)
1052 {
1053 struct sun6i_dma_dev *sdc = platform_get_drvdata(pdev);
1054
1055 of_dma_controller_free(pdev->dev.of_node);
1056 dma_async_device_unregister(&sdc->slave);
1057
1058 sun6i_kill_tasklet(sdc);
1059
1060 clk_disable_unprepare(sdc->clk);
1061 reset_control_assert(sdc->rstc);
1062
1063 sun6i_dma_free(sdc);
1064
1065 return 0;
1066 }
1067
1068 static struct platform_driver sun6i_dma_driver = {
1069 .probe = sun6i_dma_probe,
1070 .remove = sun6i_dma_remove,
1071 .driver = {
1072 .name = "sun6i-dma",
1073 .of_match_table = sun6i_dma_match,
1074 },
1075 };
1076 module_platform_driver(sun6i_dma_driver);
1077
1078 MODULE_DESCRIPTION("Allwinner A31 DMA Controller Driver");
1079 MODULE_AUTHOR("Sugar <shuge@allwinnertech.com>");
1080 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1081 MODULE_LICENSE("GPL");
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