2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
6 * Jaswinder Singh <jassi.brar@samsung.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/slab.h>
18 #include <linux/module.h>
19 #include <linux/string.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/dmaengine.h>
24 #include <linux/amba/bus.h>
25 #include <linux/amba/pl330.h>
26 #include <linux/scatterlist.h>
28 #include <linux/of_dma.h>
29 #include <linux/err.h>
30 #include <linux/pm_runtime.h>
32 #include "dmaengine.h"
33 #define PL330_MAX_CHAN 8
34 #define PL330_MAX_IRQS 32
35 #define PL330_MAX_PERI 32
37 enum pl330_cachectrl
{
38 CCTRL0
, /* Noncacheable and nonbufferable */
39 CCTRL1
, /* Bufferable only */
40 CCTRL2
, /* Cacheable, but do not allocate */
41 CCTRL3
, /* Cacheable and bufferable, but do not allocate */
42 INVALID1
, /* AWCACHE = 0x1000 */
44 CCTRL6
, /* Cacheable write-through, allocate on writes only */
45 CCTRL7
, /* Cacheable write-back, allocate on writes only */
56 /* Register and Bit field Definitions */
58 #define DS_ST_STOP 0x0
59 #define DS_ST_EXEC 0x1
60 #define DS_ST_CMISS 0x2
61 #define DS_ST_UPDTPC 0x3
63 #define DS_ST_ATBRR 0x5
64 #define DS_ST_QBUSY 0x6
66 #define DS_ST_KILL 0x8
67 #define DS_ST_CMPLT 0x9
68 #define DS_ST_FLTCMP 0xe
69 #define DS_ST_FAULT 0xf
74 #define INTSTATUS 0x28
81 #define FTC(n) (_FTC + (n)*0x4)
84 #define CS(n) (_CS + (n)*0x8)
85 #define CS_CNS (1 << 21)
88 #define CPC(n) (_CPC + (n)*0x8)
91 #define SA(n) (_SA + (n)*0x20)
94 #define DA(n) (_DA + (n)*0x20)
97 #define CC(n) (_CC + (n)*0x20)
99 #define CC_SRCINC (1 << 0)
100 #define CC_DSTINC (1 << 14)
101 #define CC_SRCPRI (1 << 8)
102 #define CC_DSTPRI (1 << 22)
103 #define CC_SRCNS (1 << 9)
104 #define CC_DSTNS (1 << 23)
105 #define CC_SRCIA (1 << 10)
106 #define CC_DSTIA (1 << 24)
107 #define CC_SRCBRSTLEN_SHFT 4
108 #define CC_DSTBRSTLEN_SHFT 18
109 #define CC_SRCBRSTSIZE_SHFT 1
110 #define CC_DSTBRSTSIZE_SHFT 15
111 #define CC_SRCCCTRL_SHFT 11
112 #define CC_SRCCCTRL_MASK 0x7
113 #define CC_DSTCCTRL_SHFT 25
114 #define CC_DRCCCTRL_MASK 0x7
115 #define CC_SWAP_SHFT 28
118 #define LC0(n) (_LC0 + (n)*0x20)
121 #define LC1(n) (_LC1 + (n)*0x20)
123 #define DBGSTATUS 0xd00
124 #define DBG_BUSY (1 << 0)
127 #define DBGINST0 0xd08
128 #define DBGINST1 0xd0c
137 #define PERIPH_ID 0xfe0
138 #define PERIPH_REV_SHIFT 20
139 #define PERIPH_REV_MASK 0xf
140 #define PERIPH_REV_R0P0 0
141 #define PERIPH_REV_R1P0 1
142 #define PERIPH_REV_R1P1 2
144 #define CR0_PERIPH_REQ_SET (1 << 0)
145 #define CR0_BOOT_EN_SET (1 << 1)
146 #define CR0_BOOT_MAN_NS (1 << 2)
147 #define CR0_NUM_CHANS_SHIFT 4
148 #define CR0_NUM_CHANS_MASK 0x7
149 #define CR0_NUM_PERIPH_SHIFT 12
150 #define CR0_NUM_PERIPH_MASK 0x1f
151 #define CR0_NUM_EVENTS_SHIFT 17
152 #define CR0_NUM_EVENTS_MASK 0x1f
154 #define CR1_ICACHE_LEN_SHIFT 0
155 #define CR1_ICACHE_LEN_MASK 0x7
156 #define CR1_NUM_ICACHELINES_SHIFT 4
157 #define CR1_NUM_ICACHELINES_MASK 0xf
159 #define CRD_DATA_WIDTH_SHIFT 0
160 #define CRD_DATA_WIDTH_MASK 0x7
161 #define CRD_WR_CAP_SHIFT 4
162 #define CRD_WR_CAP_MASK 0x7
163 #define CRD_WR_Q_DEP_SHIFT 8
164 #define CRD_WR_Q_DEP_MASK 0xf
165 #define CRD_RD_CAP_SHIFT 12
166 #define CRD_RD_CAP_MASK 0x7
167 #define CRD_RD_Q_DEP_SHIFT 16
168 #define CRD_RD_Q_DEP_MASK 0xf
169 #define CRD_DATA_BUFF_SHIFT 20
170 #define CRD_DATA_BUFF_MASK 0x3ff
173 #define DESIGNER 0x41
175 #define INTEG_CFG 0x0
176 #define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
178 #define PL330_STATE_STOPPED (1 << 0)
179 #define PL330_STATE_EXECUTING (1 << 1)
180 #define PL330_STATE_WFE (1 << 2)
181 #define PL330_STATE_FAULTING (1 << 3)
182 #define PL330_STATE_COMPLETING (1 << 4)
183 #define PL330_STATE_WFP (1 << 5)
184 #define PL330_STATE_KILLING (1 << 6)
185 #define PL330_STATE_FAULT_COMPLETING (1 << 7)
186 #define PL330_STATE_CACHEMISS (1 << 8)
187 #define PL330_STATE_UPDTPC (1 << 9)
188 #define PL330_STATE_ATBARRIER (1 << 10)
189 #define PL330_STATE_QUEUEBUSY (1 << 11)
190 #define PL330_STATE_INVALID (1 << 15)
192 #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
193 | PL330_STATE_WFE | PL330_STATE_FAULTING)
195 #define CMD_DMAADDH 0x54
196 #define CMD_DMAEND 0x00
197 #define CMD_DMAFLUSHP 0x35
198 #define CMD_DMAGO 0xa0
199 #define CMD_DMALD 0x04
200 #define CMD_DMALDP 0x25
201 #define CMD_DMALP 0x20
202 #define CMD_DMALPEND 0x28
203 #define CMD_DMAKILL 0x01
204 #define CMD_DMAMOV 0xbc
205 #define CMD_DMANOP 0x18
206 #define CMD_DMARMB 0x12
207 #define CMD_DMASEV 0x34
208 #define CMD_DMAST 0x08
209 #define CMD_DMASTP 0x29
210 #define CMD_DMASTZ 0x0c
211 #define CMD_DMAWFE 0x36
212 #define CMD_DMAWFP 0x30
213 #define CMD_DMAWMB 0x13
217 #define SZ_DMAFLUSHP 2
221 #define SZ_DMALPEND 2
235 #define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
236 #define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
238 #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
239 #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
242 * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
243 * at 1byte/burst for P<->M and M<->M respectively.
244 * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
245 * should be enough for P<->M and M<->M respectively.
247 #define MCODE_BUFF_PER_REQ 256
249 /* Use this _only_ to wait on transient states */
250 #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
252 #ifdef PL330_DEBUG_MCGEN
253 static unsigned cmd_line
;
254 #define PL330_DBGCMD_DUMP(off, x...) do { \
255 printk("%x:", cmd_line); \
259 #define PL330_DBGMC_START(addr) (cmd_line = addr)
261 #define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
262 #define PL330_DBGMC_START(addr) do {} while (0)
265 /* The number of default descriptors */
267 #define NR_DEFAULT_DESC 16
269 /* Delay for runtime PM autosuspend, ms */
270 #define PL330_AUTOSUSPEND_DELAY 20
272 /* Populated by the PL330 core driver for DMA API driver's info */
273 struct pl330_config
{
275 #define DMAC_MODE_NS (1 << 0)
277 unsigned int data_bus_width
:10; /* In number of bits */
278 unsigned int data_buf_dep
:11;
279 unsigned int num_chan
:4;
280 unsigned int num_peri
:6;
282 unsigned int num_events
:6;
287 * Request Configuration.
288 * The PL330 core does not modify this and uses the last
289 * working configuration if the request doesn't provide any.
291 * The Client may want to provide this info only for the
292 * first request and a request with new settings.
294 struct pl330_reqcfg
{
295 /* Address Incrementing */
300 * For now, the SRC & DST protection levels
301 * and burst size/length are assumed same.
307 unsigned brst_size
:3; /* in power of 2 */
309 enum pl330_cachectrl dcctl
;
310 enum pl330_cachectrl scctl
;
311 enum pl330_byteswap swap
;
312 struct pl330_config
*pcfg
;
316 * One cycle of DMAC operation.
317 * There may be more than one xfer in a request.
326 /* The xfer callbacks are made with one of these arguments. */
328 /* The all xfers in the request were success. */
330 /* If req aborted due to global error. */
332 /* If req failed due to problem with Channel. */
353 struct dma_pl330_desc
;
358 struct dma_pl330_desc
*desc
;
361 /* ToBeDone for tasklet */
369 struct pl330_thread
{
372 /* If the channel is not yet acquired by any client */
375 struct pl330_dmac
*dmac
;
376 /* Only two at a time */
377 struct _pl330_req req
[2];
378 /* Index of the last enqueued request */
380 /* Index of the last submitted request or -1 if the DMA is stopped */
384 enum pl330_dmac_state
{
391 /* In the DMAC pool */
394 * Allocated to some channel during prep_xxx
395 * Also may be sitting on the work_list.
399 * Sitting on the work_list and already submitted
400 * to the PL330 core. Not more than two descriptors
401 * of a channel can be BUSY at any time.
405 * Sitting on the channel work_list but xfer done
411 struct dma_pl330_chan
{
412 /* Schedule desc completion */
413 struct tasklet_struct task
;
415 /* DMA-Engine Channel */
416 struct dma_chan chan
;
418 /* List of submitted descriptors */
419 struct list_head submitted_list
;
420 /* List of issued descriptors */
421 struct list_head work_list
;
422 /* List of completed descriptors */
423 struct list_head completed_list
;
425 /* Pointer to the DMAC that manages this channel,
426 * NULL if the channel is available to be acquired.
427 * As the parent, this DMAC also provides descriptors
430 struct pl330_dmac
*dmac
;
432 /* To protect channel manipulation */
436 * Hardware channel thread of PL330 DMAC. NULL if the channel is
439 struct pl330_thread
*thread
;
441 /* For D-to-M and M-to-D channels */
442 int burst_sz
; /* the peripheral fifo width */
443 int burst_len
; /* the number of burst */
444 dma_addr_t fifo_addr
;
446 /* for cyclic capability */
451 /* DMA-Engine Device */
452 struct dma_device ddma
;
454 /* Holds info about sg limitations */
455 struct device_dma_parameters dma_parms
;
457 /* Pool of descriptors available for the DMAC's channels */
458 struct list_head desc_pool
;
459 /* To protect desc_pool manipulation */
460 spinlock_t pool_lock
;
462 /* Size of MicroCode buffers for each channel. */
464 /* ioremap'ed address of PL330 registers. */
466 /* Populated by the PL330 core driver during pl330_add */
467 struct pl330_config pcfg
;
470 /* Maximum possible events/irqs */
472 /* BUS address of MicroCode buffer */
473 dma_addr_t mcode_bus
;
474 /* CPU address of MicroCode buffer */
476 /* List of all Channel threads */
477 struct pl330_thread
*channels
;
478 /* Pointer to the MANAGER thread */
479 struct pl330_thread
*manager
;
480 /* To handle bad news in interrupt */
481 struct tasklet_struct tasks
;
482 struct _pl330_tbd dmac_tbd
;
483 /* State of DMAC operation */
484 enum pl330_dmac_state state
;
485 /* Holds list of reqs with due callbacks */
486 struct list_head req_done
;
488 /* Peripheral channels connected to this DMAC */
489 unsigned int num_peripherals
;
490 struct dma_pl330_chan
*peripherals
; /* keep at end */
493 struct dma_pl330_desc
{
494 /* To attach to a queue as child */
495 struct list_head node
;
497 /* Descriptor for the DMA Engine API */
498 struct dma_async_tx_descriptor txd
;
500 /* Xfer for PL330 core */
501 struct pl330_xfer px
;
503 struct pl330_reqcfg rqcfg
;
505 enum desc_status status
;
507 /* The channel which currently holds this desc */
508 struct dma_pl330_chan
*pchan
;
510 enum dma_transfer_direction rqtype
;
511 /* Index of peripheral for the xfer. */
513 /* Hook to attach to DMAC's list of reqs with due callback */
514 struct list_head rqd
;
519 struct dma_pl330_desc
*desc
;
522 static inline bool _queue_empty(struct pl330_thread
*thrd
)
524 return thrd
->req
[0].desc
== NULL
&& thrd
->req
[1].desc
== NULL
;
527 static inline bool _queue_full(struct pl330_thread
*thrd
)
529 return thrd
->req
[0].desc
!= NULL
&& thrd
->req
[1].desc
!= NULL
;
532 static inline bool is_manager(struct pl330_thread
*thrd
)
534 return thrd
->dmac
->manager
== thrd
;
537 /* If manager of the thread is in Non-Secure mode */
538 static inline bool _manager_ns(struct pl330_thread
*thrd
)
540 return (thrd
->dmac
->pcfg
.mode
& DMAC_MODE_NS
) ? true : false;
543 static inline u32
get_revision(u32 periph_id
)
545 return (periph_id
>> PERIPH_REV_SHIFT
) & PERIPH_REV_MASK
;
548 static inline u32
_emit_ADDH(unsigned dry_run
, u8 buf
[],
549 enum pl330_dst da
, u16 val
)
554 buf
[0] = CMD_DMAADDH
;
556 *((u16
*)&buf
[1]) = val
;
558 PL330_DBGCMD_DUMP(SZ_DMAADDH
, "\tDMAADDH %s %u\n",
559 da
== 1 ? "DA" : "SA", val
);
564 static inline u32
_emit_END(unsigned dry_run
, u8 buf
[])
571 PL330_DBGCMD_DUMP(SZ_DMAEND
, "\tDMAEND\n");
576 static inline u32
_emit_FLUSHP(unsigned dry_run
, u8 buf
[], u8 peri
)
581 buf
[0] = CMD_DMAFLUSHP
;
587 PL330_DBGCMD_DUMP(SZ_DMAFLUSHP
, "\tDMAFLUSHP %u\n", peri
>> 3);
592 static inline u32
_emit_LD(unsigned dry_run
, u8 buf
[], enum pl330_cond cond
)
600 buf
[0] |= (0 << 1) | (1 << 0);
601 else if (cond
== BURST
)
602 buf
[0] |= (1 << 1) | (1 << 0);
604 PL330_DBGCMD_DUMP(SZ_DMALD
, "\tDMALD%c\n",
605 cond
== SINGLE
? 'S' : (cond
== BURST
? 'B' : 'A'));
610 static inline u32
_emit_LDP(unsigned dry_run
, u8 buf
[],
611 enum pl330_cond cond
, u8 peri
)
625 PL330_DBGCMD_DUMP(SZ_DMALDP
, "\tDMALDP%c %u\n",
626 cond
== SINGLE
? 'S' : 'B', peri
>> 3);
631 static inline u32
_emit_LP(unsigned dry_run
, u8 buf
[],
632 unsigned loop
, u8 cnt
)
642 cnt
--; /* DMAC increments by 1 internally */
645 PL330_DBGCMD_DUMP(SZ_DMALP
, "\tDMALP_%c %u\n", loop
? '1' : '0', cnt
);
651 enum pl330_cond cond
;
657 static inline u32
_emit_LPEND(unsigned dry_run
, u8 buf
[],
658 const struct _arg_LPEND
*arg
)
660 enum pl330_cond cond
= arg
->cond
;
661 bool forever
= arg
->forever
;
662 unsigned loop
= arg
->loop
;
663 u8 bjump
= arg
->bjump
;
668 buf
[0] = CMD_DMALPEND
;
677 buf
[0] |= (0 << 1) | (1 << 0);
678 else if (cond
== BURST
)
679 buf
[0] |= (1 << 1) | (1 << 0);
683 PL330_DBGCMD_DUMP(SZ_DMALPEND
, "\tDMALP%s%c_%c bjmpto_%x\n",
684 forever
? "FE" : "END",
685 cond
== SINGLE
? 'S' : (cond
== BURST
? 'B' : 'A'),
692 static inline u32
_emit_KILL(unsigned dry_run
, u8 buf
[])
697 buf
[0] = CMD_DMAKILL
;
702 static inline u32
_emit_MOV(unsigned dry_run
, u8 buf
[],
703 enum dmamov_dst dst
, u32 val
)
710 *((u32
*)&buf
[2]) = val
;
712 PL330_DBGCMD_DUMP(SZ_DMAMOV
, "\tDMAMOV %s 0x%x\n",
713 dst
== SAR
? "SAR" : (dst
== DAR
? "DAR" : "CCR"), val
);
718 static inline u32
_emit_NOP(unsigned dry_run
, u8 buf
[])
725 PL330_DBGCMD_DUMP(SZ_DMANOP
, "\tDMANOP\n");
730 static inline u32
_emit_RMB(unsigned dry_run
, u8 buf
[])
737 PL330_DBGCMD_DUMP(SZ_DMARMB
, "\tDMARMB\n");
742 static inline u32
_emit_SEV(unsigned dry_run
, u8 buf
[], u8 ev
)
753 PL330_DBGCMD_DUMP(SZ_DMASEV
, "\tDMASEV %u\n", ev
>> 3);
758 static inline u32
_emit_ST(unsigned dry_run
, u8 buf
[], enum pl330_cond cond
)
766 buf
[0] |= (0 << 1) | (1 << 0);
767 else if (cond
== BURST
)
768 buf
[0] |= (1 << 1) | (1 << 0);
770 PL330_DBGCMD_DUMP(SZ_DMAST
, "\tDMAST%c\n",
771 cond
== SINGLE
? 'S' : (cond
== BURST
? 'B' : 'A'));
776 static inline u32
_emit_STP(unsigned dry_run
, u8 buf
[],
777 enum pl330_cond cond
, u8 peri
)
791 PL330_DBGCMD_DUMP(SZ_DMASTP
, "\tDMASTP%c %u\n",
792 cond
== SINGLE
? 'S' : 'B', peri
>> 3);
797 static inline u32
_emit_STZ(unsigned dry_run
, u8 buf
[])
804 PL330_DBGCMD_DUMP(SZ_DMASTZ
, "\tDMASTZ\n");
809 static inline u32
_emit_WFE(unsigned dry_run
, u8 buf
[], u8 ev
,
824 PL330_DBGCMD_DUMP(SZ_DMAWFE
, "\tDMAWFE %u%s\n",
825 ev
>> 3, invalidate
? ", I" : "");
830 static inline u32
_emit_WFP(unsigned dry_run
, u8 buf
[],
831 enum pl330_cond cond
, u8 peri
)
839 buf
[0] |= (0 << 1) | (0 << 0);
840 else if (cond
== BURST
)
841 buf
[0] |= (1 << 1) | (0 << 0);
843 buf
[0] |= (0 << 1) | (1 << 0);
849 PL330_DBGCMD_DUMP(SZ_DMAWFP
, "\tDMAWFP%c %u\n",
850 cond
== SINGLE
? 'S' : (cond
== BURST
? 'B' : 'P'), peri
>> 3);
855 static inline u32
_emit_WMB(unsigned dry_run
, u8 buf
[])
862 PL330_DBGCMD_DUMP(SZ_DMAWMB
, "\tDMAWMB\n");
873 static inline u32
_emit_GO(unsigned dry_run
, u8 buf
[],
874 const struct _arg_GO
*arg
)
877 u32 addr
= arg
->addr
;
878 unsigned ns
= arg
->ns
;
888 *((u32
*)&buf
[2]) = addr
;
893 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
895 /* Returns Time-Out */
896 static bool _until_dmac_idle(struct pl330_thread
*thrd
)
898 void __iomem
*regs
= thrd
->dmac
->base
;
899 unsigned long loops
= msecs_to_loops(5);
902 /* Until Manager is Idle */
903 if (!(readl(regs
+ DBGSTATUS
) & DBG_BUSY
))
915 static inline void _execute_DBGINSN(struct pl330_thread
*thrd
,
916 u8 insn
[], bool as_manager
)
918 void __iomem
*regs
= thrd
->dmac
->base
;
921 val
= (insn
[0] << 16) | (insn
[1] << 24);
924 val
|= (thrd
->id
<< 8); /* Channel Number */
926 writel(val
, regs
+ DBGINST0
);
928 val
= *((u32
*)&insn
[2]);
929 writel(val
, regs
+ DBGINST1
);
931 /* If timed out due to halted state-machine */
932 if (_until_dmac_idle(thrd
)) {
933 dev_err(thrd
->dmac
->ddma
.dev
, "DMAC halted!\n");
938 writel(0, regs
+ DBGCMD
);
941 static inline u32
_state(struct pl330_thread
*thrd
)
943 void __iomem
*regs
= thrd
->dmac
->base
;
946 if (is_manager(thrd
))
947 val
= readl(regs
+ DS
) & 0xf;
949 val
= readl(regs
+ CS(thrd
->id
)) & 0xf;
953 return PL330_STATE_STOPPED
;
955 return PL330_STATE_EXECUTING
;
957 return PL330_STATE_CACHEMISS
;
959 return PL330_STATE_UPDTPC
;
961 return PL330_STATE_WFE
;
963 return PL330_STATE_FAULTING
;
965 if (is_manager(thrd
))
966 return PL330_STATE_INVALID
;
968 return PL330_STATE_ATBARRIER
;
970 if (is_manager(thrd
))
971 return PL330_STATE_INVALID
;
973 return PL330_STATE_QUEUEBUSY
;
975 if (is_manager(thrd
))
976 return PL330_STATE_INVALID
;
978 return PL330_STATE_WFP
;
980 if (is_manager(thrd
))
981 return PL330_STATE_INVALID
;
983 return PL330_STATE_KILLING
;
985 if (is_manager(thrd
))
986 return PL330_STATE_INVALID
;
988 return PL330_STATE_COMPLETING
;
990 if (is_manager(thrd
))
991 return PL330_STATE_INVALID
;
993 return PL330_STATE_FAULT_COMPLETING
;
995 return PL330_STATE_INVALID
;
999 static void _stop(struct pl330_thread
*thrd
)
1001 void __iomem
*regs
= thrd
->dmac
->base
;
1002 u8 insn
[6] = {0, 0, 0, 0, 0, 0};
1004 if (_state(thrd
) == PL330_STATE_FAULT_COMPLETING
)
1005 UNTIL(thrd
, PL330_STATE_FAULTING
| PL330_STATE_KILLING
);
1007 /* Return if nothing needs to be done */
1008 if (_state(thrd
) == PL330_STATE_COMPLETING
1009 || _state(thrd
) == PL330_STATE_KILLING
1010 || _state(thrd
) == PL330_STATE_STOPPED
)
1013 _emit_KILL(0, insn
);
1015 /* Stop generating interrupts for SEV */
1016 writel(readl(regs
+ INTEN
) & ~(1 << thrd
->ev
), regs
+ INTEN
);
1018 _execute_DBGINSN(thrd
, insn
, is_manager(thrd
));
1021 /* Start doing req 'idx' of thread 'thrd' */
1022 static bool _trigger(struct pl330_thread
*thrd
)
1024 void __iomem
*regs
= thrd
->dmac
->base
;
1025 struct _pl330_req
*req
;
1026 struct dma_pl330_desc
*desc
;
1029 u8 insn
[6] = {0, 0, 0, 0, 0, 0};
1032 /* Return if already ACTIVE */
1033 if (_state(thrd
) != PL330_STATE_STOPPED
)
1036 idx
= 1 - thrd
->lstenq
;
1037 if (thrd
->req
[idx
].desc
!= NULL
) {
1038 req
= &thrd
->req
[idx
];
1041 if (thrd
->req
[idx
].desc
!= NULL
)
1042 req
= &thrd
->req
[idx
];
1047 /* Return if no request */
1053 ns
= desc
->rqcfg
.nonsecure
? 1 : 0;
1055 /* See 'Abort Sources' point-4 at Page 2-25 */
1056 if (_manager_ns(thrd
) && !ns
)
1057 dev_info(thrd
->dmac
->ddma
.dev
, "%s:%d Recipe for ABORT!\n",
1058 __func__
, __LINE__
);
1061 go
.addr
= req
->mc_bus
;
1063 _emit_GO(0, insn
, &go
);
1065 /* Set to generate interrupts for SEV */
1066 writel(readl(regs
+ INTEN
) | (1 << thrd
->ev
), regs
+ INTEN
);
1068 /* Only manager can execute GO */
1069 _execute_DBGINSN(thrd
, insn
, true);
1071 thrd
->req_running
= idx
;
1076 static bool _start(struct pl330_thread
*thrd
)
1078 switch (_state(thrd
)) {
1079 case PL330_STATE_FAULT_COMPLETING
:
1080 UNTIL(thrd
, PL330_STATE_FAULTING
| PL330_STATE_KILLING
);
1082 if (_state(thrd
) == PL330_STATE_KILLING
)
1083 UNTIL(thrd
, PL330_STATE_STOPPED
)
1085 case PL330_STATE_FAULTING
:
1088 case PL330_STATE_KILLING
:
1089 case PL330_STATE_COMPLETING
:
1090 UNTIL(thrd
, PL330_STATE_STOPPED
)
1092 case PL330_STATE_STOPPED
:
1093 return _trigger(thrd
);
1095 case PL330_STATE_WFP
:
1096 case PL330_STATE_QUEUEBUSY
:
1097 case PL330_STATE_ATBARRIER
:
1098 case PL330_STATE_UPDTPC
:
1099 case PL330_STATE_CACHEMISS
:
1100 case PL330_STATE_EXECUTING
:
1103 case PL330_STATE_WFE
: /* For RESUME, nothing yet */
1109 static inline int _ldst_memtomem(unsigned dry_run
, u8 buf
[],
1110 const struct _xfer_spec
*pxs
, int cyc
)
1113 struct pl330_config
*pcfg
= pxs
->desc
->rqcfg
.pcfg
;
1115 /* check lock-up free version */
1116 if (get_revision(pcfg
->periph_id
) >= PERIPH_REV_R1P0
) {
1118 off
+= _emit_LD(dry_run
, &buf
[off
], ALWAYS
);
1119 off
+= _emit_ST(dry_run
, &buf
[off
], ALWAYS
);
1123 off
+= _emit_LD(dry_run
, &buf
[off
], ALWAYS
);
1124 off
+= _emit_RMB(dry_run
, &buf
[off
]);
1125 off
+= _emit_ST(dry_run
, &buf
[off
], ALWAYS
);
1126 off
+= _emit_WMB(dry_run
, &buf
[off
]);
1133 static inline int _ldst_devtomem(unsigned dry_run
, u8 buf
[],
1134 const struct _xfer_spec
*pxs
, int cyc
)
1139 off
+= _emit_WFP(dry_run
, &buf
[off
], SINGLE
, pxs
->desc
->peri
);
1140 off
+= _emit_LDP(dry_run
, &buf
[off
], SINGLE
, pxs
->desc
->peri
);
1141 off
+= _emit_ST(dry_run
, &buf
[off
], ALWAYS
);
1142 off
+= _emit_FLUSHP(dry_run
, &buf
[off
], pxs
->desc
->peri
);
1148 static inline int _ldst_memtodev(unsigned dry_run
, u8 buf
[],
1149 const struct _xfer_spec
*pxs
, int cyc
)
1154 off
+= _emit_WFP(dry_run
, &buf
[off
], SINGLE
, pxs
->desc
->peri
);
1155 off
+= _emit_LD(dry_run
, &buf
[off
], ALWAYS
);
1156 off
+= _emit_STP(dry_run
, &buf
[off
], SINGLE
, pxs
->desc
->peri
);
1157 off
+= _emit_FLUSHP(dry_run
, &buf
[off
], pxs
->desc
->peri
);
1163 static int _bursts(unsigned dry_run
, u8 buf
[],
1164 const struct _xfer_spec
*pxs
, int cyc
)
1168 switch (pxs
->desc
->rqtype
) {
1169 case DMA_MEM_TO_DEV
:
1170 off
+= _ldst_memtodev(dry_run
, &buf
[off
], pxs
, cyc
);
1172 case DMA_DEV_TO_MEM
:
1173 off
+= _ldst_devtomem(dry_run
, &buf
[off
], pxs
, cyc
);
1175 case DMA_MEM_TO_MEM
:
1176 off
+= _ldst_memtomem(dry_run
, &buf
[off
], pxs
, cyc
);
1179 off
+= 0x40000000; /* Scare off the Client */
1186 /* Returns bytes consumed and updates bursts */
1187 static inline int _loop(unsigned dry_run
, u8 buf
[],
1188 unsigned long *bursts
, const struct _xfer_spec
*pxs
)
1190 int cyc
, cycmax
, szlp
, szlpend
, szbrst
, off
;
1191 unsigned lcnt0
, lcnt1
, ljmp0
, ljmp1
;
1192 struct _arg_LPEND lpend
;
1194 /* Max iterations possible in DMALP is 256 */
1195 if (*bursts
>= 256*256) {
1198 cyc
= *bursts
/ lcnt1
/ lcnt0
;
1199 } else if (*bursts
> 256) {
1201 lcnt0
= *bursts
/ lcnt1
;
1209 szlp
= _emit_LP(1, buf
, 0, 0);
1210 szbrst
= _bursts(1, buf
, pxs
, 1);
1212 lpend
.cond
= ALWAYS
;
1213 lpend
.forever
= false;
1216 szlpend
= _emit_LPEND(1, buf
, &lpend
);
1224 * Max bursts that we can unroll due to limit on the
1225 * size of backward jump that can be encoded in DMALPEND
1226 * which is 8-bits and hence 255
1228 cycmax
= (255 - (szlp
+ szlpend
)) / szbrst
;
1230 cyc
= (cycmax
< cyc
) ? cycmax
: cyc
;
1235 off
+= _emit_LP(dry_run
, &buf
[off
], 0, lcnt0
);
1239 off
+= _emit_LP(dry_run
, &buf
[off
], 1, lcnt1
);
1242 off
+= _bursts(dry_run
, &buf
[off
], pxs
, cyc
);
1244 lpend
.cond
= ALWAYS
;
1245 lpend
.forever
= false;
1247 lpend
.bjump
= off
- ljmp1
;
1248 off
+= _emit_LPEND(dry_run
, &buf
[off
], &lpend
);
1251 lpend
.cond
= ALWAYS
;
1252 lpend
.forever
= false;
1254 lpend
.bjump
= off
- ljmp0
;
1255 off
+= _emit_LPEND(dry_run
, &buf
[off
], &lpend
);
1258 *bursts
= lcnt1
* cyc
;
1265 static inline int _setup_loops(unsigned dry_run
, u8 buf
[],
1266 const struct _xfer_spec
*pxs
)
1268 struct pl330_xfer
*x
= &pxs
->desc
->px
;
1270 unsigned long c
, bursts
= BYTE_TO_BURST(x
->bytes
, ccr
);
1275 off
+= _loop(dry_run
, &buf
[off
], &c
, pxs
);
1282 static inline int _setup_xfer(unsigned dry_run
, u8 buf
[],
1283 const struct _xfer_spec
*pxs
)
1285 struct pl330_xfer
*x
= &pxs
->desc
->px
;
1288 /* DMAMOV SAR, x->src_addr */
1289 off
+= _emit_MOV(dry_run
, &buf
[off
], SAR
, x
->src_addr
);
1290 /* DMAMOV DAR, x->dst_addr */
1291 off
+= _emit_MOV(dry_run
, &buf
[off
], DAR
, x
->dst_addr
);
1294 off
+= _setup_loops(dry_run
, &buf
[off
], pxs
);
1300 * A req is a sequence of one or more xfer units.
1301 * Returns the number of bytes taken to setup the MC for the req.
1303 static int _setup_req(unsigned dry_run
, struct pl330_thread
*thrd
,
1304 unsigned index
, struct _xfer_spec
*pxs
)
1306 struct _pl330_req
*req
= &thrd
->req
[index
];
1307 struct pl330_xfer
*x
;
1308 u8
*buf
= req
->mc_cpu
;
1311 PL330_DBGMC_START(req
->mc_bus
);
1313 /* DMAMOV CCR, ccr */
1314 off
+= _emit_MOV(dry_run
, &buf
[off
], CCR
, pxs
->ccr
);
1317 /* Error if xfer length is not aligned at burst size */
1318 if (x
->bytes
% (BRST_SIZE(pxs
->ccr
) * BRST_LEN(pxs
->ccr
)))
1321 off
+= _setup_xfer(dry_run
, &buf
[off
], pxs
);
1323 /* DMASEV peripheral/event */
1324 off
+= _emit_SEV(dry_run
, &buf
[off
], thrd
->ev
);
1326 off
+= _emit_END(dry_run
, &buf
[off
]);
1331 static inline u32
_prepare_ccr(const struct pl330_reqcfg
*rqc
)
1341 /* We set same protection levels for Src and DST for now */
1342 if (rqc
->privileged
)
1343 ccr
|= CC_SRCPRI
| CC_DSTPRI
;
1345 ccr
|= CC_SRCNS
| CC_DSTNS
;
1346 if (rqc
->insnaccess
)
1347 ccr
|= CC_SRCIA
| CC_DSTIA
;
1349 ccr
|= (((rqc
->brst_len
- 1) & 0xf) << CC_SRCBRSTLEN_SHFT
);
1350 ccr
|= (((rqc
->brst_len
- 1) & 0xf) << CC_DSTBRSTLEN_SHFT
);
1352 ccr
|= (rqc
->brst_size
<< CC_SRCBRSTSIZE_SHFT
);
1353 ccr
|= (rqc
->brst_size
<< CC_DSTBRSTSIZE_SHFT
);
1355 ccr
|= (rqc
->scctl
<< CC_SRCCCTRL_SHFT
);
1356 ccr
|= (rqc
->dcctl
<< CC_DSTCCTRL_SHFT
);
1358 ccr
|= (rqc
->swap
<< CC_SWAP_SHFT
);
1364 * Submit a list of xfers after which the client wants notification.
1365 * Client is not notified after each xfer unit, just once after all
1366 * xfer units are done or some error occurs.
1368 static int pl330_submit_req(struct pl330_thread
*thrd
,
1369 struct dma_pl330_desc
*desc
)
1371 struct pl330_dmac
*pl330
= thrd
->dmac
;
1372 struct _xfer_spec xs
;
1373 unsigned long flags
;
1378 if (pl330
->state
== DYING
1379 || pl330
->dmac_tbd
.reset_chan
& (1 << thrd
->id
)) {
1380 dev_info(thrd
->dmac
->ddma
.dev
, "%s:%d\n",
1381 __func__
, __LINE__
);
1385 /* If request for non-existing peripheral */
1386 if (desc
->rqtype
!= DMA_MEM_TO_MEM
&&
1387 desc
->peri
>= pl330
->pcfg
.num_peri
) {
1388 dev_info(thrd
->dmac
->ddma
.dev
,
1389 "%s:%d Invalid peripheral(%u)!\n",
1390 __func__
, __LINE__
, desc
->peri
);
1394 spin_lock_irqsave(&pl330
->lock
, flags
);
1396 if (_queue_full(thrd
)) {
1401 /* Prefer Secure Channel */
1402 if (!_manager_ns(thrd
))
1403 desc
->rqcfg
.nonsecure
= 0;
1405 desc
->rqcfg
.nonsecure
= 1;
1407 ccr
= _prepare_ccr(&desc
->rqcfg
);
1409 idx
= thrd
->req
[0].desc
== NULL
? 0 : 1;
1414 /* First dry run to check if req is acceptable */
1415 ret
= _setup_req(1, thrd
, idx
, &xs
);
1419 if (ret
> pl330
->mcbufsz
/ 2) {
1420 dev_info(pl330
->ddma
.dev
, "%s:%d Trying increasing mcbufsz\n",
1421 __func__
, __LINE__
);
1426 /* Hook the request */
1428 thrd
->req
[idx
].desc
= desc
;
1429 _setup_req(0, thrd
, idx
, &xs
);
1434 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1439 static void dma_pl330_rqcb(struct dma_pl330_desc
*desc
, enum pl330_op_err err
)
1441 struct dma_pl330_chan
*pch
;
1442 unsigned long flags
;
1449 /* If desc aborted */
1453 spin_lock_irqsave(&pch
->lock
, flags
);
1455 desc
->status
= DONE
;
1457 spin_unlock_irqrestore(&pch
->lock
, flags
);
1459 tasklet_schedule(&pch
->task
);
1462 static void pl330_dotask(unsigned long data
)
1464 struct pl330_dmac
*pl330
= (struct pl330_dmac
*) data
;
1465 unsigned long flags
;
1468 spin_lock_irqsave(&pl330
->lock
, flags
);
1470 /* The DMAC itself gone nuts */
1471 if (pl330
->dmac_tbd
.reset_dmac
) {
1472 pl330
->state
= DYING
;
1473 /* Reset the manager too */
1474 pl330
->dmac_tbd
.reset_mngr
= true;
1475 /* Clear the reset flag */
1476 pl330
->dmac_tbd
.reset_dmac
= false;
1479 if (pl330
->dmac_tbd
.reset_mngr
) {
1480 _stop(pl330
->manager
);
1481 /* Reset all channels */
1482 pl330
->dmac_tbd
.reset_chan
= (1 << pl330
->pcfg
.num_chan
) - 1;
1483 /* Clear the reset flag */
1484 pl330
->dmac_tbd
.reset_mngr
= false;
1487 for (i
= 0; i
< pl330
->pcfg
.num_chan
; i
++) {
1489 if (pl330
->dmac_tbd
.reset_chan
& (1 << i
)) {
1490 struct pl330_thread
*thrd
= &pl330
->channels
[i
];
1491 void __iomem
*regs
= pl330
->base
;
1492 enum pl330_op_err err
;
1496 if (readl(regs
+ FSC
) & (1 << thrd
->id
))
1497 err
= PL330_ERR_FAIL
;
1499 err
= PL330_ERR_ABORT
;
1501 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1502 dma_pl330_rqcb(thrd
->req
[1 - thrd
->lstenq
].desc
, err
);
1503 dma_pl330_rqcb(thrd
->req
[thrd
->lstenq
].desc
, err
);
1504 spin_lock_irqsave(&pl330
->lock
, flags
);
1506 thrd
->req
[0].desc
= NULL
;
1507 thrd
->req
[1].desc
= NULL
;
1508 thrd
->req_running
= -1;
1510 /* Clear the reset flag */
1511 pl330
->dmac_tbd
.reset_chan
&= ~(1 << i
);
1515 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1520 /* Returns 1 if state was updated, 0 otherwise */
1521 static int pl330_update(struct pl330_dmac
*pl330
)
1523 struct dma_pl330_desc
*descdone
, *tmp
;
1524 unsigned long flags
;
1527 int id
, ev
, ret
= 0;
1531 spin_lock_irqsave(&pl330
->lock
, flags
);
1533 val
= readl(regs
+ FSM
) & 0x1;
1535 pl330
->dmac_tbd
.reset_mngr
= true;
1537 pl330
->dmac_tbd
.reset_mngr
= false;
1539 val
= readl(regs
+ FSC
) & ((1 << pl330
->pcfg
.num_chan
) - 1);
1540 pl330
->dmac_tbd
.reset_chan
|= val
;
1543 while (i
< pl330
->pcfg
.num_chan
) {
1544 if (val
& (1 << i
)) {
1545 dev_info(pl330
->ddma
.dev
,
1546 "Reset Channel-%d\t CS-%x FTC-%x\n",
1547 i
, readl(regs
+ CS(i
)),
1548 readl(regs
+ FTC(i
)));
1549 _stop(&pl330
->channels
[i
]);
1555 /* Check which event happened i.e, thread notified */
1556 val
= readl(regs
+ ES
);
1557 if (pl330
->pcfg
.num_events
< 32
1558 && val
& ~((1 << pl330
->pcfg
.num_events
) - 1)) {
1559 pl330
->dmac_tbd
.reset_dmac
= true;
1560 dev_err(pl330
->ddma
.dev
, "%s:%d Unexpected!\n", __func__
,
1566 for (ev
= 0; ev
< pl330
->pcfg
.num_events
; ev
++) {
1567 if (val
& (1 << ev
)) { /* Event occurred */
1568 struct pl330_thread
*thrd
;
1569 u32 inten
= readl(regs
+ INTEN
);
1572 /* Clear the event */
1573 if (inten
& (1 << ev
))
1574 writel(1 << ev
, regs
+ INTCLR
);
1578 id
= pl330
->events
[ev
];
1580 thrd
= &pl330
->channels
[id
];
1582 active
= thrd
->req_running
;
1583 if (active
== -1) /* Aborted */
1586 /* Detach the req */
1587 descdone
= thrd
->req
[active
].desc
;
1588 thrd
->req
[active
].desc
= NULL
;
1590 /* Get going again ASAP */
1593 /* For now, just make a list of callbacks to be done */
1594 list_add_tail(&descdone
->rqd
, &pl330
->req_done
);
1598 /* Now that we are in no hurry, do the callbacks */
1599 list_for_each_entry_safe(descdone
, tmp
, &pl330
->req_done
, rqd
) {
1600 list_del(&descdone
->rqd
);
1601 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1602 dma_pl330_rqcb(descdone
, PL330_ERR_NONE
);
1603 spin_lock_irqsave(&pl330
->lock
, flags
);
1607 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1609 if (pl330
->dmac_tbd
.reset_dmac
1610 || pl330
->dmac_tbd
.reset_mngr
1611 || pl330
->dmac_tbd
.reset_chan
) {
1613 tasklet_schedule(&pl330
->tasks
);
1619 /* Reserve an event */
1620 static inline int _alloc_event(struct pl330_thread
*thrd
)
1622 struct pl330_dmac
*pl330
= thrd
->dmac
;
1625 for (ev
= 0; ev
< pl330
->pcfg
.num_events
; ev
++)
1626 if (pl330
->events
[ev
] == -1) {
1627 pl330
->events
[ev
] = thrd
->id
;
1634 static bool _chan_ns(const struct pl330_dmac
*pl330
, int i
)
1636 return pl330
->pcfg
.irq_ns
& (1 << i
);
1639 /* Upon success, returns IdentityToken for the
1640 * allocated channel, NULL otherwise.
1642 static struct pl330_thread
*pl330_request_channel(struct pl330_dmac
*pl330
)
1644 struct pl330_thread
*thrd
= NULL
;
1645 unsigned long flags
;
1648 if (pl330
->state
== DYING
)
1651 chans
= pl330
->pcfg
.num_chan
;
1653 spin_lock_irqsave(&pl330
->lock
, flags
);
1655 for (i
= 0; i
< chans
; i
++) {
1656 thrd
= &pl330
->channels
[i
];
1657 if ((thrd
->free
) && (!_manager_ns(thrd
) ||
1658 _chan_ns(pl330
, i
))) {
1659 thrd
->ev
= _alloc_event(thrd
);
1660 if (thrd
->ev
>= 0) {
1663 thrd
->req
[0].desc
= NULL
;
1664 thrd
->req
[1].desc
= NULL
;
1665 thrd
->req_running
= -1;
1672 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1677 /* Release an event */
1678 static inline void _free_event(struct pl330_thread
*thrd
, int ev
)
1680 struct pl330_dmac
*pl330
= thrd
->dmac
;
1682 /* If the event is valid and was held by the thread */
1683 if (ev
>= 0 && ev
< pl330
->pcfg
.num_events
1684 && pl330
->events
[ev
] == thrd
->id
)
1685 pl330
->events
[ev
] = -1;
1688 static void pl330_release_channel(struct pl330_thread
*thrd
)
1690 struct pl330_dmac
*pl330
;
1691 unsigned long flags
;
1693 if (!thrd
|| thrd
->free
)
1698 dma_pl330_rqcb(thrd
->req
[1 - thrd
->lstenq
].desc
, PL330_ERR_ABORT
);
1699 dma_pl330_rqcb(thrd
->req
[thrd
->lstenq
].desc
, PL330_ERR_ABORT
);
1703 spin_lock_irqsave(&pl330
->lock
, flags
);
1704 _free_event(thrd
, thrd
->ev
);
1706 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1709 /* Initialize the structure for PL330 configuration, that can be used
1710 * by the client driver the make best use of the DMAC
1712 static void read_dmac_config(struct pl330_dmac
*pl330
)
1714 void __iomem
*regs
= pl330
->base
;
1717 val
= readl(regs
+ CRD
) >> CRD_DATA_WIDTH_SHIFT
;
1718 val
&= CRD_DATA_WIDTH_MASK
;
1719 pl330
->pcfg
.data_bus_width
= 8 * (1 << val
);
1721 val
= readl(regs
+ CRD
) >> CRD_DATA_BUFF_SHIFT
;
1722 val
&= CRD_DATA_BUFF_MASK
;
1723 pl330
->pcfg
.data_buf_dep
= val
+ 1;
1725 val
= readl(regs
+ CR0
) >> CR0_NUM_CHANS_SHIFT
;
1726 val
&= CR0_NUM_CHANS_MASK
;
1728 pl330
->pcfg
.num_chan
= val
;
1730 val
= readl(regs
+ CR0
);
1731 if (val
& CR0_PERIPH_REQ_SET
) {
1732 val
= (val
>> CR0_NUM_PERIPH_SHIFT
) & CR0_NUM_PERIPH_MASK
;
1734 pl330
->pcfg
.num_peri
= val
;
1735 pl330
->pcfg
.peri_ns
= readl(regs
+ CR4
);
1737 pl330
->pcfg
.num_peri
= 0;
1740 val
= readl(regs
+ CR0
);
1741 if (val
& CR0_BOOT_MAN_NS
)
1742 pl330
->pcfg
.mode
|= DMAC_MODE_NS
;
1744 pl330
->pcfg
.mode
&= ~DMAC_MODE_NS
;
1746 val
= readl(regs
+ CR0
) >> CR0_NUM_EVENTS_SHIFT
;
1747 val
&= CR0_NUM_EVENTS_MASK
;
1749 pl330
->pcfg
.num_events
= val
;
1751 pl330
->pcfg
.irq_ns
= readl(regs
+ CR3
);
1754 static inline void _reset_thread(struct pl330_thread
*thrd
)
1756 struct pl330_dmac
*pl330
= thrd
->dmac
;
1758 thrd
->req
[0].mc_cpu
= pl330
->mcode_cpu
1759 + (thrd
->id
* pl330
->mcbufsz
);
1760 thrd
->req
[0].mc_bus
= pl330
->mcode_bus
1761 + (thrd
->id
* pl330
->mcbufsz
);
1762 thrd
->req
[0].desc
= NULL
;
1764 thrd
->req
[1].mc_cpu
= thrd
->req
[0].mc_cpu
1765 + pl330
->mcbufsz
/ 2;
1766 thrd
->req
[1].mc_bus
= thrd
->req
[0].mc_bus
1767 + pl330
->mcbufsz
/ 2;
1768 thrd
->req
[1].desc
= NULL
;
1770 thrd
->req_running
= -1;
1773 static int dmac_alloc_threads(struct pl330_dmac
*pl330
)
1775 int chans
= pl330
->pcfg
.num_chan
;
1776 struct pl330_thread
*thrd
;
1779 /* Allocate 1 Manager and 'chans' Channel threads */
1780 pl330
->channels
= kzalloc((1 + chans
) * sizeof(*thrd
),
1782 if (!pl330
->channels
)
1785 /* Init Channel threads */
1786 for (i
= 0; i
< chans
; i
++) {
1787 thrd
= &pl330
->channels
[i
];
1790 _reset_thread(thrd
);
1794 /* MANAGER is indexed at the end */
1795 thrd
= &pl330
->channels
[chans
];
1799 pl330
->manager
= thrd
;
1804 static int dmac_alloc_resources(struct pl330_dmac
*pl330
)
1806 int chans
= pl330
->pcfg
.num_chan
;
1810 * Alloc MicroCode buffer for 'chans' Channel threads.
1811 * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
1813 pl330
->mcode_cpu
= dma_alloc_coherent(pl330
->ddma
.dev
,
1814 chans
* pl330
->mcbufsz
,
1815 &pl330
->mcode_bus
, GFP_KERNEL
);
1816 if (!pl330
->mcode_cpu
) {
1817 dev_err(pl330
->ddma
.dev
, "%s:%d Can't allocate memory!\n",
1818 __func__
, __LINE__
);
1822 ret
= dmac_alloc_threads(pl330
);
1824 dev_err(pl330
->ddma
.dev
, "%s:%d Can't to create channels for DMAC!\n",
1825 __func__
, __LINE__
);
1826 dma_free_coherent(pl330
->ddma
.dev
,
1827 chans
* pl330
->mcbufsz
,
1828 pl330
->mcode_cpu
, pl330
->mcode_bus
);
1835 static int pl330_add(struct pl330_dmac
*pl330
)
1842 /* Check if we can handle this DMAC */
1843 if ((pl330
->pcfg
.periph_id
& 0xfffff) != PERIPH_ID_VAL
) {
1844 dev_err(pl330
->ddma
.dev
, "PERIPH_ID 0x%x !\n",
1845 pl330
->pcfg
.periph_id
);
1849 /* Read the configuration of the DMAC */
1850 read_dmac_config(pl330
);
1852 if (pl330
->pcfg
.num_events
== 0) {
1853 dev_err(pl330
->ddma
.dev
, "%s:%d Can't work without events!\n",
1854 __func__
, __LINE__
);
1858 spin_lock_init(&pl330
->lock
);
1860 INIT_LIST_HEAD(&pl330
->req_done
);
1862 /* Use default MC buffer size if not provided */
1863 if (!pl330
->mcbufsz
)
1864 pl330
->mcbufsz
= MCODE_BUFF_PER_REQ
* 2;
1866 /* Mark all events as free */
1867 for (i
= 0; i
< pl330
->pcfg
.num_events
; i
++)
1868 pl330
->events
[i
] = -1;
1870 /* Allocate resources needed by the DMAC */
1871 ret
= dmac_alloc_resources(pl330
);
1873 dev_err(pl330
->ddma
.dev
, "Unable to create channels for DMAC\n");
1877 tasklet_init(&pl330
->tasks
, pl330_dotask
, (unsigned long) pl330
);
1879 pl330
->state
= INIT
;
1884 static int dmac_free_threads(struct pl330_dmac
*pl330
)
1886 struct pl330_thread
*thrd
;
1889 /* Release Channel threads */
1890 for (i
= 0; i
< pl330
->pcfg
.num_chan
; i
++) {
1891 thrd
= &pl330
->channels
[i
];
1892 pl330_release_channel(thrd
);
1896 kfree(pl330
->channels
);
1901 static void pl330_del(struct pl330_dmac
*pl330
)
1903 pl330
->state
= UNINIT
;
1905 tasklet_kill(&pl330
->tasks
);
1907 /* Free DMAC resources */
1908 dmac_free_threads(pl330
);
1910 dma_free_coherent(pl330
->ddma
.dev
,
1911 pl330
->pcfg
.num_chan
* pl330
->mcbufsz
, pl330
->mcode_cpu
,
1915 /* forward declaration */
1916 static struct amba_driver pl330_driver
;
1918 static inline struct dma_pl330_chan
*
1919 to_pchan(struct dma_chan
*ch
)
1924 return container_of(ch
, struct dma_pl330_chan
, chan
);
1927 static inline struct dma_pl330_desc
*
1928 to_desc(struct dma_async_tx_descriptor
*tx
)
1930 return container_of(tx
, struct dma_pl330_desc
, txd
);
1933 static inline void fill_queue(struct dma_pl330_chan
*pch
)
1935 struct dma_pl330_desc
*desc
;
1938 list_for_each_entry(desc
, &pch
->work_list
, node
) {
1940 /* If already submitted */
1941 if (desc
->status
== BUSY
)
1944 ret
= pl330_submit_req(pch
->thread
, desc
);
1946 desc
->status
= BUSY
;
1947 } else if (ret
== -EAGAIN
) {
1948 /* QFull or DMAC Dying */
1951 /* Unacceptable request */
1952 desc
->status
= DONE
;
1953 dev_err(pch
->dmac
->ddma
.dev
, "%s:%d Bad Desc(%d)\n",
1954 __func__
, __LINE__
, desc
->txd
.cookie
);
1955 tasklet_schedule(&pch
->task
);
1960 static void pl330_tasklet(unsigned long data
)
1962 struct dma_pl330_chan
*pch
= (struct dma_pl330_chan
*)data
;
1963 struct dma_pl330_desc
*desc
, *_dt
;
1964 unsigned long flags
;
1965 bool power_down
= false;
1967 spin_lock_irqsave(&pch
->lock
, flags
);
1969 /* Pick up ripe tomatoes */
1970 list_for_each_entry_safe(desc
, _dt
, &pch
->work_list
, node
)
1971 if (desc
->status
== DONE
) {
1973 dma_cookie_complete(&desc
->txd
);
1974 list_move_tail(&desc
->node
, &pch
->completed_list
);
1977 /* Try to submit a req imm. next to the last completed cookie */
1980 if (list_empty(&pch
->work_list
)) {
1981 spin_lock(&pch
->thread
->dmac
->lock
);
1983 spin_unlock(&pch
->thread
->dmac
->lock
);
1986 /* Make sure the PL330 Channel thread is active */
1987 spin_lock(&pch
->thread
->dmac
->lock
);
1988 _start(pch
->thread
);
1989 spin_unlock(&pch
->thread
->dmac
->lock
);
1992 while (!list_empty(&pch
->completed_list
)) {
1993 dma_async_tx_callback callback
;
1994 void *callback_param
;
1996 desc
= list_first_entry(&pch
->completed_list
,
1997 struct dma_pl330_desc
, node
);
1999 callback
= desc
->txd
.callback
;
2000 callback_param
= desc
->txd
.callback_param
;
2003 desc
->status
= PREP
;
2004 list_move_tail(&desc
->node
, &pch
->work_list
);
2006 spin_lock(&pch
->thread
->dmac
->lock
);
2007 _start(pch
->thread
);
2008 spin_unlock(&pch
->thread
->dmac
->lock
);
2012 desc
->status
= FREE
;
2013 list_move_tail(&desc
->node
, &pch
->dmac
->desc_pool
);
2016 dma_descriptor_unmap(&desc
->txd
);
2019 spin_unlock_irqrestore(&pch
->lock
, flags
);
2020 callback(callback_param
);
2021 spin_lock_irqsave(&pch
->lock
, flags
);
2024 spin_unlock_irqrestore(&pch
->lock
, flags
);
2026 /* If work list empty, power down */
2028 pm_runtime_mark_last_busy(pch
->dmac
->ddma
.dev
);
2029 pm_runtime_put_autosuspend(pch
->dmac
->ddma
.dev
);
2033 bool pl330_filter(struct dma_chan
*chan
, void *param
)
2037 if (chan
->device
->dev
->driver
!= &pl330_driver
.drv
)
2040 peri_id
= chan
->private;
2041 return *peri_id
== (unsigned long)param
;
2043 EXPORT_SYMBOL(pl330_filter
);
2045 static struct dma_chan
*of_dma_pl330_xlate(struct of_phandle_args
*dma_spec
,
2046 struct of_dma
*ofdma
)
2048 int count
= dma_spec
->args_count
;
2049 struct pl330_dmac
*pl330
= ofdma
->of_dma_data
;
2050 unsigned int chan_id
;
2058 chan_id
= dma_spec
->args
[0];
2059 if (chan_id
>= pl330
->num_peripherals
)
2062 return dma_get_slave_channel(&pl330
->peripherals
[chan_id
].chan
);
2065 static int pl330_alloc_chan_resources(struct dma_chan
*chan
)
2067 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2068 struct pl330_dmac
*pl330
= pch
->dmac
;
2069 unsigned long flags
;
2071 spin_lock_irqsave(&pch
->lock
, flags
);
2073 dma_cookie_init(chan
);
2074 pch
->cyclic
= false;
2076 pch
->thread
= pl330_request_channel(pl330
);
2078 spin_unlock_irqrestore(&pch
->lock
, flags
);
2082 tasklet_init(&pch
->task
, pl330_tasklet
, (unsigned long) pch
);
2084 spin_unlock_irqrestore(&pch
->lock
, flags
);
2089 static int pl330_control(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
, unsigned long arg
)
2091 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2092 struct dma_pl330_desc
*desc
;
2093 unsigned long flags
;
2094 struct pl330_dmac
*pl330
= pch
->dmac
;
2095 struct dma_slave_config
*slave_config
;
2099 case DMA_TERMINATE_ALL
:
2100 pm_runtime_get_sync(pl330
->ddma
.dev
);
2101 spin_lock_irqsave(&pch
->lock
, flags
);
2103 spin_lock(&pl330
->lock
);
2105 spin_unlock(&pl330
->lock
);
2107 pch
->thread
->req
[0].desc
= NULL
;
2108 pch
->thread
->req
[1].desc
= NULL
;
2109 pch
->thread
->req_running
= -1;
2111 /* Mark all desc done */
2112 list_for_each_entry(desc
, &pch
->submitted_list
, node
) {
2113 desc
->status
= FREE
;
2114 dma_cookie_complete(&desc
->txd
);
2117 list_for_each_entry(desc
, &pch
->work_list
, node
) {
2118 desc
->status
= FREE
;
2119 dma_cookie_complete(&desc
->txd
);
2122 list_for_each_entry(desc
, &pch
->completed_list
, node
) {
2123 desc
->status
= FREE
;
2124 dma_cookie_complete(&desc
->txd
);
2127 if (!list_empty(&pch
->work_list
))
2128 pm_runtime_put(pl330
->ddma
.dev
);
2130 list_splice_tail_init(&pch
->submitted_list
, &pl330
->desc_pool
);
2131 list_splice_tail_init(&pch
->work_list
, &pl330
->desc_pool
);
2132 list_splice_tail_init(&pch
->completed_list
, &pl330
->desc_pool
);
2133 spin_unlock_irqrestore(&pch
->lock
, flags
);
2134 pm_runtime_mark_last_busy(pl330
->ddma
.dev
);
2135 pm_runtime_put_autosuspend(pl330
->ddma
.dev
);
2137 case DMA_SLAVE_CONFIG
:
2138 slave_config
= (struct dma_slave_config
*)arg
;
2140 if (slave_config
->direction
== DMA_MEM_TO_DEV
) {
2141 if (slave_config
->dst_addr
)
2142 pch
->fifo_addr
= slave_config
->dst_addr
;
2143 if (slave_config
->dst_addr_width
)
2144 pch
->burst_sz
= __ffs(slave_config
->dst_addr_width
);
2145 if (slave_config
->dst_maxburst
)
2146 pch
->burst_len
= slave_config
->dst_maxburst
;
2147 } else if (slave_config
->direction
== DMA_DEV_TO_MEM
) {
2148 if (slave_config
->src_addr
)
2149 pch
->fifo_addr
= slave_config
->src_addr
;
2150 if (slave_config
->src_addr_width
)
2151 pch
->burst_sz
= __ffs(slave_config
->src_addr_width
);
2152 if (slave_config
->src_maxburst
)
2153 pch
->burst_len
= slave_config
->src_maxburst
;
2157 dev_err(pch
->dmac
->ddma
.dev
, "Not supported command.\n");
2164 static void pl330_free_chan_resources(struct dma_chan
*chan
)
2166 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2167 unsigned long flags
;
2169 tasklet_kill(&pch
->task
);
2171 pm_runtime_get_sync(pch
->dmac
->ddma
.dev
);
2172 spin_lock_irqsave(&pch
->lock
, flags
);
2174 pl330_release_channel(pch
->thread
);
2178 list_splice_tail_init(&pch
->work_list
, &pch
->dmac
->desc_pool
);
2180 spin_unlock_irqrestore(&pch
->lock
, flags
);
2181 pm_runtime_mark_last_busy(pch
->dmac
->ddma
.dev
);
2182 pm_runtime_put_autosuspend(pch
->dmac
->ddma
.dev
);
2185 static enum dma_status
2186 pl330_tx_status(struct dma_chan
*chan
, dma_cookie_t cookie
,
2187 struct dma_tx_state
*txstate
)
2189 return dma_cookie_status(chan
, cookie
, txstate
);
2192 static void pl330_issue_pending(struct dma_chan
*chan
)
2194 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2195 unsigned long flags
;
2197 spin_lock_irqsave(&pch
->lock
, flags
);
2198 if (list_empty(&pch
->work_list
)) {
2200 * Warn on nothing pending. Empty submitted_list may
2201 * break our pm_runtime usage counter as it is
2202 * updated on work_list emptiness status.
2204 WARN_ON(list_empty(&pch
->submitted_list
));
2205 pm_runtime_get_sync(pch
->dmac
->ddma
.dev
);
2207 list_splice_tail_init(&pch
->submitted_list
, &pch
->work_list
);
2208 spin_unlock_irqrestore(&pch
->lock
, flags
);
2210 pl330_tasklet((unsigned long)pch
);
2214 * We returned the last one of the circular list of descriptor(s)
2215 * from prep_xxx, so the argument to submit corresponds to the last
2216 * descriptor of the list.
2218 static dma_cookie_t
pl330_tx_submit(struct dma_async_tx_descriptor
*tx
)
2220 struct dma_pl330_desc
*desc
, *last
= to_desc(tx
);
2221 struct dma_pl330_chan
*pch
= to_pchan(tx
->chan
);
2222 dma_cookie_t cookie
;
2223 unsigned long flags
;
2225 spin_lock_irqsave(&pch
->lock
, flags
);
2227 /* Assign cookies to all nodes */
2228 while (!list_empty(&last
->node
)) {
2229 desc
= list_entry(last
->node
.next
, struct dma_pl330_desc
, node
);
2231 desc
->txd
.callback
= last
->txd
.callback
;
2232 desc
->txd
.callback_param
= last
->txd
.callback_param
;
2235 dma_cookie_assign(&desc
->txd
);
2237 list_move_tail(&desc
->node
, &pch
->submitted_list
);
2240 cookie
= dma_cookie_assign(&last
->txd
);
2241 list_add_tail(&last
->node
, &pch
->submitted_list
);
2242 spin_unlock_irqrestore(&pch
->lock
, flags
);
2247 static inline void _init_desc(struct dma_pl330_desc
*desc
)
2249 desc
->rqcfg
.swap
= SWAP_NO
;
2250 desc
->rqcfg
.scctl
= CCTRL0
;
2251 desc
->rqcfg
.dcctl
= CCTRL0
;
2252 desc
->txd
.tx_submit
= pl330_tx_submit
;
2254 INIT_LIST_HEAD(&desc
->node
);
2257 /* Returns the number of descriptors added to the DMAC pool */
2258 static int add_desc(struct pl330_dmac
*pl330
, gfp_t flg
, int count
)
2260 struct dma_pl330_desc
*desc
;
2261 unsigned long flags
;
2264 desc
= kcalloc(count
, sizeof(*desc
), flg
);
2268 spin_lock_irqsave(&pl330
->pool_lock
, flags
);
2270 for (i
= 0; i
< count
; i
++) {
2271 _init_desc(&desc
[i
]);
2272 list_add_tail(&desc
[i
].node
, &pl330
->desc_pool
);
2275 spin_unlock_irqrestore(&pl330
->pool_lock
, flags
);
2280 static struct dma_pl330_desc
*pluck_desc(struct pl330_dmac
*pl330
)
2282 struct dma_pl330_desc
*desc
= NULL
;
2283 unsigned long flags
;
2285 spin_lock_irqsave(&pl330
->pool_lock
, flags
);
2287 if (!list_empty(&pl330
->desc_pool
)) {
2288 desc
= list_entry(pl330
->desc_pool
.next
,
2289 struct dma_pl330_desc
, node
);
2291 list_del_init(&desc
->node
);
2293 desc
->status
= PREP
;
2294 desc
->txd
.callback
= NULL
;
2297 spin_unlock_irqrestore(&pl330
->pool_lock
, flags
);
2302 static struct dma_pl330_desc
*pl330_get_desc(struct dma_pl330_chan
*pch
)
2304 struct pl330_dmac
*pl330
= pch
->dmac
;
2305 u8
*peri_id
= pch
->chan
.private;
2306 struct dma_pl330_desc
*desc
;
2308 /* Pluck one desc from the pool of DMAC */
2309 desc
= pluck_desc(pl330
);
2311 /* If the DMAC pool is empty, alloc new */
2313 if (!add_desc(pl330
, GFP_ATOMIC
, 1))
2317 desc
= pluck_desc(pl330
);
2319 dev_err(pch
->dmac
->ddma
.dev
,
2320 "%s:%d ALERT!\n", __func__
, __LINE__
);
2325 /* Initialize the descriptor */
2327 desc
->txd
.cookie
= 0;
2328 async_tx_ack(&desc
->txd
);
2330 desc
->peri
= peri_id
? pch
->chan
.chan_id
: 0;
2331 desc
->rqcfg
.pcfg
= &pch
->dmac
->pcfg
;
2333 dma_async_tx_descriptor_init(&desc
->txd
, &pch
->chan
);
2338 static inline void fill_px(struct pl330_xfer
*px
,
2339 dma_addr_t dst
, dma_addr_t src
, size_t len
)
2346 static struct dma_pl330_desc
*
2347 __pl330_prep_dma_memcpy(struct dma_pl330_chan
*pch
, dma_addr_t dst
,
2348 dma_addr_t src
, size_t len
)
2350 struct dma_pl330_desc
*desc
= pl330_get_desc(pch
);
2353 dev_err(pch
->dmac
->ddma
.dev
, "%s:%d Unable to fetch desc\n",
2354 __func__
, __LINE__
);
2359 * Ideally we should lookout for reqs bigger than
2360 * those that can be programmed with 256 bytes of
2361 * MC buffer, but considering a req size is seldom
2362 * going to be word-unaligned and more than 200MB,
2364 * Also, should the limit is reached we'd rather
2365 * have the platform increase MC buffer size than
2366 * complicating this API driver.
2368 fill_px(&desc
->px
, dst
, src
, len
);
2373 /* Call after fixing burst size */
2374 static inline int get_burst_len(struct dma_pl330_desc
*desc
, size_t len
)
2376 struct dma_pl330_chan
*pch
= desc
->pchan
;
2377 struct pl330_dmac
*pl330
= pch
->dmac
;
2380 burst_len
= pl330
->pcfg
.data_bus_width
/ 8;
2381 burst_len
*= pl330
->pcfg
.data_buf_dep
/ pl330
->pcfg
.num_chan
;
2382 burst_len
>>= desc
->rqcfg
.brst_size
;
2384 /* src/dst_burst_len can't be more than 16 */
2388 while (burst_len
> 1) {
2389 if (!(len
% (burst_len
<< desc
->rqcfg
.brst_size
)))
2397 static struct dma_async_tx_descriptor
*pl330_prep_dma_cyclic(
2398 struct dma_chan
*chan
, dma_addr_t dma_addr
, size_t len
,
2399 size_t period_len
, enum dma_transfer_direction direction
,
2400 unsigned long flags
)
2402 struct dma_pl330_desc
*desc
= NULL
, *first
= NULL
;
2403 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2404 struct pl330_dmac
*pl330
= pch
->dmac
;
2409 if (len
% period_len
!= 0)
2412 if (!is_slave_direction(direction
)) {
2413 dev_err(pch
->dmac
->ddma
.dev
, "%s:%d Invalid dma direction\n",
2414 __func__
, __LINE__
);
2418 for (i
= 0; i
< len
/ period_len
; i
++) {
2419 desc
= pl330_get_desc(pch
);
2421 dev_err(pch
->dmac
->ddma
.dev
, "%s:%d Unable to fetch desc\n",
2422 __func__
, __LINE__
);
2427 spin_lock_irqsave(&pl330
->pool_lock
, flags
);
2429 while (!list_empty(&first
->node
)) {
2430 desc
= list_entry(first
->node
.next
,
2431 struct dma_pl330_desc
, node
);
2432 list_move_tail(&desc
->node
, &pl330
->desc_pool
);
2435 list_move_tail(&first
->node
, &pl330
->desc_pool
);
2437 spin_unlock_irqrestore(&pl330
->pool_lock
, flags
);
2442 switch (direction
) {
2443 case DMA_MEM_TO_DEV
:
2444 desc
->rqcfg
.src_inc
= 1;
2445 desc
->rqcfg
.dst_inc
= 0;
2447 dst
= pch
->fifo_addr
;
2449 case DMA_DEV_TO_MEM
:
2450 desc
->rqcfg
.src_inc
= 0;
2451 desc
->rqcfg
.dst_inc
= 1;
2452 src
= pch
->fifo_addr
;
2459 desc
->rqtype
= direction
;
2460 desc
->rqcfg
.brst_size
= pch
->burst_sz
;
2461 desc
->rqcfg
.brst_len
= 1;
2462 fill_px(&desc
->px
, dst
, src
, period_len
);
2467 list_add_tail(&desc
->node
, &first
->node
);
2469 dma_addr
+= period_len
;
2476 desc
->txd
.flags
= flags
;
2481 static struct dma_async_tx_descriptor
*
2482 pl330_prep_dma_memcpy(struct dma_chan
*chan
, dma_addr_t dst
,
2483 dma_addr_t src
, size_t len
, unsigned long flags
)
2485 struct dma_pl330_desc
*desc
;
2486 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2487 struct pl330_dmac
*pl330
= pch
->dmac
;
2490 if (unlikely(!pch
|| !len
))
2493 desc
= __pl330_prep_dma_memcpy(pch
, dst
, src
, len
);
2497 desc
->rqcfg
.src_inc
= 1;
2498 desc
->rqcfg
.dst_inc
= 1;
2499 desc
->rqtype
= DMA_MEM_TO_MEM
;
2501 /* Select max possible burst size */
2502 burst
= pl330
->pcfg
.data_bus_width
/ 8;
2505 * Make sure we use a burst size that aligns with all the memcpy
2506 * parameters because our DMA programming algorithm doesn't cope with
2507 * transfers which straddle an entry in the DMA device's MFIFO.
2509 while ((src
| dst
| len
) & (burst
- 1))
2512 desc
->rqcfg
.brst_size
= 0;
2513 while (burst
!= (1 << desc
->rqcfg
.brst_size
))
2514 desc
->rqcfg
.brst_size
++;
2517 * If burst size is smaller than bus width then make sure we only
2518 * transfer one at a time to avoid a burst stradling an MFIFO entry.
2520 if (desc
->rqcfg
.brst_size
* 8 < pl330
->pcfg
.data_bus_width
)
2521 desc
->rqcfg
.brst_len
= 1;
2523 desc
->rqcfg
.brst_len
= get_burst_len(desc
, len
);
2525 desc
->txd
.flags
= flags
;
2530 static void __pl330_giveback_desc(struct pl330_dmac
*pl330
,
2531 struct dma_pl330_desc
*first
)
2533 unsigned long flags
;
2534 struct dma_pl330_desc
*desc
;
2539 spin_lock_irqsave(&pl330
->pool_lock
, flags
);
2541 while (!list_empty(&first
->node
)) {
2542 desc
= list_entry(first
->node
.next
,
2543 struct dma_pl330_desc
, node
);
2544 list_move_tail(&desc
->node
, &pl330
->desc_pool
);
2547 list_move_tail(&first
->node
, &pl330
->desc_pool
);
2549 spin_unlock_irqrestore(&pl330
->pool_lock
, flags
);
2552 static struct dma_async_tx_descriptor
*
2553 pl330_prep_slave_sg(struct dma_chan
*chan
, struct scatterlist
*sgl
,
2554 unsigned int sg_len
, enum dma_transfer_direction direction
,
2555 unsigned long flg
, void *context
)
2557 struct dma_pl330_desc
*first
, *desc
= NULL
;
2558 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2559 struct scatterlist
*sg
;
2563 if (unlikely(!pch
|| !sgl
|| !sg_len
))
2566 addr
= pch
->fifo_addr
;
2570 for_each_sg(sgl
, sg
, sg_len
, i
) {
2572 desc
= pl330_get_desc(pch
);
2574 struct pl330_dmac
*pl330
= pch
->dmac
;
2576 dev_err(pch
->dmac
->ddma
.dev
,
2577 "%s:%d Unable to fetch desc\n",
2578 __func__
, __LINE__
);
2579 __pl330_giveback_desc(pl330
, first
);
2587 list_add_tail(&desc
->node
, &first
->node
);
2589 if (direction
== DMA_MEM_TO_DEV
) {
2590 desc
->rqcfg
.src_inc
= 1;
2591 desc
->rqcfg
.dst_inc
= 0;
2593 addr
, sg_dma_address(sg
), sg_dma_len(sg
));
2595 desc
->rqcfg
.src_inc
= 0;
2596 desc
->rqcfg
.dst_inc
= 1;
2598 sg_dma_address(sg
), addr
, sg_dma_len(sg
));
2601 desc
->rqcfg
.brst_size
= pch
->burst_sz
;
2602 desc
->rqcfg
.brst_len
= 1;
2603 desc
->rqtype
= direction
;
2606 /* Return the last desc in the chain */
2607 desc
->txd
.flags
= flg
;
2611 static irqreturn_t
pl330_irq_handler(int irq
, void *data
)
2613 if (pl330_update(data
))
2619 #define PL330_DMA_BUSWIDTHS \
2620 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
2621 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
2622 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
2623 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
2624 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
2626 static int pl330_dma_device_slave_caps(struct dma_chan
*dchan
,
2627 struct dma_slave_caps
*caps
)
2629 caps
->src_addr_widths
= PL330_DMA_BUSWIDTHS
;
2630 caps
->dstn_addr_widths
= PL330_DMA_BUSWIDTHS
;
2631 caps
->directions
= BIT(DMA_DEV_TO_MEM
) | BIT(DMA_MEM_TO_DEV
);
2632 caps
->cmd_pause
= false;
2633 caps
->cmd_terminate
= true;
2634 caps
->residue_granularity
= DMA_RESIDUE_GRANULARITY_DESCRIPTOR
;
2640 * Runtime PM callbacks are provided by amba/bus.c driver.
2642 * It is assumed here that IRQ safe runtime PM is chosen in probe and amba
2643 * bus driver will only disable/enable the clock in runtime PM callbacks.
2645 static int __maybe_unused
pl330_suspend(struct device
*dev
)
2647 struct amba_device
*pcdev
= to_amba_device(dev
);
2649 pm_runtime_disable(dev
);
2651 if (!pm_runtime_status_suspended(dev
)) {
2652 /* amba did not disable the clock */
2653 amba_pclk_disable(pcdev
);
2655 amba_pclk_unprepare(pcdev
);
2660 static int __maybe_unused
pl330_resume(struct device
*dev
)
2662 struct amba_device
*pcdev
= to_amba_device(dev
);
2665 ret
= amba_pclk_prepare(pcdev
);
2669 if (!pm_runtime_status_suspended(dev
))
2670 ret
= amba_pclk_enable(pcdev
);
2672 pm_runtime_enable(dev
);
2677 static SIMPLE_DEV_PM_OPS(pl330_pm
, pl330_suspend
, pl330_resume
);
2680 pl330_probe(struct amba_device
*adev
, const struct amba_id
*id
)
2682 struct dma_pl330_platdata
*pdat
;
2683 struct pl330_config
*pcfg
;
2684 struct pl330_dmac
*pl330
;
2685 struct dma_pl330_chan
*pch
, *_p
;
2686 struct dma_device
*pd
;
2687 struct resource
*res
;
2691 pdat
= dev_get_platdata(&adev
->dev
);
2693 ret
= dma_set_mask_and_coherent(&adev
->dev
, DMA_BIT_MASK(32));
2697 /* Allocate a new DMAC and its Channels */
2698 pl330
= devm_kzalloc(&adev
->dev
, sizeof(*pl330
), GFP_KERNEL
);
2700 dev_err(&adev
->dev
, "unable to allocate mem\n");
2705 pd
->dev
= &adev
->dev
;
2707 pl330
->mcbufsz
= pdat
? pdat
->mcbuf_sz
: 0;
2710 pl330
->base
= devm_ioremap_resource(&adev
->dev
, res
);
2711 if (IS_ERR(pl330
->base
))
2712 return PTR_ERR(pl330
->base
);
2714 amba_set_drvdata(adev
, pl330
);
2716 for (i
= 0; i
< AMBA_NR_IRQS
; i
++) {
2719 ret
= devm_request_irq(&adev
->dev
, irq
,
2720 pl330_irq_handler
, 0,
2721 dev_name(&adev
->dev
), pl330
);
2729 pcfg
= &pl330
->pcfg
;
2731 pcfg
->periph_id
= adev
->periphid
;
2732 ret
= pl330_add(pl330
);
2736 INIT_LIST_HEAD(&pl330
->desc_pool
);
2737 spin_lock_init(&pl330
->pool_lock
);
2739 /* Create a descriptor pool of default size */
2740 if (!add_desc(pl330
, GFP_KERNEL
, NR_DEFAULT_DESC
))
2741 dev_warn(&adev
->dev
, "unable to allocate desc\n");
2743 INIT_LIST_HEAD(&pd
->channels
);
2745 /* Initialize channel parameters */
2747 num_chan
= max_t(int, pdat
->nr_valid_peri
, pcfg
->num_chan
);
2749 num_chan
= max_t(int, pcfg
->num_peri
, pcfg
->num_chan
);
2751 pl330
->num_peripherals
= num_chan
;
2753 pl330
->peripherals
= kzalloc(num_chan
* sizeof(*pch
), GFP_KERNEL
);
2754 if (!pl330
->peripherals
) {
2756 dev_err(&adev
->dev
, "unable to allocate pl330->peripherals\n");
2760 for (i
= 0; i
< num_chan
; i
++) {
2761 pch
= &pl330
->peripherals
[i
];
2762 if (!adev
->dev
.of_node
)
2763 pch
->chan
.private = pdat
? &pdat
->peri_id
[i
] : NULL
;
2765 pch
->chan
.private = adev
->dev
.of_node
;
2767 INIT_LIST_HEAD(&pch
->submitted_list
);
2768 INIT_LIST_HEAD(&pch
->work_list
);
2769 INIT_LIST_HEAD(&pch
->completed_list
);
2770 spin_lock_init(&pch
->lock
);
2772 pch
->chan
.device
= pd
;
2775 /* Add the channel to the DMAC list */
2776 list_add_tail(&pch
->chan
.device_node
, &pd
->channels
);
2780 pd
->cap_mask
= pdat
->cap_mask
;
2782 dma_cap_set(DMA_MEMCPY
, pd
->cap_mask
);
2783 if (pcfg
->num_peri
) {
2784 dma_cap_set(DMA_SLAVE
, pd
->cap_mask
);
2785 dma_cap_set(DMA_CYCLIC
, pd
->cap_mask
);
2786 dma_cap_set(DMA_PRIVATE
, pd
->cap_mask
);
2790 pd
->device_alloc_chan_resources
= pl330_alloc_chan_resources
;
2791 pd
->device_free_chan_resources
= pl330_free_chan_resources
;
2792 pd
->device_prep_dma_memcpy
= pl330_prep_dma_memcpy
;
2793 pd
->device_prep_dma_cyclic
= pl330_prep_dma_cyclic
;
2794 pd
->device_tx_status
= pl330_tx_status
;
2795 pd
->device_prep_slave_sg
= pl330_prep_slave_sg
;
2796 pd
->device_control
= pl330_control
;
2797 pd
->device_issue_pending
= pl330_issue_pending
;
2798 pd
->device_slave_caps
= pl330_dma_device_slave_caps
;
2800 ret
= dma_async_device_register(pd
);
2802 dev_err(&adev
->dev
, "unable to register DMAC\n");
2806 if (adev
->dev
.of_node
) {
2807 ret
= of_dma_controller_register(adev
->dev
.of_node
,
2808 of_dma_pl330_xlate
, pl330
);
2811 "unable to register DMA to the generic DT DMA helpers\n");
2815 adev
->dev
.dma_parms
= &pl330
->dma_parms
;
2818 * This is the limit for transfers with a buswidth of 1, larger
2819 * buswidths will have larger limits.
2821 ret
= dma_set_max_seg_size(&adev
->dev
, 1900800);
2823 dev_err(&adev
->dev
, "unable to set the seg size\n");
2826 dev_info(&adev
->dev
,
2827 "Loaded driver for PL330 DMAC-%x\n", adev
->periphid
);
2828 dev_info(&adev
->dev
,
2829 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
2830 pcfg
->data_buf_dep
, pcfg
->data_bus_width
/ 8, pcfg
->num_chan
,
2831 pcfg
->num_peri
, pcfg
->num_events
);
2833 pm_runtime_irq_safe(&adev
->dev
);
2834 pm_runtime_use_autosuspend(&adev
->dev
);
2835 pm_runtime_set_autosuspend_delay(&adev
->dev
, PL330_AUTOSUSPEND_DELAY
);
2836 pm_runtime_mark_last_busy(&adev
->dev
);
2837 pm_runtime_put_autosuspend(&adev
->dev
);
2842 list_for_each_entry_safe(pch
, _p
, &pl330
->ddma
.channels
,
2845 /* Remove the channel */
2846 list_del(&pch
->chan
.device_node
);
2848 /* Flush the channel */
2850 pl330_control(&pch
->chan
, DMA_TERMINATE_ALL
, 0);
2851 pl330_free_chan_resources(&pch
->chan
);
2860 static int pl330_remove(struct amba_device
*adev
)
2862 struct pl330_dmac
*pl330
= amba_get_drvdata(adev
);
2863 struct dma_pl330_chan
*pch
, *_p
;
2865 pm_runtime_get_noresume(pl330
->ddma
.dev
);
2867 if (adev
->dev
.of_node
)
2868 of_dma_controller_free(adev
->dev
.of_node
);
2870 dma_async_device_unregister(&pl330
->ddma
);
2873 list_for_each_entry_safe(pch
, _p
, &pl330
->ddma
.channels
,
2876 /* Remove the channel */
2877 list_del(&pch
->chan
.device_node
);
2879 /* Flush the channel */
2881 pl330_control(&pch
->chan
, DMA_TERMINATE_ALL
, 0);
2882 pl330_free_chan_resources(&pch
->chan
);
2891 static struct amba_id pl330_ids
[] = {
2899 MODULE_DEVICE_TABLE(amba
, pl330_ids
);
2901 static struct amba_driver pl330_driver
= {
2903 .owner
= THIS_MODULE
,
2904 .name
= "dma-pl330",
2907 .id_table
= pl330_ids
,
2908 .probe
= pl330_probe
,
2909 .remove
= pl330_remove
,
2912 module_amba_driver(pl330_driver
);
2914 MODULE_AUTHOR("Jaswinder Singh <jassisinghbrar@gmail.com>");
2915 MODULE_DESCRIPTION("API Driver for PL330 DMAC");
2916 MODULE_LICENSE("GPL");