2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2010 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/phy.h>
36 #include <linux/brcmphy.h>
37 #include <linux/if_vlan.h>
39 #include <linux/tcp.h>
40 #include <linux/workqueue.h>
41 #include <linux/prefetch.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/firmware.h>
45 #include <net/checksum.h>
48 #include <asm/system.h>
50 #include <asm/byteorder.h>
51 #include <asm/uaccess.h>
54 #include <asm/idprom.h>
61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62 #define TG3_VLAN_TAG_USED 1
64 #define TG3_VLAN_TAG_USED 0
69 #define DRV_MODULE_NAME "tg3"
70 #define DRV_MODULE_VERSION "3.110"
71 #define DRV_MODULE_RELDATE "April 9, 2010"
73 #define TG3_DEF_MAC_MODE 0
74 #define TG3_DEF_RX_MODE 0
75 #define TG3_DEF_TX_MODE 0
76 #define TG3_DEF_MSG_ENABLE \
86 /* length of time before we decide the hardware is borked,
87 * and dev->tx_timeout() should be called to fix the problem
89 #define TG3_TX_TIMEOUT (5 * HZ)
91 /* hardware minimum and maximum for a single frame's data payload */
92 #define TG3_MIN_MTU 60
93 #define TG3_MAX_MTU(tp) \
94 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
96 /* These numbers seem to be hard coded in the NIC firmware somehow.
97 * You can't change the ring sizes, but you can change where you place
98 * them in the NIC onboard memory.
100 #define TG3_RX_RING_SIZE 512
101 #define TG3_DEF_RX_RING_PENDING 200
102 #define TG3_RX_JUMBO_RING_SIZE 256
103 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
104 #define TG3_RSS_INDIR_TBL_SIZE 128
106 /* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et
108 * al. operations are done with shifts and masks instead of with
109 * hw multiply/modulo instructions. Another solution would be to
110 * replace things like '% foo' with '& (foo - 1)'.
112 #define TG3_RX_RCB_RING_SIZE(tp) \
113 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
114 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
116 #define TG3_TX_RING_SIZE 512
117 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
119 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
122 TG3_RX_JUMBO_RING_SIZE)
123 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
124 TG3_RX_RCB_RING_SIZE(tp))
125 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
127 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
129 #define TG3_RX_DMA_ALIGN 16
130 #define TG3_RX_HEADROOM ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
132 #define TG3_DMA_BYTE_ENAB 64
134 #define TG3_RX_STD_DMA_SZ 1536
135 #define TG3_RX_JMB_DMA_SZ 9046
137 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
139 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
140 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
142 #define TG3_RX_STD_BUFF_RING_SIZE \
143 (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
145 #define TG3_RX_JMB_BUFF_RING_SIZE \
146 (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
148 #define TG3_RSS_MIN_NUM_MSIX_VECS 2
150 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
151 * that are at least dword aligned when used in PCIX mode. The driver
152 * works around this bug by double copying the packet. This workaround
153 * is built into the normal double copy length check for efficiency.
155 * However, the double copy is only necessary on those architectures
156 * where unaligned memory accesses are inefficient. For those architectures
157 * where unaligned memory accesses incur little penalty, we can reintegrate
158 * the 5701 in the normal rx path. Doing so saves a device structure
159 * dereference by hardcoding the double copy threshold in place.
161 #define TG3_RX_COPY_THRESHOLD 256
162 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
163 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
165 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
168 /* minimum number of free TX descriptors required to wake up TX process */
169 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
171 #define TG3_RAW_IP_ALIGN 2
173 /* number of ETHTOOL_GSTATS u64's */
174 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
176 #define TG3_NUM_TEST 6
178 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
180 #define FIRMWARE_TG3 "tigon/tg3.bin"
181 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
182 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
184 static char version
[] __devinitdata
=
185 DRV_MODULE_NAME
".c:v" DRV_MODULE_VERSION
" (" DRV_MODULE_RELDATE
")";
187 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
188 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
189 MODULE_LICENSE("GPL");
190 MODULE_VERSION(DRV_MODULE_VERSION
);
191 MODULE_FIRMWARE(FIRMWARE_TG3
);
192 MODULE_FIRMWARE(FIRMWARE_TG3TSO
);
193 MODULE_FIRMWARE(FIRMWARE_TG3TSO5
);
195 static int tg3_debug
= -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
196 module_param(tg3_debug
, int, 0);
197 MODULE_PARM_DESC(tg3_debug
, "Tigon3 bitmapped debugging message enable value");
199 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl
) = {
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5700
)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5701
)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702
)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703
)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704
)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702FE
)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705
)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705_2
)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705M
)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705M_2
)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702X
)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703X
)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704S
)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702A3
)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703A3
)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5782
)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5788
)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5789
)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5901
)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5901_2
)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704S_2
)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705F
)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5720
)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5721
)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5722
)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5750
)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751
)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5750M
)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751M
)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751F
)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5752
)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5752M
)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753
)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753M
)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753F
)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5754
)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5754M
)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5755
)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5755M
)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5756
)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5786
)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787
)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787M
)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787F
)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5714
)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5714S
)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5715
)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5715S
)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5780
)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5780S
)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5781
)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5906
)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5906M
)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5784
)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5764
)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5723
)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5761
)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5761E
)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5761S
)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5761SE
)},
260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5785_G
)},
261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5785_F
)},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57780
)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57760
)},
264 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57790
)},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57788
)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5717
)},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5718
)},
268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5724
)},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57781
)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57785
)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57761
)},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57765
)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57791
)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57795
)},
275 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_9DXX
)},
276 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_9MXX
)},
277 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1000
)},
278 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1001
)},
279 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1003
)},
280 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC9100
)},
281 {PCI_DEVICE(PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_TIGON3
)},
285 MODULE_DEVICE_TABLE(pci
, tg3_pci_tbl
);
287 static const struct {
288 const char string
[ETH_GSTRING_LEN
];
289 } ethtool_stats_keys
[TG3_NUM_STATS
] = {
292 { "rx_ucast_packets" },
293 { "rx_mcast_packets" },
294 { "rx_bcast_packets" },
296 { "rx_align_errors" },
297 { "rx_xon_pause_rcvd" },
298 { "rx_xoff_pause_rcvd" },
299 { "rx_mac_ctrl_rcvd" },
300 { "rx_xoff_entered" },
301 { "rx_frame_too_long_errors" },
303 { "rx_undersize_packets" },
304 { "rx_in_length_errors" },
305 { "rx_out_length_errors" },
306 { "rx_64_or_less_octet_packets" },
307 { "rx_65_to_127_octet_packets" },
308 { "rx_128_to_255_octet_packets" },
309 { "rx_256_to_511_octet_packets" },
310 { "rx_512_to_1023_octet_packets" },
311 { "rx_1024_to_1522_octet_packets" },
312 { "rx_1523_to_2047_octet_packets" },
313 { "rx_2048_to_4095_octet_packets" },
314 { "rx_4096_to_8191_octet_packets" },
315 { "rx_8192_to_9022_octet_packets" },
322 { "tx_flow_control" },
324 { "tx_single_collisions" },
325 { "tx_mult_collisions" },
327 { "tx_excessive_collisions" },
328 { "tx_late_collisions" },
329 { "tx_collide_2times" },
330 { "tx_collide_3times" },
331 { "tx_collide_4times" },
332 { "tx_collide_5times" },
333 { "tx_collide_6times" },
334 { "tx_collide_7times" },
335 { "tx_collide_8times" },
336 { "tx_collide_9times" },
337 { "tx_collide_10times" },
338 { "tx_collide_11times" },
339 { "tx_collide_12times" },
340 { "tx_collide_13times" },
341 { "tx_collide_14times" },
342 { "tx_collide_15times" },
343 { "tx_ucast_packets" },
344 { "tx_mcast_packets" },
345 { "tx_bcast_packets" },
346 { "tx_carrier_sense_errors" },
350 { "dma_writeq_full" },
351 { "dma_write_prioq_full" },
355 { "rx_threshold_hit" },
357 { "dma_readq_full" },
358 { "dma_read_prioq_full" },
359 { "tx_comp_queue_full" },
361 { "ring_set_send_prod_index" },
362 { "ring_status_update" },
364 { "nic_avoided_irqs" },
365 { "nic_tx_threshold_hit" }
368 static const struct {
369 const char string
[ETH_GSTRING_LEN
];
370 } ethtool_test_keys
[TG3_NUM_TEST
] = {
371 { "nvram test (online) " },
372 { "link test (online) " },
373 { "register test (offline)" },
374 { "memory test (offline)" },
375 { "loopback test (offline)" },
376 { "interrupt test (offline)" },
379 static void tg3_write32(struct tg3
*tp
, u32 off
, u32 val
)
381 writel(val
, tp
->regs
+ off
);
384 static u32
tg3_read32(struct tg3
*tp
, u32 off
)
386 return readl(tp
->regs
+ off
);
389 static void tg3_ape_write32(struct tg3
*tp
, u32 off
, u32 val
)
391 writel(val
, tp
->aperegs
+ off
);
394 static u32
tg3_ape_read32(struct tg3
*tp
, u32 off
)
396 return readl(tp
->aperegs
+ off
);
399 static void tg3_write_indirect_reg32(struct tg3
*tp
, u32 off
, u32 val
)
403 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
404 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
);
405 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, val
);
406 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
409 static void tg3_write_flush_reg32(struct tg3
*tp
, u32 off
, u32 val
)
411 writel(val
, tp
->regs
+ off
);
412 readl(tp
->regs
+ off
);
415 static u32
tg3_read_indirect_reg32(struct tg3
*tp
, u32 off
)
420 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
421 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
);
422 pci_read_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, &val
);
423 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
427 static void tg3_write_indirect_mbox(struct tg3
*tp
, u32 off
, u32 val
)
431 if (off
== (MAILBOX_RCVRET_CON_IDX_0
+ TG3_64BIT_REG_LOW
)) {
432 pci_write_config_dword(tp
->pdev
, TG3PCI_RCV_RET_RING_CON_IDX
+
433 TG3_64BIT_REG_LOW
, val
);
436 if (off
== TG3_RX_STD_PROD_IDX_REG
) {
437 pci_write_config_dword(tp
->pdev
, TG3PCI_STD_RING_PROD_IDX
+
438 TG3_64BIT_REG_LOW
, val
);
442 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
443 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
+ 0x5600);
444 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, val
);
445 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
447 /* In indirect mode when disabling interrupts, we also need
448 * to clear the interrupt bit in the GRC local ctrl register.
450 if ((off
== (MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
)) &&
452 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_LOCAL_CTRL
,
453 tp
->grc_local_ctrl
|GRC_LCLCTRL_CLEARINT
);
457 static u32
tg3_read_indirect_mbox(struct tg3
*tp
, u32 off
)
462 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
463 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
+ 0x5600);
464 pci_read_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, &val
);
465 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
469 /* usec_wait specifies the wait time in usec when writing to certain registers
470 * where it is unsafe to read back the register without some delay.
471 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
472 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
474 static void _tw32_flush(struct tg3
*tp
, u32 off
, u32 val
, u32 usec_wait
)
476 if ((tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
) ||
477 (tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
))
478 /* Non-posted methods */
479 tp
->write32(tp
, off
, val
);
482 tg3_write32(tp
, off
, val
);
487 /* Wait again after the read for the posted method to guarantee that
488 * the wait time is met.
494 static inline void tw32_mailbox_flush(struct tg3
*tp
, u32 off
, u32 val
)
496 tp
->write32_mbox(tp
, off
, val
);
497 if (!(tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
) &&
498 !(tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
))
499 tp
->read32_mbox(tp
, off
);
502 static void tg3_write32_tx_mbox(struct tg3
*tp
, u32 off
, u32 val
)
504 void __iomem
*mbox
= tp
->regs
+ off
;
506 if (tp
->tg3_flags
& TG3_FLAG_TXD_MBOX_HWBUG
)
508 if (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)
512 static u32
tg3_read32_mbox_5906(struct tg3
*tp
, u32 off
)
514 return readl(tp
->regs
+ off
+ GRCMBOX_BASE
);
517 static void tg3_write32_mbox_5906(struct tg3
*tp
, u32 off
, u32 val
)
519 writel(val
, tp
->regs
+ off
+ GRCMBOX_BASE
);
522 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
523 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
524 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
525 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
526 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
528 #define tw32(reg, val) tp->write32(tp, reg, val)
529 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
530 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
531 #define tr32(reg) tp->read32(tp, reg)
533 static void tg3_write_mem(struct tg3
*tp
, u32 off
, u32 val
)
537 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) &&
538 (off
>= NIC_SRAM_STATS_BLK
) && (off
< NIC_SRAM_TX_BUFFER_DESC
))
541 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
542 if (tp
->tg3_flags
& TG3_FLAG_SRAM_USE_CONFIG
) {
543 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, off
);
544 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
546 /* Always leave this as zero. */
547 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
549 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, off
);
550 tw32_f(TG3PCI_MEM_WIN_DATA
, val
);
552 /* Always leave this as zero. */
553 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
555 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
558 static void tg3_read_mem(struct tg3
*tp
, u32 off
, u32
*val
)
562 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) &&
563 (off
>= NIC_SRAM_STATS_BLK
) && (off
< NIC_SRAM_TX_BUFFER_DESC
)) {
568 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
569 if (tp
->tg3_flags
& TG3_FLAG_SRAM_USE_CONFIG
) {
570 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, off
);
571 pci_read_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
573 /* Always leave this as zero. */
574 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
576 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, off
);
577 *val
= tr32(TG3PCI_MEM_WIN_DATA
);
579 /* Always leave this as zero. */
580 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
582 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
585 static void tg3_ape_lock_init(struct tg3
*tp
)
590 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
591 regbase
= TG3_APE_LOCK_GRANT
;
593 regbase
= TG3_APE_PER_LOCK_GRANT
;
595 /* Make sure the driver hasn't any stale locks. */
596 for (i
= 0; i
< 8; i
++)
597 tg3_ape_write32(tp
, regbase
+ 4 * i
, APE_LOCK_GRANT_DRIVER
);
600 static int tg3_ape_lock(struct tg3
*tp
, int locknum
)
604 u32 status
, req
, gnt
;
606 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
610 case TG3_APE_LOCK_GRC
:
611 case TG3_APE_LOCK_MEM
:
617 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
) {
618 req
= TG3_APE_LOCK_REQ
;
619 gnt
= TG3_APE_LOCK_GRANT
;
621 req
= TG3_APE_PER_LOCK_REQ
;
622 gnt
= TG3_APE_PER_LOCK_GRANT
;
627 tg3_ape_write32(tp
, req
+ off
, APE_LOCK_REQ_DRIVER
);
629 /* Wait for up to 1 millisecond to acquire lock. */
630 for (i
= 0; i
< 100; i
++) {
631 status
= tg3_ape_read32(tp
, gnt
+ off
);
632 if (status
== APE_LOCK_GRANT_DRIVER
)
637 if (status
!= APE_LOCK_GRANT_DRIVER
) {
638 /* Revoke the lock request. */
639 tg3_ape_write32(tp
, gnt
+ off
,
640 APE_LOCK_GRANT_DRIVER
);
648 static void tg3_ape_unlock(struct tg3
*tp
, int locknum
)
652 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
656 case TG3_APE_LOCK_GRC
:
657 case TG3_APE_LOCK_MEM
:
663 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
664 gnt
= TG3_APE_LOCK_GRANT
;
666 gnt
= TG3_APE_PER_LOCK_GRANT
;
668 tg3_ape_write32(tp
, gnt
+ 4 * locknum
, APE_LOCK_GRANT_DRIVER
);
671 static void tg3_disable_ints(struct tg3
*tp
)
675 tw32(TG3PCI_MISC_HOST_CTRL
,
676 (tp
->misc_host_ctrl
| MISC_HOST_CTRL_MASK_PCI_INT
));
677 for (i
= 0; i
< tp
->irq_max
; i
++)
678 tw32_mailbox_f(tp
->napi
[i
].int_mbox
, 0x00000001);
681 static void tg3_enable_ints(struct tg3
*tp
)
688 tw32(TG3PCI_MISC_HOST_CTRL
,
689 (tp
->misc_host_ctrl
& ~MISC_HOST_CTRL_MASK_PCI_INT
));
691 tp
->coal_now
= tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
;
692 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
693 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
695 tw32_mailbox_f(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
696 if (tp
->tg3_flags2
& TG3_FLG2_1SHOT_MSI
)
697 tw32_mailbox_f(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
699 tp
->coal_now
|= tnapi
->coal_now
;
702 /* Force an initial interrupt */
703 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) &&
704 (tp
->napi
[0].hw_status
->status
& SD_STATUS_UPDATED
))
705 tw32(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
| GRC_LCLCTRL_SETINT
);
707 tw32(HOSTCC_MODE
, tp
->coal_now
);
709 tp
->coal_now
&= ~(tp
->napi
[0].coal_now
| tp
->napi
[1].coal_now
);
712 static inline unsigned int tg3_has_work(struct tg3_napi
*tnapi
)
714 struct tg3
*tp
= tnapi
->tp
;
715 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
716 unsigned int work_exists
= 0;
718 /* check for phy events */
719 if (!(tp
->tg3_flags
&
720 (TG3_FLAG_USE_LINKCHG_REG
|
721 TG3_FLAG_POLL_SERDES
))) {
722 if (sblk
->status
& SD_STATUS_LINK_CHG
)
725 /* check for RX/TX work to do */
726 if (sblk
->idx
[0].tx_consumer
!= tnapi
->tx_cons
||
727 *(tnapi
->rx_rcb_prod_idx
) != tnapi
->rx_rcb_ptr
)
734 * similar to tg3_enable_ints, but it accurately determines whether there
735 * is new work pending and can return without flushing the PIO write
736 * which reenables interrupts
738 static void tg3_int_reenable(struct tg3_napi
*tnapi
)
740 struct tg3
*tp
= tnapi
->tp
;
742 tw32_mailbox(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
745 /* When doing tagged status, this work check is unnecessary.
746 * The last_tag we write above tells the chip which piece of
747 * work we've completed.
749 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) &&
751 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
752 HOSTCC_MODE_ENABLE
| tnapi
->coal_now
);
755 static void tg3_napi_disable(struct tg3
*tp
)
759 for (i
= tp
->irq_cnt
- 1; i
>= 0; i
--)
760 napi_disable(&tp
->napi
[i
].napi
);
763 static void tg3_napi_enable(struct tg3
*tp
)
767 for (i
= 0; i
< tp
->irq_cnt
; i
++)
768 napi_enable(&tp
->napi
[i
].napi
);
771 static inline void tg3_netif_stop(struct tg3
*tp
)
773 tp
->dev
->trans_start
= jiffies
; /* prevent tx timeout */
774 tg3_napi_disable(tp
);
775 netif_tx_disable(tp
->dev
);
778 static inline void tg3_netif_start(struct tg3
*tp
)
780 /* NOTE: unconditional netif_tx_wake_all_queues is only
781 * appropriate so long as all callers are assured to
782 * have free tx slots (such as after tg3_init_hw)
784 netif_tx_wake_all_queues(tp
->dev
);
787 tp
->napi
[0].hw_status
->status
|= SD_STATUS_UPDATED
;
791 static void tg3_switch_clocks(struct tg3
*tp
)
796 if ((tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) ||
797 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
800 clock_ctrl
= tr32(TG3PCI_CLOCK_CTRL
);
802 orig_clock_ctrl
= clock_ctrl
;
803 clock_ctrl
&= (CLOCK_CTRL_FORCE_CLKRUN
|
804 CLOCK_CTRL_CLKRUN_OENABLE
|
806 tp
->pci_clock_ctrl
= clock_ctrl
;
808 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
809 if (orig_clock_ctrl
& CLOCK_CTRL_625_CORE
) {
810 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
811 clock_ctrl
| CLOCK_CTRL_625_CORE
, 40);
813 } else if ((orig_clock_ctrl
& CLOCK_CTRL_44MHZ_CORE
) != 0) {
814 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
816 (CLOCK_CTRL_44MHZ_CORE
| CLOCK_CTRL_ALTCLK
),
818 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
819 clock_ctrl
| (CLOCK_CTRL_ALTCLK
),
822 tw32_wait_f(TG3PCI_CLOCK_CTRL
, clock_ctrl
, 40);
825 #define PHY_BUSY_LOOPS 5000
827 static int tg3_readphy(struct tg3
*tp
, int reg
, u32
*val
)
833 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
835 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
841 frame_val
= ((tp
->phy_addr
<< MI_COM_PHY_ADDR_SHIFT
) &
842 MI_COM_PHY_ADDR_MASK
);
843 frame_val
|= ((reg
<< MI_COM_REG_ADDR_SHIFT
) &
844 MI_COM_REG_ADDR_MASK
);
845 frame_val
|= (MI_COM_CMD_READ
| MI_COM_START
);
847 tw32_f(MAC_MI_COM
, frame_val
);
849 loops
= PHY_BUSY_LOOPS
;
852 frame_val
= tr32(MAC_MI_COM
);
854 if ((frame_val
& MI_COM_BUSY
) == 0) {
856 frame_val
= tr32(MAC_MI_COM
);
864 *val
= frame_val
& MI_COM_DATA_MASK
;
868 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
869 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
876 static int tg3_writephy(struct tg3
*tp
, int reg
, u32 val
)
882 if ((tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) &&
883 (reg
== MII_TG3_CTRL
|| reg
== MII_TG3_AUX_CTRL
))
886 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
888 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
892 frame_val
= ((tp
->phy_addr
<< MI_COM_PHY_ADDR_SHIFT
) &
893 MI_COM_PHY_ADDR_MASK
);
894 frame_val
|= ((reg
<< MI_COM_REG_ADDR_SHIFT
) &
895 MI_COM_REG_ADDR_MASK
);
896 frame_val
|= (val
& MI_COM_DATA_MASK
);
897 frame_val
|= (MI_COM_CMD_WRITE
| MI_COM_START
);
899 tw32_f(MAC_MI_COM
, frame_val
);
901 loops
= PHY_BUSY_LOOPS
;
904 frame_val
= tr32(MAC_MI_COM
);
905 if ((frame_val
& MI_COM_BUSY
) == 0) {
907 frame_val
= tr32(MAC_MI_COM
);
917 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
918 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
925 static int tg3_bmcr_reset(struct tg3
*tp
)
930 /* OK, reset it, and poll the BMCR_RESET bit until it
931 * clears or we time out.
933 phy_control
= BMCR_RESET
;
934 err
= tg3_writephy(tp
, MII_BMCR
, phy_control
);
940 err
= tg3_readphy(tp
, MII_BMCR
, &phy_control
);
944 if ((phy_control
& BMCR_RESET
) == 0) {
956 static int tg3_mdio_read(struct mii_bus
*bp
, int mii_id
, int reg
)
958 struct tg3
*tp
= bp
->priv
;
961 spin_lock_bh(&tp
->lock
);
963 if (tg3_readphy(tp
, reg
, &val
))
966 spin_unlock_bh(&tp
->lock
);
971 static int tg3_mdio_write(struct mii_bus
*bp
, int mii_id
, int reg
, u16 val
)
973 struct tg3
*tp
= bp
->priv
;
976 spin_lock_bh(&tp
->lock
);
978 if (tg3_writephy(tp
, reg
, val
))
981 spin_unlock_bh(&tp
->lock
);
986 static int tg3_mdio_reset(struct mii_bus
*bp
)
991 static void tg3_mdio_config_5785(struct tg3
*tp
)
994 struct phy_device
*phydev
;
996 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
997 switch (phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
) {
998 case PHY_ID_BCM50610
:
999 case PHY_ID_BCM50610M
:
1000 val
= MAC_PHYCFG2_50610_LED_MODES
;
1002 case PHY_ID_BCMAC131
:
1003 val
= MAC_PHYCFG2_AC131_LED_MODES
;
1005 case PHY_ID_RTL8211C
:
1006 val
= MAC_PHYCFG2_RTL8211C_LED_MODES
;
1008 case PHY_ID_RTL8201E
:
1009 val
= MAC_PHYCFG2_RTL8201E_LED_MODES
;
1015 if (phydev
->interface
!= PHY_INTERFACE_MODE_RGMII
) {
1016 tw32(MAC_PHYCFG2
, val
);
1018 val
= tr32(MAC_PHYCFG1
);
1019 val
&= ~(MAC_PHYCFG1_RGMII_INT
|
1020 MAC_PHYCFG1_RXCLK_TO_MASK
| MAC_PHYCFG1_TXCLK_TO_MASK
);
1021 val
|= MAC_PHYCFG1_RXCLK_TIMEOUT
| MAC_PHYCFG1_TXCLK_TIMEOUT
;
1022 tw32(MAC_PHYCFG1
, val
);
1027 if (!(tp
->tg3_flags3
& TG3_FLG3_RGMII_INBAND_DISABLE
))
1028 val
|= MAC_PHYCFG2_EMODE_MASK_MASK
|
1029 MAC_PHYCFG2_FMODE_MASK_MASK
|
1030 MAC_PHYCFG2_GMODE_MASK_MASK
|
1031 MAC_PHYCFG2_ACT_MASK_MASK
|
1032 MAC_PHYCFG2_QUAL_MASK_MASK
|
1033 MAC_PHYCFG2_INBAND_ENABLE
;
1035 tw32(MAC_PHYCFG2
, val
);
1037 val
= tr32(MAC_PHYCFG1
);
1038 val
&= ~(MAC_PHYCFG1_RXCLK_TO_MASK
| MAC_PHYCFG1_TXCLK_TO_MASK
|
1039 MAC_PHYCFG1_RGMII_EXT_RX_DEC
| MAC_PHYCFG1_RGMII_SND_STAT_EN
);
1040 if (!(tp
->tg3_flags3
& TG3_FLG3_RGMII_INBAND_DISABLE
)) {
1041 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
1042 val
|= MAC_PHYCFG1_RGMII_EXT_RX_DEC
;
1043 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
1044 val
|= MAC_PHYCFG1_RGMII_SND_STAT_EN
;
1046 val
|= MAC_PHYCFG1_RXCLK_TIMEOUT
| MAC_PHYCFG1_TXCLK_TIMEOUT
|
1047 MAC_PHYCFG1_RGMII_INT
| MAC_PHYCFG1_TXC_DRV
;
1048 tw32(MAC_PHYCFG1
, val
);
1050 val
= tr32(MAC_EXT_RGMII_MODE
);
1051 val
&= ~(MAC_RGMII_MODE_RX_INT_B
|
1052 MAC_RGMII_MODE_RX_QUALITY
|
1053 MAC_RGMII_MODE_RX_ACTIVITY
|
1054 MAC_RGMII_MODE_RX_ENG_DET
|
1055 MAC_RGMII_MODE_TX_ENABLE
|
1056 MAC_RGMII_MODE_TX_LOWPWR
|
1057 MAC_RGMII_MODE_TX_RESET
);
1058 if (!(tp
->tg3_flags3
& TG3_FLG3_RGMII_INBAND_DISABLE
)) {
1059 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
1060 val
|= MAC_RGMII_MODE_RX_INT_B
|
1061 MAC_RGMII_MODE_RX_QUALITY
|
1062 MAC_RGMII_MODE_RX_ACTIVITY
|
1063 MAC_RGMII_MODE_RX_ENG_DET
;
1064 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
1065 val
|= MAC_RGMII_MODE_TX_ENABLE
|
1066 MAC_RGMII_MODE_TX_LOWPWR
|
1067 MAC_RGMII_MODE_TX_RESET
;
1069 tw32(MAC_EXT_RGMII_MODE
, val
);
1072 static void tg3_mdio_start(struct tg3
*tp
)
1074 tp
->mi_mode
&= ~MAC_MI_MODE_AUTO_POLL
;
1075 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
1078 if ((tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
) &&
1079 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
1080 tg3_mdio_config_5785(tp
);
1083 static int tg3_mdio_init(struct tg3
*tp
)
1087 struct phy_device
*phydev
;
1089 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
) {
1090 u32 funcnum
, is_serdes
;
1092 funcnum
= tr32(TG3_CPMU_STATUS
) & TG3_CPMU_STATUS_PCIE_FUNC
;
1098 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5717_A0
)
1099 is_serdes
= tr32(SG_DIG_STATUS
) & SG_DIG_IS_SERDES
;
1101 is_serdes
= tr32(TG3_CPMU_PHY_STRAP
) &
1102 TG3_CPMU_PHY_STRAP_IS_SERDES
;
1106 tp
->phy_addr
= TG3_PHY_MII_ADDR
;
1110 if (!(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) ||
1111 (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
))
1114 tp
->mdio_bus
= mdiobus_alloc();
1115 if (tp
->mdio_bus
== NULL
)
1118 tp
->mdio_bus
->name
= "tg3 mdio bus";
1119 snprintf(tp
->mdio_bus
->id
, MII_BUS_ID_SIZE
, "%x",
1120 (tp
->pdev
->bus
->number
<< 8) | tp
->pdev
->devfn
);
1121 tp
->mdio_bus
->priv
= tp
;
1122 tp
->mdio_bus
->parent
= &tp
->pdev
->dev
;
1123 tp
->mdio_bus
->read
= &tg3_mdio_read
;
1124 tp
->mdio_bus
->write
= &tg3_mdio_write
;
1125 tp
->mdio_bus
->reset
= &tg3_mdio_reset
;
1126 tp
->mdio_bus
->phy_mask
= ~(1 << TG3_PHY_MII_ADDR
);
1127 tp
->mdio_bus
->irq
= &tp
->mdio_irq
[0];
1129 for (i
= 0; i
< PHY_MAX_ADDR
; i
++)
1130 tp
->mdio_bus
->irq
[i
] = PHY_POLL
;
1132 /* The bus registration will look for all the PHYs on the mdio bus.
1133 * Unfortunately, it does not ensure the PHY is powered up before
1134 * accessing the PHY ID registers. A chip reset is the
1135 * quickest way to bring the device back to an operational state..
1137 if (tg3_readphy(tp
, MII_BMCR
, ®
) || (reg
& BMCR_PDOWN
))
1140 i
= mdiobus_register(tp
->mdio_bus
);
1142 dev_warn(&tp
->pdev
->dev
, "mdiobus_reg failed (0x%x)\n", i
);
1143 mdiobus_free(tp
->mdio_bus
);
1147 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1149 if (!phydev
|| !phydev
->drv
) {
1150 dev_warn(&tp
->pdev
->dev
, "No PHY devices\n");
1151 mdiobus_unregister(tp
->mdio_bus
);
1152 mdiobus_free(tp
->mdio_bus
);
1156 switch (phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
) {
1157 case PHY_ID_BCM57780
:
1158 phydev
->interface
= PHY_INTERFACE_MODE_GMII
;
1159 phydev
->dev_flags
|= PHY_BRCM_AUTO_PWRDWN_ENABLE
;
1161 case PHY_ID_BCM50610
:
1162 case PHY_ID_BCM50610M
:
1163 phydev
->dev_flags
|= PHY_BRCM_CLEAR_RGMII_MODE
|
1164 PHY_BRCM_RX_REFCLK_UNUSED
|
1165 PHY_BRCM_DIS_TXCRXC_NOENRGY
|
1166 PHY_BRCM_AUTO_PWRDWN_ENABLE
;
1167 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_INBAND_DISABLE
)
1168 phydev
->dev_flags
|= PHY_BRCM_STD_IBND_DISABLE
;
1169 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
1170 phydev
->dev_flags
|= PHY_BRCM_EXT_IBND_RX_ENABLE
;
1171 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
1172 phydev
->dev_flags
|= PHY_BRCM_EXT_IBND_TX_ENABLE
;
1174 case PHY_ID_RTL8211C
:
1175 phydev
->interface
= PHY_INTERFACE_MODE_RGMII
;
1177 case PHY_ID_RTL8201E
:
1178 case PHY_ID_BCMAC131
:
1179 phydev
->interface
= PHY_INTERFACE_MODE_MII
;
1180 phydev
->dev_flags
|= PHY_BRCM_AUTO_PWRDWN_ENABLE
;
1181 tp
->tg3_flags3
|= TG3_FLG3_PHY_IS_FET
;
1185 tp
->tg3_flags3
|= TG3_FLG3_MDIOBUS_INITED
;
1187 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
1188 tg3_mdio_config_5785(tp
);
1193 static void tg3_mdio_fini(struct tg3
*tp
)
1195 if (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
) {
1196 tp
->tg3_flags3
&= ~TG3_FLG3_MDIOBUS_INITED
;
1197 mdiobus_unregister(tp
->mdio_bus
);
1198 mdiobus_free(tp
->mdio_bus
);
1202 /* tp->lock is held. */
1203 static inline void tg3_generate_fw_event(struct tg3
*tp
)
1207 val
= tr32(GRC_RX_CPU_EVENT
);
1208 val
|= GRC_RX_CPU_DRIVER_EVENT
;
1209 tw32_f(GRC_RX_CPU_EVENT
, val
);
1211 tp
->last_event_jiffies
= jiffies
;
1214 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1216 /* tp->lock is held. */
1217 static void tg3_wait_for_event_ack(struct tg3
*tp
)
1220 unsigned int delay_cnt
;
1223 /* If enough time has passed, no wait is necessary. */
1224 time_remain
= (long)(tp
->last_event_jiffies
+ 1 +
1225 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC
)) -
1227 if (time_remain
< 0)
1230 /* Check if we can shorten the wait time. */
1231 delay_cnt
= jiffies_to_usecs(time_remain
);
1232 if (delay_cnt
> TG3_FW_EVENT_TIMEOUT_USEC
)
1233 delay_cnt
= TG3_FW_EVENT_TIMEOUT_USEC
;
1234 delay_cnt
= (delay_cnt
>> 3) + 1;
1236 for (i
= 0; i
< delay_cnt
; i
++) {
1237 if (!(tr32(GRC_RX_CPU_EVENT
) & GRC_RX_CPU_DRIVER_EVENT
))
1243 /* tp->lock is held. */
1244 static void tg3_ump_link_report(struct tg3
*tp
)
1249 if (!(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
1250 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
1253 tg3_wait_for_event_ack(tp
);
1255 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
, FWCMD_NICDRV_LINK_UPDATE
);
1257 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_LEN_MBOX
, 14);
1260 if (!tg3_readphy(tp
, MII_BMCR
, ®
))
1262 if (!tg3_readphy(tp
, MII_BMSR
, ®
))
1263 val
|= (reg
& 0xffff);
1264 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
, val
);
1267 if (!tg3_readphy(tp
, MII_ADVERTISE
, ®
))
1269 if (!tg3_readphy(tp
, MII_LPA
, ®
))
1270 val
|= (reg
& 0xffff);
1271 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 4, val
);
1274 if (!(tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)) {
1275 if (!tg3_readphy(tp
, MII_CTRL1000
, ®
))
1277 if (!tg3_readphy(tp
, MII_STAT1000
, ®
))
1278 val
|= (reg
& 0xffff);
1280 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 8, val
);
1282 if (!tg3_readphy(tp
, MII_PHYADDR
, ®
))
1286 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 12, val
);
1288 tg3_generate_fw_event(tp
);
1291 static void tg3_link_report(struct tg3
*tp
)
1293 if (!netif_carrier_ok(tp
->dev
)) {
1294 netif_info(tp
, link
, tp
->dev
, "Link is down\n");
1295 tg3_ump_link_report(tp
);
1296 } else if (netif_msg_link(tp
)) {
1297 netdev_info(tp
->dev
, "Link is up at %d Mbps, %s duplex\n",
1298 (tp
->link_config
.active_speed
== SPEED_1000
?
1300 (tp
->link_config
.active_speed
== SPEED_100
?
1302 (tp
->link_config
.active_duplex
== DUPLEX_FULL
?
1305 netdev_info(tp
->dev
, "Flow control is %s for TX and %s for RX\n",
1306 (tp
->link_config
.active_flowctrl
& FLOW_CTRL_TX
) ?
1308 (tp
->link_config
.active_flowctrl
& FLOW_CTRL_RX
) ?
1310 tg3_ump_link_report(tp
);
1314 static u16
tg3_advert_flowctrl_1000T(u8 flow_ctrl
)
1318 if ((flow_ctrl
& FLOW_CTRL_TX
) && (flow_ctrl
& FLOW_CTRL_RX
))
1319 miireg
= ADVERTISE_PAUSE_CAP
;
1320 else if (flow_ctrl
& FLOW_CTRL_TX
)
1321 miireg
= ADVERTISE_PAUSE_ASYM
;
1322 else if (flow_ctrl
& FLOW_CTRL_RX
)
1323 miireg
= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
1330 static u16
tg3_advert_flowctrl_1000X(u8 flow_ctrl
)
1334 if ((flow_ctrl
& FLOW_CTRL_TX
) && (flow_ctrl
& FLOW_CTRL_RX
))
1335 miireg
= ADVERTISE_1000XPAUSE
;
1336 else if (flow_ctrl
& FLOW_CTRL_TX
)
1337 miireg
= ADVERTISE_1000XPSE_ASYM
;
1338 else if (flow_ctrl
& FLOW_CTRL_RX
)
1339 miireg
= ADVERTISE_1000XPAUSE
| ADVERTISE_1000XPSE_ASYM
;
1346 static u8
tg3_resolve_flowctrl_1000X(u16 lcladv
, u16 rmtadv
)
1350 if (lcladv
& ADVERTISE_1000XPAUSE
) {
1351 if (lcladv
& ADVERTISE_1000XPSE_ASYM
) {
1352 if (rmtadv
& LPA_1000XPAUSE
)
1353 cap
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
1354 else if (rmtadv
& LPA_1000XPAUSE_ASYM
)
1357 if (rmtadv
& LPA_1000XPAUSE
)
1358 cap
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
1360 } else if (lcladv
& ADVERTISE_1000XPSE_ASYM
) {
1361 if ((rmtadv
& LPA_1000XPAUSE
) && (rmtadv
& LPA_1000XPAUSE_ASYM
))
1368 static void tg3_setup_flow_control(struct tg3
*tp
, u32 lcladv
, u32 rmtadv
)
1372 u32 old_rx_mode
= tp
->rx_mode
;
1373 u32 old_tx_mode
= tp
->tx_mode
;
1375 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)
1376 autoneg
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]->autoneg
;
1378 autoneg
= tp
->link_config
.autoneg
;
1380 if (autoneg
== AUTONEG_ENABLE
&&
1381 (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
)) {
1382 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)
1383 flowctrl
= tg3_resolve_flowctrl_1000X(lcladv
, rmtadv
);
1385 flowctrl
= mii_resolve_flowctrl_fdx(lcladv
, rmtadv
);
1387 flowctrl
= tp
->link_config
.flowctrl
;
1389 tp
->link_config
.active_flowctrl
= flowctrl
;
1391 if (flowctrl
& FLOW_CTRL_RX
)
1392 tp
->rx_mode
|= RX_MODE_FLOW_CTRL_ENABLE
;
1394 tp
->rx_mode
&= ~RX_MODE_FLOW_CTRL_ENABLE
;
1396 if (old_rx_mode
!= tp
->rx_mode
)
1397 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
1399 if (flowctrl
& FLOW_CTRL_TX
)
1400 tp
->tx_mode
|= TX_MODE_FLOW_CTRL_ENABLE
;
1402 tp
->tx_mode
&= ~TX_MODE_FLOW_CTRL_ENABLE
;
1404 if (old_tx_mode
!= tp
->tx_mode
)
1405 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
1408 static void tg3_adjust_link(struct net_device
*dev
)
1410 u8 oldflowctrl
, linkmesg
= 0;
1411 u32 mac_mode
, lcl_adv
, rmt_adv
;
1412 struct tg3
*tp
= netdev_priv(dev
);
1413 struct phy_device
*phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1415 spin_lock_bh(&tp
->lock
);
1417 mac_mode
= tp
->mac_mode
& ~(MAC_MODE_PORT_MODE_MASK
|
1418 MAC_MODE_HALF_DUPLEX
);
1420 oldflowctrl
= tp
->link_config
.active_flowctrl
;
1426 if (phydev
->speed
== SPEED_100
|| phydev
->speed
== SPEED_10
)
1427 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
1428 else if (phydev
->speed
== SPEED_1000
||
1429 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
)
1430 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
1432 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
1434 if (phydev
->duplex
== DUPLEX_HALF
)
1435 mac_mode
|= MAC_MODE_HALF_DUPLEX
;
1437 lcl_adv
= tg3_advert_flowctrl_1000T(
1438 tp
->link_config
.flowctrl
);
1441 rmt_adv
= LPA_PAUSE_CAP
;
1442 if (phydev
->asym_pause
)
1443 rmt_adv
|= LPA_PAUSE_ASYM
;
1446 tg3_setup_flow_control(tp
, lcl_adv
, rmt_adv
);
1448 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
1450 if (mac_mode
!= tp
->mac_mode
) {
1451 tp
->mac_mode
= mac_mode
;
1452 tw32_f(MAC_MODE
, tp
->mac_mode
);
1456 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
) {
1457 if (phydev
->speed
== SPEED_10
)
1459 MAC_MI_STAT_10MBPS_MODE
|
1460 MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
1462 tw32(MAC_MI_STAT
, MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
1465 if (phydev
->speed
== SPEED_1000
&& phydev
->duplex
== DUPLEX_HALF
)
1466 tw32(MAC_TX_LENGTHS
,
1467 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
1468 (6 << TX_LENGTHS_IPG_SHIFT
) |
1469 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT
)));
1471 tw32(MAC_TX_LENGTHS
,
1472 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
1473 (6 << TX_LENGTHS_IPG_SHIFT
) |
1474 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
)));
1476 if ((phydev
->link
&& tp
->link_config
.active_speed
== SPEED_INVALID
) ||
1477 (!phydev
->link
&& tp
->link_config
.active_speed
!= SPEED_INVALID
) ||
1478 phydev
->speed
!= tp
->link_config
.active_speed
||
1479 phydev
->duplex
!= tp
->link_config
.active_duplex
||
1480 oldflowctrl
!= tp
->link_config
.active_flowctrl
)
1483 tp
->link_config
.active_speed
= phydev
->speed
;
1484 tp
->link_config
.active_duplex
= phydev
->duplex
;
1486 spin_unlock_bh(&tp
->lock
);
1489 tg3_link_report(tp
);
1492 static int tg3_phy_init(struct tg3
*tp
)
1494 struct phy_device
*phydev
;
1496 if (tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
)
1499 /* Bring the PHY back to a known state. */
1502 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1504 /* Attach the MAC to the PHY. */
1505 phydev
= phy_connect(tp
->dev
, dev_name(&phydev
->dev
), tg3_adjust_link
,
1506 phydev
->dev_flags
, phydev
->interface
);
1507 if (IS_ERR(phydev
)) {
1508 dev_err(&tp
->pdev
->dev
, "Could not attach to PHY\n");
1509 return PTR_ERR(phydev
);
1512 /* Mask with MAC supported features. */
1513 switch (phydev
->interface
) {
1514 case PHY_INTERFACE_MODE_GMII
:
1515 case PHY_INTERFACE_MODE_RGMII
:
1516 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)) {
1517 phydev
->supported
&= (PHY_GBIT_FEATURES
|
1519 SUPPORTED_Asym_Pause
);
1523 case PHY_INTERFACE_MODE_MII
:
1524 phydev
->supported
&= (PHY_BASIC_FEATURES
|
1526 SUPPORTED_Asym_Pause
);
1529 phy_disconnect(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
1533 tp
->tg3_flags3
|= TG3_FLG3_PHY_CONNECTED
;
1535 phydev
->advertising
= phydev
->supported
;
1540 static void tg3_phy_start(struct tg3
*tp
)
1542 struct phy_device
*phydev
;
1544 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
1547 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1549 if (tp
->link_config
.phy_is_low_power
) {
1550 tp
->link_config
.phy_is_low_power
= 0;
1551 phydev
->speed
= tp
->link_config
.orig_speed
;
1552 phydev
->duplex
= tp
->link_config
.orig_duplex
;
1553 phydev
->autoneg
= tp
->link_config
.orig_autoneg
;
1554 phydev
->advertising
= tp
->link_config
.orig_advertising
;
1559 phy_start_aneg(phydev
);
1562 static void tg3_phy_stop(struct tg3
*tp
)
1564 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
1567 phy_stop(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
1570 static void tg3_phy_fini(struct tg3
*tp
)
1572 if (tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
) {
1573 phy_disconnect(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
1574 tp
->tg3_flags3
&= ~TG3_FLG3_PHY_CONNECTED
;
1578 static void tg3_phydsp_write(struct tg3
*tp
, u32 reg
, u32 val
)
1580 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, reg
);
1581 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, val
);
1584 static void tg3_phy_fet_toggle_apd(struct tg3
*tp
, bool enable
)
1588 if (!tg3_readphy(tp
, MII_TG3_FET_TEST
, &phytest
)) {
1591 tg3_writephy(tp
, MII_TG3_FET_TEST
,
1592 phytest
| MII_TG3_FET_SHADOW_EN
);
1593 if (!tg3_readphy(tp
, MII_TG3_FET_SHDW_AUXSTAT2
, &phy
)) {
1595 phy
|= MII_TG3_FET_SHDW_AUXSTAT2_APD
;
1597 phy
&= ~MII_TG3_FET_SHDW_AUXSTAT2_APD
;
1598 tg3_writephy(tp
, MII_TG3_FET_SHDW_AUXSTAT2
, phy
);
1600 tg3_writephy(tp
, MII_TG3_FET_TEST
, phytest
);
1604 static void tg3_phy_toggle_apd(struct tg3
*tp
, bool enable
)
1608 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
1609 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
&&
1610 (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)))
1613 if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) {
1614 tg3_phy_fet_toggle_apd(tp
, enable
);
1618 reg
= MII_TG3_MISC_SHDW_WREN
|
1619 MII_TG3_MISC_SHDW_SCR5_SEL
|
1620 MII_TG3_MISC_SHDW_SCR5_LPED
|
1621 MII_TG3_MISC_SHDW_SCR5_DLPTLM
|
1622 MII_TG3_MISC_SHDW_SCR5_SDTL
|
1623 MII_TG3_MISC_SHDW_SCR5_C125OE
;
1624 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5784
|| !enable
)
1625 reg
|= MII_TG3_MISC_SHDW_SCR5_DLLAPD
;
1627 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, reg
);
1630 reg
= MII_TG3_MISC_SHDW_WREN
|
1631 MII_TG3_MISC_SHDW_APD_SEL
|
1632 MII_TG3_MISC_SHDW_APD_WKTM_84MS
;
1634 reg
|= MII_TG3_MISC_SHDW_APD_ENABLE
;
1636 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, reg
);
1639 static void tg3_phy_toggle_automdix(struct tg3
*tp
, int enable
)
1643 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
1644 (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
))
1647 if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) {
1650 if (!tg3_readphy(tp
, MII_TG3_FET_TEST
, &ephy
)) {
1651 u32 reg
= MII_TG3_FET_SHDW_MISCCTRL
;
1653 tg3_writephy(tp
, MII_TG3_FET_TEST
,
1654 ephy
| MII_TG3_FET_SHADOW_EN
);
1655 if (!tg3_readphy(tp
, reg
, &phy
)) {
1657 phy
|= MII_TG3_FET_SHDW_MISCCTRL_MDIX
;
1659 phy
&= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX
;
1660 tg3_writephy(tp
, reg
, phy
);
1662 tg3_writephy(tp
, MII_TG3_FET_TEST
, ephy
);
1665 phy
= MII_TG3_AUXCTL_MISC_RDSEL_MISC
|
1666 MII_TG3_AUXCTL_SHDWSEL_MISC
;
1667 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
) &&
1668 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &phy
)) {
1670 phy
|= MII_TG3_AUXCTL_MISC_FORCE_AMDIX
;
1672 phy
&= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX
;
1673 phy
|= MII_TG3_AUXCTL_MISC_WREN
;
1674 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1679 static void tg3_phy_set_wirespeed(struct tg3
*tp
)
1683 if (tp
->tg3_flags2
& TG3_FLG2_NO_ETH_WIRE_SPEED
)
1686 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x7007) &&
1687 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &val
))
1688 tg3_writephy(tp
, MII_TG3_AUX_CTRL
,
1689 (val
| (1 << 15) | (1 << 4)));
1692 static void tg3_phy_apply_otp(struct tg3
*tp
)
1701 /* Enable SM_DSP clock and tx 6dB coding. */
1702 phy
= MII_TG3_AUXCTL_SHDWSEL_AUXCTL
|
1703 MII_TG3_AUXCTL_ACTL_SMDSP_ENA
|
1704 MII_TG3_AUXCTL_ACTL_TX_6DB
;
1705 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1707 phy
= ((otp
& TG3_OTP_AGCTGT_MASK
) >> TG3_OTP_AGCTGT_SHIFT
);
1708 phy
|= MII_TG3_DSP_TAP1_AGCTGT_DFLT
;
1709 tg3_phydsp_write(tp
, MII_TG3_DSP_TAP1
, phy
);
1711 phy
= ((otp
& TG3_OTP_HPFFLTR_MASK
) >> TG3_OTP_HPFFLTR_SHIFT
) |
1712 ((otp
& TG3_OTP_HPFOVER_MASK
) >> TG3_OTP_HPFOVER_SHIFT
);
1713 tg3_phydsp_write(tp
, MII_TG3_DSP_AADJ1CH0
, phy
);
1715 phy
= ((otp
& TG3_OTP_LPFDIS_MASK
) >> TG3_OTP_LPFDIS_SHIFT
);
1716 phy
|= MII_TG3_DSP_AADJ1CH3_ADCCKADJ
;
1717 tg3_phydsp_write(tp
, MII_TG3_DSP_AADJ1CH3
, phy
);
1719 phy
= ((otp
& TG3_OTP_VDAC_MASK
) >> TG3_OTP_VDAC_SHIFT
);
1720 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP75
, phy
);
1722 phy
= ((otp
& TG3_OTP_10BTAMP_MASK
) >> TG3_OTP_10BTAMP_SHIFT
);
1723 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP96
, phy
);
1725 phy
= ((otp
& TG3_OTP_ROFF_MASK
) >> TG3_OTP_ROFF_SHIFT
) |
1726 ((otp
& TG3_OTP_RCOFF_MASK
) >> TG3_OTP_RCOFF_SHIFT
);
1727 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP97
, phy
);
1729 /* Turn off SM_DSP clock. */
1730 phy
= MII_TG3_AUXCTL_SHDWSEL_AUXCTL
|
1731 MII_TG3_AUXCTL_ACTL_TX_6DB
;
1732 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1735 static int tg3_wait_macro_done(struct tg3
*tp
)
1742 if (!tg3_readphy(tp
, 0x16, &tmp32
)) {
1743 if ((tmp32
& 0x1000) == 0)
1753 static int tg3_phy_write_and_check_testpat(struct tg3
*tp
, int *resetp
)
1755 static const u32 test_pat
[4][6] = {
1756 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1757 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1758 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1759 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1763 for (chan
= 0; chan
< 4; chan
++) {
1766 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1767 (chan
* 0x2000) | 0x0200);
1768 tg3_writephy(tp
, 0x16, 0x0002);
1770 for (i
= 0; i
< 6; i
++)
1771 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
,
1774 tg3_writephy(tp
, 0x16, 0x0202);
1775 if (tg3_wait_macro_done(tp
)) {
1780 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1781 (chan
* 0x2000) | 0x0200);
1782 tg3_writephy(tp
, 0x16, 0x0082);
1783 if (tg3_wait_macro_done(tp
)) {
1788 tg3_writephy(tp
, 0x16, 0x0802);
1789 if (tg3_wait_macro_done(tp
)) {
1794 for (i
= 0; i
< 6; i
+= 2) {
1797 if (tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &low
) ||
1798 tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &high
) ||
1799 tg3_wait_macro_done(tp
)) {
1805 if (low
!= test_pat
[chan
][i
] ||
1806 high
!= test_pat
[chan
][i
+1]) {
1807 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000b);
1808 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x4001);
1809 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x4005);
1819 static int tg3_phy_reset_chanpat(struct tg3
*tp
)
1823 for (chan
= 0; chan
< 4; chan
++) {
1826 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1827 (chan
* 0x2000) | 0x0200);
1828 tg3_writephy(tp
, 0x16, 0x0002);
1829 for (i
= 0; i
< 6; i
++)
1830 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x000);
1831 tg3_writephy(tp
, 0x16, 0x0202);
1832 if (tg3_wait_macro_done(tp
))
1839 static int tg3_phy_reset_5703_4_5(struct tg3
*tp
)
1841 u32 reg32
, phy9_orig
;
1842 int retries
, do_phy_reset
, err
;
1848 err
= tg3_bmcr_reset(tp
);
1854 /* Disable transmitter and interrupt. */
1855 if (tg3_readphy(tp
, MII_TG3_EXT_CTRL
, ®32
))
1859 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, reg32
);
1861 /* Set full-duplex, 1000 mbps. */
1862 tg3_writephy(tp
, MII_BMCR
,
1863 BMCR_FULLDPLX
| TG3_BMCR_SPEED1000
);
1865 /* Set to master mode. */
1866 if (tg3_readphy(tp
, MII_TG3_CTRL
, &phy9_orig
))
1869 tg3_writephy(tp
, MII_TG3_CTRL
,
1870 (MII_TG3_CTRL_AS_MASTER
|
1871 MII_TG3_CTRL_ENABLE_AS_MASTER
));
1873 /* Enable SM_DSP_CLOCK and 6dB. */
1874 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1876 /* Block the PHY control access. */
1877 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8005);
1878 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0800);
1880 err
= tg3_phy_write_and_check_testpat(tp
, &do_phy_reset
);
1883 } while (--retries
);
1885 err
= tg3_phy_reset_chanpat(tp
);
1889 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8005);
1890 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0000);
1892 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8200);
1893 tg3_writephy(tp
, 0x16, 0x0000);
1895 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
1896 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
1897 /* Set Extended packet length bit for jumbo frames */
1898 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4400);
1900 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
1903 tg3_writephy(tp
, MII_TG3_CTRL
, phy9_orig
);
1905 if (!tg3_readphy(tp
, MII_TG3_EXT_CTRL
, ®32
)) {
1907 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, reg32
);
1914 /* This will reset the tigon3 PHY if there is no valid
1915 * link unless the FORCE argument is non-zero.
1917 static int tg3_phy_reset(struct tg3
*tp
)
1923 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
1926 val
= tr32(GRC_MISC_CFG
);
1927 tw32_f(GRC_MISC_CFG
, val
& ~GRC_MISC_CFG_EPHY_IDDQ
);
1930 err
= tg3_readphy(tp
, MII_BMSR
, &phy_status
);
1931 err
|= tg3_readphy(tp
, MII_BMSR
, &phy_status
);
1935 if (netif_running(tp
->dev
) && netif_carrier_ok(tp
->dev
)) {
1936 netif_carrier_off(tp
->dev
);
1937 tg3_link_report(tp
);
1940 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
1941 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
1942 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
1943 err
= tg3_phy_reset_5703_4_5(tp
);
1950 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
1951 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) {
1952 cpmuctrl
= tr32(TG3_CPMU_CTRL
);
1953 if (cpmuctrl
& CPMU_CTRL_GPHY_10MB_RXONLY
)
1955 cpmuctrl
& ~CPMU_CTRL_GPHY_10MB_RXONLY
);
1958 err
= tg3_bmcr_reset(tp
);
1962 if (cpmuctrl
& CPMU_CTRL_GPHY_10MB_RXONLY
) {
1965 phy
= MII_TG3_DSP_EXP8_AEDW
| MII_TG3_DSP_EXP8_REJ2MHz
;
1966 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP8
, phy
);
1968 tw32(TG3_CPMU_CTRL
, cpmuctrl
);
1971 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
||
1972 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5761_AX
) {
1975 val
= tr32(TG3_CPMU_LSPD_1000MB_CLK
);
1976 if ((val
& CPMU_LSPD_1000MB_MACCLK_MASK
) ==
1977 CPMU_LSPD_1000MB_MACCLK_12_5
) {
1978 val
&= ~CPMU_LSPD_1000MB_MACCLK_MASK
;
1980 tw32_f(TG3_CPMU_LSPD_1000MB_CLK
, val
);
1984 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
&&
1985 (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
))
1988 tg3_phy_apply_otp(tp
);
1990 if (tp
->tg3_flags3
& TG3_FLG3_PHY_ENABLE_APD
)
1991 tg3_phy_toggle_apd(tp
, true);
1993 tg3_phy_toggle_apd(tp
, false);
1996 if (tp
->tg3_flags2
& TG3_FLG2_PHY_ADC_BUG
) {
1997 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1998 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x201f);
1999 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x2aaa);
2000 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000a);
2001 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0323);
2002 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
2004 if (tp
->tg3_flags2
& TG3_FLG2_PHY_5704_A0_BUG
) {
2005 tg3_writephy(tp
, 0x1c, 0x8d68);
2006 tg3_writephy(tp
, 0x1c, 0x8d68);
2008 if (tp
->tg3_flags2
& TG3_FLG2_PHY_BER_BUG
) {
2009 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
2010 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000a);
2011 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x310b);
2012 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x201f);
2013 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x9506);
2014 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x401f);
2015 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x14e2);
2016 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
2017 } else if (tp
->tg3_flags2
& TG3_FLG2_PHY_JITTER_BUG
) {
2018 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
2019 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000a);
2020 if (tp
->tg3_flags2
& TG3_FLG2_PHY_ADJUST_TRIM
) {
2021 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x110b);
2022 tg3_writephy(tp
, MII_TG3_TEST1
,
2023 MII_TG3_TEST1_TRIM_EN
| 0x4);
2025 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x010b);
2026 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
2028 /* Set Extended packet length bit (bit 14) on all chips that */
2029 /* support jumbo frames */
2030 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5401
) {
2031 /* Cannot do read-modify-write on 5401 */
2032 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4c20);
2033 } else if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
2036 /* Set bit 14 with read-modify-write to preserve other bits */
2037 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0007) &&
2038 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &phy_reg
))
2039 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy_reg
| 0x4000);
2042 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2043 * jumbo frames transmission.
2045 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
2048 if (!tg3_readphy(tp
, MII_TG3_EXT_CTRL
, &phy_reg
))
2049 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
2050 phy_reg
| MII_TG3_EXT_CTRL_FIFO_ELASTIC
);
2053 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2054 /* adjust output voltage */
2055 tg3_writephy(tp
, MII_TG3_FET_PTEST
, 0x12);
2058 tg3_phy_toggle_automdix(tp
, 1);
2059 tg3_phy_set_wirespeed(tp
);
2063 static void tg3_frob_aux_power(struct tg3
*tp
)
2065 struct tg3
*tp_peer
= tp
;
2067 /* The GPIOs do something completely different on 57765. */
2068 if ((tp
->tg3_flags2
& TG3_FLG2_IS_NIC
) == 0 ||
2069 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
2072 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
2073 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
||
2074 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
) {
2075 struct net_device
*dev_peer
;
2077 dev_peer
= pci_get_drvdata(tp
->pdev_peer
);
2078 /* remove_one() may have been run on the peer. */
2082 tp_peer
= netdev_priv(dev_peer
);
2085 if ((tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) != 0 ||
2086 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0 ||
2087 (tp_peer
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) != 0 ||
2088 (tp_peer
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0) {
2089 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2090 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2091 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2092 (GRC_LCLCTRL_GPIO_OE0
|
2093 GRC_LCLCTRL_GPIO_OE1
|
2094 GRC_LCLCTRL_GPIO_OE2
|
2095 GRC_LCLCTRL_GPIO_OUTPUT0
|
2096 GRC_LCLCTRL_GPIO_OUTPUT1
),
2098 } else if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5761
||
2099 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5761S
) {
2100 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2101 u32 grc_local_ctrl
= GRC_LCLCTRL_GPIO_OE0
|
2102 GRC_LCLCTRL_GPIO_OE1
|
2103 GRC_LCLCTRL_GPIO_OE2
|
2104 GRC_LCLCTRL_GPIO_OUTPUT0
|
2105 GRC_LCLCTRL_GPIO_OUTPUT1
|
2107 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
2109 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OUTPUT2
;
2110 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
2112 grc_local_ctrl
&= ~GRC_LCLCTRL_GPIO_OUTPUT0
;
2113 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
2116 u32 grc_local_ctrl
= 0;
2118 if (tp_peer
!= tp
&&
2119 (tp_peer
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) != 0)
2122 /* Workaround to prevent overdrawing Amps. */
2123 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
2125 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE3
;
2126 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2127 grc_local_ctrl
, 100);
2130 /* On 5753 and variants, GPIO2 cannot be used. */
2131 no_gpio2
= tp
->nic_sram_data_cfg
&
2132 NIC_SRAM_DATA_CFG_NO_GPIO2
;
2134 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE0
|
2135 GRC_LCLCTRL_GPIO_OE1
|
2136 GRC_LCLCTRL_GPIO_OE2
|
2137 GRC_LCLCTRL_GPIO_OUTPUT1
|
2138 GRC_LCLCTRL_GPIO_OUTPUT2
;
2140 grc_local_ctrl
&= ~(GRC_LCLCTRL_GPIO_OE2
|
2141 GRC_LCLCTRL_GPIO_OUTPUT2
);
2143 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2144 grc_local_ctrl
, 100);
2146 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OUTPUT0
;
2148 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2149 grc_local_ctrl
, 100);
2152 grc_local_ctrl
&= ~GRC_LCLCTRL_GPIO_OUTPUT2
;
2153 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2154 grc_local_ctrl
, 100);
2158 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
2159 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) {
2160 if (tp_peer
!= tp
&&
2161 (tp_peer
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) != 0)
2164 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2165 (GRC_LCLCTRL_GPIO_OE1
|
2166 GRC_LCLCTRL_GPIO_OUTPUT1
), 100);
2168 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2169 GRC_LCLCTRL_GPIO_OE1
, 100);
2171 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2172 (GRC_LCLCTRL_GPIO_OE1
|
2173 GRC_LCLCTRL_GPIO_OUTPUT1
), 100);
2178 static int tg3_5700_link_polarity(struct tg3
*tp
, u32 speed
)
2180 if (tp
->led_ctrl
== LED_CTRL_MODE_PHY_2
)
2182 else if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5411
) {
2183 if (speed
!= SPEED_10
)
2185 } else if (speed
== SPEED_10
)
2191 static int tg3_setup_phy(struct tg3
*, int);
2193 #define RESET_KIND_SHUTDOWN 0
2194 #define RESET_KIND_INIT 1
2195 #define RESET_KIND_SUSPEND 2
2197 static void tg3_write_sig_post_reset(struct tg3
*, int);
2198 static int tg3_halt_cpu(struct tg3
*, u32
);
2200 static void tg3_power_down_phy(struct tg3
*tp
, bool do_low_power
)
2204 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
2205 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
2206 u32 sg_dig_ctrl
= tr32(SG_DIG_CTRL
);
2207 u32 serdes_cfg
= tr32(MAC_SERDES_CFG
);
2210 SG_DIG_USING_HW_AUTONEG
| SG_DIG_SOFT_RESET
;
2211 tw32(SG_DIG_CTRL
, sg_dig_ctrl
);
2212 tw32(MAC_SERDES_CFG
, serdes_cfg
| (1 << 15));
2217 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2219 val
= tr32(GRC_MISC_CFG
);
2220 tw32_f(GRC_MISC_CFG
, val
| GRC_MISC_CFG_EPHY_IDDQ
);
2223 } else if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) {
2225 if (!tg3_readphy(tp
, MII_TG3_FET_TEST
, &phytest
)) {
2228 tg3_writephy(tp
, MII_ADVERTISE
, 0);
2229 tg3_writephy(tp
, MII_BMCR
,
2230 BMCR_ANENABLE
| BMCR_ANRESTART
);
2232 tg3_writephy(tp
, MII_TG3_FET_TEST
,
2233 phytest
| MII_TG3_FET_SHADOW_EN
);
2234 if (!tg3_readphy(tp
, MII_TG3_FET_SHDW_AUXMODE4
, &phy
)) {
2235 phy
|= MII_TG3_FET_SHDW_AUXMODE4_SBPD
;
2237 MII_TG3_FET_SHDW_AUXMODE4
,
2240 tg3_writephy(tp
, MII_TG3_FET_TEST
, phytest
);
2243 } else if (do_low_power
) {
2244 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
2245 MII_TG3_EXT_CTRL_FORCE_LED_OFF
);
2247 tg3_writephy(tp
, MII_TG3_AUX_CTRL
,
2248 MII_TG3_AUXCTL_SHDWSEL_PWRCTL
|
2249 MII_TG3_AUXCTL_PCTL_100TX_LPWR
|
2250 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE
|
2251 MII_TG3_AUXCTL_PCTL_VREG_11V
);
2254 /* The PHY should not be powered down on some chips because
2257 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2258 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
2259 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
&&
2260 (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)))
2263 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
||
2264 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5761_AX
) {
2265 val
= tr32(TG3_CPMU_LSPD_1000MB_CLK
);
2266 val
&= ~CPMU_LSPD_1000MB_MACCLK_MASK
;
2267 val
|= CPMU_LSPD_1000MB_MACCLK_12_5
;
2268 tw32_f(TG3_CPMU_LSPD_1000MB_CLK
, val
);
2271 tg3_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
2274 /* tp->lock is held. */
2275 static int tg3_nvram_lock(struct tg3
*tp
)
2277 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
) {
2280 if (tp
->nvram_lock_cnt
== 0) {
2281 tw32(NVRAM_SWARB
, SWARB_REQ_SET1
);
2282 for (i
= 0; i
< 8000; i
++) {
2283 if (tr32(NVRAM_SWARB
) & SWARB_GNT1
)
2288 tw32(NVRAM_SWARB
, SWARB_REQ_CLR1
);
2292 tp
->nvram_lock_cnt
++;
2297 /* tp->lock is held. */
2298 static void tg3_nvram_unlock(struct tg3
*tp
)
2300 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
) {
2301 if (tp
->nvram_lock_cnt
> 0)
2302 tp
->nvram_lock_cnt
--;
2303 if (tp
->nvram_lock_cnt
== 0)
2304 tw32_f(NVRAM_SWARB
, SWARB_REQ_CLR1
);
2308 /* tp->lock is held. */
2309 static void tg3_enable_nvram_access(struct tg3
*tp
)
2311 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2312 !(tp
->tg3_flags3
& TG3_FLG3_PROTECTED_NVRAM
)) {
2313 u32 nvaccess
= tr32(NVRAM_ACCESS
);
2315 tw32(NVRAM_ACCESS
, nvaccess
| ACCESS_ENABLE
);
2319 /* tp->lock is held. */
2320 static void tg3_disable_nvram_access(struct tg3
*tp
)
2322 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2323 !(tp
->tg3_flags3
& TG3_FLG3_PROTECTED_NVRAM
)) {
2324 u32 nvaccess
= tr32(NVRAM_ACCESS
);
2326 tw32(NVRAM_ACCESS
, nvaccess
& ~ACCESS_ENABLE
);
2330 static int tg3_nvram_read_using_eeprom(struct tg3
*tp
,
2331 u32 offset
, u32
*val
)
2336 if (offset
> EEPROM_ADDR_ADDR_MASK
|| (offset
% 4) != 0)
2339 tmp
= tr32(GRC_EEPROM_ADDR
) & ~(EEPROM_ADDR_ADDR_MASK
|
2340 EEPROM_ADDR_DEVID_MASK
|
2342 tw32(GRC_EEPROM_ADDR
,
2344 (0 << EEPROM_ADDR_DEVID_SHIFT
) |
2345 ((offset
<< EEPROM_ADDR_ADDR_SHIFT
) &
2346 EEPROM_ADDR_ADDR_MASK
) |
2347 EEPROM_ADDR_READ
| EEPROM_ADDR_START
);
2349 for (i
= 0; i
< 1000; i
++) {
2350 tmp
= tr32(GRC_EEPROM_ADDR
);
2352 if (tmp
& EEPROM_ADDR_COMPLETE
)
2356 if (!(tmp
& EEPROM_ADDR_COMPLETE
))
2359 tmp
= tr32(GRC_EEPROM_DATA
);
2362 * The data will always be opposite the native endian
2363 * format. Perform a blind byteswap to compensate.
2370 #define NVRAM_CMD_TIMEOUT 10000
2372 static int tg3_nvram_exec_cmd(struct tg3
*tp
, u32 nvram_cmd
)
2376 tw32(NVRAM_CMD
, nvram_cmd
);
2377 for (i
= 0; i
< NVRAM_CMD_TIMEOUT
; i
++) {
2379 if (tr32(NVRAM_CMD
) & NVRAM_CMD_DONE
) {
2385 if (i
== NVRAM_CMD_TIMEOUT
)
2391 static u32
tg3_nvram_phys_addr(struct tg3
*tp
, u32 addr
)
2393 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM
) &&
2394 (tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) &&
2395 (tp
->tg3_flags2
& TG3_FLG2_FLASH
) &&
2396 !(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM_ADDR_TRANS
) &&
2397 (tp
->nvram_jedecnum
== JEDEC_ATMEL
))
2399 addr
= ((addr
/ tp
->nvram_pagesize
) <<
2400 ATMEL_AT45DB0X1B_PAGE_POS
) +
2401 (addr
% tp
->nvram_pagesize
);
2406 static u32
tg3_nvram_logical_addr(struct tg3
*tp
, u32 addr
)
2408 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM
) &&
2409 (tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) &&
2410 (tp
->tg3_flags2
& TG3_FLG2_FLASH
) &&
2411 !(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM_ADDR_TRANS
) &&
2412 (tp
->nvram_jedecnum
== JEDEC_ATMEL
))
2414 addr
= ((addr
>> ATMEL_AT45DB0X1B_PAGE_POS
) *
2415 tp
->nvram_pagesize
) +
2416 (addr
& ((1 << ATMEL_AT45DB0X1B_PAGE_POS
) - 1));
2421 /* NOTE: Data read in from NVRAM is byteswapped according to
2422 * the byteswapping settings for all other register accesses.
2423 * tg3 devices are BE devices, so on a BE machine, the data
2424 * returned will be exactly as it is seen in NVRAM. On a LE
2425 * machine, the 32-bit value will be byteswapped.
2427 static int tg3_nvram_read(struct tg3
*tp
, u32 offset
, u32
*val
)
2431 if (!(tp
->tg3_flags
& TG3_FLAG_NVRAM
))
2432 return tg3_nvram_read_using_eeprom(tp
, offset
, val
);
2434 offset
= tg3_nvram_phys_addr(tp
, offset
);
2436 if (offset
> NVRAM_ADDR_MSK
)
2439 ret
= tg3_nvram_lock(tp
);
2443 tg3_enable_nvram_access(tp
);
2445 tw32(NVRAM_ADDR
, offset
);
2446 ret
= tg3_nvram_exec_cmd(tp
, NVRAM_CMD_RD
| NVRAM_CMD_GO
|
2447 NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
| NVRAM_CMD_DONE
);
2450 *val
= tr32(NVRAM_RDDATA
);
2452 tg3_disable_nvram_access(tp
);
2454 tg3_nvram_unlock(tp
);
2459 /* Ensures NVRAM data is in bytestream format. */
2460 static int tg3_nvram_read_be32(struct tg3
*tp
, u32 offset
, __be32
*val
)
2463 int res
= tg3_nvram_read(tp
, offset
, &v
);
2465 *val
= cpu_to_be32(v
);
2469 /* tp->lock is held. */
2470 static void __tg3_set_mac_addr(struct tg3
*tp
, int skip_mac_1
)
2472 u32 addr_high
, addr_low
;
2475 addr_high
= ((tp
->dev
->dev_addr
[0] << 8) |
2476 tp
->dev
->dev_addr
[1]);
2477 addr_low
= ((tp
->dev
->dev_addr
[2] << 24) |
2478 (tp
->dev
->dev_addr
[3] << 16) |
2479 (tp
->dev
->dev_addr
[4] << 8) |
2480 (tp
->dev
->dev_addr
[5] << 0));
2481 for (i
= 0; i
< 4; i
++) {
2482 if (i
== 1 && skip_mac_1
)
2484 tw32(MAC_ADDR_0_HIGH
+ (i
* 8), addr_high
);
2485 tw32(MAC_ADDR_0_LOW
+ (i
* 8), addr_low
);
2488 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
2489 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
2490 for (i
= 0; i
< 12; i
++) {
2491 tw32(MAC_EXTADDR_0_HIGH
+ (i
* 8), addr_high
);
2492 tw32(MAC_EXTADDR_0_LOW
+ (i
* 8), addr_low
);
2496 addr_high
= (tp
->dev
->dev_addr
[0] +
2497 tp
->dev
->dev_addr
[1] +
2498 tp
->dev
->dev_addr
[2] +
2499 tp
->dev
->dev_addr
[3] +
2500 tp
->dev
->dev_addr
[4] +
2501 tp
->dev
->dev_addr
[5]) &
2502 TX_BACKOFF_SEED_MASK
;
2503 tw32(MAC_TX_BACKOFF_SEED
, addr_high
);
2506 static int tg3_set_power_state(struct tg3
*tp
, pci_power_t state
)
2509 bool device_should_wake
, do_low_power
;
2511 /* Make sure register accesses (indirect or otherwise)
2512 * will function correctly.
2514 pci_write_config_dword(tp
->pdev
,
2515 TG3PCI_MISC_HOST_CTRL
,
2516 tp
->misc_host_ctrl
);
2520 pci_enable_wake(tp
->pdev
, state
, false);
2521 pci_set_power_state(tp
->pdev
, PCI_D0
);
2523 /* Switch out of Vaux if it is a NIC */
2524 if (tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)
2525 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
, 100);
2535 netdev_err(tp
->dev
, "Invalid power state (D%d) requested\n",
2540 /* Restore the CLKREQ setting. */
2541 if (tp
->tg3_flags3
& TG3_FLG3_CLKREQ_BUG
) {
2544 pci_read_config_word(tp
->pdev
,
2545 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
2547 lnkctl
|= PCI_EXP_LNKCTL_CLKREQ_EN
;
2548 pci_write_config_word(tp
->pdev
,
2549 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
2553 misc_host_ctrl
= tr32(TG3PCI_MISC_HOST_CTRL
);
2554 tw32(TG3PCI_MISC_HOST_CTRL
,
2555 misc_host_ctrl
| MISC_HOST_CTRL_MASK_PCI_INT
);
2557 device_should_wake
= pci_pme_capable(tp
->pdev
, state
) &&
2558 device_may_wakeup(&tp
->pdev
->dev
) &&
2559 (tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
);
2561 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
2562 do_low_power
= false;
2563 if ((tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
) &&
2564 !tp
->link_config
.phy_is_low_power
) {
2565 struct phy_device
*phydev
;
2566 u32 phyid
, advertising
;
2568 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
2570 tp
->link_config
.phy_is_low_power
= 1;
2572 tp
->link_config
.orig_speed
= phydev
->speed
;
2573 tp
->link_config
.orig_duplex
= phydev
->duplex
;
2574 tp
->link_config
.orig_autoneg
= phydev
->autoneg
;
2575 tp
->link_config
.orig_advertising
= phydev
->advertising
;
2577 advertising
= ADVERTISED_TP
|
2579 ADVERTISED_Autoneg
|
2580 ADVERTISED_10baseT_Half
;
2582 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
2583 device_should_wake
) {
2584 if (tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
)
2586 ADVERTISED_100baseT_Half
|
2587 ADVERTISED_100baseT_Full
|
2588 ADVERTISED_10baseT_Full
;
2590 advertising
|= ADVERTISED_10baseT_Full
;
2593 phydev
->advertising
= advertising
;
2595 phy_start_aneg(phydev
);
2597 phyid
= phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
;
2598 if (phyid
!= PHY_ID_BCMAC131
) {
2599 phyid
&= PHY_BCM_OUI_MASK
;
2600 if (phyid
== PHY_BCM_OUI_1
||
2601 phyid
== PHY_BCM_OUI_2
||
2602 phyid
== PHY_BCM_OUI_3
)
2603 do_low_power
= true;
2607 do_low_power
= true;
2609 if (tp
->link_config
.phy_is_low_power
== 0) {
2610 tp
->link_config
.phy_is_low_power
= 1;
2611 tp
->link_config
.orig_speed
= tp
->link_config
.speed
;
2612 tp
->link_config
.orig_duplex
= tp
->link_config
.duplex
;
2613 tp
->link_config
.orig_autoneg
= tp
->link_config
.autoneg
;
2616 if (!(tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)) {
2617 tp
->link_config
.speed
= SPEED_10
;
2618 tp
->link_config
.duplex
= DUPLEX_HALF
;
2619 tp
->link_config
.autoneg
= AUTONEG_ENABLE
;
2620 tg3_setup_phy(tp
, 0);
2624 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2627 val
= tr32(GRC_VCPU_EXT_CTRL
);
2628 tw32(GRC_VCPU_EXT_CTRL
, val
| GRC_VCPU_EXT_CTRL_DISABLE_WOL
);
2629 } else if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
2633 for (i
= 0; i
< 200; i
++) {
2634 tg3_read_mem(tp
, NIC_SRAM_FW_ASF_STATUS_MBOX
, &val
);
2635 if (val
== ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1
)
2640 if (tp
->tg3_flags
& TG3_FLAG_WOL_CAP
)
2641 tg3_write_mem(tp
, NIC_SRAM_WOL_MBOX
, WOL_SIGNATURE
|
2642 WOL_DRV_STATE_SHUTDOWN
|
2646 if (device_should_wake
) {
2649 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)) {
2651 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x5a);
2655 if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)
2656 mac_mode
= MAC_MODE_PORT_MODE_GMII
;
2658 mac_mode
= MAC_MODE_PORT_MODE_MII
;
2660 mac_mode
|= tp
->mac_mode
& MAC_MODE_LINK_POLARITY
;
2661 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
2663 u32 speed
= (tp
->tg3_flags
&
2664 TG3_FLAG_WOL_SPEED_100MB
) ?
2665 SPEED_100
: SPEED_10
;
2666 if (tg3_5700_link_polarity(tp
, speed
))
2667 mac_mode
|= MAC_MODE_LINK_POLARITY
;
2669 mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
2672 mac_mode
= MAC_MODE_PORT_MODE_TBI
;
2675 if (!(tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
2676 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
2678 mac_mode
|= MAC_MODE_MAGIC_PKT_ENABLE
;
2679 if (((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
2680 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) &&
2681 ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
2682 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)))
2683 mac_mode
|= MAC_MODE_KEEP_FRAME_IN_WOL
;
2685 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
2686 mac_mode
|= tp
->mac_mode
&
2687 (MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
);
2688 if (mac_mode
& MAC_MODE_APE_TX_EN
)
2689 mac_mode
|= MAC_MODE_TDE_ENABLE
;
2692 tw32_f(MAC_MODE
, mac_mode
);
2695 tw32_f(MAC_RX_MODE
, RX_MODE_ENABLE
);
2699 if (!(tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
) &&
2700 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2701 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
2704 base_val
= tp
->pci_clock_ctrl
;
2705 base_val
|= (CLOCK_CTRL_RXCLK_DISABLE
|
2706 CLOCK_CTRL_TXCLK_DISABLE
);
2708 tw32_wait_f(TG3PCI_CLOCK_CTRL
, base_val
| CLOCK_CTRL_ALTCLK
|
2709 CLOCK_CTRL_PWRDOWN_PLL133
, 40);
2710 } else if ((tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
2711 (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) ||
2712 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)) {
2714 } else if (!((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2715 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))) {
2716 u32 newbits1
, newbits2
;
2718 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2719 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2720 newbits1
= (CLOCK_CTRL_RXCLK_DISABLE
|
2721 CLOCK_CTRL_TXCLK_DISABLE
|
2723 newbits2
= newbits1
| CLOCK_CTRL_44MHZ_CORE
;
2724 } else if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
2725 newbits1
= CLOCK_CTRL_625_CORE
;
2726 newbits2
= newbits1
| CLOCK_CTRL_ALTCLK
;
2728 newbits1
= CLOCK_CTRL_ALTCLK
;
2729 newbits2
= newbits1
| CLOCK_CTRL_44MHZ_CORE
;
2732 tw32_wait_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
| newbits1
,
2735 tw32_wait_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
| newbits2
,
2738 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
2741 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2742 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2743 newbits3
= (CLOCK_CTRL_RXCLK_DISABLE
|
2744 CLOCK_CTRL_TXCLK_DISABLE
|
2745 CLOCK_CTRL_44MHZ_CORE
);
2747 newbits3
= CLOCK_CTRL_44MHZ_CORE
;
2750 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
2751 tp
->pci_clock_ctrl
| newbits3
, 40);
2755 if (!(device_should_wake
) &&
2756 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
2757 tg3_power_down_phy(tp
, do_low_power
);
2759 tg3_frob_aux_power(tp
);
2761 /* Workaround for unstable PLL clock */
2762 if ((GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_AX
) ||
2763 (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_BX
)) {
2764 u32 val
= tr32(0x7d00);
2766 val
&= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2768 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
2771 err
= tg3_nvram_lock(tp
);
2772 tg3_halt_cpu(tp
, RX_CPU_BASE
);
2774 tg3_nvram_unlock(tp
);
2778 tg3_write_sig_post_reset(tp
, RESET_KIND_SHUTDOWN
);
2780 if (device_should_wake
)
2781 pci_enable_wake(tp
->pdev
, state
, true);
2783 /* Finally, set the new power state. */
2784 pci_set_power_state(tp
->pdev
, state
);
2789 static void tg3_aux_stat_to_speed_duplex(struct tg3
*tp
, u32 val
, u16
*speed
, u8
*duplex
)
2791 switch (val
& MII_TG3_AUX_STAT_SPDMASK
) {
2792 case MII_TG3_AUX_STAT_10HALF
:
2794 *duplex
= DUPLEX_HALF
;
2797 case MII_TG3_AUX_STAT_10FULL
:
2799 *duplex
= DUPLEX_FULL
;
2802 case MII_TG3_AUX_STAT_100HALF
:
2804 *duplex
= DUPLEX_HALF
;
2807 case MII_TG3_AUX_STAT_100FULL
:
2809 *duplex
= DUPLEX_FULL
;
2812 case MII_TG3_AUX_STAT_1000HALF
:
2813 *speed
= SPEED_1000
;
2814 *duplex
= DUPLEX_HALF
;
2817 case MII_TG3_AUX_STAT_1000FULL
:
2818 *speed
= SPEED_1000
;
2819 *duplex
= DUPLEX_FULL
;
2823 if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) {
2824 *speed
= (val
& MII_TG3_AUX_STAT_100
) ? SPEED_100
:
2826 *duplex
= (val
& MII_TG3_AUX_STAT_FULL
) ? DUPLEX_FULL
:
2830 *speed
= SPEED_INVALID
;
2831 *duplex
= DUPLEX_INVALID
;
2836 static void tg3_phy_copper_begin(struct tg3
*tp
)
2841 if (tp
->link_config
.phy_is_low_power
) {
2842 /* Entering low power mode. Disable gigabit and
2843 * 100baseT advertisements.
2845 tg3_writephy(tp
, MII_TG3_CTRL
, 0);
2847 new_adv
= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
2848 ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
);
2849 if (tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
)
2850 new_adv
|= (ADVERTISE_100HALF
| ADVERTISE_100FULL
);
2852 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2853 } else if (tp
->link_config
.speed
== SPEED_INVALID
) {
2854 if (tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)
2855 tp
->link_config
.advertising
&=
2856 ~(ADVERTISED_1000baseT_Half
|
2857 ADVERTISED_1000baseT_Full
);
2859 new_adv
= ADVERTISE_CSMA
;
2860 if (tp
->link_config
.advertising
& ADVERTISED_10baseT_Half
)
2861 new_adv
|= ADVERTISE_10HALF
;
2862 if (tp
->link_config
.advertising
& ADVERTISED_10baseT_Full
)
2863 new_adv
|= ADVERTISE_10FULL
;
2864 if (tp
->link_config
.advertising
& ADVERTISED_100baseT_Half
)
2865 new_adv
|= ADVERTISE_100HALF
;
2866 if (tp
->link_config
.advertising
& ADVERTISED_100baseT_Full
)
2867 new_adv
|= ADVERTISE_100FULL
;
2869 new_adv
|= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
2871 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2873 if (tp
->link_config
.advertising
&
2874 (ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
)) {
2876 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Half
)
2877 new_adv
|= MII_TG3_CTRL_ADV_1000_HALF
;
2878 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Full
)
2879 new_adv
|= MII_TG3_CTRL_ADV_1000_FULL
;
2880 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
) &&
2881 (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
2882 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
))
2883 new_adv
|= (MII_TG3_CTRL_AS_MASTER
|
2884 MII_TG3_CTRL_ENABLE_AS_MASTER
);
2885 tg3_writephy(tp
, MII_TG3_CTRL
, new_adv
);
2887 tg3_writephy(tp
, MII_TG3_CTRL
, 0);
2890 new_adv
= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
2891 new_adv
|= ADVERTISE_CSMA
;
2893 /* Asking for a specific link mode. */
2894 if (tp
->link_config
.speed
== SPEED_1000
) {
2895 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2897 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2898 new_adv
= MII_TG3_CTRL_ADV_1000_FULL
;
2900 new_adv
= MII_TG3_CTRL_ADV_1000_HALF
;
2901 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
2902 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
)
2903 new_adv
|= (MII_TG3_CTRL_AS_MASTER
|
2904 MII_TG3_CTRL_ENABLE_AS_MASTER
);
2906 if (tp
->link_config
.speed
== SPEED_100
) {
2907 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2908 new_adv
|= ADVERTISE_100FULL
;
2910 new_adv
|= ADVERTISE_100HALF
;
2912 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2913 new_adv
|= ADVERTISE_10FULL
;
2915 new_adv
|= ADVERTISE_10HALF
;
2917 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2922 tg3_writephy(tp
, MII_TG3_CTRL
, new_adv
);
2925 if (tp
->link_config
.autoneg
== AUTONEG_DISABLE
&&
2926 tp
->link_config
.speed
!= SPEED_INVALID
) {
2927 u32 bmcr
, orig_bmcr
;
2929 tp
->link_config
.active_speed
= tp
->link_config
.speed
;
2930 tp
->link_config
.active_duplex
= tp
->link_config
.duplex
;
2933 switch (tp
->link_config
.speed
) {
2939 bmcr
|= BMCR_SPEED100
;
2943 bmcr
|= TG3_BMCR_SPEED1000
;
2947 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2948 bmcr
|= BMCR_FULLDPLX
;
2950 if (!tg3_readphy(tp
, MII_BMCR
, &orig_bmcr
) &&
2951 (bmcr
!= orig_bmcr
)) {
2952 tg3_writephy(tp
, MII_BMCR
, BMCR_LOOPBACK
);
2953 for (i
= 0; i
< 1500; i
++) {
2957 if (tg3_readphy(tp
, MII_BMSR
, &tmp
) ||
2958 tg3_readphy(tp
, MII_BMSR
, &tmp
))
2960 if (!(tmp
& BMSR_LSTATUS
)) {
2965 tg3_writephy(tp
, MII_BMCR
, bmcr
);
2969 tg3_writephy(tp
, MII_BMCR
,
2970 BMCR_ANENABLE
| BMCR_ANRESTART
);
2974 static int tg3_init_5401phy_dsp(struct tg3
*tp
)
2978 /* Turn off tap power management. */
2979 /* Set Extended packet length bit */
2980 err
= tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4c20);
2982 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x0012);
2983 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x1804);
2985 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x0013);
2986 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x1204);
2988 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8006);
2989 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0132);
2991 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8006);
2992 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0232);
2994 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x201f);
2995 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0a20);
3002 static int tg3_copper_is_advertising_all(struct tg3
*tp
, u32 mask
)
3004 u32 adv_reg
, all_mask
= 0;
3006 if (mask
& ADVERTISED_10baseT_Half
)
3007 all_mask
|= ADVERTISE_10HALF
;
3008 if (mask
& ADVERTISED_10baseT_Full
)
3009 all_mask
|= ADVERTISE_10FULL
;
3010 if (mask
& ADVERTISED_100baseT_Half
)
3011 all_mask
|= ADVERTISE_100HALF
;
3012 if (mask
& ADVERTISED_100baseT_Full
)
3013 all_mask
|= ADVERTISE_100FULL
;
3015 if (tg3_readphy(tp
, MII_ADVERTISE
, &adv_reg
))
3018 if ((adv_reg
& all_mask
) != all_mask
)
3020 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)) {
3024 if (mask
& ADVERTISED_1000baseT_Half
)
3025 all_mask
|= ADVERTISE_1000HALF
;
3026 if (mask
& ADVERTISED_1000baseT_Full
)
3027 all_mask
|= ADVERTISE_1000FULL
;
3029 if (tg3_readphy(tp
, MII_TG3_CTRL
, &tg3_ctrl
))
3032 if ((tg3_ctrl
& all_mask
) != all_mask
)
3038 static int tg3_adv_1000T_flowctrl_ok(struct tg3
*tp
, u32
*lcladv
, u32
*rmtadv
)
3042 if (tg3_readphy(tp
, MII_ADVERTISE
, lcladv
))
3045 curadv
= *lcladv
& (ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
3046 reqadv
= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
3048 if (tp
->link_config
.active_duplex
== DUPLEX_FULL
) {
3049 if (curadv
!= reqadv
)
3052 if (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
)
3053 tg3_readphy(tp
, MII_LPA
, rmtadv
);
3055 /* Reprogram the advertisement register, even if it
3056 * does not affect the current link. If the link
3057 * gets renegotiated in the future, we can save an
3058 * additional renegotiation cycle by advertising
3059 * it correctly in the first place.
3061 if (curadv
!= reqadv
) {
3062 *lcladv
&= ~(ADVERTISE_PAUSE_CAP
|
3063 ADVERTISE_PAUSE_ASYM
);
3064 tg3_writephy(tp
, MII_ADVERTISE
, *lcladv
| reqadv
);
3071 static int tg3_setup_copper_phy(struct tg3
*tp
, int force_reset
)
3073 int current_link_up
;
3075 u32 lcl_adv
, rmt_adv
;
3083 (MAC_STATUS_SYNC_CHANGED
|
3084 MAC_STATUS_CFG_CHANGED
|
3085 MAC_STATUS_MI_COMPLETION
|
3086 MAC_STATUS_LNKSTATE_CHANGED
));
3089 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
3091 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
3095 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x02);
3097 /* Some third-party PHYs need to be reset on link going
3100 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
3101 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
3102 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) &&
3103 netif_carrier_ok(tp
->dev
)) {
3104 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3105 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
3106 !(bmsr
& BMSR_LSTATUS
))
3112 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5401
) {
3113 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3114 if (tg3_readphy(tp
, MII_BMSR
, &bmsr
) ||
3115 !(tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
))
3118 if (!(bmsr
& BMSR_LSTATUS
)) {
3119 err
= tg3_init_5401phy_dsp(tp
);
3123 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3124 for (i
= 0; i
< 1000; i
++) {
3126 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
3127 (bmsr
& BMSR_LSTATUS
)) {
3133 if ((tp
->phy_id
& TG3_PHY_ID_REV_MASK
) ==
3134 TG3_PHY_REV_BCM5401_B0
&&
3135 !(bmsr
& BMSR_LSTATUS
) &&
3136 tp
->link_config
.active_speed
== SPEED_1000
) {
3137 err
= tg3_phy_reset(tp
);
3139 err
= tg3_init_5401phy_dsp(tp
);
3144 } else if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
3145 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
) {
3146 /* 5701 {A0,B0} CRC bug workaround */
3147 tg3_writephy(tp
, 0x15, 0x0a75);
3148 tg3_writephy(tp
, 0x1c, 0x8c68);
3149 tg3_writephy(tp
, 0x1c, 0x8d68);
3150 tg3_writephy(tp
, 0x1c, 0x8c68);
3153 /* Clear pending interrupts... */
3154 tg3_readphy(tp
, MII_TG3_ISTAT
, &dummy
);
3155 tg3_readphy(tp
, MII_TG3_ISTAT
, &dummy
);
3157 if (tp
->tg3_flags
& TG3_FLAG_USE_MI_INTERRUPT
)
3158 tg3_writephy(tp
, MII_TG3_IMASK
, ~MII_TG3_INT_LINKCHG
);
3159 else if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
))
3160 tg3_writephy(tp
, MII_TG3_IMASK
, ~0);
3162 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
3163 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
3164 if (tp
->led_ctrl
== LED_CTRL_MODE_PHY_1
)
3165 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
3166 MII_TG3_EXT_CTRL_LNK3_LED_MODE
);
3168 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, 0);
3171 current_link_up
= 0;
3172 current_speed
= SPEED_INVALID
;
3173 current_duplex
= DUPLEX_INVALID
;
3175 if (tp
->tg3_flags2
& TG3_FLG2_CAPACITIVE_COUPLING
) {
3178 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4007);
3179 tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &val
);
3180 if (!(val
& (1 << 10))) {
3182 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, val
);
3188 for (i
= 0; i
< 100; i
++) {
3189 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3190 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
3191 (bmsr
& BMSR_LSTATUS
))
3196 if (bmsr
& BMSR_LSTATUS
) {
3199 tg3_readphy(tp
, MII_TG3_AUX_STAT
, &aux_stat
);
3200 for (i
= 0; i
< 2000; i
++) {
3202 if (!tg3_readphy(tp
, MII_TG3_AUX_STAT
, &aux_stat
) &&
3207 tg3_aux_stat_to_speed_duplex(tp
, aux_stat
,
3212 for (i
= 0; i
< 200; i
++) {
3213 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
3214 if (tg3_readphy(tp
, MII_BMCR
, &bmcr
))
3216 if (bmcr
&& bmcr
!= 0x7fff)
3224 tp
->link_config
.active_speed
= current_speed
;
3225 tp
->link_config
.active_duplex
= current_duplex
;
3227 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
3228 if ((bmcr
& BMCR_ANENABLE
) &&
3229 tg3_copper_is_advertising_all(tp
,
3230 tp
->link_config
.advertising
)) {
3231 if (tg3_adv_1000T_flowctrl_ok(tp
, &lcl_adv
,
3233 current_link_up
= 1;
3236 if (!(bmcr
& BMCR_ANENABLE
) &&
3237 tp
->link_config
.speed
== current_speed
&&
3238 tp
->link_config
.duplex
== current_duplex
&&
3239 tp
->link_config
.flowctrl
==
3240 tp
->link_config
.active_flowctrl
) {
3241 current_link_up
= 1;
3245 if (current_link_up
== 1 &&
3246 tp
->link_config
.active_duplex
== DUPLEX_FULL
)
3247 tg3_setup_flow_control(tp
, lcl_adv
, rmt_adv
);
3251 if (current_link_up
== 0 || tp
->link_config
.phy_is_low_power
) {
3254 tg3_phy_copper_begin(tp
);
3256 tg3_readphy(tp
, MII_BMSR
, &tmp
);
3257 if (!tg3_readphy(tp
, MII_BMSR
, &tmp
) &&
3258 (tmp
& BMSR_LSTATUS
))
3259 current_link_up
= 1;
3262 tp
->mac_mode
&= ~MAC_MODE_PORT_MODE_MASK
;
3263 if (current_link_up
== 1) {
3264 if (tp
->link_config
.active_speed
== SPEED_100
||
3265 tp
->link_config
.active_speed
== SPEED_10
)
3266 tp
->mac_mode
|= MAC_MODE_PORT_MODE_MII
;
3268 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
3269 } else if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
)
3270 tp
->mac_mode
|= MAC_MODE_PORT_MODE_MII
;
3272 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
3274 tp
->mac_mode
&= ~MAC_MODE_HALF_DUPLEX
;
3275 if (tp
->link_config
.active_duplex
== DUPLEX_HALF
)
3276 tp
->mac_mode
|= MAC_MODE_HALF_DUPLEX
;
3278 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) {
3279 if (current_link_up
== 1 &&
3280 tg3_5700_link_polarity(tp
, tp
->link_config
.active_speed
))
3281 tp
->mac_mode
|= MAC_MODE_LINK_POLARITY
;
3283 tp
->mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
3286 /* ??? Without this setting Netgear GA302T PHY does not
3287 * ??? send/receive packets...
3289 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5411
&&
3290 tp
->pci_chip_rev_id
== CHIPREV_ID_5700_ALTIMA
) {
3291 tp
->mi_mode
|= MAC_MI_MODE_AUTO_POLL
;
3292 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
3296 tw32_f(MAC_MODE
, tp
->mac_mode
);
3299 if (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) {
3300 /* Polled via timer. */
3301 tw32_f(MAC_EVENT
, 0);
3303 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
3307 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
&&
3308 current_link_up
== 1 &&
3309 tp
->link_config
.active_speed
== SPEED_1000
&&
3310 ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) ||
3311 (tp
->tg3_flags
& TG3_FLAG_PCI_HIGH_SPEED
))) {
3314 (MAC_STATUS_SYNC_CHANGED
|
3315 MAC_STATUS_CFG_CHANGED
));
3318 NIC_SRAM_FIRMWARE_MBOX
,
3319 NIC_SRAM_FIRMWARE_MBOX_MAGIC2
);
3322 /* Prevent send BD corruption. */
3323 if (tp
->tg3_flags3
& TG3_FLG3_CLKREQ_BUG
) {
3324 u16 oldlnkctl
, newlnkctl
;
3326 pci_read_config_word(tp
->pdev
,
3327 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
3329 if (tp
->link_config
.active_speed
== SPEED_100
||
3330 tp
->link_config
.active_speed
== SPEED_10
)
3331 newlnkctl
= oldlnkctl
& ~PCI_EXP_LNKCTL_CLKREQ_EN
;
3333 newlnkctl
= oldlnkctl
| PCI_EXP_LNKCTL_CLKREQ_EN
;
3334 if (newlnkctl
!= oldlnkctl
)
3335 pci_write_config_word(tp
->pdev
,
3336 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
3340 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
3341 if (current_link_up
)
3342 netif_carrier_on(tp
->dev
);
3344 netif_carrier_off(tp
->dev
);
3345 tg3_link_report(tp
);
3351 struct tg3_fiber_aneginfo
{
3353 #define ANEG_STATE_UNKNOWN 0
3354 #define ANEG_STATE_AN_ENABLE 1
3355 #define ANEG_STATE_RESTART_INIT 2
3356 #define ANEG_STATE_RESTART 3
3357 #define ANEG_STATE_DISABLE_LINK_OK 4
3358 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3359 #define ANEG_STATE_ABILITY_DETECT 6
3360 #define ANEG_STATE_ACK_DETECT_INIT 7
3361 #define ANEG_STATE_ACK_DETECT 8
3362 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3363 #define ANEG_STATE_COMPLETE_ACK 10
3364 #define ANEG_STATE_IDLE_DETECT_INIT 11
3365 #define ANEG_STATE_IDLE_DETECT 12
3366 #define ANEG_STATE_LINK_OK 13
3367 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3368 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3371 #define MR_AN_ENABLE 0x00000001
3372 #define MR_RESTART_AN 0x00000002
3373 #define MR_AN_COMPLETE 0x00000004
3374 #define MR_PAGE_RX 0x00000008
3375 #define MR_NP_LOADED 0x00000010
3376 #define MR_TOGGLE_TX 0x00000020
3377 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3378 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3379 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3380 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3381 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3382 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3383 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3384 #define MR_TOGGLE_RX 0x00002000
3385 #define MR_NP_RX 0x00004000
3387 #define MR_LINK_OK 0x80000000
3389 unsigned long link_time
, cur_time
;
3391 u32 ability_match_cfg
;
3392 int ability_match_count
;
3394 char ability_match
, idle_match
, ack_match
;
3396 u32 txconfig
, rxconfig
;
3397 #define ANEG_CFG_NP 0x00000080
3398 #define ANEG_CFG_ACK 0x00000040
3399 #define ANEG_CFG_RF2 0x00000020
3400 #define ANEG_CFG_RF1 0x00000010
3401 #define ANEG_CFG_PS2 0x00000001
3402 #define ANEG_CFG_PS1 0x00008000
3403 #define ANEG_CFG_HD 0x00004000
3404 #define ANEG_CFG_FD 0x00002000
3405 #define ANEG_CFG_INVAL 0x00001f06
3410 #define ANEG_TIMER_ENAB 2
3411 #define ANEG_FAILED -1
3413 #define ANEG_STATE_SETTLE_TIME 10000
3415 static int tg3_fiber_aneg_smachine(struct tg3
*tp
,
3416 struct tg3_fiber_aneginfo
*ap
)
3419 unsigned long delta
;
3423 if (ap
->state
== ANEG_STATE_UNKNOWN
) {
3427 ap
->ability_match_cfg
= 0;
3428 ap
->ability_match_count
= 0;
3429 ap
->ability_match
= 0;
3435 if (tr32(MAC_STATUS
) & MAC_STATUS_RCVD_CFG
) {
3436 rx_cfg_reg
= tr32(MAC_RX_AUTO_NEG
);
3438 if (rx_cfg_reg
!= ap
->ability_match_cfg
) {
3439 ap
->ability_match_cfg
= rx_cfg_reg
;
3440 ap
->ability_match
= 0;
3441 ap
->ability_match_count
= 0;
3443 if (++ap
->ability_match_count
> 1) {
3444 ap
->ability_match
= 1;
3445 ap
->ability_match_cfg
= rx_cfg_reg
;
3448 if (rx_cfg_reg
& ANEG_CFG_ACK
)
3456 ap
->ability_match_cfg
= 0;
3457 ap
->ability_match_count
= 0;
3458 ap
->ability_match
= 0;
3464 ap
->rxconfig
= rx_cfg_reg
;
3467 switch (ap
->state
) {
3468 case ANEG_STATE_UNKNOWN
:
3469 if (ap
->flags
& (MR_AN_ENABLE
| MR_RESTART_AN
))
3470 ap
->state
= ANEG_STATE_AN_ENABLE
;
3473 case ANEG_STATE_AN_ENABLE
:
3474 ap
->flags
&= ~(MR_AN_COMPLETE
| MR_PAGE_RX
);
3475 if (ap
->flags
& MR_AN_ENABLE
) {
3478 ap
->ability_match_cfg
= 0;
3479 ap
->ability_match_count
= 0;
3480 ap
->ability_match
= 0;
3484 ap
->state
= ANEG_STATE_RESTART_INIT
;
3486 ap
->state
= ANEG_STATE_DISABLE_LINK_OK
;
3490 case ANEG_STATE_RESTART_INIT
:
3491 ap
->link_time
= ap
->cur_time
;
3492 ap
->flags
&= ~(MR_NP_LOADED
);
3494 tw32(MAC_TX_AUTO_NEG
, 0);
3495 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3496 tw32_f(MAC_MODE
, tp
->mac_mode
);
3499 ret
= ANEG_TIMER_ENAB
;
3500 ap
->state
= ANEG_STATE_RESTART
;
3503 case ANEG_STATE_RESTART
:
3504 delta
= ap
->cur_time
- ap
->link_time
;
3505 if (delta
> ANEG_STATE_SETTLE_TIME
)
3506 ap
->state
= ANEG_STATE_ABILITY_DETECT_INIT
;
3508 ret
= ANEG_TIMER_ENAB
;
3511 case ANEG_STATE_DISABLE_LINK_OK
:
3515 case ANEG_STATE_ABILITY_DETECT_INIT
:
3516 ap
->flags
&= ~(MR_TOGGLE_TX
);
3517 ap
->txconfig
= ANEG_CFG_FD
;
3518 flowctrl
= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
3519 if (flowctrl
& ADVERTISE_1000XPAUSE
)
3520 ap
->txconfig
|= ANEG_CFG_PS1
;
3521 if (flowctrl
& ADVERTISE_1000XPSE_ASYM
)
3522 ap
->txconfig
|= ANEG_CFG_PS2
;
3523 tw32(MAC_TX_AUTO_NEG
, ap
->txconfig
);
3524 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3525 tw32_f(MAC_MODE
, tp
->mac_mode
);
3528 ap
->state
= ANEG_STATE_ABILITY_DETECT
;
3531 case ANEG_STATE_ABILITY_DETECT
:
3532 if (ap
->ability_match
!= 0 && ap
->rxconfig
!= 0)
3533 ap
->state
= ANEG_STATE_ACK_DETECT_INIT
;
3536 case ANEG_STATE_ACK_DETECT_INIT
:
3537 ap
->txconfig
|= ANEG_CFG_ACK
;
3538 tw32(MAC_TX_AUTO_NEG
, ap
->txconfig
);
3539 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3540 tw32_f(MAC_MODE
, tp
->mac_mode
);
3543 ap
->state
= ANEG_STATE_ACK_DETECT
;
3546 case ANEG_STATE_ACK_DETECT
:
3547 if (ap
->ack_match
!= 0) {
3548 if ((ap
->rxconfig
& ~ANEG_CFG_ACK
) ==
3549 (ap
->ability_match_cfg
& ~ANEG_CFG_ACK
)) {
3550 ap
->state
= ANEG_STATE_COMPLETE_ACK_INIT
;
3552 ap
->state
= ANEG_STATE_AN_ENABLE
;
3554 } else if (ap
->ability_match
!= 0 &&
3555 ap
->rxconfig
== 0) {
3556 ap
->state
= ANEG_STATE_AN_ENABLE
;
3560 case ANEG_STATE_COMPLETE_ACK_INIT
:
3561 if (ap
->rxconfig
& ANEG_CFG_INVAL
) {
3565 ap
->flags
&= ~(MR_LP_ADV_FULL_DUPLEX
|
3566 MR_LP_ADV_HALF_DUPLEX
|
3567 MR_LP_ADV_SYM_PAUSE
|
3568 MR_LP_ADV_ASYM_PAUSE
|
3569 MR_LP_ADV_REMOTE_FAULT1
|
3570 MR_LP_ADV_REMOTE_FAULT2
|
3571 MR_LP_ADV_NEXT_PAGE
|
3574 if (ap
->rxconfig
& ANEG_CFG_FD
)
3575 ap
->flags
|= MR_LP_ADV_FULL_DUPLEX
;
3576 if (ap
->rxconfig
& ANEG_CFG_HD
)
3577 ap
->flags
|= MR_LP_ADV_HALF_DUPLEX
;
3578 if (ap
->rxconfig
& ANEG_CFG_PS1
)
3579 ap
->flags
|= MR_LP_ADV_SYM_PAUSE
;
3580 if (ap
->rxconfig
& ANEG_CFG_PS2
)
3581 ap
->flags
|= MR_LP_ADV_ASYM_PAUSE
;
3582 if (ap
->rxconfig
& ANEG_CFG_RF1
)
3583 ap
->flags
|= MR_LP_ADV_REMOTE_FAULT1
;
3584 if (ap
->rxconfig
& ANEG_CFG_RF2
)
3585 ap
->flags
|= MR_LP_ADV_REMOTE_FAULT2
;
3586 if (ap
->rxconfig
& ANEG_CFG_NP
)
3587 ap
->flags
|= MR_LP_ADV_NEXT_PAGE
;
3589 ap
->link_time
= ap
->cur_time
;
3591 ap
->flags
^= (MR_TOGGLE_TX
);
3592 if (ap
->rxconfig
& 0x0008)
3593 ap
->flags
|= MR_TOGGLE_RX
;
3594 if (ap
->rxconfig
& ANEG_CFG_NP
)
3595 ap
->flags
|= MR_NP_RX
;
3596 ap
->flags
|= MR_PAGE_RX
;
3598 ap
->state
= ANEG_STATE_COMPLETE_ACK
;
3599 ret
= ANEG_TIMER_ENAB
;
3602 case ANEG_STATE_COMPLETE_ACK
:
3603 if (ap
->ability_match
!= 0 &&
3604 ap
->rxconfig
== 0) {
3605 ap
->state
= ANEG_STATE_AN_ENABLE
;
3608 delta
= ap
->cur_time
- ap
->link_time
;
3609 if (delta
> ANEG_STATE_SETTLE_TIME
) {
3610 if (!(ap
->flags
& (MR_LP_ADV_NEXT_PAGE
))) {
3611 ap
->state
= ANEG_STATE_IDLE_DETECT_INIT
;
3613 if ((ap
->txconfig
& ANEG_CFG_NP
) == 0 &&
3614 !(ap
->flags
& MR_NP_RX
)) {
3615 ap
->state
= ANEG_STATE_IDLE_DETECT_INIT
;
3623 case ANEG_STATE_IDLE_DETECT_INIT
:
3624 ap
->link_time
= ap
->cur_time
;
3625 tp
->mac_mode
&= ~MAC_MODE_SEND_CONFIGS
;
3626 tw32_f(MAC_MODE
, tp
->mac_mode
);
3629 ap
->state
= ANEG_STATE_IDLE_DETECT
;
3630 ret
= ANEG_TIMER_ENAB
;
3633 case ANEG_STATE_IDLE_DETECT
:
3634 if (ap
->ability_match
!= 0 &&
3635 ap
->rxconfig
== 0) {
3636 ap
->state
= ANEG_STATE_AN_ENABLE
;
3639 delta
= ap
->cur_time
- ap
->link_time
;
3640 if (delta
> ANEG_STATE_SETTLE_TIME
) {
3641 /* XXX another gem from the Broadcom driver :( */
3642 ap
->state
= ANEG_STATE_LINK_OK
;
3646 case ANEG_STATE_LINK_OK
:
3647 ap
->flags
|= (MR_AN_COMPLETE
| MR_LINK_OK
);
3651 case ANEG_STATE_NEXT_PAGE_WAIT_INIT
:
3652 /* ??? unimplemented */
3655 case ANEG_STATE_NEXT_PAGE_WAIT
:
3656 /* ??? unimplemented */
3667 static int fiber_autoneg(struct tg3
*tp
, u32
*txflags
, u32
*rxflags
)
3670 struct tg3_fiber_aneginfo aninfo
;
3671 int status
= ANEG_FAILED
;
3675 tw32_f(MAC_TX_AUTO_NEG
, 0);
3677 tmp
= tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
;
3678 tw32_f(MAC_MODE
, tmp
| MAC_MODE_PORT_MODE_GMII
);
3681 tw32_f(MAC_MODE
, tp
->mac_mode
| MAC_MODE_SEND_CONFIGS
);
3684 memset(&aninfo
, 0, sizeof(aninfo
));
3685 aninfo
.flags
|= MR_AN_ENABLE
;
3686 aninfo
.state
= ANEG_STATE_UNKNOWN
;
3687 aninfo
.cur_time
= 0;
3689 while (++tick
< 195000) {
3690 status
= tg3_fiber_aneg_smachine(tp
, &aninfo
);
3691 if (status
== ANEG_DONE
|| status
== ANEG_FAILED
)
3697 tp
->mac_mode
&= ~MAC_MODE_SEND_CONFIGS
;
3698 tw32_f(MAC_MODE
, tp
->mac_mode
);
3701 *txflags
= aninfo
.txconfig
;
3702 *rxflags
= aninfo
.flags
;
3704 if (status
== ANEG_DONE
&&
3705 (aninfo
.flags
& (MR_AN_COMPLETE
| MR_LINK_OK
|
3706 MR_LP_ADV_FULL_DUPLEX
)))
3712 static void tg3_init_bcm8002(struct tg3
*tp
)
3714 u32 mac_status
= tr32(MAC_STATUS
);
3717 /* Reset when initting first time or we have a link. */
3718 if ((tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) &&
3719 !(mac_status
& MAC_STATUS_PCS_SYNCED
))
3722 /* Set PLL lock range. */
3723 tg3_writephy(tp
, 0x16, 0x8007);
3726 tg3_writephy(tp
, MII_BMCR
, BMCR_RESET
);
3728 /* Wait for reset to complete. */
3729 /* XXX schedule_timeout() ... */
3730 for (i
= 0; i
< 500; i
++)
3733 /* Config mode; select PMA/Ch 1 regs. */
3734 tg3_writephy(tp
, 0x10, 0x8411);
3736 /* Enable auto-lock and comdet, select txclk for tx. */
3737 tg3_writephy(tp
, 0x11, 0x0a10);
3739 tg3_writephy(tp
, 0x18, 0x00a0);
3740 tg3_writephy(tp
, 0x16, 0x41ff);
3742 /* Assert and deassert POR. */
3743 tg3_writephy(tp
, 0x13, 0x0400);
3745 tg3_writephy(tp
, 0x13, 0x0000);
3747 tg3_writephy(tp
, 0x11, 0x0a50);
3749 tg3_writephy(tp
, 0x11, 0x0a10);
3751 /* Wait for signal to stabilize */
3752 /* XXX schedule_timeout() ... */
3753 for (i
= 0; i
< 15000; i
++)
3756 /* Deselect the channel register so we can read the PHYID
3759 tg3_writephy(tp
, 0x10, 0x8011);
3762 static int tg3_setup_fiber_hw_autoneg(struct tg3
*tp
, u32 mac_status
)
3765 u32 sg_dig_ctrl
, sg_dig_status
;
3766 u32 serdes_cfg
, expected_sg_dig_ctrl
;
3767 int workaround
, port_a
;
3768 int current_link_up
;
3771 expected_sg_dig_ctrl
= 0;
3774 current_link_up
= 0;
3776 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5704_A0
&&
3777 tp
->pci_chip_rev_id
!= CHIPREV_ID_5704_A1
) {
3779 if (tr32(TG3PCI_DUAL_MAC_CTRL
) & DUAL_MAC_CTRL_ID
)
3782 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3783 /* preserve bits 20-23 for voltage regulator */
3784 serdes_cfg
= tr32(MAC_SERDES_CFG
) & 0x00f06fff;
3787 sg_dig_ctrl
= tr32(SG_DIG_CTRL
);
3789 if (tp
->link_config
.autoneg
!= AUTONEG_ENABLE
) {
3790 if (sg_dig_ctrl
& SG_DIG_USING_HW_AUTONEG
) {
3792 u32 val
= serdes_cfg
;
3798 tw32_f(MAC_SERDES_CFG
, val
);
3801 tw32_f(SG_DIG_CTRL
, SG_DIG_COMMON_SETUP
);
3803 if (mac_status
& MAC_STATUS_PCS_SYNCED
) {
3804 tg3_setup_flow_control(tp
, 0, 0);
3805 current_link_up
= 1;
3810 /* Want auto-negotiation. */
3811 expected_sg_dig_ctrl
= SG_DIG_USING_HW_AUTONEG
| SG_DIG_COMMON_SETUP
;
3813 flowctrl
= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
3814 if (flowctrl
& ADVERTISE_1000XPAUSE
)
3815 expected_sg_dig_ctrl
|= SG_DIG_PAUSE_CAP
;
3816 if (flowctrl
& ADVERTISE_1000XPSE_ASYM
)
3817 expected_sg_dig_ctrl
|= SG_DIG_ASYM_PAUSE
;
3819 if (sg_dig_ctrl
!= expected_sg_dig_ctrl
) {
3820 if ((tp
->tg3_flags2
& TG3_FLG2_PARALLEL_DETECT
) &&
3821 tp
->serdes_counter
&&
3822 ((mac_status
& (MAC_STATUS_PCS_SYNCED
|
3823 MAC_STATUS_RCVD_CFG
)) ==
3824 MAC_STATUS_PCS_SYNCED
)) {
3825 tp
->serdes_counter
--;
3826 current_link_up
= 1;
3831 tw32_f(MAC_SERDES_CFG
, serdes_cfg
| 0xc011000);
3832 tw32_f(SG_DIG_CTRL
, expected_sg_dig_ctrl
| SG_DIG_SOFT_RESET
);
3834 tw32_f(SG_DIG_CTRL
, expected_sg_dig_ctrl
);
3836 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5704S
;
3837 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
3838 } else if (mac_status
& (MAC_STATUS_PCS_SYNCED
|
3839 MAC_STATUS_SIGNAL_DET
)) {
3840 sg_dig_status
= tr32(SG_DIG_STATUS
);
3841 mac_status
= tr32(MAC_STATUS
);
3843 if ((sg_dig_status
& SG_DIG_AUTONEG_COMPLETE
) &&
3844 (mac_status
& MAC_STATUS_PCS_SYNCED
)) {
3845 u32 local_adv
= 0, remote_adv
= 0;
3847 if (sg_dig_ctrl
& SG_DIG_PAUSE_CAP
)
3848 local_adv
|= ADVERTISE_1000XPAUSE
;
3849 if (sg_dig_ctrl
& SG_DIG_ASYM_PAUSE
)
3850 local_adv
|= ADVERTISE_1000XPSE_ASYM
;
3852 if (sg_dig_status
& SG_DIG_PARTNER_PAUSE_CAPABLE
)
3853 remote_adv
|= LPA_1000XPAUSE
;
3854 if (sg_dig_status
& SG_DIG_PARTNER_ASYM_PAUSE
)
3855 remote_adv
|= LPA_1000XPAUSE_ASYM
;
3857 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
3858 current_link_up
= 1;
3859 tp
->serdes_counter
= 0;
3860 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
3861 } else if (!(sg_dig_status
& SG_DIG_AUTONEG_COMPLETE
)) {
3862 if (tp
->serdes_counter
)
3863 tp
->serdes_counter
--;
3866 u32 val
= serdes_cfg
;
3873 tw32_f(MAC_SERDES_CFG
, val
);
3876 tw32_f(SG_DIG_CTRL
, SG_DIG_COMMON_SETUP
);
3879 /* Link parallel detection - link is up */
3880 /* only if we have PCS_SYNC and not */
3881 /* receiving config code words */
3882 mac_status
= tr32(MAC_STATUS
);
3883 if ((mac_status
& MAC_STATUS_PCS_SYNCED
) &&
3884 !(mac_status
& MAC_STATUS_RCVD_CFG
)) {
3885 tg3_setup_flow_control(tp
, 0, 0);
3886 current_link_up
= 1;
3888 TG3_FLG2_PARALLEL_DETECT
;
3889 tp
->serdes_counter
=
3890 SERDES_PARALLEL_DET_TIMEOUT
;
3892 goto restart_autoneg
;
3896 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5704S
;
3897 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
3901 return current_link_up
;
3904 static int tg3_setup_fiber_by_hand(struct tg3
*tp
, u32 mac_status
)
3906 int current_link_up
= 0;
3908 if (!(mac_status
& MAC_STATUS_PCS_SYNCED
))
3911 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
3912 u32 txflags
, rxflags
;
3915 if (fiber_autoneg(tp
, &txflags
, &rxflags
)) {
3916 u32 local_adv
= 0, remote_adv
= 0;
3918 if (txflags
& ANEG_CFG_PS1
)
3919 local_adv
|= ADVERTISE_1000XPAUSE
;
3920 if (txflags
& ANEG_CFG_PS2
)
3921 local_adv
|= ADVERTISE_1000XPSE_ASYM
;
3923 if (rxflags
& MR_LP_ADV_SYM_PAUSE
)
3924 remote_adv
|= LPA_1000XPAUSE
;
3925 if (rxflags
& MR_LP_ADV_ASYM_PAUSE
)
3926 remote_adv
|= LPA_1000XPAUSE_ASYM
;
3928 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
3930 current_link_up
= 1;
3932 for (i
= 0; i
< 30; i
++) {
3935 (MAC_STATUS_SYNC_CHANGED
|
3936 MAC_STATUS_CFG_CHANGED
));
3938 if ((tr32(MAC_STATUS
) &
3939 (MAC_STATUS_SYNC_CHANGED
|
3940 MAC_STATUS_CFG_CHANGED
)) == 0)
3944 mac_status
= tr32(MAC_STATUS
);
3945 if (current_link_up
== 0 &&
3946 (mac_status
& MAC_STATUS_PCS_SYNCED
) &&
3947 !(mac_status
& MAC_STATUS_RCVD_CFG
))
3948 current_link_up
= 1;
3950 tg3_setup_flow_control(tp
, 0, 0);
3952 /* Forcing 1000FD link up. */
3953 current_link_up
= 1;
3955 tw32_f(MAC_MODE
, (tp
->mac_mode
| MAC_MODE_SEND_CONFIGS
));
3958 tw32_f(MAC_MODE
, tp
->mac_mode
);
3963 return current_link_up
;
3966 static int tg3_setup_fiber_phy(struct tg3
*tp
, int force_reset
)
3969 u16 orig_active_speed
;
3970 u8 orig_active_duplex
;
3972 int current_link_up
;
3975 orig_pause_cfg
= tp
->link_config
.active_flowctrl
;
3976 orig_active_speed
= tp
->link_config
.active_speed
;
3977 orig_active_duplex
= tp
->link_config
.active_duplex
;
3979 if (!(tp
->tg3_flags2
& TG3_FLG2_HW_AUTONEG
) &&
3980 netif_carrier_ok(tp
->dev
) &&
3981 (tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
)) {
3982 mac_status
= tr32(MAC_STATUS
);
3983 mac_status
&= (MAC_STATUS_PCS_SYNCED
|
3984 MAC_STATUS_SIGNAL_DET
|
3985 MAC_STATUS_CFG_CHANGED
|
3986 MAC_STATUS_RCVD_CFG
);
3987 if (mac_status
== (MAC_STATUS_PCS_SYNCED
|
3988 MAC_STATUS_SIGNAL_DET
)) {
3989 tw32_f(MAC_STATUS
, (MAC_STATUS_SYNC_CHANGED
|
3990 MAC_STATUS_CFG_CHANGED
));
3995 tw32_f(MAC_TX_AUTO_NEG
, 0);
3997 tp
->mac_mode
&= ~(MAC_MODE_PORT_MODE_MASK
| MAC_MODE_HALF_DUPLEX
);
3998 tp
->mac_mode
|= MAC_MODE_PORT_MODE_TBI
;
3999 tw32_f(MAC_MODE
, tp
->mac_mode
);
4002 if (tp
->phy_id
== TG3_PHY_ID_BCM8002
)
4003 tg3_init_bcm8002(tp
);
4005 /* Enable link change event even when serdes polling. */
4006 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
4009 current_link_up
= 0;
4010 mac_status
= tr32(MAC_STATUS
);
4012 if (tp
->tg3_flags2
& TG3_FLG2_HW_AUTONEG
)
4013 current_link_up
= tg3_setup_fiber_hw_autoneg(tp
, mac_status
);
4015 current_link_up
= tg3_setup_fiber_by_hand(tp
, mac_status
);
4017 tp
->napi
[0].hw_status
->status
=
4018 (SD_STATUS_UPDATED
|
4019 (tp
->napi
[0].hw_status
->status
& ~SD_STATUS_LINK_CHG
));
4021 for (i
= 0; i
< 100; i
++) {
4022 tw32_f(MAC_STATUS
, (MAC_STATUS_SYNC_CHANGED
|
4023 MAC_STATUS_CFG_CHANGED
));
4025 if ((tr32(MAC_STATUS
) & (MAC_STATUS_SYNC_CHANGED
|
4026 MAC_STATUS_CFG_CHANGED
|
4027 MAC_STATUS_LNKSTATE_CHANGED
)) == 0)
4031 mac_status
= tr32(MAC_STATUS
);
4032 if ((mac_status
& MAC_STATUS_PCS_SYNCED
) == 0) {
4033 current_link_up
= 0;
4034 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
&&
4035 tp
->serdes_counter
== 0) {
4036 tw32_f(MAC_MODE
, (tp
->mac_mode
|
4037 MAC_MODE_SEND_CONFIGS
));
4039 tw32_f(MAC_MODE
, tp
->mac_mode
);
4043 if (current_link_up
== 1) {
4044 tp
->link_config
.active_speed
= SPEED_1000
;
4045 tp
->link_config
.active_duplex
= DUPLEX_FULL
;
4046 tw32(MAC_LED_CTRL
, (tp
->led_ctrl
|
4047 LED_CTRL_LNKLED_OVERRIDE
|
4048 LED_CTRL_1000MBPS_ON
));
4050 tp
->link_config
.active_speed
= SPEED_INVALID
;
4051 tp
->link_config
.active_duplex
= DUPLEX_INVALID
;
4052 tw32(MAC_LED_CTRL
, (tp
->led_ctrl
|
4053 LED_CTRL_LNKLED_OVERRIDE
|
4054 LED_CTRL_TRAFFIC_OVERRIDE
));
4057 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
4058 if (current_link_up
)
4059 netif_carrier_on(tp
->dev
);
4061 netif_carrier_off(tp
->dev
);
4062 tg3_link_report(tp
);
4064 u32 now_pause_cfg
= tp
->link_config
.active_flowctrl
;
4065 if (orig_pause_cfg
!= now_pause_cfg
||
4066 orig_active_speed
!= tp
->link_config
.active_speed
||
4067 orig_active_duplex
!= tp
->link_config
.active_duplex
)
4068 tg3_link_report(tp
);
4074 static int tg3_setup_fiber_mii_phy(struct tg3
*tp
, int force_reset
)
4076 int current_link_up
, err
= 0;
4080 u32 local_adv
, remote_adv
;
4082 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
4083 tw32_f(MAC_MODE
, tp
->mac_mode
);
4089 (MAC_STATUS_SYNC_CHANGED
|
4090 MAC_STATUS_CFG_CHANGED
|
4091 MAC_STATUS_MI_COMPLETION
|
4092 MAC_STATUS_LNKSTATE_CHANGED
));
4098 current_link_up
= 0;
4099 current_speed
= SPEED_INVALID
;
4100 current_duplex
= DUPLEX_INVALID
;
4102 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4103 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4104 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
4105 if (tr32(MAC_TX_STATUS
) & TX_STATUS_LINK_UP
)
4106 bmsr
|= BMSR_LSTATUS
;
4108 bmsr
&= ~BMSR_LSTATUS
;
4111 err
|= tg3_readphy(tp
, MII_BMCR
, &bmcr
);
4113 if ((tp
->link_config
.autoneg
== AUTONEG_ENABLE
) && !force_reset
&&
4114 (tp
->tg3_flags2
& TG3_FLG2_PARALLEL_DETECT
)) {
4115 /* do nothing, just check for link up at the end */
4116 } else if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
4119 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &adv
);
4120 new_adv
= adv
& ~(ADVERTISE_1000XFULL
| ADVERTISE_1000XHALF
|
4121 ADVERTISE_1000XPAUSE
|
4122 ADVERTISE_1000XPSE_ASYM
|
4125 new_adv
|= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
4127 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Half
)
4128 new_adv
|= ADVERTISE_1000XHALF
;
4129 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Full
)
4130 new_adv
|= ADVERTISE_1000XFULL
;
4132 if ((new_adv
!= adv
) || !(bmcr
& BMCR_ANENABLE
)) {
4133 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
4134 bmcr
|= BMCR_ANENABLE
| BMCR_ANRESTART
;
4135 tg3_writephy(tp
, MII_BMCR
, bmcr
);
4137 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
4138 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5714S
;
4139 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
4146 bmcr
&= ~BMCR_SPEED1000
;
4147 new_bmcr
= bmcr
& ~(BMCR_ANENABLE
| BMCR_FULLDPLX
);
4149 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
4150 new_bmcr
|= BMCR_FULLDPLX
;
4152 if (new_bmcr
!= bmcr
) {
4153 /* BMCR_SPEED1000 is a reserved bit that needs
4154 * to be set on write.
4156 new_bmcr
|= BMCR_SPEED1000
;
4158 /* Force a linkdown */
4159 if (netif_carrier_ok(tp
->dev
)) {
4162 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &adv
);
4163 adv
&= ~(ADVERTISE_1000XFULL
|
4164 ADVERTISE_1000XHALF
|
4166 tg3_writephy(tp
, MII_ADVERTISE
, adv
);
4167 tg3_writephy(tp
, MII_BMCR
, bmcr
|
4171 netif_carrier_off(tp
->dev
);
4173 tg3_writephy(tp
, MII_BMCR
, new_bmcr
);
4175 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4176 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4177 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
4179 if (tr32(MAC_TX_STATUS
) & TX_STATUS_LINK_UP
)
4180 bmsr
|= BMSR_LSTATUS
;
4182 bmsr
&= ~BMSR_LSTATUS
;
4184 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
4188 if (bmsr
& BMSR_LSTATUS
) {
4189 current_speed
= SPEED_1000
;
4190 current_link_up
= 1;
4191 if (bmcr
& BMCR_FULLDPLX
)
4192 current_duplex
= DUPLEX_FULL
;
4194 current_duplex
= DUPLEX_HALF
;
4199 if (bmcr
& BMCR_ANENABLE
) {
4202 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &local_adv
);
4203 err
|= tg3_readphy(tp
, MII_LPA
, &remote_adv
);
4204 common
= local_adv
& remote_adv
;
4205 if (common
& (ADVERTISE_1000XHALF
|
4206 ADVERTISE_1000XFULL
)) {
4207 if (common
& ADVERTISE_1000XFULL
)
4208 current_duplex
= DUPLEX_FULL
;
4210 current_duplex
= DUPLEX_HALF
;
4212 current_link_up
= 0;
4217 if (current_link_up
== 1 && current_duplex
== DUPLEX_FULL
)
4218 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
4220 tp
->mac_mode
&= ~MAC_MODE_HALF_DUPLEX
;
4221 if (tp
->link_config
.active_duplex
== DUPLEX_HALF
)
4222 tp
->mac_mode
|= MAC_MODE_HALF_DUPLEX
;
4224 tw32_f(MAC_MODE
, tp
->mac_mode
);
4227 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
4229 tp
->link_config
.active_speed
= current_speed
;
4230 tp
->link_config
.active_duplex
= current_duplex
;
4232 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
4233 if (current_link_up
)
4234 netif_carrier_on(tp
->dev
);
4236 netif_carrier_off(tp
->dev
);
4237 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
4239 tg3_link_report(tp
);
4244 static void tg3_serdes_parallel_detect(struct tg3
*tp
)
4246 if (tp
->serdes_counter
) {
4247 /* Give autoneg time to complete. */
4248 tp
->serdes_counter
--;
4252 if (!netif_carrier_ok(tp
->dev
) &&
4253 (tp
->link_config
.autoneg
== AUTONEG_ENABLE
)) {
4256 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
4257 if (bmcr
& BMCR_ANENABLE
) {
4260 /* Select shadow register 0x1f */
4261 tg3_writephy(tp
, 0x1c, 0x7c00);
4262 tg3_readphy(tp
, 0x1c, &phy1
);
4264 /* Select expansion interrupt status register */
4265 tg3_writephy(tp
, 0x17, 0x0f01);
4266 tg3_readphy(tp
, 0x15, &phy2
);
4267 tg3_readphy(tp
, 0x15, &phy2
);
4269 if ((phy1
& 0x10) && !(phy2
& 0x20)) {
4270 /* We have signal detect and not receiving
4271 * config code words, link is up by parallel
4275 bmcr
&= ~BMCR_ANENABLE
;
4276 bmcr
|= BMCR_SPEED1000
| BMCR_FULLDPLX
;
4277 tg3_writephy(tp
, MII_BMCR
, bmcr
);
4278 tp
->tg3_flags2
|= TG3_FLG2_PARALLEL_DETECT
;
4281 } else if (netif_carrier_ok(tp
->dev
) &&
4282 (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) &&
4283 (tp
->tg3_flags2
& TG3_FLG2_PARALLEL_DETECT
)) {
4286 /* Select expansion interrupt status register */
4287 tg3_writephy(tp
, 0x17, 0x0f01);
4288 tg3_readphy(tp
, 0x15, &phy2
);
4292 /* Config code words received, turn on autoneg. */
4293 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
4294 tg3_writephy(tp
, MII_BMCR
, bmcr
| BMCR_ANENABLE
);
4296 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
4302 static int tg3_setup_phy(struct tg3
*tp
, int force_reset
)
4306 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
4307 err
= tg3_setup_fiber_phy(tp
, force_reset
);
4308 else if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)
4309 err
= tg3_setup_fiber_mii_phy(tp
, force_reset
);
4311 err
= tg3_setup_copper_phy(tp
, force_reset
);
4313 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
) {
4316 val
= tr32(TG3_CPMU_CLCK_STAT
) & CPMU_CLCK_STAT_MAC_CLCK_MASK
;
4317 if (val
== CPMU_CLCK_STAT_MAC_CLCK_62_5
)
4319 else if (val
== CPMU_CLCK_STAT_MAC_CLCK_6_25
)
4324 val
= tr32(GRC_MISC_CFG
) & ~GRC_MISC_CFG_PRESCALAR_MASK
;
4325 val
|= (scale
<< GRC_MISC_CFG_PRESCALAR_SHIFT
);
4326 tw32(GRC_MISC_CFG
, val
);
4329 if (tp
->link_config
.active_speed
== SPEED_1000
&&
4330 tp
->link_config
.active_duplex
== DUPLEX_HALF
)
4331 tw32(MAC_TX_LENGTHS
,
4332 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
4333 (6 << TX_LENGTHS_IPG_SHIFT
) |
4334 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT
)));
4336 tw32(MAC_TX_LENGTHS
,
4337 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
4338 (6 << TX_LENGTHS_IPG_SHIFT
) |
4339 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
)));
4341 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
4342 if (netif_carrier_ok(tp
->dev
)) {
4343 tw32(HOSTCC_STAT_COAL_TICKS
,
4344 tp
->coal
.stats_block_coalesce_usecs
);
4346 tw32(HOSTCC_STAT_COAL_TICKS
, 0);
4350 if (tp
->tg3_flags
& TG3_FLAG_ASPM_WORKAROUND
) {
4351 u32 val
= tr32(PCIE_PWR_MGMT_THRESH
);
4352 if (!netif_carrier_ok(tp
->dev
))
4353 val
= (val
& ~PCIE_PWR_MGMT_L1_THRESH_MSK
) |
4356 val
|= PCIE_PWR_MGMT_L1_THRESH_MSK
;
4357 tw32(PCIE_PWR_MGMT_THRESH
, val
);
4363 /* This is called whenever we suspect that the system chipset is re-
4364 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4365 * is bogus tx completions. We try to recover by setting the
4366 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4369 static void tg3_tx_recover(struct tg3
*tp
)
4371 BUG_ON((tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
) ||
4372 tp
->write32_tx_mbox
== tg3_write_indirect_mbox
);
4374 netdev_warn(tp
->dev
,
4375 "The system may be re-ordering memory-mapped I/O "
4376 "cycles to the network device, attempting to recover. "
4377 "Please report the problem to the driver maintainer "
4378 "and include system chipset information.\n");
4380 spin_lock(&tp
->lock
);
4381 tp
->tg3_flags
|= TG3_FLAG_TX_RECOVERY_PENDING
;
4382 spin_unlock(&tp
->lock
);
4385 static inline u32
tg3_tx_avail(struct tg3_napi
*tnapi
)
4388 return tnapi
->tx_pending
-
4389 ((tnapi
->tx_prod
- tnapi
->tx_cons
) & (TG3_TX_RING_SIZE
- 1));
4392 /* Tigon3 never reports partial packet sends. So we do not
4393 * need special logic to handle SKBs that have not had all
4394 * of their frags sent yet, like SunGEM does.
4396 static void tg3_tx(struct tg3_napi
*tnapi
)
4398 struct tg3
*tp
= tnapi
->tp
;
4399 u32 hw_idx
= tnapi
->hw_status
->idx
[0].tx_consumer
;
4400 u32 sw_idx
= tnapi
->tx_cons
;
4401 struct netdev_queue
*txq
;
4402 int index
= tnapi
- tp
->napi
;
4404 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
4407 txq
= netdev_get_tx_queue(tp
->dev
, index
);
4409 while (sw_idx
!= hw_idx
) {
4410 struct ring_info
*ri
= &tnapi
->tx_buffers
[sw_idx
];
4411 struct sk_buff
*skb
= ri
->skb
;
4414 if (unlikely(skb
== NULL
)) {
4419 pci_unmap_single(tp
->pdev
,
4420 dma_unmap_addr(ri
, mapping
),
4426 sw_idx
= NEXT_TX(sw_idx
);
4428 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
4429 ri
= &tnapi
->tx_buffers
[sw_idx
];
4430 if (unlikely(ri
->skb
!= NULL
|| sw_idx
== hw_idx
))
4433 pci_unmap_page(tp
->pdev
,
4434 dma_unmap_addr(ri
, mapping
),
4435 skb_shinfo(skb
)->frags
[i
].size
,
4437 sw_idx
= NEXT_TX(sw_idx
);
4442 if (unlikely(tx_bug
)) {
4448 tnapi
->tx_cons
= sw_idx
;
4450 /* Need to make the tx_cons update visible to tg3_start_xmit()
4451 * before checking for netif_queue_stopped(). Without the
4452 * memory barrier, there is a small possibility that tg3_start_xmit()
4453 * will miss it and cause the queue to be stopped forever.
4457 if (unlikely(netif_tx_queue_stopped(txq
) &&
4458 (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
)))) {
4459 __netif_tx_lock(txq
, smp_processor_id());
4460 if (netif_tx_queue_stopped(txq
) &&
4461 (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
)))
4462 netif_tx_wake_queue(txq
);
4463 __netif_tx_unlock(txq
);
4467 static void tg3_rx_skb_free(struct tg3
*tp
, struct ring_info
*ri
, u32 map_sz
)
4472 pci_unmap_single(tp
->pdev
, dma_unmap_addr(ri
, mapping
),
4473 map_sz
, PCI_DMA_FROMDEVICE
);
4474 dev_kfree_skb_any(ri
->skb
);
4478 /* Returns size of skb allocated or < 0 on error.
4480 * We only need to fill in the address because the other members
4481 * of the RX descriptor are invariant, see tg3_init_rings.
4483 * Note the purposeful assymetry of cpu vs. chip accesses. For
4484 * posting buffers we only dirty the first cache line of the RX
4485 * descriptor (containing the address). Whereas for the RX status
4486 * buffers the cpu only reads the last cacheline of the RX descriptor
4487 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4489 static int tg3_alloc_rx_skb(struct tg3
*tp
, struct tg3_rx_prodring_set
*tpr
,
4490 u32 opaque_key
, u32 dest_idx_unmasked
)
4492 struct tg3_rx_buffer_desc
*desc
;
4493 struct ring_info
*map
, *src_map
;
4494 struct sk_buff
*skb
;
4496 int skb_size
, dest_idx
;
4499 switch (opaque_key
) {
4500 case RXD_OPAQUE_RING_STD
:
4501 dest_idx
= dest_idx_unmasked
% TG3_RX_RING_SIZE
;
4502 desc
= &tpr
->rx_std
[dest_idx
];
4503 map
= &tpr
->rx_std_buffers
[dest_idx
];
4504 skb_size
= tp
->rx_pkt_map_sz
;
4507 case RXD_OPAQUE_RING_JUMBO
:
4508 dest_idx
= dest_idx_unmasked
% TG3_RX_JUMBO_RING_SIZE
;
4509 desc
= &tpr
->rx_jmb
[dest_idx
].std
;
4510 map
= &tpr
->rx_jmb_buffers
[dest_idx
];
4511 skb_size
= TG3_RX_JMB_MAP_SZ
;
4518 /* Do not overwrite any of the map or rp information
4519 * until we are sure we can commit to a new buffer.
4521 * Callers depend upon this behavior and assume that
4522 * we leave everything unchanged if we fail.
4524 skb
= netdev_alloc_skb(tp
->dev
, skb_size
+ tp
->rx_offset
);
4528 skb_reserve(skb
, tp
->rx_offset
);
4530 mapping
= pci_map_single(tp
->pdev
, skb
->data
, skb_size
,
4531 PCI_DMA_FROMDEVICE
);
4532 if (pci_dma_mapping_error(tp
->pdev
, mapping
)) {
4538 dma_unmap_addr_set(map
, mapping
, mapping
);
4540 desc
->addr_hi
= ((u64
)mapping
>> 32);
4541 desc
->addr_lo
= ((u64
)mapping
& 0xffffffff);
4546 /* We only need to move over in the address because the other
4547 * members of the RX descriptor are invariant. See notes above
4548 * tg3_alloc_rx_skb for full details.
4550 static void tg3_recycle_rx(struct tg3_napi
*tnapi
,
4551 struct tg3_rx_prodring_set
*dpr
,
4552 u32 opaque_key
, int src_idx
,
4553 u32 dest_idx_unmasked
)
4555 struct tg3
*tp
= tnapi
->tp
;
4556 struct tg3_rx_buffer_desc
*src_desc
, *dest_desc
;
4557 struct ring_info
*src_map
, *dest_map
;
4558 struct tg3_rx_prodring_set
*spr
= &tp
->prodring
[0];
4561 switch (opaque_key
) {
4562 case RXD_OPAQUE_RING_STD
:
4563 dest_idx
= dest_idx_unmasked
% TG3_RX_RING_SIZE
;
4564 dest_desc
= &dpr
->rx_std
[dest_idx
];
4565 dest_map
= &dpr
->rx_std_buffers
[dest_idx
];
4566 src_desc
= &spr
->rx_std
[src_idx
];
4567 src_map
= &spr
->rx_std_buffers
[src_idx
];
4570 case RXD_OPAQUE_RING_JUMBO
:
4571 dest_idx
= dest_idx_unmasked
% TG3_RX_JUMBO_RING_SIZE
;
4572 dest_desc
= &dpr
->rx_jmb
[dest_idx
].std
;
4573 dest_map
= &dpr
->rx_jmb_buffers
[dest_idx
];
4574 src_desc
= &spr
->rx_jmb
[src_idx
].std
;
4575 src_map
= &spr
->rx_jmb_buffers
[src_idx
];
4582 dest_map
->skb
= src_map
->skb
;
4583 dma_unmap_addr_set(dest_map
, mapping
,
4584 dma_unmap_addr(src_map
, mapping
));
4585 dest_desc
->addr_hi
= src_desc
->addr_hi
;
4586 dest_desc
->addr_lo
= src_desc
->addr_lo
;
4588 /* Ensure that the update to the skb happens after the physical
4589 * addresses have been transferred to the new BD location.
4593 src_map
->skb
= NULL
;
4596 /* The RX ring scheme is composed of multiple rings which post fresh
4597 * buffers to the chip, and one special ring the chip uses to report
4598 * status back to the host.
4600 * The special ring reports the status of received packets to the
4601 * host. The chip does not write into the original descriptor the
4602 * RX buffer was obtained from. The chip simply takes the original
4603 * descriptor as provided by the host, updates the status and length
4604 * field, then writes this into the next status ring entry.
4606 * Each ring the host uses to post buffers to the chip is described
4607 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4608 * it is first placed into the on-chip ram. When the packet's length
4609 * is known, it walks down the TG3_BDINFO entries to select the ring.
4610 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4611 * which is within the range of the new packet's length is chosen.
4613 * The "separate ring for rx status" scheme may sound queer, but it makes
4614 * sense from a cache coherency perspective. If only the host writes
4615 * to the buffer post rings, and only the chip writes to the rx status
4616 * rings, then cache lines never move beyond shared-modified state.
4617 * If both the host and chip were to write into the same ring, cache line
4618 * eviction could occur since both entities want it in an exclusive state.
4620 static int tg3_rx(struct tg3_napi
*tnapi
, int budget
)
4622 struct tg3
*tp
= tnapi
->tp
;
4623 u32 work_mask
, rx_std_posted
= 0;
4624 u32 std_prod_idx
, jmb_prod_idx
;
4625 u32 sw_idx
= tnapi
->rx_rcb_ptr
;
4628 struct tg3_rx_prodring_set
*tpr
= tnapi
->prodring
;
4630 hw_idx
= *(tnapi
->rx_rcb_prod_idx
);
4632 * We need to order the read of hw_idx and the read of
4633 * the opaque cookie.
4638 std_prod_idx
= tpr
->rx_std_prod_idx
;
4639 jmb_prod_idx
= tpr
->rx_jmb_prod_idx
;
4640 while (sw_idx
!= hw_idx
&& budget
> 0) {
4641 struct ring_info
*ri
;
4642 struct tg3_rx_buffer_desc
*desc
= &tnapi
->rx_rcb
[sw_idx
];
4644 struct sk_buff
*skb
;
4645 dma_addr_t dma_addr
;
4646 u32 opaque_key
, desc_idx
, *post_ptr
;
4647 bool hw_vlan __maybe_unused
= false;
4648 u16 vtag __maybe_unused
= 0;
4650 desc_idx
= desc
->opaque
& RXD_OPAQUE_INDEX_MASK
;
4651 opaque_key
= desc
->opaque
& RXD_OPAQUE_RING_MASK
;
4652 if (opaque_key
== RXD_OPAQUE_RING_STD
) {
4653 ri
= &tp
->prodring
[0].rx_std_buffers
[desc_idx
];
4654 dma_addr
= dma_unmap_addr(ri
, mapping
);
4656 post_ptr
= &std_prod_idx
;
4658 } else if (opaque_key
== RXD_OPAQUE_RING_JUMBO
) {
4659 ri
= &tp
->prodring
[0].rx_jmb_buffers
[desc_idx
];
4660 dma_addr
= dma_unmap_addr(ri
, mapping
);
4662 post_ptr
= &jmb_prod_idx
;
4664 goto next_pkt_nopost
;
4666 work_mask
|= opaque_key
;
4668 if ((desc
->err_vlan
& RXD_ERR_MASK
) != 0 &&
4669 (desc
->err_vlan
!= RXD_ERR_ODD_NIBBLE_RCVD_MII
)) {
4671 tg3_recycle_rx(tnapi
, tpr
, opaque_key
,
4672 desc_idx
, *post_ptr
);
4674 /* Other statistics kept track of by card. */
4675 tp
->net_stats
.rx_dropped
++;
4679 len
= ((desc
->idx_len
& RXD_LEN_MASK
) >> RXD_LEN_SHIFT
) -
4682 if (len
> TG3_RX_COPY_THRESH(tp
)) {
4685 skb_size
= tg3_alloc_rx_skb(tp
, tpr
, opaque_key
,
4690 pci_unmap_single(tp
->pdev
, dma_addr
, skb_size
,
4691 PCI_DMA_FROMDEVICE
);
4693 /* Ensure that the update to the skb happens
4694 * after the usage of the old DMA mapping.
4702 struct sk_buff
*copy_skb
;
4704 tg3_recycle_rx(tnapi
, tpr
, opaque_key
,
4705 desc_idx
, *post_ptr
);
4707 copy_skb
= netdev_alloc_skb(tp
->dev
, len
+ VLAN_HLEN
+
4709 if (copy_skb
== NULL
)
4710 goto drop_it_no_recycle
;
4712 skb_reserve(copy_skb
, TG3_RAW_IP_ALIGN
+ VLAN_HLEN
);
4713 skb_put(copy_skb
, len
);
4714 pci_dma_sync_single_for_cpu(tp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
4715 skb_copy_from_linear_data(skb
, copy_skb
->data
, len
);
4716 pci_dma_sync_single_for_device(tp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
4718 /* We'll reuse the original ring buffer. */
4722 if ((tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) &&
4723 (desc
->type_flags
& RXD_FLAG_TCPUDP_CSUM
) &&
4724 (((desc
->ip_tcp_csum
& RXD_TCPCSUM_MASK
)
4725 >> RXD_TCPCSUM_SHIFT
) == 0xffff))
4726 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
4728 skb
->ip_summed
= CHECKSUM_NONE
;
4730 skb
->protocol
= eth_type_trans(skb
, tp
->dev
);
4732 if (len
> (tp
->dev
->mtu
+ ETH_HLEN
) &&
4733 skb
->protocol
!= htons(ETH_P_8021Q
)) {
4738 if (desc
->type_flags
& RXD_FLAG_VLAN
&&
4739 !(tp
->rx_mode
& RX_MODE_KEEP_VLAN_TAG
)) {
4740 vtag
= desc
->err_vlan
& RXD_VLAN_MASK
;
4741 #if TG3_VLAN_TAG_USED
4747 struct vlan_ethhdr
*ve
= (struct vlan_ethhdr
*)
4748 __skb_push(skb
, VLAN_HLEN
);
4750 memmove(ve
, skb
->data
+ VLAN_HLEN
,
4752 ve
->h_vlan_proto
= htons(ETH_P_8021Q
);
4753 ve
->h_vlan_TCI
= htons(vtag
);
4757 #if TG3_VLAN_TAG_USED
4759 vlan_gro_receive(&tnapi
->napi
, tp
->vlgrp
, vtag
, skb
);
4762 napi_gro_receive(&tnapi
->napi
, skb
);
4770 if (unlikely(rx_std_posted
>= tp
->rx_std_max_post
)) {
4771 tpr
->rx_std_prod_idx
= std_prod_idx
% TG3_RX_RING_SIZE
;
4772 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
,
4773 tpr
->rx_std_prod_idx
);
4774 work_mask
&= ~RXD_OPAQUE_RING_STD
;
4779 sw_idx
&= (TG3_RX_RCB_RING_SIZE(tp
) - 1);
4781 /* Refresh hw_idx to see if there is new work */
4782 if (sw_idx
== hw_idx
) {
4783 hw_idx
= *(tnapi
->rx_rcb_prod_idx
);
4788 /* ACK the status ring. */
4789 tnapi
->rx_rcb_ptr
= sw_idx
;
4790 tw32_rx_mbox(tnapi
->consmbox
, sw_idx
);
4792 /* Refill RX ring(s). */
4793 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
)) {
4794 if (work_mask
& RXD_OPAQUE_RING_STD
) {
4795 tpr
->rx_std_prod_idx
= std_prod_idx
% TG3_RX_RING_SIZE
;
4796 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
,
4797 tpr
->rx_std_prod_idx
);
4799 if (work_mask
& RXD_OPAQUE_RING_JUMBO
) {
4800 tpr
->rx_jmb_prod_idx
= jmb_prod_idx
%
4801 TG3_RX_JUMBO_RING_SIZE
;
4802 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG
,
4803 tpr
->rx_jmb_prod_idx
);
4806 } else if (work_mask
) {
4807 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4808 * updated before the producer indices can be updated.
4812 tpr
->rx_std_prod_idx
= std_prod_idx
% TG3_RX_RING_SIZE
;
4813 tpr
->rx_jmb_prod_idx
= jmb_prod_idx
% TG3_RX_JUMBO_RING_SIZE
;
4815 if (tnapi
!= &tp
->napi
[1])
4816 napi_schedule(&tp
->napi
[1].napi
);
4822 static void tg3_poll_link(struct tg3
*tp
)
4824 /* handle link change and other phy events */
4825 if (!(tp
->tg3_flags
&
4826 (TG3_FLAG_USE_LINKCHG_REG
|
4827 TG3_FLAG_POLL_SERDES
))) {
4828 struct tg3_hw_status
*sblk
= tp
->napi
[0].hw_status
;
4830 if (sblk
->status
& SD_STATUS_LINK_CHG
) {
4831 sblk
->status
= SD_STATUS_UPDATED
|
4832 (sblk
->status
& ~SD_STATUS_LINK_CHG
);
4833 spin_lock(&tp
->lock
);
4834 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
4836 (MAC_STATUS_SYNC_CHANGED
|
4837 MAC_STATUS_CFG_CHANGED
|
4838 MAC_STATUS_MI_COMPLETION
|
4839 MAC_STATUS_LNKSTATE_CHANGED
));
4842 tg3_setup_phy(tp
, 0);
4843 spin_unlock(&tp
->lock
);
4848 static int tg3_rx_prodring_xfer(struct tg3
*tp
,
4849 struct tg3_rx_prodring_set
*dpr
,
4850 struct tg3_rx_prodring_set
*spr
)
4852 u32 si
, di
, cpycnt
, src_prod_idx
;
4856 src_prod_idx
= spr
->rx_std_prod_idx
;
4858 /* Make sure updates to the rx_std_buffers[] entries and the
4859 * standard producer index are seen in the correct order.
4863 if (spr
->rx_std_cons_idx
== src_prod_idx
)
4866 if (spr
->rx_std_cons_idx
< src_prod_idx
)
4867 cpycnt
= src_prod_idx
- spr
->rx_std_cons_idx
;
4869 cpycnt
= TG3_RX_RING_SIZE
- spr
->rx_std_cons_idx
;
4871 cpycnt
= min(cpycnt
, TG3_RX_RING_SIZE
- dpr
->rx_std_prod_idx
);
4873 si
= spr
->rx_std_cons_idx
;
4874 di
= dpr
->rx_std_prod_idx
;
4876 for (i
= di
; i
< di
+ cpycnt
; i
++) {
4877 if (dpr
->rx_std_buffers
[i
].skb
) {
4887 /* Ensure that updates to the rx_std_buffers ring and the
4888 * shadowed hardware producer ring from tg3_recycle_skb() are
4889 * ordered correctly WRT the skb check above.
4893 memcpy(&dpr
->rx_std_buffers
[di
],
4894 &spr
->rx_std_buffers
[si
],
4895 cpycnt
* sizeof(struct ring_info
));
4897 for (i
= 0; i
< cpycnt
; i
++, di
++, si
++) {
4898 struct tg3_rx_buffer_desc
*sbd
, *dbd
;
4899 sbd
= &spr
->rx_std
[si
];
4900 dbd
= &dpr
->rx_std
[di
];
4901 dbd
->addr_hi
= sbd
->addr_hi
;
4902 dbd
->addr_lo
= sbd
->addr_lo
;
4905 spr
->rx_std_cons_idx
= (spr
->rx_std_cons_idx
+ cpycnt
) %
4907 dpr
->rx_std_prod_idx
= (dpr
->rx_std_prod_idx
+ cpycnt
) %
4912 src_prod_idx
= spr
->rx_jmb_prod_idx
;
4914 /* Make sure updates to the rx_jmb_buffers[] entries and
4915 * the jumbo producer index are seen in the correct order.
4919 if (spr
->rx_jmb_cons_idx
== src_prod_idx
)
4922 if (spr
->rx_jmb_cons_idx
< src_prod_idx
)
4923 cpycnt
= src_prod_idx
- spr
->rx_jmb_cons_idx
;
4925 cpycnt
= TG3_RX_JUMBO_RING_SIZE
- spr
->rx_jmb_cons_idx
;
4927 cpycnt
= min(cpycnt
,
4928 TG3_RX_JUMBO_RING_SIZE
- dpr
->rx_jmb_prod_idx
);
4930 si
= spr
->rx_jmb_cons_idx
;
4931 di
= dpr
->rx_jmb_prod_idx
;
4933 for (i
= di
; i
< di
+ cpycnt
; i
++) {
4934 if (dpr
->rx_jmb_buffers
[i
].skb
) {
4944 /* Ensure that updates to the rx_jmb_buffers ring and the
4945 * shadowed hardware producer ring from tg3_recycle_skb() are
4946 * ordered correctly WRT the skb check above.
4950 memcpy(&dpr
->rx_jmb_buffers
[di
],
4951 &spr
->rx_jmb_buffers
[si
],
4952 cpycnt
* sizeof(struct ring_info
));
4954 for (i
= 0; i
< cpycnt
; i
++, di
++, si
++) {
4955 struct tg3_rx_buffer_desc
*sbd
, *dbd
;
4956 sbd
= &spr
->rx_jmb
[si
].std
;
4957 dbd
= &dpr
->rx_jmb
[di
].std
;
4958 dbd
->addr_hi
= sbd
->addr_hi
;
4959 dbd
->addr_lo
= sbd
->addr_lo
;
4962 spr
->rx_jmb_cons_idx
= (spr
->rx_jmb_cons_idx
+ cpycnt
) %
4963 TG3_RX_JUMBO_RING_SIZE
;
4964 dpr
->rx_jmb_prod_idx
= (dpr
->rx_jmb_prod_idx
+ cpycnt
) %
4965 TG3_RX_JUMBO_RING_SIZE
;
4971 static int tg3_poll_work(struct tg3_napi
*tnapi
, int work_done
, int budget
)
4973 struct tg3
*tp
= tnapi
->tp
;
4975 /* run TX completion thread */
4976 if (tnapi
->hw_status
->idx
[0].tx_consumer
!= tnapi
->tx_cons
) {
4978 if (unlikely(tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
))
4982 /* run RX thread, within the bounds set by NAPI.
4983 * All RX "locking" is done by ensuring outside
4984 * code synchronizes with tg3->napi.poll()
4986 if (*(tnapi
->rx_rcb_prod_idx
) != tnapi
->rx_rcb_ptr
)
4987 work_done
+= tg3_rx(tnapi
, budget
- work_done
);
4989 if ((tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
) && tnapi
== &tp
->napi
[1]) {
4990 struct tg3_rx_prodring_set
*dpr
= &tp
->prodring
[0];
4992 u32 std_prod_idx
= dpr
->rx_std_prod_idx
;
4993 u32 jmb_prod_idx
= dpr
->rx_jmb_prod_idx
;
4995 for (i
= 1; i
< tp
->irq_cnt
; i
++)
4996 err
|= tg3_rx_prodring_xfer(tp
, dpr
,
4997 tp
->napi
[i
].prodring
);
5001 if (std_prod_idx
!= dpr
->rx_std_prod_idx
)
5002 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
,
5003 dpr
->rx_std_prod_idx
);
5005 if (jmb_prod_idx
!= dpr
->rx_jmb_prod_idx
)
5006 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG
,
5007 dpr
->rx_jmb_prod_idx
);
5012 tw32_f(HOSTCC_MODE
, tp
->coal_now
);
5018 static int tg3_poll_msix(struct napi_struct
*napi
, int budget
)
5020 struct tg3_napi
*tnapi
= container_of(napi
, struct tg3_napi
, napi
);
5021 struct tg3
*tp
= tnapi
->tp
;
5023 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
5026 work_done
= tg3_poll_work(tnapi
, work_done
, budget
);
5028 if (unlikely(tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
))
5031 if (unlikely(work_done
>= budget
))
5034 /* tp->last_tag is used in tg3_int_reenable() below
5035 * to tell the hw how much work has been processed,
5036 * so we must read it before checking for more work.
5038 tnapi
->last_tag
= sblk
->status_tag
;
5039 tnapi
->last_irq_tag
= tnapi
->last_tag
;
5042 /* check for RX/TX work to do */
5043 if (likely(sblk
->idx
[0].tx_consumer
== tnapi
->tx_cons
&&
5044 *(tnapi
->rx_rcb_prod_idx
) == tnapi
->rx_rcb_ptr
)) {
5045 napi_complete(napi
);
5046 /* Reenable interrupts. */
5047 tw32_mailbox(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
5056 /* work_done is guaranteed to be less than budget. */
5057 napi_complete(napi
);
5058 schedule_work(&tp
->reset_task
);
5062 static int tg3_poll(struct napi_struct
*napi
, int budget
)
5064 struct tg3_napi
*tnapi
= container_of(napi
, struct tg3_napi
, napi
);
5065 struct tg3
*tp
= tnapi
->tp
;
5067 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
5072 work_done
= tg3_poll_work(tnapi
, work_done
, budget
);
5074 if (unlikely(tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
))
5077 if (unlikely(work_done
>= budget
))
5080 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) {
5081 /* tp->last_tag is used in tg3_int_reenable() below
5082 * to tell the hw how much work has been processed,
5083 * so we must read it before checking for more work.
5085 tnapi
->last_tag
= sblk
->status_tag
;
5086 tnapi
->last_irq_tag
= tnapi
->last_tag
;
5089 sblk
->status
&= ~SD_STATUS_UPDATED
;
5091 if (likely(!tg3_has_work(tnapi
))) {
5092 napi_complete(napi
);
5093 tg3_int_reenable(tnapi
);
5101 /* work_done is guaranteed to be less than budget. */
5102 napi_complete(napi
);
5103 schedule_work(&tp
->reset_task
);
5107 static void tg3_irq_quiesce(struct tg3
*tp
)
5111 BUG_ON(tp
->irq_sync
);
5116 for (i
= 0; i
< tp
->irq_cnt
; i
++)
5117 synchronize_irq(tp
->napi
[i
].irq_vec
);
5120 static inline int tg3_irq_sync(struct tg3
*tp
)
5122 return tp
->irq_sync
;
5125 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5126 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5127 * with as well. Most of the time, this is not necessary except when
5128 * shutting down the device.
5130 static inline void tg3_full_lock(struct tg3
*tp
, int irq_sync
)
5132 spin_lock_bh(&tp
->lock
);
5134 tg3_irq_quiesce(tp
);
5137 static inline void tg3_full_unlock(struct tg3
*tp
)
5139 spin_unlock_bh(&tp
->lock
);
5142 /* One-shot MSI handler - Chip automatically disables interrupt
5143 * after sending MSI so driver doesn't have to do it.
5145 static irqreturn_t
tg3_msi_1shot(int irq
, void *dev_id
)
5147 struct tg3_napi
*tnapi
= dev_id
;
5148 struct tg3
*tp
= tnapi
->tp
;
5150 prefetch(tnapi
->hw_status
);
5152 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
5154 if (likely(!tg3_irq_sync(tp
)))
5155 napi_schedule(&tnapi
->napi
);
5160 /* MSI ISR - No need to check for interrupt sharing and no need to
5161 * flush status block and interrupt mailbox. PCI ordering rules
5162 * guarantee that MSI will arrive after the status block.
5164 static irqreturn_t
tg3_msi(int irq
, void *dev_id
)
5166 struct tg3_napi
*tnapi
= dev_id
;
5167 struct tg3
*tp
= tnapi
->tp
;
5169 prefetch(tnapi
->hw_status
);
5171 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
5173 * Writing any value to intr-mbox-0 clears PCI INTA# and
5174 * chip-internal interrupt pending events.
5175 * Writing non-zero to intr-mbox-0 additional tells the
5176 * NIC to stop sending us irqs, engaging "in-intr-handler"
5179 tw32_mailbox(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
5180 if (likely(!tg3_irq_sync(tp
)))
5181 napi_schedule(&tnapi
->napi
);
5183 return IRQ_RETVAL(1);
5186 static irqreturn_t
tg3_interrupt(int irq
, void *dev_id
)
5188 struct tg3_napi
*tnapi
= dev_id
;
5189 struct tg3
*tp
= tnapi
->tp
;
5190 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
5191 unsigned int handled
= 1;
5193 /* In INTx mode, it is possible for the interrupt to arrive at
5194 * the CPU before the status block posted prior to the interrupt.
5195 * Reading the PCI State register will confirm whether the
5196 * interrupt is ours and will flush the status block.
5198 if (unlikely(!(sblk
->status
& SD_STATUS_UPDATED
))) {
5199 if ((tp
->tg3_flags
& TG3_FLAG_CHIP_RESETTING
) ||
5200 (tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
5207 * Writing any value to intr-mbox-0 clears PCI INTA# and
5208 * chip-internal interrupt pending events.
5209 * Writing non-zero to intr-mbox-0 additional tells the
5210 * NIC to stop sending us irqs, engaging "in-intr-handler"
5213 * Flush the mailbox to de-assert the IRQ immediately to prevent
5214 * spurious interrupts. The flush impacts performance but
5215 * excessive spurious interrupts can be worse in some cases.
5217 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
5218 if (tg3_irq_sync(tp
))
5220 sblk
->status
&= ~SD_STATUS_UPDATED
;
5221 if (likely(tg3_has_work(tnapi
))) {
5222 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
5223 napi_schedule(&tnapi
->napi
);
5225 /* No work, shared interrupt perhaps? re-enable
5226 * interrupts, and flush that PCI write
5228 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
5232 return IRQ_RETVAL(handled
);
5235 static irqreturn_t
tg3_interrupt_tagged(int irq
, void *dev_id
)
5237 struct tg3_napi
*tnapi
= dev_id
;
5238 struct tg3
*tp
= tnapi
->tp
;
5239 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
5240 unsigned int handled
= 1;
5242 /* In INTx mode, it is possible for the interrupt to arrive at
5243 * the CPU before the status block posted prior to the interrupt.
5244 * Reading the PCI State register will confirm whether the
5245 * interrupt is ours and will flush the status block.
5247 if (unlikely(sblk
->status_tag
== tnapi
->last_irq_tag
)) {
5248 if ((tp
->tg3_flags
& TG3_FLAG_CHIP_RESETTING
) ||
5249 (tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
5256 * writing any value to intr-mbox-0 clears PCI INTA# and
5257 * chip-internal interrupt pending events.
5258 * writing non-zero to intr-mbox-0 additional tells the
5259 * NIC to stop sending us irqs, engaging "in-intr-handler"
5262 * Flush the mailbox to de-assert the IRQ immediately to prevent
5263 * spurious interrupts. The flush impacts performance but
5264 * excessive spurious interrupts can be worse in some cases.
5266 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
5269 * In a shared interrupt configuration, sometimes other devices'
5270 * interrupts will scream. We record the current status tag here
5271 * so that the above check can report that the screaming interrupts
5272 * are unhandled. Eventually they will be silenced.
5274 tnapi
->last_irq_tag
= sblk
->status_tag
;
5276 if (tg3_irq_sync(tp
))
5279 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
5281 napi_schedule(&tnapi
->napi
);
5284 return IRQ_RETVAL(handled
);
5287 /* ISR for interrupt test */
5288 static irqreturn_t
tg3_test_isr(int irq
, void *dev_id
)
5290 struct tg3_napi
*tnapi
= dev_id
;
5291 struct tg3
*tp
= tnapi
->tp
;
5292 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
5294 if ((sblk
->status
& SD_STATUS_UPDATED
) ||
5295 !(tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
5296 tg3_disable_ints(tp
);
5297 return IRQ_RETVAL(1);
5299 return IRQ_RETVAL(0);
5302 static int tg3_init_hw(struct tg3
*, int);
5303 static int tg3_halt(struct tg3
*, int, int);
5305 /* Restart hardware after configuration changes, self-test, etc.
5306 * Invoked with tp->lock held.
5308 static int tg3_restart_hw(struct tg3
*tp
, int reset_phy
)
5309 __releases(tp
->lock
)
5310 __acquires(tp
->lock
)
5314 err
= tg3_init_hw(tp
, reset_phy
);
5317 "Failed to re-initialize device, aborting\n");
5318 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
5319 tg3_full_unlock(tp
);
5320 del_timer_sync(&tp
->timer
);
5322 tg3_napi_enable(tp
);
5324 tg3_full_lock(tp
, 0);
5329 #ifdef CONFIG_NET_POLL_CONTROLLER
5330 static void tg3_poll_controller(struct net_device
*dev
)
5333 struct tg3
*tp
= netdev_priv(dev
);
5335 for (i
= 0; i
< tp
->irq_cnt
; i
++)
5336 tg3_interrupt(tp
->napi
[i
].irq_vec
, &tp
->napi
[i
]);
5340 static void tg3_reset_task(struct work_struct
*work
)
5342 struct tg3
*tp
= container_of(work
, struct tg3
, reset_task
);
5344 unsigned int restart_timer
;
5346 tg3_full_lock(tp
, 0);
5348 if (!netif_running(tp
->dev
)) {
5349 tg3_full_unlock(tp
);
5353 tg3_full_unlock(tp
);
5359 tg3_full_lock(tp
, 1);
5361 restart_timer
= tp
->tg3_flags2
& TG3_FLG2_RESTART_TIMER
;
5362 tp
->tg3_flags2
&= ~TG3_FLG2_RESTART_TIMER
;
5364 if (tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
) {
5365 tp
->write32_tx_mbox
= tg3_write32_tx_mbox
;
5366 tp
->write32_rx_mbox
= tg3_write_flush_reg32
;
5367 tp
->tg3_flags
|= TG3_FLAG_MBOX_WRITE_REORDER
;
5368 tp
->tg3_flags
&= ~TG3_FLAG_TX_RECOVERY_PENDING
;
5371 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 0);
5372 err
= tg3_init_hw(tp
, 1);
5376 tg3_netif_start(tp
);
5379 mod_timer(&tp
->timer
, jiffies
+ 1);
5382 tg3_full_unlock(tp
);
5388 static void tg3_dump_short_state(struct tg3
*tp
)
5390 netdev_err(tp
->dev
, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5391 tr32(MAC_TX_STATUS
), tr32(MAC_RX_STATUS
));
5392 netdev_err(tp
->dev
, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5393 tr32(RDMAC_STATUS
), tr32(WDMAC_STATUS
));
5396 static void tg3_tx_timeout(struct net_device
*dev
)
5398 struct tg3
*tp
= netdev_priv(dev
);
5400 if (netif_msg_tx_err(tp
)) {
5401 netdev_err(dev
, "transmit timed out, resetting\n");
5402 tg3_dump_short_state(tp
);
5405 schedule_work(&tp
->reset_task
);
5408 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5409 static inline int tg3_4g_overflow_test(dma_addr_t mapping
, int len
)
5411 u32 base
= (u32
) mapping
& 0xffffffff;
5413 return ((base
> 0xffffdcc0) &&
5414 (base
+ len
+ 8 < base
));
5417 /* Test for DMA addresses > 40-bit */
5418 static inline int tg3_40bit_overflow_test(struct tg3
*tp
, dma_addr_t mapping
,
5421 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5422 if (tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
)
5423 return (((u64
) mapping
+ len
) > DMA_BIT_MASK(40));
5430 static void tg3_set_txd(struct tg3_napi
*, int, dma_addr_t
, int, u32
, u32
);
5432 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5433 static int tigon3_dma_hwbug_workaround(struct tg3_napi
*tnapi
,
5434 struct sk_buff
*skb
, u32 last_plus_one
,
5435 u32
*start
, u32 base_flags
, u32 mss
)
5437 struct tg3
*tp
= tnapi
->tp
;
5438 struct sk_buff
*new_skb
;
5439 dma_addr_t new_addr
= 0;
5443 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
)
5444 new_skb
= skb_copy(skb
, GFP_ATOMIC
);
5446 int more_headroom
= 4 - ((unsigned long)skb
->data
& 3);
5448 new_skb
= skb_copy_expand(skb
,
5449 skb_headroom(skb
) + more_headroom
,
5450 skb_tailroom(skb
), GFP_ATOMIC
);
5456 /* New SKB is guaranteed to be linear. */
5458 new_addr
= pci_map_single(tp
->pdev
, new_skb
->data
, new_skb
->len
,
5460 /* Make sure the mapping succeeded */
5461 if (pci_dma_mapping_error(tp
->pdev
, new_addr
)) {
5463 dev_kfree_skb(new_skb
);
5466 /* Make sure new skb does not cross any 4G boundaries.
5467 * Drop the packet if it does.
5469 } else if ((tp
->tg3_flags3
& TG3_FLG3_4G_DMA_BNDRY_BUG
) &&
5470 tg3_4g_overflow_test(new_addr
, new_skb
->len
)) {
5471 pci_unmap_single(tp
->pdev
, new_addr
, new_skb
->len
,
5474 dev_kfree_skb(new_skb
);
5477 tg3_set_txd(tnapi
, entry
, new_addr
, new_skb
->len
,
5478 base_flags
, 1 | (mss
<< 1));
5479 *start
= NEXT_TX(entry
);
5483 /* Now clean up the sw ring entries. */
5485 while (entry
!= last_plus_one
) {
5489 len
= skb_headlen(skb
);
5491 len
= skb_shinfo(skb
)->frags
[i
-1].size
;
5493 pci_unmap_single(tp
->pdev
,
5494 dma_unmap_addr(&tnapi
->tx_buffers
[entry
],
5496 len
, PCI_DMA_TODEVICE
);
5498 tnapi
->tx_buffers
[entry
].skb
= new_skb
;
5499 dma_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
,
5502 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5504 entry
= NEXT_TX(entry
);
5513 static void tg3_set_txd(struct tg3_napi
*tnapi
, int entry
,
5514 dma_addr_t mapping
, int len
, u32 flags
,
5517 struct tg3_tx_buffer_desc
*txd
= &tnapi
->tx_ring
[entry
];
5518 int is_end
= (mss_and_is_end
& 0x1);
5519 u32 mss
= (mss_and_is_end
>> 1);
5523 flags
|= TXD_FLAG_END
;
5524 if (flags
& TXD_FLAG_VLAN
) {
5525 vlan_tag
= flags
>> 16;
5528 vlan_tag
|= (mss
<< TXD_MSS_SHIFT
);
5530 txd
->addr_hi
= ((u64
) mapping
>> 32);
5531 txd
->addr_lo
= ((u64
) mapping
& 0xffffffff);
5532 txd
->len_flags
= (len
<< TXD_LEN_SHIFT
) | flags
;
5533 txd
->vlan_tag
= vlan_tag
<< TXD_VLAN_TAG_SHIFT
;
5536 /* hard_start_xmit for devices that don't have any bugs and
5537 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5539 static netdev_tx_t
tg3_start_xmit(struct sk_buff
*skb
,
5540 struct net_device
*dev
)
5542 struct tg3
*tp
= netdev_priv(dev
);
5543 u32 len
, entry
, base_flags
, mss
;
5545 struct tg3_napi
*tnapi
;
5546 struct netdev_queue
*txq
;
5547 unsigned int i
, last
;
5549 txq
= netdev_get_tx_queue(dev
, skb_get_queue_mapping(skb
));
5550 tnapi
= &tp
->napi
[skb_get_queue_mapping(skb
)];
5551 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
5554 /* We are running in BH disabled context with netif_tx_lock
5555 * and TX reclaim runs via tp->napi.poll inside of a software
5556 * interrupt. Furthermore, IRQ processing runs lockless so we have
5557 * no IRQ context deadlocks to worry about either. Rejoice!
5559 if (unlikely(tg3_tx_avail(tnapi
) <= (skb_shinfo(skb
)->nr_frags
+ 1))) {
5560 if (!netif_tx_queue_stopped(txq
)) {
5561 netif_tx_stop_queue(txq
);
5563 /* This is a hard error, log it. */
5565 "BUG! Tx Ring full when queue awake!\n");
5567 return NETDEV_TX_BUSY
;
5570 entry
= tnapi
->tx_prod
;
5573 if ((mss
= skb_shinfo(skb
)->gso_size
) != 0) {
5574 int tcp_opt_len
, ip_tcp_len
;
5577 if (skb_header_cloned(skb
) &&
5578 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
5583 if (skb_shinfo(skb
)->gso_type
& SKB_GSO_TCPV6
)
5584 hdrlen
= skb_headlen(skb
) - ETH_HLEN
;
5586 struct iphdr
*iph
= ip_hdr(skb
);
5588 tcp_opt_len
= tcp_optlen(skb
);
5589 ip_tcp_len
= ip_hdrlen(skb
) + sizeof(struct tcphdr
);
5592 iph
->tot_len
= htons(mss
+ ip_tcp_len
+ tcp_opt_len
);
5593 hdrlen
= ip_tcp_len
+ tcp_opt_len
;
5596 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
) {
5597 mss
|= (hdrlen
& 0xc) << 12;
5599 base_flags
|= 0x00000010;
5600 base_flags
|= (hdrlen
& 0x3e0) << 5;
5604 base_flags
|= (TXD_FLAG_CPU_PRE_DMA
|
5605 TXD_FLAG_CPU_POST_DMA
);
5607 tcp_hdr(skb
)->check
= 0;
5609 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
5610 base_flags
|= TXD_FLAG_TCPUDP_CSUM
;
5613 #if TG3_VLAN_TAG_USED
5614 if (tp
->vlgrp
!= NULL
&& vlan_tx_tag_present(skb
))
5615 base_flags
|= (TXD_FLAG_VLAN
|
5616 (vlan_tx_tag_get(skb
) << 16));
5619 len
= skb_headlen(skb
);
5621 /* Queue skb data, a.k.a. the main skb fragment. */
5622 mapping
= pci_map_single(tp
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
5623 if (pci_dma_mapping_error(tp
->pdev
, mapping
)) {
5628 tnapi
->tx_buffers
[entry
].skb
= skb
;
5629 dma_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
, mapping
);
5631 if ((tp
->tg3_flags3
& TG3_FLG3_USE_JUMBO_BDFLAG
) &&
5632 !mss
&& skb
->len
> ETH_DATA_LEN
)
5633 base_flags
|= TXD_FLAG_JMB_PKT
;
5635 tg3_set_txd(tnapi
, entry
, mapping
, len
, base_flags
,
5636 (skb_shinfo(skb
)->nr_frags
== 0) | (mss
<< 1));
5638 entry
= NEXT_TX(entry
);
5640 /* Now loop through additional data fragments, and queue them. */
5641 if (skb_shinfo(skb
)->nr_frags
> 0) {
5642 last
= skb_shinfo(skb
)->nr_frags
- 1;
5643 for (i
= 0; i
<= last
; i
++) {
5644 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
5647 mapping
= pci_map_page(tp
->pdev
,
5650 len
, PCI_DMA_TODEVICE
);
5651 if (pci_dma_mapping_error(tp
->pdev
, mapping
))
5654 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5655 dma_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
,
5658 tg3_set_txd(tnapi
, entry
, mapping
, len
,
5659 base_flags
, (i
== last
) | (mss
<< 1));
5661 entry
= NEXT_TX(entry
);
5665 /* Packets are ready, update Tx producer idx local and on card. */
5666 tw32_tx_mbox(tnapi
->prodmbox
, entry
);
5668 tnapi
->tx_prod
= entry
;
5669 if (unlikely(tg3_tx_avail(tnapi
) <= (MAX_SKB_FRAGS
+ 1))) {
5670 netif_tx_stop_queue(txq
);
5671 if (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
))
5672 netif_tx_wake_queue(txq
);
5678 return NETDEV_TX_OK
;
5682 entry
= tnapi
->tx_prod
;
5683 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5684 pci_unmap_single(tp
->pdev
,
5685 dma_unmap_addr(&tnapi
->tx_buffers
[entry
], mapping
),
5688 for (i
= 0; i
<= last
; i
++) {
5689 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
5690 entry
= NEXT_TX(entry
);
5692 pci_unmap_page(tp
->pdev
,
5693 dma_unmap_addr(&tnapi
->tx_buffers
[entry
],
5695 frag
->size
, PCI_DMA_TODEVICE
);
5699 return NETDEV_TX_OK
;
5702 static netdev_tx_t
tg3_start_xmit_dma_bug(struct sk_buff
*,
5703 struct net_device
*);
5705 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5706 * TSO header is greater than 80 bytes.
5708 static int tg3_tso_bug(struct tg3
*tp
, struct sk_buff
*skb
)
5710 struct sk_buff
*segs
, *nskb
;
5711 u32 frag_cnt_est
= skb_shinfo(skb
)->gso_segs
* 3;
5713 /* Estimate the number of fragments in the worst case */
5714 if (unlikely(tg3_tx_avail(&tp
->napi
[0]) <= frag_cnt_est
)) {
5715 netif_stop_queue(tp
->dev
);
5716 if (tg3_tx_avail(&tp
->napi
[0]) <= frag_cnt_est
)
5717 return NETDEV_TX_BUSY
;
5719 netif_wake_queue(tp
->dev
);
5722 segs
= skb_gso_segment(skb
, tp
->dev
->features
& ~NETIF_F_TSO
);
5724 goto tg3_tso_bug_end
;
5730 tg3_start_xmit_dma_bug(nskb
, tp
->dev
);
5736 return NETDEV_TX_OK
;
5739 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5740 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5742 static netdev_tx_t
tg3_start_xmit_dma_bug(struct sk_buff
*skb
,
5743 struct net_device
*dev
)
5745 struct tg3
*tp
= netdev_priv(dev
);
5746 u32 len
, entry
, base_flags
, mss
;
5747 int would_hit_hwbug
;
5749 struct tg3_napi
*tnapi
;
5750 struct netdev_queue
*txq
;
5751 unsigned int i
, last
;
5753 txq
= netdev_get_tx_queue(dev
, skb_get_queue_mapping(skb
));
5754 tnapi
= &tp
->napi
[skb_get_queue_mapping(skb
)];
5755 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
5758 /* We are running in BH disabled context with netif_tx_lock
5759 * and TX reclaim runs via tp->napi.poll inside of a software
5760 * interrupt. Furthermore, IRQ processing runs lockless so we have
5761 * no IRQ context deadlocks to worry about either. Rejoice!
5763 if (unlikely(tg3_tx_avail(tnapi
) <= (skb_shinfo(skb
)->nr_frags
+ 1))) {
5764 if (!netif_tx_queue_stopped(txq
)) {
5765 netif_tx_stop_queue(txq
);
5767 /* This is a hard error, log it. */
5769 "BUG! Tx Ring full when queue awake!\n");
5771 return NETDEV_TX_BUSY
;
5774 entry
= tnapi
->tx_prod
;
5776 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
5777 base_flags
|= TXD_FLAG_TCPUDP_CSUM
;
5779 if ((mss
= skb_shinfo(skb
)->gso_size
) != 0) {
5781 u32 tcp_opt_len
, ip_tcp_len
, hdr_len
;
5783 if (skb_header_cloned(skb
) &&
5784 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
5789 tcp_opt_len
= tcp_optlen(skb
);
5790 ip_tcp_len
= ip_hdrlen(skb
) + sizeof(struct tcphdr
);
5792 hdr_len
= ip_tcp_len
+ tcp_opt_len
;
5793 if (unlikely((ETH_HLEN
+ hdr_len
) > 80) &&
5794 (tp
->tg3_flags2
& TG3_FLG2_TSO_BUG
))
5795 return tg3_tso_bug(tp
, skb
);
5797 base_flags
|= (TXD_FLAG_CPU_PRE_DMA
|
5798 TXD_FLAG_CPU_POST_DMA
);
5802 iph
->tot_len
= htons(mss
+ hdr_len
);
5803 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) {
5804 tcp_hdr(skb
)->check
= 0;
5805 base_flags
&= ~TXD_FLAG_TCPUDP_CSUM
;
5807 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
5812 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
) {
5813 mss
|= (hdr_len
& 0xc) << 12;
5815 base_flags
|= 0x00000010;
5816 base_flags
|= (hdr_len
& 0x3e0) << 5;
5817 } else if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_2
)
5818 mss
|= hdr_len
<< 9;
5819 else if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_1
) ||
5820 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
5821 if (tcp_opt_len
|| iph
->ihl
> 5) {
5824 tsflags
= (iph
->ihl
- 5) + (tcp_opt_len
>> 2);
5825 mss
|= (tsflags
<< 11);
5828 if (tcp_opt_len
|| iph
->ihl
> 5) {
5831 tsflags
= (iph
->ihl
- 5) + (tcp_opt_len
>> 2);
5832 base_flags
|= tsflags
<< 12;
5836 #if TG3_VLAN_TAG_USED
5837 if (tp
->vlgrp
!= NULL
&& vlan_tx_tag_present(skb
))
5838 base_flags
|= (TXD_FLAG_VLAN
|
5839 (vlan_tx_tag_get(skb
) << 16));
5842 if ((tp
->tg3_flags3
& TG3_FLG3_USE_JUMBO_BDFLAG
) &&
5843 !mss
&& skb
->len
> ETH_DATA_LEN
)
5844 base_flags
|= TXD_FLAG_JMB_PKT
;
5846 len
= skb_headlen(skb
);
5848 mapping
= pci_map_single(tp
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
5849 if (pci_dma_mapping_error(tp
->pdev
, mapping
)) {
5854 tnapi
->tx_buffers
[entry
].skb
= skb
;
5855 dma_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
, mapping
);
5857 would_hit_hwbug
= 0;
5859 if ((tp
->tg3_flags3
& TG3_FLG3_SHORT_DMA_BUG
) && len
<= 8)
5860 would_hit_hwbug
= 1;
5862 if ((tp
->tg3_flags3
& TG3_FLG3_4G_DMA_BNDRY_BUG
) &&
5863 tg3_4g_overflow_test(mapping
, len
))
5864 would_hit_hwbug
= 1;
5866 if ((tp
->tg3_flags3
& TG3_FLG3_40BIT_DMA_LIMIT_BUG
) &&
5867 tg3_40bit_overflow_test(tp
, mapping
, len
))
5868 would_hit_hwbug
= 1;
5870 if (tp
->tg3_flags3
& TG3_FLG3_5701_DMA_BUG
)
5871 would_hit_hwbug
= 1;
5873 tg3_set_txd(tnapi
, entry
, mapping
, len
, base_flags
,
5874 (skb_shinfo(skb
)->nr_frags
== 0) | (mss
<< 1));
5876 entry
= NEXT_TX(entry
);
5878 /* Now loop through additional data fragments, and queue them. */
5879 if (skb_shinfo(skb
)->nr_frags
> 0) {
5880 last
= skb_shinfo(skb
)->nr_frags
- 1;
5881 for (i
= 0; i
<= last
; i
++) {
5882 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
5885 mapping
= pci_map_page(tp
->pdev
,
5888 len
, PCI_DMA_TODEVICE
);
5890 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5891 dma_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
,
5893 if (pci_dma_mapping_error(tp
->pdev
, mapping
))
5896 if ((tp
->tg3_flags3
& TG3_FLG3_SHORT_DMA_BUG
) &&
5898 would_hit_hwbug
= 1;
5900 if ((tp
->tg3_flags3
& TG3_FLG3_4G_DMA_BNDRY_BUG
) &&
5901 tg3_4g_overflow_test(mapping
, len
))
5902 would_hit_hwbug
= 1;
5904 if ((tp
->tg3_flags3
& TG3_FLG3_40BIT_DMA_LIMIT_BUG
) &&
5905 tg3_40bit_overflow_test(tp
, mapping
, len
))
5906 would_hit_hwbug
= 1;
5908 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
5909 tg3_set_txd(tnapi
, entry
, mapping
, len
,
5910 base_flags
, (i
== last
)|(mss
<< 1));
5912 tg3_set_txd(tnapi
, entry
, mapping
, len
,
5913 base_flags
, (i
== last
));
5915 entry
= NEXT_TX(entry
);
5919 if (would_hit_hwbug
) {
5920 u32 last_plus_one
= entry
;
5923 start
= entry
- 1 - skb_shinfo(skb
)->nr_frags
;
5924 start
&= (TG3_TX_RING_SIZE
- 1);
5926 /* If the workaround fails due to memory/mapping
5927 * failure, silently drop this packet.
5929 if (tigon3_dma_hwbug_workaround(tnapi
, skb
, last_plus_one
,
5930 &start
, base_flags
, mss
))
5936 /* Packets are ready, update Tx producer idx local and on card. */
5937 tw32_tx_mbox(tnapi
->prodmbox
, entry
);
5939 tnapi
->tx_prod
= entry
;
5940 if (unlikely(tg3_tx_avail(tnapi
) <= (MAX_SKB_FRAGS
+ 1))) {
5941 netif_tx_stop_queue(txq
);
5942 if (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
))
5943 netif_tx_wake_queue(txq
);
5949 return NETDEV_TX_OK
;
5953 entry
= tnapi
->tx_prod
;
5954 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5955 pci_unmap_single(tp
->pdev
,
5956 dma_unmap_addr(&tnapi
->tx_buffers
[entry
], mapping
),
5959 for (i
= 0; i
<= last
; i
++) {
5960 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
5961 entry
= NEXT_TX(entry
);
5963 pci_unmap_page(tp
->pdev
,
5964 dma_unmap_addr(&tnapi
->tx_buffers
[entry
],
5966 frag
->size
, PCI_DMA_TODEVICE
);
5970 return NETDEV_TX_OK
;
5973 static inline void tg3_set_mtu(struct net_device
*dev
, struct tg3
*tp
,
5978 if (new_mtu
> ETH_DATA_LEN
) {
5979 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) {
5980 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_CAPABLE
;
5981 ethtool_op_set_tso(dev
, 0);
5983 tp
->tg3_flags
|= TG3_FLAG_JUMBO_RING_ENABLE
;
5986 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)
5987 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
5988 tp
->tg3_flags
&= ~TG3_FLAG_JUMBO_RING_ENABLE
;
5992 static int tg3_change_mtu(struct net_device
*dev
, int new_mtu
)
5994 struct tg3
*tp
= netdev_priv(dev
);
5997 if (new_mtu
< TG3_MIN_MTU
|| new_mtu
> TG3_MAX_MTU(tp
))
6000 if (!netif_running(dev
)) {
6001 /* We'll just catch it later when the
6004 tg3_set_mtu(dev
, tp
, new_mtu
);
6012 tg3_full_lock(tp
, 1);
6014 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
6016 tg3_set_mtu(dev
, tp
, new_mtu
);
6018 err
= tg3_restart_hw(tp
, 0);
6021 tg3_netif_start(tp
);
6023 tg3_full_unlock(tp
);
6031 static void tg3_rx_prodring_free(struct tg3
*tp
,
6032 struct tg3_rx_prodring_set
*tpr
)
6036 if (tpr
!= &tp
->prodring
[0]) {
6037 for (i
= tpr
->rx_std_cons_idx
; i
!= tpr
->rx_std_prod_idx
;
6038 i
= (i
+ 1) % TG3_RX_RING_SIZE
)
6039 tg3_rx_skb_free(tp
, &tpr
->rx_std_buffers
[i
],
6042 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
6043 for (i
= tpr
->rx_jmb_cons_idx
;
6044 i
!= tpr
->rx_jmb_prod_idx
;
6045 i
= (i
+ 1) % TG3_RX_JUMBO_RING_SIZE
) {
6046 tg3_rx_skb_free(tp
, &tpr
->rx_jmb_buffers
[i
],
6054 for (i
= 0; i
< TG3_RX_RING_SIZE
; i
++)
6055 tg3_rx_skb_free(tp
, &tpr
->rx_std_buffers
[i
],
6058 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
6059 for (i
= 0; i
< TG3_RX_JUMBO_RING_SIZE
; i
++)
6060 tg3_rx_skb_free(tp
, &tpr
->rx_jmb_buffers
[i
],
6065 /* Initialize rx rings for packet processing.
6067 * The chip has been shut down and the driver detached from
6068 * the networking, so no interrupts or new tx packets will
6069 * end up in the driver. tp->{tx,}lock are held and thus
6072 static int tg3_rx_prodring_alloc(struct tg3
*tp
,
6073 struct tg3_rx_prodring_set
*tpr
)
6075 u32 i
, rx_pkt_dma_sz
;
6077 tpr
->rx_std_cons_idx
= 0;
6078 tpr
->rx_std_prod_idx
= 0;
6079 tpr
->rx_jmb_cons_idx
= 0;
6080 tpr
->rx_jmb_prod_idx
= 0;
6082 if (tpr
!= &tp
->prodring
[0]) {
6083 memset(&tpr
->rx_std_buffers
[0], 0, TG3_RX_STD_BUFF_RING_SIZE
);
6084 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
)
6085 memset(&tpr
->rx_jmb_buffers
[0], 0,
6086 TG3_RX_JMB_BUFF_RING_SIZE
);
6090 /* Zero out all descriptors. */
6091 memset(tpr
->rx_std
, 0, TG3_RX_RING_BYTES
);
6093 rx_pkt_dma_sz
= TG3_RX_STD_DMA_SZ
;
6094 if ((tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) &&
6095 tp
->dev
->mtu
> ETH_DATA_LEN
)
6096 rx_pkt_dma_sz
= TG3_RX_JMB_DMA_SZ
;
6097 tp
->rx_pkt_map_sz
= TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz
);
6099 /* Initialize invariants of the rings, we only set this
6100 * stuff once. This works because the card does not
6101 * write into the rx buffer posting rings.
6103 for (i
= 0; i
< TG3_RX_RING_SIZE
; i
++) {
6104 struct tg3_rx_buffer_desc
*rxd
;
6106 rxd
= &tpr
->rx_std
[i
];
6107 rxd
->idx_len
= rx_pkt_dma_sz
<< RXD_LEN_SHIFT
;
6108 rxd
->type_flags
= (RXD_FLAG_END
<< RXD_FLAGS_SHIFT
);
6109 rxd
->opaque
= (RXD_OPAQUE_RING_STD
|
6110 (i
<< RXD_OPAQUE_INDEX_SHIFT
));
6113 /* Now allocate fresh SKBs for each rx ring. */
6114 for (i
= 0; i
< tp
->rx_pending
; i
++) {
6115 if (tg3_alloc_rx_skb(tp
, tpr
, RXD_OPAQUE_RING_STD
, i
) < 0) {
6116 netdev_warn(tp
->dev
,
6117 "Using a smaller RX standard ring. Only "
6118 "%d out of %d buffers were allocated "
6119 "successfully\n", i
, tp
->rx_pending
);
6127 if (!(tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
))
6130 memset(tpr
->rx_jmb
, 0, TG3_RX_JUMBO_RING_BYTES
);
6132 if (!(tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
))
6135 for (i
= 0; i
< TG3_RX_JUMBO_RING_SIZE
; i
++) {
6136 struct tg3_rx_buffer_desc
*rxd
;
6138 rxd
= &tpr
->rx_jmb
[i
].std
;
6139 rxd
->idx_len
= TG3_RX_JMB_DMA_SZ
<< RXD_LEN_SHIFT
;
6140 rxd
->type_flags
= (RXD_FLAG_END
<< RXD_FLAGS_SHIFT
) |
6142 rxd
->opaque
= (RXD_OPAQUE_RING_JUMBO
|
6143 (i
<< RXD_OPAQUE_INDEX_SHIFT
));
6146 for (i
= 0; i
< tp
->rx_jumbo_pending
; i
++) {
6147 if (tg3_alloc_rx_skb(tp
, tpr
, RXD_OPAQUE_RING_JUMBO
, i
) < 0) {
6148 netdev_warn(tp
->dev
,
6149 "Using a smaller RX jumbo ring. Only %d "
6150 "out of %d buffers were allocated "
6151 "successfully\n", i
, tp
->rx_jumbo_pending
);
6154 tp
->rx_jumbo_pending
= i
;
6163 tg3_rx_prodring_free(tp
, tpr
);
6167 static void tg3_rx_prodring_fini(struct tg3
*tp
,
6168 struct tg3_rx_prodring_set
*tpr
)
6170 kfree(tpr
->rx_std_buffers
);
6171 tpr
->rx_std_buffers
= NULL
;
6172 kfree(tpr
->rx_jmb_buffers
);
6173 tpr
->rx_jmb_buffers
= NULL
;
6175 pci_free_consistent(tp
->pdev
, TG3_RX_RING_BYTES
,
6176 tpr
->rx_std
, tpr
->rx_std_mapping
);
6180 pci_free_consistent(tp
->pdev
, TG3_RX_JUMBO_RING_BYTES
,
6181 tpr
->rx_jmb
, tpr
->rx_jmb_mapping
);
6186 static int tg3_rx_prodring_init(struct tg3
*tp
,
6187 struct tg3_rx_prodring_set
*tpr
)
6189 tpr
->rx_std_buffers
= kzalloc(TG3_RX_STD_BUFF_RING_SIZE
, GFP_KERNEL
);
6190 if (!tpr
->rx_std_buffers
)
6193 tpr
->rx_std
= pci_alloc_consistent(tp
->pdev
, TG3_RX_RING_BYTES
,
6194 &tpr
->rx_std_mapping
);
6198 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
6199 tpr
->rx_jmb_buffers
= kzalloc(TG3_RX_JMB_BUFF_RING_SIZE
,
6201 if (!tpr
->rx_jmb_buffers
)
6204 tpr
->rx_jmb
= pci_alloc_consistent(tp
->pdev
,
6205 TG3_RX_JUMBO_RING_BYTES
,
6206 &tpr
->rx_jmb_mapping
);
6214 tg3_rx_prodring_fini(tp
, tpr
);
6218 /* Free up pending packets in all rx/tx rings.
6220 * The chip has been shut down and the driver detached from
6221 * the networking, so no interrupts or new tx packets will
6222 * end up in the driver. tp->{tx,}lock is not held and we are not
6223 * in an interrupt context and thus may sleep.
6225 static void tg3_free_rings(struct tg3
*tp
)
6229 for (j
= 0; j
< tp
->irq_cnt
; j
++) {
6230 struct tg3_napi
*tnapi
= &tp
->napi
[j
];
6232 tg3_rx_prodring_free(tp
, &tp
->prodring
[j
]);
6234 if (!tnapi
->tx_buffers
)
6237 for (i
= 0; i
< TG3_TX_RING_SIZE
; ) {
6238 struct ring_info
*txp
;
6239 struct sk_buff
*skb
;
6242 txp
= &tnapi
->tx_buffers
[i
];
6250 pci_unmap_single(tp
->pdev
,
6251 dma_unmap_addr(txp
, mapping
),
6258 for (k
= 0; k
< skb_shinfo(skb
)->nr_frags
; k
++) {
6259 txp
= &tnapi
->tx_buffers
[i
& (TG3_TX_RING_SIZE
- 1)];
6260 pci_unmap_page(tp
->pdev
,
6261 dma_unmap_addr(txp
, mapping
),
6262 skb_shinfo(skb
)->frags
[k
].size
,
6267 dev_kfree_skb_any(skb
);
6272 /* Initialize tx/rx rings for packet processing.
6274 * The chip has been shut down and the driver detached from
6275 * the networking, so no interrupts or new tx packets will
6276 * end up in the driver. tp->{tx,}lock are held and thus
6279 static int tg3_init_rings(struct tg3
*tp
)
6283 /* Free up all the SKBs. */
6286 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6287 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6289 tnapi
->last_tag
= 0;
6290 tnapi
->last_irq_tag
= 0;
6291 tnapi
->hw_status
->status
= 0;
6292 tnapi
->hw_status
->status_tag
= 0;
6293 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
6298 memset(tnapi
->tx_ring
, 0, TG3_TX_RING_BYTES
);
6300 tnapi
->rx_rcb_ptr
= 0;
6302 memset(tnapi
->rx_rcb
, 0, TG3_RX_RCB_RING_BYTES(tp
));
6304 if (tg3_rx_prodring_alloc(tp
, &tp
->prodring
[i
])) {
6314 * Must not be invoked with interrupt sources disabled and
6315 * the hardware shutdown down.
6317 static void tg3_free_consistent(struct tg3
*tp
)
6321 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6322 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6324 if (tnapi
->tx_ring
) {
6325 pci_free_consistent(tp
->pdev
, TG3_TX_RING_BYTES
,
6326 tnapi
->tx_ring
, tnapi
->tx_desc_mapping
);
6327 tnapi
->tx_ring
= NULL
;
6330 kfree(tnapi
->tx_buffers
);
6331 tnapi
->tx_buffers
= NULL
;
6333 if (tnapi
->rx_rcb
) {
6334 pci_free_consistent(tp
->pdev
, TG3_RX_RCB_RING_BYTES(tp
),
6336 tnapi
->rx_rcb_mapping
);
6337 tnapi
->rx_rcb
= NULL
;
6340 if (tnapi
->hw_status
) {
6341 pci_free_consistent(tp
->pdev
, TG3_HW_STATUS_SIZE
,
6343 tnapi
->status_mapping
);
6344 tnapi
->hw_status
= NULL
;
6349 pci_free_consistent(tp
->pdev
, sizeof(struct tg3_hw_stats
),
6350 tp
->hw_stats
, tp
->stats_mapping
);
6351 tp
->hw_stats
= NULL
;
6354 for (i
= 0; i
< tp
->irq_cnt
; i
++)
6355 tg3_rx_prodring_fini(tp
, &tp
->prodring
[i
]);
6359 * Must not be invoked with interrupt sources disabled and
6360 * the hardware shutdown down. Can sleep.
6362 static int tg3_alloc_consistent(struct tg3
*tp
)
6366 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6367 if (tg3_rx_prodring_init(tp
, &tp
->prodring
[i
]))
6371 tp
->hw_stats
= pci_alloc_consistent(tp
->pdev
,
6372 sizeof(struct tg3_hw_stats
),
6373 &tp
->stats_mapping
);
6377 memset(tp
->hw_stats
, 0, sizeof(struct tg3_hw_stats
));
6379 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6380 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6381 struct tg3_hw_status
*sblk
;
6383 tnapi
->hw_status
= pci_alloc_consistent(tp
->pdev
,
6385 &tnapi
->status_mapping
);
6386 if (!tnapi
->hw_status
)
6389 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
6390 sblk
= tnapi
->hw_status
;
6392 /* If multivector TSS is enabled, vector 0 does not handle
6393 * tx interrupts. Don't allocate any resources for it.
6395 if ((!i
&& !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)) ||
6396 (i
&& (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
))) {
6397 tnapi
->tx_buffers
= kzalloc(sizeof(struct ring_info
) *
6400 if (!tnapi
->tx_buffers
)
6403 tnapi
->tx_ring
= pci_alloc_consistent(tp
->pdev
,
6405 &tnapi
->tx_desc_mapping
);
6406 if (!tnapi
->tx_ring
)
6411 * When RSS is enabled, the status block format changes
6412 * slightly. The "rx_jumbo_consumer", "reserved",
6413 * and "rx_mini_consumer" members get mapped to the
6414 * other three rx return ring producer indexes.
6418 tnapi
->rx_rcb_prod_idx
= &sblk
->idx
[0].rx_producer
;
6421 tnapi
->rx_rcb_prod_idx
= &sblk
->rx_jumbo_consumer
;
6424 tnapi
->rx_rcb_prod_idx
= &sblk
->reserved
;
6427 tnapi
->rx_rcb_prod_idx
= &sblk
->rx_mini_consumer
;
6431 tnapi
->prodring
= &tp
->prodring
[i
];
6434 * If multivector RSS is enabled, vector 0 does not handle
6435 * rx or tx interrupts. Don't allocate any resources for it.
6437 if (!i
&& (tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
))
6440 tnapi
->rx_rcb
= pci_alloc_consistent(tp
->pdev
,
6441 TG3_RX_RCB_RING_BYTES(tp
),
6442 &tnapi
->rx_rcb_mapping
);
6446 memset(tnapi
->rx_rcb
, 0, TG3_RX_RCB_RING_BYTES(tp
));
6452 tg3_free_consistent(tp
);
6456 #define MAX_WAIT_CNT 1000
6458 /* To stop a block, clear the enable bit and poll till it
6459 * clears. tp->lock is held.
6461 static int tg3_stop_block(struct tg3
*tp
, unsigned long ofs
, u32 enable_bit
, int silent
)
6466 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
6473 /* We can't enable/disable these bits of the
6474 * 5705/5750, just say success.
6487 for (i
= 0; i
< MAX_WAIT_CNT
; i
++) {
6490 if ((val
& enable_bit
) == 0)
6494 if (i
== MAX_WAIT_CNT
&& !silent
) {
6495 dev_err(&tp
->pdev
->dev
,
6496 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6504 /* tp->lock is held. */
6505 static int tg3_abort_hw(struct tg3
*tp
, int silent
)
6509 tg3_disable_ints(tp
);
6511 tp
->rx_mode
&= ~RX_MODE_ENABLE
;
6512 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
6515 err
= tg3_stop_block(tp
, RCVBDI_MODE
, RCVBDI_MODE_ENABLE
, silent
);
6516 err
|= tg3_stop_block(tp
, RCVLPC_MODE
, RCVLPC_MODE_ENABLE
, silent
);
6517 err
|= tg3_stop_block(tp
, RCVLSC_MODE
, RCVLSC_MODE_ENABLE
, silent
);
6518 err
|= tg3_stop_block(tp
, RCVDBDI_MODE
, RCVDBDI_MODE_ENABLE
, silent
);
6519 err
|= tg3_stop_block(tp
, RCVDCC_MODE
, RCVDCC_MODE_ENABLE
, silent
);
6520 err
|= tg3_stop_block(tp
, RCVCC_MODE
, RCVCC_MODE_ENABLE
, silent
);
6522 err
|= tg3_stop_block(tp
, SNDBDS_MODE
, SNDBDS_MODE_ENABLE
, silent
);
6523 err
|= tg3_stop_block(tp
, SNDBDI_MODE
, SNDBDI_MODE_ENABLE
, silent
);
6524 err
|= tg3_stop_block(tp
, SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
, silent
);
6525 err
|= tg3_stop_block(tp
, RDMAC_MODE
, RDMAC_MODE_ENABLE
, silent
);
6526 err
|= tg3_stop_block(tp
, SNDDATAC_MODE
, SNDDATAC_MODE_ENABLE
, silent
);
6527 err
|= tg3_stop_block(tp
, DMAC_MODE
, DMAC_MODE_ENABLE
, silent
);
6528 err
|= tg3_stop_block(tp
, SNDBDC_MODE
, SNDBDC_MODE_ENABLE
, silent
);
6530 tp
->mac_mode
&= ~MAC_MODE_TDE_ENABLE
;
6531 tw32_f(MAC_MODE
, tp
->mac_mode
);
6534 tp
->tx_mode
&= ~TX_MODE_ENABLE
;
6535 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
6537 for (i
= 0; i
< MAX_WAIT_CNT
; i
++) {
6539 if (!(tr32(MAC_TX_MODE
) & TX_MODE_ENABLE
))
6542 if (i
>= MAX_WAIT_CNT
) {
6543 dev_err(&tp
->pdev
->dev
,
6544 "%s timed out, TX_MODE_ENABLE will not clear "
6545 "MAC_TX_MODE=%08x\n", __func__
, tr32(MAC_TX_MODE
));
6549 err
|= tg3_stop_block(tp
, HOSTCC_MODE
, HOSTCC_MODE_ENABLE
, silent
);
6550 err
|= tg3_stop_block(tp
, WDMAC_MODE
, WDMAC_MODE_ENABLE
, silent
);
6551 err
|= tg3_stop_block(tp
, MBFREE_MODE
, MBFREE_MODE_ENABLE
, silent
);
6553 tw32(FTQ_RESET
, 0xffffffff);
6554 tw32(FTQ_RESET
, 0x00000000);
6556 err
|= tg3_stop_block(tp
, BUFMGR_MODE
, BUFMGR_MODE_ENABLE
, silent
);
6557 err
|= tg3_stop_block(tp
, MEMARB_MODE
, MEMARB_MODE_ENABLE
, silent
);
6559 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6560 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6561 if (tnapi
->hw_status
)
6562 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
6565 memset(tp
->hw_stats
, 0, sizeof(struct tg3_hw_stats
));
6570 static void tg3_ape_send_event(struct tg3
*tp
, u32 event
)
6575 apedata
= tg3_ape_read32(tp
, TG3_APE_SEG_SIG
);
6576 if (apedata
!= APE_SEG_SIG_MAGIC
)
6579 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_STATUS
);
6580 if (!(apedata
& APE_FW_STATUS_READY
))
6583 /* Wait for up to 1 millisecond for APE to service previous event. */
6584 for (i
= 0; i
< 10; i
++) {
6585 if (tg3_ape_lock(tp
, TG3_APE_LOCK_MEM
))
6588 apedata
= tg3_ape_read32(tp
, TG3_APE_EVENT_STATUS
);
6590 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
6591 tg3_ape_write32(tp
, TG3_APE_EVENT_STATUS
,
6592 event
| APE_EVENT_STATUS_EVENT_PENDING
);
6594 tg3_ape_unlock(tp
, TG3_APE_LOCK_MEM
);
6596 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
6602 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
6603 tg3_ape_write32(tp
, TG3_APE_EVENT
, APE_EVENT_1
);
6606 static void tg3_ape_driver_state_change(struct tg3
*tp
, int kind
)
6611 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
6615 case RESET_KIND_INIT
:
6616 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_SIG
,
6617 APE_HOST_SEG_SIG_MAGIC
);
6618 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_LEN
,
6619 APE_HOST_SEG_LEN_MAGIC
);
6620 apedata
= tg3_ape_read32(tp
, TG3_APE_HOST_INIT_COUNT
);
6621 tg3_ape_write32(tp
, TG3_APE_HOST_INIT_COUNT
, ++apedata
);
6622 tg3_ape_write32(tp
, TG3_APE_HOST_DRIVER_ID
,
6623 APE_HOST_DRIVER_ID_MAGIC
);
6624 tg3_ape_write32(tp
, TG3_APE_HOST_BEHAVIOR
,
6625 APE_HOST_BEHAV_NO_PHYLOCK
);
6627 event
= APE_EVENT_STATUS_STATE_START
;
6629 case RESET_KIND_SHUTDOWN
:
6630 /* With the interface we are currently using,
6631 * APE does not track driver state. Wiping
6632 * out the HOST SEGMENT SIGNATURE forces
6633 * the APE to assume OS absent status.
6635 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_SIG
, 0x0);
6637 event
= APE_EVENT_STATUS_STATE_UNLOAD
;
6639 case RESET_KIND_SUSPEND
:
6640 event
= APE_EVENT_STATUS_STATE_SUSPEND
;
6646 event
|= APE_EVENT_STATUS_DRIVER_EVNT
| APE_EVENT_STATUS_STATE_CHNGE
;
6648 tg3_ape_send_event(tp
, event
);
6651 /* tp->lock is held. */
6652 static void tg3_write_sig_pre_reset(struct tg3
*tp
, int kind
)
6654 tg3_write_mem(tp
, NIC_SRAM_FIRMWARE_MBOX
,
6655 NIC_SRAM_FIRMWARE_MBOX_MAGIC1
);
6657 if (tp
->tg3_flags2
& TG3_FLG2_ASF_NEW_HANDSHAKE
) {
6659 case RESET_KIND_INIT
:
6660 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6664 case RESET_KIND_SHUTDOWN
:
6665 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6669 case RESET_KIND_SUSPEND
:
6670 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6679 if (kind
== RESET_KIND_INIT
||
6680 kind
== RESET_KIND_SUSPEND
)
6681 tg3_ape_driver_state_change(tp
, kind
);
6684 /* tp->lock is held. */
6685 static void tg3_write_sig_post_reset(struct tg3
*tp
, int kind
)
6687 if (tp
->tg3_flags2
& TG3_FLG2_ASF_NEW_HANDSHAKE
) {
6689 case RESET_KIND_INIT
:
6690 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6691 DRV_STATE_START_DONE
);
6694 case RESET_KIND_SHUTDOWN
:
6695 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6696 DRV_STATE_UNLOAD_DONE
);
6704 if (kind
== RESET_KIND_SHUTDOWN
)
6705 tg3_ape_driver_state_change(tp
, kind
);
6708 /* tp->lock is held. */
6709 static void tg3_write_sig_legacy(struct tg3
*tp
, int kind
)
6711 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) {
6713 case RESET_KIND_INIT
:
6714 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6718 case RESET_KIND_SHUTDOWN
:
6719 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6723 case RESET_KIND_SUSPEND
:
6724 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6734 static int tg3_poll_fw(struct tg3
*tp
)
6739 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
6740 /* Wait up to 20ms for init done. */
6741 for (i
= 0; i
< 200; i
++) {
6742 if (tr32(VCPU_STATUS
) & VCPU_STATUS_INIT_DONE
)
6749 /* Wait for firmware initialization to complete. */
6750 for (i
= 0; i
< 100000; i
++) {
6751 tg3_read_mem(tp
, NIC_SRAM_FIRMWARE_MBOX
, &val
);
6752 if (val
== ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1
)
6757 /* Chip might not be fitted with firmware. Some Sun onboard
6758 * parts are configured like that. So don't signal the timeout
6759 * of the above loop as an error, but do report the lack of
6760 * running firmware once.
6763 !(tp
->tg3_flags2
& TG3_FLG2_NO_FWARE_REPORTED
)) {
6764 tp
->tg3_flags2
|= TG3_FLG2_NO_FWARE_REPORTED
;
6766 netdev_info(tp
->dev
, "No firmware running\n");
6769 if (tp
->pci_chip_rev_id
== CHIPREV_ID_57765_A0
) {
6770 /* The 57765 A0 needs a little more
6771 * time to do some important work.
6779 /* Save PCI command register before chip reset */
6780 static void tg3_save_pci_state(struct tg3
*tp
)
6782 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &tp
->pci_cmd
);
6785 /* Restore PCI state after chip reset */
6786 static void tg3_restore_pci_state(struct tg3
*tp
)
6790 /* Re-enable indirect register accesses. */
6791 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
6792 tp
->misc_host_ctrl
);
6794 /* Set MAX PCI retry to zero. */
6795 val
= (PCISTATE_ROM_ENABLE
| PCISTATE_ROM_RETRY_ENABLE
);
6796 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
&&
6797 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
))
6798 val
|= PCISTATE_RETRY_SAME_DMA
;
6799 /* Allow reads and writes to the APE register and memory space. */
6800 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
6801 val
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
6802 PCISTATE_ALLOW_APE_SHMEM_WR
|
6803 PCISTATE_ALLOW_APE_PSPACE_WR
;
6804 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, val
);
6806 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, tp
->pci_cmd
);
6808 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
) {
6809 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)
6810 pcie_set_readrq(tp
->pdev
, 4096);
6812 pci_write_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
,
6813 tp
->pci_cacheline_sz
);
6814 pci_write_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
6819 /* Make sure PCI-X relaxed ordering bit is clear. */
6820 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
6823 pci_read_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
6825 pcix_cmd
&= ~PCI_X_CMD_ERO
;
6826 pci_write_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
6830 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) {
6832 /* Chip reset on 5780 will reset MSI enable bit,
6833 * so need to restore it.
6835 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
6838 pci_read_config_word(tp
->pdev
,
6839 tp
->msi_cap
+ PCI_MSI_FLAGS
,
6841 pci_write_config_word(tp
->pdev
,
6842 tp
->msi_cap
+ PCI_MSI_FLAGS
,
6843 ctrl
| PCI_MSI_FLAGS_ENABLE
);
6844 val
= tr32(MSGINT_MODE
);
6845 tw32(MSGINT_MODE
, val
| MSGINT_MODE_ENABLE
);
6850 static void tg3_stop_fw(struct tg3
*);
6852 /* tp->lock is held. */
6853 static int tg3_chip_reset(struct tg3
*tp
)
6856 void (*write_op
)(struct tg3
*, u32
, u32
);
6861 tg3_ape_lock(tp
, TG3_APE_LOCK_GRC
);
6863 /* No matching tg3_nvram_unlock() after this because
6864 * chip reset below will undo the nvram lock.
6866 tp
->nvram_lock_cnt
= 0;
6868 /* GRC_MISC_CFG core clock reset will clear the memory
6869 * enable bit in PCI register 4 and the MSI enable bit
6870 * on some chips, so we save relevant registers here.
6872 tg3_save_pci_state(tp
);
6874 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
6875 (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
))
6876 tw32(GRC_FASTBOOT_PC
, 0);
6879 * We must avoid the readl() that normally takes place.
6880 * It locks machines, causes machine checks, and other
6881 * fun things. So, temporarily disable the 5701
6882 * hardware workaround, while we do the reset.
6884 write_op
= tp
->write32
;
6885 if (write_op
== tg3_write_flush_reg32
)
6886 tp
->write32
= tg3_write32
;
6888 /* Prevent the irq handler from reading or writing PCI registers
6889 * during chip reset when the memory enable bit in the PCI command
6890 * register may be cleared. The chip does not generate interrupt
6891 * at this time, but the irq handler may still be called due to irq
6892 * sharing or irqpoll.
6894 tp
->tg3_flags
|= TG3_FLAG_CHIP_RESETTING
;
6895 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6896 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6897 if (tnapi
->hw_status
) {
6898 tnapi
->hw_status
->status
= 0;
6899 tnapi
->hw_status
->status_tag
= 0;
6901 tnapi
->last_tag
= 0;
6902 tnapi
->last_irq_tag
= 0;
6906 for (i
= 0; i
< tp
->irq_cnt
; i
++)
6907 synchronize_irq(tp
->napi
[i
].irq_vec
);
6909 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
) {
6910 val
= tr32(TG3_PCIE_LNKCTL
) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN
;
6911 tw32(TG3_PCIE_LNKCTL
, val
| TG3_PCIE_LNKCTL_L1_PLL_PD_DIS
);
6915 val
= GRC_MISC_CFG_CORECLK_RESET
;
6917 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
6918 if (tr32(0x7e2c) == 0x60) {
6921 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
) {
6922 tw32(GRC_MISC_CFG
, (1 << 29));
6927 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
6928 tw32(VCPU_STATUS
, tr32(VCPU_STATUS
) | VCPU_STATUS_DRV_RESET
);
6929 tw32(GRC_VCPU_EXT_CTRL
,
6930 tr32(GRC_VCPU_EXT_CTRL
) & ~GRC_VCPU_EXT_CTRL_HALT_CPU
);
6933 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
6934 val
|= GRC_MISC_CFG_KEEP_GPHY_POWER
;
6935 tw32(GRC_MISC_CFG
, val
);
6937 /* restore 5701 hardware bug workaround write method */
6938 tp
->write32
= write_op
;
6940 /* Unfortunately, we have to delay before the PCI read back.
6941 * Some 575X chips even will not respond to a PCI cfg access
6942 * when the reset command is given to the chip.
6944 * How do these hardware designers expect things to work
6945 * properly if the PCI write is posted for a long period
6946 * of time? It is always necessary to have some method by
6947 * which a register read back can occur to push the write
6948 * out which does the reset.
6950 * For most tg3 variants the trick below was working.
6955 /* Flush PCI posted writes. The normal MMIO registers
6956 * are inaccessible at this time so this is the only
6957 * way to make this reliably (actually, this is no longer
6958 * the case, see above). I tried to use indirect
6959 * register read/write but this upset some 5701 variants.
6961 pci_read_config_dword(tp
->pdev
, PCI_COMMAND
, &val
);
6965 if ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) && tp
->pcie_cap
) {
6968 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A0
) {
6972 /* Wait for link training to complete. */
6973 for (i
= 0; i
< 5000; i
++)
6976 pci_read_config_dword(tp
->pdev
, 0xc4, &cfg_val
);
6977 pci_write_config_dword(tp
->pdev
, 0xc4,
6978 cfg_val
| (1 << 15));
6981 /* Clear the "no snoop" and "relaxed ordering" bits. */
6982 pci_read_config_word(tp
->pdev
,
6983 tp
->pcie_cap
+ PCI_EXP_DEVCTL
,
6985 val16
&= ~(PCI_EXP_DEVCTL_RELAX_EN
|
6986 PCI_EXP_DEVCTL_NOSNOOP_EN
);
6988 * Older PCIe devices only support the 128 byte
6989 * MPS setting. Enforce the restriction.
6991 if (!(tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) ||
6992 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
))
6993 val16
&= ~PCI_EXP_DEVCTL_PAYLOAD
;
6994 pci_write_config_word(tp
->pdev
,
6995 tp
->pcie_cap
+ PCI_EXP_DEVCTL
,
6998 pcie_set_readrq(tp
->pdev
, 4096);
7000 /* Clear error status */
7001 pci_write_config_word(tp
->pdev
,
7002 tp
->pcie_cap
+ PCI_EXP_DEVSTA
,
7003 PCI_EXP_DEVSTA_CED
|
7004 PCI_EXP_DEVSTA_NFED
|
7005 PCI_EXP_DEVSTA_FED
|
7006 PCI_EXP_DEVSTA_URD
);
7009 tg3_restore_pci_state(tp
);
7011 tp
->tg3_flags
&= ~TG3_FLAG_CHIP_RESETTING
;
7014 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)
7015 val
= tr32(MEMARB_MODE
);
7016 tw32(MEMARB_MODE
, val
| MEMARB_MODE_ENABLE
);
7018 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A3
) {
7020 tw32(0x5000, 0x400);
7023 tw32(GRC_MODE
, tp
->grc_mode
);
7025 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
) {
7028 tw32(0xc4, val
| (1 << 15));
7031 if ((tp
->nic_sram_data_cfg
& NIC_SRAM_DATA_CFG_MINI_PCI
) != 0 &&
7032 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
7033 tp
->pci_clock_ctrl
|= CLOCK_CTRL_CLKRUN_OENABLE
;
7034 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
)
7035 tp
->pci_clock_ctrl
|= CLOCK_CTRL_FORCE_CLKRUN
;
7036 tw32(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
);
7039 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
7040 tp
->mac_mode
= MAC_MODE_PORT_MODE_TBI
;
7041 tw32_f(MAC_MODE
, tp
->mac_mode
);
7042 } else if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) {
7043 tp
->mac_mode
= MAC_MODE_PORT_MODE_GMII
;
7044 tw32_f(MAC_MODE
, tp
->mac_mode
);
7045 } else if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
7046 tp
->mac_mode
&= (MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
);
7047 if (tp
->mac_mode
& MAC_MODE_APE_TX_EN
)
7048 tp
->mac_mode
|= MAC_MODE_TDE_ENABLE
;
7049 tw32_f(MAC_MODE
, tp
->mac_mode
);
7051 tw32_f(MAC_MODE
, 0);
7054 tg3_ape_unlock(tp
, TG3_APE_LOCK_GRC
);
7056 err
= tg3_poll_fw(tp
);
7062 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
) {
7065 phy_addr
= tp
->phy_addr
;
7066 tp
->phy_addr
= TG3_PHY_PCIE_ADDR
;
7068 tg3_writephy(tp
, TG3_PCIEPHY_BLOCK_ADDR
,
7069 TG3_PCIEPHY_TXB_BLK
<< TG3_PCIEPHY_BLOCK_SHIFT
);
7070 val
= TG3_PCIEPHY_TX0CTRL1_TXOCM
| TG3_PCIEPHY_TX0CTRL1_RDCTL
|
7071 TG3_PCIEPHY_TX0CTRL1_TXCMV
| TG3_PCIEPHY_TX0CTRL1_TKSEL
|
7072 TG3_PCIEPHY_TX0CTRL1_NB_EN
;
7073 tg3_writephy(tp
, TG3_PCIEPHY_TX0CTRL1
, val
);
7076 tg3_writephy(tp
, TG3_PCIEPHY_BLOCK_ADDR
,
7077 TG3_PCIEPHY_XGXS_BLK1
<< TG3_PCIEPHY_BLOCK_SHIFT
);
7078 val
= TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN
|
7079 TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN
;
7080 tg3_writephy(tp
, TG3_PCIEPHY_PWRMGMT4
, val
);
7083 tp
->phy_addr
= phy_addr
;
7086 if ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) &&
7087 tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
&&
7088 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
&&
7089 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5717
&&
7090 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_57765
) {
7093 tw32(0x7c00, val
| (1 << 25));
7096 /* Reprobe ASF enable state. */
7097 tp
->tg3_flags
&= ~TG3_FLAG_ENABLE_ASF
;
7098 tp
->tg3_flags2
&= ~TG3_FLG2_ASF_NEW_HANDSHAKE
;
7099 tg3_read_mem(tp
, NIC_SRAM_DATA_SIG
, &val
);
7100 if (val
== NIC_SRAM_DATA_SIG_MAGIC
) {
7103 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG
, &nic_cfg
);
7104 if (nic_cfg
& NIC_SRAM_DATA_CFG_ASF_ENABLE
) {
7105 tp
->tg3_flags
|= TG3_FLAG_ENABLE_ASF
;
7106 tp
->last_event_jiffies
= jiffies
;
7107 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
7108 tp
->tg3_flags2
|= TG3_FLG2_ASF_NEW_HANDSHAKE
;
7115 /* tp->lock is held. */
7116 static void tg3_stop_fw(struct tg3
*tp
)
7118 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) &&
7119 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
7120 /* Wait for RX cpu to ACK the previous event. */
7121 tg3_wait_for_event_ack(tp
);
7123 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
, FWCMD_NICDRV_PAUSE_FW
);
7125 tg3_generate_fw_event(tp
);
7127 /* Wait for RX cpu to ACK this event. */
7128 tg3_wait_for_event_ack(tp
);
7132 /* tp->lock is held. */
7133 static int tg3_halt(struct tg3
*tp
, int kind
, int silent
)
7139 tg3_write_sig_pre_reset(tp
, kind
);
7141 tg3_abort_hw(tp
, silent
);
7142 err
= tg3_chip_reset(tp
);
7144 __tg3_set_mac_addr(tp
, 0);
7146 tg3_write_sig_legacy(tp
, kind
);
7147 tg3_write_sig_post_reset(tp
, kind
);
7155 #define RX_CPU_SCRATCH_BASE 0x30000
7156 #define RX_CPU_SCRATCH_SIZE 0x04000
7157 #define TX_CPU_SCRATCH_BASE 0x34000
7158 #define TX_CPU_SCRATCH_SIZE 0x04000
7160 /* tp->lock is held. */
7161 static int tg3_halt_cpu(struct tg3
*tp
, u32 offset
)
7165 BUG_ON(offset
== TX_CPU_BASE
&&
7166 (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
));
7168 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
7169 u32 val
= tr32(GRC_VCPU_EXT_CTRL
);
7171 tw32(GRC_VCPU_EXT_CTRL
, val
| GRC_VCPU_EXT_CTRL_HALT_CPU
);
7174 if (offset
== RX_CPU_BASE
) {
7175 for (i
= 0; i
< 10000; i
++) {
7176 tw32(offset
+ CPU_STATE
, 0xffffffff);
7177 tw32(offset
+ CPU_MODE
, CPU_MODE_HALT
);
7178 if (tr32(offset
+ CPU_MODE
) & CPU_MODE_HALT
)
7182 tw32(offset
+ CPU_STATE
, 0xffffffff);
7183 tw32_f(offset
+ CPU_MODE
, CPU_MODE_HALT
);
7186 for (i
= 0; i
< 10000; i
++) {
7187 tw32(offset
+ CPU_STATE
, 0xffffffff);
7188 tw32(offset
+ CPU_MODE
, CPU_MODE_HALT
);
7189 if (tr32(offset
+ CPU_MODE
) & CPU_MODE_HALT
)
7195 netdev_err(tp
->dev
, "%s timed out, %s CPU\n",
7196 __func__
, offset
== RX_CPU_BASE
? "RX" : "TX");
7200 /* Clear firmware's nvram arbitration. */
7201 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
)
7202 tw32(NVRAM_SWARB
, SWARB_REQ_CLR0
);
7207 unsigned int fw_base
;
7208 unsigned int fw_len
;
7209 const __be32
*fw_data
;
7212 /* tp->lock is held. */
7213 static int tg3_load_firmware_cpu(struct tg3
*tp
, u32 cpu_base
, u32 cpu_scratch_base
,
7214 int cpu_scratch_size
, struct fw_info
*info
)
7216 int err
, lock_err
, i
;
7217 void (*write_op
)(struct tg3
*, u32
, u32
);
7219 if (cpu_base
== TX_CPU_BASE
&&
7220 (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
7222 "%s: Trying to load TX cpu firmware which is 5705\n",
7227 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
7228 write_op
= tg3_write_mem
;
7230 write_op
= tg3_write_indirect_reg32
;
7232 /* It is possible that bootcode is still loading at this point.
7233 * Get the nvram lock first before halting the cpu.
7235 lock_err
= tg3_nvram_lock(tp
);
7236 err
= tg3_halt_cpu(tp
, cpu_base
);
7238 tg3_nvram_unlock(tp
);
7242 for (i
= 0; i
< cpu_scratch_size
; i
+= sizeof(u32
))
7243 write_op(tp
, cpu_scratch_base
+ i
, 0);
7244 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
7245 tw32(cpu_base
+ CPU_MODE
, tr32(cpu_base
+CPU_MODE
)|CPU_MODE_HALT
);
7246 for (i
= 0; i
< (info
->fw_len
/ sizeof(u32
)); i
++)
7247 write_op(tp
, (cpu_scratch_base
+
7248 (info
->fw_base
& 0xffff) +
7250 be32_to_cpu(info
->fw_data
[i
]));
7258 /* tp->lock is held. */
7259 static int tg3_load_5701_a0_firmware_fix(struct tg3
*tp
)
7261 struct fw_info info
;
7262 const __be32
*fw_data
;
7265 fw_data
= (void *)tp
->fw
->data
;
7267 /* Firmware blob starts with version numbers, followed by
7268 start address and length. We are setting complete length.
7269 length = end_address_of_bss - start_address_of_text.
7270 Remainder is the blob to be loaded contiguously
7271 from start address. */
7273 info
.fw_base
= be32_to_cpu(fw_data
[1]);
7274 info
.fw_len
= tp
->fw
->size
- 12;
7275 info
.fw_data
= &fw_data
[3];
7277 err
= tg3_load_firmware_cpu(tp
, RX_CPU_BASE
,
7278 RX_CPU_SCRATCH_BASE
, RX_CPU_SCRATCH_SIZE
,
7283 err
= tg3_load_firmware_cpu(tp
, TX_CPU_BASE
,
7284 TX_CPU_SCRATCH_BASE
, TX_CPU_SCRATCH_SIZE
,
7289 /* Now startup only the RX cpu. */
7290 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
7291 tw32_f(RX_CPU_BASE
+ CPU_PC
, info
.fw_base
);
7293 for (i
= 0; i
< 5; i
++) {
7294 if (tr32(RX_CPU_BASE
+ CPU_PC
) == info
.fw_base
)
7296 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
7297 tw32(RX_CPU_BASE
+ CPU_MODE
, CPU_MODE_HALT
);
7298 tw32_f(RX_CPU_BASE
+ CPU_PC
, info
.fw_base
);
7302 netdev_err(tp
->dev
, "%s fails to set RX CPU PC, is %08x "
7303 "should be %08x\n", __func__
,
7304 tr32(RX_CPU_BASE
+ CPU_PC
), info
.fw_base
);
7307 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
7308 tw32_f(RX_CPU_BASE
+ CPU_MODE
, 0x00000000);
7313 /* 5705 needs a special version of the TSO firmware. */
7315 /* tp->lock is held. */
7316 static int tg3_load_tso_firmware(struct tg3
*tp
)
7318 struct fw_info info
;
7319 const __be32
*fw_data
;
7320 unsigned long cpu_base
, cpu_scratch_base
, cpu_scratch_size
;
7323 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
7326 fw_data
= (void *)tp
->fw
->data
;
7328 /* Firmware blob starts with version numbers, followed by
7329 start address and length. We are setting complete length.
7330 length = end_address_of_bss - start_address_of_text.
7331 Remainder is the blob to be loaded contiguously
7332 from start address. */
7334 info
.fw_base
= be32_to_cpu(fw_data
[1]);
7335 cpu_scratch_size
= tp
->fw_len
;
7336 info
.fw_len
= tp
->fw
->size
- 12;
7337 info
.fw_data
= &fw_data
[3];
7339 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
7340 cpu_base
= RX_CPU_BASE
;
7341 cpu_scratch_base
= NIC_SRAM_MBUF_POOL_BASE5705
;
7343 cpu_base
= TX_CPU_BASE
;
7344 cpu_scratch_base
= TX_CPU_SCRATCH_BASE
;
7345 cpu_scratch_size
= TX_CPU_SCRATCH_SIZE
;
7348 err
= tg3_load_firmware_cpu(tp
, cpu_base
,
7349 cpu_scratch_base
, cpu_scratch_size
,
7354 /* Now startup the cpu. */
7355 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
7356 tw32_f(cpu_base
+ CPU_PC
, info
.fw_base
);
7358 for (i
= 0; i
< 5; i
++) {
7359 if (tr32(cpu_base
+ CPU_PC
) == info
.fw_base
)
7361 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
7362 tw32(cpu_base
+ CPU_MODE
, CPU_MODE_HALT
);
7363 tw32_f(cpu_base
+ CPU_PC
, info
.fw_base
);
7368 "%s fails to set CPU PC, is %08x should be %08x\n",
7369 __func__
, tr32(cpu_base
+ CPU_PC
), info
.fw_base
);
7372 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
7373 tw32_f(cpu_base
+ CPU_MODE
, 0x00000000);
7378 static int tg3_set_mac_addr(struct net_device
*dev
, void *p
)
7380 struct tg3
*tp
= netdev_priv(dev
);
7381 struct sockaddr
*addr
= p
;
7382 int err
= 0, skip_mac_1
= 0;
7384 if (!is_valid_ether_addr(addr
->sa_data
))
7387 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
7389 if (!netif_running(dev
))
7392 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) {
7393 u32 addr0_high
, addr0_low
, addr1_high
, addr1_low
;
7395 addr0_high
= tr32(MAC_ADDR_0_HIGH
);
7396 addr0_low
= tr32(MAC_ADDR_0_LOW
);
7397 addr1_high
= tr32(MAC_ADDR_1_HIGH
);
7398 addr1_low
= tr32(MAC_ADDR_1_LOW
);
7400 /* Skip MAC addr 1 if ASF is using it. */
7401 if ((addr0_high
!= addr1_high
|| addr0_low
!= addr1_low
) &&
7402 !(addr1_high
== 0 && addr1_low
== 0))
7405 spin_lock_bh(&tp
->lock
);
7406 __tg3_set_mac_addr(tp
, skip_mac_1
);
7407 spin_unlock_bh(&tp
->lock
);
7412 /* tp->lock is held. */
7413 static void tg3_set_bdinfo(struct tg3
*tp
, u32 bdinfo_addr
,
7414 dma_addr_t mapping
, u32 maxlen_flags
,
7418 (bdinfo_addr
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
),
7419 ((u64
) mapping
>> 32));
7421 (bdinfo_addr
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
),
7422 ((u64
) mapping
& 0xffffffff));
7424 (bdinfo_addr
+ TG3_BDINFO_MAXLEN_FLAGS
),
7427 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7429 (bdinfo_addr
+ TG3_BDINFO_NIC_ADDR
),
7433 static void __tg3_set_rx_mode(struct net_device
*);
7434 static void __tg3_set_coalesce(struct tg3
*tp
, struct ethtool_coalesce
*ec
)
7438 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)) {
7439 tw32(HOSTCC_TXCOL_TICKS
, ec
->tx_coalesce_usecs
);
7440 tw32(HOSTCC_TXMAX_FRAMES
, ec
->tx_max_coalesced_frames
);
7441 tw32(HOSTCC_TXCOAL_MAXF_INT
, ec
->tx_max_coalesced_frames_irq
);
7443 tw32(HOSTCC_TXCOL_TICKS
, 0);
7444 tw32(HOSTCC_TXMAX_FRAMES
, 0);
7445 tw32(HOSTCC_TXCOAL_MAXF_INT
, 0);
7448 if (!(tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
)) {
7449 tw32(HOSTCC_RXCOL_TICKS
, ec
->rx_coalesce_usecs
);
7450 tw32(HOSTCC_RXMAX_FRAMES
, ec
->rx_max_coalesced_frames
);
7451 tw32(HOSTCC_RXCOAL_MAXF_INT
, ec
->rx_max_coalesced_frames_irq
);
7453 tw32(HOSTCC_RXCOL_TICKS
, 0);
7454 tw32(HOSTCC_RXMAX_FRAMES
, 0);
7455 tw32(HOSTCC_RXCOAL_MAXF_INT
, 0);
7458 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
7459 u32 val
= ec
->stats_block_coalesce_usecs
;
7461 tw32(HOSTCC_RXCOAL_TICK_INT
, ec
->rx_coalesce_usecs_irq
);
7462 tw32(HOSTCC_TXCOAL_TICK_INT
, ec
->tx_coalesce_usecs_irq
);
7464 if (!netif_carrier_ok(tp
->dev
))
7467 tw32(HOSTCC_STAT_COAL_TICKS
, val
);
7470 for (i
= 0; i
< tp
->irq_cnt
- 1; i
++) {
7473 reg
= HOSTCC_RXCOL_TICKS_VEC1
+ i
* 0x18;
7474 tw32(reg
, ec
->rx_coalesce_usecs
);
7475 reg
= HOSTCC_RXMAX_FRAMES_VEC1
+ i
* 0x18;
7476 tw32(reg
, ec
->rx_max_coalesced_frames
);
7477 reg
= HOSTCC_RXCOAL_MAXF_INT_VEC1
+ i
* 0x18;
7478 tw32(reg
, ec
->rx_max_coalesced_frames_irq
);
7480 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
) {
7481 reg
= HOSTCC_TXCOL_TICKS_VEC1
+ i
* 0x18;
7482 tw32(reg
, ec
->tx_coalesce_usecs
);
7483 reg
= HOSTCC_TXMAX_FRAMES_VEC1
+ i
* 0x18;
7484 tw32(reg
, ec
->tx_max_coalesced_frames
);
7485 reg
= HOSTCC_TXCOAL_MAXF_INT_VEC1
+ i
* 0x18;
7486 tw32(reg
, ec
->tx_max_coalesced_frames_irq
);
7490 for (; i
< tp
->irq_max
- 1; i
++) {
7491 tw32(HOSTCC_RXCOL_TICKS_VEC1
+ i
* 0x18, 0);
7492 tw32(HOSTCC_RXMAX_FRAMES_VEC1
+ i
* 0x18, 0);
7493 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1
+ i
* 0x18, 0);
7495 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
) {
7496 tw32(HOSTCC_TXCOL_TICKS_VEC1
+ i
* 0x18, 0);
7497 tw32(HOSTCC_TXMAX_FRAMES_VEC1
+ i
* 0x18, 0);
7498 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1
+ i
* 0x18, 0);
7503 /* tp->lock is held. */
7504 static void tg3_rings_reset(struct tg3
*tp
)
7507 u32 stblk
, txrcb
, rxrcb
, limit
;
7508 struct tg3_napi
*tnapi
= &tp
->napi
[0];
7510 /* Disable all transmit rings but the first. */
7511 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7512 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
* 16;
7513 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
7514 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
* 2;
7516 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
;
7518 for (txrcb
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
;
7519 txrcb
< limit
; txrcb
+= TG3_BDINFO_SIZE
)
7520 tg3_write_mem(tp
, txrcb
+ TG3_BDINFO_MAXLEN_FLAGS
,
7521 BDINFO_FLAGS_DISABLED
);
7524 /* Disable all receive return rings but the first. */
7525 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
)
7526 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
* 17;
7527 else if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7528 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
* 16;
7529 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
7530 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
7531 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
* 4;
7533 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
;
7535 for (rxrcb
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
;
7536 rxrcb
< limit
; rxrcb
+= TG3_BDINFO_SIZE
)
7537 tg3_write_mem(tp
, rxrcb
+ TG3_BDINFO_MAXLEN_FLAGS
,
7538 BDINFO_FLAGS_DISABLED
);
7540 /* Disable interrupts */
7541 tw32_mailbox_f(tp
->napi
[0].int_mbox
, 1);
7543 /* Zero mailbox registers. */
7544 if (tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSIX
) {
7545 for (i
= 1; i
< TG3_IRQ_MAX_VECS
; i
++) {
7546 tp
->napi
[i
].tx_prod
= 0;
7547 tp
->napi
[i
].tx_cons
= 0;
7548 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
7549 tw32_mailbox(tp
->napi
[i
].prodmbox
, 0);
7550 tw32_rx_mbox(tp
->napi
[i
].consmbox
, 0);
7551 tw32_mailbox_f(tp
->napi
[i
].int_mbox
, 1);
7553 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
))
7554 tw32_mailbox(tp
->napi
[0].prodmbox
, 0);
7556 tp
->napi
[0].tx_prod
= 0;
7557 tp
->napi
[0].tx_cons
= 0;
7558 tw32_mailbox(tp
->napi
[0].prodmbox
, 0);
7559 tw32_rx_mbox(tp
->napi
[0].consmbox
, 0);
7562 /* Make sure the NIC-based send BD rings are disabled. */
7563 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
7564 u32 mbox
= MAILBOX_SNDNIC_PROD_IDX_0
+ TG3_64BIT_REG_LOW
;
7565 for (i
= 0; i
< 16; i
++)
7566 tw32_tx_mbox(mbox
+ i
* 8, 0);
7569 txrcb
= NIC_SRAM_SEND_RCB
;
7570 rxrcb
= NIC_SRAM_RCV_RET_RCB
;
7572 /* Clear status block in ram. */
7573 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
7575 /* Set status block DMA address */
7576 tw32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
7577 ((u64
) tnapi
->status_mapping
>> 32));
7578 tw32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
7579 ((u64
) tnapi
->status_mapping
& 0xffffffff));
7581 if (tnapi
->tx_ring
) {
7582 tg3_set_bdinfo(tp
, txrcb
, tnapi
->tx_desc_mapping
,
7583 (TG3_TX_RING_SIZE
<<
7584 BDINFO_FLAGS_MAXLEN_SHIFT
),
7585 NIC_SRAM_TX_BUFFER_DESC
);
7586 txrcb
+= TG3_BDINFO_SIZE
;
7589 if (tnapi
->rx_rcb
) {
7590 tg3_set_bdinfo(tp
, rxrcb
, tnapi
->rx_rcb_mapping
,
7591 (TG3_RX_RCB_RING_SIZE(tp
) <<
7592 BDINFO_FLAGS_MAXLEN_SHIFT
), 0);
7593 rxrcb
+= TG3_BDINFO_SIZE
;
7596 stblk
= HOSTCC_STATBLCK_RING1
;
7598 for (i
= 1, tnapi
++; i
< tp
->irq_cnt
; i
++, tnapi
++) {
7599 u64 mapping
= (u64
)tnapi
->status_mapping
;
7600 tw32(stblk
+ TG3_64BIT_REG_HIGH
, mapping
>> 32);
7601 tw32(stblk
+ TG3_64BIT_REG_LOW
, mapping
& 0xffffffff);
7603 /* Clear status block in ram. */
7604 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
7606 if (tnapi
->tx_ring
) {
7607 tg3_set_bdinfo(tp
, txrcb
, tnapi
->tx_desc_mapping
,
7608 (TG3_TX_RING_SIZE
<<
7609 BDINFO_FLAGS_MAXLEN_SHIFT
),
7610 NIC_SRAM_TX_BUFFER_DESC
);
7611 txrcb
+= TG3_BDINFO_SIZE
;
7614 tg3_set_bdinfo(tp
, rxrcb
, tnapi
->rx_rcb_mapping
,
7615 (TG3_RX_RCB_RING_SIZE(tp
) <<
7616 BDINFO_FLAGS_MAXLEN_SHIFT
), 0);
7619 rxrcb
+= TG3_BDINFO_SIZE
;
7623 /* tp->lock is held. */
7624 static int tg3_reset_hw(struct tg3
*tp
, int reset_phy
)
7626 u32 val
, rdmac_mode
;
7628 struct tg3_rx_prodring_set
*tpr
= &tp
->prodring
[0];
7630 tg3_disable_ints(tp
);
7634 tg3_write_sig_pre_reset(tp
, RESET_KIND_INIT
);
7636 if (tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
)
7637 tg3_abort_hw(tp
, 1);
7642 err
= tg3_chip_reset(tp
);
7646 tg3_write_sig_legacy(tp
, RESET_KIND_INIT
);
7648 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
) {
7649 val
= tr32(TG3_CPMU_CTRL
);
7650 val
&= ~(CPMU_CTRL_LINK_AWARE_MODE
| CPMU_CTRL_LINK_IDLE_MODE
);
7651 tw32(TG3_CPMU_CTRL
, val
);
7653 val
= tr32(TG3_CPMU_LSPD_10MB_CLK
);
7654 val
&= ~CPMU_LSPD_10MB_MACCLK_MASK
;
7655 val
|= CPMU_LSPD_10MB_MACCLK_6_25
;
7656 tw32(TG3_CPMU_LSPD_10MB_CLK
, val
);
7658 val
= tr32(TG3_CPMU_LNK_AWARE_PWRMD
);
7659 val
&= ~CPMU_LNK_AWARE_MACCLK_MASK
;
7660 val
|= CPMU_LNK_AWARE_MACCLK_6_25
;
7661 tw32(TG3_CPMU_LNK_AWARE_PWRMD
, val
);
7663 val
= tr32(TG3_CPMU_HST_ACC
);
7664 val
&= ~CPMU_HST_ACC_MACCLK_MASK
;
7665 val
|= CPMU_HST_ACC_MACCLK_6_25
;
7666 tw32(TG3_CPMU_HST_ACC
, val
);
7669 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
) {
7670 val
= tr32(PCIE_PWR_MGMT_THRESH
) & ~PCIE_PWR_MGMT_L1_THRESH_MSK
;
7671 val
|= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN
|
7672 PCIE_PWR_MGMT_L1_THRESH_4MS
;
7673 tw32(PCIE_PWR_MGMT_THRESH
, val
);
7675 val
= tr32(TG3_PCIE_EIDLE_DELAY
) & ~TG3_PCIE_EIDLE_DELAY_MASK
;
7676 tw32(TG3_PCIE_EIDLE_DELAY
, val
| TG3_PCIE_EIDLE_DELAY_13_CLKS
);
7678 tw32(TG3_CORR_ERR_STAT
, TG3_CORR_ERR_STAT_CLEAR
);
7680 val
= tr32(TG3_PCIE_LNKCTL
) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN
;
7681 tw32(TG3_PCIE_LNKCTL
, val
| TG3_PCIE_LNKCTL_L1_PLL_PD_DIS
);
7684 if (tp
->tg3_flags3
& TG3_FLG3_L1PLLPD_EN
) {
7685 u32 grc_mode
= tr32(GRC_MODE
);
7687 /* Access the lower 1K of PL PCIE block registers. */
7688 val
= grc_mode
& ~GRC_MODE_PCIE_PORT_MASK
;
7689 tw32(GRC_MODE
, val
| GRC_MODE_PCIE_PL_SEL
);
7691 val
= tr32(TG3_PCIE_TLDLPL_PORT
+ TG3_PCIE_PL_LO_PHYCTL1
);
7692 tw32(TG3_PCIE_TLDLPL_PORT
+ TG3_PCIE_PL_LO_PHYCTL1
,
7693 val
| TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN
);
7695 tw32(GRC_MODE
, grc_mode
);
7698 if (tp
->pci_chip_rev_id
== CHIPREV_ID_57765_A0
) {
7699 u32 grc_mode
= tr32(GRC_MODE
);
7701 /* Access the lower 1K of PL PCIE block registers. */
7702 val
= grc_mode
& ~GRC_MODE_PCIE_PORT_MASK
;
7703 tw32(GRC_MODE
, val
| GRC_MODE_PCIE_PL_SEL
);
7705 val
= tr32(TG3_PCIE_TLDLPL_PORT
+ TG3_PCIE_PL_LO_PHYCTL5
);
7706 tw32(TG3_PCIE_TLDLPL_PORT
+ TG3_PCIE_PL_LO_PHYCTL5
,
7707 val
| TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ
);
7709 tw32(GRC_MODE
, grc_mode
);
7711 val
= tr32(TG3_CPMU_LSPD_10MB_CLK
);
7712 val
&= ~CPMU_LSPD_10MB_MACCLK_MASK
;
7713 val
|= CPMU_LSPD_10MB_MACCLK_6_25
;
7714 tw32(TG3_CPMU_LSPD_10MB_CLK
, val
);
7717 /* This works around an issue with Athlon chipsets on
7718 * B3 tigon3 silicon. This bit has no effect on any
7719 * other revision. But do not set this on PCI Express
7720 * chips and don't even touch the clocks if the CPMU is present.
7722 if (!(tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
)) {
7723 if (!(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
7724 tp
->pci_clock_ctrl
|= CLOCK_CTRL_DELAY_PCI_GRANT
;
7725 tw32_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
);
7728 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
&&
7729 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
)) {
7730 val
= tr32(TG3PCI_PCISTATE
);
7731 val
|= PCISTATE_RETRY_SAME_DMA
;
7732 tw32(TG3PCI_PCISTATE
, val
);
7735 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
7736 /* Allow reads and writes to the
7737 * APE register and memory space.
7739 val
= tr32(TG3PCI_PCISTATE
);
7740 val
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
7741 PCISTATE_ALLOW_APE_SHMEM_WR
|
7742 PCISTATE_ALLOW_APE_PSPACE_WR
;
7743 tw32(TG3PCI_PCISTATE
, val
);
7746 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5704_BX
) {
7747 /* Enable some hw fixes. */
7748 val
= tr32(TG3PCI_MSI_DATA
);
7749 val
|= (1 << 26) | (1 << 28) | (1 << 29);
7750 tw32(TG3PCI_MSI_DATA
, val
);
7753 /* Descriptor ring init may make accesses to the
7754 * NIC SRAM area to setup the TX descriptors, so we
7755 * can only do this after the hardware has been
7756 * successfully reset.
7758 err
= tg3_init_rings(tp
);
7762 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
7763 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
) {
7764 val
= tr32(TG3PCI_DMA_RW_CTRL
) &
7765 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT
;
7766 if (tp
->pci_chip_rev_id
== CHIPREV_ID_57765_A0
)
7767 val
&= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK
;
7768 tw32(TG3PCI_DMA_RW_CTRL
, val
| tp
->dma_rwctrl
);
7769 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5784
&&
7770 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5761
) {
7771 /* This value is determined during the probe time DMA
7772 * engine test, tg3_test_dma.
7774 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
7777 tp
->grc_mode
&= ~(GRC_MODE_HOST_SENDBDS
|
7778 GRC_MODE_4X_NIC_SEND_RINGS
|
7779 GRC_MODE_NO_TX_PHDR_CSUM
|
7780 GRC_MODE_NO_RX_PHDR_CSUM
);
7781 tp
->grc_mode
|= GRC_MODE_HOST_SENDBDS
;
7783 /* Pseudo-header checksum is done by hardware logic and not
7784 * the offload processers, so make the chip do the pseudo-
7785 * header checksums on receive. For transmit it is more
7786 * convenient to do the pseudo-header checksum in software
7787 * as Linux does that on transmit for us in all cases.
7789 tp
->grc_mode
|= GRC_MODE_NO_TX_PHDR_CSUM
;
7793 (GRC_MODE_IRQ_ON_MAC_ATTN
| GRC_MODE_HOST_STACKUP
));
7795 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7796 val
= tr32(GRC_MISC_CFG
);
7798 val
|= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT
);
7799 tw32(GRC_MISC_CFG
, val
);
7801 /* Initialize MBUF/DESC pool. */
7802 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
7804 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5705
) {
7805 tw32(BUFMGR_MB_POOL_ADDR
, NIC_SRAM_MBUF_POOL_BASE
);
7806 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
7807 tw32(BUFMGR_MB_POOL_SIZE
, NIC_SRAM_MBUF_POOL_SIZE64
);
7809 tw32(BUFMGR_MB_POOL_SIZE
, NIC_SRAM_MBUF_POOL_SIZE96
);
7810 tw32(BUFMGR_DMA_DESC_POOL_ADDR
, NIC_SRAM_DMA_DESC_POOL_BASE
);
7811 tw32(BUFMGR_DMA_DESC_POOL_SIZE
, NIC_SRAM_DMA_DESC_POOL_SIZE
);
7812 } else if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) {
7815 fw_len
= tp
->fw_len
;
7816 fw_len
= (fw_len
+ (0x80 - 1)) & ~(0x80 - 1);
7817 tw32(BUFMGR_MB_POOL_ADDR
,
7818 NIC_SRAM_MBUF_POOL_BASE5705
+ fw_len
);
7819 tw32(BUFMGR_MB_POOL_SIZE
,
7820 NIC_SRAM_MBUF_POOL_SIZE5705
- fw_len
- 0xa00);
7823 if (tp
->dev
->mtu
<= ETH_DATA_LEN
) {
7824 tw32(BUFMGR_MB_RDMA_LOW_WATER
,
7825 tp
->bufmgr_config
.mbuf_read_dma_low_water
);
7826 tw32(BUFMGR_MB_MACRX_LOW_WATER
,
7827 tp
->bufmgr_config
.mbuf_mac_rx_low_water
);
7828 tw32(BUFMGR_MB_HIGH_WATER
,
7829 tp
->bufmgr_config
.mbuf_high_water
);
7831 tw32(BUFMGR_MB_RDMA_LOW_WATER
,
7832 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
);
7833 tw32(BUFMGR_MB_MACRX_LOW_WATER
,
7834 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
);
7835 tw32(BUFMGR_MB_HIGH_WATER
,
7836 tp
->bufmgr_config
.mbuf_high_water_jumbo
);
7838 tw32(BUFMGR_DMA_LOW_WATER
,
7839 tp
->bufmgr_config
.dma_low_water
);
7840 tw32(BUFMGR_DMA_HIGH_WATER
,
7841 tp
->bufmgr_config
.dma_high_water
);
7843 tw32(BUFMGR_MODE
, BUFMGR_MODE_ENABLE
| BUFMGR_MODE_ATTN_ENABLE
);
7844 for (i
= 0; i
< 2000; i
++) {
7845 if (tr32(BUFMGR_MODE
) & BUFMGR_MODE_ENABLE
)
7850 netdev_err(tp
->dev
, "%s cannot enable BUFMGR\n", __func__
);
7854 /* Setup replenish threshold. */
7855 val
= tp
->rx_pending
/ 8;
7858 else if (val
> tp
->rx_std_max_post
)
7859 val
= tp
->rx_std_max_post
;
7860 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
7861 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5906_A1
)
7862 tw32(ISO_PKT_TX
, (tr32(ISO_PKT_TX
) & ~0x3) | 0x2);
7864 if (val
> (TG3_RX_INTERNAL_RING_SZ_5906
/ 2))
7865 val
= TG3_RX_INTERNAL_RING_SZ_5906
/ 2;
7868 tw32(RCVBDI_STD_THRESH
, val
);
7870 /* Initialize TG3_BDINFO's at:
7871 * RCVDBDI_STD_BD: standard eth size rx ring
7872 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7873 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7876 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7877 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7878 * ring attribute flags
7879 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7881 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7882 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7884 * The size of each ring is fixed in the firmware, but the location is
7887 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
7888 ((u64
) tpr
->rx_std_mapping
>> 32));
7889 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
7890 ((u64
) tpr
->rx_std_mapping
& 0xffffffff));
7891 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5717
)
7892 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_NIC_ADDR
,
7893 NIC_SRAM_RX_BUFFER_DESC
);
7895 /* Disable the mini ring */
7896 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7897 tw32(RCVDBDI_MINI_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
7898 BDINFO_FLAGS_DISABLED
);
7900 /* Program the jumbo buffer descriptor ring control
7901 * blocks on those devices that have them.
7903 if ((tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) &&
7904 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
7905 /* Setup replenish threshold. */
7906 tw32(RCVBDI_JUMBO_THRESH
, tp
->rx_jumbo_pending
/ 8);
7908 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
) {
7909 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
7910 ((u64
) tpr
->rx_jmb_mapping
>> 32));
7911 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
7912 ((u64
) tpr
->rx_jmb_mapping
& 0xffffffff));
7913 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
7914 (RX_JUMBO_MAX_SIZE
<< BDINFO_FLAGS_MAXLEN_SHIFT
) |
7915 BDINFO_FLAGS_USE_EXT_RECV
);
7916 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5717
)
7917 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_NIC_ADDR
,
7918 NIC_SRAM_RX_JUMBO_BUFFER_DESC
);
7920 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
7921 BDINFO_FLAGS_DISABLED
);
7924 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
7925 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
7926 val
= (RX_STD_MAX_SIZE_5705
<< BDINFO_FLAGS_MAXLEN_SHIFT
) |
7927 (TG3_RX_STD_DMA_SZ
<< 2);
7929 val
= TG3_RX_STD_DMA_SZ
<< BDINFO_FLAGS_MAXLEN_SHIFT
;
7931 val
= RX_STD_MAX_SIZE_5705
<< BDINFO_FLAGS_MAXLEN_SHIFT
;
7933 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_MAXLEN_FLAGS
, val
);
7935 tpr
->rx_std_prod_idx
= tp
->rx_pending
;
7936 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
, tpr
->rx_std_prod_idx
);
7938 tpr
->rx_jmb_prod_idx
= (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
) ?
7939 tp
->rx_jumbo_pending
: 0;
7940 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG
, tpr
->rx_jmb_prod_idx
);
7942 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
7943 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
) {
7944 tw32(STD_REPLENISH_LWM
, 32);
7945 tw32(JMB_REPLENISH_LWM
, 16);
7948 tg3_rings_reset(tp
);
7950 /* Initialize MAC address and backoff seed. */
7951 __tg3_set_mac_addr(tp
, 0);
7953 /* MTU + ethernet header + FCS + optional VLAN tag */
7954 tw32(MAC_RX_MTU_SIZE
,
7955 tp
->dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+ VLAN_HLEN
);
7957 /* The slot time is changed by tg3_setup_phy if we
7958 * run at gigabit with half duplex.
7960 tw32(MAC_TX_LENGTHS
,
7961 (2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
7962 (6 << TX_LENGTHS_IPG_SHIFT
) |
7963 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
));
7965 /* Receive rules. */
7966 tw32(MAC_RCV_RULE_CFG
, RCV_RULE_CFG_DEFAULT_CLASS
);
7967 tw32(RCVLPC_CONFIG
, 0x0181);
7969 /* Calculate RDMAC_MODE setting early, we need it to determine
7970 * the RCVLPC_STATE_ENABLE mask.
7972 rdmac_mode
= (RDMAC_MODE_ENABLE
| RDMAC_MODE_TGTABORT_ENAB
|
7973 RDMAC_MODE_MSTABORT_ENAB
| RDMAC_MODE_PARITYERR_ENAB
|
7974 RDMAC_MODE_ADDROFLOW_ENAB
| RDMAC_MODE_FIFOOFLOW_ENAB
|
7975 RDMAC_MODE_FIFOURUN_ENAB
| RDMAC_MODE_FIFOOREAD_ENAB
|
7976 RDMAC_MODE_LNGREAD_ENAB
);
7978 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
)
7979 rdmac_mode
|= RDMAC_MODE_MULT_DMA_RD_DIS
;
7981 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
7982 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
7983 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
7984 rdmac_mode
|= RDMAC_MODE_BD_SBD_CRPT_ENAB
|
7985 RDMAC_MODE_MBUF_RBD_CRPT_ENAB
|
7986 RDMAC_MODE_MBUF_SBD_CRPT_ENAB
;
7988 /* If statement applies to 5705 and 5750 PCI devices only */
7989 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
7990 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) ||
7991 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
)) {
7992 if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
&&
7993 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
7994 rdmac_mode
|= RDMAC_MODE_FIFO_SIZE_128
;
7995 } else if (!(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
) &&
7996 !(tp
->tg3_flags2
& TG3_FLG2_IS_5788
)) {
7997 rdmac_mode
|= RDMAC_MODE_FIFO_LONG_BURST
;
8001 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)
8002 rdmac_mode
|= RDMAC_MODE_FIFO_LONG_BURST
;
8004 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
8005 rdmac_mode
|= RDMAC_MODE_IPV4_LSO_EN
;
8007 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
) ||
8008 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
8009 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
8010 rdmac_mode
|= RDMAC_MODE_IPV6_LSO_EN
;
8012 /* Receive/send statistics. */
8013 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
8014 val
= tr32(RCVLPC_STATS_ENABLE
);
8015 val
&= ~RCVLPC_STATSENAB_DACK_FIX
;
8016 tw32(RCVLPC_STATS_ENABLE
, val
);
8017 } else if ((rdmac_mode
& RDMAC_MODE_FIFO_SIZE_128
) &&
8018 (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
8019 val
= tr32(RCVLPC_STATS_ENABLE
);
8020 val
&= ~RCVLPC_STATSENAB_LNGBRST_RFIX
;
8021 tw32(RCVLPC_STATS_ENABLE
, val
);
8023 tw32(RCVLPC_STATS_ENABLE
, 0xffffff);
8025 tw32(RCVLPC_STATSCTRL
, RCVLPC_STATSCTRL_ENABLE
);
8026 tw32(SNDDATAI_STATSENAB
, 0xffffff);
8027 tw32(SNDDATAI_STATSCTRL
,
8028 (SNDDATAI_SCTRL_ENABLE
|
8029 SNDDATAI_SCTRL_FASTUPD
));
8031 /* Setup host coalescing engine. */
8032 tw32(HOSTCC_MODE
, 0);
8033 for (i
= 0; i
< 2000; i
++) {
8034 if (!(tr32(HOSTCC_MODE
) & HOSTCC_MODE_ENABLE
))
8039 __tg3_set_coalesce(tp
, &tp
->coal
);
8041 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
8042 /* Status/statistics block address. See tg3_timer,
8043 * the tg3_periodic_fetch_stats call there, and
8044 * tg3_get_stats to see how this works for 5705/5750 chips.
8046 tw32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
8047 ((u64
) tp
->stats_mapping
>> 32));
8048 tw32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
8049 ((u64
) tp
->stats_mapping
& 0xffffffff));
8050 tw32(HOSTCC_STATS_BLK_NIC_ADDR
, NIC_SRAM_STATS_BLK
);
8052 tw32(HOSTCC_STATUS_BLK_NIC_ADDR
, NIC_SRAM_STATUS_BLK
);
8054 /* Clear statistics and status block memory areas */
8055 for (i
= NIC_SRAM_STATS_BLK
;
8056 i
< NIC_SRAM_STATUS_BLK
+ TG3_HW_STATUS_SIZE
;
8058 tg3_write_mem(tp
, i
, 0);
8063 tw32(HOSTCC_MODE
, HOSTCC_MODE_ENABLE
| tp
->coalesce_mode
);
8065 tw32(RCVCC_MODE
, RCVCC_MODE_ENABLE
| RCVCC_MODE_ATTN_ENABLE
);
8066 tw32(RCVLPC_MODE
, RCVLPC_MODE_ENABLE
);
8067 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
8068 tw32(RCVLSC_MODE
, RCVLSC_MODE_ENABLE
| RCVLSC_MODE_ATTN_ENABLE
);
8070 if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) {
8071 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
8072 /* reset to prevent losing 1st rx packet intermittently */
8073 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
8077 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
8078 tp
->mac_mode
&= MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
;
8081 tp
->mac_mode
|= MAC_MODE_TXSTAT_ENABLE
| MAC_MODE_RXSTAT_ENABLE
|
8082 MAC_MODE_TDE_ENABLE
| MAC_MODE_RDE_ENABLE
| MAC_MODE_FHDE_ENABLE
;
8083 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
8084 !(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
8085 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
)
8086 tp
->mac_mode
|= MAC_MODE_LINK_POLARITY
;
8087 tw32_f(MAC_MODE
, tp
->mac_mode
| MAC_MODE_RXSTAT_CLEAR
| MAC_MODE_TXSTAT_CLEAR
);
8090 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8091 * If TG3_FLG2_IS_NIC is zero, we should read the
8092 * register to preserve the GPIO settings for LOMs. The GPIOs,
8093 * whether used as inputs or outputs, are set by boot code after
8096 if (!(tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)) {
8099 gpio_mask
= GRC_LCLCTRL_GPIO_OE0
| GRC_LCLCTRL_GPIO_OE1
|
8100 GRC_LCLCTRL_GPIO_OE2
| GRC_LCLCTRL_GPIO_OUTPUT0
|
8101 GRC_LCLCTRL_GPIO_OUTPUT1
| GRC_LCLCTRL_GPIO_OUTPUT2
;
8103 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
8104 gpio_mask
|= GRC_LCLCTRL_GPIO_OE3
|
8105 GRC_LCLCTRL_GPIO_OUTPUT3
;
8107 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
8108 gpio_mask
|= GRC_LCLCTRL_GPIO_UART_SEL
;
8110 tp
->grc_local_ctrl
&= ~gpio_mask
;
8111 tp
->grc_local_ctrl
|= tr32(GRC_LOCAL_CTRL
) & gpio_mask
;
8113 /* GPIO1 must be driven high for eeprom write protect */
8114 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
)
8115 tp
->grc_local_ctrl
|= (GRC_LCLCTRL_GPIO_OE1
|
8116 GRC_LCLCTRL_GPIO_OUTPUT1
);
8118 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
8121 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
) {
8122 val
= tr32(MSGINT_MODE
);
8123 val
|= MSGINT_MODE_MULTIVEC_EN
| MSGINT_MODE_ENABLE
;
8124 tw32(MSGINT_MODE
, val
);
8127 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
8128 tw32_f(DMAC_MODE
, DMAC_MODE_ENABLE
);
8132 val
= (WDMAC_MODE_ENABLE
| WDMAC_MODE_TGTABORT_ENAB
|
8133 WDMAC_MODE_MSTABORT_ENAB
| WDMAC_MODE_PARITYERR_ENAB
|
8134 WDMAC_MODE_ADDROFLOW_ENAB
| WDMAC_MODE_FIFOOFLOW_ENAB
|
8135 WDMAC_MODE_FIFOURUN_ENAB
| WDMAC_MODE_FIFOOREAD_ENAB
|
8136 WDMAC_MODE_LNGREAD_ENAB
);
8138 /* If statement applies to 5705 and 5750 PCI devices only */
8139 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
8140 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) ||
8141 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
) {
8142 if ((tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) &&
8143 (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A1
||
8144 tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A2
)) {
8146 } else if (!(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
) &&
8147 !(tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
8148 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)) {
8149 val
|= WDMAC_MODE_RX_ACCEL
;
8153 /* Enable host coalescing bug fix */
8154 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
8155 val
|= WDMAC_MODE_STATUS_TAG_FIX
;
8157 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
8158 val
|= WDMAC_MODE_BURST_ALL_DATA
;
8160 tw32_f(WDMAC_MODE
, val
);
8163 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
8166 pci_read_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
8168 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
) {
8169 pcix_cmd
&= ~PCI_X_CMD_MAX_READ
;
8170 pcix_cmd
|= PCI_X_CMD_READ_2K
;
8171 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
8172 pcix_cmd
&= ~(PCI_X_CMD_MAX_SPLIT
| PCI_X_CMD_MAX_READ
);
8173 pcix_cmd
|= PCI_X_CMD_READ_2K
;
8175 pci_write_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
8179 tw32_f(RDMAC_MODE
, rdmac_mode
);
8182 tw32(RCVDCC_MODE
, RCVDCC_MODE_ENABLE
| RCVDCC_MODE_ATTN_ENABLE
);
8183 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
8184 tw32(MBFREE_MODE
, MBFREE_MODE_ENABLE
);
8186 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
8188 SNDDATAC_MODE_ENABLE
| SNDDATAC_MODE_CDELAY
);
8190 tw32(SNDDATAC_MODE
, SNDDATAC_MODE_ENABLE
);
8192 tw32(SNDBDC_MODE
, SNDBDC_MODE_ENABLE
| SNDBDC_MODE_ATTN_ENABLE
);
8193 tw32(RCVBDI_MODE
, RCVBDI_MODE_ENABLE
| RCVBDI_MODE_RCB_ATTN_ENAB
);
8194 tw32(RCVDBDI_MODE
, RCVDBDI_MODE_ENABLE
| RCVDBDI_MODE_INV_RING_SZ
);
8195 tw32(SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
);
8196 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
8197 tw32(SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
| 0x8);
8198 val
= SNDBDI_MODE_ENABLE
| SNDBDI_MODE_ATTN_ENABLE
;
8199 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
8200 val
|= SNDBDI_MODE_MULTI_TXQ_EN
;
8201 tw32(SNDBDI_MODE
, val
);
8202 tw32(SNDBDS_MODE
, SNDBDS_MODE_ENABLE
| SNDBDS_MODE_ATTN_ENABLE
);
8204 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
) {
8205 err
= tg3_load_5701_a0_firmware_fix(tp
);
8210 if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) {
8211 err
= tg3_load_tso_firmware(tp
);
8216 tp
->tx_mode
= TX_MODE_ENABLE
;
8217 if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
8218 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
8219 tp
->tx_mode
|= TX_MODE_MBUF_LOCKUP_FIX
;
8220 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
8223 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
) {
8224 u32 reg
= MAC_RSS_INDIR_TBL_0
;
8225 u8
*ent
= (u8
*)&val
;
8227 /* Setup the indirection table */
8228 for (i
= 0; i
< TG3_RSS_INDIR_TBL_SIZE
; i
++) {
8229 int idx
= i
% sizeof(val
);
8231 ent
[idx
] = i
% (tp
->irq_cnt
- 1);
8232 if (idx
== sizeof(val
) - 1) {
8238 /* Setup the "secret" hash key. */
8239 tw32(MAC_RSS_HASH_KEY_0
, 0x5f865437);
8240 tw32(MAC_RSS_HASH_KEY_1
, 0xe4ac62cc);
8241 tw32(MAC_RSS_HASH_KEY_2
, 0x50103a45);
8242 tw32(MAC_RSS_HASH_KEY_3
, 0x36621985);
8243 tw32(MAC_RSS_HASH_KEY_4
, 0xbf14c0e8);
8244 tw32(MAC_RSS_HASH_KEY_5
, 0x1bc27a1e);
8245 tw32(MAC_RSS_HASH_KEY_6
, 0x84f4b556);
8246 tw32(MAC_RSS_HASH_KEY_7
, 0x094ea6fe);
8247 tw32(MAC_RSS_HASH_KEY_8
, 0x7dda01e7);
8248 tw32(MAC_RSS_HASH_KEY_9
, 0xc04d7481);
8251 tp
->rx_mode
= RX_MODE_ENABLE
;
8252 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
8253 tp
->rx_mode
|= RX_MODE_IPV6_CSUM_ENABLE
;
8255 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_RSS
)
8256 tp
->rx_mode
|= RX_MODE_RSS_ENABLE
|
8257 RX_MODE_RSS_ITBL_HASH_BITS_7
|
8258 RX_MODE_RSS_IPV6_HASH_EN
|
8259 RX_MODE_RSS_TCP_IPV6_HASH_EN
|
8260 RX_MODE_RSS_IPV4_HASH_EN
|
8261 RX_MODE_RSS_TCP_IPV4_HASH_EN
;
8263 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
8266 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
8268 tw32(MAC_MI_STAT
, MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
8269 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
8270 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
8273 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
8276 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
8277 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) &&
8278 !(tp
->tg3_flags2
& TG3_FLG2_SERDES_PREEMPHASIS
)) {
8279 /* Set drive transmission level to 1.2V */
8280 /* only if the signal pre-emphasis bit is not set */
8281 val
= tr32(MAC_SERDES_CFG
);
8284 tw32(MAC_SERDES_CFG
, val
);
8286 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A1
)
8287 tw32(MAC_SERDES_CFG
, 0x616000);
8290 /* Prevent chip from dropping frames when flow control
8293 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
8297 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME
, val
);
8299 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
&&
8300 (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)) {
8301 /* Use hardware link auto-negotiation */
8302 tp
->tg3_flags2
|= TG3_FLG2_HW_AUTONEG
;
8305 if ((tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) &&
8306 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
)) {
8309 tmp
= tr32(SERDES_RX_CTRL
);
8310 tw32(SERDES_RX_CTRL
, tmp
| SERDES_RX_SIG_DETECT
);
8311 tp
->grc_local_ctrl
&= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT
;
8312 tp
->grc_local_ctrl
|= GRC_LCLCTRL_USE_SIG_DETECT
;
8313 tw32(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
8316 if (!(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)) {
8317 if (tp
->link_config
.phy_is_low_power
) {
8318 tp
->link_config
.phy_is_low_power
= 0;
8319 tp
->link_config
.speed
= tp
->link_config
.orig_speed
;
8320 tp
->link_config
.duplex
= tp
->link_config
.orig_duplex
;
8321 tp
->link_config
.autoneg
= tp
->link_config
.orig_autoneg
;
8324 err
= tg3_setup_phy(tp
, 0);
8328 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
8329 !(tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
)) {
8332 /* Clear CRC stats. */
8333 if (!tg3_readphy(tp
, MII_TG3_TEST1
, &tmp
)) {
8334 tg3_writephy(tp
, MII_TG3_TEST1
,
8335 tmp
| MII_TG3_TEST1_CRC_EN
);
8336 tg3_readphy(tp
, 0x14, &tmp
);
8341 __tg3_set_rx_mode(tp
->dev
);
8343 /* Initialize receive rules. */
8344 tw32(MAC_RCV_RULE_0
, 0xc2000000 & RCV_RULE_DISABLE_MASK
);
8345 tw32(MAC_RCV_VALUE_0
, 0xffffffff & RCV_RULE_DISABLE_MASK
);
8346 tw32(MAC_RCV_RULE_1
, 0x86000004 & RCV_RULE_DISABLE_MASK
);
8347 tw32(MAC_RCV_VALUE_1
, 0xffffffff & RCV_RULE_DISABLE_MASK
);
8349 if ((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
8350 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
8354 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)
8358 tw32(MAC_RCV_RULE_15
, 0); tw32(MAC_RCV_VALUE_15
, 0);
8360 tw32(MAC_RCV_RULE_14
, 0); tw32(MAC_RCV_VALUE_14
, 0);
8362 tw32(MAC_RCV_RULE_13
, 0); tw32(MAC_RCV_VALUE_13
, 0);
8364 tw32(MAC_RCV_RULE_12
, 0); tw32(MAC_RCV_VALUE_12
, 0);
8366 tw32(MAC_RCV_RULE_11
, 0); tw32(MAC_RCV_VALUE_11
, 0);
8368 tw32(MAC_RCV_RULE_10
, 0); tw32(MAC_RCV_VALUE_10
, 0);
8370 tw32(MAC_RCV_RULE_9
, 0); tw32(MAC_RCV_VALUE_9
, 0);
8372 tw32(MAC_RCV_RULE_8
, 0); tw32(MAC_RCV_VALUE_8
, 0);
8374 tw32(MAC_RCV_RULE_7
, 0); tw32(MAC_RCV_VALUE_7
, 0);
8376 tw32(MAC_RCV_RULE_6
, 0); tw32(MAC_RCV_VALUE_6
, 0);
8378 tw32(MAC_RCV_RULE_5
, 0); tw32(MAC_RCV_VALUE_5
, 0);
8380 tw32(MAC_RCV_RULE_4
, 0); tw32(MAC_RCV_VALUE_4
, 0);
8382 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8384 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8392 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
8393 /* Write our heartbeat update interval to APE. */
8394 tg3_ape_write32(tp
, TG3_APE_HOST_HEARTBEAT_INT_MS
,
8395 APE_HOST_HEARTBEAT_INT_DISABLE
);
8397 tg3_write_sig_post_reset(tp
, RESET_KIND_INIT
);
8402 /* Called at device open time to get the chip ready for
8403 * packet processing. Invoked with tp->lock held.
8405 static int tg3_init_hw(struct tg3
*tp
, int reset_phy
)
8407 tg3_switch_clocks(tp
);
8409 tw32(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
8411 return tg3_reset_hw(tp
, reset_phy
);
8414 #define TG3_STAT_ADD32(PSTAT, REG) \
8415 do { u32 __val = tr32(REG); \
8416 (PSTAT)->low += __val; \
8417 if ((PSTAT)->low < __val) \
8418 (PSTAT)->high += 1; \
8421 static void tg3_periodic_fetch_stats(struct tg3
*tp
)
8423 struct tg3_hw_stats
*sp
= tp
->hw_stats
;
8425 if (!netif_carrier_ok(tp
->dev
))
8428 TG3_STAT_ADD32(&sp
->tx_octets
, MAC_TX_STATS_OCTETS
);
8429 TG3_STAT_ADD32(&sp
->tx_collisions
, MAC_TX_STATS_COLLISIONS
);
8430 TG3_STAT_ADD32(&sp
->tx_xon_sent
, MAC_TX_STATS_XON_SENT
);
8431 TG3_STAT_ADD32(&sp
->tx_xoff_sent
, MAC_TX_STATS_XOFF_SENT
);
8432 TG3_STAT_ADD32(&sp
->tx_mac_errors
, MAC_TX_STATS_MAC_ERRORS
);
8433 TG3_STAT_ADD32(&sp
->tx_single_collisions
, MAC_TX_STATS_SINGLE_COLLISIONS
);
8434 TG3_STAT_ADD32(&sp
->tx_mult_collisions
, MAC_TX_STATS_MULT_COLLISIONS
);
8435 TG3_STAT_ADD32(&sp
->tx_deferred
, MAC_TX_STATS_DEFERRED
);
8436 TG3_STAT_ADD32(&sp
->tx_excessive_collisions
, MAC_TX_STATS_EXCESSIVE_COL
);
8437 TG3_STAT_ADD32(&sp
->tx_late_collisions
, MAC_TX_STATS_LATE_COL
);
8438 TG3_STAT_ADD32(&sp
->tx_ucast_packets
, MAC_TX_STATS_UCAST
);
8439 TG3_STAT_ADD32(&sp
->tx_mcast_packets
, MAC_TX_STATS_MCAST
);
8440 TG3_STAT_ADD32(&sp
->tx_bcast_packets
, MAC_TX_STATS_BCAST
);
8442 TG3_STAT_ADD32(&sp
->rx_octets
, MAC_RX_STATS_OCTETS
);
8443 TG3_STAT_ADD32(&sp
->rx_fragments
, MAC_RX_STATS_FRAGMENTS
);
8444 TG3_STAT_ADD32(&sp
->rx_ucast_packets
, MAC_RX_STATS_UCAST
);
8445 TG3_STAT_ADD32(&sp
->rx_mcast_packets
, MAC_RX_STATS_MCAST
);
8446 TG3_STAT_ADD32(&sp
->rx_bcast_packets
, MAC_RX_STATS_BCAST
);
8447 TG3_STAT_ADD32(&sp
->rx_fcs_errors
, MAC_RX_STATS_FCS_ERRORS
);
8448 TG3_STAT_ADD32(&sp
->rx_align_errors
, MAC_RX_STATS_ALIGN_ERRORS
);
8449 TG3_STAT_ADD32(&sp
->rx_xon_pause_rcvd
, MAC_RX_STATS_XON_PAUSE_RECVD
);
8450 TG3_STAT_ADD32(&sp
->rx_xoff_pause_rcvd
, MAC_RX_STATS_XOFF_PAUSE_RECVD
);
8451 TG3_STAT_ADD32(&sp
->rx_mac_ctrl_rcvd
, MAC_RX_STATS_MAC_CTRL_RECVD
);
8452 TG3_STAT_ADD32(&sp
->rx_xoff_entered
, MAC_RX_STATS_XOFF_ENTERED
);
8453 TG3_STAT_ADD32(&sp
->rx_frame_too_long_errors
, MAC_RX_STATS_FRAME_TOO_LONG
);
8454 TG3_STAT_ADD32(&sp
->rx_jabbers
, MAC_RX_STATS_JABBERS
);
8455 TG3_STAT_ADD32(&sp
->rx_undersize_packets
, MAC_RX_STATS_UNDERSIZE
);
8457 TG3_STAT_ADD32(&sp
->rxbds_empty
, RCVLPC_NO_RCV_BD_CNT
);
8458 TG3_STAT_ADD32(&sp
->rx_discards
, RCVLPC_IN_DISCARDS_CNT
);
8459 TG3_STAT_ADD32(&sp
->rx_errors
, RCVLPC_IN_ERRORS_CNT
);
8462 static void tg3_timer(unsigned long __opaque
)
8464 struct tg3
*tp
= (struct tg3
*) __opaque
;
8469 spin_lock(&tp
->lock
);
8471 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)) {
8472 /* All of this garbage is because when using non-tagged
8473 * IRQ status the mailbox/status_block protocol the chip
8474 * uses with the cpu is race prone.
8476 if (tp
->napi
[0].hw_status
->status
& SD_STATUS_UPDATED
) {
8477 tw32(GRC_LOCAL_CTRL
,
8478 tp
->grc_local_ctrl
| GRC_LCLCTRL_SETINT
);
8480 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
8481 HOSTCC_MODE_ENABLE
| HOSTCC_MODE_NOW
);
8484 if (!(tr32(WDMAC_MODE
) & WDMAC_MODE_ENABLE
)) {
8485 tp
->tg3_flags2
|= TG3_FLG2_RESTART_TIMER
;
8486 spin_unlock(&tp
->lock
);
8487 schedule_work(&tp
->reset_task
);
8492 /* This part only runs once per second. */
8493 if (!--tp
->timer_counter
) {
8494 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
8495 tg3_periodic_fetch_stats(tp
);
8497 if (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) {
8501 mac_stat
= tr32(MAC_STATUS
);
8504 if (tp
->tg3_flags
& TG3_FLAG_USE_MI_INTERRUPT
) {
8505 if (mac_stat
& MAC_STATUS_MI_INTERRUPT
)
8507 } else if (mac_stat
& MAC_STATUS_LNKSTATE_CHANGED
)
8511 tg3_setup_phy(tp
, 0);
8512 } else if (tp
->tg3_flags
& TG3_FLAG_POLL_SERDES
) {
8513 u32 mac_stat
= tr32(MAC_STATUS
);
8516 if (netif_carrier_ok(tp
->dev
) &&
8517 (mac_stat
& MAC_STATUS_LNKSTATE_CHANGED
)) {
8520 if (! netif_carrier_ok(tp
->dev
) &&
8521 (mac_stat
& (MAC_STATUS_PCS_SYNCED
|
8522 MAC_STATUS_SIGNAL_DET
))) {
8526 if (!tp
->serdes_counter
) {
8529 ~MAC_MODE_PORT_MODE_MASK
));
8531 tw32_f(MAC_MODE
, tp
->mac_mode
);
8534 tg3_setup_phy(tp
, 0);
8536 } else if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)
8537 tg3_serdes_parallel_detect(tp
);
8539 tp
->timer_counter
= tp
->timer_multiplier
;
8542 /* Heartbeat is only sent once every 2 seconds.
8544 * The heartbeat is to tell the ASF firmware that the host
8545 * driver is still alive. In the event that the OS crashes,
8546 * ASF needs to reset the hardware to free up the FIFO space
8547 * that may be filled with rx packets destined for the host.
8548 * If the FIFO is full, ASF will no longer function properly.
8550 * Unintended resets have been reported on real time kernels
8551 * where the timer doesn't run on time. Netpoll will also have
8554 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8555 * to check the ring condition when the heartbeat is expiring
8556 * before doing the reset. This will prevent most unintended
8559 if (!--tp
->asf_counter
) {
8560 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) &&
8561 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
8562 tg3_wait_for_event_ack(tp
);
8564 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
,
8565 FWCMD_NICDRV_ALIVE3
);
8566 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_LEN_MBOX
, 4);
8567 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
,
8568 TG3_FW_UPDATE_TIMEOUT_SEC
);
8570 tg3_generate_fw_event(tp
);
8572 tp
->asf_counter
= tp
->asf_multiplier
;
8575 spin_unlock(&tp
->lock
);
8578 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
8579 add_timer(&tp
->timer
);
8582 static int tg3_request_irq(struct tg3
*tp
, int irq_num
)
8585 unsigned long flags
;
8587 struct tg3_napi
*tnapi
= &tp
->napi
[irq_num
];
8589 if (tp
->irq_cnt
== 1)
8590 name
= tp
->dev
->name
;
8592 name
= &tnapi
->irq_lbl
[0];
8593 snprintf(name
, IFNAMSIZ
, "%s-%d", tp
->dev
->name
, irq_num
);
8594 name
[IFNAMSIZ
-1] = 0;
8597 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI_OR_MSIX
) {
8599 if (tp
->tg3_flags2
& TG3_FLG2_1SHOT_MSI
)
8601 flags
= IRQF_SAMPLE_RANDOM
;
8604 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)
8605 fn
= tg3_interrupt_tagged
;
8606 flags
= IRQF_SHARED
| IRQF_SAMPLE_RANDOM
;
8609 return request_irq(tnapi
->irq_vec
, fn
, flags
, name
, tnapi
);
8612 static int tg3_test_interrupt(struct tg3
*tp
)
8614 struct tg3_napi
*tnapi
= &tp
->napi
[0];
8615 struct net_device
*dev
= tp
->dev
;
8616 int err
, i
, intr_ok
= 0;
8619 if (!netif_running(dev
))
8622 tg3_disable_ints(tp
);
8624 free_irq(tnapi
->irq_vec
, tnapi
);
8627 * Turn off MSI one shot mode. Otherwise this test has no
8628 * observable way to know whether the interrupt was delivered.
8630 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
8631 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
) &&
8632 (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
)) {
8633 val
= tr32(MSGINT_MODE
) | MSGINT_MODE_ONE_SHOT_DISABLE
;
8634 tw32(MSGINT_MODE
, val
);
8637 err
= request_irq(tnapi
->irq_vec
, tg3_test_isr
,
8638 IRQF_SHARED
| IRQF_SAMPLE_RANDOM
, dev
->name
, tnapi
);
8642 tnapi
->hw_status
->status
&= ~SD_STATUS_UPDATED
;
8643 tg3_enable_ints(tp
);
8645 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
8648 for (i
= 0; i
< 5; i
++) {
8649 u32 int_mbox
, misc_host_ctrl
;
8651 int_mbox
= tr32_mailbox(tnapi
->int_mbox
);
8652 misc_host_ctrl
= tr32(TG3PCI_MISC_HOST_CTRL
);
8654 if ((int_mbox
!= 0) ||
8655 (misc_host_ctrl
& MISC_HOST_CTRL_MASK_PCI_INT
)) {
8663 tg3_disable_ints(tp
);
8665 free_irq(tnapi
->irq_vec
, tnapi
);
8667 err
= tg3_request_irq(tp
, 0);
8673 /* Reenable MSI one shot mode. */
8674 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
8675 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
) &&
8676 (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
)) {
8677 val
= tr32(MSGINT_MODE
) & ~MSGINT_MODE_ONE_SHOT_DISABLE
;
8678 tw32(MSGINT_MODE
, val
);
8686 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8687 * successfully restored
8689 static int tg3_test_msi(struct tg3
*tp
)
8694 if (!(tp
->tg3_flags2
& TG3_FLG2_USING_MSI
))
8697 /* Turn off SERR reporting in case MSI terminates with Master
8700 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
8701 pci_write_config_word(tp
->pdev
, PCI_COMMAND
,
8702 pci_cmd
& ~PCI_COMMAND_SERR
);
8704 err
= tg3_test_interrupt(tp
);
8706 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
8711 /* other failures */
8715 /* MSI test failed, go back to INTx mode */
8716 netdev_warn(tp
->dev
, "No interrupt was generated using MSI. Switching "
8717 "to INTx mode. Please report this failure to the PCI "
8718 "maintainer and include system chipset information\n");
8720 free_irq(tp
->napi
[0].irq_vec
, &tp
->napi
[0]);
8722 pci_disable_msi(tp
->pdev
);
8724 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI
;
8725 tp
->napi
[0].irq_vec
= tp
->pdev
->irq
;
8727 err
= tg3_request_irq(tp
, 0);
8731 /* Need to reset the chip because the MSI cycle may have terminated
8732 * with Master Abort.
8734 tg3_full_lock(tp
, 1);
8736 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
8737 err
= tg3_init_hw(tp
, 1);
8739 tg3_full_unlock(tp
);
8742 free_irq(tp
->napi
[0].irq_vec
, &tp
->napi
[0]);
8747 static int tg3_request_firmware(struct tg3
*tp
)
8749 const __be32
*fw_data
;
8751 if (request_firmware(&tp
->fw
, tp
->fw_needed
, &tp
->pdev
->dev
)) {
8752 netdev_err(tp
->dev
, "Failed to load firmware \"%s\"\n",
8757 fw_data
= (void *)tp
->fw
->data
;
8759 /* Firmware blob starts with version numbers, followed by
8760 * start address and _full_ length including BSS sections
8761 * (which must be longer than the actual data, of course
8764 tp
->fw_len
= be32_to_cpu(fw_data
[2]); /* includes bss */
8765 if (tp
->fw_len
< (tp
->fw
->size
- 12)) {
8766 netdev_err(tp
->dev
, "bogus length %d in \"%s\"\n",
8767 tp
->fw_len
, tp
->fw_needed
);
8768 release_firmware(tp
->fw
);
8773 /* We no longer need firmware; we have it. */
8774 tp
->fw_needed
= NULL
;
8778 static bool tg3_enable_msix(struct tg3
*tp
)
8780 int i
, rc
, cpus
= num_online_cpus();
8781 struct msix_entry msix_ent
[tp
->irq_max
];
8784 /* Just fallback to the simpler MSI mode. */
8788 * We want as many rx rings enabled as there are cpus.
8789 * The first MSIX vector only deals with link interrupts, etc,
8790 * so we add one to the number of vectors we are requesting.
8792 tp
->irq_cnt
= min_t(unsigned, cpus
+ 1, tp
->irq_max
);
8794 for (i
= 0; i
< tp
->irq_max
; i
++) {
8795 msix_ent
[i
].entry
= i
;
8796 msix_ent
[i
].vector
= 0;
8799 rc
= pci_enable_msix(tp
->pdev
, msix_ent
, tp
->irq_cnt
);
8801 if (rc
< TG3_RSS_MIN_NUM_MSIX_VECS
)
8803 if (pci_enable_msix(tp
->pdev
, msix_ent
, rc
))
8805 netdev_notice(tp
->dev
, "Requested %d MSI-X vectors, received %d\n",
8810 tp
->tg3_flags3
|= TG3_FLG3_ENABLE_RSS
;
8812 for (i
= 0; i
< tp
->irq_max
; i
++)
8813 tp
->napi
[i
].irq_vec
= msix_ent
[i
].vector
;
8815 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
) {
8816 tp
->tg3_flags3
|= TG3_FLG3_ENABLE_TSS
;
8817 tp
->dev
->real_num_tx_queues
= tp
->irq_cnt
- 1;
8819 tp
->dev
->real_num_tx_queues
= 1;
8824 static void tg3_ints_init(struct tg3
*tp
)
8826 if ((tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSI_OR_MSIX
) &&
8827 !(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)) {
8828 /* All MSI supporting chips should support tagged
8829 * status. Assert that this is the case.
8831 netdev_warn(tp
->dev
,
8832 "MSI without TAGGED_STATUS? Not using MSI\n");
8836 if ((tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSIX
) && tg3_enable_msix(tp
))
8837 tp
->tg3_flags2
|= TG3_FLG2_USING_MSIX
;
8838 else if ((tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSI
) &&
8839 pci_enable_msi(tp
->pdev
) == 0)
8840 tp
->tg3_flags2
|= TG3_FLG2_USING_MSI
;
8842 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI_OR_MSIX
) {
8843 u32 msi_mode
= tr32(MSGINT_MODE
);
8844 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
)
8845 msi_mode
|= MSGINT_MODE_MULTIVEC_EN
;
8846 tw32(MSGINT_MODE
, msi_mode
| MSGINT_MODE_ENABLE
);
8849 if (!(tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
)) {
8851 tp
->napi
[0].irq_vec
= tp
->pdev
->irq
;
8852 tp
->dev
->real_num_tx_queues
= 1;
8856 static void tg3_ints_fini(struct tg3
*tp
)
8858 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
)
8859 pci_disable_msix(tp
->pdev
);
8860 else if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
)
8861 pci_disable_msi(tp
->pdev
);
8862 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI_OR_MSIX
;
8863 tp
->tg3_flags3
&= ~TG3_FLG3_ENABLE_RSS
;
8866 static int tg3_open(struct net_device
*dev
)
8868 struct tg3
*tp
= netdev_priv(dev
);
8871 if (tp
->fw_needed
) {
8872 err
= tg3_request_firmware(tp
);
8873 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
) {
8877 netdev_warn(tp
->dev
, "TSO capability disabled\n");
8878 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_CAPABLE
;
8879 } else if (!(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
8880 netdev_notice(tp
->dev
, "TSO capability restored\n");
8881 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
8885 netif_carrier_off(tp
->dev
);
8887 err
= tg3_set_power_state(tp
, PCI_D0
);
8891 tg3_full_lock(tp
, 0);
8893 tg3_disable_ints(tp
);
8894 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
8896 tg3_full_unlock(tp
);
8899 * Setup interrupts first so we know how
8900 * many NAPI resources to allocate
8904 /* The placement of this call is tied
8905 * to the setup and use of Host TX descriptors.
8907 err
= tg3_alloc_consistent(tp
);
8911 tg3_napi_enable(tp
);
8913 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
8914 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
8915 err
= tg3_request_irq(tp
, i
);
8917 for (i
--; i
>= 0; i
--)
8918 free_irq(tnapi
->irq_vec
, tnapi
);
8926 tg3_full_lock(tp
, 0);
8928 err
= tg3_init_hw(tp
, 1);
8930 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
8933 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)
8934 tp
->timer_offset
= HZ
;
8936 tp
->timer_offset
= HZ
/ 10;
8938 BUG_ON(tp
->timer_offset
> HZ
);
8939 tp
->timer_counter
= tp
->timer_multiplier
=
8940 (HZ
/ tp
->timer_offset
);
8941 tp
->asf_counter
= tp
->asf_multiplier
=
8942 ((HZ
/ tp
->timer_offset
) * 2);
8944 init_timer(&tp
->timer
);
8945 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
8946 tp
->timer
.data
= (unsigned long) tp
;
8947 tp
->timer
.function
= tg3_timer
;
8950 tg3_full_unlock(tp
);
8955 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
8956 err
= tg3_test_msi(tp
);
8959 tg3_full_lock(tp
, 0);
8960 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
8962 tg3_full_unlock(tp
);
8967 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5717
&&
8968 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_57765
&&
8969 (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) &&
8970 (tp
->tg3_flags2
& TG3_FLG2_1SHOT_MSI
)) {
8971 u32 val
= tr32(PCIE_TRANSACTION_CFG
);
8973 tw32(PCIE_TRANSACTION_CFG
,
8974 val
| PCIE_TRANS_CFG_1SHOT_MSI
);
8980 tg3_full_lock(tp
, 0);
8982 add_timer(&tp
->timer
);
8983 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
8984 tg3_enable_ints(tp
);
8986 tg3_full_unlock(tp
);
8988 netif_tx_start_all_queues(dev
);
8993 for (i
= tp
->irq_cnt
- 1; i
>= 0; i
--) {
8994 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
8995 free_irq(tnapi
->irq_vec
, tnapi
);
8999 tg3_napi_disable(tp
);
9000 tg3_free_consistent(tp
);
9007 static struct net_device_stats
*tg3_get_stats(struct net_device
*);
9008 static struct tg3_ethtool_stats
*tg3_get_estats(struct tg3
*);
9010 static int tg3_close(struct net_device
*dev
)
9013 struct tg3
*tp
= netdev_priv(dev
);
9015 tg3_napi_disable(tp
);
9016 cancel_work_sync(&tp
->reset_task
);
9018 netif_tx_stop_all_queues(dev
);
9020 del_timer_sync(&tp
->timer
);
9024 tg3_full_lock(tp
, 1);
9026 tg3_disable_ints(tp
);
9028 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
9030 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
9032 tg3_full_unlock(tp
);
9034 for (i
= tp
->irq_cnt
- 1; i
>= 0; i
--) {
9035 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
9036 free_irq(tnapi
->irq_vec
, tnapi
);
9041 memcpy(&tp
->net_stats_prev
, tg3_get_stats(tp
->dev
),
9042 sizeof(tp
->net_stats_prev
));
9043 memcpy(&tp
->estats_prev
, tg3_get_estats(tp
),
9044 sizeof(tp
->estats_prev
));
9046 tg3_free_consistent(tp
);
9048 tg3_set_power_state(tp
, PCI_D3hot
);
9050 netif_carrier_off(tp
->dev
);
9055 static inline unsigned long get_stat64(tg3_stat64_t
*val
)
9059 #if (BITS_PER_LONG == 32)
9062 ret
= ((u64
)val
->high
<< 32) | ((u64
)val
->low
);
9067 static inline u64
get_estat64(tg3_stat64_t
*val
)
9069 return ((u64
)val
->high
<< 32) | ((u64
)val
->low
);
9072 static unsigned long calc_crc_errors(struct tg3
*tp
)
9074 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
9076 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
9077 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
9078 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
9081 spin_lock_bh(&tp
->lock
);
9082 if (!tg3_readphy(tp
, MII_TG3_TEST1
, &val
)) {
9083 tg3_writephy(tp
, MII_TG3_TEST1
,
9084 val
| MII_TG3_TEST1_CRC_EN
);
9085 tg3_readphy(tp
, 0x14, &val
);
9088 spin_unlock_bh(&tp
->lock
);
9090 tp
->phy_crc_errors
+= val
;
9092 return tp
->phy_crc_errors
;
9095 return get_stat64(&hw_stats
->rx_fcs_errors
);
9098 #define ESTAT_ADD(member) \
9099 estats->member = old_estats->member + \
9100 get_estat64(&hw_stats->member)
9102 static struct tg3_ethtool_stats
*tg3_get_estats(struct tg3
*tp
)
9104 struct tg3_ethtool_stats
*estats
= &tp
->estats
;
9105 struct tg3_ethtool_stats
*old_estats
= &tp
->estats_prev
;
9106 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
9111 ESTAT_ADD(rx_octets
);
9112 ESTAT_ADD(rx_fragments
);
9113 ESTAT_ADD(rx_ucast_packets
);
9114 ESTAT_ADD(rx_mcast_packets
);
9115 ESTAT_ADD(rx_bcast_packets
);
9116 ESTAT_ADD(rx_fcs_errors
);
9117 ESTAT_ADD(rx_align_errors
);
9118 ESTAT_ADD(rx_xon_pause_rcvd
);
9119 ESTAT_ADD(rx_xoff_pause_rcvd
);
9120 ESTAT_ADD(rx_mac_ctrl_rcvd
);
9121 ESTAT_ADD(rx_xoff_entered
);
9122 ESTAT_ADD(rx_frame_too_long_errors
);
9123 ESTAT_ADD(rx_jabbers
);
9124 ESTAT_ADD(rx_undersize_packets
);
9125 ESTAT_ADD(rx_in_length_errors
);
9126 ESTAT_ADD(rx_out_length_errors
);
9127 ESTAT_ADD(rx_64_or_less_octet_packets
);
9128 ESTAT_ADD(rx_65_to_127_octet_packets
);
9129 ESTAT_ADD(rx_128_to_255_octet_packets
);
9130 ESTAT_ADD(rx_256_to_511_octet_packets
);
9131 ESTAT_ADD(rx_512_to_1023_octet_packets
);
9132 ESTAT_ADD(rx_1024_to_1522_octet_packets
);
9133 ESTAT_ADD(rx_1523_to_2047_octet_packets
);
9134 ESTAT_ADD(rx_2048_to_4095_octet_packets
);
9135 ESTAT_ADD(rx_4096_to_8191_octet_packets
);
9136 ESTAT_ADD(rx_8192_to_9022_octet_packets
);
9138 ESTAT_ADD(tx_octets
);
9139 ESTAT_ADD(tx_collisions
);
9140 ESTAT_ADD(tx_xon_sent
);
9141 ESTAT_ADD(tx_xoff_sent
);
9142 ESTAT_ADD(tx_flow_control
);
9143 ESTAT_ADD(tx_mac_errors
);
9144 ESTAT_ADD(tx_single_collisions
);
9145 ESTAT_ADD(tx_mult_collisions
);
9146 ESTAT_ADD(tx_deferred
);
9147 ESTAT_ADD(tx_excessive_collisions
);
9148 ESTAT_ADD(tx_late_collisions
);
9149 ESTAT_ADD(tx_collide_2times
);
9150 ESTAT_ADD(tx_collide_3times
);
9151 ESTAT_ADD(tx_collide_4times
);
9152 ESTAT_ADD(tx_collide_5times
);
9153 ESTAT_ADD(tx_collide_6times
);
9154 ESTAT_ADD(tx_collide_7times
);
9155 ESTAT_ADD(tx_collide_8times
);
9156 ESTAT_ADD(tx_collide_9times
);
9157 ESTAT_ADD(tx_collide_10times
);
9158 ESTAT_ADD(tx_collide_11times
);
9159 ESTAT_ADD(tx_collide_12times
);
9160 ESTAT_ADD(tx_collide_13times
);
9161 ESTAT_ADD(tx_collide_14times
);
9162 ESTAT_ADD(tx_collide_15times
);
9163 ESTAT_ADD(tx_ucast_packets
);
9164 ESTAT_ADD(tx_mcast_packets
);
9165 ESTAT_ADD(tx_bcast_packets
);
9166 ESTAT_ADD(tx_carrier_sense_errors
);
9167 ESTAT_ADD(tx_discards
);
9168 ESTAT_ADD(tx_errors
);
9170 ESTAT_ADD(dma_writeq_full
);
9171 ESTAT_ADD(dma_write_prioq_full
);
9172 ESTAT_ADD(rxbds_empty
);
9173 ESTAT_ADD(rx_discards
);
9174 ESTAT_ADD(rx_errors
);
9175 ESTAT_ADD(rx_threshold_hit
);
9177 ESTAT_ADD(dma_readq_full
);
9178 ESTAT_ADD(dma_read_prioq_full
);
9179 ESTAT_ADD(tx_comp_queue_full
);
9181 ESTAT_ADD(ring_set_send_prod_index
);
9182 ESTAT_ADD(ring_status_update
);
9183 ESTAT_ADD(nic_irqs
);
9184 ESTAT_ADD(nic_avoided_irqs
);
9185 ESTAT_ADD(nic_tx_threshold_hit
);
9190 static struct net_device_stats
*tg3_get_stats(struct net_device
*dev
)
9192 struct tg3
*tp
= netdev_priv(dev
);
9193 struct net_device_stats
*stats
= &tp
->net_stats
;
9194 struct net_device_stats
*old_stats
= &tp
->net_stats_prev
;
9195 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
9200 stats
->rx_packets
= old_stats
->rx_packets
+
9201 get_stat64(&hw_stats
->rx_ucast_packets
) +
9202 get_stat64(&hw_stats
->rx_mcast_packets
) +
9203 get_stat64(&hw_stats
->rx_bcast_packets
);
9205 stats
->tx_packets
= old_stats
->tx_packets
+
9206 get_stat64(&hw_stats
->tx_ucast_packets
) +
9207 get_stat64(&hw_stats
->tx_mcast_packets
) +
9208 get_stat64(&hw_stats
->tx_bcast_packets
);
9210 stats
->rx_bytes
= old_stats
->rx_bytes
+
9211 get_stat64(&hw_stats
->rx_octets
);
9212 stats
->tx_bytes
= old_stats
->tx_bytes
+
9213 get_stat64(&hw_stats
->tx_octets
);
9215 stats
->rx_errors
= old_stats
->rx_errors
+
9216 get_stat64(&hw_stats
->rx_errors
);
9217 stats
->tx_errors
= old_stats
->tx_errors
+
9218 get_stat64(&hw_stats
->tx_errors
) +
9219 get_stat64(&hw_stats
->tx_mac_errors
) +
9220 get_stat64(&hw_stats
->tx_carrier_sense_errors
) +
9221 get_stat64(&hw_stats
->tx_discards
);
9223 stats
->multicast
= old_stats
->multicast
+
9224 get_stat64(&hw_stats
->rx_mcast_packets
);
9225 stats
->collisions
= old_stats
->collisions
+
9226 get_stat64(&hw_stats
->tx_collisions
);
9228 stats
->rx_length_errors
= old_stats
->rx_length_errors
+
9229 get_stat64(&hw_stats
->rx_frame_too_long_errors
) +
9230 get_stat64(&hw_stats
->rx_undersize_packets
);
9232 stats
->rx_over_errors
= old_stats
->rx_over_errors
+
9233 get_stat64(&hw_stats
->rxbds_empty
);
9234 stats
->rx_frame_errors
= old_stats
->rx_frame_errors
+
9235 get_stat64(&hw_stats
->rx_align_errors
);
9236 stats
->tx_aborted_errors
= old_stats
->tx_aborted_errors
+
9237 get_stat64(&hw_stats
->tx_discards
);
9238 stats
->tx_carrier_errors
= old_stats
->tx_carrier_errors
+
9239 get_stat64(&hw_stats
->tx_carrier_sense_errors
);
9241 stats
->rx_crc_errors
= old_stats
->rx_crc_errors
+
9242 calc_crc_errors(tp
);
9244 stats
->rx_missed_errors
= old_stats
->rx_missed_errors
+
9245 get_stat64(&hw_stats
->rx_discards
);
9250 static inline u32
calc_crc(unsigned char *buf
, int len
)
9258 for (j
= 0; j
< len
; j
++) {
9261 for (k
= 0; k
< 8; k
++) {
9274 static void tg3_set_multi(struct tg3
*tp
, unsigned int accept_all
)
9276 /* accept or reject all multicast frames */
9277 tw32(MAC_HASH_REG_0
, accept_all
? 0xffffffff : 0);
9278 tw32(MAC_HASH_REG_1
, accept_all
? 0xffffffff : 0);
9279 tw32(MAC_HASH_REG_2
, accept_all
? 0xffffffff : 0);
9280 tw32(MAC_HASH_REG_3
, accept_all
? 0xffffffff : 0);
9283 static void __tg3_set_rx_mode(struct net_device
*dev
)
9285 struct tg3
*tp
= netdev_priv(dev
);
9288 rx_mode
= tp
->rx_mode
& ~(RX_MODE_PROMISC
|
9289 RX_MODE_KEEP_VLAN_TAG
);
9291 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9294 #if TG3_VLAN_TAG_USED
9296 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
9297 rx_mode
|= RX_MODE_KEEP_VLAN_TAG
;
9299 /* By definition, VLAN is disabled always in this
9302 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
9303 rx_mode
|= RX_MODE_KEEP_VLAN_TAG
;
9306 if (dev
->flags
& IFF_PROMISC
) {
9307 /* Promiscuous mode. */
9308 rx_mode
|= RX_MODE_PROMISC
;
9309 } else if (dev
->flags
& IFF_ALLMULTI
) {
9310 /* Accept all multicast. */
9311 tg3_set_multi(tp
, 1);
9312 } else if (netdev_mc_empty(dev
)) {
9313 /* Reject all multicast. */
9314 tg3_set_multi(tp
, 0);
9316 /* Accept one or more multicast(s). */
9317 struct netdev_hw_addr
*ha
;
9318 u32 mc_filter
[4] = { 0, };
9323 netdev_for_each_mc_addr(ha
, dev
) {
9324 crc
= calc_crc(ha
->addr
, ETH_ALEN
);
9326 regidx
= (bit
& 0x60) >> 5;
9328 mc_filter
[regidx
] |= (1 << bit
);
9331 tw32(MAC_HASH_REG_0
, mc_filter
[0]);
9332 tw32(MAC_HASH_REG_1
, mc_filter
[1]);
9333 tw32(MAC_HASH_REG_2
, mc_filter
[2]);
9334 tw32(MAC_HASH_REG_3
, mc_filter
[3]);
9337 if (rx_mode
!= tp
->rx_mode
) {
9338 tp
->rx_mode
= rx_mode
;
9339 tw32_f(MAC_RX_MODE
, rx_mode
);
9344 static void tg3_set_rx_mode(struct net_device
*dev
)
9346 struct tg3
*tp
= netdev_priv(dev
);
9348 if (!netif_running(dev
))
9351 tg3_full_lock(tp
, 0);
9352 __tg3_set_rx_mode(dev
);
9353 tg3_full_unlock(tp
);
9356 #define TG3_REGDUMP_LEN (32 * 1024)
9358 static int tg3_get_regs_len(struct net_device
*dev
)
9360 return TG3_REGDUMP_LEN
;
9363 static void tg3_get_regs(struct net_device
*dev
,
9364 struct ethtool_regs
*regs
, void *_p
)
9367 struct tg3
*tp
= netdev_priv(dev
);
9373 memset(p
, 0, TG3_REGDUMP_LEN
);
9375 if (tp
->link_config
.phy_is_low_power
)
9378 tg3_full_lock(tp
, 0);
9380 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
9381 #define GET_REG32_LOOP(base,len) \
9382 do { p = (u32 *)(orig_p + (base)); \
9383 for (i = 0; i < len; i += 4) \
9384 __GET_REG32((base) + i); \
9386 #define GET_REG32_1(reg) \
9387 do { p = (u32 *)(orig_p + (reg)); \
9388 __GET_REG32((reg)); \
9391 GET_REG32_LOOP(TG3PCI_VENDOR
, 0xb0);
9392 GET_REG32_LOOP(MAILBOX_INTERRUPT_0
, 0x200);
9393 GET_REG32_LOOP(MAC_MODE
, 0x4f0);
9394 GET_REG32_LOOP(SNDDATAI_MODE
, 0xe0);
9395 GET_REG32_1(SNDDATAC_MODE
);
9396 GET_REG32_LOOP(SNDBDS_MODE
, 0x80);
9397 GET_REG32_LOOP(SNDBDI_MODE
, 0x48);
9398 GET_REG32_1(SNDBDC_MODE
);
9399 GET_REG32_LOOP(RCVLPC_MODE
, 0x20);
9400 GET_REG32_LOOP(RCVLPC_SELLST_BASE
, 0x15c);
9401 GET_REG32_LOOP(RCVDBDI_MODE
, 0x0c);
9402 GET_REG32_LOOP(RCVDBDI_JUMBO_BD
, 0x3c);
9403 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0
, 0x44);
9404 GET_REG32_1(RCVDCC_MODE
);
9405 GET_REG32_LOOP(RCVBDI_MODE
, 0x20);
9406 GET_REG32_LOOP(RCVCC_MODE
, 0x14);
9407 GET_REG32_LOOP(RCVLSC_MODE
, 0x08);
9408 GET_REG32_1(MBFREE_MODE
);
9409 GET_REG32_LOOP(HOSTCC_MODE
, 0x100);
9410 GET_REG32_LOOP(MEMARB_MODE
, 0x10);
9411 GET_REG32_LOOP(BUFMGR_MODE
, 0x58);
9412 GET_REG32_LOOP(RDMAC_MODE
, 0x08);
9413 GET_REG32_LOOP(WDMAC_MODE
, 0x08);
9414 GET_REG32_1(RX_CPU_MODE
);
9415 GET_REG32_1(RX_CPU_STATE
);
9416 GET_REG32_1(RX_CPU_PGMCTR
);
9417 GET_REG32_1(RX_CPU_HWBKPT
);
9418 GET_REG32_1(TX_CPU_MODE
);
9419 GET_REG32_1(TX_CPU_STATE
);
9420 GET_REG32_1(TX_CPU_PGMCTR
);
9421 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0
, 0x110);
9422 GET_REG32_LOOP(FTQ_RESET
, 0x120);
9423 GET_REG32_LOOP(MSGINT_MODE
, 0x0c);
9424 GET_REG32_1(DMAC_MODE
);
9425 GET_REG32_LOOP(GRC_MODE
, 0x4c);
9426 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
)
9427 GET_REG32_LOOP(NVRAM_CMD
, 0x24);
9430 #undef GET_REG32_LOOP
9433 tg3_full_unlock(tp
);
9436 static int tg3_get_eeprom_len(struct net_device
*dev
)
9438 struct tg3
*tp
= netdev_priv(dev
);
9440 return tp
->nvram_size
;
9443 static int tg3_get_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
, u8
*data
)
9445 struct tg3
*tp
= netdev_priv(dev
);
9448 u32 i
, offset
, len
, b_offset
, b_count
;
9451 if (tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
)
9454 if (tp
->link_config
.phy_is_low_power
)
9457 offset
= eeprom
->offset
;
9461 eeprom
->magic
= TG3_EEPROM_MAGIC
;
9464 /* adjustments to start on required 4 byte boundary */
9465 b_offset
= offset
& 3;
9466 b_count
= 4 - b_offset
;
9467 if (b_count
> len
) {
9468 /* i.e. offset=1 len=2 */
9471 ret
= tg3_nvram_read_be32(tp
, offset
-b_offset
, &val
);
9474 memcpy(data
, ((char*)&val
) + b_offset
, b_count
);
9477 eeprom
->len
+= b_count
;
9480 /* read bytes upto the last 4 byte boundary */
9481 pd
= &data
[eeprom
->len
];
9482 for (i
= 0; i
< (len
- (len
& 3)); i
+= 4) {
9483 ret
= tg3_nvram_read_be32(tp
, offset
+ i
, &val
);
9488 memcpy(pd
+ i
, &val
, 4);
9493 /* read last bytes not ending on 4 byte boundary */
9494 pd
= &data
[eeprom
->len
];
9496 b_offset
= offset
+ len
- b_count
;
9497 ret
= tg3_nvram_read_be32(tp
, b_offset
, &val
);
9500 memcpy(pd
, &val
, b_count
);
9501 eeprom
->len
+= b_count
;
9506 static int tg3_nvram_write_block(struct tg3
*tp
, u32 offset
, u32 len
, u8
*buf
);
9508 static int tg3_set_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
, u8
*data
)
9510 struct tg3
*tp
= netdev_priv(dev
);
9512 u32 offset
, len
, b_offset
, odd_len
;
9516 if (tp
->link_config
.phy_is_low_power
)
9519 if ((tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) ||
9520 eeprom
->magic
!= TG3_EEPROM_MAGIC
)
9523 offset
= eeprom
->offset
;
9526 if ((b_offset
= (offset
& 3))) {
9527 /* adjustments to start on required 4 byte boundary */
9528 ret
= tg3_nvram_read_be32(tp
, offset
-b_offset
, &start
);
9539 /* adjustments to end on required 4 byte boundary */
9541 len
= (len
+ 3) & ~3;
9542 ret
= tg3_nvram_read_be32(tp
, offset
+len
-4, &end
);
9548 if (b_offset
|| odd_len
) {
9549 buf
= kmalloc(len
, GFP_KERNEL
);
9553 memcpy(buf
, &start
, 4);
9555 memcpy(buf
+len
-4, &end
, 4);
9556 memcpy(buf
+ b_offset
, data
, eeprom
->len
);
9559 ret
= tg3_nvram_write_block(tp
, offset
, len
, buf
);
9567 static int tg3_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
9569 struct tg3
*tp
= netdev_priv(dev
);
9571 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9572 struct phy_device
*phydev
;
9573 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
9575 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
9576 return phy_ethtool_gset(phydev
, cmd
);
9579 cmd
->supported
= (SUPPORTED_Autoneg
);
9581 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
))
9582 cmd
->supported
|= (SUPPORTED_1000baseT_Half
|
9583 SUPPORTED_1000baseT_Full
);
9585 if (!(tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)) {
9586 cmd
->supported
|= (SUPPORTED_100baseT_Half
|
9587 SUPPORTED_100baseT_Full
|
9588 SUPPORTED_10baseT_Half
|
9589 SUPPORTED_10baseT_Full
|
9591 cmd
->port
= PORT_TP
;
9593 cmd
->supported
|= SUPPORTED_FIBRE
;
9594 cmd
->port
= PORT_FIBRE
;
9597 cmd
->advertising
= tp
->link_config
.advertising
;
9598 if (netif_running(dev
)) {
9599 cmd
->speed
= tp
->link_config
.active_speed
;
9600 cmd
->duplex
= tp
->link_config
.active_duplex
;
9602 cmd
->phy_address
= tp
->phy_addr
;
9603 cmd
->transceiver
= XCVR_INTERNAL
;
9604 cmd
->autoneg
= tp
->link_config
.autoneg
;
9610 static int tg3_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
9612 struct tg3
*tp
= netdev_priv(dev
);
9614 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9615 struct phy_device
*phydev
;
9616 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
9618 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
9619 return phy_ethtool_sset(phydev
, cmd
);
9622 if (cmd
->autoneg
!= AUTONEG_ENABLE
&&
9623 cmd
->autoneg
!= AUTONEG_DISABLE
)
9626 if (cmd
->autoneg
== AUTONEG_DISABLE
&&
9627 cmd
->duplex
!= DUPLEX_FULL
&&
9628 cmd
->duplex
!= DUPLEX_HALF
)
9631 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
9632 u32 mask
= ADVERTISED_Autoneg
|
9634 ADVERTISED_Asym_Pause
;
9636 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
))
9637 mask
|= ADVERTISED_1000baseT_Half
|
9638 ADVERTISED_1000baseT_Full
;
9640 if (!(tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
))
9641 mask
|= ADVERTISED_100baseT_Half
|
9642 ADVERTISED_100baseT_Full
|
9643 ADVERTISED_10baseT_Half
|
9644 ADVERTISED_10baseT_Full
|
9647 mask
|= ADVERTISED_FIBRE
;
9649 if (cmd
->advertising
& ~mask
)
9652 mask
&= (ADVERTISED_1000baseT_Half
|
9653 ADVERTISED_1000baseT_Full
|
9654 ADVERTISED_100baseT_Half
|
9655 ADVERTISED_100baseT_Full
|
9656 ADVERTISED_10baseT_Half
|
9657 ADVERTISED_10baseT_Full
);
9659 cmd
->advertising
&= mask
;
9661 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
) {
9662 if (cmd
->speed
!= SPEED_1000
)
9665 if (cmd
->duplex
!= DUPLEX_FULL
)
9668 if (cmd
->speed
!= SPEED_100
&&
9669 cmd
->speed
!= SPEED_10
)
9674 tg3_full_lock(tp
, 0);
9676 tp
->link_config
.autoneg
= cmd
->autoneg
;
9677 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
9678 tp
->link_config
.advertising
= (cmd
->advertising
|
9679 ADVERTISED_Autoneg
);
9680 tp
->link_config
.speed
= SPEED_INVALID
;
9681 tp
->link_config
.duplex
= DUPLEX_INVALID
;
9683 tp
->link_config
.advertising
= 0;
9684 tp
->link_config
.speed
= cmd
->speed
;
9685 tp
->link_config
.duplex
= cmd
->duplex
;
9688 tp
->link_config
.orig_speed
= tp
->link_config
.speed
;
9689 tp
->link_config
.orig_duplex
= tp
->link_config
.duplex
;
9690 tp
->link_config
.orig_autoneg
= tp
->link_config
.autoneg
;
9692 if (netif_running(dev
))
9693 tg3_setup_phy(tp
, 1);
9695 tg3_full_unlock(tp
);
9700 static void tg3_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
9702 struct tg3
*tp
= netdev_priv(dev
);
9704 strcpy(info
->driver
, DRV_MODULE_NAME
);
9705 strcpy(info
->version
, DRV_MODULE_VERSION
);
9706 strcpy(info
->fw_version
, tp
->fw_ver
);
9707 strcpy(info
->bus_info
, pci_name(tp
->pdev
));
9710 static void tg3_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
9712 struct tg3
*tp
= netdev_priv(dev
);
9714 if ((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) &&
9715 device_can_wakeup(&tp
->pdev
->dev
))
9716 wol
->supported
= WAKE_MAGIC
;
9720 if ((tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) &&
9721 device_can_wakeup(&tp
->pdev
->dev
))
9722 wol
->wolopts
= WAKE_MAGIC
;
9723 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
9726 static int tg3_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
9728 struct tg3
*tp
= netdev_priv(dev
);
9729 struct device
*dp
= &tp
->pdev
->dev
;
9731 if (wol
->wolopts
& ~WAKE_MAGIC
)
9733 if ((wol
->wolopts
& WAKE_MAGIC
) &&
9734 !((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) && device_can_wakeup(dp
)))
9737 spin_lock_bh(&tp
->lock
);
9738 if (wol
->wolopts
& WAKE_MAGIC
) {
9739 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
9740 device_set_wakeup_enable(dp
, true);
9742 tp
->tg3_flags
&= ~TG3_FLAG_WOL_ENABLE
;
9743 device_set_wakeup_enable(dp
, false);
9745 spin_unlock_bh(&tp
->lock
);
9750 static u32
tg3_get_msglevel(struct net_device
*dev
)
9752 struct tg3
*tp
= netdev_priv(dev
);
9753 return tp
->msg_enable
;
9756 static void tg3_set_msglevel(struct net_device
*dev
, u32 value
)
9758 struct tg3
*tp
= netdev_priv(dev
);
9759 tp
->msg_enable
= value
;
9762 static int tg3_set_tso(struct net_device
*dev
, u32 value
)
9764 struct tg3
*tp
= netdev_priv(dev
);
9766 if (!(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
9771 if ((dev
->features
& NETIF_F_IPV6_CSUM
) &&
9772 ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_2
) ||
9773 (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
))) {
9775 dev
->features
|= NETIF_F_TSO6
;
9776 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
) ||
9777 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
9778 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
9779 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) ||
9780 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
9781 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
9782 dev
->features
|= NETIF_F_TSO_ECN
;
9784 dev
->features
&= ~(NETIF_F_TSO6
| NETIF_F_TSO_ECN
);
9786 return ethtool_op_set_tso(dev
, value
);
9789 static int tg3_nway_reset(struct net_device
*dev
)
9791 struct tg3
*tp
= netdev_priv(dev
);
9794 if (!netif_running(dev
))
9797 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
9800 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9801 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
9803 r
= phy_start_aneg(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
9807 spin_lock_bh(&tp
->lock
);
9809 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
9810 if (!tg3_readphy(tp
, MII_BMCR
, &bmcr
) &&
9811 ((bmcr
& BMCR_ANENABLE
) ||
9812 (tp
->tg3_flags2
& TG3_FLG2_PARALLEL_DETECT
))) {
9813 tg3_writephy(tp
, MII_BMCR
, bmcr
| BMCR_ANRESTART
|
9817 spin_unlock_bh(&tp
->lock
);
9823 static void tg3_get_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
9825 struct tg3
*tp
= netdev_priv(dev
);
9827 ering
->rx_max_pending
= TG3_RX_RING_SIZE
- 1;
9828 ering
->rx_mini_max_pending
= 0;
9829 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
)
9830 ering
->rx_jumbo_max_pending
= TG3_RX_JUMBO_RING_SIZE
- 1;
9832 ering
->rx_jumbo_max_pending
= 0;
9834 ering
->tx_max_pending
= TG3_TX_RING_SIZE
- 1;
9836 ering
->rx_pending
= tp
->rx_pending
;
9837 ering
->rx_mini_pending
= 0;
9838 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
)
9839 ering
->rx_jumbo_pending
= tp
->rx_jumbo_pending
;
9841 ering
->rx_jumbo_pending
= 0;
9843 ering
->tx_pending
= tp
->napi
[0].tx_pending
;
9846 static int tg3_set_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
9848 struct tg3
*tp
= netdev_priv(dev
);
9849 int i
, irq_sync
= 0, err
= 0;
9851 if ((ering
->rx_pending
> TG3_RX_RING_SIZE
- 1) ||
9852 (ering
->rx_jumbo_pending
> TG3_RX_JUMBO_RING_SIZE
- 1) ||
9853 (ering
->tx_pending
> TG3_TX_RING_SIZE
- 1) ||
9854 (ering
->tx_pending
<= MAX_SKB_FRAGS
) ||
9855 ((tp
->tg3_flags2
& TG3_FLG2_TSO_BUG
) &&
9856 (ering
->tx_pending
<= (MAX_SKB_FRAGS
* 3))))
9859 if (netif_running(dev
)) {
9865 tg3_full_lock(tp
, irq_sync
);
9867 tp
->rx_pending
= ering
->rx_pending
;
9869 if ((tp
->tg3_flags2
& TG3_FLG2_MAX_RXPEND_64
) &&
9870 tp
->rx_pending
> 63)
9871 tp
->rx_pending
= 63;
9872 tp
->rx_jumbo_pending
= ering
->rx_jumbo_pending
;
9874 for (i
= 0; i
< TG3_IRQ_MAX_VECS
; i
++)
9875 tp
->napi
[i
].tx_pending
= ering
->tx_pending
;
9877 if (netif_running(dev
)) {
9878 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
9879 err
= tg3_restart_hw(tp
, 1);
9881 tg3_netif_start(tp
);
9884 tg3_full_unlock(tp
);
9886 if (irq_sync
&& !err
)
9892 static void tg3_get_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
9894 struct tg3
*tp
= netdev_priv(dev
);
9896 epause
->autoneg
= (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
) != 0;
9898 if (tp
->link_config
.active_flowctrl
& FLOW_CTRL_RX
)
9899 epause
->rx_pause
= 1;
9901 epause
->rx_pause
= 0;
9903 if (tp
->link_config
.active_flowctrl
& FLOW_CTRL_TX
)
9904 epause
->tx_pause
= 1;
9906 epause
->tx_pause
= 0;
9909 static int tg3_set_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
9911 struct tg3
*tp
= netdev_priv(dev
);
9914 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9916 struct phy_device
*phydev
;
9918 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
9920 if (!(phydev
->supported
& SUPPORTED_Pause
) ||
9921 (!(phydev
->supported
& SUPPORTED_Asym_Pause
) &&
9922 ((epause
->rx_pause
&& !epause
->tx_pause
) ||
9923 (!epause
->rx_pause
&& epause
->tx_pause
))))
9926 tp
->link_config
.flowctrl
= 0;
9927 if (epause
->rx_pause
) {
9928 tp
->link_config
.flowctrl
|= FLOW_CTRL_RX
;
9930 if (epause
->tx_pause
) {
9931 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
9932 newadv
= ADVERTISED_Pause
;
9934 newadv
= ADVERTISED_Pause
|
9935 ADVERTISED_Asym_Pause
;
9936 } else if (epause
->tx_pause
) {
9937 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
9938 newadv
= ADVERTISED_Asym_Pause
;
9942 if (epause
->autoneg
)
9943 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
9945 tp
->tg3_flags
&= ~TG3_FLAG_PAUSE_AUTONEG
;
9947 if (tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
) {
9948 u32 oldadv
= phydev
->advertising
&
9949 (ADVERTISED_Pause
| ADVERTISED_Asym_Pause
);
9950 if (oldadv
!= newadv
) {
9951 phydev
->advertising
&=
9952 ~(ADVERTISED_Pause
|
9953 ADVERTISED_Asym_Pause
);
9954 phydev
->advertising
|= newadv
;
9955 if (phydev
->autoneg
) {
9957 * Always renegotiate the link to
9958 * inform our link partner of our
9959 * flow control settings, even if the
9960 * flow control is forced. Let
9961 * tg3_adjust_link() do the final
9962 * flow control setup.
9964 return phy_start_aneg(phydev
);
9968 if (!epause
->autoneg
)
9969 tg3_setup_flow_control(tp
, 0, 0);
9971 tp
->link_config
.orig_advertising
&=
9972 ~(ADVERTISED_Pause
|
9973 ADVERTISED_Asym_Pause
);
9974 tp
->link_config
.orig_advertising
|= newadv
;
9979 if (netif_running(dev
)) {
9984 tg3_full_lock(tp
, irq_sync
);
9986 if (epause
->autoneg
)
9987 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
9989 tp
->tg3_flags
&= ~TG3_FLAG_PAUSE_AUTONEG
;
9990 if (epause
->rx_pause
)
9991 tp
->link_config
.flowctrl
|= FLOW_CTRL_RX
;
9993 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_RX
;
9994 if (epause
->tx_pause
)
9995 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
9997 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_TX
;
9999 if (netif_running(dev
)) {
10000 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
10001 err
= tg3_restart_hw(tp
, 1);
10003 tg3_netif_start(tp
);
10006 tg3_full_unlock(tp
);
10012 static u32
tg3_get_rx_csum(struct net_device
*dev
)
10014 struct tg3
*tp
= netdev_priv(dev
);
10015 return (tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) != 0;
10018 static int tg3_set_rx_csum(struct net_device
*dev
, u32 data
)
10020 struct tg3
*tp
= netdev_priv(dev
);
10022 if (tp
->tg3_flags
& TG3_FLAG_BROKEN_CHECKSUMS
) {
10028 spin_lock_bh(&tp
->lock
);
10030 tp
->tg3_flags
|= TG3_FLAG_RX_CHECKSUMS
;
10032 tp
->tg3_flags
&= ~TG3_FLAG_RX_CHECKSUMS
;
10033 spin_unlock_bh(&tp
->lock
);
10038 static int tg3_set_tx_csum(struct net_device
*dev
, u32 data
)
10040 struct tg3
*tp
= netdev_priv(dev
);
10042 if (tp
->tg3_flags
& TG3_FLAG_BROKEN_CHECKSUMS
) {
10048 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
10049 ethtool_op_set_tx_ipv6_csum(dev
, data
);
10051 ethtool_op_set_tx_csum(dev
, data
);
10056 static int tg3_get_sset_count(struct net_device
*dev
, int sset
)
10060 return TG3_NUM_TEST
;
10062 return TG3_NUM_STATS
;
10064 return -EOPNOTSUPP
;
10068 static void tg3_get_strings(struct net_device
*dev
, u32 stringset
, u8
*buf
)
10070 switch (stringset
) {
10072 memcpy(buf
, ðtool_stats_keys
, sizeof(ethtool_stats_keys
));
10075 memcpy(buf
, ðtool_test_keys
, sizeof(ethtool_test_keys
));
10078 WARN_ON(1); /* we need a WARN() */
10083 static int tg3_phys_id(struct net_device
*dev
, u32 data
)
10085 struct tg3
*tp
= netdev_priv(dev
);
10088 if (!netif_running(tp
->dev
))
10092 data
= UINT_MAX
/ 2;
10094 for (i
= 0; i
< (data
* 2); i
++) {
10096 tw32(MAC_LED_CTRL
, LED_CTRL_LNKLED_OVERRIDE
|
10097 LED_CTRL_1000MBPS_ON
|
10098 LED_CTRL_100MBPS_ON
|
10099 LED_CTRL_10MBPS_ON
|
10100 LED_CTRL_TRAFFIC_OVERRIDE
|
10101 LED_CTRL_TRAFFIC_BLINK
|
10102 LED_CTRL_TRAFFIC_LED
);
10105 tw32(MAC_LED_CTRL
, LED_CTRL_LNKLED_OVERRIDE
|
10106 LED_CTRL_TRAFFIC_OVERRIDE
);
10108 if (msleep_interruptible(500))
10111 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
10115 static void tg3_get_ethtool_stats(struct net_device
*dev
,
10116 struct ethtool_stats
*estats
, u64
*tmp_stats
)
10118 struct tg3
*tp
= netdev_priv(dev
);
10119 memcpy(tmp_stats
, tg3_get_estats(tp
), sizeof(tp
->estats
));
10122 #define NVRAM_TEST_SIZE 0x100
10123 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10124 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10125 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
10126 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10127 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10129 static int tg3_test_nvram(struct tg3
*tp
)
10133 int i
, j
, k
, err
= 0, size
;
10135 if (tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
)
10138 if (tg3_nvram_read(tp
, 0, &magic
) != 0)
10141 if (magic
== TG3_EEPROM_MAGIC
)
10142 size
= NVRAM_TEST_SIZE
;
10143 else if ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) == TG3_EEPROM_MAGIC_FW
) {
10144 if ((magic
& TG3_EEPROM_SB_FORMAT_MASK
) ==
10145 TG3_EEPROM_SB_FORMAT_1
) {
10146 switch (magic
& TG3_EEPROM_SB_REVISION_MASK
) {
10147 case TG3_EEPROM_SB_REVISION_0
:
10148 size
= NVRAM_SELFBOOT_FORMAT1_0_SIZE
;
10150 case TG3_EEPROM_SB_REVISION_2
:
10151 size
= NVRAM_SELFBOOT_FORMAT1_2_SIZE
;
10153 case TG3_EEPROM_SB_REVISION_3
:
10154 size
= NVRAM_SELFBOOT_FORMAT1_3_SIZE
;
10161 } else if ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) == TG3_EEPROM_MAGIC_HW
)
10162 size
= NVRAM_SELFBOOT_HW_SIZE
;
10166 buf
= kmalloc(size
, GFP_KERNEL
);
10171 for (i
= 0, j
= 0; i
< size
; i
+= 4, j
++) {
10172 err
= tg3_nvram_read_be32(tp
, i
, &buf
[j
]);
10179 /* Selfboot format */
10180 magic
= be32_to_cpu(buf
[0]);
10181 if ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) ==
10182 TG3_EEPROM_MAGIC_FW
) {
10183 u8
*buf8
= (u8
*) buf
, csum8
= 0;
10185 if ((magic
& TG3_EEPROM_SB_REVISION_MASK
) ==
10186 TG3_EEPROM_SB_REVISION_2
) {
10187 /* For rev 2, the csum doesn't include the MBA. */
10188 for (i
= 0; i
< TG3_EEPROM_SB_F1R2_MBA_OFF
; i
++)
10190 for (i
= TG3_EEPROM_SB_F1R2_MBA_OFF
+ 4; i
< size
; i
++)
10193 for (i
= 0; i
< size
; i
++)
10206 if ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) ==
10207 TG3_EEPROM_MAGIC_HW
) {
10208 u8 data
[NVRAM_SELFBOOT_DATA_SIZE
];
10209 u8 parity
[NVRAM_SELFBOOT_DATA_SIZE
];
10210 u8
*buf8
= (u8
*) buf
;
10212 /* Separate the parity bits and the data bytes. */
10213 for (i
= 0, j
= 0, k
= 0; i
< NVRAM_SELFBOOT_HW_SIZE
; i
++) {
10214 if ((i
== 0) || (i
== 8)) {
10218 for (l
= 0, msk
= 0x80; l
< 7; l
++, msk
>>= 1)
10219 parity
[k
++] = buf8
[i
] & msk
;
10221 } else if (i
== 16) {
10225 for (l
= 0, msk
= 0x20; l
< 6; l
++, msk
>>= 1)
10226 parity
[k
++] = buf8
[i
] & msk
;
10229 for (l
= 0, msk
= 0x80; l
< 8; l
++, msk
>>= 1)
10230 parity
[k
++] = buf8
[i
] & msk
;
10233 data
[j
++] = buf8
[i
];
10237 for (i
= 0; i
< NVRAM_SELFBOOT_DATA_SIZE
; i
++) {
10238 u8 hw8
= hweight8(data
[i
]);
10240 if ((hw8
& 0x1) && parity
[i
])
10242 else if (!(hw8
& 0x1) && !parity
[i
])
10249 /* Bootstrap checksum at offset 0x10 */
10250 csum
= calc_crc((unsigned char *) buf
, 0x10);
10251 if (csum
!= be32_to_cpu(buf
[0x10/4]))
10254 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10255 csum
= calc_crc((unsigned char *) &buf
[0x74/4], 0x88);
10256 if (csum
!= be32_to_cpu(buf
[0xfc/4]))
10266 #define TG3_SERDES_TIMEOUT_SEC 2
10267 #define TG3_COPPER_TIMEOUT_SEC 6
10269 static int tg3_test_link(struct tg3
*tp
)
10273 if (!netif_running(tp
->dev
))
10276 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)
10277 max
= TG3_SERDES_TIMEOUT_SEC
;
10279 max
= TG3_COPPER_TIMEOUT_SEC
;
10281 for (i
= 0; i
< max
; i
++) {
10282 if (netif_carrier_ok(tp
->dev
))
10285 if (msleep_interruptible(1000))
10292 /* Only test the commonly used registers */
10293 static int tg3_test_registers(struct tg3
*tp
)
10295 int i
, is_5705
, is_5750
;
10296 u32 offset
, read_mask
, write_mask
, val
, save_val
, read_val
;
10300 #define TG3_FL_5705 0x1
10301 #define TG3_FL_NOT_5705 0x2
10302 #define TG3_FL_NOT_5788 0x4
10303 #define TG3_FL_NOT_5750 0x8
10307 /* MAC Control Registers */
10308 { MAC_MODE
, TG3_FL_NOT_5705
,
10309 0x00000000, 0x00ef6f8c },
10310 { MAC_MODE
, TG3_FL_5705
,
10311 0x00000000, 0x01ef6b8c },
10312 { MAC_STATUS
, TG3_FL_NOT_5705
,
10313 0x03800107, 0x00000000 },
10314 { MAC_STATUS
, TG3_FL_5705
,
10315 0x03800100, 0x00000000 },
10316 { MAC_ADDR_0_HIGH
, 0x0000,
10317 0x00000000, 0x0000ffff },
10318 { MAC_ADDR_0_LOW
, 0x0000,
10319 0x00000000, 0xffffffff },
10320 { MAC_RX_MTU_SIZE
, 0x0000,
10321 0x00000000, 0x0000ffff },
10322 { MAC_TX_MODE
, 0x0000,
10323 0x00000000, 0x00000070 },
10324 { MAC_TX_LENGTHS
, 0x0000,
10325 0x00000000, 0x00003fff },
10326 { MAC_RX_MODE
, TG3_FL_NOT_5705
,
10327 0x00000000, 0x000007fc },
10328 { MAC_RX_MODE
, TG3_FL_5705
,
10329 0x00000000, 0x000007dc },
10330 { MAC_HASH_REG_0
, 0x0000,
10331 0x00000000, 0xffffffff },
10332 { MAC_HASH_REG_1
, 0x0000,
10333 0x00000000, 0xffffffff },
10334 { MAC_HASH_REG_2
, 0x0000,
10335 0x00000000, 0xffffffff },
10336 { MAC_HASH_REG_3
, 0x0000,
10337 0x00000000, 0xffffffff },
10339 /* Receive Data and Receive BD Initiator Control Registers. */
10340 { RCVDBDI_JUMBO_BD
+0, TG3_FL_NOT_5705
,
10341 0x00000000, 0xffffffff },
10342 { RCVDBDI_JUMBO_BD
+4, TG3_FL_NOT_5705
,
10343 0x00000000, 0xffffffff },
10344 { RCVDBDI_JUMBO_BD
+8, TG3_FL_NOT_5705
,
10345 0x00000000, 0x00000003 },
10346 { RCVDBDI_JUMBO_BD
+0xc, TG3_FL_NOT_5705
,
10347 0x00000000, 0xffffffff },
10348 { RCVDBDI_STD_BD
+0, 0x0000,
10349 0x00000000, 0xffffffff },
10350 { RCVDBDI_STD_BD
+4, 0x0000,
10351 0x00000000, 0xffffffff },
10352 { RCVDBDI_STD_BD
+8, 0x0000,
10353 0x00000000, 0xffff0002 },
10354 { RCVDBDI_STD_BD
+0xc, 0x0000,
10355 0x00000000, 0xffffffff },
10357 /* Receive BD Initiator Control Registers. */
10358 { RCVBDI_STD_THRESH
, TG3_FL_NOT_5705
,
10359 0x00000000, 0xffffffff },
10360 { RCVBDI_STD_THRESH
, TG3_FL_5705
,
10361 0x00000000, 0x000003ff },
10362 { RCVBDI_JUMBO_THRESH
, TG3_FL_NOT_5705
,
10363 0x00000000, 0xffffffff },
10365 /* Host Coalescing Control Registers. */
10366 { HOSTCC_MODE
, TG3_FL_NOT_5705
,
10367 0x00000000, 0x00000004 },
10368 { HOSTCC_MODE
, TG3_FL_5705
,
10369 0x00000000, 0x000000f6 },
10370 { HOSTCC_RXCOL_TICKS
, TG3_FL_NOT_5705
,
10371 0x00000000, 0xffffffff },
10372 { HOSTCC_RXCOL_TICKS
, TG3_FL_5705
,
10373 0x00000000, 0x000003ff },
10374 { HOSTCC_TXCOL_TICKS
, TG3_FL_NOT_5705
,
10375 0x00000000, 0xffffffff },
10376 { HOSTCC_TXCOL_TICKS
, TG3_FL_5705
,
10377 0x00000000, 0x000003ff },
10378 { HOSTCC_RXMAX_FRAMES
, TG3_FL_NOT_5705
,
10379 0x00000000, 0xffffffff },
10380 { HOSTCC_RXMAX_FRAMES
, TG3_FL_5705
| TG3_FL_NOT_5788
,
10381 0x00000000, 0x000000ff },
10382 { HOSTCC_TXMAX_FRAMES
, TG3_FL_NOT_5705
,
10383 0x00000000, 0xffffffff },
10384 { HOSTCC_TXMAX_FRAMES
, TG3_FL_5705
| TG3_FL_NOT_5788
,
10385 0x00000000, 0x000000ff },
10386 { HOSTCC_RXCOAL_TICK_INT
, TG3_FL_NOT_5705
,
10387 0x00000000, 0xffffffff },
10388 { HOSTCC_TXCOAL_TICK_INT
, TG3_FL_NOT_5705
,
10389 0x00000000, 0xffffffff },
10390 { HOSTCC_RXCOAL_MAXF_INT
, TG3_FL_NOT_5705
,
10391 0x00000000, 0xffffffff },
10392 { HOSTCC_RXCOAL_MAXF_INT
, TG3_FL_5705
| TG3_FL_NOT_5788
,
10393 0x00000000, 0x000000ff },
10394 { HOSTCC_TXCOAL_MAXF_INT
, TG3_FL_NOT_5705
,
10395 0x00000000, 0xffffffff },
10396 { HOSTCC_TXCOAL_MAXF_INT
, TG3_FL_5705
| TG3_FL_NOT_5788
,
10397 0x00000000, 0x000000ff },
10398 { HOSTCC_STAT_COAL_TICKS
, TG3_FL_NOT_5705
,
10399 0x00000000, 0xffffffff },
10400 { HOSTCC_STATS_BLK_HOST_ADDR
, TG3_FL_NOT_5705
,
10401 0x00000000, 0xffffffff },
10402 { HOSTCC_STATS_BLK_HOST_ADDR
+4, TG3_FL_NOT_5705
,
10403 0x00000000, 0xffffffff },
10404 { HOSTCC_STATUS_BLK_HOST_ADDR
, 0x0000,
10405 0x00000000, 0xffffffff },
10406 { HOSTCC_STATUS_BLK_HOST_ADDR
+4, 0x0000,
10407 0x00000000, 0xffffffff },
10408 { HOSTCC_STATS_BLK_NIC_ADDR
, 0x0000,
10409 0xffffffff, 0x00000000 },
10410 { HOSTCC_STATUS_BLK_NIC_ADDR
, 0x0000,
10411 0xffffffff, 0x00000000 },
10413 /* Buffer Manager Control Registers. */
10414 { BUFMGR_MB_POOL_ADDR
, TG3_FL_NOT_5750
,
10415 0x00000000, 0x007fff80 },
10416 { BUFMGR_MB_POOL_SIZE
, TG3_FL_NOT_5750
,
10417 0x00000000, 0x007fffff },
10418 { BUFMGR_MB_RDMA_LOW_WATER
, 0x0000,
10419 0x00000000, 0x0000003f },
10420 { BUFMGR_MB_MACRX_LOW_WATER
, 0x0000,
10421 0x00000000, 0x000001ff },
10422 { BUFMGR_MB_HIGH_WATER
, 0x0000,
10423 0x00000000, 0x000001ff },
10424 { BUFMGR_DMA_DESC_POOL_ADDR
, TG3_FL_NOT_5705
,
10425 0xffffffff, 0x00000000 },
10426 { BUFMGR_DMA_DESC_POOL_SIZE
, TG3_FL_NOT_5705
,
10427 0xffffffff, 0x00000000 },
10429 /* Mailbox Registers */
10430 { GRCMBOX_RCVSTD_PROD_IDX
+4, 0x0000,
10431 0x00000000, 0x000001ff },
10432 { GRCMBOX_RCVJUMBO_PROD_IDX
+4, TG3_FL_NOT_5705
,
10433 0x00000000, 0x000001ff },
10434 { GRCMBOX_RCVRET_CON_IDX_0
+4, 0x0000,
10435 0x00000000, 0x000007ff },
10436 { GRCMBOX_SNDHOST_PROD_IDX_0
+4, 0x0000,
10437 0x00000000, 0x000001ff },
10439 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10442 is_5705
= is_5750
= 0;
10443 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
10445 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
10449 for (i
= 0; reg_tbl
[i
].offset
!= 0xffff; i
++) {
10450 if (is_5705
&& (reg_tbl
[i
].flags
& TG3_FL_NOT_5705
))
10453 if (!is_5705
&& (reg_tbl
[i
].flags
& TG3_FL_5705
))
10456 if ((tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
10457 (reg_tbl
[i
].flags
& TG3_FL_NOT_5788
))
10460 if (is_5750
&& (reg_tbl
[i
].flags
& TG3_FL_NOT_5750
))
10463 offset
= (u32
) reg_tbl
[i
].offset
;
10464 read_mask
= reg_tbl
[i
].read_mask
;
10465 write_mask
= reg_tbl
[i
].write_mask
;
10467 /* Save the original register content */
10468 save_val
= tr32(offset
);
10470 /* Determine the read-only value. */
10471 read_val
= save_val
& read_mask
;
10473 /* Write zero to the register, then make sure the read-only bits
10474 * are not changed and the read/write bits are all zeros.
10478 val
= tr32(offset
);
10480 /* Test the read-only and read/write bits. */
10481 if (((val
& read_mask
) != read_val
) || (val
& write_mask
))
10484 /* Write ones to all the bits defined by RdMask and WrMask, then
10485 * make sure the read-only bits are not changed and the
10486 * read/write bits are all ones.
10488 tw32(offset
, read_mask
| write_mask
);
10490 val
= tr32(offset
);
10492 /* Test the read-only bits. */
10493 if ((val
& read_mask
) != read_val
)
10496 /* Test the read/write bits. */
10497 if ((val
& write_mask
) != write_mask
)
10500 tw32(offset
, save_val
);
10506 if (netif_msg_hw(tp
))
10507 netdev_err(tp
->dev
,
10508 "Register test failed at offset %x\n", offset
);
10509 tw32(offset
, save_val
);
10513 static int tg3_do_mem_test(struct tg3
*tp
, u32 offset
, u32 len
)
10515 static const u32 test_pattern
[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10519 for (i
= 0; i
< ARRAY_SIZE(test_pattern
); i
++) {
10520 for (j
= 0; j
< len
; j
+= 4) {
10523 tg3_write_mem(tp
, offset
+ j
, test_pattern
[i
]);
10524 tg3_read_mem(tp
, offset
+ j
, &val
);
10525 if (val
!= test_pattern
[i
])
10532 static int tg3_test_memory(struct tg3
*tp
)
10534 static struct mem_entry
{
10537 } mem_tbl_570x
[] = {
10538 { 0x00000000, 0x00b50},
10539 { 0x00002000, 0x1c000},
10540 { 0xffffffff, 0x00000}
10541 }, mem_tbl_5705
[] = {
10542 { 0x00000100, 0x0000c},
10543 { 0x00000200, 0x00008},
10544 { 0x00004000, 0x00800},
10545 { 0x00006000, 0x01000},
10546 { 0x00008000, 0x02000},
10547 { 0x00010000, 0x0e000},
10548 { 0xffffffff, 0x00000}
10549 }, mem_tbl_5755
[] = {
10550 { 0x00000200, 0x00008},
10551 { 0x00004000, 0x00800},
10552 { 0x00006000, 0x00800},
10553 { 0x00008000, 0x02000},
10554 { 0x00010000, 0x0c000},
10555 { 0xffffffff, 0x00000}
10556 }, mem_tbl_5906
[] = {
10557 { 0x00000200, 0x00008},
10558 { 0x00004000, 0x00400},
10559 { 0x00006000, 0x00400},
10560 { 0x00008000, 0x01000},
10561 { 0x00010000, 0x01000},
10562 { 0xffffffff, 0x00000}
10563 }, mem_tbl_5717
[] = {
10564 { 0x00000200, 0x00008},
10565 { 0x00010000, 0x0a000},
10566 { 0x00020000, 0x13c00},
10567 { 0xffffffff, 0x00000}
10568 }, mem_tbl_57765
[] = {
10569 { 0x00000200, 0x00008},
10570 { 0x00004000, 0x00800},
10571 { 0x00006000, 0x09800},
10572 { 0x00010000, 0x0a000},
10573 { 0xffffffff, 0x00000}
10575 struct mem_entry
*mem_tbl
;
10579 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
)
10580 mem_tbl
= mem_tbl_5717
;
10581 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
10582 mem_tbl
= mem_tbl_57765
;
10583 else if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
10584 mem_tbl
= mem_tbl_5755
;
10585 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
10586 mem_tbl
= mem_tbl_5906
;
10587 else if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
10588 mem_tbl
= mem_tbl_5705
;
10590 mem_tbl
= mem_tbl_570x
;
10592 for (i
= 0; mem_tbl
[i
].offset
!= 0xffffffff; i
++) {
10593 if ((err
= tg3_do_mem_test(tp
, mem_tbl
[i
].offset
,
10594 mem_tbl
[i
].len
)) != 0)
10601 #define TG3_MAC_LOOPBACK 0
10602 #define TG3_PHY_LOOPBACK 1
10604 static int tg3_run_loopback(struct tg3
*tp
, int loopback_mode
)
10606 u32 mac_mode
, rx_start_idx
, rx_idx
, tx_idx
, opaque_key
;
10607 u32 desc_idx
, coal_now
;
10608 struct sk_buff
*skb
, *rx_skb
;
10611 int num_pkts
, tx_len
, rx_len
, i
, err
;
10612 struct tg3_rx_buffer_desc
*desc
;
10613 struct tg3_napi
*tnapi
, *rnapi
;
10614 struct tg3_rx_prodring_set
*tpr
= &tp
->prodring
[0];
10616 tnapi
= &tp
->napi
[0];
10617 rnapi
= &tp
->napi
[0];
10618 if (tp
->irq_cnt
> 1) {
10619 rnapi
= &tp
->napi
[1];
10620 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_TSS
)
10621 tnapi
= &tp
->napi
[1];
10623 coal_now
= tnapi
->coal_now
| rnapi
->coal_now
;
10625 if (loopback_mode
== TG3_MAC_LOOPBACK
) {
10626 /* HW errata - mac loopback fails in some cases on 5780.
10627 * Normal traffic and PHY loopback are not affected by
10630 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
)
10633 mac_mode
= (tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
) |
10634 MAC_MODE_PORT_INT_LPBACK
;
10635 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
10636 mac_mode
|= MAC_MODE_LINK_POLARITY
;
10637 if (tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)
10638 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
10640 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
10641 tw32(MAC_MODE
, mac_mode
);
10642 } else if (loopback_mode
== TG3_PHY_LOOPBACK
) {
10645 if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) {
10646 tg3_phy_fet_toggle_apd(tp
, false);
10647 val
= BMCR_LOOPBACK
| BMCR_FULLDPLX
| BMCR_SPEED100
;
10649 val
= BMCR_LOOPBACK
| BMCR_FULLDPLX
| BMCR_SPEED1000
;
10651 tg3_phy_toggle_automdix(tp
, 0);
10653 tg3_writephy(tp
, MII_BMCR
, val
);
10656 mac_mode
= tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
;
10657 if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) {
10658 tg3_writephy(tp
, MII_TG3_FET_PTEST
,
10659 MII_TG3_FET_PTEST_FRC_TX_LINK
|
10660 MII_TG3_FET_PTEST_FRC_TX_LOCK
);
10661 /* The write needs to be flushed for the AC131 */
10662 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
10663 tg3_readphy(tp
, MII_TG3_FET_PTEST
, &val
);
10664 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
10666 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
10668 /* reset to prevent losing 1st rx packet intermittently */
10669 if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) {
10670 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
10672 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
10674 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) {
10675 u32 masked_phy_id
= tp
->phy_id
& TG3_PHY_ID_MASK
;
10676 if (masked_phy_id
== TG3_PHY_ID_BCM5401
)
10677 mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
10678 else if (masked_phy_id
== TG3_PHY_ID_BCM5411
)
10679 mac_mode
|= MAC_MODE_LINK_POLARITY
;
10680 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
10681 MII_TG3_EXT_CTRL_LNK3_LED_MODE
);
10683 tw32(MAC_MODE
, mac_mode
);
10691 skb
= netdev_alloc_skb(tp
->dev
, tx_len
);
10695 tx_data
= skb_put(skb
, tx_len
);
10696 memcpy(tx_data
, tp
->dev
->dev_addr
, 6);
10697 memset(tx_data
+ 6, 0x0, 8);
10699 tw32(MAC_RX_MTU_SIZE
, tx_len
+ 4);
10701 for (i
= 14; i
< tx_len
; i
++)
10702 tx_data
[i
] = (u8
) (i
& 0xff);
10704 map
= pci_map_single(tp
->pdev
, skb
->data
, tx_len
, PCI_DMA_TODEVICE
);
10705 if (pci_dma_mapping_error(tp
->pdev
, map
)) {
10706 dev_kfree_skb(skb
);
10710 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
10715 rx_start_idx
= rnapi
->hw_status
->idx
[0].rx_producer
;
10719 tg3_set_txd(tnapi
, tnapi
->tx_prod
, map
, tx_len
, 0, 1);
10724 tw32_tx_mbox(tnapi
->prodmbox
, tnapi
->tx_prod
);
10725 tr32_mailbox(tnapi
->prodmbox
);
10729 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10730 for (i
= 0; i
< 35; i
++) {
10731 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
10736 tx_idx
= tnapi
->hw_status
->idx
[0].tx_consumer
;
10737 rx_idx
= rnapi
->hw_status
->idx
[0].rx_producer
;
10738 if ((tx_idx
== tnapi
->tx_prod
) &&
10739 (rx_idx
== (rx_start_idx
+ num_pkts
)))
10743 pci_unmap_single(tp
->pdev
, map
, tx_len
, PCI_DMA_TODEVICE
);
10744 dev_kfree_skb(skb
);
10746 if (tx_idx
!= tnapi
->tx_prod
)
10749 if (rx_idx
!= rx_start_idx
+ num_pkts
)
10752 desc
= &rnapi
->rx_rcb
[rx_start_idx
];
10753 desc_idx
= desc
->opaque
& RXD_OPAQUE_INDEX_MASK
;
10754 opaque_key
= desc
->opaque
& RXD_OPAQUE_RING_MASK
;
10755 if (opaque_key
!= RXD_OPAQUE_RING_STD
)
10758 if ((desc
->err_vlan
& RXD_ERR_MASK
) != 0 &&
10759 (desc
->err_vlan
!= RXD_ERR_ODD_NIBBLE_RCVD_MII
))
10762 rx_len
= ((desc
->idx_len
& RXD_LEN_MASK
) >> RXD_LEN_SHIFT
) - 4;
10763 if (rx_len
!= tx_len
)
10766 rx_skb
= tpr
->rx_std_buffers
[desc_idx
].skb
;
10768 map
= dma_unmap_addr(&tpr
->rx_std_buffers
[desc_idx
], mapping
);
10769 pci_dma_sync_single_for_cpu(tp
->pdev
, map
, rx_len
, PCI_DMA_FROMDEVICE
);
10771 for (i
= 14; i
< tx_len
; i
++) {
10772 if (*(rx_skb
->data
+ i
) != (u8
) (i
& 0xff))
10777 /* tg3_free_rings will unmap and free the rx_skb */
10782 #define TG3_MAC_LOOPBACK_FAILED 1
10783 #define TG3_PHY_LOOPBACK_FAILED 2
10784 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10785 TG3_PHY_LOOPBACK_FAILED)
10787 static int tg3_test_loopback(struct tg3
*tp
)
10792 if (!netif_running(tp
->dev
))
10793 return TG3_LOOPBACK_FAILED
;
10795 err
= tg3_reset_hw(tp
, 1);
10797 return TG3_LOOPBACK_FAILED
;
10799 /* Turn off gphy autopowerdown. */
10800 if (tp
->tg3_flags3
& TG3_FLG3_PHY_ENABLE_APD
)
10801 tg3_phy_toggle_apd(tp
, false);
10803 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) {
10807 tw32(TG3_CPMU_MUTEX_REQ
, CPMU_MUTEX_REQ_DRIVER
);
10809 /* Wait for up to 40 microseconds to acquire lock. */
10810 for (i
= 0; i
< 4; i
++) {
10811 status
= tr32(TG3_CPMU_MUTEX_GNT
);
10812 if (status
== CPMU_MUTEX_GNT_DRIVER
)
10817 if (status
!= CPMU_MUTEX_GNT_DRIVER
)
10818 return TG3_LOOPBACK_FAILED
;
10820 /* Turn off link-based power management. */
10821 cpmuctrl
= tr32(TG3_CPMU_CTRL
);
10822 tw32(TG3_CPMU_CTRL
,
10823 cpmuctrl
& ~(CPMU_CTRL_LINK_SPEED_MODE
|
10824 CPMU_CTRL_LINK_AWARE_MODE
));
10827 if (tg3_run_loopback(tp
, TG3_MAC_LOOPBACK
))
10828 err
|= TG3_MAC_LOOPBACK_FAILED
;
10830 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) {
10831 tw32(TG3_CPMU_CTRL
, cpmuctrl
);
10833 /* Release the mutex */
10834 tw32(TG3_CPMU_MUTEX_GNT
, CPMU_MUTEX_GNT_DRIVER
);
10837 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
10838 !(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)) {
10839 if (tg3_run_loopback(tp
, TG3_PHY_LOOPBACK
))
10840 err
|= TG3_PHY_LOOPBACK_FAILED
;
10843 /* Re-enable gphy autopowerdown. */
10844 if (tp
->tg3_flags3
& TG3_FLG3_PHY_ENABLE_APD
)
10845 tg3_phy_toggle_apd(tp
, true);
10850 static void tg3_self_test(struct net_device
*dev
, struct ethtool_test
*etest
,
10853 struct tg3
*tp
= netdev_priv(dev
);
10855 if (tp
->link_config
.phy_is_low_power
)
10856 tg3_set_power_state(tp
, PCI_D0
);
10858 memset(data
, 0, sizeof(u64
) * TG3_NUM_TEST
);
10860 if (tg3_test_nvram(tp
) != 0) {
10861 etest
->flags
|= ETH_TEST_FL_FAILED
;
10864 if (tg3_test_link(tp
) != 0) {
10865 etest
->flags
|= ETH_TEST_FL_FAILED
;
10868 if (etest
->flags
& ETH_TEST_FL_OFFLINE
) {
10869 int err
, err2
= 0, irq_sync
= 0;
10871 if (netif_running(dev
)) {
10873 tg3_netif_stop(tp
);
10877 tg3_full_lock(tp
, irq_sync
);
10879 tg3_halt(tp
, RESET_KIND_SUSPEND
, 1);
10880 err
= tg3_nvram_lock(tp
);
10881 tg3_halt_cpu(tp
, RX_CPU_BASE
);
10882 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
10883 tg3_halt_cpu(tp
, TX_CPU_BASE
);
10885 tg3_nvram_unlock(tp
);
10887 if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)
10890 if (tg3_test_registers(tp
) != 0) {
10891 etest
->flags
|= ETH_TEST_FL_FAILED
;
10894 if (tg3_test_memory(tp
) != 0) {
10895 etest
->flags
|= ETH_TEST_FL_FAILED
;
10898 if ((data
[4] = tg3_test_loopback(tp
)) != 0)
10899 etest
->flags
|= ETH_TEST_FL_FAILED
;
10901 tg3_full_unlock(tp
);
10903 if (tg3_test_interrupt(tp
) != 0) {
10904 etest
->flags
|= ETH_TEST_FL_FAILED
;
10908 tg3_full_lock(tp
, 0);
10910 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
10911 if (netif_running(dev
)) {
10912 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
10913 err2
= tg3_restart_hw(tp
, 1);
10915 tg3_netif_start(tp
);
10918 tg3_full_unlock(tp
);
10920 if (irq_sync
&& !err2
)
10923 if (tp
->link_config
.phy_is_low_power
)
10924 tg3_set_power_state(tp
, PCI_D3hot
);
10928 static int tg3_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
10930 struct mii_ioctl_data
*data
= if_mii(ifr
);
10931 struct tg3
*tp
= netdev_priv(dev
);
10934 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
10935 struct phy_device
*phydev
;
10936 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
10938 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
10939 return phy_mii_ioctl(phydev
, data
, cmd
);
10944 data
->phy_id
= tp
->phy_addr
;
10947 case SIOCGMIIREG
: {
10950 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
10951 break; /* We have no PHY */
10953 if (tp
->link_config
.phy_is_low_power
)
10956 spin_lock_bh(&tp
->lock
);
10957 err
= tg3_readphy(tp
, data
->reg_num
& 0x1f, &mii_regval
);
10958 spin_unlock_bh(&tp
->lock
);
10960 data
->val_out
= mii_regval
;
10966 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
10967 break; /* We have no PHY */
10969 if (tp
->link_config
.phy_is_low_power
)
10972 spin_lock_bh(&tp
->lock
);
10973 err
= tg3_writephy(tp
, data
->reg_num
& 0x1f, data
->val_in
);
10974 spin_unlock_bh(&tp
->lock
);
10982 return -EOPNOTSUPP
;
10985 #if TG3_VLAN_TAG_USED
10986 static void tg3_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
10988 struct tg3
*tp
= netdev_priv(dev
);
10990 if (!netif_running(dev
)) {
10995 tg3_netif_stop(tp
);
10997 tg3_full_lock(tp
, 0);
11001 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11002 __tg3_set_rx_mode(dev
);
11004 tg3_netif_start(tp
);
11006 tg3_full_unlock(tp
);
11010 static int tg3_get_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
11012 struct tg3
*tp
= netdev_priv(dev
);
11014 memcpy(ec
, &tp
->coal
, sizeof(*ec
));
11018 static int tg3_set_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
11020 struct tg3
*tp
= netdev_priv(dev
);
11021 u32 max_rxcoal_tick_int
= 0, max_txcoal_tick_int
= 0;
11022 u32 max_stat_coal_ticks
= 0, min_stat_coal_ticks
= 0;
11024 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
11025 max_rxcoal_tick_int
= MAX_RXCOAL_TICK_INT
;
11026 max_txcoal_tick_int
= MAX_TXCOAL_TICK_INT
;
11027 max_stat_coal_ticks
= MAX_STAT_COAL_TICKS
;
11028 min_stat_coal_ticks
= MIN_STAT_COAL_TICKS
;
11031 if ((ec
->rx_coalesce_usecs
> MAX_RXCOL_TICKS
) ||
11032 (ec
->tx_coalesce_usecs
> MAX_TXCOL_TICKS
) ||
11033 (ec
->rx_max_coalesced_frames
> MAX_RXMAX_FRAMES
) ||
11034 (ec
->tx_max_coalesced_frames
> MAX_TXMAX_FRAMES
) ||
11035 (ec
->rx_coalesce_usecs_irq
> max_rxcoal_tick_int
) ||
11036 (ec
->tx_coalesce_usecs_irq
> max_txcoal_tick_int
) ||
11037 (ec
->rx_max_coalesced_frames_irq
> MAX_RXCOAL_MAXF_INT
) ||
11038 (ec
->tx_max_coalesced_frames_irq
> MAX_TXCOAL_MAXF_INT
) ||
11039 (ec
->stats_block_coalesce_usecs
> max_stat_coal_ticks
) ||
11040 (ec
->stats_block_coalesce_usecs
< min_stat_coal_ticks
))
11043 /* No rx interrupts will be generated if both are zero */
11044 if ((ec
->rx_coalesce_usecs
== 0) &&
11045 (ec
->rx_max_coalesced_frames
== 0))
11048 /* No tx interrupts will be generated if both are zero */
11049 if ((ec
->tx_coalesce_usecs
== 0) &&
11050 (ec
->tx_max_coalesced_frames
== 0))
11053 /* Only copy relevant parameters, ignore all others. */
11054 tp
->coal
.rx_coalesce_usecs
= ec
->rx_coalesce_usecs
;
11055 tp
->coal
.tx_coalesce_usecs
= ec
->tx_coalesce_usecs
;
11056 tp
->coal
.rx_max_coalesced_frames
= ec
->rx_max_coalesced_frames
;
11057 tp
->coal
.tx_max_coalesced_frames
= ec
->tx_max_coalesced_frames
;
11058 tp
->coal
.rx_coalesce_usecs_irq
= ec
->rx_coalesce_usecs_irq
;
11059 tp
->coal
.tx_coalesce_usecs_irq
= ec
->tx_coalesce_usecs_irq
;
11060 tp
->coal
.rx_max_coalesced_frames_irq
= ec
->rx_max_coalesced_frames_irq
;
11061 tp
->coal
.tx_max_coalesced_frames_irq
= ec
->tx_max_coalesced_frames_irq
;
11062 tp
->coal
.stats_block_coalesce_usecs
= ec
->stats_block_coalesce_usecs
;
11064 if (netif_running(dev
)) {
11065 tg3_full_lock(tp
, 0);
11066 __tg3_set_coalesce(tp
, &tp
->coal
);
11067 tg3_full_unlock(tp
);
11072 static const struct ethtool_ops tg3_ethtool_ops
= {
11073 .get_settings
= tg3_get_settings
,
11074 .set_settings
= tg3_set_settings
,
11075 .get_drvinfo
= tg3_get_drvinfo
,
11076 .get_regs_len
= tg3_get_regs_len
,
11077 .get_regs
= tg3_get_regs
,
11078 .get_wol
= tg3_get_wol
,
11079 .set_wol
= tg3_set_wol
,
11080 .get_msglevel
= tg3_get_msglevel
,
11081 .set_msglevel
= tg3_set_msglevel
,
11082 .nway_reset
= tg3_nway_reset
,
11083 .get_link
= ethtool_op_get_link
,
11084 .get_eeprom_len
= tg3_get_eeprom_len
,
11085 .get_eeprom
= tg3_get_eeprom
,
11086 .set_eeprom
= tg3_set_eeprom
,
11087 .get_ringparam
= tg3_get_ringparam
,
11088 .set_ringparam
= tg3_set_ringparam
,
11089 .get_pauseparam
= tg3_get_pauseparam
,
11090 .set_pauseparam
= tg3_set_pauseparam
,
11091 .get_rx_csum
= tg3_get_rx_csum
,
11092 .set_rx_csum
= tg3_set_rx_csum
,
11093 .set_tx_csum
= tg3_set_tx_csum
,
11094 .set_sg
= ethtool_op_set_sg
,
11095 .set_tso
= tg3_set_tso
,
11096 .self_test
= tg3_self_test
,
11097 .get_strings
= tg3_get_strings
,
11098 .phys_id
= tg3_phys_id
,
11099 .get_ethtool_stats
= tg3_get_ethtool_stats
,
11100 .get_coalesce
= tg3_get_coalesce
,
11101 .set_coalesce
= tg3_set_coalesce
,
11102 .get_sset_count
= tg3_get_sset_count
,
11105 static void __devinit
tg3_get_eeprom_size(struct tg3
*tp
)
11107 u32 cursize
, val
, magic
;
11109 tp
->nvram_size
= EEPROM_CHIP_SIZE
;
11111 if (tg3_nvram_read(tp
, 0, &magic
) != 0)
11114 if ((magic
!= TG3_EEPROM_MAGIC
) &&
11115 ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) != TG3_EEPROM_MAGIC_FW
) &&
11116 ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) != TG3_EEPROM_MAGIC_HW
))
11120 * Size the chip by reading offsets at increasing powers of two.
11121 * When we encounter our validation signature, we know the addressing
11122 * has wrapped around, and thus have our chip size.
11126 while (cursize
< tp
->nvram_size
) {
11127 if (tg3_nvram_read(tp
, cursize
, &val
) != 0)
11136 tp
->nvram_size
= cursize
;
11139 static void __devinit
tg3_get_nvram_size(struct tg3
*tp
)
11143 if ((tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) ||
11144 tg3_nvram_read(tp
, 0, &val
) != 0)
11147 /* Selfboot format */
11148 if (val
!= TG3_EEPROM_MAGIC
) {
11149 tg3_get_eeprom_size(tp
);
11153 if (tg3_nvram_read(tp
, 0xf0, &val
) == 0) {
11155 /* This is confusing. We want to operate on the
11156 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11157 * call will read from NVRAM and byteswap the data
11158 * according to the byteswapping settings for all
11159 * other register accesses. This ensures the data we
11160 * want will always reside in the lower 16-bits.
11161 * However, the data in NVRAM is in LE format, which
11162 * means the data from the NVRAM read will always be
11163 * opposite the endianness of the CPU. The 16-bit
11164 * byteswap then brings the data to CPU endianness.
11166 tp
->nvram_size
= swab16((u16
)(val
& 0x0000ffff)) * 1024;
11170 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
11173 static void __devinit
tg3_get_nvram_info(struct tg3
*tp
)
11177 nvcfg1
= tr32(NVRAM_CFG1
);
11178 if (nvcfg1
& NVRAM_CFG1_FLASHIF_ENAB
) {
11179 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11181 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11182 tw32(NVRAM_CFG1
, nvcfg1
);
11185 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
) ||
11186 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
11187 switch (nvcfg1
& NVRAM_CFG1_VENDOR_MASK
) {
11188 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED
:
11189 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11190 tp
->nvram_pagesize
= ATMEL_AT45DB0X1B_PAGE_SIZE
;
11191 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11193 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED
:
11194 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11195 tp
->nvram_pagesize
= ATMEL_AT25F512_PAGE_SIZE
;
11197 case FLASH_VENDOR_ATMEL_EEPROM
:
11198 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11199 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11200 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11202 case FLASH_VENDOR_ST
:
11203 tp
->nvram_jedecnum
= JEDEC_ST
;
11204 tp
->nvram_pagesize
= ST_M45PEX0_PAGE_SIZE
;
11205 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11207 case FLASH_VENDOR_SAIFUN
:
11208 tp
->nvram_jedecnum
= JEDEC_SAIFUN
;
11209 tp
->nvram_pagesize
= SAIFUN_SA25F0XX_PAGE_SIZE
;
11211 case FLASH_VENDOR_SST_SMALL
:
11212 case FLASH_VENDOR_SST_LARGE
:
11213 tp
->nvram_jedecnum
= JEDEC_SST
;
11214 tp
->nvram_pagesize
= SST_25VF0X0_PAGE_SIZE
;
11218 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11219 tp
->nvram_pagesize
= ATMEL_AT45DB0X1B_PAGE_SIZE
;
11220 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11224 static void __devinit
tg3_nvram_get_pagesize(struct tg3
*tp
, u32 nvmcfg1
)
11226 switch (nvmcfg1
& NVRAM_CFG1_5752PAGE_SIZE_MASK
) {
11227 case FLASH_5752PAGE_SIZE_256
:
11228 tp
->nvram_pagesize
= 256;
11230 case FLASH_5752PAGE_SIZE_512
:
11231 tp
->nvram_pagesize
= 512;
11233 case FLASH_5752PAGE_SIZE_1K
:
11234 tp
->nvram_pagesize
= 1024;
11236 case FLASH_5752PAGE_SIZE_2K
:
11237 tp
->nvram_pagesize
= 2048;
11239 case FLASH_5752PAGE_SIZE_4K
:
11240 tp
->nvram_pagesize
= 4096;
11242 case FLASH_5752PAGE_SIZE_264
:
11243 tp
->nvram_pagesize
= 264;
11245 case FLASH_5752PAGE_SIZE_528
:
11246 tp
->nvram_pagesize
= 528;
11251 static void __devinit
tg3_get_5752_nvram_info(struct tg3
*tp
)
11255 nvcfg1
= tr32(NVRAM_CFG1
);
11257 /* NVRAM protection for TPM */
11258 if (nvcfg1
& (1 << 27))
11259 tp
->tg3_flags3
|= TG3_FLG3_PROTECTED_NVRAM
;
11261 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11262 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ
:
11263 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ
:
11264 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11265 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11267 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
11268 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11269 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11270 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11272 case FLASH_5752VENDOR_ST_M45PE10
:
11273 case FLASH_5752VENDOR_ST_M45PE20
:
11274 case FLASH_5752VENDOR_ST_M45PE40
:
11275 tp
->nvram_jedecnum
= JEDEC_ST
;
11276 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11277 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11281 if (tp
->tg3_flags2
& TG3_FLG2_FLASH
) {
11282 tg3_nvram_get_pagesize(tp
, nvcfg1
);
11284 /* For eeprom, set pagesize to maximum eeprom size */
11285 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11287 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11288 tw32(NVRAM_CFG1
, nvcfg1
);
11292 static void __devinit
tg3_get_5755_nvram_info(struct tg3
*tp
)
11294 u32 nvcfg1
, protect
= 0;
11296 nvcfg1
= tr32(NVRAM_CFG1
);
11298 /* NVRAM protection for TPM */
11299 if (nvcfg1
& (1 << 27)) {
11300 tp
->tg3_flags3
|= TG3_FLG3_PROTECTED_NVRAM
;
11304 nvcfg1
&= NVRAM_CFG1_5752VENDOR_MASK
;
11306 case FLASH_5755VENDOR_ATMEL_FLASH_1
:
11307 case FLASH_5755VENDOR_ATMEL_FLASH_2
:
11308 case FLASH_5755VENDOR_ATMEL_FLASH_3
:
11309 case FLASH_5755VENDOR_ATMEL_FLASH_5
:
11310 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11311 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11312 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11313 tp
->nvram_pagesize
= 264;
11314 if (nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_1
||
11315 nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_5
)
11316 tp
->nvram_size
= (protect
? 0x3e200 :
11317 TG3_NVRAM_SIZE_512KB
);
11318 else if (nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_2
)
11319 tp
->nvram_size
= (protect
? 0x1f200 :
11320 TG3_NVRAM_SIZE_256KB
);
11322 tp
->nvram_size
= (protect
? 0x1f200 :
11323 TG3_NVRAM_SIZE_128KB
);
11325 case FLASH_5752VENDOR_ST_M45PE10
:
11326 case FLASH_5752VENDOR_ST_M45PE20
:
11327 case FLASH_5752VENDOR_ST_M45PE40
:
11328 tp
->nvram_jedecnum
= JEDEC_ST
;
11329 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11330 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11331 tp
->nvram_pagesize
= 256;
11332 if (nvcfg1
== FLASH_5752VENDOR_ST_M45PE10
)
11333 tp
->nvram_size
= (protect
?
11334 TG3_NVRAM_SIZE_64KB
:
11335 TG3_NVRAM_SIZE_128KB
);
11336 else if (nvcfg1
== FLASH_5752VENDOR_ST_M45PE20
)
11337 tp
->nvram_size
= (protect
?
11338 TG3_NVRAM_SIZE_64KB
:
11339 TG3_NVRAM_SIZE_256KB
);
11341 tp
->nvram_size
= (protect
?
11342 TG3_NVRAM_SIZE_128KB
:
11343 TG3_NVRAM_SIZE_512KB
);
11348 static void __devinit
tg3_get_5787_nvram_info(struct tg3
*tp
)
11352 nvcfg1
= tr32(NVRAM_CFG1
);
11354 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11355 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ
:
11356 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ
:
11357 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ
:
11358 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ
:
11359 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11360 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11361 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11363 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11364 tw32(NVRAM_CFG1
, nvcfg1
);
11366 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
11367 case FLASH_5755VENDOR_ATMEL_FLASH_1
:
11368 case FLASH_5755VENDOR_ATMEL_FLASH_2
:
11369 case FLASH_5755VENDOR_ATMEL_FLASH_3
:
11370 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11371 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11372 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11373 tp
->nvram_pagesize
= 264;
11375 case FLASH_5752VENDOR_ST_M45PE10
:
11376 case FLASH_5752VENDOR_ST_M45PE20
:
11377 case FLASH_5752VENDOR_ST_M45PE40
:
11378 tp
->nvram_jedecnum
= JEDEC_ST
;
11379 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11380 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11381 tp
->nvram_pagesize
= 256;
11386 static void __devinit
tg3_get_5761_nvram_info(struct tg3
*tp
)
11388 u32 nvcfg1
, protect
= 0;
11390 nvcfg1
= tr32(NVRAM_CFG1
);
11392 /* NVRAM protection for TPM */
11393 if (nvcfg1
& (1 << 27)) {
11394 tp
->tg3_flags3
|= TG3_FLG3_PROTECTED_NVRAM
;
11398 nvcfg1
&= NVRAM_CFG1_5752VENDOR_MASK
;
11400 case FLASH_5761VENDOR_ATMEL_ADB021D
:
11401 case FLASH_5761VENDOR_ATMEL_ADB041D
:
11402 case FLASH_5761VENDOR_ATMEL_ADB081D
:
11403 case FLASH_5761VENDOR_ATMEL_ADB161D
:
11404 case FLASH_5761VENDOR_ATMEL_MDB021D
:
11405 case FLASH_5761VENDOR_ATMEL_MDB041D
:
11406 case FLASH_5761VENDOR_ATMEL_MDB081D
:
11407 case FLASH_5761VENDOR_ATMEL_MDB161D
:
11408 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11409 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11410 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11411 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
11412 tp
->nvram_pagesize
= 256;
11414 case FLASH_5761VENDOR_ST_A_M45PE20
:
11415 case FLASH_5761VENDOR_ST_A_M45PE40
:
11416 case FLASH_5761VENDOR_ST_A_M45PE80
:
11417 case FLASH_5761VENDOR_ST_A_M45PE16
:
11418 case FLASH_5761VENDOR_ST_M_M45PE20
:
11419 case FLASH_5761VENDOR_ST_M_M45PE40
:
11420 case FLASH_5761VENDOR_ST_M_M45PE80
:
11421 case FLASH_5761VENDOR_ST_M_M45PE16
:
11422 tp
->nvram_jedecnum
= JEDEC_ST
;
11423 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11424 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11425 tp
->nvram_pagesize
= 256;
11430 tp
->nvram_size
= tr32(NVRAM_ADDR_LOCKOUT
);
11433 case FLASH_5761VENDOR_ATMEL_ADB161D
:
11434 case FLASH_5761VENDOR_ATMEL_MDB161D
:
11435 case FLASH_5761VENDOR_ST_A_M45PE16
:
11436 case FLASH_5761VENDOR_ST_M_M45PE16
:
11437 tp
->nvram_size
= TG3_NVRAM_SIZE_2MB
;
11439 case FLASH_5761VENDOR_ATMEL_ADB081D
:
11440 case FLASH_5761VENDOR_ATMEL_MDB081D
:
11441 case FLASH_5761VENDOR_ST_A_M45PE80
:
11442 case FLASH_5761VENDOR_ST_M_M45PE80
:
11443 tp
->nvram_size
= TG3_NVRAM_SIZE_1MB
;
11445 case FLASH_5761VENDOR_ATMEL_ADB041D
:
11446 case FLASH_5761VENDOR_ATMEL_MDB041D
:
11447 case FLASH_5761VENDOR_ST_A_M45PE40
:
11448 case FLASH_5761VENDOR_ST_M_M45PE40
:
11449 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
11451 case FLASH_5761VENDOR_ATMEL_ADB021D
:
11452 case FLASH_5761VENDOR_ATMEL_MDB021D
:
11453 case FLASH_5761VENDOR_ST_A_M45PE20
:
11454 case FLASH_5761VENDOR_ST_M_M45PE20
:
11455 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11461 static void __devinit
tg3_get_5906_nvram_info(struct tg3
*tp
)
11463 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11464 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11465 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11468 static void __devinit
tg3_get_57780_nvram_info(struct tg3
*tp
)
11472 nvcfg1
= tr32(NVRAM_CFG1
);
11474 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11475 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ
:
11476 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ
:
11477 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11478 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11479 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11481 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11482 tw32(NVRAM_CFG1
, nvcfg1
);
11484 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
11485 case FLASH_57780VENDOR_ATMEL_AT45DB011D
:
11486 case FLASH_57780VENDOR_ATMEL_AT45DB011B
:
11487 case FLASH_57780VENDOR_ATMEL_AT45DB021D
:
11488 case FLASH_57780VENDOR_ATMEL_AT45DB021B
:
11489 case FLASH_57780VENDOR_ATMEL_AT45DB041D
:
11490 case FLASH_57780VENDOR_ATMEL_AT45DB041B
:
11491 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11492 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11493 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11495 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11496 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
11497 case FLASH_57780VENDOR_ATMEL_AT45DB011D
:
11498 case FLASH_57780VENDOR_ATMEL_AT45DB011B
:
11499 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
11501 case FLASH_57780VENDOR_ATMEL_AT45DB021D
:
11502 case FLASH_57780VENDOR_ATMEL_AT45DB021B
:
11503 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11505 case FLASH_57780VENDOR_ATMEL_AT45DB041D
:
11506 case FLASH_57780VENDOR_ATMEL_AT45DB041B
:
11507 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
11511 case FLASH_5752VENDOR_ST_M45PE10
:
11512 case FLASH_5752VENDOR_ST_M45PE20
:
11513 case FLASH_5752VENDOR_ST_M45PE40
:
11514 tp
->nvram_jedecnum
= JEDEC_ST
;
11515 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11516 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11518 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11519 case FLASH_5752VENDOR_ST_M45PE10
:
11520 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
11522 case FLASH_5752VENDOR_ST_M45PE20
:
11523 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11525 case FLASH_5752VENDOR_ST_M45PE40
:
11526 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
11531 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM
;
11535 tg3_nvram_get_pagesize(tp
, nvcfg1
);
11536 if (tp
->nvram_pagesize
!= 264 && tp
->nvram_pagesize
!= 528)
11537 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
11541 static void __devinit
tg3_get_5717_nvram_info(struct tg3
*tp
)
11545 nvcfg1
= tr32(NVRAM_CFG1
);
11547 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11548 case FLASH_5717VENDOR_ATMEL_EEPROM
:
11549 case FLASH_5717VENDOR_MICRO_EEPROM
:
11550 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11551 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11552 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
11554 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
11555 tw32(NVRAM_CFG1
, nvcfg1
);
11557 case FLASH_5717VENDOR_ATMEL_MDB011D
:
11558 case FLASH_5717VENDOR_ATMEL_ADB011B
:
11559 case FLASH_5717VENDOR_ATMEL_ADB011D
:
11560 case FLASH_5717VENDOR_ATMEL_MDB021D
:
11561 case FLASH_5717VENDOR_ATMEL_ADB021B
:
11562 case FLASH_5717VENDOR_ATMEL_ADB021D
:
11563 case FLASH_5717VENDOR_ATMEL_45USPT
:
11564 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
11565 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11566 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11568 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11569 case FLASH_5717VENDOR_ATMEL_MDB021D
:
11570 case FLASH_5717VENDOR_ATMEL_ADB021B
:
11571 case FLASH_5717VENDOR_ATMEL_ADB021D
:
11572 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11575 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
11579 case FLASH_5717VENDOR_ST_M_M25PE10
:
11580 case FLASH_5717VENDOR_ST_A_M25PE10
:
11581 case FLASH_5717VENDOR_ST_M_M45PE10
:
11582 case FLASH_5717VENDOR_ST_A_M45PE10
:
11583 case FLASH_5717VENDOR_ST_M_M25PE20
:
11584 case FLASH_5717VENDOR_ST_A_M25PE20
:
11585 case FLASH_5717VENDOR_ST_M_M45PE20
:
11586 case FLASH_5717VENDOR_ST_A_M45PE20
:
11587 case FLASH_5717VENDOR_ST_25USPT
:
11588 case FLASH_5717VENDOR_ST_45USPT
:
11589 tp
->nvram_jedecnum
= JEDEC_ST
;
11590 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
11591 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
11593 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
11594 case FLASH_5717VENDOR_ST_M_M25PE20
:
11595 case FLASH_5717VENDOR_ST_A_M25PE20
:
11596 case FLASH_5717VENDOR_ST_M_M45PE20
:
11597 case FLASH_5717VENDOR_ST_A_M45PE20
:
11598 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
11601 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
11606 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM
;
11610 tg3_nvram_get_pagesize(tp
, nvcfg1
);
11611 if (tp
->nvram_pagesize
!= 264 && tp
->nvram_pagesize
!= 528)
11612 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
11615 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11616 static void __devinit
tg3_nvram_init(struct tg3
*tp
)
11618 tw32_f(GRC_EEPROM_ADDR
,
11619 (EEPROM_ADDR_FSM_RESET
|
11620 (EEPROM_DEFAULT_CLOCK_PERIOD
<<
11621 EEPROM_ADDR_CLKPERD_SHIFT
)));
11625 /* Enable seeprom accesses. */
11626 tw32_f(GRC_LOCAL_CTRL
,
11627 tr32(GRC_LOCAL_CTRL
) | GRC_LCLCTRL_AUTO_SEEPROM
);
11630 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
11631 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) {
11632 tp
->tg3_flags
|= TG3_FLAG_NVRAM
;
11634 if (tg3_nvram_lock(tp
)) {
11635 netdev_warn(tp
->dev
,
11636 "Cannot get nvram lock, %s failed\n",
11640 tg3_enable_nvram_access(tp
);
11642 tp
->nvram_size
= 0;
11644 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
11645 tg3_get_5752_nvram_info(tp
);
11646 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
11647 tg3_get_5755_nvram_info(tp
);
11648 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
11649 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
11650 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
11651 tg3_get_5787_nvram_info(tp
);
11652 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
11653 tg3_get_5761_nvram_info(tp
);
11654 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
11655 tg3_get_5906_nvram_info(tp
);
11656 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
11657 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
11658 tg3_get_57780_nvram_info(tp
);
11659 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
)
11660 tg3_get_5717_nvram_info(tp
);
11662 tg3_get_nvram_info(tp
);
11664 if (tp
->nvram_size
== 0)
11665 tg3_get_nvram_size(tp
);
11667 tg3_disable_nvram_access(tp
);
11668 tg3_nvram_unlock(tp
);
11671 tp
->tg3_flags
&= ~(TG3_FLAG_NVRAM
| TG3_FLAG_NVRAM_BUFFERED
);
11673 tg3_get_eeprom_size(tp
);
11677 static int tg3_nvram_write_block_using_eeprom(struct tg3
*tp
,
11678 u32 offset
, u32 len
, u8
*buf
)
11683 for (i
= 0; i
< len
; i
+= 4) {
11689 memcpy(&data
, buf
+ i
, 4);
11692 * The SEEPROM interface expects the data to always be opposite
11693 * the native endian format. We accomplish this by reversing
11694 * all the operations that would have been performed on the
11695 * data from a call to tg3_nvram_read_be32().
11697 tw32(GRC_EEPROM_DATA
, swab32(be32_to_cpu(data
)));
11699 val
= tr32(GRC_EEPROM_ADDR
);
11700 tw32(GRC_EEPROM_ADDR
, val
| EEPROM_ADDR_COMPLETE
);
11702 val
&= ~(EEPROM_ADDR_ADDR_MASK
| EEPROM_ADDR_DEVID_MASK
|
11704 tw32(GRC_EEPROM_ADDR
, val
|
11705 (0 << EEPROM_ADDR_DEVID_SHIFT
) |
11706 (addr
& EEPROM_ADDR_ADDR_MASK
) |
11707 EEPROM_ADDR_START
|
11708 EEPROM_ADDR_WRITE
);
11710 for (j
= 0; j
< 1000; j
++) {
11711 val
= tr32(GRC_EEPROM_ADDR
);
11713 if (val
& EEPROM_ADDR_COMPLETE
)
11717 if (!(val
& EEPROM_ADDR_COMPLETE
)) {
11726 /* offset and length are dword aligned */
11727 static int tg3_nvram_write_block_unbuffered(struct tg3
*tp
, u32 offset
, u32 len
,
11731 u32 pagesize
= tp
->nvram_pagesize
;
11732 u32 pagemask
= pagesize
- 1;
11736 tmp
= kmalloc(pagesize
, GFP_KERNEL
);
11742 u32 phy_addr
, page_off
, size
;
11744 phy_addr
= offset
& ~pagemask
;
11746 for (j
= 0; j
< pagesize
; j
+= 4) {
11747 ret
= tg3_nvram_read_be32(tp
, phy_addr
+ j
,
11748 (__be32
*) (tmp
+ j
));
11755 page_off
= offset
& pagemask
;
11762 memcpy(tmp
+ page_off
, buf
, size
);
11764 offset
= offset
+ (pagesize
- page_off
);
11766 tg3_enable_nvram_access(tp
);
11769 * Before we can erase the flash page, we need
11770 * to issue a special "write enable" command.
11772 nvram_cmd
= NVRAM_CMD_WREN
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
11774 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
11777 /* Erase the target page */
11778 tw32(NVRAM_ADDR
, phy_addr
);
11780 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
| NVRAM_CMD_WR
|
11781 NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
| NVRAM_CMD_ERASE
;
11783 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
11786 /* Issue another write enable to start the write. */
11787 nvram_cmd
= NVRAM_CMD_WREN
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
11789 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
11792 for (j
= 0; j
< pagesize
; j
+= 4) {
11795 data
= *((__be32
*) (tmp
+ j
));
11797 tw32(NVRAM_WRDATA
, be32_to_cpu(data
));
11799 tw32(NVRAM_ADDR
, phy_addr
+ j
);
11801 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
|
11805 nvram_cmd
|= NVRAM_CMD_FIRST
;
11806 else if (j
== (pagesize
- 4))
11807 nvram_cmd
|= NVRAM_CMD_LAST
;
11809 if ((ret
= tg3_nvram_exec_cmd(tp
, nvram_cmd
)))
11816 nvram_cmd
= NVRAM_CMD_WRDI
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
11817 tg3_nvram_exec_cmd(tp
, nvram_cmd
);
11824 /* offset and length are dword aligned */
11825 static int tg3_nvram_write_block_buffered(struct tg3
*tp
, u32 offset
, u32 len
,
11830 for (i
= 0; i
< len
; i
+= 4, offset
+= 4) {
11831 u32 page_off
, phy_addr
, nvram_cmd
;
11834 memcpy(&data
, buf
+ i
, 4);
11835 tw32(NVRAM_WRDATA
, be32_to_cpu(data
));
11837 page_off
= offset
% tp
->nvram_pagesize
;
11839 phy_addr
= tg3_nvram_phys_addr(tp
, offset
);
11841 tw32(NVRAM_ADDR
, phy_addr
);
11843 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
| NVRAM_CMD_WR
;
11845 if (page_off
== 0 || i
== 0)
11846 nvram_cmd
|= NVRAM_CMD_FIRST
;
11847 if (page_off
== (tp
->nvram_pagesize
- 4))
11848 nvram_cmd
|= NVRAM_CMD_LAST
;
11850 if (i
== (len
- 4))
11851 nvram_cmd
|= NVRAM_CMD_LAST
;
11853 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5752
&&
11854 !(tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) &&
11855 (tp
->nvram_jedecnum
== JEDEC_ST
) &&
11856 (nvram_cmd
& NVRAM_CMD_FIRST
)) {
11858 if ((ret
= tg3_nvram_exec_cmd(tp
,
11859 NVRAM_CMD_WREN
| NVRAM_CMD_GO
|
11864 if (!(tp
->tg3_flags2
& TG3_FLG2_FLASH
)) {
11865 /* We always do complete word writes to eeprom. */
11866 nvram_cmd
|= (NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
);
11869 if ((ret
= tg3_nvram_exec_cmd(tp
, nvram_cmd
)))
11875 /* offset and length are dword aligned */
11876 static int tg3_nvram_write_block(struct tg3
*tp
, u32 offset
, u32 len
, u8
*buf
)
11880 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
) {
11881 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
&
11882 ~GRC_LCLCTRL_GPIO_OUTPUT1
);
11886 if (!(tp
->tg3_flags
& TG3_FLAG_NVRAM
)) {
11887 ret
= tg3_nvram_write_block_using_eeprom(tp
, offset
, len
, buf
);
11891 ret
= tg3_nvram_lock(tp
);
11895 tg3_enable_nvram_access(tp
);
11896 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
11897 !(tp
->tg3_flags3
& TG3_FLG3_PROTECTED_NVRAM
))
11898 tw32(NVRAM_WRITE1
, 0x406);
11900 grc_mode
= tr32(GRC_MODE
);
11901 tw32(GRC_MODE
, grc_mode
| GRC_MODE_NVRAM_WR_ENABLE
);
11903 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) ||
11904 !(tp
->tg3_flags2
& TG3_FLG2_FLASH
)) {
11906 ret
= tg3_nvram_write_block_buffered(tp
, offset
, len
,
11909 ret
= tg3_nvram_write_block_unbuffered(tp
, offset
, len
,
11913 grc_mode
= tr32(GRC_MODE
);
11914 tw32(GRC_MODE
, grc_mode
& ~GRC_MODE_NVRAM_WR_ENABLE
);
11916 tg3_disable_nvram_access(tp
);
11917 tg3_nvram_unlock(tp
);
11920 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
) {
11921 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
11928 struct subsys_tbl_ent
{
11929 u16 subsys_vendor
, subsys_devid
;
11933 static struct subsys_tbl_ent subsys_id_to_phy_id
[] __devinitdata
= {
11934 /* Broadcom boards. */
11935 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11936 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6
, TG3_PHY_ID_BCM5401
},
11937 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11938 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5
, TG3_PHY_ID_BCM5701
},
11939 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11940 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6
, TG3_PHY_ID_BCM8002
},
11941 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11942 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9
, 0 },
11943 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11944 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1
, TG3_PHY_ID_BCM5701
},
11945 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11946 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8
, TG3_PHY_ID_BCM5701
},
11947 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11948 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7
, 0 },
11949 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11950 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10
, TG3_PHY_ID_BCM5701
},
11951 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11952 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12
, TG3_PHY_ID_BCM5701
},
11953 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11954 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1
, TG3_PHY_ID_BCM5703
},
11955 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
11956 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2
, TG3_PHY_ID_BCM5703
},
11959 { TG3PCI_SUBVENDOR_ID_3COM
,
11960 TG3PCI_SUBDEVICE_ID_3COM_3C996T
, TG3_PHY_ID_BCM5401
},
11961 { TG3PCI_SUBVENDOR_ID_3COM
,
11962 TG3PCI_SUBDEVICE_ID_3COM_3C996BT
, TG3_PHY_ID_BCM5701
},
11963 { TG3PCI_SUBVENDOR_ID_3COM
,
11964 TG3PCI_SUBDEVICE_ID_3COM_3C996SX
, 0 },
11965 { TG3PCI_SUBVENDOR_ID_3COM
,
11966 TG3PCI_SUBDEVICE_ID_3COM_3C1000T
, TG3_PHY_ID_BCM5701
},
11967 { TG3PCI_SUBVENDOR_ID_3COM
,
11968 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01
, TG3_PHY_ID_BCM5701
},
11971 { TG3PCI_SUBVENDOR_ID_DELL
,
11972 TG3PCI_SUBDEVICE_ID_DELL_VIPER
, TG3_PHY_ID_BCM5401
},
11973 { TG3PCI_SUBVENDOR_ID_DELL
,
11974 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR
, TG3_PHY_ID_BCM5401
},
11975 { TG3PCI_SUBVENDOR_ID_DELL
,
11976 TG3PCI_SUBDEVICE_ID_DELL_MERLOT
, TG3_PHY_ID_BCM5411
},
11977 { TG3PCI_SUBVENDOR_ID_DELL
,
11978 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT
, TG3_PHY_ID_BCM5411
},
11980 /* Compaq boards. */
11981 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
11982 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE
, TG3_PHY_ID_BCM5701
},
11983 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
11984 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2
, TG3_PHY_ID_BCM5701
},
11985 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
11986 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING
, 0 },
11987 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
11988 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780
, TG3_PHY_ID_BCM5701
},
11989 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
11990 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2
, TG3_PHY_ID_BCM5701
},
11993 { TG3PCI_SUBVENDOR_ID_IBM
,
11994 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2
, 0 }
11997 static struct subsys_tbl_ent
* __devinit
tg3_lookup_by_subsys(struct tg3
*tp
)
12001 for (i
= 0; i
< ARRAY_SIZE(subsys_id_to_phy_id
); i
++) {
12002 if ((subsys_id_to_phy_id
[i
].subsys_vendor
==
12003 tp
->pdev
->subsystem_vendor
) &&
12004 (subsys_id_to_phy_id
[i
].subsys_devid
==
12005 tp
->pdev
->subsystem_device
))
12006 return &subsys_id_to_phy_id
[i
];
12011 static void __devinit
tg3_get_eeprom_hw_cfg(struct tg3
*tp
)
12016 /* On some early chips the SRAM cannot be accessed in D3hot state,
12017 * so need make sure we're in D0.
12019 pci_read_config_word(tp
->pdev
, tp
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
12020 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
12021 pci_write_config_word(tp
->pdev
, tp
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
12024 /* Make sure register accesses (indirect or otherwise)
12025 * will function correctly.
12027 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
12028 tp
->misc_host_ctrl
);
12030 /* The memory arbiter has to be enabled in order for SRAM accesses
12031 * to succeed. Normally on powerup the tg3 chip firmware will make
12032 * sure it is enabled, but other entities such as system netboot
12033 * code might disable it.
12035 val
= tr32(MEMARB_MODE
);
12036 tw32(MEMARB_MODE
, val
| MEMARB_MODE_ENABLE
);
12038 tp
->phy_id
= TG3_PHY_ID_INVALID
;
12039 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
12041 /* Assume an onboard device and WOL capable by default. */
12042 tp
->tg3_flags
|= TG3_FLAG_EEPROM_WRITE_PROT
| TG3_FLAG_WOL_CAP
;
12044 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
12045 if (!(tr32(PCIE_TRANSACTION_CFG
) & PCIE_TRANS_CFG_LOM
)) {
12046 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
12047 tp
->tg3_flags2
|= TG3_FLG2_IS_NIC
;
12049 val
= tr32(VCPU_CFGSHDW
);
12050 if (val
& VCPU_CFGSHDW_ASPM_DBNC
)
12051 tp
->tg3_flags
|= TG3_FLAG_ASPM_WORKAROUND
;
12052 if ((val
& VCPU_CFGSHDW_WOL_ENABLE
) &&
12053 (val
& VCPU_CFGSHDW_WOL_MAGPKT
))
12054 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
12058 tg3_read_mem(tp
, NIC_SRAM_DATA_SIG
, &val
);
12059 if (val
== NIC_SRAM_DATA_SIG_MAGIC
) {
12060 u32 nic_cfg
, led_cfg
;
12061 u32 nic_phy_id
, ver
, cfg2
= 0, cfg4
= 0, eeprom_phy_id
;
12062 int eeprom_phy_serdes
= 0;
12064 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG
, &nic_cfg
);
12065 tp
->nic_sram_data_cfg
= nic_cfg
;
12067 tg3_read_mem(tp
, NIC_SRAM_DATA_VER
, &ver
);
12068 ver
>>= NIC_SRAM_DATA_VER_SHIFT
;
12069 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
) &&
12070 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) &&
12071 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5703
) &&
12072 (ver
> 0) && (ver
< 0x100))
12073 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_2
, &cfg2
);
12075 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
12076 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_4
, &cfg4
);
12078 if ((nic_cfg
& NIC_SRAM_DATA_CFG_PHY_TYPE_MASK
) ==
12079 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER
)
12080 eeprom_phy_serdes
= 1;
12082 tg3_read_mem(tp
, NIC_SRAM_DATA_PHY_ID
, &nic_phy_id
);
12083 if (nic_phy_id
!= 0) {
12084 u32 id1
= nic_phy_id
& NIC_SRAM_DATA_PHY_ID1_MASK
;
12085 u32 id2
= nic_phy_id
& NIC_SRAM_DATA_PHY_ID2_MASK
;
12087 eeprom_phy_id
= (id1
>> 16) << 10;
12088 eeprom_phy_id
|= (id2
& 0xfc00) << 16;
12089 eeprom_phy_id
|= (id2
& 0x03ff) << 0;
12093 tp
->phy_id
= eeprom_phy_id
;
12094 if (eeprom_phy_serdes
) {
12095 if ((tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
12096 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
)
12097 tp
->tg3_flags2
|= TG3_FLG2_MII_SERDES
;
12099 tp
->tg3_flags2
|= TG3_FLG2_PHY_SERDES
;
12102 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
12103 led_cfg
= cfg2
& (NIC_SRAM_DATA_CFG_LED_MODE_MASK
|
12104 SHASTA_EXT_LED_MODE_MASK
);
12106 led_cfg
= nic_cfg
& NIC_SRAM_DATA_CFG_LED_MODE_MASK
;
12110 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1
:
12111 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
12114 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2
:
12115 tp
->led_ctrl
= LED_CTRL_MODE_PHY_2
;
12118 case NIC_SRAM_DATA_CFG_LED_MODE_MAC
:
12119 tp
->led_ctrl
= LED_CTRL_MODE_MAC
;
12121 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12122 * read on some older 5700/5701 bootcode.
12124 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
12126 GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
12128 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
12132 case SHASTA_EXT_LED_SHARED
:
12133 tp
->led_ctrl
= LED_CTRL_MODE_SHARED
;
12134 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
&&
12135 tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A1
)
12136 tp
->led_ctrl
|= (LED_CTRL_MODE_PHY_1
|
12137 LED_CTRL_MODE_PHY_2
);
12140 case SHASTA_EXT_LED_MAC
:
12141 tp
->led_ctrl
= LED_CTRL_MODE_SHASTA_MAC
;
12144 case SHASTA_EXT_LED_COMBO
:
12145 tp
->led_ctrl
= LED_CTRL_MODE_COMBO
;
12146 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
)
12147 tp
->led_ctrl
|= (LED_CTRL_MODE_PHY_1
|
12148 LED_CTRL_MODE_PHY_2
);
12153 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
12154 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) &&
12155 tp
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
)
12156 tp
->led_ctrl
= LED_CTRL_MODE_PHY_2
;
12158 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
)
12159 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
12161 if (nic_cfg
& NIC_SRAM_DATA_CFG_EEPROM_WP
) {
12162 tp
->tg3_flags
|= TG3_FLAG_EEPROM_WRITE_PROT
;
12163 if ((tp
->pdev
->subsystem_vendor
==
12164 PCI_VENDOR_ID_ARIMA
) &&
12165 (tp
->pdev
->subsystem_device
== 0x205a ||
12166 tp
->pdev
->subsystem_device
== 0x2063))
12167 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
12169 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
12170 tp
->tg3_flags2
|= TG3_FLG2_IS_NIC
;
12173 if (nic_cfg
& NIC_SRAM_DATA_CFG_ASF_ENABLE
) {
12174 tp
->tg3_flags
|= TG3_FLAG_ENABLE_ASF
;
12175 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
12176 tp
->tg3_flags2
|= TG3_FLG2_ASF_NEW_HANDSHAKE
;
12179 if ((nic_cfg
& NIC_SRAM_DATA_CFG_APE_ENABLE
) &&
12180 (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
12181 tp
->tg3_flags3
|= TG3_FLG3_ENABLE_APE
;
12183 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
&&
12184 !(nic_cfg
& NIC_SRAM_DATA_CFG_FIBER_WOL
))
12185 tp
->tg3_flags
&= ~TG3_FLAG_WOL_CAP
;
12187 if ((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) &&
12188 (nic_cfg
& NIC_SRAM_DATA_CFG_WOL_ENABLE
))
12189 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
12191 if (cfg2
& (1 << 17))
12192 tp
->tg3_flags2
|= TG3_FLG2_CAPACITIVE_COUPLING
;
12194 /* serdes signal pre-emphasis in register 0x590 set by */
12195 /* bootcode if bit 18 is set */
12196 if (cfg2
& (1 << 18))
12197 tp
->tg3_flags2
|= TG3_FLG2_SERDES_PREEMPHASIS
;
12199 if (((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
12200 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
)) &&
12201 (cfg2
& NIC_SRAM_DATA_CFG_2_APD_EN
))
12202 tp
->tg3_flags3
|= TG3_FLG3_PHY_ENABLE_APD
;
12204 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
12207 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_3
, &cfg3
);
12208 if (cfg3
& NIC_SRAM_ASPM_DEBOUNCE
)
12209 tp
->tg3_flags
|= TG3_FLAG_ASPM_WORKAROUND
;
12212 if (cfg4
& NIC_SRAM_RGMII_INBAND_DISABLE
)
12213 tp
->tg3_flags3
|= TG3_FLG3_RGMII_INBAND_DISABLE
;
12214 if (cfg4
& NIC_SRAM_RGMII_EXT_IBND_RX_EN
)
12215 tp
->tg3_flags3
|= TG3_FLG3_RGMII_EXT_IBND_RX_EN
;
12216 if (cfg4
& NIC_SRAM_RGMII_EXT_IBND_TX_EN
)
12217 tp
->tg3_flags3
|= TG3_FLG3_RGMII_EXT_IBND_TX_EN
;
12220 device_init_wakeup(&tp
->pdev
->dev
, tp
->tg3_flags
& TG3_FLAG_WOL_CAP
);
12221 device_set_wakeup_enable(&tp
->pdev
->dev
,
12222 tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
);
12225 static int __devinit
tg3_issue_otp_command(struct tg3
*tp
, u32 cmd
)
12230 tw32(OTP_CTRL
, cmd
| OTP_CTRL_OTP_CMD_START
);
12231 tw32(OTP_CTRL
, cmd
);
12233 /* Wait for up to 1 ms for command to execute. */
12234 for (i
= 0; i
< 100; i
++) {
12235 val
= tr32(OTP_STATUS
);
12236 if (val
& OTP_STATUS_CMD_DONE
)
12241 return (val
& OTP_STATUS_CMD_DONE
) ? 0 : -EBUSY
;
12244 /* Read the gphy configuration from the OTP region of the chip. The gphy
12245 * configuration is a 32-bit value that straddles the alignment boundary.
12246 * We do two 32-bit reads and then shift and merge the results.
12248 static u32 __devinit
tg3_read_otp_phycfg(struct tg3
*tp
)
12250 u32 bhalf_otp
, thalf_otp
;
12252 tw32(OTP_MODE
, OTP_MODE_OTP_THRU_GRC
);
12254 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_INIT
))
12257 tw32(OTP_ADDRESS
, OTP_ADDRESS_MAGIC1
);
12259 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_READ
))
12262 thalf_otp
= tr32(OTP_READ_DATA
);
12264 tw32(OTP_ADDRESS
, OTP_ADDRESS_MAGIC2
);
12266 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_READ
))
12269 bhalf_otp
= tr32(OTP_READ_DATA
);
12271 return ((thalf_otp
& 0x0000ffff) << 16) | (bhalf_otp
>> 16);
12274 static int __devinit
tg3_phy_probe(struct tg3
*tp
)
12276 u32 hw_phy_id_1
, hw_phy_id_2
;
12277 u32 hw_phy_id
, hw_phy_id_masked
;
12280 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)
12281 return tg3_phy_init(tp
);
12283 /* Reading the PHY ID register can conflict with ASF
12284 * firmware access to the PHY hardware.
12287 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
12288 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
12289 hw_phy_id
= hw_phy_id_masked
= TG3_PHY_ID_INVALID
;
12291 /* Now read the physical PHY_ID from the chip and verify
12292 * that it is sane. If it doesn't look good, we fall back
12293 * to either the hard-coded table based PHY_ID and failing
12294 * that the value found in the eeprom area.
12296 err
|= tg3_readphy(tp
, MII_PHYSID1
, &hw_phy_id_1
);
12297 err
|= tg3_readphy(tp
, MII_PHYSID2
, &hw_phy_id_2
);
12299 hw_phy_id
= (hw_phy_id_1
& 0xffff) << 10;
12300 hw_phy_id
|= (hw_phy_id_2
& 0xfc00) << 16;
12301 hw_phy_id
|= (hw_phy_id_2
& 0x03ff) << 0;
12303 hw_phy_id_masked
= hw_phy_id
& TG3_PHY_ID_MASK
;
12306 if (!err
&& TG3_KNOWN_PHY_ID(hw_phy_id_masked
)) {
12307 tp
->phy_id
= hw_phy_id
;
12308 if (hw_phy_id_masked
== TG3_PHY_ID_BCM8002
)
12309 tp
->tg3_flags2
|= TG3_FLG2_PHY_SERDES
;
12311 tp
->tg3_flags2
&= ~TG3_FLG2_PHY_SERDES
;
12313 if (tp
->phy_id
!= TG3_PHY_ID_INVALID
) {
12314 /* Do nothing, phy ID already set up in
12315 * tg3_get_eeprom_hw_cfg().
12318 struct subsys_tbl_ent
*p
;
12320 /* No eeprom signature? Try the hardcoded
12321 * subsys device table.
12323 p
= tg3_lookup_by_subsys(tp
);
12327 tp
->phy_id
= p
->phy_id
;
12329 tp
->phy_id
== TG3_PHY_ID_BCM8002
)
12330 tp
->tg3_flags2
|= TG3_FLG2_PHY_SERDES
;
12334 if (!(tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
) &&
12335 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) &&
12336 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
12337 u32 bmsr
, adv_reg
, tg3_ctrl
, mask
;
12339 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
12340 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
12341 (bmsr
& BMSR_LSTATUS
))
12342 goto skip_phy_reset
;
12344 err
= tg3_phy_reset(tp
);
12348 adv_reg
= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
12349 ADVERTISE_100HALF
| ADVERTISE_100FULL
|
12350 ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
);
12352 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)) {
12353 tg3_ctrl
= (MII_TG3_CTRL_ADV_1000_HALF
|
12354 MII_TG3_CTRL_ADV_1000_FULL
);
12355 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
12356 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
)
12357 tg3_ctrl
|= (MII_TG3_CTRL_AS_MASTER
|
12358 MII_TG3_CTRL_ENABLE_AS_MASTER
);
12361 mask
= (ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
12362 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
12363 ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
);
12364 if (!tg3_copper_is_advertising_all(tp
, mask
)) {
12365 tg3_writephy(tp
, MII_ADVERTISE
, adv_reg
);
12367 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
))
12368 tg3_writephy(tp
, MII_TG3_CTRL
, tg3_ctrl
);
12370 tg3_writephy(tp
, MII_BMCR
,
12371 BMCR_ANENABLE
| BMCR_ANRESTART
);
12373 tg3_phy_set_wirespeed(tp
);
12375 tg3_writephy(tp
, MII_ADVERTISE
, adv_reg
);
12376 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
))
12377 tg3_writephy(tp
, MII_TG3_CTRL
, tg3_ctrl
);
12381 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5401
) {
12382 err
= tg3_init_5401phy_dsp(tp
);
12386 err
= tg3_init_5401phy_dsp(tp
);
12389 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)
12390 tp
->link_config
.advertising
=
12391 (ADVERTISED_1000baseT_Half
|
12392 ADVERTISED_1000baseT_Full
|
12393 ADVERTISED_Autoneg
|
12395 if (tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)
12396 tp
->link_config
.advertising
&=
12397 ~(ADVERTISED_1000baseT_Half
|
12398 ADVERTISED_1000baseT_Full
);
12403 static void __devinit
tg3_read_vpd(struct tg3
*tp
)
12405 u8 vpd_data
[TG3_NVM_VPD_LEN
];
12406 unsigned int block_end
, rosize
, len
;
12410 if ((tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) ||
12411 tg3_nvram_read(tp
, 0x0, &magic
))
12412 goto out_not_found
;
12414 if (magic
== TG3_EEPROM_MAGIC
) {
12415 for (i
= 0; i
< TG3_NVM_VPD_LEN
; i
+= 4) {
12418 /* The data is in little-endian format in NVRAM.
12419 * Use the big-endian read routines to preserve
12420 * the byte order as it exists in NVRAM.
12422 if (tg3_nvram_read_be32(tp
, TG3_NVM_VPD_OFF
+ i
, &tmp
))
12423 goto out_not_found
;
12425 memcpy(&vpd_data
[i
], &tmp
, sizeof(tmp
));
12429 unsigned int pos
= 0;
12431 for (; pos
< TG3_NVM_VPD_LEN
&& i
< 3; i
++, pos
+= cnt
) {
12432 cnt
= pci_read_vpd(tp
->pdev
, pos
,
12433 TG3_NVM_VPD_LEN
- pos
,
12435 if (cnt
== -ETIMEDOUT
|| -EINTR
)
12438 goto out_not_found
;
12440 if (pos
!= TG3_NVM_VPD_LEN
)
12441 goto out_not_found
;
12444 i
= pci_vpd_find_tag(vpd_data
, 0, TG3_NVM_VPD_LEN
,
12445 PCI_VPD_LRDT_RO_DATA
);
12447 goto out_not_found
;
12449 rosize
= pci_vpd_lrdt_size(&vpd_data
[i
]);
12450 block_end
= i
+ PCI_VPD_LRDT_TAG_SIZE
+ rosize
;
12451 i
+= PCI_VPD_LRDT_TAG_SIZE
;
12453 if (block_end
> TG3_NVM_VPD_LEN
)
12454 goto out_not_found
;
12456 j
= pci_vpd_find_info_keyword(vpd_data
, i
, rosize
,
12457 PCI_VPD_RO_KEYWORD_MFR_ID
);
12459 len
= pci_vpd_info_field_size(&vpd_data
[j
]);
12461 j
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
12462 if (j
+ len
> block_end
|| len
!= 4 ||
12463 memcmp(&vpd_data
[j
], "1028", 4))
12466 j
= pci_vpd_find_info_keyword(vpd_data
, i
, rosize
,
12467 PCI_VPD_RO_KEYWORD_VENDOR0
);
12471 len
= pci_vpd_info_field_size(&vpd_data
[j
]);
12473 j
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
12474 if (j
+ len
> block_end
)
12477 memcpy(tp
->fw_ver
, &vpd_data
[j
], len
);
12478 strncat(tp
->fw_ver
, " bc ", TG3_NVM_VPD_LEN
- len
- 1);
12482 i
= pci_vpd_find_info_keyword(vpd_data
, i
, rosize
,
12483 PCI_VPD_RO_KEYWORD_PARTNO
);
12485 goto out_not_found
;
12487 len
= pci_vpd_info_field_size(&vpd_data
[i
]);
12489 i
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
12490 if (len
> TG3_BPN_SIZE
||
12491 (len
+ i
) > TG3_NVM_VPD_LEN
)
12492 goto out_not_found
;
12494 memcpy(tp
->board_part_number
, &vpd_data
[i
], len
);
12499 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
12500 strcpy(tp
->board_part_number
, "BCM95906");
12501 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
&&
12502 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57780
)
12503 strcpy(tp
->board_part_number
, "BCM57780");
12504 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
&&
12505 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57760
)
12506 strcpy(tp
->board_part_number
, "BCM57760");
12507 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
&&
12508 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57790
)
12509 strcpy(tp
->board_part_number
, "BCM57790");
12510 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
&&
12511 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57788
)
12512 strcpy(tp
->board_part_number
, "BCM57788");
12513 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
&&
12514 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57761
)
12515 strcpy(tp
->board_part_number
, "BCM57761");
12516 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
&&
12517 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57765
)
12518 strcpy(tp
->board_part_number
, "BCM57765");
12519 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
&&
12520 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57781
)
12521 strcpy(tp
->board_part_number
, "BCM57781");
12522 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
&&
12523 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57785
)
12524 strcpy(tp
->board_part_number
, "BCM57785");
12525 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
&&
12526 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57791
)
12527 strcpy(tp
->board_part_number
, "BCM57791");
12528 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
&&
12529 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57795
)
12530 strcpy(tp
->board_part_number
, "BCM57795");
12532 strcpy(tp
->board_part_number
, "none");
12535 static int __devinit
tg3_fw_img_is_valid(struct tg3
*tp
, u32 offset
)
12539 if (tg3_nvram_read(tp
, offset
, &val
) ||
12540 (val
& 0xfc000000) != 0x0c000000 ||
12541 tg3_nvram_read(tp
, offset
+ 4, &val
) ||
12548 static void __devinit
tg3_read_bc_ver(struct tg3
*tp
)
12550 u32 val
, offset
, start
, ver_offset
;
12552 bool newver
= false;
12554 if (tg3_nvram_read(tp
, 0xc, &offset
) ||
12555 tg3_nvram_read(tp
, 0x4, &start
))
12558 offset
= tg3_nvram_logical_addr(tp
, offset
);
12560 if (tg3_nvram_read(tp
, offset
, &val
))
12563 if ((val
& 0xfc000000) == 0x0c000000) {
12564 if (tg3_nvram_read(tp
, offset
+ 4, &val
))
12571 dst_off
= strlen(tp
->fw_ver
);
12574 if (TG3_VER_SIZE
- dst_off
< 16 ||
12575 tg3_nvram_read(tp
, offset
+ 8, &ver_offset
))
12578 offset
= offset
+ ver_offset
- start
;
12579 for (i
= 0; i
< 16; i
+= 4) {
12581 if (tg3_nvram_read_be32(tp
, offset
+ i
, &v
))
12584 memcpy(tp
->fw_ver
+ dst_off
+ i
, &v
, sizeof(v
));
12589 if (tg3_nvram_read(tp
, TG3_NVM_PTREV_BCVER
, &ver_offset
))
12592 major
= (ver_offset
& TG3_NVM_BCVER_MAJMSK
) >>
12593 TG3_NVM_BCVER_MAJSFT
;
12594 minor
= ver_offset
& TG3_NVM_BCVER_MINMSK
;
12595 snprintf(&tp
->fw_ver
[dst_off
], TG3_VER_SIZE
- dst_off
,
12596 "v%d.%02d", major
, minor
);
12600 static void __devinit
tg3_read_hwsb_ver(struct tg3
*tp
)
12602 u32 val
, major
, minor
;
12604 /* Use native endian representation */
12605 if (tg3_nvram_read(tp
, TG3_NVM_HWSB_CFG1
, &val
))
12608 major
= (val
& TG3_NVM_HWSB_CFG1_MAJMSK
) >>
12609 TG3_NVM_HWSB_CFG1_MAJSFT
;
12610 minor
= (val
& TG3_NVM_HWSB_CFG1_MINMSK
) >>
12611 TG3_NVM_HWSB_CFG1_MINSFT
;
12613 snprintf(&tp
->fw_ver
[0], 32, "sb v%d.%02d", major
, minor
);
12616 static void __devinit
tg3_read_sb_ver(struct tg3
*tp
, u32 val
)
12618 u32 offset
, major
, minor
, build
;
12620 strncat(tp
->fw_ver
, "sb", TG3_VER_SIZE
- strlen(tp
->fw_ver
) - 1);
12622 if ((val
& TG3_EEPROM_SB_FORMAT_MASK
) != TG3_EEPROM_SB_FORMAT_1
)
12625 switch (val
& TG3_EEPROM_SB_REVISION_MASK
) {
12626 case TG3_EEPROM_SB_REVISION_0
:
12627 offset
= TG3_EEPROM_SB_F1R0_EDH_OFF
;
12629 case TG3_EEPROM_SB_REVISION_2
:
12630 offset
= TG3_EEPROM_SB_F1R2_EDH_OFF
;
12632 case TG3_EEPROM_SB_REVISION_3
:
12633 offset
= TG3_EEPROM_SB_F1R3_EDH_OFF
;
12635 case TG3_EEPROM_SB_REVISION_4
:
12636 offset
= TG3_EEPROM_SB_F1R4_EDH_OFF
;
12638 case TG3_EEPROM_SB_REVISION_5
:
12639 offset
= TG3_EEPROM_SB_F1R5_EDH_OFF
;
12645 if (tg3_nvram_read(tp
, offset
, &val
))
12648 build
= (val
& TG3_EEPROM_SB_EDH_BLD_MASK
) >>
12649 TG3_EEPROM_SB_EDH_BLD_SHFT
;
12650 major
= (val
& TG3_EEPROM_SB_EDH_MAJ_MASK
) >>
12651 TG3_EEPROM_SB_EDH_MAJ_SHFT
;
12652 minor
= val
& TG3_EEPROM_SB_EDH_MIN_MASK
;
12654 if (minor
> 99 || build
> 26)
12657 offset
= strlen(tp
->fw_ver
);
12658 snprintf(&tp
->fw_ver
[offset
], TG3_VER_SIZE
- offset
,
12659 " v%d.%02d", major
, minor
);
12662 offset
= strlen(tp
->fw_ver
);
12663 if (offset
< TG3_VER_SIZE
- 1)
12664 tp
->fw_ver
[offset
] = 'a' + build
- 1;
12668 static void __devinit
tg3_read_mgmtfw_ver(struct tg3
*tp
)
12670 u32 val
, offset
, start
;
12673 for (offset
= TG3_NVM_DIR_START
;
12674 offset
< TG3_NVM_DIR_END
;
12675 offset
+= TG3_NVM_DIRENT_SIZE
) {
12676 if (tg3_nvram_read(tp
, offset
, &val
))
12679 if ((val
>> TG3_NVM_DIRTYPE_SHIFT
) == TG3_NVM_DIRTYPE_ASFINI
)
12683 if (offset
== TG3_NVM_DIR_END
)
12686 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
12687 start
= 0x08000000;
12688 else if (tg3_nvram_read(tp
, offset
- 4, &start
))
12691 if (tg3_nvram_read(tp
, offset
+ 4, &offset
) ||
12692 !tg3_fw_img_is_valid(tp
, offset
) ||
12693 tg3_nvram_read(tp
, offset
+ 8, &val
))
12696 offset
+= val
- start
;
12698 vlen
= strlen(tp
->fw_ver
);
12700 tp
->fw_ver
[vlen
++] = ',';
12701 tp
->fw_ver
[vlen
++] = ' ';
12703 for (i
= 0; i
< 4; i
++) {
12705 if (tg3_nvram_read_be32(tp
, offset
, &v
))
12708 offset
+= sizeof(v
);
12710 if (vlen
> TG3_VER_SIZE
- sizeof(v
)) {
12711 memcpy(&tp
->fw_ver
[vlen
], &v
, TG3_VER_SIZE
- vlen
);
12715 memcpy(&tp
->fw_ver
[vlen
], &v
, sizeof(v
));
12720 static void __devinit
tg3_read_dash_ver(struct tg3
*tp
)
12725 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) ||
12726 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
12729 apedata
= tg3_ape_read32(tp
, TG3_APE_SEG_SIG
);
12730 if (apedata
!= APE_SEG_SIG_MAGIC
)
12733 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_STATUS
);
12734 if (!(apedata
& APE_FW_STATUS_READY
))
12737 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_VERSION
);
12739 vlen
= strlen(tp
->fw_ver
);
12741 snprintf(&tp
->fw_ver
[vlen
], TG3_VER_SIZE
- vlen
, " DASH v%d.%d.%d.%d",
12742 (apedata
& APE_FW_VERSION_MAJMSK
) >> APE_FW_VERSION_MAJSFT
,
12743 (apedata
& APE_FW_VERSION_MINMSK
) >> APE_FW_VERSION_MINSFT
,
12744 (apedata
& APE_FW_VERSION_REVMSK
) >> APE_FW_VERSION_REVSFT
,
12745 (apedata
& APE_FW_VERSION_BLDMSK
));
12748 static void __devinit
tg3_read_fw_ver(struct tg3
*tp
)
12751 bool vpd_vers
= false;
12753 if (tp
->fw_ver
[0] != 0)
12756 if (tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) {
12757 strcat(tp
->fw_ver
, "sb");
12761 if (tg3_nvram_read(tp
, 0, &val
))
12764 if (val
== TG3_EEPROM_MAGIC
)
12765 tg3_read_bc_ver(tp
);
12766 else if ((val
& TG3_EEPROM_MAGIC_FW_MSK
) == TG3_EEPROM_MAGIC_FW
)
12767 tg3_read_sb_ver(tp
, val
);
12768 else if ((val
& TG3_EEPROM_MAGIC_HW_MSK
) == TG3_EEPROM_MAGIC_HW
)
12769 tg3_read_hwsb_ver(tp
);
12773 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
12774 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) || vpd_vers
)
12777 tg3_read_mgmtfw_ver(tp
);
12780 tp
->fw_ver
[TG3_VER_SIZE
- 1] = 0;
12783 static struct pci_dev
* __devinit
tg3_find_peer(struct tg3
*);
12785 static int __devinit
tg3_get_invariants(struct tg3
*tp
)
12787 static struct pci_device_id write_reorder_chipsets
[] = {
12788 { PCI_DEVICE(PCI_VENDOR_ID_AMD
,
12789 PCI_DEVICE_ID_AMD_FE_GATE_700C
) },
12790 { PCI_DEVICE(PCI_VENDOR_ID_AMD
,
12791 PCI_DEVICE_ID_AMD_8131_BRIDGE
) },
12792 { PCI_DEVICE(PCI_VENDOR_ID_VIA
,
12793 PCI_DEVICE_ID_VIA_8385_0
) },
12797 u32 pci_state_reg
, grc_misc_cfg
;
12802 /* Force memory write invalidate off. If we leave it on,
12803 * then on 5700_BX chips we have to enable a workaround.
12804 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12805 * to match the cacheline size. The Broadcom driver have this
12806 * workaround but turns MWI off all the times so never uses
12807 * it. This seems to suggest that the workaround is insufficient.
12809 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
12810 pci_cmd
&= ~PCI_COMMAND_INVALIDATE
;
12811 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
12813 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12814 * has the register indirect write enable bit set before
12815 * we try to access any of the MMIO registers. It is also
12816 * critical that the PCI-X hw workaround situation is decided
12817 * before that as well.
12819 pci_read_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
12822 tp
->pci_chip_rev_id
= (misc_ctrl_reg
>>
12823 MISC_HOST_CTRL_CHIPREV_SHIFT
);
12824 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_USE_PROD_ID_REG
) {
12825 u32 prod_id_asic_rev
;
12827 if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5717
||
12828 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5718
||
12829 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5724
)
12830 pci_read_config_dword(tp
->pdev
,
12831 TG3PCI_GEN2_PRODID_ASICREV
,
12832 &prod_id_asic_rev
);
12833 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57781
||
12834 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57785
||
12835 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57761
||
12836 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57765
||
12837 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57791
||
12838 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57795
)
12839 pci_read_config_dword(tp
->pdev
,
12840 TG3PCI_GEN15_PRODID_ASICREV
,
12841 &prod_id_asic_rev
);
12843 pci_read_config_dword(tp
->pdev
, TG3PCI_PRODID_ASICREV
,
12844 &prod_id_asic_rev
);
12846 tp
->pci_chip_rev_id
= prod_id_asic_rev
;
12849 /* Wrong chip ID in 5752 A0. This code can be removed later
12850 * as A0 is not in production.
12852 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5752_A0_HW
)
12853 tp
->pci_chip_rev_id
= CHIPREV_ID_5752_A0
;
12855 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12856 * we need to disable memory and use config. cycles
12857 * only to access all registers. The 5702/03 chips
12858 * can mistakenly decode the special cycles from the
12859 * ICH chipsets as memory write cycles, causing corruption
12860 * of register and memory space. Only certain ICH bridges
12861 * will drive special cycles with non-zero data during the
12862 * address phase which can fall within the 5703's address
12863 * range. This is not an ICH bug as the PCI spec allows
12864 * non-zero address during special cycles. However, only
12865 * these ICH bridges are known to drive non-zero addresses
12866 * during special cycles.
12868 * Since special cycles do not cross PCI bridges, we only
12869 * enable this workaround if the 5703 is on the secondary
12870 * bus of these ICH bridges.
12872 if ((tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A1
) ||
12873 (tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A2
)) {
12874 static struct tg3_dev_id
{
12878 } ich_chipsets
[] = {
12879 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_8
,
12881 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AB_8
,
12883 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_11
,
12885 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_6
,
12889 struct tg3_dev_id
*pci_id
= &ich_chipsets
[0];
12890 struct pci_dev
*bridge
= NULL
;
12892 while (pci_id
->vendor
!= 0) {
12893 bridge
= pci_get_device(pci_id
->vendor
, pci_id
->device
,
12899 if (pci_id
->rev
!= PCI_ANY_ID
) {
12900 if (bridge
->revision
> pci_id
->rev
)
12903 if (bridge
->subordinate
&&
12904 (bridge
->subordinate
->number
==
12905 tp
->pdev
->bus
->number
)) {
12907 tp
->tg3_flags2
|= TG3_FLG2_ICH_WORKAROUND
;
12908 pci_dev_put(bridge
);
12914 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
12915 static struct tg3_dev_id
{
12918 } bridge_chipsets
[] = {
12919 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
},
12920 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
},
12923 struct tg3_dev_id
*pci_id
= &bridge_chipsets
[0];
12924 struct pci_dev
*bridge
= NULL
;
12926 while (pci_id
->vendor
!= 0) {
12927 bridge
= pci_get_device(pci_id
->vendor
,
12934 if (bridge
->subordinate
&&
12935 (bridge
->subordinate
->number
<=
12936 tp
->pdev
->bus
->number
) &&
12937 (bridge
->subordinate
->subordinate
>=
12938 tp
->pdev
->bus
->number
)) {
12939 tp
->tg3_flags3
|= TG3_FLG3_5701_DMA_BUG
;
12940 pci_dev_put(bridge
);
12946 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12947 * DMA addresses > 40-bit. This bridge may have other additional
12948 * 57xx devices behind it in some 4-port NIC designs for example.
12949 * Any tg3 device found behind the bridge will also need the 40-bit
12952 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
||
12953 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
12954 tp
->tg3_flags2
|= TG3_FLG2_5780_CLASS
;
12955 tp
->tg3_flags
|= TG3_FLAG_40BIT_DMA_BUG
;
12956 tp
->msi_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_MSI
);
12958 struct pci_dev
*bridge
= NULL
;
12961 bridge
= pci_get_device(PCI_VENDOR_ID_SERVERWORKS
,
12962 PCI_DEVICE_ID_SERVERWORKS_EPB
,
12964 if (bridge
&& bridge
->subordinate
&&
12965 (bridge
->subordinate
->number
<=
12966 tp
->pdev
->bus
->number
) &&
12967 (bridge
->subordinate
->subordinate
>=
12968 tp
->pdev
->bus
->number
)) {
12969 tp
->tg3_flags
|= TG3_FLAG_40BIT_DMA_BUG
;
12970 pci_dev_put(bridge
);
12976 /* Initialize misc host control in PCI block. */
12977 tp
->misc_host_ctrl
|= (misc_ctrl_reg
&
12978 MISC_HOST_CTRL_CHIPREV
);
12979 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
12980 tp
->misc_host_ctrl
);
12982 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
12983 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
||
12984 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
)
12985 tp
->pdev_peer
= tg3_find_peer(tp
);
12987 /* Intentionally exclude ASIC_REV_5906 */
12988 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
12989 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
12990 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
12991 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
12992 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
12993 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
12994 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
12995 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
12996 tp
->tg3_flags3
|= TG3_FLG3_5755_PLUS
;
12998 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
||
12999 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
13000 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
||
13001 (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
13002 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
13003 tp
->tg3_flags2
|= TG3_FLG2_5750_PLUS
;
13005 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) ||
13006 (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
13007 tp
->tg3_flags2
|= TG3_FLG2_5705_PLUS
;
13009 /* 5700 B0 chips do not support checksumming correctly due
13010 * to hardware bugs.
13012 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5700_B0
)
13013 tp
->tg3_flags
|= TG3_FLAG_BROKEN_CHECKSUMS
;
13015 tp
->tg3_flags
|= TG3_FLAG_RX_CHECKSUMS
;
13016 tp
->dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
;
13017 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
13018 tp
->dev
->features
|= NETIF_F_IPV6_CSUM
;
13019 tp
->dev
->features
|= NETIF_F_GRO
;
13022 /* Determine TSO capabilities */
13023 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
13024 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
13025 tp
->tg3_flags2
|= TG3_FLG2_HW_TSO_3
;
13026 else if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
13027 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13028 tp
->tg3_flags2
|= TG3_FLG2_HW_TSO_2
;
13029 else if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
13030 tp
->tg3_flags2
|= TG3_FLG2_HW_TSO_1
| TG3_FLG2_TSO_BUG
;
13031 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
&&
13032 tp
->pci_chip_rev_id
>= CHIPREV_ID_5750_C2
)
13033 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_BUG
;
13034 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
13035 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
&&
13036 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) {
13037 tp
->tg3_flags2
|= TG3_FLG2_TSO_BUG
;
13038 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
)
13039 tp
->fw_needed
= FIRMWARE_TG3TSO5
;
13041 tp
->fw_needed
= FIRMWARE_TG3TSO
;
13046 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
13047 tp
->tg3_flags
|= TG3_FLAG_SUPPORT_MSI
;
13048 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_AX
||
13049 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_BX
||
13050 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
&&
13051 tp
->pci_chip_rev_id
<= CHIPREV_ID_5714_A2
&&
13052 tp
->pdev_peer
== tp
->pdev
))
13053 tp
->tg3_flags
&= ~TG3_FLAG_SUPPORT_MSI
;
13055 if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
13056 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
13057 tp
->tg3_flags2
|= TG3_FLG2_1SHOT_MSI
;
13060 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
13061 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
) {
13062 tp
->tg3_flags
|= TG3_FLAG_SUPPORT_MSIX
;
13063 tp
->irq_max
= TG3_IRQ_MAX_VECS
;
13067 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
13068 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13069 tp
->tg3_flags3
|= TG3_FLG3_SHORT_DMA_BUG
;
13070 else if (!(tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)) {
13071 tp
->tg3_flags3
|= TG3_FLG3_4G_DMA_BNDRY_BUG
;
13072 tp
->tg3_flags3
|= TG3_FLG3_40BIT_DMA_LIMIT_BUG
;
13075 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
13076 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
13077 tp
->tg3_flags3
|= TG3_FLG3_USE_JUMBO_BDFLAG
;
13079 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
13080 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
13081 (tp
->tg3_flags3
& TG3_FLG3_USE_JUMBO_BDFLAG
))
13082 tp
->tg3_flags
|= TG3_FLAG_JUMBO_CAPABLE
;
13084 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
13087 tp
->pcie_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_EXP
);
13088 if (tp
->pcie_cap
!= 0) {
13091 tp
->tg3_flags2
|= TG3_FLG2_PCI_EXPRESS
;
13093 pcie_set_readrq(tp
->pdev
, 4096);
13095 pci_read_config_word(tp
->pdev
,
13096 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
13098 if (lnkctl
& PCI_EXP_LNKCTL_CLKREQ_EN
) {
13099 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13100 tp
->tg3_flags2
&= ~TG3_FLG2_HW_TSO_2
;
13101 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
13102 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
13103 tp
->pci_chip_rev_id
== CHIPREV_ID_57780_A0
||
13104 tp
->pci_chip_rev_id
== CHIPREV_ID_57780_A1
)
13105 tp
->tg3_flags3
|= TG3_FLG3_CLKREQ_BUG
;
13106 } else if (tp
->pci_chip_rev_id
== CHIPREV_ID_5717_A0
) {
13107 tp
->tg3_flags3
|= TG3_FLG3_L1PLLPD_EN
;
13109 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
) {
13110 tp
->tg3_flags2
|= TG3_FLG2_PCI_EXPRESS
;
13111 } else if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
13112 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
13113 tp
->pcix_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_PCIX
);
13114 if (!tp
->pcix_cap
) {
13115 dev_err(&tp
->pdev
->dev
,
13116 "Cannot find PCI-X capability, aborting\n");
13120 if (!(pci_state_reg
& PCISTATE_CONV_PCI_MODE
))
13121 tp
->tg3_flags
|= TG3_FLAG_PCIX_MODE
;
13124 /* If we have an AMD 762 or VIA K8T800 chipset, write
13125 * reordering to the mailbox registers done by the host
13126 * controller can cause major troubles. We read back from
13127 * every mailbox register write to force the writes to be
13128 * posted to the chip in order.
13130 if (pci_dev_present(write_reorder_chipsets
) &&
13131 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
13132 tp
->tg3_flags
|= TG3_FLAG_MBOX_WRITE_REORDER
;
13134 pci_read_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
,
13135 &tp
->pci_cacheline_sz
);
13136 pci_read_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
13137 &tp
->pci_lat_timer
);
13138 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
&&
13139 tp
->pci_lat_timer
< 64) {
13140 tp
->pci_lat_timer
= 64;
13141 pci_write_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
13142 tp
->pci_lat_timer
);
13145 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5700_BX
) {
13146 /* 5700 BX chips need to have their TX producer index
13147 * mailboxes written twice to workaround a bug.
13149 tp
->tg3_flags
|= TG3_FLAG_TXD_MBOX_HWBUG
;
13151 /* If we are in PCI-X mode, enable register write workaround.
13153 * The workaround is to use indirect register accesses
13154 * for all chip writes not to mailbox registers.
13156 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
13159 tp
->tg3_flags
|= TG3_FLAG_PCIX_TARGET_HWBUG
;
13161 /* The chip can have it's power management PCI config
13162 * space registers clobbered due to this bug.
13163 * So explicitly force the chip into D0 here.
13165 pci_read_config_dword(tp
->pdev
,
13166 tp
->pm_cap
+ PCI_PM_CTRL
,
13168 pm_reg
&= ~PCI_PM_CTRL_STATE_MASK
;
13169 pm_reg
|= PCI_PM_CTRL_PME_ENABLE
| 0 /* D0 */;
13170 pci_write_config_dword(tp
->pdev
,
13171 tp
->pm_cap
+ PCI_PM_CTRL
,
13174 /* Also, force SERR#/PERR# in PCI command. */
13175 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
13176 pci_cmd
|= PCI_COMMAND_PARITY
| PCI_COMMAND_SERR
;
13177 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
13181 if ((pci_state_reg
& PCISTATE_BUS_SPEED_HIGH
) != 0)
13182 tp
->tg3_flags
|= TG3_FLAG_PCI_HIGH_SPEED
;
13183 if ((pci_state_reg
& PCISTATE_BUS_32BIT
) != 0)
13184 tp
->tg3_flags
|= TG3_FLAG_PCI_32BIT
;
13186 /* Chip-specific fixup from Broadcom driver */
13187 if ((tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
) &&
13188 (!(pci_state_reg
& PCISTATE_RETRY_SAME_DMA
))) {
13189 pci_state_reg
|= PCISTATE_RETRY_SAME_DMA
;
13190 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, pci_state_reg
);
13193 /* Default fast path register access methods */
13194 tp
->read32
= tg3_read32
;
13195 tp
->write32
= tg3_write32
;
13196 tp
->read32_mbox
= tg3_read32
;
13197 tp
->write32_mbox
= tg3_write32
;
13198 tp
->write32_tx_mbox
= tg3_write32
;
13199 tp
->write32_rx_mbox
= tg3_write32
;
13201 /* Various workaround register access methods */
13202 if (tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
)
13203 tp
->write32
= tg3_write_indirect_reg32
;
13204 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
||
13205 ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) &&
13206 tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A0
)) {
13208 * Back to back register writes can cause problems on these
13209 * chips, the workaround is to read back all reg writes
13210 * except those to mailbox regs.
13212 * See tg3_write_indirect_reg32().
13214 tp
->write32
= tg3_write_flush_reg32
;
13217 if ((tp
->tg3_flags
& TG3_FLAG_TXD_MBOX_HWBUG
) ||
13218 (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)) {
13219 tp
->write32_tx_mbox
= tg3_write32_tx_mbox
;
13220 if (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)
13221 tp
->write32_rx_mbox
= tg3_write_flush_reg32
;
13224 if (tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
) {
13225 tp
->read32
= tg3_read_indirect_reg32
;
13226 tp
->write32
= tg3_write_indirect_reg32
;
13227 tp
->read32_mbox
= tg3_read_indirect_mbox
;
13228 tp
->write32_mbox
= tg3_write_indirect_mbox
;
13229 tp
->write32_tx_mbox
= tg3_write_indirect_mbox
;
13230 tp
->write32_rx_mbox
= tg3_write_indirect_mbox
;
13235 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
13236 pci_cmd
&= ~PCI_COMMAND_MEMORY
;
13237 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
13239 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
13240 tp
->read32_mbox
= tg3_read32_mbox_5906
;
13241 tp
->write32_mbox
= tg3_write32_mbox_5906
;
13242 tp
->write32_tx_mbox
= tg3_write32_mbox_5906
;
13243 tp
->write32_rx_mbox
= tg3_write32_mbox_5906
;
13246 if (tp
->write32
== tg3_write_indirect_reg32
||
13247 ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) &&
13248 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
13249 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)))
13250 tp
->tg3_flags
|= TG3_FLAG_SRAM_USE_CONFIG
;
13252 /* Get eeprom hw config before calling tg3_set_power_state().
13253 * In particular, the TG3_FLG2_IS_NIC flag must be
13254 * determined before calling tg3_set_power_state() so that
13255 * we know whether or not to switch out of Vaux power.
13256 * When the flag is set, it means that GPIO1 is used for eeprom
13257 * write protect and also implies that it is a LOM where GPIOs
13258 * are not used to switch power.
13260 tg3_get_eeprom_hw_cfg(tp
);
13262 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
13263 /* Allow reads and writes to the
13264 * APE register and memory space.
13266 pci_state_reg
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
13267 PCISTATE_ALLOW_APE_SHMEM_WR
|
13268 PCISTATE_ALLOW_APE_PSPACE_WR
;
13269 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
13273 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
13274 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
13275 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
13276 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
13277 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
13278 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
13279 tp
->tg3_flags
|= TG3_FLAG_CPMU_PRESENT
;
13281 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13282 * GPIO1 driven high will bring 5700's external PHY out of reset.
13283 * It is also used as eeprom write protect on LOMs.
13285 tp
->grc_local_ctrl
= GRC_LCLCTRL_INT_ON_ATTN
| GRC_LCLCTRL_AUTO_SEEPROM
;
13286 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) ||
13287 (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
))
13288 tp
->grc_local_ctrl
|= (GRC_LCLCTRL_GPIO_OE1
|
13289 GRC_LCLCTRL_GPIO_OUTPUT1
);
13290 /* Unused GPIO3 must be driven as output on 5752 because there
13291 * are no pull-up resistors on unused GPIO pins.
13293 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
13294 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE3
;
13296 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
13297 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
||
13298 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
13299 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_UART_SEL
;
13301 if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5761
||
13302 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5761S
) {
13303 /* Turn off the debug UART. */
13304 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_UART_SEL
;
13305 if (tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)
13306 /* Keep VMain power. */
13307 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE0
|
13308 GRC_LCLCTRL_GPIO_OUTPUT0
;
13311 /* Force the chip into D0. */
13312 err
= tg3_set_power_state(tp
, PCI_D0
);
13314 dev_err(&tp
->pdev
->dev
, "Transition to D0 failed\n");
13318 /* Derive initial jumbo mode from MTU assigned in
13319 * ether_setup() via the alloc_etherdev() call
13321 if (tp
->dev
->mtu
> ETH_DATA_LEN
&&
13322 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
13323 tp
->tg3_flags
|= TG3_FLAG_JUMBO_RING_ENABLE
;
13325 /* Determine WakeOnLan speed to use. */
13326 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
13327 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
13328 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
||
13329 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B2
) {
13330 tp
->tg3_flags
&= ~(TG3_FLAG_WOL_SPEED_100MB
);
13332 tp
->tg3_flags
|= TG3_FLAG_WOL_SPEED_100MB
;
13335 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13336 tp
->tg3_flags3
|= TG3_FLG3_PHY_IS_FET
;
13338 /* A few boards don't want Ethernet@WireSpeed phy feature */
13339 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) ||
13340 ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) &&
13341 (tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) &&
13342 (tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A1
)) ||
13343 (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) ||
13344 (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
))
13345 tp
->tg3_flags2
|= TG3_FLG2_NO_ETH_WIRE_SPEED
;
13347 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5703_AX
||
13348 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5704_AX
)
13349 tp
->tg3_flags2
|= TG3_FLG2_PHY_ADC_BUG
;
13350 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
)
13351 tp
->tg3_flags2
|= TG3_FLG2_PHY_5704_A0_BUG
;
13353 if ((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
13354 !(tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) &&
13355 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
&&
13356 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_57780
&&
13357 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5717
&&
13358 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_57765
) {
13359 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
13360 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
13361 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
13362 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
) {
13363 if (tp
->pdev
->device
!= PCI_DEVICE_ID_TIGON3_5756
&&
13364 tp
->pdev
->device
!= PCI_DEVICE_ID_TIGON3_5722
)
13365 tp
->tg3_flags2
|= TG3_FLG2_PHY_JITTER_BUG
;
13366 if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5755M
)
13367 tp
->tg3_flags2
|= TG3_FLG2_PHY_ADJUST_TRIM
;
13369 tp
->tg3_flags2
|= TG3_FLG2_PHY_BER_BUG
;
13372 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
13373 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) {
13374 tp
->phy_otp
= tg3_read_otp_phycfg(tp
);
13375 if (tp
->phy_otp
== 0)
13376 tp
->phy_otp
= TG3_OTP_DEFAULT
;
13379 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
)
13380 tp
->mi_mode
= MAC_MI_MODE_500KHZ_CONST
;
13382 tp
->mi_mode
= MAC_MI_MODE_BASE
;
13384 tp
->coalesce_mode
= 0;
13385 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5700_AX
&&
13386 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5700_BX
)
13387 tp
->coalesce_mode
|= HOSTCC_MODE_32BYTE
;
13389 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
13390 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
13391 tp
->tg3_flags3
|= TG3_FLG3_USE_PHYLIB
;
13393 err
= tg3_mdio_init(tp
);
13397 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
&&
13398 (tp
->pci_chip_rev_id
!= CHIPREV_ID_5717_A0
||
13399 (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)))
13402 /* Initialize data/descriptor byte/word swapping. */
13403 val
= tr32(GRC_MODE
);
13404 val
&= GRC_MODE_HOST_STACKUP
;
13405 tw32(GRC_MODE
, val
| tp
->grc_mode
);
13407 tg3_switch_clocks(tp
);
13409 /* Clear this out for sanity. */
13410 tw32(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
13412 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
13414 if ((pci_state_reg
& PCISTATE_CONV_PCI_MODE
) == 0 &&
13415 (tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
) == 0) {
13416 u32 chiprevid
= GET_CHIP_REV_ID(tp
->misc_host_ctrl
);
13418 if (chiprevid
== CHIPREV_ID_5701_A0
||
13419 chiprevid
== CHIPREV_ID_5701_B0
||
13420 chiprevid
== CHIPREV_ID_5701_B2
||
13421 chiprevid
== CHIPREV_ID_5701_B5
) {
13422 void __iomem
*sram_base
;
13424 /* Write some dummy words into the SRAM status block
13425 * area, see if it reads back correctly. If the return
13426 * value is bad, force enable the PCIX workaround.
13428 sram_base
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_STATS_BLK
;
13430 writel(0x00000000, sram_base
);
13431 writel(0x00000000, sram_base
+ 4);
13432 writel(0xffffffff, sram_base
+ 4);
13433 if (readl(sram_base
) != 0x00000000)
13434 tp
->tg3_flags
|= TG3_FLAG_PCIX_TARGET_HWBUG
;
13439 tg3_nvram_init(tp
);
13441 grc_misc_cfg
= tr32(GRC_MISC_CFG
);
13442 grc_misc_cfg
&= GRC_MISC_CFG_BOARD_ID_MASK
;
13444 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
13445 (grc_misc_cfg
== GRC_MISC_CFG_BOARD_ID_5788
||
13446 grc_misc_cfg
== GRC_MISC_CFG_BOARD_ID_5788M
))
13447 tp
->tg3_flags2
|= TG3_FLG2_IS_5788
;
13449 if (!(tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
13450 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
))
13451 tp
->tg3_flags
|= TG3_FLAG_TAGGED_STATUS
;
13452 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) {
13453 tp
->coalesce_mode
|= (HOSTCC_MODE_CLRTICK_RXBD
|
13454 HOSTCC_MODE_CLRTICK_TXBD
);
13456 tp
->misc_host_ctrl
|= MISC_HOST_CTRL_TAGGED_STATUS
;
13457 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
13458 tp
->misc_host_ctrl
);
13461 /* Preserve the APE MAC_MODE bits */
13462 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
13463 tp
->mac_mode
= tr32(MAC_MODE
) |
13464 MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
;
13466 tp
->mac_mode
= TG3_DEF_MAC_MODE
;
13468 /* these are limited to 10/100 only */
13469 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
&&
13470 (grc_misc_cfg
== 0x8000 || grc_misc_cfg
== 0x4000)) ||
13471 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
13472 tp
->pdev
->vendor
== PCI_VENDOR_ID_BROADCOM
&&
13473 (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5901
||
13474 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5901_2
||
13475 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5705F
)) ||
13476 (tp
->pdev
->vendor
== PCI_VENDOR_ID_BROADCOM
&&
13477 (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5751F
||
13478 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5753F
||
13479 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5787F
)) ||
13480 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57790
||
13481 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57791
||
13482 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57795
||
13483 (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
))
13484 tp
->tg3_flags
|= TG3_FLAG_10_100_ONLY
;
13486 err
= tg3_phy_probe(tp
);
13488 dev_err(&tp
->pdev
->dev
, "phy probe failed, err %d\n", err
);
13489 /* ... but do not return immediately ... */
13494 tg3_read_fw_ver(tp
);
13496 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
13497 tp
->tg3_flags
&= ~TG3_FLAG_USE_MI_INTERRUPT
;
13499 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
)
13500 tp
->tg3_flags
|= TG3_FLAG_USE_MI_INTERRUPT
;
13502 tp
->tg3_flags
&= ~TG3_FLAG_USE_MI_INTERRUPT
;
13505 /* 5700 {AX,BX} chips have a broken status block link
13506 * change bit implementation, so we must use the
13507 * status register in those cases.
13509 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
)
13510 tp
->tg3_flags
|= TG3_FLAG_USE_LINKCHG_REG
;
13512 tp
->tg3_flags
&= ~TG3_FLAG_USE_LINKCHG_REG
;
13514 /* The led_ctrl is set during tg3_phy_probe, here we might
13515 * have to force the link status polling mechanism based
13516 * upon subsystem IDs.
13518 if (tp
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
&&
13519 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
&&
13520 !(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)) {
13521 tp
->tg3_flags
|= (TG3_FLAG_USE_MI_INTERRUPT
|
13522 TG3_FLAG_USE_LINKCHG_REG
);
13525 /* For all SERDES we poll the MAC status register. */
13526 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
13527 tp
->tg3_flags
|= TG3_FLAG_POLL_SERDES
;
13529 tp
->tg3_flags
&= ~TG3_FLAG_POLL_SERDES
;
13531 tp
->rx_offset
= NET_IP_ALIGN
+ TG3_RX_HEADROOM
;
13532 tp
->rx_copy_thresh
= TG3_RX_COPY_THRESHOLD
;
13533 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
&&
13534 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) != 0) {
13535 tp
->rx_offset
-= NET_IP_ALIGN
;
13536 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13537 tp
->rx_copy_thresh
= ~(u16
)0;
13541 tp
->rx_std_max_post
= TG3_RX_RING_SIZE
;
13543 /* Increment the rx prod index on the rx std ring by at most
13544 * 8 for these chips to workaround hw errata.
13546 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
||
13547 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
13548 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
13549 tp
->rx_std_max_post
= 8;
13551 if (tp
->tg3_flags
& TG3_FLAG_ASPM_WORKAROUND
)
13552 tp
->pwrmgmt_thresh
= tr32(PCIE_PWR_MGMT_THRESH
) &
13553 PCIE_PWR_MGMT_L1_THRESH_MSK
;
13558 #ifdef CONFIG_SPARC
13559 static int __devinit
tg3_get_macaddr_sparc(struct tg3
*tp
)
13561 struct net_device
*dev
= tp
->dev
;
13562 struct pci_dev
*pdev
= tp
->pdev
;
13563 struct device_node
*dp
= pci_device_to_OF_node(pdev
);
13564 const unsigned char *addr
;
13567 addr
= of_get_property(dp
, "local-mac-address", &len
);
13568 if (addr
&& len
== 6) {
13569 memcpy(dev
->dev_addr
, addr
, 6);
13570 memcpy(dev
->perm_addr
, dev
->dev_addr
, 6);
13576 static int __devinit
tg3_get_default_macaddr_sparc(struct tg3
*tp
)
13578 struct net_device
*dev
= tp
->dev
;
13580 memcpy(dev
->dev_addr
, idprom
->id_ethaddr
, 6);
13581 memcpy(dev
->perm_addr
, idprom
->id_ethaddr
, 6);
13586 static int __devinit
tg3_get_device_address(struct tg3
*tp
)
13588 struct net_device
*dev
= tp
->dev
;
13589 u32 hi
, lo
, mac_offset
;
13592 #ifdef CONFIG_SPARC
13593 if (!tg3_get_macaddr_sparc(tp
))
13598 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) ||
13599 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
13600 if (tr32(TG3PCI_DUAL_MAC_CTRL
) & DUAL_MAC_CTRL_ID
)
13602 if (tg3_nvram_lock(tp
))
13603 tw32_f(NVRAM_CMD
, NVRAM_CMD_RESET
);
13605 tg3_nvram_unlock(tp
);
13606 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
) {
13607 if (tr32(TG3_CPMU_STATUS
) & TG3_CPMU_STATUS_PCIE_FUNC
)
13609 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13612 /* First try to get it from MAC address mailbox. */
13613 tg3_read_mem(tp
, NIC_SRAM_MAC_ADDR_HIGH_MBOX
, &hi
);
13614 if ((hi
>> 16) == 0x484b) {
13615 dev
->dev_addr
[0] = (hi
>> 8) & 0xff;
13616 dev
->dev_addr
[1] = (hi
>> 0) & 0xff;
13618 tg3_read_mem(tp
, NIC_SRAM_MAC_ADDR_LOW_MBOX
, &lo
);
13619 dev
->dev_addr
[2] = (lo
>> 24) & 0xff;
13620 dev
->dev_addr
[3] = (lo
>> 16) & 0xff;
13621 dev
->dev_addr
[4] = (lo
>> 8) & 0xff;
13622 dev
->dev_addr
[5] = (lo
>> 0) & 0xff;
13624 /* Some old bootcode may report a 0 MAC address in SRAM */
13625 addr_ok
= is_valid_ether_addr(&dev
->dev_addr
[0]);
13628 /* Next, try NVRAM. */
13629 if (!(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) &&
13630 !tg3_nvram_read_be32(tp
, mac_offset
+ 0, &hi
) &&
13631 !tg3_nvram_read_be32(tp
, mac_offset
+ 4, &lo
)) {
13632 memcpy(&dev
->dev_addr
[0], ((char *)&hi
) + 2, 2);
13633 memcpy(&dev
->dev_addr
[2], (char *)&lo
, sizeof(lo
));
13635 /* Finally just fetch it out of the MAC control regs. */
13637 hi
= tr32(MAC_ADDR_0_HIGH
);
13638 lo
= tr32(MAC_ADDR_0_LOW
);
13640 dev
->dev_addr
[5] = lo
& 0xff;
13641 dev
->dev_addr
[4] = (lo
>> 8) & 0xff;
13642 dev
->dev_addr
[3] = (lo
>> 16) & 0xff;
13643 dev
->dev_addr
[2] = (lo
>> 24) & 0xff;
13644 dev
->dev_addr
[1] = hi
& 0xff;
13645 dev
->dev_addr
[0] = (hi
>> 8) & 0xff;
13649 if (!is_valid_ether_addr(&dev
->dev_addr
[0])) {
13650 #ifdef CONFIG_SPARC
13651 if (!tg3_get_default_macaddr_sparc(tp
))
13656 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
13660 #define BOUNDARY_SINGLE_CACHELINE 1
13661 #define BOUNDARY_MULTI_CACHELINE 2
13663 static u32 __devinit
tg3_calc_dma_bndry(struct tg3
*tp
, u32 val
)
13665 int cacheline_size
;
13669 pci_read_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
, &byte
);
13671 cacheline_size
= 1024;
13673 cacheline_size
= (int) byte
* 4;
13675 /* On 5703 and later chips, the boundary bits have no
13678 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
13679 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
&&
13680 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
13683 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13684 goal
= BOUNDARY_MULTI_CACHELINE
;
13686 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13687 goal
= BOUNDARY_SINGLE_CACHELINE
;
13693 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
13694 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
) {
13695 val
= goal
? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT
;
13702 /* PCI controllers on most RISC systems tend to disconnect
13703 * when a device tries to burst across a cache-line boundary.
13704 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13706 * Unfortunately, for PCI-E there are only limited
13707 * write-side controls for this, and thus for reads
13708 * we will still get the disconnects. We'll also waste
13709 * these PCI cycles for both read and write for chips
13710 * other than 5700 and 5701 which do not implement the
13713 if ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) &&
13714 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)) {
13715 switch (cacheline_size
) {
13720 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13721 val
|= (DMA_RWCTRL_READ_BNDRY_128_PCIX
|
13722 DMA_RWCTRL_WRITE_BNDRY_128_PCIX
);
13724 val
|= (DMA_RWCTRL_READ_BNDRY_384_PCIX
|
13725 DMA_RWCTRL_WRITE_BNDRY_384_PCIX
);
13730 val
|= (DMA_RWCTRL_READ_BNDRY_256_PCIX
|
13731 DMA_RWCTRL_WRITE_BNDRY_256_PCIX
);
13735 val
|= (DMA_RWCTRL_READ_BNDRY_384_PCIX
|
13736 DMA_RWCTRL_WRITE_BNDRY_384_PCIX
);
13739 } else if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
13740 switch (cacheline_size
) {
13744 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13745 val
&= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE
;
13746 val
|= DMA_RWCTRL_WRITE_BNDRY_64_PCIE
;
13752 val
&= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE
;
13753 val
|= DMA_RWCTRL_WRITE_BNDRY_128_PCIE
;
13757 switch (cacheline_size
) {
13759 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13760 val
|= (DMA_RWCTRL_READ_BNDRY_16
|
13761 DMA_RWCTRL_WRITE_BNDRY_16
);
13766 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13767 val
|= (DMA_RWCTRL_READ_BNDRY_32
|
13768 DMA_RWCTRL_WRITE_BNDRY_32
);
13773 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13774 val
|= (DMA_RWCTRL_READ_BNDRY_64
|
13775 DMA_RWCTRL_WRITE_BNDRY_64
);
13780 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13781 val
|= (DMA_RWCTRL_READ_BNDRY_128
|
13782 DMA_RWCTRL_WRITE_BNDRY_128
);
13787 val
|= (DMA_RWCTRL_READ_BNDRY_256
|
13788 DMA_RWCTRL_WRITE_BNDRY_256
);
13791 val
|= (DMA_RWCTRL_READ_BNDRY_512
|
13792 DMA_RWCTRL_WRITE_BNDRY_512
);
13796 val
|= (DMA_RWCTRL_READ_BNDRY_1024
|
13797 DMA_RWCTRL_WRITE_BNDRY_1024
);
13806 static int __devinit
tg3_do_test_dma(struct tg3
*tp
, u32
*buf
, dma_addr_t buf_dma
, int size
, int to_device
)
13808 struct tg3_internal_buffer_desc test_desc
;
13809 u32 sram_dma_descs
;
13812 sram_dma_descs
= NIC_SRAM_DMA_DESC_POOL_BASE
;
13814 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ
, 0);
13815 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ
, 0);
13816 tw32(RDMAC_STATUS
, 0);
13817 tw32(WDMAC_STATUS
, 0);
13819 tw32(BUFMGR_MODE
, 0);
13820 tw32(FTQ_RESET
, 0);
13822 test_desc
.addr_hi
= ((u64
) buf_dma
) >> 32;
13823 test_desc
.addr_lo
= buf_dma
& 0xffffffff;
13824 test_desc
.nic_mbuf
= 0x00002100;
13825 test_desc
.len
= size
;
13828 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13829 * the *second* time the tg3 driver was getting loaded after an
13832 * Broadcom tells me:
13833 * ...the DMA engine is connected to the GRC block and a DMA
13834 * reset may affect the GRC block in some unpredictable way...
13835 * The behavior of resets to individual blocks has not been tested.
13837 * Broadcom noted the GRC reset will also reset all sub-components.
13840 test_desc
.cqid_sqid
= (13 << 8) | 2;
13842 tw32_f(RDMAC_MODE
, RDMAC_MODE_ENABLE
);
13845 test_desc
.cqid_sqid
= (16 << 8) | 7;
13847 tw32_f(WDMAC_MODE
, WDMAC_MODE_ENABLE
);
13850 test_desc
.flags
= 0x00000005;
13852 for (i
= 0; i
< (sizeof(test_desc
) / sizeof(u32
)); i
++) {
13855 val
= *(((u32
*)&test_desc
) + i
);
13856 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
,
13857 sram_dma_descs
+ (i
* sizeof(u32
)));
13858 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
13860 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
13863 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ
, sram_dma_descs
);
13865 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ
, sram_dma_descs
);
13868 for (i
= 0; i
< 40; i
++) {
13872 val
= tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ
);
13874 val
= tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ
);
13875 if ((val
& 0xffff) == sram_dma_descs
) {
13886 #define TEST_BUFFER_SIZE 0x2000
13888 static int __devinit
tg3_test_dma(struct tg3
*tp
)
13890 dma_addr_t buf_dma
;
13891 u32
*buf
, saved_dma_rwctrl
;
13894 buf
= pci_alloc_consistent(tp
->pdev
, TEST_BUFFER_SIZE
, &buf_dma
);
13900 tp
->dma_rwctrl
= ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT
) |
13901 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT
));
13903 tp
->dma_rwctrl
= tg3_calc_dma_bndry(tp
, tp
->dma_rwctrl
);
13905 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
13906 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
)
13909 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
13910 /* DMA read watermark not used on PCIE */
13911 tp
->dma_rwctrl
|= 0x00180000;
13912 } else if (!(tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
)) {
13913 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
||
13914 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
)
13915 tp
->dma_rwctrl
|= 0x003f0000;
13917 tp
->dma_rwctrl
|= 0x003f000f;
13919 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
13920 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
13921 u32 ccval
= (tr32(TG3PCI_CLOCK_CTRL
) & 0x1f);
13922 u32 read_water
= 0x7;
13924 /* If the 5704 is behind the EPB bridge, we can
13925 * do the less restrictive ONE_DMA workaround for
13926 * better performance.
13928 if ((tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
) &&
13929 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
13930 tp
->dma_rwctrl
|= 0x8000;
13931 else if (ccval
== 0x6 || ccval
== 0x7)
13932 tp
->dma_rwctrl
|= DMA_RWCTRL_ONE_DMA
;
13934 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
)
13936 /* Set bit 23 to enable PCIX hw bug fix */
13938 (read_water
<< DMA_RWCTRL_READ_WATER_SHIFT
) |
13939 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT
) |
13941 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
) {
13942 /* 5780 always in PCIX mode */
13943 tp
->dma_rwctrl
|= 0x00144000;
13944 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
13945 /* 5714 always in PCIX mode */
13946 tp
->dma_rwctrl
|= 0x00148000;
13948 tp
->dma_rwctrl
|= 0x001b000f;
13952 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
13953 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
13954 tp
->dma_rwctrl
&= 0xfffffff0;
13956 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
13957 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
13958 /* Remove this if it causes problems for some boards. */
13959 tp
->dma_rwctrl
|= DMA_RWCTRL_USE_MEM_READ_MULT
;
13961 /* On 5700/5701 chips, we need to set this bit.
13962 * Otherwise the chip will issue cacheline transactions
13963 * to streamable DMA memory with not all the byte
13964 * enables turned on. This is an error on several
13965 * RISC PCI controllers, in particular sparc64.
13967 * On 5703/5704 chips, this bit has been reassigned
13968 * a different meaning. In particular, it is used
13969 * on those chips to enable a PCI-X workaround.
13971 tp
->dma_rwctrl
|= DMA_RWCTRL_ASSERT_ALL_BE
;
13974 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
13977 /* Unneeded, already done by tg3_get_invariants. */
13978 tg3_switch_clocks(tp
);
13981 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
13982 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
)
13985 /* It is best to perform DMA test with maximum write burst size
13986 * to expose the 5700/5701 write DMA bug.
13988 saved_dma_rwctrl
= tp
->dma_rwctrl
;
13989 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
13990 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
13995 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++)
13998 /* Send the buffer to the chip. */
13999 ret
= tg3_do_test_dma(tp
, buf
, buf_dma
, TEST_BUFFER_SIZE
, 1);
14001 dev_err(&tp
->pdev
->dev
,
14002 "%s: Buffer write failed. err = %d\n",
14008 /* validate data reached card RAM correctly. */
14009 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++) {
14011 tg3_read_mem(tp
, 0x2100 + (i
*4), &val
);
14012 if (le32_to_cpu(val
) != p
[i
]) {
14013 dev_err(&tp
->pdev
->dev
,
14014 "%s: Buffer corrupted on device! "
14015 "(%d != %d)\n", __func__
, val
, i
);
14016 /* ret = -ENODEV here? */
14021 /* Now read it back. */
14022 ret
= tg3_do_test_dma(tp
, buf
, buf_dma
, TEST_BUFFER_SIZE
, 0);
14024 dev_err(&tp
->pdev
->dev
, "%s: Buffer read failed. "
14025 "err = %d\n", __func__
, ret
);
14030 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++) {
14034 if ((tp
->dma_rwctrl
& DMA_RWCTRL_WRITE_BNDRY_MASK
) !=
14035 DMA_RWCTRL_WRITE_BNDRY_16
) {
14036 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
14037 tp
->dma_rwctrl
|= DMA_RWCTRL_WRITE_BNDRY_16
;
14038 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
14041 dev_err(&tp
->pdev
->dev
,
14042 "%s: Buffer corrupted on read back! "
14043 "(%d != %d)\n", __func__
, p
[i
], i
);
14049 if (i
== (TEST_BUFFER_SIZE
/ sizeof(u32
))) {
14055 if ((tp
->dma_rwctrl
& DMA_RWCTRL_WRITE_BNDRY_MASK
) !=
14056 DMA_RWCTRL_WRITE_BNDRY_16
) {
14057 static struct pci_device_id dma_wait_state_chipsets
[] = {
14058 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
,
14059 PCI_DEVICE_ID_APPLE_UNI_N_PCI15
) },
14063 /* DMA test passed without adjusting DMA boundary,
14064 * now look for chipsets that are known to expose the
14065 * DMA bug without failing the test.
14067 if (pci_dev_present(dma_wait_state_chipsets
)) {
14068 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
14069 tp
->dma_rwctrl
|= DMA_RWCTRL_WRITE_BNDRY_16
;
14071 /* Safe to use the calculated DMA boundary. */
14072 tp
->dma_rwctrl
= saved_dma_rwctrl
;
14075 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
14079 pci_free_consistent(tp
->pdev
, TEST_BUFFER_SIZE
, buf
, buf_dma
);
14084 static void __devinit
tg3_init_link_config(struct tg3
*tp
)
14086 tp
->link_config
.advertising
=
14087 (ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
14088 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
14089 ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
|
14090 ADVERTISED_Autoneg
| ADVERTISED_MII
);
14091 tp
->link_config
.speed
= SPEED_INVALID
;
14092 tp
->link_config
.duplex
= DUPLEX_INVALID
;
14093 tp
->link_config
.autoneg
= AUTONEG_ENABLE
;
14094 tp
->link_config
.active_speed
= SPEED_INVALID
;
14095 tp
->link_config
.active_duplex
= DUPLEX_INVALID
;
14096 tp
->link_config
.phy_is_low_power
= 0;
14097 tp
->link_config
.orig_speed
= SPEED_INVALID
;
14098 tp
->link_config
.orig_duplex
= DUPLEX_INVALID
;
14099 tp
->link_config
.orig_autoneg
= AUTONEG_INVALID
;
14102 static void __devinit
tg3_init_bufmgr_config(struct tg3
*tp
)
14104 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5717
||
14105 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57765
) {
14106 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
14107 DEFAULT_MB_RDMA_LOW_WATER_5705
;
14108 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
14109 DEFAULT_MB_MACRX_LOW_WATER_57765
;
14110 tp
->bufmgr_config
.mbuf_high_water
=
14111 DEFAULT_MB_HIGH_WATER_57765
;
14113 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
14114 DEFAULT_MB_RDMA_LOW_WATER_5705
;
14115 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
14116 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765
;
14117 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
14118 DEFAULT_MB_HIGH_WATER_JUMBO_57765
;
14119 } else if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
14120 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
14121 DEFAULT_MB_RDMA_LOW_WATER_5705
;
14122 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
14123 DEFAULT_MB_MACRX_LOW_WATER_5705
;
14124 tp
->bufmgr_config
.mbuf_high_water
=
14125 DEFAULT_MB_HIGH_WATER_5705
;
14126 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
14127 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
14128 DEFAULT_MB_MACRX_LOW_WATER_5906
;
14129 tp
->bufmgr_config
.mbuf_high_water
=
14130 DEFAULT_MB_HIGH_WATER_5906
;
14133 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
14134 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780
;
14135 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
14136 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780
;
14137 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
14138 DEFAULT_MB_HIGH_WATER_JUMBO_5780
;
14140 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
14141 DEFAULT_MB_RDMA_LOW_WATER
;
14142 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
14143 DEFAULT_MB_MACRX_LOW_WATER
;
14144 tp
->bufmgr_config
.mbuf_high_water
=
14145 DEFAULT_MB_HIGH_WATER
;
14147 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
14148 DEFAULT_MB_RDMA_LOW_WATER_JUMBO
;
14149 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
14150 DEFAULT_MB_MACRX_LOW_WATER_JUMBO
;
14151 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
14152 DEFAULT_MB_HIGH_WATER_JUMBO
;
14155 tp
->bufmgr_config
.dma_low_water
= DEFAULT_DMA_LOW_WATER
;
14156 tp
->bufmgr_config
.dma_high_water
= DEFAULT_DMA_HIGH_WATER
;
14159 static char * __devinit
tg3_phy_string(struct tg3
*tp
)
14161 switch (tp
->phy_id
& TG3_PHY_ID_MASK
) {
14162 case TG3_PHY_ID_BCM5400
: return "5400";
14163 case TG3_PHY_ID_BCM5401
: return "5401";
14164 case TG3_PHY_ID_BCM5411
: return "5411";
14165 case TG3_PHY_ID_BCM5701
: return "5701";
14166 case TG3_PHY_ID_BCM5703
: return "5703";
14167 case TG3_PHY_ID_BCM5704
: return "5704";
14168 case TG3_PHY_ID_BCM5705
: return "5705";
14169 case TG3_PHY_ID_BCM5750
: return "5750";
14170 case TG3_PHY_ID_BCM5752
: return "5752";
14171 case TG3_PHY_ID_BCM5714
: return "5714";
14172 case TG3_PHY_ID_BCM5780
: return "5780";
14173 case TG3_PHY_ID_BCM5755
: return "5755";
14174 case TG3_PHY_ID_BCM5787
: return "5787";
14175 case TG3_PHY_ID_BCM5784
: return "5784";
14176 case TG3_PHY_ID_BCM5756
: return "5722/5756";
14177 case TG3_PHY_ID_BCM5906
: return "5906";
14178 case TG3_PHY_ID_BCM5761
: return "5761";
14179 case TG3_PHY_ID_BCM5718C
: return "5718C";
14180 case TG3_PHY_ID_BCM5718S
: return "5718S";
14181 case TG3_PHY_ID_BCM57765
: return "57765";
14182 case TG3_PHY_ID_BCM8002
: return "8002/serdes";
14183 case 0: return "serdes";
14184 default: return "unknown";
14188 static char * __devinit
tg3_bus_string(struct tg3
*tp
, char *str
)
14190 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
14191 strcpy(str
, "PCI Express");
14193 } else if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
14194 u32 clock_ctrl
= tr32(TG3PCI_CLOCK_CTRL
) & 0x1f;
14196 strcpy(str
, "PCIX:");
14198 if ((clock_ctrl
== 7) ||
14199 ((tr32(GRC_MISC_CFG
) & GRC_MISC_CFG_BOARD_ID_MASK
) ==
14200 GRC_MISC_CFG_BOARD_ID_5704CIOBE
))
14201 strcat(str
, "133MHz");
14202 else if (clock_ctrl
== 0)
14203 strcat(str
, "33MHz");
14204 else if (clock_ctrl
== 2)
14205 strcat(str
, "50MHz");
14206 else if (clock_ctrl
== 4)
14207 strcat(str
, "66MHz");
14208 else if (clock_ctrl
== 6)
14209 strcat(str
, "100MHz");
14211 strcpy(str
, "PCI:");
14212 if (tp
->tg3_flags
& TG3_FLAG_PCI_HIGH_SPEED
)
14213 strcat(str
, "66MHz");
14215 strcat(str
, "33MHz");
14217 if (tp
->tg3_flags
& TG3_FLAG_PCI_32BIT
)
14218 strcat(str
, ":32-bit");
14220 strcat(str
, ":64-bit");
14224 static struct pci_dev
* __devinit
tg3_find_peer(struct tg3
*tp
)
14226 struct pci_dev
*peer
;
14227 unsigned int func
, devnr
= tp
->pdev
->devfn
& ~7;
14229 for (func
= 0; func
< 8; func
++) {
14230 peer
= pci_get_slot(tp
->pdev
->bus
, devnr
| func
);
14231 if (peer
&& peer
!= tp
->pdev
)
14235 /* 5704 can be configured in single-port mode, set peer to
14236 * tp->pdev in that case.
14244 * We don't need to keep the refcount elevated; there's no way
14245 * to remove one half of this device without removing the other
14252 static void __devinit
tg3_init_coal(struct tg3
*tp
)
14254 struct ethtool_coalesce
*ec
= &tp
->coal
;
14256 memset(ec
, 0, sizeof(*ec
));
14257 ec
->cmd
= ETHTOOL_GCOALESCE
;
14258 ec
->rx_coalesce_usecs
= LOW_RXCOL_TICKS
;
14259 ec
->tx_coalesce_usecs
= LOW_TXCOL_TICKS
;
14260 ec
->rx_max_coalesced_frames
= LOW_RXMAX_FRAMES
;
14261 ec
->tx_max_coalesced_frames
= LOW_TXMAX_FRAMES
;
14262 ec
->rx_coalesce_usecs_irq
= DEFAULT_RXCOAL_TICK_INT
;
14263 ec
->tx_coalesce_usecs_irq
= DEFAULT_TXCOAL_TICK_INT
;
14264 ec
->rx_max_coalesced_frames_irq
= DEFAULT_RXCOAL_MAXF_INT
;
14265 ec
->tx_max_coalesced_frames_irq
= DEFAULT_TXCOAL_MAXF_INT
;
14266 ec
->stats_block_coalesce_usecs
= DEFAULT_STAT_COAL_TICKS
;
14268 if (tp
->coalesce_mode
& (HOSTCC_MODE_CLRTICK_RXBD
|
14269 HOSTCC_MODE_CLRTICK_TXBD
)) {
14270 ec
->rx_coalesce_usecs
= LOW_RXCOL_TICKS_CLRTCKS
;
14271 ec
->rx_coalesce_usecs_irq
= DEFAULT_RXCOAL_TICK_INT_CLRTCKS
;
14272 ec
->tx_coalesce_usecs
= LOW_TXCOL_TICKS_CLRTCKS
;
14273 ec
->tx_coalesce_usecs_irq
= DEFAULT_TXCOAL_TICK_INT_CLRTCKS
;
14276 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
14277 ec
->rx_coalesce_usecs_irq
= 0;
14278 ec
->tx_coalesce_usecs_irq
= 0;
14279 ec
->stats_block_coalesce_usecs
= 0;
14283 static const struct net_device_ops tg3_netdev_ops
= {
14284 .ndo_open
= tg3_open
,
14285 .ndo_stop
= tg3_close
,
14286 .ndo_start_xmit
= tg3_start_xmit
,
14287 .ndo_get_stats
= tg3_get_stats
,
14288 .ndo_validate_addr
= eth_validate_addr
,
14289 .ndo_set_multicast_list
= tg3_set_rx_mode
,
14290 .ndo_set_mac_address
= tg3_set_mac_addr
,
14291 .ndo_do_ioctl
= tg3_ioctl
,
14292 .ndo_tx_timeout
= tg3_tx_timeout
,
14293 .ndo_change_mtu
= tg3_change_mtu
,
14294 #if TG3_VLAN_TAG_USED
14295 .ndo_vlan_rx_register
= tg3_vlan_rx_register
,
14297 #ifdef CONFIG_NET_POLL_CONTROLLER
14298 .ndo_poll_controller
= tg3_poll_controller
,
14302 static const struct net_device_ops tg3_netdev_ops_dma_bug
= {
14303 .ndo_open
= tg3_open
,
14304 .ndo_stop
= tg3_close
,
14305 .ndo_start_xmit
= tg3_start_xmit_dma_bug
,
14306 .ndo_get_stats
= tg3_get_stats
,
14307 .ndo_validate_addr
= eth_validate_addr
,
14308 .ndo_set_multicast_list
= tg3_set_rx_mode
,
14309 .ndo_set_mac_address
= tg3_set_mac_addr
,
14310 .ndo_do_ioctl
= tg3_ioctl
,
14311 .ndo_tx_timeout
= tg3_tx_timeout
,
14312 .ndo_change_mtu
= tg3_change_mtu
,
14313 #if TG3_VLAN_TAG_USED
14314 .ndo_vlan_rx_register
= tg3_vlan_rx_register
,
14316 #ifdef CONFIG_NET_POLL_CONTROLLER
14317 .ndo_poll_controller
= tg3_poll_controller
,
14321 static int __devinit
tg3_init_one(struct pci_dev
*pdev
,
14322 const struct pci_device_id
*ent
)
14324 struct net_device
*dev
;
14326 int i
, err
, pm_cap
;
14327 u32 sndmbx
, rcvmbx
, intmbx
;
14329 u64 dma_mask
, persist_dma_mask
;
14331 printk_once(KERN_INFO
"%s\n", version
);
14333 err
= pci_enable_device(pdev
);
14335 dev_err(&pdev
->dev
, "Cannot enable PCI device, aborting\n");
14339 err
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
14341 dev_err(&pdev
->dev
, "Cannot obtain PCI resources, aborting\n");
14342 goto err_out_disable_pdev
;
14345 pci_set_master(pdev
);
14347 /* Find power-management capability. */
14348 pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
14350 dev_err(&pdev
->dev
,
14351 "Cannot find Power Management capability, aborting\n");
14353 goto err_out_free_res
;
14356 dev
= alloc_etherdev_mq(sizeof(*tp
), TG3_IRQ_MAX_VECS
);
14358 dev_err(&pdev
->dev
, "Etherdev alloc failed, aborting\n");
14360 goto err_out_free_res
;
14363 SET_NETDEV_DEV(dev
, &pdev
->dev
);
14365 #if TG3_VLAN_TAG_USED
14366 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
14369 tp
= netdev_priv(dev
);
14372 tp
->pm_cap
= pm_cap
;
14373 tp
->rx_mode
= TG3_DEF_RX_MODE
;
14374 tp
->tx_mode
= TG3_DEF_TX_MODE
;
14377 tp
->msg_enable
= tg3_debug
;
14379 tp
->msg_enable
= TG3_DEF_MSG_ENABLE
;
14381 /* The word/byte swap controls here control register access byte
14382 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14385 tp
->misc_host_ctrl
=
14386 MISC_HOST_CTRL_MASK_PCI_INT
|
14387 MISC_HOST_CTRL_WORD_SWAP
|
14388 MISC_HOST_CTRL_INDIR_ACCESS
|
14389 MISC_HOST_CTRL_PCISTATE_RW
;
14391 /* The NONFRM (non-frame) byte/word swap controls take effect
14392 * on descriptor entries, anything which isn't packet data.
14394 * The StrongARM chips on the board (one for tx, one for rx)
14395 * are running in big-endian mode.
14397 tp
->grc_mode
= (GRC_MODE_WSWAP_DATA
| GRC_MODE_BSWAP_DATA
|
14398 GRC_MODE_WSWAP_NONFRM_DATA
);
14399 #ifdef __BIG_ENDIAN
14400 tp
->grc_mode
|= GRC_MODE_BSWAP_NONFRM_DATA
;
14402 spin_lock_init(&tp
->lock
);
14403 spin_lock_init(&tp
->indirect_lock
);
14404 INIT_WORK(&tp
->reset_task
, tg3_reset_task
);
14406 tp
->regs
= pci_ioremap_bar(pdev
, BAR_0
);
14408 dev_err(&pdev
->dev
, "Cannot map device registers, aborting\n");
14410 goto err_out_free_dev
;
14413 tg3_init_link_config(tp
);
14415 tp
->rx_pending
= TG3_DEF_RX_RING_PENDING
;
14416 tp
->rx_jumbo_pending
= TG3_DEF_RX_JUMBO_RING_PENDING
;
14418 dev
->ethtool_ops
= &tg3_ethtool_ops
;
14419 dev
->watchdog_timeo
= TG3_TX_TIMEOUT
;
14420 dev
->irq
= pdev
->irq
;
14422 err
= tg3_get_invariants(tp
);
14424 dev_err(&pdev
->dev
,
14425 "Problem fetching invariants of chip, aborting\n");
14426 goto err_out_iounmap
;
14429 if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) &&
14430 tp
->pci_chip_rev_id
!= CHIPREV_ID_5717_A0
)
14431 dev
->netdev_ops
= &tg3_netdev_ops
;
14433 dev
->netdev_ops
= &tg3_netdev_ops_dma_bug
;
14436 /* The EPB bridge inside 5714, 5715, and 5780 and any
14437 * device behind the EPB cannot support DMA addresses > 40-bit.
14438 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14439 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14440 * do DMA address check in tg3_start_xmit().
14442 if (tp
->tg3_flags2
& TG3_FLG2_IS_5788
)
14443 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(32);
14444 else if (tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
) {
14445 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(40);
14446 #ifdef CONFIG_HIGHMEM
14447 dma_mask
= DMA_BIT_MASK(64);
14450 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(64);
14452 /* Configure DMA attributes. */
14453 if (dma_mask
> DMA_BIT_MASK(32)) {
14454 err
= pci_set_dma_mask(pdev
, dma_mask
);
14456 dev
->features
|= NETIF_F_HIGHDMA
;
14457 err
= pci_set_consistent_dma_mask(pdev
,
14460 dev_err(&pdev
->dev
, "Unable to obtain 64 bit "
14461 "DMA for consistent allocations\n");
14462 goto err_out_iounmap
;
14466 if (err
|| dma_mask
== DMA_BIT_MASK(32)) {
14467 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
14469 dev_err(&pdev
->dev
,
14470 "No usable DMA configuration, aborting\n");
14471 goto err_out_iounmap
;
14475 tg3_init_bufmgr_config(tp
);
14477 /* Selectively allow TSO based on operating conditions */
14478 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) ||
14479 (tp
->fw_needed
&& !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)))
14480 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
14482 tp
->tg3_flags2
&= ~(TG3_FLG2_TSO_CAPABLE
| TG3_FLG2_TSO_BUG
);
14483 tp
->fw_needed
= NULL
;
14486 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
)
14487 tp
->fw_needed
= FIRMWARE_TG3
;
14489 /* TSO is on by default on chips that support hardware TSO.
14490 * Firmware TSO on older chips gives lower performance, so it
14491 * is off by default, but can be enabled using ethtool.
14493 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) &&
14494 (dev
->features
& NETIF_F_IP_CSUM
))
14495 dev
->features
|= NETIF_F_TSO
;
14497 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_2
) ||
14498 (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
)) {
14499 if (dev
->features
& NETIF_F_IPV6_CSUM
)
14500 dev
->features
|= NETIF_F_TSO6
;
14501 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO_3
) ||
14502 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
14503 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
14504 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) ||
14505 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
14506 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
14507 dev
->features
|= NETIF_F_TSO_ECN
;
14510 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A1
&&
14511 !(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) &&
14512 !(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
)) {
14513 tp
->tg3_flags2
|= TG3_FLG2_MAX_RXPEND_64
;
14514 tp
->rx_pending
= 63;
14517 err
= tg3_get_device_address(tp
);
14519 dev_err(&pdev
->dev
,
14520 "Could not obtain valid ethernet address, aborting\n");
14521 goto err_out_iounmap
;
14524 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
14525 tp
->aperegs
= pci_ioremap_bar(pdev
, BAR_2
);
14526 if (!tp
->aperegs
) {
14527 dev_err(&pdev
->dev
,
14528 "Cannot map APE registers, aborting\n");
14530 goto err_out_iounmap
;
14533 tg3_ape_lock_init(tp
);
14535 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)
14536 tg3_read_dash_ver(tp
);
14540 * Reset chip in case UNDI or EFI driver did not shutdown
14541 * DMA self test will enable WDMAC and we'll see (spurious)
14542 * pending DMA on the PCI bus at that point.
14544 if ((tr32(HOSTCC_MODE
) & HOSTCC_MODE_ENABLE
) ||
14545 (tr32(WDMAC_MODE
) & WDMAC_MODE_ENABLE
)) {
14546 tw32(MEMARB_MODE
, MEMARB_MODE_ENABLE
);
14547 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
14550 err
= tg3_test_dma(tp
);
14552 dev_err(&pdev
->dev
, "DMA engine test failed, aborting\n");
14553 goto err_out_apeunmap
;
14556 /* flow control autonegotiation is default behavior */
14557 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
14558 tp
->link_config
.flowctrl
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
14560 intmbx
= MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
;
14561 rcvmbx
= MAILBOX_RCVRET_CON_IDX_0
+ TG3_64BIT_REG_LOW
;
14562 sndmbx
= MAILBOX_SNDHOST_PROD_IDX_0
+ TG3_64BIT_REG_LOW
;
14563 for (i
= 0; i
< TG3_IRQ_MAX_VECS
; i
++) {
14564 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
14567 tnapi
->tx_pending
= TG3_DEF_TX_RING_PENDING
;
14569 tnapi
->int_mbox
= intmbx
;
14575 tnapi
->consmbox
= rcvmbx
;
14576 tnapi
->prodmbox
= sndmbx
;
14579 tnapi
->coal_now
= HOSTCC_MODE_COAL_VEC1_NOW
<< (i
- 1);
14580 netif_napi_add(dev
, &tnapi
->napi
, tg3_poll_msix
, 64);
14582 tnapi
->coal_now
= HOSTCC_MODE_NOW
;
14583 netif_napi_add(dev
, &tnapi
->napi
, tg3_poll
, 64);
14586 if (!(tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSIX
))
14590 * If we support MSIX, we'll be using RSS. If we're using
14591 * RSS, the first vector only handles link interrupts and the
14592 * remaining vectors handle rx and tx interrupts. Reuse the
14593 * mailbox values for the next iteration. The values we setup
14594 * above are still useful for the single vectored mode.
14609 pci_set_drvdata(pdev
, dev
);
14611 err
= register_netdev(dev
);
14613 dev_err(&pdev
->dev
, "Cannot register net device, aborting\n");
14614 goto err_out_apeunmap
;
14617 netdev_info(dev
, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14618 tp
->board_part_number
,
14619 tp
->pci_chip_rev_id
,
14620 tg3_bus_string(tp
, str
),
14623 if (tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
) {
14624 struct phy_device
*phydev
;
14625 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
14627 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14628 phydev
->drv
->name
, dev_name(&phydev
->dev
));
14630 netdev_info(dev
, "attached PHY is %s (%s Ethernet) "
14631 "(WireSpeed[%d])\n", tg3_phy_string(tp
),
14632 ((tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
) ? "10/100Base-TX" :
14633 ((tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
) ? "1000Base-SX" :
14634 "10/100/1000Base-T")),
14635 (tp
->tg3_flags2
& TG3_FLG2_NO_ETH_WIRE_SPEED
) == 0);
14637 netdev_info(dev
, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14638 (tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) != 0,
14639 (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) != 0,
14640 (tp
->tg3_flags
& TG3_FLAG_USE_MI_INTERRUPT
) != 0,
14641 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0,
14642 (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) != 0);
14643 netdev_info(dev
, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14645 pdev
->dma_mask
== DMA_BIT_MASK(32) ? 32 :
14646 ((u64
)pdev
->dma_mask
) == DMA_BIT_MASK(40) ? 40 : 64);
14652 iounmap(tp
->aperegs
);
14653 tp
->aperegs
= NULL
;
14666 pci_release_regions(pdev
);
14668 err_out_disable_pdev
:
14669 pci_disable_device(pdev
);
14670 pci_set_drvdata(pdev
, NULL
);
14674 static void __devexit
tg3_remove_one(struct pci_dev
*pdev
)
14676 struct net_device
*dev
= pci_get_drvdata(pdev
);
14679 struct tg3
*tp
= netdev_priv(dev
);
14682 release_firmware(tp
->fw
);
14684 flush_scheduled_work();
14686 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
14691 unregister_netdev(dev
);
14693 iounmap(tp
->aperegs
);
14694 tp
->aperegs
= NULL
;
14701 pci_release_regions(pdev
);
14702 pci_disable_device(pdev
);
14703 pci_set_drvdata(pdev
, NULL
);
14707 static int tg3_suspend(struct pci_dev
*pdev
, pm_message_t state
)
14709 struct net_device
*dev
= pci_get_drvdata(pdev
);
14710 struct tg3
*tp
= netdev_priv(dev
);
14711 pci_power_t target_state
;
14714 /* PCI register 4 needs to be saved whether netif_running() or not.
14715 * MSI address and data need to be saved if using MSI and
14718 pci_save_state(pdev
);
14720 if (!netif_running(dev
))
14723 flush_scheduled_work();
14725 tg3_netif_stop(tp
);
14727 del_timer_sync(&tp
->timer
);
14729 tg3_full_lock(tp
, 1);
14730 tg3_disable_ints(tp
);
14731 tg3_full_unlock(tp
);
14733 netif_device_detach(dev
);
14735 tg3_full_lock(tp
, 0);
14736 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
14737 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
14738 tg3_full_unlock(tp
);
14740 target_state
= pdev
->pm_cap
? pci_target_state(pdev
) : PCI_D3hot
;
14742 err
= tg3_set_power_state(tp
, target_state
);
14746 tg3_full_lock(tp
, 0);
14748 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
14749 err2
= tg3_restart_hw(tp
, 1);
14753 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
14754 add_timer(&tp
->timer
);
14756 netif_device_attach(dev
);
14757 tg3_netif_start(tp
);
14760 tg3_full_unlock(tp
);
14769 static int tg3_resume(struct pci_dev
*pdev
)
14771 struct net_device
*dev
= pci_get_drvdata(pdev
);
14772 struct tg3
*tp
= netdev_priv(dev
);
14775 pci_restore_state(tp
->pdev
);
14777 if (!netif_running(dev
))
14780 err
= tg3_set_power_state(tp
, PCI_D0
);
14784 netif_device_attach(dev
);
14786 tg3_full_lock(tp
, 0);
14788 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
14789 err
= tg3_restart_hw(tp
, 1);
14793 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
14794 add_timer(&tp
->timer
);
14796 tg3_netif_start(tp
);
14799 tg3_full_unlock(tp
);
14807 static struct pci_driver tg3_driver
= {
14808 .name
= DRV_MODULE_NAME
,
14809 .id_table
= tg3_pci_tbl
,
14810 .probe
= tg3_init_one
,
14811 .remove
= __devexit_p(tg3_remove_one
),
14812 .suspend
= tg3_suspend
,
14813 .resume
= tg3_resume
14816 static int __init
tg3_init(void)
14818 return pci_register_driver(&tg3_driver
);
14821 static void __exit
tg3_cleanup(void)
14823 pci_unregister_driver(&tg3_driver
);
14826 module_init(tg3_init
);
14827 module_exit(tg3_cleanup
);