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License cleanup: add SPDX GPL-2.0 license identifier to files with no license
[linux-2.6/btrfs-unstable.git] / drivers / crypto / marvell / cesa.h
blob0032e3bf46ee436ea8587376c39fce15ac4e4762
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __MARVELL_CESA_H__
3 #define __MARVELL_CESA_H__
4
5 #include <crypto/algapi.h>
6 #include <crypto/hash.h>
7 #include <crypto/internal/hash.h>
8
9 #include <linux/crypto.h>
10 #include <linux/dmapool.h>
11
12 #define CESA_ENGINE_OFF(i) (((i) * 0x2000))
13
14 #define CESA_TDMA_BYTE_CNT 0x800
15 #define CESA_TDMA_SRC_ADDR 0x810
16 #define CESA_TDMA_DST_ADDR 0x820
17 #define CESA_TDMA_NEXT_ADDR 0x830
18
19 #define CESA_TDMA_CONTROL 0x840
20 #define CESA_TDMA_DST_BURST GENMASK(2, 0)
21 #define CESA_TDMA_DST_BURST_32B 3
22 #define CESA_TDMA_DST_BURST_128B 4
23 #define CESA_TDMA_OUT_RD_EN BIT(4)
24 #define CESA_TDMA_SRC_BURST GENMASK(8, 6)
25 #define CESA_TDMA_SRC_BURST_32B (3 << 6)
26 #define CESA_TDMA_SRC_BURST_128B (4 << 6)
27 #define CESA_TDMA_CHAIN BIT(9)
28 #define CESA_TDMA_BYTE_SWAP BIT(11)
29 #define CESA_TDMA_NO_BYTE_SWAP BIT(11)
30 #define CESA_TDMA_EN BIT(12)
31 #define CESA_TDMA_FETCH_ND BIT(13)
32 #define CESA_TDMA_ACT BIT(14)
33
34 #define CESA_TDMA_CUR 0x870
35 #define CESA_TDMA_ERROR_CAUSE 0x8c8
36 #define CESA_TDMA_ERROR_MSK 0x8cc
37
38 #define CESA_TDMA_WINDOW_BASE(x) (((x) * 0x8) + 0xa00)
39 #define CESA_TDMA_WINDOW_CTRL(x) (((x) * 0x8) + 0xa04)
40
41 #define CESA_IVDIG(x) (0xdd00 + ((x) * 4) + \
42 (((x) < 5) ? 0 : 0x14))
43
44 #define CESA_SA_CMD 0xde00
45 #define CESA_SA_CMD_EN_CESA_SA_ACCL0 BIT(0)
46 #define CESA_SA_CMD_EN_CESA_SA_ACCL1 BIT(1)
47 #define CESA_SA_CMD_DISABLE_SEC BIT(2)
48
49 #define CESA_SA_DESC_P0 0xde04
50
51 #define CESA_SA_DESC_P1 0xde14
52
53 #define CESA_SA_CFG 0xde08
54 #define CESA_SA_CFG_STOP_DIG_ERR GENMASK(1, 0)
55 #define CESA_SA_CFG_DIG_ERR_CONT 0
56 #define CESA_SA_CFG_DIG_ERR_SKIP 1
57 #define CESA_SA_CFG_DIG_ERR_STOP 3
58 #define CESA_SA_CFG_CH0_W_IDMA BIT(7)
59 #define CESA_SA_CFG_CH1_W_IDMA BIT(8)
60 #define CESA_SA_CFG_ACT_CH0_IDMA BIT(9)
61 #define CESA_SA_CFG_ACT_CH1_IDMA BIT(10)
62 #define CESA_SA_CFG_MULTI_PKT BIT(11)
63 #define CESA_SA_CFG_PARA_DIS BIT(13)
64
65 #define CESA_SA_ACCEL_STATUS 0xde0c
66 #define CESA_SA_ST_ACT_0 BIT(0)
67 #define CESA_SA_ST_ACT_1 BIT(1)
68
69 /*
70 * CESA_SA_FPGA_INT_STATUS looks like a FPGA leftover and is documented only
71 * in Errata 4.12. It looks like that it was part of an IRQ-controller in FPGA
72 * and someone forgot to remove it while switching to the core and moving to
73 * CESA_SA_INT_STATUS.
74 */
75 #define CESA_SA_FPGA_INT_STATUS 0xdd68
76 #define CESA_SA_INT_STATUS 0xde20
77 #define CESA_SA_INT_AUTH_DONE BIT(0)
78 #define CESA_SA_INT_DES_E_DONE BIT(1)
79 #define CESA_SA_INT_AES_E_DONE BIT(2)
80 #define CESA_SA_INT_AES_D_DONE BIT(3)
81 #define CESA_SA_INT_ENC_DONE BIT(4)
82 #define CESA_SA_INT_ACCEL0_DONE BIT(5)
83 #define CESA_SA_INT_ACCEL1_DONE BIT(6)
84 #define CESA_SA_INT_ACC0_IDMA_DONE BIT(7)
85 #define CESA_SA_INT_ACC1_IDMA_DONE BIT(8)
86 #define CESA_SA_INT_IDMA_DONE BIT(9)
87 #define CESA_SA_INT_IDMA_OWN_ERR BIT(10)
88
89 #define CESA_SA_INT_MSK 0xde24
90
91 #define CESA_SA_DESC_CFG_OP_MAC_ONLY 0
92 #define CESA_SA_DESC_CFG_OP_CRYPT_ONLY 1
93 #define CESA_SA_DESC_CFG_OP_MAC_CRYPT 2
94 #define CESA_SA_DESC_CFG_OP_CRYPT_MAC 3
95 #define CESA_SA_DESC_CFG_OP_MSK GENMASK(1, 0)
96 #define CESA_SA_DESC_CFG_MACM_SHA256 (1 << 4)
97 #define CESA_SA_DESC_CFG_MACM_HMAC_SHA256 (3 << 4)
98 #define CESA_SA_DESC_CFG_MACM_MD5 (4 << 4)
99 #define CESA_SA_DESC_CFG_MACM_SHA1 (5 << 4)
100 #define CESA_SA_DESC_CFG_MACM_HMAC_MD5 (6 << 4)
101 #define CESA_SA_DESC_CFG_MACM_HMAC_SHA1 (7 << 4)
102 #define CESA_SA_DESC_CFG_MACM_MSK GENMASK(6, 4)
103 #define CESA_SA_DESC_CFG_CRYPTM_DES (1 << 8)
104 #define CESA_SA_DESC_CFG_CRYPTM_3DES (2 << 8)
105 #define CESA_SA_DESC_CFG_CRYPTM_AES (3 << 8)
106 #define CESA_SA_DESC_CFG_CRYPTM_MSK GENMASK(9, 8)
107 #define CESA_SA_DESC_CFG_DIR_ENC (0 << 12)
108 #define CESA_SA_DESC_CFG_DIR_DEC (1 << 12)
109 #define CESA_SA_DESC_CFG_CRYPTCM_ECB (0 << 16)
110 #define CESA_SA_DESC_CFG_CRYPTCM_CBC (1 << 16)
111 #define CESA_SA_DESC_CFG_CRYPTCM_MSK BIT(16)
112 #define CESA_SA_DESC_CFG_3DES_EEE (0 << 20)
113 #define CESA_SA_DESC_CFG_3DES_EDE (1 << 20)
114 #define CESA_SA_DESC_CFG_AES_LEN_128 (0 << 24)
115 #define CESA_SA_DESC_CFG_AES_LEN_192 (1 << 24)
116 #define CESA_SA_DESC_CFG_AES_LEN_256 (2 << 24)
117 #define CESA_SA_DESC_CFG_AES_LEN_MSK GENMASK(25, 24)
118 #define CESA_SA_DESC_CFG_NOT_FRAG (0 << 30)
119 #define CESA_SA_DESC_CFG_FIRST_FRAG (1 << 30)
120 #define CESA_SA_DESC_CFG_LAST_FRAG (2 << 30)
121 #define CESA_SA_DESC_CFG_MID_FRAG (3 << 30)
122 #define CESA_SA_DESC_CFG_FRAG_MSK GENMASK(31, 30)
123
124 /*
125 * /-----------\ 0
126 * | ACCEL CFG | 4 * 8
127 * |-----------| 0x20
128 * | CRYPT KEY | 8 * 4
129 * |-----------| 0x40
130 * | IV IN | 4 * 4
131 * |-----------| 0x40 (inplace)
132 * | IV BUF | 4 * 4
133 * |-----------| 0x80
134 * | DATA IN | 16 * x (max ->max_req_size)
135 * |-----------| 0x80 (inplace operation)
136 * | DATA OUT | 16 * x (max ->max_req_size)
137 * \-----------/ SRAM size
138 */
139
140 /*
141 * Hashing memory map:
142 * /-----------\ 0
143 * | ACCEL CFG | 4 * 8
144 * |-----------| 0x20
145 * | Inner IV | 8 * 4
146 * |-----------| 0x40
147 * | Outer IV | 8 * 4
148 * |-----------| 0x60
149 * | Output BUF| 8 * 4
150 * |-----------| 0x80
151 * | DATA IN | 64 * x (max ->max_req_size)
152 * \-----------/ SRAM size
153 */
154
155 #define CESA_SA_CFG_SRAM_OFFSET 0x00
156 #define CESA_SA_DATA_SRAM_OFFSET 0x80
157
158 #define CESA_SA_CRYPT_KEY_SRAM_OFFSET 0x20
159 #define CESA_SA_CRYPT_IV_SRAM_OFFSET 0x40
160
161 #define CESA_SA_MAC_IIV_SRAM_OFFSET 0x20
162 #define CESA_SA_MAC_OIV_SRAM_OFFSET 0x40
163 #define CESA_SA_MAC_DIG_SRAM_OFFSET 0x60
164
165 #define CESA_SA_DESC_CRYPT_DATA(offset) \
166 cpu_to_le32((CESA_SA_DATA_SRAM_OFFSET + (offset)) | \
167 ((CESA_SA_DATA_SRAM_OFFSET + (offset)) << 16))
168
169 #define CESA_SA_DESC_CRYPT_IV(offset) \
170 cpu_to_le32((CESA_SA_CRYPT_IV_SRAM_OFFSET + (offset)) | \
171 ((CESA_SA_CRYPT_IV_SRAM_OFFSET + (offset)) << 16))
172
173 #define CESA_SA_DESC_CRYPT_KEY(offset) \
174 cpu_to_le32(CESA_SA_CRYPT_KEY_SRAM_OFFSET + (offset))
175
176 #define CESA_SA_DESC_MAC_DATA(offset) \
177 cpu_to_le32(CESA_SA_DATA_SRAM_OFFSET + (offset))
178 #define CESA_SA_DESC_MAC_DATA_MSK cpu_to_le32(GENMASK(15, 0))
179
180 #define CESA_SA_DESC_MAC_TOTAL_LEN(total_len) cpu_to_le32((total_len) << 16)
181 #define CESA_SA_DESC_MAC_TOTAL_LEN_MSK cpu_to_le32(GENMASK(31, 16))
182
183 #define CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX 0xffff
184
185 #define CESA_SA_DESC_MAC_DIGEST(offset) \
186 cpu_to_le32(CESA_SA_MAC_DIG_SRAM_OFFSET + (offset))
187 #define CESA_SA_DESC_MAC_DIGEST_MSK cpu_to_le32(GENMASK(15, 0))
188
189 #define CESA_SA_DESC_MAC_FRAG_LEN(frag_len) cpu_to_le32((frag_len) << 16)
190 #define CESA_SA_DESC_MAC_FRAG_LEN_MSK cpu_to_le32(GENMASK(31, 16))
191
192 #define CESA_SA_DESC_MAC_IV(offset) \
193 cpu_to_le32((CESA_SA_MAC_IIV_SRAM_OFFSET + (offset)) | \
194 ((CESA_SA_MAC_OIV_SRAM_OFFSET + (offset)) << 16))
195
196 #define CESA_SA_SRAM_SIZE 2048
197 #define CESA_SA_SRAM_PAYLOAD_SIZE (cesa_dev->sram_size - \
198 CESA_SA_DATA_SRAM_OFFSET)
199
200 #define CESA_SA_DEFAULT_SRAM_SIZE 2048
201 #define CESA_SA_MIN_SRAM_SIZE 1024
202
203 #define CESA_SA_SRAM_MSK (2048 - 1)
204
205 #define CESA_MAX_HASH_BLOCK_SIZE 64
206 #define CESA_HASH_BLOCK_SIZE_MSK (CESA_MAX_HASH_BLOCK_SIZE - 1)
207
208 /**
209 * struct mv_cesa_sec_accel_desc - security accelerator descriptor
210 * @config: engine config
211 * @enc_p: input and output data pointers for a cipher operation
212 * @enc_len: cipher operation length
213 * @enc_key_p: cipher key pointer
214 * @enc_iv: cipher IV pointers
215 * @mac_src_p: input pointer and total hash length
216 * @mac_digest: digest pointer and hash operation length
217 * @mac_iv: hmac IV pointers
218 *
219 * Structure passed to the CESA engine to describe the crypto operation
220 * to be executed.
221 */
222 struct mv_cesa_sec_accel_desc {
223 __le32 config;
224 __le32 enc_p;
225 __le32 enc_len;
226 __le32 enc_key_p;
227 __le32 enc_iv;
228 __le32 mac_src_p;
229 __le32 mac_digest;
230 __le32 mac_iv;
231 };
232
233 /**
234 * struct mv_cesa_blkcipher_op_ctx - cipher operation context
235 * @key: cipher key
236 * @iv: cipher IV
237 *
238 * Context associated to a cipher operation.
239 */
240 struct mv_cesa_blkcipher_op_ctx {
241 u32 key[8];
242 u32 iv[4];
243 };
244
245 /**
246 * struct mv_cesa_hash_op_ctx - hash or hmac operation context
247 * @key: cipher key
248 * @iv: cipher IV
249 *
250 * Context associated to an hash or hmac operation.
251 */
252 struct mv_cesa_hash_op_ctx {
253 u32 iv[16];
254 u32 hash[8];
255 };
256
257 /**
258 * struct mv_cesa_op_ctx - crypto operation context
259 * @desc: CESA descriptor
260 * @ctx: context associated to the crypto operation
261 *
262 * Context associated to a crypto operation.
263 */
264 struct mv_cesa_op_ctx {
265 struct mv_cesa_sec_accel_desc desc;
266 union {
267 struct mv_cesa_blkcipher_op_ctx blkcipher;
268 struct mv_cesa_hash_op_ctx hash;
269 } ctx;
270 };
271
272 /* TDMA descriptor flags */
273 #define CESA_TDMA_DST_IN_SRAM BIT(31)
274 #define CESA_TDMA_SRC_IN_SRAM BIT(30)
275 #define CESA_TDMA_END_OF_REQ BIT(29)
276 #define CESA_TDMA_BREAK_CHAIN BIT(28)
277 #define CESA_TDMA_SET_STATE BIT(27)
278 #define CESA_TDMA_TYPE_MSK GENMASK(26, 0)
279 #define CESA_TDMA_DUMMY 0
280 #define CESA_TDMA_DATA 1
281 #define CESA_TDMA_OP 2
282 #define CESA_TDMA_RESULT 3
283
284 /**
285 * struct mv_cesa_tdma_desc - TDMA descriptor
286 * @byte_cnt: number of bytes to transfer
287 * @src: DMA address of the source
288 * @dst: DMA address of the destination
289 * @next_dma: DMA address of the next TDMA descriptor
290 * @cur_dma: DMA address of this TDMA descriptor
291 * @next: pointer to the next TDMA descriptor
292 * @op: CESA operation attached to this TDMA descriptor
293 * @data: raw data attached to this TDMA descriptor
294 * @flags: flags describing the TDMA transfer. See the
295 * "TDMA descriptor flags" section above
296 *
297 * TDMA descriptor used to create a transfer chain describing a crypto
298 * operation.
299 */
300 struct mv_cesa_tdma_desc {
301 __le32 byte_cnt;
302 __le32 src;
303 __le32 dst;
304 __le32 next_dma;
305
306 /* Software state */
307 dma_addr_t cur_dma;
308 struct mv_cesa_tdma_desc *next;
309 union {
310 struct mv_cesa_op_ctx *op;
311 void *data;
312 };
313 u32 flags;
314 };
315
316 /**
317 * struct mv_cesa_sg_dma_iter - scatter-gather iterator
318 * @dir: transfer direction
319 * @sg: scatter list
320 * @offset: current position in the scatter list
321 * @op_offset: current position in the crypto operation
322 *
323 * Iterator used to iterate over a scatterlist while creating a TDMA chain for
324 * a crypto operation.
325 */
326 struct mv_cesa_sg_dma_iter {
327 enum dma_data_direction dir;
328 struct scatterlist *sg;
329 unsigned int offset;
330 unsigned int op_offset;
331 };
332
333 /**
334 * struct mv_cesa_dma_iter - crypto operation iterator
335 * @len: the crypto operation length
336 * @offset: current position in the crypto operation
337 * @op_len: sub-operation length (the crypto engine can only act on 2kb
338 * chunks)
339 *
340 * Iterator used to create a TDMA chain for a given crypto operation.
341 */
342 struct mv_cesa_dma_iter {
343 unsigned int len;
344 unsigned int offset;
345 unsigned int op_len;
346 };
347
348 /**
349 * struct mv_cesa_tdma_chain - TDMA chain
350 * @first: first entry in the TDMA chain
351 * @last: last entry in the TDMA chain
352 *
353 * Stores a TDMA chain for a specific crypto operation.
354 */
355 struct mv_cesa_tdma_chain {
356 struct mv_cesa_tdma_desc *first;
357 struct mv_cesa_tdma_desc *last;
358 };
359
360 struct mv_cesa_engine;
361
362 /**
363 * struct mv_cesa_caps - CESA device capabilities
364 * @engines: number of engines
365 * @has_tdma: whether this device has a TDMA block
366 * @cipher_algs: supported cipher algorithms
367 * @ncipher_algs: number of supported cipher algorithms
368 * @ahash_algs: supported hash algorithms
369 * @nahash_algs: number of supported hash algorithms
370 *
371 * Structure used to describe CESA device capabilities.
372 */
373 struct mv_cesa_caps {
374 int nengines;
375 bool has_tdma;
376 struct crypto_alg **cipher_algs;
377 int ncipher_algs;
378 struct ahash_alg **ahash_algs;
379 int nahash_algs;
380 };
381
382 /**
383 * struct mv_cesa_dev_dma - DMA pools
384 * @tdma_desc_pool: TDMA desc pool
385 * @op_pool: crypto operation pool
386 * @cache_pool: data cache pool (used by hash implementation when the
387 * hash request is smaller than the hash block size)
388 * @padding_pool: padding pool (used by hash implementation when hardware
389 * padding cannot be used)
390 *
391 * Structure containing the different DMA pools used by this driver.
392 */
393 struct mv_cesa_dev_dma {
394 struct dma_pool *tdma_desc_pool;
395 struct dma_pool *op_pool;
396 struct dma_pool *cache_pool;
397 struct dma_pool *padding_pool;
398 };
399
400 /**
401 * struct mv_cesa_dev - CESA device
402 * @caps: device capabilities
403 * @regs: device registers
404 * @sram_size: usable SRAM size
405 * @lock: device lock
406 * @engines: array of engines
407 * @dma: dma pools
408 *
409 * Structure storing CESA device information.
410 */
411 struct mv_cesa_dev {
412 const struct mv_cesa_caps *caps;
413 void __iomem *regs;
414 struct device *dev;
415 unsigned int sram_size;
416 spinlock_t lock;
417 struct mv_cesa_engine *engines;
418 struct mv_cesa_dev_dma *dma;
419 };
420
421 /**
422 * struct mv_cesa_engine - CESA engine
423 * @id: engine id
424 * @regs: engine registers
425 * @sram: SRAM memory region
426 * @sram_dma: DMA address of the SRAM memory region
427 * @lock: engine lock
428 * @req: current crypto request
429 * @clk: engine clk
430 * @zclk: engine zclk
431 * @max_req_len: maximum chunk length (useful to create the TDMA chain)
432 * @int_mask: interrupt mask cache
433 * @pool: memory pool pointing to the memory region reserved in
434 * SRAM
435 * @queue: fifo of the pending crypto requests
436 * @load: engine load counter, useful for load balancing
437 * @chain: list of the current tdma descriptors being processed
438 * by this engine.
439 * @complete_queue: fifo of the processed requests by the engine
440 *
441 * Structure storing CESA engine information.
442 */
443 struct mv_cesa_engine {
444 int id;
445 void __iomem *regs;
446 void __iomem *sram;
447 dma_addr_t sram_dma;
448 spinlock_t lock;
449 struct crypto_async_request *req;
450 struct clk *clk;
451 struct clk *zclk;
452 size_t max_req_len;
453 u32 int_mask;
454 struct gen_pool *pool;
455 struct crypto_queue queue;
456 atomic_t load;
457 struct mv_cesa_tdma_chain chain;
458 struct list_head complete_queue;
459 };
460
461 /**
462 * struct mv_cesa_req_ops - CESA request operations
463 * @process: process a request chunk result (should return 0 if the
464 * operation, -EINPROGRESS if it needs more steps or an error
465 * code)
466 * @step: launch the crypto operation on the next chunk
467 * @cleanup: cleanup the crypto request (release associated data)
468 * @complete: complete the request, i.e copy result or context from sram when
469 * needed.
470 */
471 struct mv_cesa_req_ops {
472 int (*process)(struct crypto_async_request *req, u32 status);
473 void (*step)(struct crypto_async_request *req);
474 void (*cleanup)(struct crypto_async_request *req);
475 void (*complete)(struct crypto_async_request *req);
476 };
477
478 /**
479 * struct mv_cesa_ctx - CESA operation context
480 * @ops: crypto operations
481 *
482 * Base context structure inherited by operation specific ones.
483 */
484 struct mv_cesa_ctx {
485 const struct mv_cesa_req_ops *ops;
486 };
487
488 /**
489 * struct mv_cesa_hash_ctx - CESA hash operation context
490 * @base: base context structure
491 *
492 * Hash context structure.
493 */
494 struct mv_cesa_hash_ctx {
495 struct mv_cesa_ctx base;
496 };
497
498 /**
499 * struct mv_cesa_hash_ctx - CESA hmac operation context
500 * @base: base context structure
501 * @iv: initialization vectors
502 *
503 * HMAC context structure.
504 */
505 struct mv_cesa_hmac_ctx {
506 struct mv_cesa_ctx base;
507 u32 iv[16];
508 };
509
510 /**
511 * enum mv_cesa_req_type - request type definitions
512 * @CESA_STD_REQ: standard request
513 * @CESA_DMA_REQ: DMA request
514 */
515 enum mv_cesa_req_type {
516 CESA_STD_REQ,
517 CESA_DMA_REQ,
518 };
519
520 /**
521 * struct mv_cesa_req - CESA request
522 * @engine: engine associated with this request
523 * @chain: list of tdma descriptors associated with this request
524 */
525 struct mv_cesa_req {
526 struct mv_cesa_engine *engine;
527 struct mv_cesa_tdma_chain chain;
528 };
529
530 /**
531 * struct mv_cesa_sg_std_iter - CESA scatter-gather iterator for standard
532 * requests
533 * @iter: sg mapping iterator
534 * @offset: current offset in the SG entry mapped in memory
535 */
536 struct mv_cesa_sg_std_iter {
537 struct sg_mapping_iter iter;
538 unsigned int offset;
539 };
540
541 /**
542 * struct mv_cesa_ablkcipher_std_req - cipher standard request
543 * @op: operation context
544 * @offset: current operation offset
545 * @size: size of the crypto operation
546 */
547 struct mv_cesa_ablkcipher_std_req {
548 struct mv_cesa_op_ctx op;
549 unsigned int offset;
550 unsigned int size;
551 bool skip_ctx;
552 };
553
554 /**
555 * struct mv_cesa_ablkcipher_req - cipher request
556 * @req: type specific request information
557 * @src_nents: number of entries in the src sg list
558 * @dst_nents: number of entries in the dest sg list
559 */
560 struct mv_cesa_ablkcipher_req {
561 struct mv_cesa_req base;
562 struct mv_cesa_ablkcipher_std_req std;
563 int src_nents;
564 int dst_nents;
565 };
566
567 /**
568 * struct mv_cesa_ahash_std_req - standard hash request
569 * @offset: current operation offset
570 */
571 struct mv_cesa_ahash_std_req {
572 unsigned int offset;
573 };
574
575 /**
576 * struct mv_cesa_ahash_dma_req - DMA hash request
577 * @padding: padding buffer
578 * @padding_dma: DMA address of the padding buffer
579 * @cache_dma: DMA address of the cache buffer
580 */
581 struct mv_cesa_ahash_dma_req {
582 u8 *padding;
583 dma_addr_t padding_dma;
584 u8 *cache;
585 dma_addr_t cache_dma;
586 };
587
588 /**
589 * struct mv_cesa_ahash_req - hash request
590 * @req: type specific request information
591 * @cache: cache buffer
592 * @cache_ptr: write pointer in the cache buffer
593 * @len: hash total length
594 * @src_nents: number of entries in the scatterlist
595 * @last_req: define whether the current operation is the last one
596 * or not
597 * @state: hash state
598 */
599 struct mv_cesa_ahash_req {
600 struct mv_cesa_req base;
601 union {
602 struct mv_cesa_ahash_dma_req dma;
603 struct mv_cesa_ahash_std_req std;
604 } req;
605 struct mv_cesa_op_ctx op_tmpl;
606 u8 cache[CESA_MAX_HASH_BLOCK_SIZE];
607 unsigned int cache_ptr;
608 u64 len;
609 int src_nents;
610 bool last_req;
611 bool algo_le;
612 u32 state[8];
613 };
614
615 /* CESA functions */
616
617 extern struct mv_cesa_dev *cesa_dev;
618
619
620 static inline void
621 mv_cesa_engine_enqueue_complete_request(struct mv_cesa_engine *engine,
622 struct crypto_async_request *req)
623 {
624 list_add_tail(&req->list, &engine->complete_queue);
625 }
626
627 static inline struct crypto_async_request *
628 mv_cesa_engine_dequeue_complete_request(struct mv_cesa_engine *engine)
629 {
630 struct crypto_async_request *req;
631
632 req = list_first_entry_or_null(&engine->complete_queue,
633 struct crypto_async_request,
634 list);
635 if (req)
636 list_del(&req->list);
637
638 return req;
639 }
640
641
642 static inline enum mv_cesa_req_type
643 mv_cesa_req_get_type(struct mv_cesa_req *req)
644 {
645 return req->chain.first ? CESA_DMA_REQ : CESA_STD_REQ;
646 }
647
648 static inline void mv_cesa_update_op_cfg(struct mv_cesa_op_ctx *op,
649 u32 cfg, u32 mask)
650 {
651 op->desc.config &= cpu_to_le32(~mask);
652 op->desc.config |= cpu_to_le32(cfg);
653 }
654
655 static inline u32 mv_cesa_get_op_cfg(const struct mv_cesa_op_ctx *op)
656 {
657 return le32_to_cpu(op->desc.config);
658 }
659
660 static inline void mv_cesa_set_op_cfg(struct mv_cesa_op_ctx *op, u32 cfg)
661 {
662 op->desc.config = cpu_to_le32(cfg);
663 }
664
665 static inline void mv_cesa_adjust_op(struct mv_cesa_engine *engine,
666 struct mv_cesa_op_ctx *op)
667 {
668 u32 offset = engine->sram_dma & CESA_SA_SRAM_MSK;
669
670 op->desc.enc_p = CESA_SA_DESC_CRYPT_DATA(offset);
671 op->desc.enc_key_p = CESA_SA_DESC_CRYPT_KEY(offset);
672 op->desc.enc_iv = CESA_SA_DESC_CRYPT_IV(offset);
673 op->desc.mac_src_p &= ~CESA_SA_DESC_MAC_DATA_MSK;
674 op->desc.mac_src_p |= CESA_SA_DESC_MAC_DATA(offset);
675 op->desc.mac_digest &= ~CESA_SA_DESC_MAC_DIGEST_MSK;
676 op->desc.mac_digest |= CESA_SA_DESC_MAC_DIGEST(offset);
677 op->desc.mac_iv = CESA_SA_DESC_MAC_IV(offset);
678 }
679
680 static inline void mv_cesa_set_crypt_op_len(struct mv_cesa_op_ctx *op, int len)
681 {
682 op->desc.enc_len = cpu_to_le32(len);
683 }
684
685 static inline void mv_cesa_set_mac_op_total_len(struct mv_cesa_op_ctx *op,
686 int len)
687 {
688 op->desc.mac_src_p &= ~CESA_SA_DESC_MAC_TOTAL_LEN_MSK;
689 op->desc.mac_src_p |= CESA_SA_DESC_MAC_TOTAL_LEN(len);
690 }
691
692 static inline void mv_cesa_set_mac_op_frag_len(struct mv_cesa_op_ctx *op,
693 int len)
694 {
695 op->desc.mac_digest &= ~CESA_SA_DESC_MAC_FRAG_LEN_MSK;
696 op->desc.mac_digest |= CESA_SA_DESC_MAC_FRAG_LEN(len);
697 }
698
699 static inline void mv_cesa_set_int_mask(struct mv_cesa_engine *engine,
700 u32 int_mask)
701 {
702 if (int_mask == engine->int_mask)
703 return;
704
705 writel_relaxed(int_mask, engine->regs + CESA_SA_INT_MSK);
706 engine->int_mask = int_mask;
707 }
708
709 static inline u32 mv_cesa_get_int_mask(struct mv_cesa_engine *engine)
710 {
711 return engine->int_mask;
712 }
713
714 static inline bool mv_cesa_mac_op_is_first_frag(const struct mv_cesa_op_ctx *op)
715 {
716 return (mv_cesa_get_op_cfg(op) & CESA_SA_DESC_CFG_FRAG_MSK) ==
717 CESA_SA_DESC_CFG_FIRST_FRAG;
718 }
719
720 int mv_cesa_queue_req(struct crypto_async_request *req,
721 struct mv_cesa_req *creq);
722
723 struct crypto_async_request *
724 mv_cesa_dequeue_req_locked(struct mv_cesa_engine *engine,
725 struct crypto_async_request **backlog);
726
727 static inline struct mv_cesa_engine *mv_cesa_select_engine(int weight)
728 {
729 int i;
730 u32 min_load = U32_MAX;
731 struct mv_cesa_engine *selected = NULL;
732
733 for (i = 0; i < cesa_dev->caps->nengines; i++) {
734 struct mv_cesa_engine *engine = cesa_dev->engines + i;
735 u32 load = atomic_read(&engine->load);
736 if (load < min_load) {
737 min_load = load;
738 selected = engine;
739 }
740 }
741
742 atomic_add(weight, &selected->load);
743
744 return selected;
745 }
746
747 /*
748 * Helper function that indicates whether a crypto request needs to be
749 * cleaned up or not after being enqueued using mv_cesa_queue_req().
750 */
751 static inline int mv_cesa_req_needs_cleanup(struct crypto_async_request *req,
752 int ret)
753 {
754 /*
755 * The queue still had some space, the request was queued
756 * normally, so there's no need to clean it up.
757 */
758 if (ret == -EINPROGRESS)
759 return false;
760
761 /*
762 * The queue had not space left, but since the request is
763 * flagged with CRYPTO_TFM_REQ_MAY_BACKLOG, it was added to
764 * the backlog and will be processed later. There's no need to
765 * clean it up.
766 */
767 if (ret == -EBUSY && req->flags & CRYPTO_TFM_REQ_MAY_BACKLOG)
768 return false;
769
770 /* Request wasn't queued, we need to clean it up */
771 return true;
772 }
773
774 /* TDMA functions */
775
776 static inline void mv_cesa_req_dma_iter_init(struct mv_cesa_dma_iter *iter,
777 unsigned int len)
778 {
779 iter->len = len;
780 iter->op_len = min(len, CESA_SA_SRAM_PAYLOAD_SIZE);
781 iter->offset = 0;
782 }
783
784 static inline void mv_cesa_sg_dma_iter_init(struct mv_cesa_sg_dma_iter *iter,
785 struct scatterlist *sg,
786 enum dma_data_direction dir)
787 {
788 iter->op_offset = 0;
789 iter->offset = 0;
790 iter->sg = sg;
791 iter->dir = dir;
792 }
793
794 static inline unsigned int
795 mv_cesa_req_dma_iter_transfer_len(struct mv_cesa_dma_iter *iter,
796 struct mv_cesa_sg_dma_iter *sgiter)
797 {
798 return min(iter->op_len - sgiter->op_offset,
799 sg_dma_len(sgiter->sg) - sgiter->offset);
800 }
801
802 bool mv_cesa_req_dma_iter_next_transfer(struct mv_cesa_dma_iter *chain,
803 struct mv_cesa_sg_dma_iter *sgiter,
804 unsigned int len);
805
806 static inline bool mv_cesa_req_dma_iter_next_op(struct mv_cesa_dma_iter *iter)
807 {
808 iter->offset += iter->op_len;
809 iter->op_len = min(iter->len - iter->offset,
810 CESA_SA_SRAM_PAYLOAD_SIZE);
811
812 return iter->op_len;
813 }
814
815 void mv_cesa_dma_step(struct mv_cesa_req *dreq);
816
817 static inline int mv_cesa_dma_process(struct mv_cesa_req *dreq,
818 u32 status)
819 {
820 if (!(status & CESA_SA_INT_ACC0_IDMA_DONE))
821 return -EINPROGRESS;
822
823 if (status & CESA_SA_INT_IDMA_OWN_ERR)
824 return -EINVAL;
825
826 return 0;
827 }
828
829 void mv_cesa_dma_prepare(struct mv_cesa_req *dreq,
830 struct mv_cesa_engine *engine);
831 void mv_cesa_dma_cleanup(struct mv_cesa_req *dreq);
832 void mv_cesa_tdma_chain(struct mv_cesa_engine *engine,
833 struct mv_cesa_req *dreq);
834 int mv_cesa_tdma_process(struct mv_cesa_engine *engine, u32 status);
835
836
837 static inline void
838 mv_cesa_tdma_desc_iter_init(struct mv_cesa_tdma_chain *chain)
839 {
840 memset(chain, 0, sizeof(*chain));
841 }
842
843 int mv_cesa_dma_add_result_op(struct mv_cesa_tdma_chain *chain, dma_addr_t src,
844 u32 size, u32 flags, gfp_t gfp_flags);
845
846 struct mv_cesa_op_ctx *mv_cesa_dma_add_op(struct mv_cesa_tdma_chain *chain,
847 const struct mv_cesa_op_ctx *op_templ,
848 bool skip_ctx,
849 gfp_t flags);
850
851 int mv_cesa_dma_add_data_transfer(struct mv_cesa_tdma_chain *chain,
852 dma_addr_t dst, dma_addr_t src, u32 size,
853 u32 flags, gfp_t gfp_flags);
854
855 int mv_cesa_dma_add_dummy_launch(struct mv_cesa_tdma_chain *chain, gfp_t flags);
856 int mv_cesa_dma_add_dummy_end(struct mv_cesa_tdma_chain *chain, gfp_t flags);
857
858 int mv_cesa_dma_add_op_transfers(struct mv_cesa_tdma_chain *chain,
859 struct mv_cesa_dma_iter *dma_iter,
860 struct mv_cesa_sg_dma_iter *sgiter,
861 gfp_t gfp_flags);
862
863 /* Algorithm definitions */
864
865 extern struct ahash_alg mv_md5_alg;
866 extern struct ahash_alg mv_sha1_alg;
867 extern struct ahash_alg mv_sha256_alg;
868 extern struct ahash_alg mv_ahmac_md5_alg;
869 extern struct ahash_alg mv_ahmac_sha1_alg;
870 extern struct ahash_alg mv_ahmac_sha256_alg;
871
872 extern struct crypto_alg mv_cesa_ecb_des_alg;
873 extern struct crypto_alg mv_cesa_cbc_des_alg;
874 extern struct crypto_alg mv_cesa_ecb_des3_ede_alg;
875 extern struct crypto_alg mv_cesa_cbc_des3_ede_alg;
876 extern struct crypto_alg mv_cesa_ecb_aes_alg;
877 extern struct crypto_alg mv_cesa_cbc_aes_alg;
878
879 #endif /* __MARVELL_CESA_H__ */
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