PCI: enumerate the PCI device only removed out PCI hieratchy of OS when re-scanning PCI
[linux-2.6/btrfs-unstable.git] / drivers / net / e1000 / e1000_osdep.h
blob33e7c45a4fe4831bf306d501b93ff12ce673b065
1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 /* glue for the OS independent part of e1000
31 * includes register access macros
34 #ifndef _E1000_OSDEP_H_
35 #define _E1000_OSDEP_H_
37 #include <asm/io.h>
39 #define CONFIG_RAM_BASE 0x60000
40 #define GBE_CONFIG_OFFSET 0x0
42 #define GBE_CONFIG_RAM_BASE \
43 ((unsigned int)(CONFIG_RAM_BASE + GBE_CONFIG_OFFSET))
45 #define GBE_CONFIG_BASE_VIRT \
46 ((void __iomem *)phys_to_virt(GBE_CONFIG_RAM_BASE))
48 #define GBE_CONFIG_FLASH_WRITE(base, offset, count, data) \
49 (iowrite16_rep(base + offset, data, count))
51 #define GBE_CONFIG_FLASH_READ(base, offset, count, data) \
52 (ioread16_rep(base + (offset << 1), data, count))
54 #define er32(reg) \
55 (readl(hw->hw_addr + ((hw->mac_type >= e1000_82543) \
56 ? E1000_##reg : E1000_82542_##reg)))
58 #define ew32(reg, value) \
59 (writel((value), (hw->hw_addr + ((hw->mac_type >= e1000_82543) \
60 ? E1000_##reg : E1000_82542_##reg))))
62 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \
63 writel((value), ((a)->hw_addr + \
64 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
65 ((offset) << 2))))
67 #define E1000_READ_REG_ARRAY(a, reg, offset) ( \
68 readl((a)->hw_addr + \
69 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
70 ((offset) << 2)))
72 #define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY
73 #define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY
75 #define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) ( \
76 writew((value), ((a)->hw_addr + \
77 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
78 ((offset) << 1))))
80 #define E1000_READ_REG_ARRAY_WORD(a, reg, offset) ( \
81 readw((a)->hw_addr + \
82 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
83 ((offset) << 1)))
85 #define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) ( \
86 writeb((value), ((a)->hw_addr + \
87 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
88 (offset))))
90 #define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) ( \
91 readb((a)->hw_addr + \
92 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
93 (offset)))
95 #define E1000_WRITE_FLUSH() er32(STATUS)
97 #define E1000_WRITE_ICH_FLASH_REG(a, reg, value) ( \
98 writel((value), ((a)->flash_address + reg)))
100 #define E1000_READ_ICH_FLASH_REG(a, reg) ( \
101 readl((a)->flash_address + reg))
103 #define E1000_WRITE_ICH_FLASH_REG16(a, reg, value) ( \
104 writew((value), ((a)->flash_address + reg)))
106 #define E1000_READ_ICH_FLASH_REG16(a, reg) ( \
107 readw((a)->flash_address + reg))
109 #endif /* _E1000_OSDEP_H_ */