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rtl8xxxu: Handle 8723bu style rx descriptors
[linux-2.6/btrfs-unstable.git] / drivers / net / wireless / realtek / rtl8xxxu / rtl8xxxu.c
blob8e6d54f18119d5eeab14b2687ab9d4d8ee731c9f
1 /*
2 * RTL8XXXU mac80211 USB driver
3 *
4 * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com>
5 *
6 * Portions, notably calibration code:
7 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
8 *
9 * This driver was written as a replacement for the vendor provided
10 * rtl8723au driver. As the Realtek 8xxx chips are very similar in
11 * their programming interface, I have started adding support for
12 * additional 8xxx chips like the 8192cu, 8188cus, etc.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of version 2 of the GNU General Public License as
16 * published by the Free Software Foundation.
17 *
18 * This program is distributed in the hope that it will be useful, but WITHOUT
19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * more details.
22 */
23
24 #include <linux/init.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
27 #include <linux/errno.h>
28 #include <linux/slab.h>
29 #include <linux/module.h>
30 #include <linux/spinlock.h>
31 #include <linux/list.h>
32 #include <linux/usb.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/wireless.h>
37 #include <linux/firmware.h>
38 #include <linux/moduleparam.h>
39 #include <net/mac80211.h>
40 #include "rtl8xxxu.h"
41 #include "rtl8xxxu_regs.h"
42
43 #define DRIVER_NAME "rtl8xxxu"
44
45 static int rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
46 static bool rtl8xxxu_ht40_2g;
47
48 MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@redhat.com>");
49 MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
50 MODULE_LICENSE("GPL");
51 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");
52 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");
53 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");
54 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");
55 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");
56 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
57 MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin");
58 MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin");
59 MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin");
60
61 module_param_named(debug, rtl8xxxu_debug, int, 0600);
62 MODULE_PARM_DESC(debug, "Set debug mask");
63 module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
64 MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
65
66 #define USB_VENDOR_ID_REALTEK 0x0bda
67 /* Minimum IEEE80211_MAX_FRAME_LEN */
68 #define RTL_RX_BUFFER_SIZE IEEE80211_MAX_FRAME_LEN
69 #define RTL8XXXU_RX_URBS 32
70 #define RTL8XXXU_RX_URB_PENDING_WATER 8
71 #define RTL8XXXU_TX_URBS 64
72 #define RTL8XXXU_TX_URB_LOW_WATER 25
73 #define RTL8XXXU_TX_URB_HIGH_WATER 32
74
75 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
76 struct rtl8xxxu_rx_urb *rx_urb);
77
78 static struct ieee80211_rate rtl8xxxu_rates[] = {
79 { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },
80 { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },
81 { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },
82 { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },
83 { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },
84 { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },
85 { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },
86 { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },
87 { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },
88 { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },
89 { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },
90 { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },
91 };
92
93 static struct ieee80211_channel rtl8xxxu_channels_2g[] = {
94 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2412,
95 .hw_value = 1, .max_power = 30 },
96 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2417,
97 .hw_value = 2, .max_power = 30 },
98 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2422,
99 .hw_value = 3, .max_power = 30 },
100 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2427,
101 .hw_value = 4, .max_power = 30 },
102 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2432,
103 .hw_value = 5, .max_power = 30 },
104 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2437,
105 .hw_value = 6, .max_power = 30 },
106 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2442,
107 .hw_value = 7, .max_power = 30 },
108 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2447,
109 .hw_value = 8, .max_power = 30 },
110 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2452,
111 .hw_value = 9, .max_power = 30 },
112 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2457,
113 .hw_value = 10, .max_power = 30 },
114 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2462,
115 .hw_value = 11, .max_power = 30 },
116 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2467,
117 .hw_value = 12, .max_power = 30 },
118 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2472,
119 .hw_value = 13, .max_power = 30 },
120 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2484,
121 .hw_value = 14, .max_power = 30 }
122 };
123
124 static struct ieee80211_supported_band rtl8xxxu_supported_band = {
125 .channels = rtl8xxxu_channels_2g,
126 .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),
127 .bitrates = rtl8xxxu_rates,
128 .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
129 };
130
131 static struct rtl8xxxu_reg8val rtl8723a_mac_init_table[] = {
132 {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
133 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
134 {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
135 {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
136 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
137 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
138 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
139 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
140 {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
141 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
142 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
143 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
144 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
145 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
146 {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
147 {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
148 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
149 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
150 {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
151 {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
152 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
153 {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
154 };
155
156 static struct rtl8xxxu_reg8val rtl8723b_mac_init_table[] = {
157 {0x02f, 0x30}, {0x035, 0x00}, {0x039, 0x08}, {0x04e, 0xe0},
158 {0x064, 0x00}, {0x067, 0x20}, {0x428, 0x0a}, {0x429, 0x10},
159 {0x430, 0x00}, {0x431, 0x00},
160 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
161 {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
162 {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
163 {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
164 {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
165 {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
166 {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
167 {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},
168 {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
169 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
170 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
171 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
172 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
173 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
174 {0x516, 0x0a}, {0x525, 0x4f},
175 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50},
176 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
177 {0x620, 0xff}, {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff},
178 {0x624, 0xff}, {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff},
179 {0x638, 0x50}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
180 {0x63f, 0x0e}, {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00},
181 {0x652, 0xc8}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
182 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
183 {0x70a, 0x65}, {0x70b, 0x87}, {0x765, 0x18}, {0x76e, 0x04},
184 {0xffff, 0xff},
185 };
186
187 static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
188 {0x800, 0x80040000}, {0x804, 0x00000003},
189 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
190 {0x810, 0x10001331}, {0x814, 0x020c3d10},
191 {0x818, 0x02200385}, {0x81c, 0x00000000},
192 {0x820, 0x01000100}, {0x824, 0x00390004},
193 {0x828, 0x00000000}, {0x82c, 0x00000000},
194 {0x830, 0x00000000}, {0x834, 0x00000000},
195 {0x838, 0x00000000}, {0x83c, 0x00000000},
196 {0x840, 0x00010000}, {0x844, 0x00000000},
197 {0x848, 0x00000000}, {0x84c, 0x00000000},
198 {0x850, 0x00000000}, {0x854, 0x00000000},
199 {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
200 {0x860, 0x66f60110}, {0x864, 0x061f0130},
201 {0x868, 0x00000000}, {0x86c, 0x32323200},
202 {0x870, 0x07000760}, {0x874, 0x22004000},
203 {0x878, 0x00000808}, {0x87c, 0x00000000},
204 {0x880, 0xc0083070}, {0x884, 0x000004d5},
205 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
206 {0x890, 0x00000800}, {0x894, 0xfffffffe},
207 {0x898, 0x40302010}, {0x89c, 0x00706050},
208 {0x900, 0x00000000}, {0x904, 0x00000023},
209 {0x908, 0x00000000}, {0x90c, 0x81121111},
210 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
211 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
212 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
213 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
214 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
215 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
216 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
217 {0xa78, 0x00000900},
218 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
219 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
220 {0xc10, 0x08800000}, {0xc14, 0x40000100},
221 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
222 {0xc20, 0x00000000}, {0xc24, 0x00000000},
223 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
224 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
225 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
226 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
227 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
228 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
229 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
230 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
231 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
232 {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
233 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
234 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
235 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
236 {0xc90, 0x00121820}, {0xc94, 0x00000000},
237 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
238 {0xca0, 0x00000000}, {0xca4, 0x00000080},
239 {0xca8, 0x00000000}, {0xcac, 0x00000000},
240 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
241 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
242 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
243 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
244 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
245 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
246 {0xce0, 0x00222222}, {0xce4, 0x00000000},
247 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
248 {0xd00, 0x00080740}, {0xd04, 0x00020401},
249 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
250 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
251 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
252 {0xd30, 0x00000000}, {0xd34, 0x80608000},
253 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
254 {0xd40, 0x00000000}, {0xd44, 0x00000000},
255 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
256 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
257 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
258 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
259 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
260 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
261 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
262 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
263 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
264 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
265 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
266 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
267 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
268 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
269 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
270 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
271 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
272 {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
273 {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
274 {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
275 {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
276 {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
277 {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
278 {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
279 {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
280 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
281 {0xf00, 0x00000300},
282 {0xffff, 0xffffffff},
283 };
284
285 static struct rtl8xxxu_reg32val rtl8723b_phy_1t_init_table[] = {
286 {0x800, 0x80040000}, {0x804, 0x00000003},
287 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
288 {0x810, 0x10001331}, {0x814, 0x020c3d10},
289 {0x818, 0x02200385}, {0x81c, 0x00000000},
290 {0x820, 0x01000100}, {0x824, 0x00190204},
291 {0x828, 0x00000000}, {0x82c, 0x00000000},
292 {0x830, 0x00000000}, {0x834, 0x00000000},
293 {0x838, 0x00000000}, {0x83c, 0x00000000},
294 {0x840, 0x00010000}, {0x844, 0x00000000},
295 {0x848, 0x00000000}, {0x84c, 0x00000000},
296 {0x850, 0x00000000}, {0x854, 0x00000000},
297 {0x858, 0x569a11a9}, {0x85c, 0x01000014},
298 {0x860, 0x66f60110}, {0x864, 0x061f0649},
299 {0x868, 0x00000000}, {0x86c, 0x27272700},
300 {0x870, 0x07000760}, {0x874, 0x25004000},
301 {0x878, 0x00000808}, {0x87c, 0x00000000},
302 {0x880, 0xb0000c1c}, {0x884, 0x00000001},
303 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
304 {0x890, 0x00000800}, {0x894, 0xfffffffe},
305 {0x898, 0x40302010}, {0x89c, 0x00706050},
306 {0x900, 0x00000000}, {0x904, 0x00000023},
307 {0x908, 0x00000000}, {0x90c, 0x81121111},
308 {0x910, 0x00000002}, {0x914, 0x00000201},
309 {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c},
310 {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f},
311 {0xa10, 0x9500bb78}, {0xa14, 0x1114d028},
312 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
313 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
314 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
315 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
316 {0xa78, 0x00000900}, {0xa7c, 0x225b0606},
317 {0xa80, 0x21806490}, {0xb2c, 0x00000000},
318 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
319 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
320 {0xc10, 0x08800000}, {0xc14, 0x40000100},
321 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
322 {0xc20, 0x00000000}, {0xc24, 0x00000000},
323 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
324 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
325 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
326 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
327 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
328 {0xc50, 0x69553420}, {0xc54, 0x43bc0094},
329 {0xc58, 0x00013149}, {0xc5c, 0x00250492},
330 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
331 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
332 {0xc70, 0x2c7f000d}, {0xc74, 0x020610db},
333 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
334 {0xc80, 0x390000e4}, {0xc84, 0x20f60000},
335 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
336 {0xc90, 0x00020e1a}, {0xc94, 0x00000000},
337 {0xc98, 0x00020e1a}, {0xc9c, 0x00007f7f},
338 {0xca0, 0x00000000}, {0xca4, 0x000300a0},
339 {0xca8, 0x00000000}, {0xcac, 0x00000000},
340 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
341 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
342 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
343 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
344 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
345 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
346 {0xce0, 0x00222222}, {0xce4, 0x00000000},
347 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
348 {0xd00, 0x00000740}, {0xd04, 0x40020401},
349 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
350 {0xd10, 0xa0633333}, {0xd14, 0x3333bc53},
351 {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975},
352 {0xd30, 0x00000000}, {0xd34, 0x80608000},
353 {0xd38, 0x00000000}, {0xd3c, 0x00127353},
354 {0xd40, 0x00000000}, {0xd44, 0x00000000},
355 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
356 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
357 {0xd58, 0x00000282}, {0xd5c, 0x30032064},
358 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
359 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
360 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
361 {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d},
362 {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d},
363 {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d},
364 {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d},
365 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
366 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
367 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
368 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
369 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
370 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
371 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
372 {0xe68, 0x001b2556}, {0xe6c, 0x00c00096},
373 {0xe70, 0x00c00096}, {0xe74, 0x01000056},
374 {0xe78, 0x01000014}, {0xe7c, 0x01000056},
375 {0xe80, 0x01000014}, {0xe84, 0x00c00096},
376 {0xe88, 0x01000056}, {0xe8c, 0x00c00096},
377 {0xed0, 0x00c00096}, {0xed4, 0x00c00096},
378 {0xed8, 0x00c00096}, {0xedc, 0x000000d6},
379 {0xee0, 0x000000d6}, {0xeec, 0x01c00016},
380 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
381 {0xf00, 0x00000300},
382 {0x820, 0x01000100}, {0x800, 0x83040000},
383 {0xffff, 0xffffffff},
384 };
385
386 static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
387 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
388 {0x800, 0x80040002}, {0x804, 0x00000003},
389 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
390 {0x810, 0x10000330}, {0x814, 0x020c3d10},
391 {0x818, 0x02200385}, {0x81c, 0x00000000},
392 {0x820, 0x01000100}, {0x824, 0x00390004},
393 {0x828, 0x01000100}, {0x82c, 0x00390004},
394 {0x830, 0x27272727}, {0x834, 0x27272727},
395 {0x838, 0x27272727}, {0x83c, 0x27272727},
396 {0x840, 0x00010000}, {0x844, 0x00010000},
397 {0x848, 0x27272727}, {0x84c, 0x27272727},
398 {0x850, 0x00000000}, {0x854, 0x00000000},
399 {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
400 {0x860, 0x66e60230}, {0x864, 0x061f0130},
401 {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
402 {0x870, 0x07000700}, {0x874, 0x22184000},
403 {0x878, 0x08080808}, {0x87c, 0x00000000},
404 {0x880, 0xc0083070}, {0x884, 0x000004d5},
405 {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
406 {0x890, 0x00000800}, {0x894, 0xfffffffe},
407 {0x898, 0x40302010}, {0x89c, 0x00706050},
408 {0x900, 0x00000000}, {0x904, 0x00000023},
409 {0x908, 0x00000000}, {0x90c, 0x81121313},
410 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
411 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
412 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
413 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
414 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
415 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
416 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
417 {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
418 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
419 {0xc10, 0x08800000}, {0xc14, 0x40000100},
420 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
421 {0xc20, 0x00000000}, {0xc24, 0x00000000},
422 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
423 {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
424 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
425 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
426 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
427 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
428 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
429 {0xc60, 0x00000000}, {0xc64, 0x5116848b},
430 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
431 {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
432 {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
433 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
434 {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
435 {0xc90, 0x00121820}, {0xc94, 0x00000000},
436 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
437 {0xca0, 0x00000000}, {0xca4, 0x00000080},
438 {0xca8, 0x00000000}, {0xcac, 0x00000000},
439 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
440 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
441 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
442 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
443 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
444 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
445 {0xce0, 0x00222222}, {0xce4, 0x00000000},
446 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
447 {0xd00, 0x00080740}, {0xd04, 0x00020403},
448 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
449 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
450 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
451 {0xd30, 0x00000000}, {0xd34, 0x80608000},
452 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
453 {0xd40, 0x00000000}, {0xd44, 0x00000000},
454 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
455 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
456 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
457 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
458 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
459 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
460 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
461 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
462 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
463 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
464 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
465 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
466 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
467 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
468 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
469 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
470 {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
471 {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
472 {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
473 {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
474 {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
475 {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
476 {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
477 {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
478 {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
479 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
480 {0xf00, 0x00000300},
481 {0xffff, 0xffffffff},
482 };
483
484 static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
485 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
486 {0x040, 0x000c0004}, {0x800, 0x80040000},
487 {0x804, 0x00000001}, {0x808, 0x0000fc00},
488 {0x80c, 0x0000000a}, {0x810, 0x10005388},
489 {0x814, 0x020c3d10}, {0x818, 0x02200385},
490 {0x81c, 0x00000000}, {0x820, 0x01000100},
491 {0x824, 0x00390204}, {0x828, 0x00000000},
492 {0x82c, 0x00000000}, {0x830, 0x00000000},
493 {0x834, 0x00000000}, {0x838, 0x00000000},
494 {0x83c, 0x00000000}, {0x840, 0x00010000},
495 {0x844, 0x00000000}, {0x848, 0x00000000},
496 {0x84c, 0x00000000}, {0x850, 0x00000000},
497 {0x854, 0x00000000}, {0x858, 0x569a569a},
498 {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
499 {0x864, 0x061f0130}, {0x868, 0x00000000},
500 {0x86c, 0x20202000}, {0x870, 0x03000300},
501 {0x874, 0x22004000}, {0x878, 0x00000808},
502 {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
503 {0x884, 0x000004d5}, {0x888, 0x00000000},
504 {0x88c, 0xccc000c0}, {0x890, 0x00000800},
505 {0x894, 0xfffffffe}, {0x898, 0x40302010},
506 {0x89c, 0x00706050}, {0x900, 0x00000000},
507 {0x904, 0x00000023}, {0x908, 0x00000000},
508 {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
509 {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
510 {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
511 {0xa14, 0x11144028}, {0xa18, 0x00881117},
512 {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
513 {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
514 {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
515 {0xa74, 0x00000007}, {0xc00, 0x48071d40},
516 {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
517 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
518 {0xc14, 0x40000100}, {0xc18, 0x08800000},
519 {0xc1c, 0x40000100}, {0xc20, 0x00000000},
520 {0xc24, 0x00000000}, {0xc28, 0x00000000},
521 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
522 {0xc34, 0x469652cf}, {0xc38, 0x49795994},
523 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
524 {0xc44, 0x000100b7}, {0xc48, 0xec020107},
525 {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
526 {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
527 {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
528 {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
529 {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
530 {0xc74, 0x018610db}, {0xc78, 0x0000001f},
531 {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
532 {0xc84, 0x20f60000}, {0xc88, 0x24000090},
533 {0xc8c, 0x20200000}, {0xc90, 0x00121820},
534 {0xc94, 0x00000000}, {0xc98, 0x00121820},
535 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
536 {0xca4, 0x00000080}, {0xca8, 0x00000000},
537 {0xcac, 0x00000000}, {0xcb0, 0x00000000},
538 {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
539 {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
540 {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
541 {0xccc, 0x00000000}, {0xcd0, 0x00000000},
542 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
543 {0xcdc, 0x00766932}, {0xce0, 0x00222222},
544 {0xce4, 0x00000000}, {0xce8, 0x37644302},
545 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
546 {0xd04, 0x00020401}, {0xd08, 0x0000907f},
547 {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
548 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
549 {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
550 {0xd34, 0x80608000}, {0xd38, 0x00000000},
551 {0xd3c, 0x00027293}, {0xd40, 0x00000000},
552 {0xd44, 0x00000000}, {0xd48, 0x00000000},
553 {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
554 {0xd54, 0x00000000}, {0xd58, 0x00000000},
555 {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
556 {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
557 {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
558 {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
559 {0xe00, 0x24242424}, {0xe04, 0x24242424},
560 {0xe08, 0x03902024}, {0xe10, 0x24242424},
561 {0xe14, 0x24242424}, {0xe18, 0x24242424},
562 {0xe1c, 0x24242424}, {0xe28, 0x00000000},
563 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
564 {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
565 {0xe40, 0x01007c00}, {0xe44, 0x01004800},
566 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
567 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
568 {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
569 {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
570 {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
571 {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
572 {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
573 {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
574 {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
575 {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
576 {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
577 {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
578 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
579 {0xf00, 0x00000300},
580 {0xffff, 0xffffffff},
581 };
582
583 static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
584 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
585 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
586 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
587 {0xc78, 0x7a060001}, {0xc78, 0x79070001},
588 {0xc78, 0x78080001}, {0xc78, 0x77090001},
589 {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
590 {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
591 {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
592 {0xc78, 0x70100001}, {0xc78, 0x6f110001},
593 {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
594 {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
595 {0xc78, 0x6a160001}, {0xc78, 0x69170001},
596 {0xc78, 0x68180001}, {0xc78, 0x67190001},
597 {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
598 {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
599 {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
600 {0xc78, 0x60200001}, {0xc78, 0x49210001},
601 {0xc78, 0x48220001}, {0xc78, 0x47230001},
602 {0xc78, 0x46240001}, {0xc78, 0x45250001},
603 {0xc78, 0x44260001}, {0xc78, 0x43270001},
604 {0xc78, 0x42280001}, {0xc78, 0x41290001},
605 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
606 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
607 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
608 {0xc78, 0x21300001}, {0xc78, 0x20310001},
609 {0xc78, 0x06320001}, {0xc78, 0x05330001},
610 {0xc78, 0x04340001}, {0xc78, 0x03350001},
611 {0xc78, 0x02360001}, {0xc78, 0x01370001},
612 {0xc78, 0x00380001}, {0xc78, 0x00390001},
613 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
614 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
615 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
616 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
617 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
618 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
619 {0xc78, 0x7a460001}, {0xc78, 0x79470001},
620 {0xc78, 0x78480001}, {0xc78, 0x77490001},
621 {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
622 {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
623 {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
624 {0xc78, 0x70500001}, {0xc78, 0x6f510001},
625 {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
626 {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
627 {0xc78, 0x6a560001}, {0xc78, 0x69570001},
628 {0xc78, 0x68580001}, {0xc78, 0x67590001},
629 {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
630 {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
631 {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
632 {0xc78, 0x60600001}, {0xc78, 0x49610001},
633 {0xc78, 0x48620001}, {0xc78, 0x47630001},
634 {0xc78, 0x46640001}, {0xc78, 0x45650001},
635 {0xc78, 0x44660001}, {0xc78, 0x43670001},
636 {0xc78, 0x42680001}, {0xc78, 0x41690001},
637 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
638 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
639 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
640 {0xc78, 0x21700001}, {0xc78, 0x20710001},
641 {0xc78, 0x06720001}, {0xc78, 0x05730001},
642 {0xc78, 0x04740001}, {0xc78, 0x03750001},
643 {0xc78, 0x02760001}, {0xc78, 0x01770001},
644 {0xc78, 0x00780001}, {0xc78, 0x00790001},
645 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
646 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
647 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
648 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
649 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
650 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
651 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
652 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
653 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
654 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
655 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
656 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
657 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
658 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
659 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
660 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
661 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
662 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
663 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
664 {0xffff, 0xffffffff}
665 };
666
667 static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
668 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
669 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
670 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
671 {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
672 {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
673 {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
674 {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
675 {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
676 {0xc78, 0x73100001}, {0xc78, 0x72110001},
677 {0xc78, 0x71120001}, {0xc78, 0x70130001},
678 {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
679 {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
680 {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
681 {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
682 {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
683 {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
684 {0xc78, 0x63200001}, {0xc78, 0x62210001},
685 {0xc78, 0x61220001}, {0xc78, 0x60230001},
686 {0xc78, 0x46240001}, {0xc78, 0x45250001},
687 {0xc78, 0x44260001}, {0xc78, 0x43270001},
688 {0xc78, 0x42280001}, {0xc78, 0x41290001},
689 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
690 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
691 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
692 {0xc78, 0x21300001}, {0xc78, 0x20310001},
693 {0xc78, 0x06320001}, {0xc78, 0x05330001},
694 {0xc78, 0x04340001}, {0xc78, 0x03350001},
695 {0xc78, 0x02360001}, {0xc78, 0x01370001},
696 {0xc78, 0x00380001}, {0xc78, 0x00390001},
697 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
698 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
699 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
700 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
701 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
702 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
703 {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
704 {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
705 {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
706 {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
707 {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
708 {0xc78, 0x73500001}, {0xc78, 0x72510001},
709 {0xc78, 0x71520001}, {0xc78, 0x70530001},
710 {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
711 {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
712 {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
713 {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
714 {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
715 {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
716 {0xc78, 0x63600001}, {0xc78, 0x62610001},
717 {0xc78, 0x61620001}, {0xc78, 0x60630001},
718 {0xc78, 0x46640001}, {0xc78, 0x45650001},
719 {0xc78, 0x44660001}, {0xc78, 0x43670001},
720 {0xc78, 0x42680001}, {0xc78, 0x41690001},
721 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
722 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
723 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
724 {0xc78, 0x21700001}, {0xc78, 0x20710001},
725 {0xc78, 0x06720001}, {0xc78, 0x05730001},
726 {0xc78, 0x04740001}, {0xc78, 0x03750001},
727 {0xc78, 0x02760001}, {0xc78, 0x01770001},
728 {0xc78, 0x00780001}, {0xc78, 0x00790001},
729 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
730 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
731 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
732 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
733 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
734 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
735 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
736 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
737 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
738 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
739 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
740 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
741 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
742 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
743 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
744 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
745 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
746 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
747 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
748 {0xffff, 0xffffffff}
749 };
750
751 static struct rtl8xxxu_reg32val rtl8xxx_agc_8723bu_table[] = {
752 {0xc78, 0xfd000001}, {0xc78, 0xfc010001},
753 {0xc78, 0xfb020001}, {0xc78, 0xfa030001},
754 {0xc78, 0xf9040001}, {0xc78, 0xf8050001},
755 {0xc78, 0xf7060001}, {0xc78, 0xf6070001},
756 {0xc78, 0xf5080001}, {0xc78, 0xf4090001},
757 {0xc78, 0xf30a0001}, {0xc78, 0xf20b0001},
758 {0xc78, 0xf10c0001}, {0xc78, 0xf00d0001},
759 {0xc78, 0xef0e0001}, {0xc78, 0xee0f0001},
760 {0xc78, 0xed100001}, {0xc78, 0xec110001},
761 {0xc78, 0xeb120001}, {0xc78, 0xea130001},
762 {0xc78, 0xe9140001}, {0xc78, 0xe8150001},
763 {0xc78, 0xe7160001}, {0xc78, 0xe6170001},
764 {0xc78, 0xe5180001}, {0xc78, 0xe4190001},
765 {0xc78, 0xe31a0001}, {0xc78, 0xa51b0001},
766 {0xc78, 0xa41c0001}, {0xc78, 0xa31d0001},
767 {0xc78, 0x671e0001}, {0xc78, 0x661f0001},
768 {0xc78, 0x65200001}, {0xc78, 0x64210001},
769 {0xc78, 0x63220001}, {0xc78, 0x4a230001},
770 {0xc78, 0x49240001}, {0xc78, 0x48250001},
771 {0xc78, 0x47260001}, {0xc78, 0x46270001},
772 {0xc78, 0x45280001}, {0xc78, 0x44290001},
773 {0xc78, 0x432a0001}, {0xc78, 0x422b0001},
774 {0xc78, 0x292c0001}, {0xc78, 0x282d0001},
775 {0xc78, 0x272e0001}, {0xc78, 0x262f0001},
776 {0xc78, 0x0a300001}, {0xc78, 0x09310001},
777 {0xc78, 0x08320001}, {0xc78, 0x07330001},
778 {0xc78, 0x06340001}, {0xc78, 0x05350001},
779 {0xc78, 0x04360001}, {0xc78, 0x03370001},
780 {0xc78, 0x02380001}, {0xc78, 0x01390001},
781 {0xc78, 0x013a0001}, {0xc78, 0x013b0001},
782 {0xc78, 0x013c0001}, {0xc78, 0x013d0001},
783 {0xc78, 0x013e0001}, {0xc78, 0x013f0001},
784 {0xc78, 0xfc400001}, {0xc78, 0xfb410001},
785 {0xc78, 0xfa420001}, {0xc78, 0xf9430001},
786 {0xc78, 0xf8440001}, {0xc78, 0xf7450001},
787 {0xc78, 0xf6460001}, {0xc78, 0xf5470001},
788 {0xc78, 0xf4480001}, {0xc78, 0xf3490001},
789 {0xc78, 0xf24a0001}, {0xc78, 0xf14b0001},
790 {0xc78, 0xf04c0001}, {0xc78, 0xef4d0001},
791 {0xc78, 0xee4e0001}, {0xc78, 0xed4f0001},
792 {0xc78, 0xec500001}, {0xc78, 0xeb510001},
793 {0xc78, 0xea520001}, {0xc78, 0xe9530001},
794 {0xc78, 0xe8540001}, {0xc78, 0xe7550001},
795 {0xc78, 0xe6560001}, {0xc78, 0xe5570001},
796 {0xc78, 0xe4580001}, {0xc78, 0xe3590001},
797 {0xc78, 0xa65a0001}, {0xc78, 0xa55b0001},
798 {0xc78, 0xa45c0001}, {0xc78, 0xa35d0001},
799 {0xc78, 0x675e0001}, {0xc78, 0x665f0001},
800 {0xc78, 0x65600001}, {0xc78, 0x64610001},
801 {0xc78, 0x63620001}, {0xc78, 0x62630001},
802 {0xc78, 0x61640001}, {0xc78, 0x48650001},
803 {0xc78, 0x47660001}, {0xc78, 0x46670001},
804 {0xc78, 0x45680001}, {0xc78, 0x44690001},
805 {0xc78, 0x436a0001}, {0xc78, 0x426b0001},
806 {0xc78, 0x286c0001}, {0xc78, 0x276d0001},
807 {0xc78, 0x266e0001}, {0xc78, 0x256f0001},
808 {0xc78, 0x24700001}, {0xc78, 0x09710001},
809 {0xc78, 0x08720001}, {0xc78, 0x07730001},
810 {0xc78, 0x06740001}, {0xc78, 0x05750001},
811 {0xc78, 0x04760001}, {0xc78, 0x03770001},
812 {0xc78, 0x02780001}, {0xc78, 0x01790001},
813 {0xc78, 0x017a0001}, {0xc78, 0x017b0001},
814 {0xc78, 0x017c0001}, {0xc78, 0x017d0001},
815 {0xc78, 0x017e0001}, {0xc78, 0x017f0001},
816 {0xc50, 0x69553422},
817 {0xc50, 0x69553420},
818 {0x824, 0x00390204},
819 {0xffff, 0xffffffff}
820 };
821
822 static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = {
823 {0x00, 0x00030159}, {0x01, 0x00031284},
824 {0x02, 0x00098000}, {0x03, 0x00039c63},
825 {0x04, 0x000210e7}, {0x09, 0x0002044f},
826 {0x0a, 0x0001a3f1}, {0x0b, 0x00014787},
827 {0x0c, 0x000896fe}, {0x0d, 0x0000e02c},
828 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
829 {0x19, 0x00000000}, {0x1a, 0x00030355},
830 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
831 {0x1d, 0x000a1250}, {0x1e, 0x0000024f},
832 {0x1f, 0x00000000}, {0x20, 0x0000b614},
833 {0x21, 0x0006c000}, {0x22, 0x00000000},
834 {0x23, 0x00001558}, {0x24, 0x00000060},
835 {0x25, 0x00000483}, {0x26, 0x0004f000},
836 {0x27, 0x000ec7d9}, {0x28, 0x00057730},
837 {0x29, 0x00004783}, {0x2a, 0x00000001},
838 {0x2b, 0x00021334}, {0x2a, 0x00000000},
839 {0x2b, 0x00000054}, {0x2a, 0x00000001},
840 {0x2b, 0x00000808}, {0x2b, 0x00053333},
841 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
842 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
843 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
844 {0x2b, 0x00000808}, {0x2b, 0x00063333},
845 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
846 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
847 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
848 {0x2b, 0x00000808}, {0x2b, 0x00073333},
849 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
850 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
851 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
852 {0x2b, 0x00000709}, {0x2b, 0x00063333},
853 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
854 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
855 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
856 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
857 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
858 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
859 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
860 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
861 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
862 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
863 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
864 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
865 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
866 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
867 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
868 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
869 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
870 {0x10, 0x0002000f}, {0x11, 0x000203f9},
871 {0x10, 0x0003000f}, {0x11, 0x000ff500},
872 {0x10, 0x00000000}, {0x11, 0x00000000},
873 {0x10, 0x0008000f}, {0x11, 0x0003f100},
874 {0x10, 0x0009000f}, {0x11, 0x00023100},
875 {0x12, 0x00032000}, {0x12, 0x00071000},
876 {0x12, 0x000b0000}, {0x12, 0x000fc000},
877 {0x13, 0x000287b3}, {0x13, 0x000244b7},
878 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
879 {0x13, 0x00018493}, {0x13, 0x0001429b},
880 {0x13, 0x00010299}, {0x13, 0x0000c29c},
881 {0x13, 0x000081a0}, {0x13, 0x000040ac},
882 {0x13, 0x00000020}, {0x14, 0x0001944c},
883 {0x14, 0x00059444}, {0x14, 0x0009944c},
884 {0x14, 0x000d9444}, {0x15, 0x0000f474},
885 {0x15, 0x0004f477}, {0x15, 0x0008f455},
886 {0x15, 0x000cf455}, {0x16, 0x00000339},
887 {0x16, 0x00040339}, {0x16, 0x00080339},
888 {0x16, 0x000c0366}, {0x00, 0x00010159},
889 {0x18, 0x0000f401}, {0xfe, 0x00000000},
890 {0xfe, 0x00000000}, {0x1f, 0x00000003},
891 {0xfe, 0x00000000}, {0xfe, 0x00000000},
892 {0x1e, 0x00000247}, {0x1f, 0x00000000},
893 {0x00, 0x00030159},
894 {0xff, 0xffffffff}
895 };
896
897 static struct rtl8xxxu_rfregval rtl8723bu_radioa_1t_init_table[] = {
898 {0x00, 0x00010000}, {0xb0, 0x000dffe0},
899 {0xfe, 0x00000000}, {0xfe, 0x00000000},
900 {0xfe, 0x00000000}, {0xb1, 0x00000018},
901 {0xfe, 0x00000000}, {0xfe, 0x00000000},
902 {0xfe, 0x00000000}, {0xb2, 0x00084c00},
903 {0xb5, 0x0000d2cc}, {0xb6, 0x000925aa},
904 {0xb7, 0x00000010}, {0xb8, 0x0000907f},
905 {0x5c, 0x00000002}, {0x7c, 0x00000002},
906 {0x7e, 0x00000005}, {0x8b, 0x0006fc00},
907 {0xb0, 0x000ff9f0}, {0x1c, 0x000739d2},
908 {0x1e, 0x00000000}, {0xdf, 0x00000780},
909 {0x50, 0x00067435},
910 /*
911 * The 8723bu vendor driver indicates that bit 8 should be set in
912 * 0x51 for package types TFBGA90, TFBGA80, and TFBGA79. However
913 * they never actually check the package type - and just default
914 * to not setting it.
915 */
916 {0x51, 0x0006b04e},
917 {0x52, 0x000007d2}, {0x53, 0x00000000},
918 {0x54, 0x00050400}, {0x55, 0x0004026e},
919 {0xdd, 0x0000004c}, {0x70, 0x00067435},
920 /*
921 * 0x71 has same package type condition as for register 0x51
922 */
923 {0x71, 0x0006b04e},
924 {0x72, 0x000007d2}, {0x73, 0x00000000},
925 {0x74, 0x00050400}, {0x75, 0x0004026e},
926 {0xef, 0x00000100}, {0x34, 0x0000add7},
927 {0x35, 0x00005c00}, {0x34, 0x00009dd4},
928 {0x35, 0x00005000}, {0x34, 0x00008dd1},
929 {0x35, 0x00004400}, {0x34, 0x00007dce},
930 {0x35, 0x00003800}, {0x34, 0x00006cd1},
931 {0x35, 0x00004400}, {0x34, 0x00005cce},
932 {0x35, 0x00003800}, {0x34, 0x000048ce},
933 {0x35, 0x00004400}, {0x34, 0x000034ce},
934 {0x35, 0x00003800}, {0x34, 0x00002451},
935 {0x35, 0x00004400}, {0x34, 0x0000144e},
936 {0x35, 0x00003800}, {0x34, 0x00000051},
937 {0x35, 0x00004400}, {0xef, 0x00000000},
938 {0xef, 0x00000100}, {0xed, 0x00000010},
939 {0x44, 0x0000add7}, {0x44, 0x00009dd4},
940 {0x44, 0x00008dd1}, {0x44, 0x00007dce},
941 {0x44, 0x00006cc1}, {0x44, 0x00005cce},
942 {0x44, 0x000044d1}, {0x44, 0x000034ce},
943 {0x44, 0x00002451}, {0x44, 0x0000144e},
944 {0x44, 0x00000051}, {0xef, 0x00000000},
945 {0xed, 0x00000000}, {0x7f, 0x00020080},
946 {0xef, 0x00002000}, {0x3b, 0x000380ef},
947 {0x3b, 0x000302fe}, {0x3b, 0x00028ce6},
948 {0x3b, 0x000200bc}, {0x3b, 0x000188a5},
949 {0x3b, 0x00010fbc}, {0x3b, 0x00008f71},
950 {0x3b, 0x00000900}, {0xef, 0x00000000},
951 {0xed, 0x00000001}, {0x40, 0x000380ef},
952 {0x40, 0x000302fe}, {0x40, 0x00028ce6},
953 {0x40, 0x000200bc}, {0x40, 0x000188a5},
954 {0x40, 0x00010fbc}, {0x40, 0x00008f71},
955 {0x40, 0x00000900}, {0xed, 0x00000000},
956 {0x82, 0x00080000}, {0x83, 0x00008000},
957 {0x84, 0x00048d80}, {0x85, 0x00068000},
958 {0xa2, 0x00080000}, {0xa3, 0x00008000},
959 {0xa4, 0x00048d80}, {0xa5, 0x00068000},
960 {0xed, 0x00000002}, {0xef, 0x00000002},
961 {0x56, 0x00000032}, {0x76, 0x00000032},
962 {0x01, 0x00000780},
963 {0xff, 0xffffffff}
964 };
965
966 static struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = {
967 {0x00, 0x00030159}, {0x01, 0x00031284},
968 {0x02, 0x00098000}, {0x03, 0x00018c63},
969 {0x04, 0x000210e7}, {0x09, 0x0002044f},
970 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
971 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
972 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
973 {0x19, 0x00000000}, {0x1a, 0x00010255},
974 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
975 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
976 {0x1f, 0x00080001}, {0x20, 0x0000b614},
977 {0x21, 0x0006c000}, {0x22, 0x00000000},
978 {0x23, 0x00001558}, {0x24, 0x00000060},
979 {0x25, 0x00000483}, {0x26, 0x0004f000},
980 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
981 {0x29, 0x00004783}, {0x2a, 0x00000001},
982 {0x2b, 0x00021334}, {0x2a, 0x00000000},
983 {0x2b, 0x00000054}, {0x2a, 0x00000001},
984 {0x2b, 0x00000808}, {0x2b, 0x00053333},
985 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
986 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
987 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
988 {0x2b, 0x00000808}, {0x2b, 0x00063333},
989 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
990 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
991 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
992 {0x2b, 0x00000808}, {0x2b, 0x00073333},
993 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
994 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
995 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
996 {0x2b, 0x00000709}, {0x2b, 0x00063333},
997 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
998 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
999 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1000 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1001 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1002 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1003 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1004 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1005 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1006 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1007 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1008 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1009 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1010 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1011 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1012 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1013 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1014 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1015 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1016 {0x10, 0x00000000}, {0x11, 0x00000000},
1017 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1018 {0x10, 0x0009000f}, {0x11, 0x00023100},
1019 {0x12, 0x00032000}, {0x12, 0x00071000},
1020 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1021 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1022 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1023 {0x13, 0x00018493}, {0x13, 0x0001429b},
1024 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1025 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1026 {0x13, 0x00000020}, {0x14, 0x0001944c},
1027 {0x14, 0x00059444}, {0x14, 0x0009944c},
1028 {0x14, 0x000d9444}, {0x15, 0x0000f424},
1029 {0x15, 0x0004f424}, {0x15, 0x0008f424},
1030 {0x15, 0x000cf424}, {0x16, 0x000e0330},
1031 {0x16, 0x000a0330}, {0x16, 0x00060330},
1032 {0x16, 0x00020330}, {0x00, 0x00010159},
1033 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1034 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1035 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1036 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1037 {0x00, 0x00030159},
1038 {0xff, 0xffffffff}
1039 };
1040
1041 static struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = {
1042 {0x00, 0x00030159}, {0x01, 0x00031284},
1043 {0x02, 0x00098000}, {0x03, 0x00018c63},
1044 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1045 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1046 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1047 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1048 {0x12, 0x00032000}, {0x12, 0x00071000},
1049 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1050 {0x13, 0x000287af}, {0x13, 0x000244b7},
1051 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1052 {0x13, 0x00018493}, {0x13, 0x00014297},
1053 {0x13, 0x00010295}, {0x13, 0x0000c298},
1054 {0x13, 0x0000819c}, {0x13, 0x000040a8},
1055 {0x13, 0x0000001c}, {0x14, 0x0001944c},
1056 {0x14, 0x00059444}, {0x14, 0x0009944c},
1057 {0x14, 0x000d9444}, {0x15, 0x0000f424},
1058 {0x15, 0x0004f424}, {0x15, 0x0008f424},
1059 {0x15, 0x000cf424}, {0x16, 0x000e0330},
1060 {0x16, 0x000a0330}, {0x16, 0x00060330},
1061 {0x16, 0x00020330},
1062 {0xff, 0xffffffff}
1063 };
1064
1065 static struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = {
1066 {0x00, 0x00030159}, {0x01, 0x00031284},
1067 {0x02, 0x00098000}, {0x03, 0x00018c63},
1068 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1069 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1070 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1071 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1072 {0x19, 0x00000000}, {0x1a, 0x00010255},
1073 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1074 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1075 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1076 {0x21, 0x0006c000}, {0x22, 0x00000000},
1077 {0x23, 0x00001558}, {0x24, 0x00000060},
1078 {0x25, 0x00000483}, {0x26, 0x0004f000},
1079 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
1080 {0x29, 0x00004783}, {0x2a, 0x00000001},
1081 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1082 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1083 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1084 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1085 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1086 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1087 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1088 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1089 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1090 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1091 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1092 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1093 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1094 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1095 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1096 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1097 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1098 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1099 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1100 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1101 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1102 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1103 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1104 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1105 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1106 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1107 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1108 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1109 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1110 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1111 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1112 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1113 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1114 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1115 {0x10, 0x00000000}, {0x11, 0x00000000},
1116 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1117 {0x10, 0x0009000f}, {0x11, 0x00023100},
1118 {0x12, 0x00032000}, {0x12, 0x00071000},
1119 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1120 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1121 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1122 {0x13, 0x00018493}, {0x13, 0x0001429b},
1123 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1124 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1125 {0x13, 0x00000020}, {0x14, 0x0001944c},
1126 {0x14, 0x00059444}, {0x14, 0x0009944c},
1127 {0x14, 0x000d9444}, {0x15, 0x0000f405},
1128 {0x15, 0x0004f405}, {0x15, 0x0008f405},
1129 {0x15, 0x000cf405}, {0x16, 0x000e0330},
1130 {0x16, 0x000a0330}, {0x16, 0x00060330},
1131 {0x16, 0x00020330}, {0x00, 0x00010159},
1132 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1133 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1134 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1135 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1136 {0x00, 0x00030159},
1137 {0xff, 0xffffffff}
1138 };
1139
1140 static struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table[] = {
1141 {0x00, 0x00030159}, {0x01, 0x00031284},
1142 {0x02, 0x00098000}, {0x03, 0x00018c63},
1143 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1144 {0x0a, 0x0001adb0}, {0x0b, 0x00054867},
1145 {0x0c, 0x0008992e}, {0x0d, 0x0000e529},
1146 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1147 {0x19, 0x00000000}, {0x1a, 0x00000255},
1148 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1149 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1150 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1151 {0x21, 0x0006c000}, {0x22, 0x0000083c},
1152 {0x23, 0x00001558}, {0x24, 0x00000060},
1153 {0x25, 0x00000483}, {0x26, 0x0004f000},
1154 {0x27, 0x000ec7d9}, {0x28, 0x000977c0},
1155 {0x29, 0x00004783}, {0x2a, 0x00000001},
1156 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1157 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1158 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1159 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1160 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1161 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1162 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1163 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1164 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1165 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1166 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1167 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1168 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1169 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1170 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1171 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1172 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1173 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1174 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1175 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1176 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1177 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1178 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1179 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1180 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1181 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1182 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1183 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1184 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1185 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1186 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1187 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1188 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1189 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1190 {0x10, 0x00000000}, {0x11, 0x00000000},
1191 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1192 {0x10, 0x0009000f}, {0x11, 0x00023100},
1193 {0x12, 0x000d8000}, {0x12, 0x00090000},
1194 {0x12, 0x00051000}, {0x12, 0x00012000},
1195 {0x13, 0x00028fb4}, {0x13, 0x00024fa8},
1196 {0x13, 0x000207a4}, {0x13, 0x0001c3b0},
1197 {0x13, 0x000183a4}, {0x13, 0x00014398},
1198 {0x13, 0x000101a4}, {0x13, 0x0000c198},
1199 {0x13, 0x000080a4}, {0x13, 0x00004098},
1200 {0x13, 0x00000000}, {0x14, 0x0001944c},
1201 {0x14, 0x00059444}, {0x14, 0x0009944c},
1202 {0x14, 0x000d9444}, {0x15, 0x0000f405},
1203 {0x15, 0x0004f405}, {0x15, 0x0008f405},
1204 {0x15, 0x000cf405}, {0x16, 0x000e0330},
1205 {0x16, 0x000a0330}, {0x16, 0x00060330},
1206 {0x16, 0x00020330}, {0x00, 0x00010159},
1207 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1208 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1209 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1210 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1211 {0x00, 0x00030159},
1212 {0xff, 0xffffffff}
1213 };
1214
1215 static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
1216 { /* RF_A */
1217 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
1218 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
1219 .lssiparm = REG_FPGA0_XA_LSSI_PARM,
1220 .hspiread = REG_HSPI_XA_READBACK,
1221 .lssiread = REG_FPGA0_XA_LSSI_READBACK,
1222 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,
1223 },
1224 { /* RF_B */
1225 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,
1226 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,
1227 .lssiparm = REG_FPGA0_XB_LSSI_PARM,
1228 .hspiread = REG_HSPI_XB_READBACK,
1229 .lssiread = REG_FPGA0_XB_LSSI_READBACK,
1230 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,
1231 },
1232 };
1233
1234 static const u32 rtl8723au_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
1235 REG_OFDM0_XA_RX_IQ_IMBALANCE,
1236 REG_OFDM0_XB_RX_IQ_IMBALANCE,
1237 REG_OFDM0_ENERGY_CCA_THRES,
1238 REG_OFDM0_AGCR_SSI_TABLE,
1239 REG_OFDM0_XA_TX_IQ_IMBALANCE,
1240 REG_OFDM0_XB_TX_IQ_IMBALANCE,
1241 REG_OFDM0_XC_TX_AFE,
1242 REG_OFDM0_XD_TX_AFE,
1243 REG_OFDM0_RX_IQ_EXT_ANTA
1244 };
1245
1246 static u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)
1247 {
1248 struct usb_device *udev = priv->udev;
1249 int len;
1250 u8 data;
1251
1252 mutex_lock(&priv->usb_buf_mutex);
1253 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1254 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1255 addr, 0, &priv->usb_buf.val8, sizeof(u8),
1256 RTW_USB_CONTROL_MSG_TIMEOUT);
1257 data = priv->usb_buf.val8;
1258 mutex_unlock(&priv->usb_buf_mutex);
1259
1260 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1261 dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n",
1262 __func__, addr, data, len);
1263 return data;
1264 }
1265
1266 static u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)
1267 {
1268 struct usb_device *udev = priv->udev;
1269 int len;
1270 u16 data;
1271
1272 mutex_lock(&priv->usb_buf_mutex);
1273 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1274 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1275 addr, 0, &priv->usb_buf.val16, sizeof(u16),
1276 RTW_USB_CONTROL_MSG_TIMEOUT);
1277 data = le16_to_cpu(priv->usb_buf.val16);
1278 mutex_unlock(&priv->usb_buf_mutex);
1279
1280 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1281 dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n",
1282 __func__, addr, data, len);
1283 return data;
1284 }
1285
1286 static u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
1287 {
1288 struct usb_device *udev = priv->udev;
1289 int len;
1290 u32 data;
1291
1292 mutex_lock(&priv->usb_buf_mutex);
1293 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1294 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1295 addr, 0, &priv->usb_buf.val32, sizeof(u32),
1296 RTW_USB_CONTROL_MSG_TIMEOUT);
1297 data = le32_to_cpu(priv->usb_buf.val32);
1298 mutex_unlock(&priv->usb_buf_mutex);
1299
1300 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1301 dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n",
1302 __func__, addr, data, len);
1303 return data;
1304 }
1305
1306 static int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)
1307 {
1308 struct usb_device *udev = priv->udev;
1309 int ret;
1310
1311 mutex_lock(&priv->usb_buf_mutex);
1312 priv->usb_buf.val8 = val;
1313 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1314 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1315 addr, 0, &priv->usb_buf.val8, sizeof(u8),
1316 RTW_USB_CONTROL_MSG_TIMEOUT);
1317
1318 mutex_unlock(&priv->usb_buf_mutex);
1319
1320 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1321 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",
1322 __func__, addr, val);
1323 return ret;
1324 }
1325
1326 static int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)
1327 {
1328 struct usb_device *udev = priv->udev;
1329 int ret;
1330
1331 mutex_lock(&priv->usb_buf_mutex);
1332 priv->usb_buf.val16 = cpu_to_le16(val);
1333 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1334 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1335 addr, 0, &priv->usb_buf.val16, sizeof(u16),
1336 RTW_USB_CONTROL_MSG_TIMEOUT);
1337 mutex_unlock(&priv->usb_buf_mutex);
1338
1339 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1340 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",
1341 __func__, addr, val);
1342 return ret;
1343 }
1344
1345 static int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)
1346 {
1347 struct usb_device *udev = priv->udev;
1348 int ret;
1349
1350 mutex_lock(&priv->usb_buf_mutex);
1351 priv->usb_buf.val32 = cpu_to_le32(val);
1352 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1353 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1354 addr, 0, &priv->usb_buf.val32, sizeof(u32),
1355 RTW_USB_CONTROL_MSG_TIMEOUT);
1356 mutex_unlock(&priv->usb_buf_mutex);
1357
1358 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1359 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",
1360 __func__, addr, val);
1361 return ret;
1362 }
1363
1364 static int
1365 rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)
1366 {
1367 struct usb_device *udev = priv->udev;
1368 int blocksize = priv->fops->writeN_block_size;
1369 int ret, i, count, remainder;
1370
1371 count = len / blocksize;
1372 remainder = len % blocksize;
1373
1374 for (i = 0; i < count; i++) {
1375 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1376 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1377 addr, 0, buf, blocksize,
1378 RTW_USB_CONTROL_MSG_TIMEOUT);
1379 if (ret != blocksize)
1380 goto write_error;
1381
1382 addr += blocksize;
1383 buf += blocksize;
1384 }
1385
1386 if (remainder) {
1387 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1388 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1389 addr, 0, buf, remainder,
1390 RTW_USB_CONTROL_MSG_TIMEOUT);
1391 if (ret != remainder)
1392 goto write_error;
1393 }
1394
1395 return len;
1396
1397 write_error:
1398 dev_info(&udev->dev,
1399 "%s: Failed to write block at addr: %04x size: %04x\n",
1400 __func__, addr, blocksize);
1401 return -EAGAIN;
1402 }
1403
1404 static u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
1405 enum rtl8xxxu_rfpath path, u8 reg)
1406 {
1407 u32 hssia, val32, retval;
1408
1409 hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
1410 if (path != RF_A)
1411 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
1412 else
1413 val32 = hssia;
1414
1415 val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;
1416 val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);
1417 val32 |= FPGA0_HSSI_PARM2_EDGE_READ;
1418 hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;
1419 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1420
1421 udelay(10);
1422
1423 rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);
1424 udelay(100);
1425
1426 hssia |= FPGA0_HSSI_PARM2_EDGE_READ;
1427 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1428 udelay(10);
1429
1430 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
1431 if (val32 & FPGA0_HSSI_PARM1_PI)
1432 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
1433 else
1434 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
1435
1436 retval &= 0xfffff;
1437
1438 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)
1439 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1440 __func__, reg, retval);
1441 return retval;
1442 }
1443
1444 /*
1445 * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can
1446 * have write issues in high temperature conditions. We may have to
1447 * retry writing them.
1448 */
1449 static int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
1450 enum rtl8xxxu_rfpath path, u8 reg, u32 data)
1451 {
1452 int ret, retval;
1453 u32 dataaddr;
1454
1455 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
1456 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1457 __func__, reg, data);
1458
1459 data &= FPGA0_LSSI_PARM_DATA_MASK;
1460 dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
1461
1462 /* Use XB for path B */
1463 ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
1464 if (ret != sizeof(dataaddr))
1465 retval = -EIO;
1466 else
1467 retval = 0;
1468
1469 udelay(1);
1470
1471 return retval;
1472 }
1473
1474 static int rtl8723a_h2c_cmd(struct rtl8xxxu_priv *priv,
1475 struct h2c_cmd *h2c, int len)
1476 {
1477 struct device *dev = &priv->udev->dev;
1478 int mbox_nr, retry, retval = 0;
1479 int mbox_reg, mbox_ext_reg;
1480 u8 val8;
1481
1482 mutex_lock(&priv->h2c_mutex);
1483
1484 mbox_nr = priv->next_mbox;
1485 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
1486 mbox_ext_reg = priv->fops->mbox_ext_reg +
1487 (mbox_nr * priv->fops->mbox_ext_width);
1488
1489 /*
1490 * MBOX ready?
1491 */
1492 retry = 100;
1493 do {
1494 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
1495 if (!(val8 & BIT(mbox_nr)))
1496 break;
1497 } while (retry--);
1498
1499 if (!retry) {
1500 dev_info(dev, "%s: Mailbox busy\n", __func__);
1501 retval = -EBUSY;
1502 goto error;
1503 }
1504
1505 /*
1506 * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
1507 */
1508 if (len > sizeof(u32)) {
1509 if (priv->fops->mbox_ext_width == 4) {
1510 rtl8xxxu_write32(priv, mbox_ext_reg,
1511 le32_to_cpu(h2c->raw_wide.ext));
1512 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1513 dev_info(dev, "H2C_EXT %08x\n",
1514 le32_to_cpu(h2c->raw_wide.ext));
1515 } else {
1516 rtl8xxxu_write16(priv, mbox_ext_reg,
1517 le16_to_cpu(h2c->raw.ext));
1518 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1519 dev_info(dev, "H2C_EXT %04x\n",
1520 le16_to_cpu(h2c->raw.ext));
1521 }
1522 }
1523 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
1524 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1525 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
1526
1527 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
1528
1529 error:
1530 mutex_unlock(&priv->h2c_mutex);
1531 return retval;
1532 }
1533
1534 static void rtl8723a_enable_rf(struct rtl8xxxu_priv *priv)
1535 {
1536 u8 val8;
1537 u32 val32;
1538
1539 val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1540 val8 |= BIT(0) | BIT(3);
1541 rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
1542
1543 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1544 val32 &= ~(BIT(4) | BIT(5));
1545 val32 |= BIT(3);
1546 if (priv->rf_paths == 2) {
1547 val32 &= ~(BIT(20) | BIT(21));
1548 val32 |= BIT(19);
1549 }
1550 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1551
1552 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1553 val32 &= ~OFDM_RF_PATH_TX_MASK;
1554 if (priv->tx_paths == 2)
1555 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
1556 else if (priv->rtlchip == 0x8192c || priv->rtlchip == 0x8191c)
1557 val32 |= OFDM_RF_PATH_TX_B;
1558 else
1559 val32 |= OFDM_RF_PATH_TX_A;
1560 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1561
1562 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1563 val32 &= ~FPGA_RF_MODE_JAPAN;
1564 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1565
1566 if (priv->rf_paths == 2)
1567 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);
1568 else
1569 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);
1570
1571 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);
1572 if (priv->rf_paths == 2)
1573 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);
1574
1575 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
1576 }
1577
1578 static void rtl8723a_disable_rf(struct rtl8xxxu_priv *priv)
1579 {
1580 u8 sps0;
1581 u32 val32;
1582
1583 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
1584
1585 sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1586
1587 /* RF RX code for preamble power saving */
1588 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1589 val32 &= ~(BIT(3) | BIT(4) | BIT(5));
1590 if (priv->rf_paths == 2)
1591 val32 &= ~(BIT(19) | BIT(20) | BIT(21));
1592 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1593
1594 /* Disable TX for four paths */
1595 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1596 val32 &= ~OFDM_RF_PATH_TX_MASK;
1597 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1598
1599 /* Enable power saving */
1600 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1601 val32 |= FPGA_RF_MODE_JAPAN;
1602 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1603
1604 /* AFE control register to power down bits [30:22] */
1605 if (priv->rf_paths == 2)
1606 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);
1607 else
1608 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);
1609
1610 /* Power down RF module */
1611 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
1612 if (priv->rf_paths == 2)
1613 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);
1614
1615 sps0 &= ~(BIT(0) | BIT(3));
1616 rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);
1617 }
1618
1619
1620 static void rtl8723a_stop_tx_beacon(struct rtl8xxxu_priv *priv)
1621 {
1622 u8 val8;
1623
1624 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1625 val8 &= ~BIT(6);
1626 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1627
1628 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);
1629 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1630 val8 &= ~BIT(0);
1631 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1632 }
1633
1634
1635 /*
1636 * The rtl8723a has 3 channel groups for it's efuse settings. It only
1637 * supports the 2.4GHz band, so channels 1 - 14:
1638 * group 0: channels 1 - 3
1639 * group 1: channels 4 - 9
1640 * group 2: channels 10 - 14
1641 *
1642 * Note: We index from 0 in the code
1643 */
1644 static int rtl8723a_channel_to_group(int channel)
1645 {
1646 int group;
1647
1648 if (channel < 4)
1649 group = 0;
1650 else if (channel < 10)
1651 group = 1;
1652 else
1653 group = 2;
1654
1655 return group;
1656 }
1657
1658 static void rtl8723au_config_channel(struct ieee80211_hw *hw)
1659 {
1660 struct rtl8xxxu_priv *priv = hw->priv;
1661 u32 val32, rsr;
1662 u8 val8, opmode;
1663 bool ht = true;
1664 int sec_ch_above, channel;
1665 int i;
1666
1667 opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
1668 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1669 channel = hw->conf.chandef.chan->hw_value;
1670
1671 switch (hw->conf.chandef.width) {
1672 case NL80211_CHAN_WIDTH_20_NOHT:
1673 ht = false;
1674 case NL80211_CHAN_WIDTH_20:
1675 opmode |= BW_OPMODE_20MHZ;
1676 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1677
1678 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1679 val32 &= ~FPGA_RF_MODE;
1680 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1681
1682 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1683 val32 &= ~FPGA_RF_MODE;
1684 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1685
1686 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1687 val32 |= FPGA0_ANALOG2_20MHZ;
1688 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1689 break;
1690 case NL80211_CHAN_WIDTH_40:
1691 if (hw->conf.chandef.center_freq1 >
1692 hw->conf.chandef.chan->center_freq) {
1693 sec_ch_above = 1;
1694 channel += 2;
1695 } else {
1696 sec_ch_above = 0;
1697 channel -= 2;
1698 }
1699
1700 opmode &= ~BW_OPMODE_20MHZ;
1701 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1702 rsr &= ~RSR_RSC_BANDWIDTH_40M;
1703 if (sec_ch_above)
1704 rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
1705 else
1706 rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
1707 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
1708
1709 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1710 val32 |= FPGA_RF_MODE;
1711 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1712
1713 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1714 val32 |= FPGA_RF_MODE;
1715 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1716
1717 /*
1718 * Set Control channel to upper or lower. These settings
1719 * are required only for 40MHz
1720 */
1721 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1722 val32 &= ~CCK0_SIDEBAND;
1723 if (!sec_ch_above)
1724 val32 |= CCK0_SIDEBAND;
1725 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1726
1727 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1728 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1729 if (sec_ch_above)
1730 val32 |= OFDM_LSTF_PRIME_CH_LOW;
1731 else
1732 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1733 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1734
1735 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1736 val32 &= ~FPGA0_ANALOG2_20MHZ;
1737 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1738
1739 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1740 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1741 if (sec_ch_above)
1742 val32 |= FPGA0_PS_UPPER_CHANNEL;
1743 else
1744 val32 |= FPGA0_PS_LOWER_CHANNEL;
1745 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1746 break;
1747
1748 default:
1749 break;
1750 }
1751
1752 for (i = RF_A; i < priv->rf_paths; i++) {
1753 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1754 val32 &= ~MODE_AG_CHANNEL_MASK;
1755 val32 |= channel;
1756 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1757 }
1758
1759 if (ht)
1760 val8 = 0x0e;
1761 else
1762 val8 = 0x0a;
1763
1764 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1765 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1766
1767 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1768 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1769
1770 for (i = RF_A; i < priv->rf_paths; i++) {
1771 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1772 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
1773 val32 &= ~MODE_AG_CHANNEL_20MHZ;
1774 else
1775 val32 |= MODE_AG_CHANNEL_20MHZ;
1776 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1777 }
1778 }
1779
1780 static void rtl8723bu_config_channel(struct ieee80211_hw *hw)
1781 {
1782 struct rtl8xxxu_priv *priv = hw->priv;
1783 u32 val32, rsr;
1784 u8 val8, subchannel;
1785 u16 rf_mode_bw;
1786 bool ht = true;
1787 int sec_ch_above, channel;
1788 int i;
1789
1790 rf_mode_bw = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL);
1791 rf_mode_bw &= ~WMAC_TRXPTCL_CTL_BW_MASK;
1792 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1793 channel = hw->conf.chandef.chan->hw_value;
1794
1795 /* Hack */
1796 subchannel = 0;
1797
1798 switch (hw->conf.chandef.width) {
1799 case NL80211_CHAN_WIDTH_20_NOHT:
1800 ht = false;
1801 case NL80211_CHAN_WIDTH_20:
1802 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_20;
1803 subchannel = 0;
1804
1805 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1806 val32 &= ~FPGA_RF_MODE;
1807 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1808
1809 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1810 val32 &= ~FPGA_RF_MODE;
1811 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1812
1813 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT);
1814 val32 &= ~(BIT(30) | BIT(31));
1815 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32);
1816
1817 break;
1818 case NL80211_CHAN_WIDTH_40:
1819 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_40;
1820
1821 if (hw->conf.chandef.center_freq1 >
1822 hw->conf.chandef.chan->center_freq) {
1823 sec_ch_above = 1;
1824 channel += 2;
1825 } else {
1826 sec_ch_above = 0;
1827 channel -= 2;
1828 }
1829
1830 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1831 val32 |= FPGA_RF_MODE;
1832 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1833
1834 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1835 val32 |= FPGA_RF_MODE;
1836 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1837
1838 /*
1839 * Set Control channel to upper or lower. These settings
1840 * are required only for 40MHz
1841 */
1842 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1843 val32 &= ~CCK0_SIDEBAND;
1844 if (!sec_ch_above)
1845 val32 |= CCK0_SIDEBAND;
1846 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1847
1848 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1849 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1850 if (sec_ch_above)
1851 val32 |= OFDM_LSTF_PRIME_CH_LOW;
1852 else
1853 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1854 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1855
1856 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1857 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1858 if (sec_ch_above)
1859 val32 |= FPGA0_PS_UPPER_CHANNEL;
1860 else
1861 val32 |= FPGA0_PS_LOWER_CHANNEL;
1862 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1863 break;
1864 case NL80211_CHAN_WIDTH_80:
1865 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_80;
1866 break;
1867 default:
1868 break;
1869 }
1870
1871 for (i = RF_A; i < priv->rf_paths; i++) {
1872 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1873 val32 &= ~MODE_AG_CHANNEL_MASK;
1874 val32 |= channel;
1875 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1876 }
1877
1878 rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, rf_mode_bw);
1879 rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel);
1880
1881 if (ht)
1882 val8 = 0x0e;
1883 else
1884 val8 = 0x0a;
1885
1886 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1887 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1888
1889 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1890 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1891
1892 for (i = RF_A; i < priv->rf_paths; i++) {
1893 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1894 val32 &= ~MODE_AG_BW_MASK;
1895 switch(hw->conf.chandef.width) {
1896 case NL80211_CHAN_WIDTH_80:
1897 val32 |= MODE_AG_BW_80MHZ_8723B;
1898 break;
1899 case NL80211_CHAN_WIDTH_40:
1900 val32 |= MODE_AG_BW_40MHZ_8723B;
1901 break;
1902 default:
1903 val32 |= MODE_AG_BW_20MHZ_8723B;
1904 break;
1905 }
1906 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1907 }
1908 }
1909
1910 static void
1911 rtl8723a_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
1912 {
1913 u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];
1914 u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];
1915 u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;
1916 u8 val8;
1917 int group, i;
1918
1919 group = rtl8723a_channel_to_group(channel);
1920
1921 cck[0] = priv->cck_tx_power_index_A[group];
1922 cck[1] = priv->cck_tx_power_index_B[group];
1923
1924 ofdm[0] = priv->ht40_1s_tx_power_index_A[group];
1925 ofdm[1] = priv->ht40_1s_tx_power_index_B[group];
1926
1927 ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;
1928 ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;
1929
1930 mcsbase[0] = ofdm[0];
1931 mcsbase[1] = ofdm[1];
1932 if (!ht40) {
1933 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;
1934 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;
1935 }
1936
1937 if (priv->tx_paths > 1) {
1938 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)
1939 ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a;
1940 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)
1941 ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b;
1942 }
1943
1944 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
1945 dev_info(&priv->udev->dev,
1946 "%s: Setting TX power CCK A: %02x, "
1947 "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
1948 __func__, cck[0], cck[1], ofdm[0], ofdm[1]);
1949
1950 for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {
1951 if (cck[i] > RF6052_MAX_TX_PWR)
1952 cck[i] = RF6052_MAX_TX_PWR;
1953 if (ofdm[i] > RF6052_MAX_TX_PWR)
1954 ofdm[i] = RF6052_MAX_TX_PWR;
1955 }
1956
1957 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
1958 val32 &= 0xffff00ff;
1959 val32 |= (cck[0] << 8);
1960 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
1961
1962 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1963 val32 &= 0xff;
1964 val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));
1965 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1966
1967 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1968 val32 &= 0xffffff00;
1969 val32 |= cck[1];
1970 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1971
1972 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
1973 val32 &= 0xff;
1974 val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));
1975 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
1976
1977 ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |
1978 ofdmbase[0] << 16 | ofdmbase[0] << 24;
1979 ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |
1980 ofdmbase[1] << 16 | ofdmbase[1] << 24;
1981 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm_a);
1982 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm_b);
1983
1984 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm_a);
1985 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm_b);
1986
1987 mcs_a = mcsbase[0] | mcsbase[0] << 8 |
1988 mcsbase[0] << 16 | mcsbase[0] << 24;
1989 mcs_b = mcsbase[1] | mcsbase[1] << 8 |
1990 mcsbase[1] << 16 | mcsbase[1] << 24;
1991
1992 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs_a);
1993 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs_b);
1994
1995 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs_a);
1996 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs_b);
1997
1998 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs_a);
1999 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs_b);
2000
2001 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs_a);
2002 for (i = 0; i < 3; i++) {
2003 if (i != 2)
2004 val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0;
2005 else
2006 val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0;
2007 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);
2008 }
2009 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs_b);
2010 for (i = 0; i < 3; i++) {
2011 if (i != 2)
2012 val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0;
2013 else
2014 val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0;
2015 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);
2016 }
2017 }
2018
2019 static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,
2020 enum nl80211_iftype linktype)
2021 {
2022 u8 val8;
2023
2024 val8 = rtl8xxxu_read8(priv, REG_MSR);
2025 val8 &= ~MSR_LINKTYPE_MASK;
2026
2027 switch (linktype) {
2028 case NL80211_IFTYPE_UNSPECIFIED:
2029 val8 |= MSR_LINKTYPE_NONE;
2030 break;
2031 case NL80211_IFTYPE_ADHOC:
2032 val8 |= MSR_LINKTYPE_ADHOC;
2033 break;
2034 case NL80211_IFTYPE_STATION:
2035 val8 |= MSR_LINKTYPE_STATION;
2036 break;
2037 case NL80211_IFTYPE_AP:
2038 val8 |= MSR_LINKTYPE_AP;
2039 break;
2040 default:
2041 goto out;
2042 }
2043
2044 rtl8xxxu_write8(priv, REG_MSR, val8);
2045 out:
2046 return;
2047 }
2048
2049 static void
2050 rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)
2051 {
2052 u16 val16;
2053
2054 val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &
2055 RETRY_LIMIT_SHORT_MASK) |
2056 ((long_retry << RETRY_LIMIT_LONG_SHIFT) &
2057 RETRY_LIMIT_LONG_MASK);
2058
2059 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
2060 }
2061
2062 static void
2063 rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)
2064 {
2065 u16 val16;
2066
2067 val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |
2068 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);
2069
2070 rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);
2071 }
2072
2073 static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
2074 {
2075 struct device *dev = &priv->udev->dev;
2076 char *cut;
2077
2078 switch (priv->chip_cut) {
2079 case 0:
2080 cut = "A";
2081 break;
2082 case 1:
2083 cut = "B";
2084 break;
2085 case 2:
2086 cut = "C";
2087 break;
2088 case 3:
2089 cut = "D";
2090 break;
2091 case 4:
2092 cut = "E";
2093 break;
2094 default:
2095 cut = "unknown";
2096 }
2097
2098 dev_info(dev,
2099 "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
2100 priv->chip_name, cut, priv->chip_vendor, priv->tx_paths,
2101 priv->rx_paths, priv->ep_tx_count, priv->has_wifi,
2102 priv->has_bluetooth, priv->has_gps, priv->hi_pa);
2103
2104 dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);
2105 }
2106
2107 static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
2108 {
2109 struct device *dev = &priv->udev->dev;
2110 u32 val32, bonding;
2111 u16 val16;
2112
2113 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
2114 priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >>
2115 SYS_CFG_CHIP_VERSION_SHIFT;
2116 if (val32 & SYS_CFG_TRP_VAUX_EN) {
2117 dev_info(dev, "Unsupported test chip\n");
2118 return -ENOTSUPP;
2119 }
2120
2121 if (val32 & SYS_CFG_BT_FUNC) {
2122 if (priv->chip_cut >= 3) {
2123 sprintf(priv->chip_name, "8723BU");
2124 priv->rtlchip = 0x8723b;
2125 } else {
2126 sprintf(priv->chip_name, "8723AU");
2127 priv->usb_interrupts = 1;
2128 priv->rtlchip = 0x8723a;
2129 }
2130
2131 priv->rf_paths = 1;
2132 priv->rx_paths = 1;
2133 priv->tx_paths = 1;
2134
2135 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
2136 if (val32 & MULTI_WIFI_FUNC_EN)
2137 priv->has_wifi = 1;
2138 if (val32 & MULTI_BT_FUNC_EN)
2139 priv->has_bluetooth = 1;
2140 if (val32 & MULTI_GPS_FUNC_EN)
2141 priv->has_gps = 1;
2142 priv->is_multi_func = 1;
2143 } else if (val32 & SYS_CFG_TYPE_ID) {
2144 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM);
2145 bonding &= HPON_FSM_BONDING_MASK;
2146 if (priv->chip_cut >= 3) {
2147 if (bonding == HPON_FSM_BONDING_1T2R) {
2148 sprintf(priv->chip_name, "8191EU");
2149 priv->rf_paths = 2;
2150 priv->rx_paths = 2;
2151 priv->tx_paths = 1;
2152 priv->rtlchip = 0x8191e;
2153 } else {
2154 sprintf(priv->chip_name, "8192EU");
2155 priv->rf_paths = 2;
2156 priv->rx_paths = 2;
2157 priv->tx_paths = 2;
2158 priv->rtlchip = 0x8192e;
2159 }
2160 } else if (bonding == HPON_FSM_BONDING_1T2R) {
2161 sprintf(priv->chip_name, "8191CU");
2162 priv->rf_paths = 2;
2163 priv->rx_paths = 2;
2164 priv->tx_paths = 1;
2165 priv->usb_interrupts = 1;
2166 priv->rtlchip = 0x8191c;
2167 } else {
2168 sprintf(priv->chip_name, "8192CU");
2169 priv->rf_paths = 2;
2170 priv->rx_paths = 2;
2171 priv->tx_paths = 2;
2172 priv->usb_interrupts = 1;
2173 priv->rtlchip = 0x8192c;
2174 }
2175 priv->has_wifi = 1;
2176 } else {
2177 sprintf(priv->chip_name, "8188CU");
2178 priv->rf_paths = 1;
2179 priv->rx_paths = 1;
2180 priv->tx_paths = 1;
2181 priv->rtlchip = 0x8188c;
2182 priv->usb_interrupts = 1;
2183 priv->has_wifi = 1;
2184 }
2185
2186 switch (priv->rtlchip) {
2187 case 0x8188e:
2188 case 0x8192e:
2189 case 0x8723b:
2190 switch (val32 & SYS_CFG_VENDOR_EXT_MASK) {
2191 case SYS_CFG_VENDOR_ID_TSMC:
2192 sprintf(priv->chip_vendor, "TSMC");
2193 break;
2194 case SYS_CFG_VENDOR_ID_SMIC:
2195 sprintf(priv->chip_vendor, "SMIC");
2196 priv->vendor_smic = 1;
2197 break;
2198 case SYS_CFG_VENDOR_ID_UMC:
2199 sprintf(priv->chip_vendor, "UMC");
2200 priv->vendor_umc = 1;
2201 break;
2202 default:
2203 sprintf(priv->chip_vendor, "unknown");
2204 }
2205 break;
2206 default:
2207 if (val32 & SYS_CFG_VENDOR_ID) {
2208 sprintf(priv->chip_vendor, "UMC");
2209 priv->vendor_umc = 1;
2210 } else {
2211 sprintf(priv->chip_vendor, "TSMC");
2212 }
2213 }
2214
2215 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
2216 priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28;
2217
2218 val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
2219 if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
2220 priv->ep_tx_high_queue = 1;
2221 priv->ep_tx_count++;
2222 }
2223
2224 if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {
2225 priv->ep_tx_normal_queue = 1;
2226 priv->ep_tx_count++;
2227 }
2228
2229 if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {
2230 priv->ep_tx_low_queue = 1;
2231 priv->ep_tx_count++;
2232 }
2233
2234 /*
2235 * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
2236 */
2237 if (!priv->ep_tx_count) {
2238 switch (priv->nr_out_eps) {
2239 case 4:
2240 case 3:
2241 priv->ep_tx_low_queue = 1;
2242 priv->ep_tx_count++;
2243 case 2:
2244 priv->ep_tx_normal_queue = 1;
2245 priv->ep_tx_count++;
2246 case 1:
2247 priv->ep_tx_high_queue = 1;
2248 priv->ep_tx_count++;
2249 break;
2250 default:
2251 dev_info(dev, "Unsupported USB TX end-points\n");
2252 return -ENOTSUPP;
2253 }
2254 }
2255
2256 return 0;
2257 }
2258
2259 static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv)
2260 {
2261 struct rtl8723au_efuse *efuse = &priv->efuse_wifi.efuse8723;
2262
2263 if (efuse->rtl_id != cpu_to_le16(0x8129))
2264 return -EINVAL;
2265
2266 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2267
2268 memcpy(priv->cck_tx_power_index_A,
2269 efuse->cck_tx_power_index_A,
2270 sizeof(priv->cck_tx_power_index_A));
2271 memcpy(priv->cck_tx_power_index_B,
2272 efuse->cck_tx_power_index_B,
2273 sizeof(priv->cck_tx_power_index_B));
2274
2275 memcpy(priv->ht40_1s_tx_power_index_A,
2276 efuse->ht40_1s_tx_power_index_A,
2277 sizeof(priv->ht40_1s_tx_power_index_A));
2278 memcpy(priv->ht40_1s_tx_power_index_B,
2279 efuse->ht40_1s_tx_power_index_B,
2280 sizeof(priv->ht40_1s_tx_power_index_B));
2281
2282 memcpy(priv->ht20_tx_power_index_diff,
2283 efuse->ht20_tx_power_index_diff,
2284 sizeof(priv->ht20_tx_power_index_diff));
2285 memcpy(priv->ofdm_tx_power_index_diff,
2286 efuse->ofdm_tx_power_index_diff,
2287 sizeof(priv->ofdm_tx_power_index_diff));
2288
2289 memcpy(priv->ht40_max_power_offset,
2290 efuse->ht40_max_power_offset,
2291 sizeof(priv->ht40_max_power_offset));
2292 memcpy(priv->ht20_max_power_offset,
2293 efuse->ht20_max_power_offset,
2294 sizeof(priv->ht20_max_power_offset));
2295
2296 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
2297 efuse->vendor_name);
2298 dev_info(&priv->udev->dev, "Product: %.41s\n",
2299 efuse->device_name);
2300 return 0;
2301 }
2302
2303 static int rtl8723bu_parse_efuse(struct rtl8xxxu_priv *priv)
2304 {
2305 struct rtl8723bu_efuse *efuse = &priv->efuse_wifi.efuse8723bu;
2306
2307 if (efuse->rtl_id != cpu_to_le16(0x8129))
2308 return -EINVAL;
2309
2310 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2311
2312 memcpy(priv->cck_tx_power_index_A, efuse->cck_tx_power_index_A,
2313 sizeof(priv->cck_tx_power_index_A));
2314 memcpy(priv->cck_tx_power_index_B, efuse->cck_tx_power_index_B,
2315 sizeof(priv->cck_tx_power_index_B));
2316
2317 memcpy(priv->ht40_1s_tx_power_index_A, efuse->ht40_1s_tx_power_index_A,
2318 sizeof(priv->ht40_1s_tx_power_index_A));
2319 memcpy(priv->ht40_1s_tx_power_index_B, efuse->ht40_1s_tx_power_index_B,
2320 sizeof(priv->ht40_1s_tx_power_index_B));
2321
2322 dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name);
2323 dev_info(&priv->udev->dev, "Product: %.41s\n", efuse->device_name);
2324
2325 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2326 int i;
2327 unsigned char *raw = priv->efuse_wifi.raw;
2328
2329 dev_info(&priv->udev->dev,
2330 "%s: dumping efuse (0x%02zx bytes):\n",
2331 __func__, sizeof(struct rtl8723bu_efuse));
2332 for (i = 0; i < sizeof(struct rtl8723bu_efuse); i += 8) {
2333 dev_info(&priv->udev->dev, "%02x: "
2334 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2335 raw[i], raw[i + 1], raw[i + 2],
2336 raw[i + 3], raw[i + 4], raw[i + 5],
2337 raw[i + 6], raw[i + 7]);
2338 }
2339 }
2340
2341 return 0;
2342 }
2343
2344 #ifdef CONFIG_RTL8XXXU_UNTESTED
2345
2346 static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv *priv)
2347 {
2348 struct rtl8192cu_efuse *efuse = &priv->efuse_wifi.efuse8192;
2349 int i;
2350
2351 if (efuse->rtl_id != cpu_to_le16(0x8129))
2352 return -EINVAL;
2353
2354 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2355
2356 memcpy(priv->cck_tx_power_index_A,
2357 efuse->cck_tx_power_index_A,
2358 sizeof(priv->cck_tx_power_index_A));
2359 memcpy(priv->cck_tx_power_index_B,
2360 efuse->cck_tx_power_index_B,
2361 sizeof(priv->cck_tx_power_index_B));
2362
2363 memcpy(priv->ht40_1s_tx_power_index_A,
2364 efuse->ht40_1s_tx_power_index_A,
2365 sizeof(priv->ht40_1s_tx_power_index_A));
2366 memcpy(priv->ht40_1s_tx_power_index_B,
2367 efuse->ht40_1s_tx_power_index_B,
2368 sizeof(priv->ht40_1s_tx_power_index_B));
2369 memcpy(priv->ht40_2s_tx_power_index_diff,
2370 efuse->ht40_2s_tx_power_index_diff,
2371 sizeof(priv->ht40_2s_tx_power_index_diff));
2372
2373 memcpy(priv->ht20_tx_power_index_diff,
2374 efuse->ht20_tx_power_index_diff,
2375 sizeof(priv->ht20_tx_power_index_diff));
2376 memcpy(priv->ofdm_tx_power_index_diff,
2377 efuse->ofdm_tx_power_index_diff,
2378 sizeof(priv->ofdm_tx_power_index_diff));
2379
2380 memcpy(priv->ht40_max_power_offset,
2381 efuse->ht40_max_power_offset,
2382 sizeof(priv->ht40_max_power_offset));
2383 memcpy(priv->ht20_max_power_offset,
2384 efuse->ht20_max_power_offset,
2385 sizeof(priv->ht20_max_power_offset));
2386
2387 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
2388 efuse->vendor_name);
2389 dev_info(&priv->udev->dev, "Product: %.20s\n",
2390 efuse->device_name);
2391
2392 if (efuse->rf_regulatory & 0x20) {
2393 sprintf(priv->chip_name, "8188RU");
2394 priv->hi_pa = 1;
2395 }
2396
2397 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2398 unsigned char *raw = priv->efuse_wifi.raw;
2399
2400 dev_info(&priv->udev->dev,
2401 "%s: dumping efuse (0x%02zx bytes):\n",
2402 __func__, sizeof(struct rtl8192cu_efuse));
2403 for (i = 0; i < sizeof(struct rtl8192cu_efuse); i += 8) {
2404 dev_info(&priv->udev->dev, "%02x: "
2405 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2406 raw[i], raw[i + 1], raw[i + 2],
2407 raw[i + 3], raw[i + 4], raw[i + 5],
2408 raw[i + 6], raw[i + 7]);
2409 }
2410 }
2411 return 0;
2412 }
2413
2414 #endif
2415
2416 static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv *priv)
2417 {
2418 struct rtl8192eu_efuse *efuse = &priv->efuse_wifi.efuse8192eu;
2419 int i;
2420
2421 if (efuse->rtl_id != cpu_to_le16(0x8129))
2422 return -EINVAL;
2423
2424 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2425
2426 dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name);
2427 dev_info(&priv->udev->dev, "Product: %.11s\n", efuse->device_name);
2428 dev_info(&priv->udev->dev, "Serial: %.11s\n", efuse->serial);
2429
2430 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2431 unsigned char *raw = priv->efuse_wifi.raw;
2432
2433 dev_info(&priv->udev->dev,
2434 "%s: dumping efuse (0x%02zx bytes):\n",
2435 __func__, sizeof(struct rtl8192eu_efuse));
2436 for (i = 0; i < sizeof(struct rtl8192eu_efuse); i += 8) {
2437 dev_info(&priv->udev->dev, "%02x: "
2438 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2439 raw[i], raw[i + 1], raw[i + 2],
2440 raw[i + 3], raw[i + 4], raw[i + 5],
2441 raw[i + 6], raw[i + 7]);
2442 }
2443 }
2444 return 0;
2445 }
2446
2447 static int
2448 rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
2449 {
2450 int i;
2451 u8 val8;
2452 u32 val32;
2453
2454 /* Write Address */
2455 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);
2456 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);
2457 val8 &= 0xfc;
2458 val8 |= (offset >> 8) & 0x03;
2459 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);
2460
2461 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);
2462 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);
2463
2464 /* Poll for data read */
2465 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2466 for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
2467 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2468 if (val32 & BIT(31))
2469 break;
2470 }
2471
2472 if (i == RTL8XXXU_MAX_REG_POLL)
2473 return -EIO;
2474
2475 udelay(50);
2476 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2477
2478 *data = val32 & 0xff;
2479 return 0;
2480 }
2481
2482 static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
2483 {
2484 struct device *dev = &priv->udev->dev;
2485 int i, ret = 0;
2486 u8 val8, word_mask, header, extheader;
2487 u16 val16, efuse_addr, offset;
2488 u32 val32;
2489
2490 val16 = rtl8xxxu_read16(priv, REG_9346CR);
2491 if (val16 & EEPROM_ENABLE)
2492 priv->has_eeprom = 1;
2493 if (val16 & EEPROM_BOOT)
2494 priv->boot_eeprom = 1;
2495
2496 if (priv->is_multi_func) {
2497 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
2498 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;
2499 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);
2500 }
2501
2502 dev_dbg(dev, "Booting from %s\n",
2503 priv->boot_eeprom ? "EEPROM" : "EFUSE");
2504
2505 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);
2506
2507 /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
2508 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
2509 if (!(val16 & SYS_ISO_PWC_EV12V)) {
2510 val16 |= SYS_ISO_PWC_EV12V;
2511 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
2512 }
2513 /* Reset: 0x0000[28], default valid */
2514 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2515 if (!(val16 & SYS_FUNC_ELDR)) {
2516 val16 |= SYS_FUNC_ELDR;
2517 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2518 }
2519
2520 /*
2521 * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
2522 */
2523 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
2524 if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {
2525 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);
2526 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);
2527 }
2528
2529 /* Default value is 0xff */
2530 memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN);
2531
2532 efuse_addr = 0;
2533 while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
2534 u16 map_addr;
2535
2536 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);
2537 if (ret || header == 0xff)
2538 goto exit;
2539
2540 if ((header & 0x1f) == 0x0f) { /* extended header */
2541 offset = (header & 0xe0) >> 5;
2542
2543 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,
2544 &extheader);
2545 if (ret)
2546 goto exit;
2547 /* All words disabled */
2548 if ((extheader & 0x0f) == 0x0f)
2549 continue;
2550
2551 offset |= ((extheader & 0xf0) >> 1);
2552 word_mask = extheader & 0x0f;
2553 } else {
2554 offset = (header >> 4) & 0x0f;
2555 word_mask = header & 0x0f;
2556 }
2557
2558 /* Get word enable value from PG header */
2559
2560 /* We have 8 bits to indicate validity */
2561 map_addr = offset * 8;
2562 if (map_addr >= EFUSE_MAP_LEN) {
2563 dev_warn(dev, "%s: Illegal map_addr (%04x), "
2564 "efuse corrupt!\n",
2565 __func__, map_addr);
2566 ret = -EINVAL;
2567 goto exit;
2568 }
2569 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
2570 /* Check word enable condition in the section */
2571 if (word_mask & BIT(i)) {
2572 map_addr += 2;
2573 continue;
2574 }
2575
2576 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
2577 if (ret)
2578 goto exit;
2579 priv->efuse_wifi.raw[map_addr++] = val8;
2580
2581 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
2582 if (ret)
2583 goto exit;
2584 priv->efuse_wifi.raw[map_addr++] = val8;
2585 }
2586 }
2587
2588 exit:
2589 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);
2590
2591 return ret;
2592 }
2593
2594 static void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv)
2595 {
2596 u8 val8;
2597 u16 sys_func;
2598
2599 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
2600 val8 &= ~BIT(0);
2601 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2602 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2603 sys_func &= ~SYS_FUNC_CPU_ENABLE;
2604 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2605 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
2606 val8 |= BIT(0);
2607 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2608 sys_func |= SYS_FUNC_CPU_ENABLE;
2609 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2610 }
2611
2612 static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
2613 {
2614 struct device *dev = &priv->udev->dev;
2615 int ret = 0, i;
2616 u32 val32;
2617
2618 /* Poll checksum report */
2619 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2620 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2621 if (val32 & MCU_FW_DL_CSUM_REPORT)
2622 break;
2623 }
2624
2625 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2626 dev_warn(dev, "Firmware checksum poll timed out\n");
2627 ret = -EAGAIN;
2628 goto exit;
2629 }
2630
2631 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2632 val32 |= MCU_FW_DL_READY;
2633 val32 &= ~MCU_WINT_INIT_READY;
2634 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2635
2636 /*
2637 * Reset the 8051 in order for the firmware to start running,
2638 * otherwise it won't come up on the 8192eu
2639 */
2640 rtl8xxxu_reset_8051(priv);
2641
2642 /* Wait for firmware to become ready */
2643 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2644 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2645 if (val32 & MCU_WINT_INIT_READY)
2646 break;
2647
2648 udelay(100);
2649 }
2650
2651 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2652 dev_warn(dev, "Firmware failed to start\n");
2653 ret = -EAGAIN;
2654 goto exit;
2655 }
2656
2657 exit:
2658 return ret;
2659 }
2660
2661 static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
2662 {
2663 int pages, remainder, i, ret;
2664 u8 val8;
2665 u16 val16;
2666 u32 val32;
2667 u8 *fwptr;
2668
2669 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);
2670 val8 |= 4;
2671 rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
2672
2673 /* 8051 enable */
2674 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2675 val16 |= SYS_FUNC_CPU_ENABLE;
2676 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2677
2678 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2679 if (val8 & MCU_FW_RAM_SEL) {
2680 pr_info("do the RAM reset\n");
2681 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
2682 rtl8xxxu_reset_8051(priv);
2683 }
2684
2685 /* MCU firmware download enable */
2686 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2687 val8 |= MCU_FW_DL_ENABLE;
2688 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
2689
2690 /* 8051 reset */
2691 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2692 val32 &= ~BIT(19);
2693 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2694
2695 /* Reset firmware download checksum */
2696 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2697 val8 |= MCU_FW_DL_CSUM_REPORT;
2698 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
2699
2700 pages = priv->fw_size / RTL_FW_PAGE_SIZE;
2701 remainder = priv->fw_size % RTL_FW_PAGE_SIZE;
2702
2703 fwptr = priv->fw_data->data;
2704
2705 for (i = 0; i < pages; i++) {
2706 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2707 val8 |= i;
2708 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
2709
2710 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2711 fwptr, RTL_FW_PAGE_SIZE);
2712 if (ret != RTL_FW_PAGE_SIZE) {
2713 ret = -EAGAIN;
2714 goto fw_abort;
2715 }
2716
2717 fwptr += RTL_FW_PAGE_SIZE;
2718 }
2719
2720 if (remainder) {
2721 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2722 val8 |= i;
2723 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
2724 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2725 fwptr, remainder);
2726 if (ret != remainder) {
2727 ret = -EAGAIN;
2728 goto fw_abort;
2729 }
2730 }
2731
2732 ret = 0;
2733 fw_abort:
2734 /* MCU firmware download disable */
2735 val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL);
2736 val16 &= ~MCU_FW_DL_ENABLE;
2737 rtl8xxxu_write16(priv, REG_MCU_FW_DL, val16);
2738
2739 return ret;
2740 }
2741
2742 static int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name)
2743 {
2744 struct device *dev = &priv->udev->dev;
2745 const struct firmware *fw;
2746 int ret = 0;
2747 u16 signature;
2748
2749 dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);
2750 if (request_firmware(&fw, fw_name, &priv->udev->dev)) {
2751 dev_warn(dev, "request_firmware(%s) failed\n", fw_name);
2752 ret = -EAGAIN;
2753 goto exit;
2754 }
2755 if (!fw) {
2756 dev_warn(dev, "Firmware data not available\n");
2757 ret = -EINVAL;
2758 goto exit;
2759 }
2760
2761 priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);
2762 if (!priv->fw_data) {
2763 ret = -ENOMEM;
2764 goto exit;
2765 }
2766 priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);
2767
2768 signature = le16_to_cpu(priv->fw_data->signature);
2769 switch (signature & 0xfff0) {
2770 case 0x92e0:
2771 case 0x92c0:
2772 case 0x88c0:
2773 case 0x5300:
2774 case 0x2300:
2775 break;
2776 default:
2777 ret = -EINVAL;
2778 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",
2779 __func__, signature);
2780 }
2781
2782 dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",
2783 le16_to_cpu(priv->fw_data->major_version),
2784 priv->fw_data->minor_version, signature);
2785
2786 exit:
2787 release_firmware(fw);
2788 return ret;
2789 }
2790
2791 static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv)
2792 {
2793 char *fw_name;
2794 int ret;
2795
2796 switch (priv->chip_cut) {
2797 case 0:
2798 fw_name = "rtlwifi/rtl8723aufw_A.bin";
2799 break;
2800 case 1:
2801 if (priv->enable_bluetooth)
2802 fw_name = "rtlwifi/rtl8723aufw_B.bin";
2803 else
2804 fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
2805
2806 break;
2807 default:
2808 return -EINVAL;
2809 }
2810
2811 ret = rtl8xxxu_load_firmware(priv, fw_name);
2812 return ret;
2813 }
2814
2815 static int rtl8723bu_load_firmware(struct rtl8xxxu_priv *priv)
2816 {
2817 char *fw_name;
2818 int ret;
2819
2820 if (priv->enable_bluetooth)
2821 fw_name = "rtlwifi/rtl8723bu_bt.bin";
2822 else
2823 fw_name = "rtlwifi/rtl8723bu_nic.bin";
2824
2825 ret = rtl8xxxu_load_firmware(priv, fw_name);
2826 return ret;
2827 }
2828
2829 #ifdef CONFIG_RTL8XXXU_UNTESTED
2830
2831 static int rtl8192cu_load_firmware(struct rtl8xxxu_priv *priv)
2832 {
2833 char *fw_name;
2834 int ret;
2835
2836 if (!priv->vendor_umc)
2837 fw_name = "rtlwifi/rtl8192cufw_TMSC.bin";
2838 else if (priv->chip_cut || priv->rtlchip == 0x8192c)
2839 fw_name = "rtlwifi/rtl8192cufw_B.bin";
2840 else
2841 fw_name = "rtlwifi/rtl8192cufw_A.bin";
2842
2843 ret = rtl8xxxu_load_firmware(priv, fw_name);
2844
2845 return ret;
2846 }
2847
2848 #endif
2849
2850 static int rtl8192eu_load_firmware(struct rtl8xxxu_priv *priv)
2851 {
2852 char *fw_name;
2853 int ret;
2854
2855 fw_name = "rtlwifi/rtl8192eu_nic.bin";
2856
2857 ret = rtl8xxxu_load_firmware(priv, fw_name);
2858
2859 return ret;
2860 }
2861
2862 static void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
2863 {
2864 u16 val16;
2865 int i = 100;
2866
2867 /* Inform 8051 to perform reset */
2868 rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
2869
2870 for (i = 100; i > 0; i--) {
2871 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2872
2873 if (!(val16 & SYS_FUNC_CPU_ENABLE)) {
2874 dev_dbg(&priv->udev->dev,
2875 "%s: Firmware self reset success!\n", __func__);
2876 break;
2877 }
2878 udelay(50);
2879 }
2880
2881 if (!i) {
2882 /* Force firmware reset */
2883 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2884 val16 &= ~SYS_FUNC_CPU_ENABLE;
2885 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2886 }
2887 }
2888
2889 static void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv)
2890 {
2891 u32 val32;
2892
2893 val32 = rtl8xxxu_read32(priv, 0x64);
2894 val32 &= ~(BIT(20) | BIT(24));
2895 rtl8xxxu_write32(priv, 0x64, val32);
2896
2897 val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG);
2898 val32 &= ~BIT(4);
2899 val32 |= BIT(3);
2900 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32);
2901
2902 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
2903 val32 &= ~BIT(23);
2904 val32 |= BIT(24);
2905 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
2906
2907 val32 = rtl8xxxu_read32(priv, 0x0944);
2908 val32 |= (BIT(0) | BIT(1));
2909 rtl8xxxu_write32(priv, 0x0944, val32);
2910
2911 val32 = rtl8xxxu_read32(priv, 0x0930);
2912 val32 &= 0xffffff00;
2913 val32 |= 0x77;
2914 rtl8xxxu_write32(priv, 0x0930, val32);
2915
2916 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
2917 val32 |= BIT(11);
2918 rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
2919 }
2920
2921 static int
2922 rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv, struct rtl8xxxu_reg8val *array)
2923 {
2924 int i, ret;
2925 u16 reg;
2926 u8 val;
2927
2928 for (i = 0; ; i++) {
2929 reg = array[i].reg;
2930 val = array[i].val;
2931
2932 if (reg == 0xffff && val == 0xff)
2933 break;
2934
2935 ret = rtl8xxxu_write8(priv, reg, val);
2936 if (ret != 1) {
2937 dev_warn(&priv->udev->dev,
2938 "Failed to initialize MAC\n");
2939 return -EAGAIN;
2940 }
2941 }
2942
2943 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
2944
2945 return 0;
2946 }
2947
2948 static int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
2949 struct rtl8xxxu_reg32val *array)
2950 {
2951 int i, ret;
2952 u16 reg;
2953 u32 val;
2954
2955 for (i = 0; ; i++) {
2956 reg = array[i].reg;
2957 val = array[i].val;
2958
2959 if (reg == 0xffff && val == 0xffffffff)
2960 break;
2961
2962 ret = rtl8xxxu_write32(priv, reg, val);
2963 if (ret != sizeof(val)) {
2964 dev_warn(&priv->udev->dev,
2965 "Failed to initialize PHY\n");
2966 return -EAGAIN;
2967 }
2968 udelay(1);
2969 }
2970
2971 return 0;
2972 }
2973
2974 /*
2975 * Most of this is black magic retrieved from the old rtl8723au driver
2976 */
2977 static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
2978 {
2979 u8 val8, ldoa15, ldov12d, lpldo, ldohci12;
2980 u32 val32;
2981
2982 /*
2983 * Todo: The vendor driver maintains a table of PHY register
2984 * addresses, which is initialized here. Do we need this?
2985 */
2986
2987 if (priv->rtlchip == 0x8723b) {
2988 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
2989 } else {
2990 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
2991 udelay(2);
2992 val8 |= AFE_PLL_320_ENABLE;
2993 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
2994 udelay(2);
2995
2996 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);
2997 udelay(2);
2998 }
2999
3000 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3001 val8 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;
3002 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3003
3004 /* AFE_XTAL_RF_GATE (bit 14) if addressing as 32 bit register */
3005 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
3006 val32 &= ~AFE_XTAL_RF_GATE;
3007 if (priv->has_bluetooth)
3008 val32 &= ~AFE_XTAL_BT_GATE;
3009 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
3010
3011 /* 6. 0x1f[7:0] = 0x07 */
3012 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
3013 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
3014
3015 if (priv->hi_pa)
3016 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);
3017 else if (priv->tx_paths == 2)
3018 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);
3019 else if (priv->rtlchip == 0x8723b)
3020 rtl8xxxu_init_phy_regs(priv, rtl8723b_phy_1t_init_table);
3021 else
3022 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);
3023
3024
3025 if (priv->rtlchip == 0x8188c && priv->hi_pa &&
3026 priv->vendor_umc && priv->chip_cut == 1)
3027 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);
3028
3029 if (priv->tx_paths == 1 && priv->rx_paths == 2) {
3030 /*
3031 * For 1T2R boards, patch the registers.
3032 *
3033 * It looks like 8191/2 1T2R boards use path B for TX
3034 */
3035 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
3036 val32 &= ~(BIT(0) | BIT(1));
3037 val32 |= BIT(1);
3038 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);
3039
3040 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
3041 val32 &= ~0x300033;
3042 val32 |= 0x200022;
3043 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);
3044
3045 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
3046 val32 &= 0xff000000;
3047 val32 |= 0x45000000;
3048 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
3049
3050 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
3051 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
3052 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
3053 OFDM_RF_PATH_TX_B);
3054 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
3055
3056 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
3057 val32 &= ~(BIT(4) | BIT(5));
3058 val32 |= BIT(4);
3059 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);
3060
3061 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
3062 val32 &= ~(BIT(27) | BIT(26));
3063 val32 |= BIT(27);
3064 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);
3065
3066 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
3067 val32 &= ~(BIT(27) | BIT(26));
3068 val32 |= BIT(27);
3069 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);
3070
3071 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
3072 val32 &= ~(BIT(27) | BIT(26));
3073 val32 |= BIT(27);
3074 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);
3075
3076 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
3077 val32 &= ~(BIT(27) | BIT(26));
3078 val32 |= BIT(27);
3079 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);
3080
3081 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
3082 val32 &= ~(BIT(27) | BIT(26));
3083 val32 |= BIT(27);
3084 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);
3085 }
3086
3087 if (priv->rtlchip == 0x8723b)
3088 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8723bu_table);
3089 else if (priv->hi_pa)
3090 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);
3091 else
3092 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);
3093
3094 if ((priv->rtlchip == 0x8723a || priv->rtlchip == 0x8723b) &&
3095 priv->efuse_wifi.efuse8723.version >= 0x01) {
3096 val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL);
3097
3098 val8 = priv->efuse_wifi.efuse8723.xtal_k & 0x3f;
3099 val32 &= 0xff000fff;
3100 val32 |= ((val8 | (val8 << 6)) << 12);
3101
3102 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32);
3103 }
3104
3105 ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;
3106 ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);
3107 ldohci12 = 0x57;
3108 lpldo = 1;
3109 val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15;
3110
3111 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);
3112
3113 return 0;
3114 }
3115
3116 static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
3117 struct rtl8xxxu_rfregval *array,
3118 enum rtl8xxxu_rfpath path)
3119 {
3120 int i, ret;
3121 u8 reg;
3122 u32 val;
3123
3124 for (i = 0; ; i++) {
3125 reg = array[i].reg;
3126 val = array[i].val;
3127
3128 if (reg == 0xff && val == 0xffffffff)
3129 break;
3130
3131 switch (reg) {
3132 case 0xfe:
3133 msleep(50);
3134 continue;
3135 case 0xfd:
3136 mdelay(5);
3137 continue;
3138 case 0xfc:
3139 mdelay(1);
3140 continue;
3141 case 0xfb:
3142 udelay(50);
3143 continue;
3144 case 0xfa:
3145 udelay(5);
3146 continue;
3147 case 0xf9:
3148 udelay(1);
3149 continue;
3150 }
3151
3152 ret = rtl8xxxu_write_rfreg(priv, path, reg, val);
3153 if (ret) {
3154 dev_warn(&priv->udev->dev,
3155 "Failed to initialize RF\n");
3156 return -EAGAIN;
3157 }
3158 udelay(1);
3159 }
3160
3161 return 0;
3162 }
3163
3164 static int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
3165 struct rtl8xxxu_rfregval *table,
3166 enum rtl8xxxu_rfpath path)
3167 {
3168 u32 val32;
3169 u16 val16, rfsi_rfenv;
3170 u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;
3171
3172 switch (path) {
3173 case RF_A:
3174 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;
3175 reg_int_oe = REG_FPGA0_XA_RF_INT_OE;
3176 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;
3177 break;
3178 case RF_B:
3179 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;
3180 reg_int_oe = REG_FPGA0_XB_RF_INT_OE;
3181 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;
3182 break;
3183 default:
3184 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",
3185 __func__, path + 'A');
3186 return -EINVAL;
3187 }
3188 /* For path B, use XB */
3189 rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);
3190 rfsi_rfenv &= FPGA0_RF_RFENV;
3191
3192 /*
3193 * These two we might be able to optimize into one
3194 */
3195 val32 = rtl8xxxu_read32(priv, reg_int_oe);
3196 val32 |= BIT(20); /* 0x10 << 16 */
3197 rtl8xxxu_write32(priv, reg_int_oe, val32);
3198 udelay(1);
3199
3200 val32 = rtl8xxxu_read32(priv, reg_int_oe);
3201 val32 |= BIT(4);
3202 rtl8xxxu_write32(priv, reg_int_oe, val32);
3203 udelay(1);
3204
3205 /*
3206 * These two we might be able to optimize into one
3207 */
3208 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
3209 val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;
3210 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
3211 udelay(1);
3212
3213 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
3214 val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;
3215 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
3216 udelay(1);
3217
3218 rtl8xxxu_init_rf_regs(priv, table, path);
3219
3220 /* For path B, use XB */
3221 val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);
3222 val16 &= ~FPGA0_RF_RFENV;
3223 val16 |= rfsi_rfenv;
3224 rtl8xxxu_write16(priv, reg_sw_ctrl, val16);
3225
3226 return 0;
3227 }
3228
3229 static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)
3230 {
3231 int ret = -EBUSY;
3232 int count = 0;
3233 u32 value;
3234
3235 value = LLT_OP_WRITE | address << 8 | data;
3236
3237 rtl8xxxu_write32(priv, REG_LLT_INIT, value);
3238
3239 do {
3240 value = rtl8xxxu_read32(priv, REG_LLT_INIT);
3241 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {
3242 ret = 0;
3243 break;
3244 }
3245 } while (count++ < 20);
3246
3247 return ret;
3248 }
3249
3250 static int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
3251 {
3252 int ret;
3253 int i;
3254
3255 for (i = 0; i < last_tx_page; i++) {
3256 ret = rtl8xxxu_llt_write(priv, i, i + 1);
3257 if (ret)
3258 goto exit;
3259 }
3260
3261 ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);
3262 if (ret)
3263 goto exit;
3264
3265 /* Mark remaining pages as a ring buffer */
3266 for (i = last_tx_page + 1; i < 0xff; i++) {
3267 ret = rtl8xxxu_llt_write(priv, i, (i + 1));
3268 if (ret)
3269 goto exit;
3270 }
3271
3272 /* Let last entry point to the start entry of ring buffer */
3273 ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1);
3274 if (ret)
3275 goto exit;
3276
3277 exit:
3278 return ret;
3279 }
3280
3281 static int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
3282 {
3283 u32 val32;
3284 int ret = 0;
3285 int i;
3286
3287 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
3288 val32 |= AUTO_LLT_INIT_LLT;
3289 rtl8xxxu_write32(priv, REG_AUTO_LLT, val32);
3290
3291 for (i = 500; i; i--) {
3292 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
3293 if (!(val32 & AUTO_LLT_INIT_LLT))
3294 break;
3295 usleep_range(2, 4);
3296 }
3297
3298 if (!i) {
3299 ret = -EBUSY;
3300 dev_warn(&priv->udev->dev, "LLT table init failed\n");
3301 }
3302
3303 return ret;
3304 }
3305
3306 static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
3307 {
3308 u16 val16, hi, lo;
3309 u16 hiq, mgq, bkq, beq, viq, voq;
3310 int hip, mgp, bkp, bep, vip, vop;
3311 int ret = 0;
3312
3313 switch (priv->ep_tx_count) {
3314 case 1:
3315 if (priv->ep_tx_high_queue) {
3316 hi = TRXDMA_QUEUE_HIGH;
3317 } else if (priv->ep_tx_low_queue) {
3318 hi = TRXDMA_QUEUE_LOW;
3319 } else if (priv->ep_tx_normal_queue) {
3320 hi = TRXDMA_QUEUE_NORMAL;
3321 } else {
3322 hi = 0;
3323 ret = -EINVAL;
3324 }
3325
3326 hiq = hi;
3327 mgq = hi;
3328 bkq = hi;
3329 beq = hi;
3330 viq = hi;
3331 voq = hi;
3332
3333 hip = 0;
3334 mgp = 0;
3335 bkp = 0;
3336 bep = 0;
3337 vip = 0;
3338 vop = 0;
3339 break;
3340 case 2:
3341 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {
3342 hi = TRXDMA_QUEUE_HIGH;
3343 lo = TRXDMA_QUEUE_LOW;
3344 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {
3345 hi = TRXDMA_QUEUE_NORMAL;
3346 lo = TRXDMA_QUEUE_LOW;
3347 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {
3348 hi = TRXDMA_QUEUE_HIGH;
3349 lo = TRXDMA_QUEUE_NORMAL;
3350 } else {
3351 ret = -EINVAL;
3352 hi = 0;
3353 lo = 0;
3354 }
3355
3356 hiq = hi;
3357 mgq = hi;
3358 bkq = lo;
3359 beq = lo;
3360 viq = hi;
3361 voq = hi;
3362
3363 hip = 0;
3364 mgp = 0;
3365 bkp = 1;
3366 bep = 1;
3367 vip = 0;
3368 vop = 0;
3369 break;
3370 case 3:
3371 beq = TRXDMA_QUEUE_LOW;
3372 bkq = TRXDMA_QUEUE_LOW;
3373 viq = TRXDMA_QUEUE_NORMAL;
3374 voq = TRXDMA_QUEUE_HIGH;
3375 mgq = TRXDMA_QUEUE_HIGH;
3376 hiq = TRXDMA_QUEUE_HIGH;
3377
3378 hip = hiq ^ 3;
3379 mgp = mgq ^ 3;
3380 bkp = bkq ^ 3;
3381 bep = beq ^ 3;
3382 vip = viq ^ 3;
3383 vop = viq ^ 3;
3384 break;
3385 default:
3386 ret = -EINVAL;
3387 }
3388
3389 /*
3390 * None of the vendor drivers are configuring the beacon
3391 * queue here .... why?
3392 */
3393 if (!ret) {
3394 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
3395 val16 &= 0x7;
3396 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
3397 (viq << TRXDMA_CTRL_VIQ_SHIFT) |
3398 (beq << TRXDMA_CTRL_BEQ_SHIFT) |
3399 (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
3400 (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
3401 (hiq << TRXDMA_CTRL_HIQ_SHIFT);
3402 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
3403
3404 priv->pipe_out[TXDESC_QUEUE_VO] =
3405 usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
3406 priv->pipe_out[TXDESC_QUEUE_VI] =
3407 usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);
3408 priv->pipe_out[TXDESC_QUEUE_BE] =
3409 usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);
3410 priv->pipe_out[TXDESC_QUEUE_BK] =
3411 usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);
3412 priv->pipe_out[TXDESC_QUEUE_BEACON] =
3413 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
3414 priv->pipe_out[TXDESC_QUEUE_MGNT] =
3415 usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);
3416 priv->pipe_out[TXDESC_QUEUE_HIGH] =
3417 usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);
3418 priv->pipe_out[TXDESC_QUEUE_CMD] =
3419 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
3420 }
3421
3422 return ret;
3423 }
3424
3425 static void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv,
3426 bool iqk_ok, int result[][8],
3427 int candidate, bool tx_only)
3428 {
3429 u32 oldval, x, tx0_a, reg;
3430 int y, tx0_c;
3431 u32 val32;
3432
3433 if (!iqk_ok)
3434 return;
3435
3436 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3437 oldval = val32 >> 22;
3438
3439 x = result[candidate][0];
3440 if ((x & 0x00000200) != 0)
3441 x = x | 0xfffffc00;
3442 tx0_a = (x * oldval) >> 8;
3443
3444 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3445 val32 &= ~0x3ff;
3446 val32 |= tx0_a;
3447 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
3448
3449 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3450 val32 &= ~BIT(31);
3451 if ((x * oldval >> 7) & 0x1)
3452 val32 |= BIT(31);
3453 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3454
3455 y = result[candidate][1];
3456 if ((y & 0x00000200) != 0)
3457 y = y | 0xfffffc00;
3458 tx0_c = (y * oldval) >> 8;
3459
3460 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
3461 val32 &= ~0xf0000000;
3462 val32 |= (((tx0_c & 0x3c0) >> 6) << 28);
3463 rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);
3464
3465 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3466 val32 &= ~0x003f0000;
3467 val32 |= ((tx0_c & 0x3f) << 16);
3468 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
3469
3470 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3471 val32 &= ~BIT(29);
3472 if ((y * oldval >> 7) & 0x1)
3473 val32 |= BIT(29);
3474 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3475
3476 if (tx_only) {
3477 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
3478 return;
3479 }
3480
3481 reg = result[candidate][2];
3482
3483 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
3484 val32 &= ~0x3ff;
3485 val32 |= (reg & 0x3ff);
3486 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
3487
3488 reg = result[candidate][3] & 0x3F;
3489
3490 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
3491 val32 &= ~0xfc00;
3492 val32 |= ((reg << 10) & 0xfc00);
3493 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
3494
3495 reg = (result[candidate][3] >> 6) & 0xF;
3496
3497 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
3498 val32 &= ~0xf0000000;
3499 val32 |= (reg << 28);
3500 rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);
3501 }
3502
3503 static void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv,
3504 bool iqk_ok, int result[][8],
3505 int candidate, bool tx_only)
3506 {
3507 u32 oldval, x, tx1_a, reg;
3508 int y, tx1_c;
3509 u32 val32;
3510
3511 if (!iqk_ok)
3512 return;
3513
3514 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3515 oldval = val32 >> 22;
3516
3517 x = result[candidate][4];
3518 if ((x & 0x00000200) != 0)
3519 x = x | 0xfffffc00;
3520 tx1_a = (x * oldval) >> 8;
3521
3522 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3523 val32 &= ~0x3ff;
3524 val32 |= tx1_a;
3525 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
3526
3527 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3528 val32 &= ~BIT(27);
3529 if ((x * oldval >> 7) & 0x1)
3530 val32 |= BIT(27);
3531 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3532
3533 y = result[candidate][5];
3534 if ((y & 0x00000200) != 0)
3535 y = y | 0xfffffc00;
3536 tx1_c = (y * oldval) >> 8;
3537
3538 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
3539 val32 &= ~0xf0000000;
3540 val32 |= (((tx1_c & 0x3c0) >> 6) << 28);
3541 rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);
3542
3543 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3544 val32 &= ~0x003f0000;
3545 val32 |= ((tx1_c & 0x3f) << 16);
3546 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
3547
3548 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3549 val32 &= ~BIT(25);
3550 if ((y * oldval >> 7) & 0x1)
3551 val32 |= BIT(25);
3552 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3553
3554 if (tx_only) {
3555 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
3556 return;
3557 }
3558
3559 reg = result[candidate][6];
3560
3561 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
3562 val32 &= ~0x3ff;
3563 val32 |= (reg & 0x3ff);
3564 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
3565
3566 reg = result[candidate][7] & 0x3f;
3567
3568 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
3569 val32 &= ~0xfc00;
3570 val32 |= ((reg << 10) & 0xfc00);
3571 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
3572
3573 reg = (result[candidate][7] >> 6) & 0xf;
3574
3575 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE);
3576 val32 &= ~0x0000f000;
3577 val32 |= (reg << 12);
3578 rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32);
3579 }
3580
3581 #define MAX_TOLERANCE 5
3582
3583 static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
3584 int result[][8], int c1, int c2)
3585 {
3586 u32 i, j, diff, simubitmap, bound = 0;
3587 int candidate[2] = {-1, -1}; /* for path A and path B */
3588 bool retval = true;
3589
3590 if (priv->tx_paths > 1)
3591 bound = 8;
3592 else
3593 bound = 4;
3594
3595 simubitmap = 0;
3596
3597 for (i = 0; i < bound; i++) {
3598 diff = (result[c1][i] > result[c2][i]) ?
3599 (result[c1][i] - result[c2][i]) :
3600 (result[c2][i] - result[c1][i]);
3601 if (diff > MAX_TOLERANCE) {
3602 if ((i == 2 || i == 6) && !simubitmap) {
3603 if (result[c1][i] + result[c1][i + 1] == 0)
3604 candidate[(i / 4)] = c2;
3605 else if (result[c2][i] + result[c2][i + 1] == 0)
3606 candidate[(i / 4)] = c1;
3607 else
3608 simubitmap = simubitmap | (1 << i);
3609 } else {
3610 simubitmap = simubitmap | (1 << i);
3611 }
3612 }
3613 }
3614
3615 if (simubitmap == 0) {
3616 for (i = 0; i < (bound / 4); i++) {
3617 if (candidate[i] >= 0) {
3618 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
3619 result[3][j] = result[candidate[i]][j];
3620 retval = false;
3621 }
3622 }
3623 return retval;
3624 } else if (!(simubitmap & 0x0f)) {
3625 /* path A OK */
3626 for (i = 0; i < 4; i++)
3627 result[3][i] = result[c1][i];
3628 } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {
3629 /* path B OK */
3630 for (i = 4; i < 8; i++)
3631 result[3][i] = result[c1][i];
3632 }
3633
3634 return false;
3635 }
3636
3637 static bool rtl8723bu_simularity_compare(struct rtl8xxxu_priv *priv,
3638 int result[][8], int c1, int c2)
3639 {
3640 u32 i, j, diff, simubitmap, bound = 0;
3641 int candidate[2] = {-1, -1}; /* for path A and path B */
3642 int tmp1, tmp2;
3643 bool retval = true;
3644
3645 if (priv->tx_paths > 1)
3646 bound = 8;
3647 else
3648 bound = 4;
3649
3650 simubitmap = 0;
3651
3652 for (i = 0; i < bound; i++) {
3653 if (i & 1) {
3654 if ((result[c1][i] & 0x00000200))
3655 tmp1 = result[c1][i] | 0xfffffc00;
3656 else
3657 tmp1 = result[c1][i];
3658
3659 if ((result[c2][i]& 0x00000200))
3660 tmp2 = result[c2][i] | 0xfffffc00;
3661 else
3662 tmp2 = result[c2][i];
3663 } else {
3664 tmp1 = result[c1][i];
3665 tmp2 = result[c2][i];
3666 }
3667
3668 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
3669
3670 if (diff > MAX_TOLERANCE) {
3671 if ((i == 2 || i == 6) && !simubitmap) {
3672 if (result[c1][i] + result[c1][i + 1] == 0)
3673 candidate[(i / 4)] = c2;
3674 else if (result[c2][i] + result[c2][i + 1] == 0)
3675 candidate[(i / 4)] = c1;
3676 else
3677 simubitmap = simubitmap | (1 << i);
3678 } else {
3679 simubitmap = simubitmap | (1 << i);
3680 }
3681 }
3682 }
3683
3684 if (simubitmap == 0) {
3685 for (i = 0; i < (bound / 4); i++) {
3686 if (candidate[i] >= 0) {
3687 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
3688 result[3][j] = result[candidate[i]][j];
3689 retval = false;
3690 }
3691 }
3692 return retval;
3693 } else {
3694 if (!(simubitmap & 0x03)) {
3695 /* path A TX OK */
3696 for (i = 0; i < 2; i++)
3697 result[3][i] = result[c1][i];
3698 }
3699
3700 if (!(simubitmap & 0x0c)) {
3701 /* path A RX OK */
3702 for (i = 2; i < 4; i++)
3703 result[3][i] = result[c1][i];
3704 }
3705
3706 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
3707 /* path B RX OK */
3708 for (i = 4; i < 6; i++)
3709 result[3][i] = result[c1][i];
3710 }
3711
3712 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
3713 /* path B RX OK */
3714 for (i = 6; i < 8; i++)
3715 result[3][i] = result[c1][i];
3716 }
3717 }
3718
3719 return false;
3720 }
3721
3722 static void
3723 rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)
3724 {
3725 int i;
3726
3727 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3728 backup[i] = rtl8xxxu_read8(priv, reg[i]);
3729
3730 backup[i] = rtl8xxxu_read32(priv, reg[i]);
3731 }
3732
3733 static void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
3734 const u32 *reg, u32 *backup)
3735 {
3736 int i;
3737
3738 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3739 rtl8xxxu_write8(priv, reg[i], backup[i]);
3740
3741 rtl8xxxu_write32(priv, reg[i], backup[i]);
3742 }
3743
3744 static void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3745 u32 *backup, int count)
3746 {
3747 int i;
3748
3749 for (i = 0; i < count; i++)
3750 backup[i] = rtl8xxxu_read32(priv, regs[i]);
3751 }
3752
3753 static void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3754 u32 *backup, int count)
3755 {
3756 int i;
3757
3758 for (i = 0; i < count; i++)
3759 rtl8xxxu_write32(priv, regs[i], backup[i]);
3760 }
3761
3762
3763 static void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
3764 bool path_a_on)
3765 {
3766 u32 path_on;
3767 int i;
3768
3769 if (priv->tx_paths == 1) {
3770 path_on = priv->fops->adda_1t_path_on;
3771 rtl8xxxu_write32(priv, regs[0], priv->fops->adda_1t_init);
3772 } else {
3773 path_on = path_a_on ? priv->fops->adda_2t_path_on_a :
3774 priv->fops->adda_2t_path_on_b;
3775
3776 rtl8xxxu_write32(priv, regs[0], path_on);
3777 }
3778
3779 for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)
3780 rtl8xxxu_write32(priv, regs[i], path_on);
3781 }
3782
3783 static void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
3784 const u32 *regs, u32 *backup)
3785 {
3786 int i = 0;
3787
3788 rtl8xxxu_write8(priv, regs[i], 0x3f);
3789
3790 for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)
3791 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));
3792
3793 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));
3794 }
3795
3796 static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)
3797 {
3798 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;
3799 int result = 0;
3800
3801 /* path-A IQK setting */
3802 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);
3803 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);
3804 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);
3805
3806 val32 = (priv->rf_paths > 1) ? 0x28160202 :
3807 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
3808 0x28160502;
3809 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);
3810
3811 /* path-B IQK setting */
3812 if (priv->rf_paths > 1) {
3813 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);
3814 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);
3815 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);
3816 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);
3817 }
3818
3819 /* LO calibration setting */
3820 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);
3821
3822 /* One shot, path A LOK & IQK */
3823 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
3824 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
3825
3826 mdelay(1);
3827
3828 /* Check failed */
3829 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3830 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
3831 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
3832 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
3833
3834 if (!(reg_eac & BIT(28)) &&
3835 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
3836 ((reg_e9c & 0x03ff0000) != 0x00420000))
3837 result |= 0x01;
3838 else /* If TX not OK, ignore RX */
3839 goto out;
3840
3841 /* If TX is OK, check whether RX is OK */
3842 if (!(reg_eac & BIT(27)) &&
3843 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
3844 ((reg_eac & 0x03ff0000) != 0x00360000))
3845 result |= 0x02;
3846 else
3847 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
3848 __func__);
3849 out:
3850 return result;
3851 }
3852
3853 static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)
3854 {
3855 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3856 int result = 0;
3857
3858 /* One shot, path B LOK & IQK */
3859 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
3860 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
3861
3862 mdelay(1);
3863
3864 /* Check failed */
3865 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3866 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3867 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3868 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3869 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3870
3871 if (!(reg_eac & BIT(31)) &&
3872 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
3873 ((reg_ebc & 0x03ff0000) != 0x00420000))
3874 result |= 0x01;
3875 else
3876 goto out;
3877
3878 if (!(reg_eac & BIT(30)) &&
3879 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
3880 (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
3881 result |= 0x02;
3882 else
3883 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
3884 __func__);
3885 out:
3886 return result;
3887 }
3888
3889 static int rtl8723bu_iqk_path_a(struct rtl8xxxu_priv *priv)
3890 {
3891 u32 reg_eac, reg_e94, reg_e9c, path_sel, val32;
3892 int result = 0;
3893
3894 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
3895
3896 /*
3897 * Leave IQK mode
3898 */
3899 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
3900 val32 &= 0x000000ff;
3901 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
3902
3903 /*
3904 * Enable path A PA in TX IQK mode
3905 */
3906 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
3907 val32 |= 0x80000;
3908 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
3909 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000);
3910 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0003f);
3911 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xc7f87);
3912
3913 /*
3914 * Tx IQK setting
3915 */
3916 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
3917 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
3918
3919 /* path-A IQK setting */
3920 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
3921 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
3922 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
3923 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
3924
3925 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ea);
3926 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000);
3927 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
3928 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
3929
3930 /* LO calibration setting */
3931 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911);
3932
3933 /*
3934 * Enter IQK mode
3935 */
3936 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
3937 val32 &= 0x000000ff;
3938 val32 |= 0x80800000;
3939 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
3940
3941 /*
3942 * The vendor driver indicates the USB module is always using
3943 * S0S1 path 1 for the 8723bu. This may be different for 8192eu
3944 */
3945 if (priv->rf_paths > 1)
3946 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
3947 else
3948 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
3949
3950 /*
3951 * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
3952 * No trace of this in the 8192eu or 8188eu vendor drivers.
3953 */
3954 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
3955
3956 /* One shot, path A LOK & IQK */
3957 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
3958 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
3959
3960 mdelay(1);
3961
3962 /* Restore Ant Path */
3963 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
3964 #ifdef RTL8723BU_BT
3965 /* GNT_BT = 1 */
3966 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
3967 #endif
3968
3969 /*
3970 * Leave IQK mode
3971 */
3972 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
3973 val32 &= 0x000000ff;
3974 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
3975
3976 /* Check failed */
3977 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3978 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
3979 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
3980
3981 val32 = (reg_e9c >> 16) & 0x3ff;
3982 if (val32 & 0x200)
3983 val32 = 0x400 - val32;
3984
3985 if (!(reg_eac & BIT(28)) &&
3986 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
3987 ((reg_e9c & 0x03ff0000) != 0x00420000) &&
3988 ((reg_e94 & 0x03ff0000) < 0x01100000) &&
3989 ((reg_e94 & 0x03ff0000) > 0x00f00000) &&
3990 val32 < 0xf)
3991 result |= 0x01;
3992 else /* If TX not OK, ignore RX */
3993 goto out;
3994
3995 out:
3996 return result;
3997 }
3998
3999 static int rtl8723bu_rx_iqk_path_a(struct rtl8xxxu_priv *priv)
4000 {
4001 u32 reg_ea4, reg_eac, reg_e94, reg_e9c, path_sel, val32;
4002 int result = 0;
4003
4004 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
4005
4006 /*
4007 * Leave IQK mode
4008 */
4009 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4010 val32 &= 0x000000ff;
4011 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4012
4013 /*
4014 * Enable path A PA in TX IQK mode
4015 */
4016 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4017 val32 |= 0x80000;
4018 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4019 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
4020 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4021 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7);
4022
4023 /*
4024 * Tx IQK setting
4025 */
4026 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
4027 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4028
4029 /* path-A IQK setting */
4030 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
4031 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
4032 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
4033 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
4034
4035 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160ff0);
4036 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000);
4037 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
4038 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
4039
4040 /* LO calibration setting */
4041 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);
4042
4043 /*
4044 * Enter IQK mode
4045 */
4046 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4047 val32 &= 0x000000ff;
4048 val32 |= 0x80800000;
4049 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4050
4051 /*
4052 * The vendor driver indicates the USB module is always using
4053 * S0S1 path 1 for the 8723bu. This may be different for 8192eu
4054 */
4055 if (priv->rf_paths > 1)
4056 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
4057 else
4058 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
4059
4060 /*
4061 * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
4062 * No trace of this in the 8192eu or 8188eu vendor drivers.
4063 */
4064 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
4065
4066 /* One shot, path A LOK & IQK */
4067 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4068 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4069
4070 mdelay(1);
4071
4072 /* Restore Ant Path */
4073 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
4074 #ifdef RTL8723BU_BT
4075 /* GNT_BT = 1 */
4076 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
4077 #endif
4078
4079 /*
4080 * Leave IQK mode
4081 */
4082 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4083 val32 &= 0x000000ff;
4084 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4085
4086 /* Check failed */
4087 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4088 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
4089 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
4090
4091 val32 = (reg_e9c >> 16) & 0x3ff;
4092 if (val32 & 0x200)
4093 val32 = 0x400 - val32;
4094
4095 if (!(reg_eac & BIT(28)) &&
4096 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
4097 ((reg_e9c & 0x03ff0000) != 0x00420000) &&
4098 ((reg_e94 & 0x03ff0000) < 0x01100000) &&
4099 ((reg_e94 & 0x03ff0000) > 0x00f00000) &&
4100 val32 < 0xf)
4101 result |= 0x01;
4102 else /* If TX not OK, ignore RX */
4103 goto out;
4104
4105 val32 = 0x80007c00 | (reg_e94 &0x3ff0000) |
4106 ((reg_e9c & 0x3ff0000) >> 16);
4107 rtl8xxxu_write32(priv, REG_TX_IQK, val32);
4108
4109 /*
4110 * Modify RX IQK mode
4111 */
4112 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4113 val32 &= 0x000000ff;
4114 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4115 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4116 val32 |= 0x80000;
4117 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4118 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
4119 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4120 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7d77);
4121
4122 /*
4123 * PA, PAD setting
4124 */
4125 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0xf80);
4126 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, 0x4021f);
4127
4128 /*
4129 * RX IQK setting
4130 */
4131 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4132
4133 /* path-A IQK setting */
4134 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
4135 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c);
4136 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
4137 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
4138
4139 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82110000);
4140 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x2816001f);
4141 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
4142 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
4143
4144 /* LO calibration setting */
4145 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a8d1);
4146
4147 /*
4148 * Enter IQK mode
4149 */
4150 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4151 val32 &= 0x000000ff;
4152 val32 |= 0x80800000;
4153 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4154
4155 if (priv->rf_paths > 1)
4156 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
4157 else
4158 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
4159
4160 /*
4161 * Disable BT
4162 */
4163 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
4164
4165 /* One shot, path A LOK & IQK */
4166 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4167 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4168
4169 mdelay(1);
4170
4171 /* Restore Ant Path */
4172 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
4173 #ifdef RTL8723BU_BT
4174 /* GNT_BT = 1 */
4175 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
4176 #endif
4177
4178 /*
4179 * Leave IQK mode
4180 */
4181 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4182 val32 &= 0x000000ff;
4183 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4184
4185 /* Check failed */
4186 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4187 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
4188
4189 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x780);
4190
4191 val32 = (reg_eac >> 16) & 0x3ff;
4192 if (val32 & 0x200)
4193 val32 = 0x400 - val32;
4194
4195 if (!(reg_eac & BIT(27)) &&
4196 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
4197 ((reg_eac & 0x03ff0000) != 0x00360000) &&
4198 ((reg_ea4 & 0x03ff0000) < 0x01100000) &&
4199 ((reg_ea4 & 0x03ff0000) > 0x00f00000) &&
4200 val32 < 0xf)
4201 result |= 0x02;
4202 else /* If TX not OK, ignore RX */
4203 goto out;
4204 out:
4205 return result;
4206 }
4207
4208 #ifdef RTL8723BU_PATH_B
4209 static int rtl8723bu_iqk_path_b(struct rtl8xxxu_priv *priv)
4210 {
4211 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc, path_sel;
4212 int result = 0;
4213
4214 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
4215
4216 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4217 val32 &= 0x000000ff;
4218 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4219
4220 /* One shot, path B LOK & IQK */
4221 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
4222 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
4223
4224 mdelay(1);
4225
4226 /* Check failed */
4227 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4228 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4229 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4230 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
4231 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
4232
4233 if (!(reg_eac & BIT(31)) &&
4234 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
4235 ((reg_ebc & 0x03ff0000) != 0x00420000))
4236 result |= 0x01;
4237 else
4238 goto out;
4239
4240 if (!(reg_eac & BIT(30)) &&
4241 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
4242 (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
4243 result |= 0x02;
4244 else
4245 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
4246 __func__);
4247 out:
4248 return result;
4249 }
4250 #endif
4251
4252 static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
4253 int result[][8], int t)
4254 {
4255 struct device *dev = &priv->udev->dev;
4256 u32 i, val32;
4257 int path_a_ok, path_b_ok;
4258 int retry = 2;
4259 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
4260 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
4261 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
4262 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
4263 REG_TX_OFDM_BBON, REG_TX_TO_RX,
4264 REG_TX_TO_TX, REG_RX_CCK,
4265 REG_RX_OFDM, REG_RX_WAIT_RIFS,
4266 REG_RX_TO_RX, REG_STANDBY,
4267 REG_SLEEP, REG_PMPD_ANAEN
4268 };
4269 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
4270 REG_TXPAUSE, REG_BEACON_CTRL,
4271 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
4272 };
4273 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
4274 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
4275 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
4276 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
4277 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
4278 };
4279
4280 /*
4281 * Note: IQ calibration must be performed after loading
4282 * PHY_REG.txt , and radio_a, radio_b.txt
4283 */
4284
4285 if (t == 0) {
4286 /* Save ADDA parameters, turn Path A ADDA on */
4287 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
4288 RTL8XXXU_ADDA_REGS);
4289 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4290 rtl8xxxu_save_regs(priv, iqk_bb_regs,
4291 priv->bb_backup, RTL8XXXU_BB_REGS);
4292 }
4293
4294 rtl8xxxu_path_adda_on(priv, adda_regs, true);
4295
4296 if (t == 0) {
4297 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
4298 if (val32 & FPGA0_HSSI_PARM1_PI)
4299 priv->pi_enabled = 1;
4300 }
4301
4302 if (!priv->pi_enabled) {
4303 /* Switch BB to PI mode to do IQ Calibration. */
4304 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
4305 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
4306 }
4307
4308 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4309 val32 &= ~FPGA_RF_MODE_CCK;
4310 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4311
4312 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
4313 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
4314 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
4315
4316 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
4317 val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
4318 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
4319
4320 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
4321 val32 &= ~BIT(10);
4322 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
4323 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
4324 val32 &= ~BIT(10);
4325 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
4326
4327 if (priv->tx_paths > 1) {
4328 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
4329 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
4330 }
4331
4332 /* MAC settings */
4333 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
4334
4335 /* Page B init */
4336 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);
4337
4338 if (priv->tx_paths > 1)
4339 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);
4340
4341 /* IQ calibration setting */
4342 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
4343 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
4344 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4345
4346 for (i = 0; i < retry; i++) {
4347 path_a_ok = rtl8xxxu_iqk_path_a(priv);
4348 if (path_a_ok == 0x03) {
4349 val32 = rtl8xxxu_read32(priv,
4350 REG_TX_POWER_BEFORE_IQK_A);
4351 result[t][0] = (val32 >> 16) & 0x3ff;
4352 val32 = rtl8xxxu_read32(priv,
4353 REG_TX_POWER_AFTER_IQK_A);
4354 result[t][1] = (val32 >> 16) & 0x3ff;
4355 val32 = rtl8xxxu_read32(priv,
4356 REG_RX_POWER_BEFORE_IQK_A_2);
4357 result[t][2] = (val32 >> 16) & 0x3ff;
4358 val32 = rtl8xxxu_read32(priv,
4359 REG_RX_POWER_AFTER_IQK_A_2);
4360 result[t][3] = (val32 >> 16) & 0x3ff;
4361 break;
4362 } else if (i == (retry - 1) && path_a_ok == 0x01) {
4363 /* TX IQK OK */
4364 dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",
4365 __func__);
4366
4367 val32 = rtl8xxxu_read32(priv,
4368 REG_TX_POWER_BEFORE_IQK_A);
4369 result[t][0] = (val32 >> 16) & 0x3ff;
4370 val32 = rtl8xxxu_read32(priv,
4371 REG_TX_POWER_AFTER_IQK_A);
4372 result[t][1] = (val32 >> 16) & 0x3ff;
4373 }
4374 }
4375
4376 if (!path_a_ok)
4377 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
4378
4379 if (priv->tx_paths > 1) {
4380 /*
4381 * Path A into standby
4382 */
4383 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
4384 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
4385 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
4386
4387 /* Turn Path B ADDA on */
4388 rtl8xxxu_path_adda_on(priv, adda_regs, false);
4389
4390 for (i = 0; i < retry; i++) {
4391 path_b_ok = rtl8xxxu_iqk_path_b(priv);
4392 if (path_b_ok == 0x03) {
4393 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4394 result[t][4] = (val32 >> 16) & 0x3ff;
4395 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4396 result[t][5] = (val32 >> 16) & 0x3ff;
4397 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
4398 result[t][6] = (val32 >> 16) & 0x3ff;
4399 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
4400 result[t][7] = (val32 >> 16) & 0x3ff;
4401 break;
4402 } else if (i == (retry - 1) && path_b_ok == 0x01) {
4403 /* TX IQK OK */
4404 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4405 result[t][4] = (val32 >> 16) & 0x3ff;
4406 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4407 result[t][5] = (val32 >> 16) & 0x3ff;
4408 }
4409 }
4410
4411 if (!path_b_ok)
4412 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
4413 }
4414
4415 /* Back to BB mode, load original value */
4416 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
4417
4418 if (t) {
4419 if (!priv->pi_enabled) {
4420 /*
4421 * Switch back BB to SI mode after finishing
4422 * IQ Calibration
4423 */
4424 val32 = 0x01000000;
4425 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
4426 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
4427 }
4428
4429 /* Reload ADDA power saving parameters */
4430 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
4431 RTL8XXXU_ADDA_REGS);
4432
4433 /* Reload MAC parameters */
4434 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4435
4436 /* Reload BB parameters */
4437 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
4438 priv->bb_backup, RTL8XXXU_BB_REGS);
4439
4440 /* Restore RX initial gain */
4441 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
4442
4443 if (priv->tx_paths > 1) {
4444 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
4445 0x00032ed3);
4446 }
4447
4448 /* Load 0xe30 IQC default value */
4449 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
4450 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
4451 }
4452 }
4453
4454 static void rtl8723bu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
4455 int result[][8], int t)
4456 {
4457 struct device *dev = &priv->udev->dev;
4458 u32 i, val32;
4459 int path_a_ok /*, path_b_ok */;
4460 int retry = 2;
4461 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
4462 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
4463 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
4464 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
4465 REG_TX_OFDM_BBON, REG_TX_TO_RX,
4466 REG_TX_TO_TX, REG_RX_CCK,
4467 REG_RX_OFDM, REG_RX_WAIT_RIFS,
4468 REG_RX_TO_RX, REG_STANDBY,
4469 REG_SLEEP, REG_PMPD_ANAEN
4470 };
4471 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
4472 REG_TXPAUSE, REG_BEACON_CTRL,
4473 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
4474 };
4475 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
4476 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
4477 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
4478 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
4479 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
4480 };
4481 u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff;
4482 u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff;
4483
4484 /*
4485 * Note: IQ calibration must be performed after loading
4486 * PHY_REG.txt , and radio_a, radio_b.txt
4487 */
4488
4489 if (t == 0) {
4490 /* Save ADDA parameters, turn Path A ADDA on */
4491 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
4492 RTL8XXXU_ADDA_REGS);
4493 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4494 rtl8xxxu_save_regs(priv, iqk_bb_regs,
4495 priv->bb_backup, RTL8XXXU_BB_REGS);
4496 }
4497
4498 rtl8xxxu_path_adda_on(priv, adda_regs, true);
4499
4500 /* MAC settings */
4501 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
4502
4503 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
4504 val32 |= 0x0f000000;
4505 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
4506
4507 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
4508 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
4509 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
4510
4511 #ifdef RTL8723BU_PATH_B
4512 /* Set RF mode to standby Path B */
4513 if (priv->tx_paths > 1)
4514 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x10000);
4515 #endif
4516
4517 #if 0
4518 /* Page B init */
4519 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x0f600000);
4520
4521 if (priv->tx_paths > 1)
4522 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x0f600000);
4523 #endif
4524
4525 /*
4526 * RX IQ calibration setting for 8723B D cut large current issue
4527 * when leaving IPS
4528 */
4529 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4530 val32 &= 0x000000ff;
4531 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4532
4533 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4534 val32 |= 0x80000;
4535 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4536
4537 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
4538 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4539 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7);
4540
4541 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED);
4542 val32 |= 0x20;
4543 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32);
4544
4545 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_43, 0x60fbd);
4546
4547 for (i = 0; i < retry; i++) {
4548 path_a_ok = rtl8723bu_iqk_path_a(priv);
4549 if (path_a_ok == 0x01) {
4550 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4551 val32 &= 0x000000ff;
4552 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4553
4554 #if 0 /* Only needed in restore case, we may need this when going to suspend */
4555 priv->RFCalibrateInfo.TxLOK[RF_A] =
4556 rtl8xxxu_read_rfreg(priv, RF_A,
4557 RF6052_REG_TXM_IDAC);
4558 #endif
4559
4560 val32 = rtl8xxxu_read32(priv,
4561 REG_TX_POWER_BEFORE_IQK_A);
4562 result[t][0] = (val32 >> 16) & 0x3ff;
4563 val32 = rtl8xxxu_read32(priv,
4564 REG_TX_POWER_AFTER_IQK_A);
4565 result[t][1] = (val32 >> 16) & 0x3ff;
4566
4567 break;
4568 }
4569 }
4570
4571 if (!path_a_ok)
4572 dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__);
4573
4574 for (i = 0; i < retry; i++) {
4575 path_a_ok = rtl8723bu_rx_iqk_path_a(priv);
4576 if (path_a_ok == 0x03) {
4577 val32 = rtl8xxxu_read32(priv,
4578 REG_RX_POWER_BEFORE_IQK_A_2);
4579 result[t][2] = (val32 >> 16) & 0x3ff;
4580 val32 = rtl8xxxu_read32(priv,
4581 REG_RX_POWER_AFTER_IQK_A_2);
4582 result[t][3] = (val32 >> 16) & 0x3ff;
4583
4584 break;
4585 }
4586 }
4587
4588 if (!path_a_ok)
4589 dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__);
4590
4591 if (priv->tx_paths > 1) {
4592 #if 1
4593 dev_warn(dev, "%s: Path B not supported\n", __func__);
4594 #else
4595
4596 /*
4597 * Path A into standby
4598 */
4599 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4600 val32 &= 0x000000ff;
4601 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4602 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000);
4603
4604 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4605 val32 &= 0x000000ff;
4606 val32 |= 0x80800000;
4607 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4608
4609 /* Turn Path B ADDA on */
4610 rtl8xxxu_path_adda_on(priv, adda_regs, false);
4611
4612 for (i = 0; i < retry; i++) {
4613 path_b_ok = rtl8xxxu_iqk_path_b(priv);
4614 if (path_b_ok == 0x03) {
4615 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4616 result[t][4] = (val32 >> 16) & 0x3ff;
4617 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4618 result[t][5] = (val32 >> 16) & 0x3ff;
4619 break;
4620 }
4621 }
4622
4623 if (!path_b_ok)
4624 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
4625
4626 for (i = 0; i < retry; i++) {
4627 path_b_ok = rtl8723bu_rx_iqk_path_b(priv);
4628 if (path_a_ok == 0x03) {
4629 val32 = rtl8xxxu_read32(priv,
4630 REG_RX_POWER_BEFORE_IQK_B_2);
4631 result[t][6] = (val32 >> 16) & 0x3ff;
4632 val32 = rtl8xxxu_read32(priv,
4633 REG_RX_POWER_AFTER_IQK_B_2);
4634 result[t][7] = (val32 >> 16) & 0x3ff;
4635 break;
4636 }
4637 }
4638
4639 if (!path_b_ok)
4640 dev_dbg(dev, "%s: Path B RX IQK failed!\n", __func__);
4641 #endif
4642 }
4643
4644 /* Back to BB mode, load original value */
4645 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4646 val32 &= 0x000000ff;
4647 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4648
4649 if (t) {
4650 /* Reload ADDA power saving parameters */
4651 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
4652 RTL8XXXU_ADDA_REGS);
4653
4654 /* Reload MAC parameters */
4655 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4656
4657 /* Reload BB parameters */
4658 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
4659 priv->bb_backup, RTL8XXXU_BB_REGS);
4660
4661 /* Restore RX initial gain */
4662 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
4663 val32 &= 0xffffff00;
4664 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50);
4665 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc);
4666
4667 if (priv->tx_paths > 1) {
4668 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1);
4669 val32 &= 0xffffff00;
4670 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
4671 val32 | 0x50);
4672 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
4673 val32 | xb_agc);
4674 }
4675
4676 /* Load 0xe30 IQC default value */
4677 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
4678 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
4679 }
4680 }
4681
4682 static void rtl8xxxu_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start)
4683 {
4684 struct h2c_cmd h2c;
4685
4686 if (priv->fops->mbox_ext_width < 4)
4687 return;
4688
4689 memset(&h2c, 0, sizeof(struct h2c_cmd));
4690 h2c.bt_wlan_calibration.cmd = H2C_8723B_BT_WLAN_CALIBRATION;
4691 h2c.bt_wlan_calibration.data = start;
4692
4693 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_wlan_calibration));
4694 }
4695
4696 static void rtl8723au_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
4697 {
4698 struct device *dev = &priv->udev->dev;
4699 int result[4][8]; /* last is final result */
4700 int i, candidate;
4701 bool path_a_ok, path_b_ok;
4702 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
4703 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
4704 s32 reg_tmp = 0;
4705 bool simu;
4706
4707 rtl8xxxu_prepare_calibrate(priv, 1);
4708
4709 memset(result, 0, sizeof(result));
4710 candidate = -1;
4711
4712 path_a_ok = false;
4713 path_b_ok = false;
4714
4715 rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4716
4717 for (i = 0; i < 3; i++) {
4718 rtl8xxxu_phy_iqcalibrate(priv, result, i);
4719
4720 if (i == 1) {
4721 simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);
4722 if (simu) {
4723 candidate = 0;
4724 break;
4725 }
4726 }
4727
4728 if (i == 2) {
4729 simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);
4730 if (simu) {
4731 candidate = 0;
4732 break;
4733 }
4734
4735 simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);
4736 if (simu) {
4737 candidate = 1;
4738 } else {
4739 for (i = 0; i < 8; i++)
4740 reg_tmp += result[3][i];
4741
4742 if (reg_tmp)
4743 candidate = 3;
4744 else
4745 candidate = -1;
4746 }
4747 }
4748 }
4749
4750 for (i = 0; i < 4; i++) {
4751 reg_e94 = result[i][0];
4752 reg_e9c = result[i][1];
4753 reg_ea4 = result[i][2];
4754 reg_eac = result[i][3];
4755 reg_eb4 = result[i][4];
4756 reg_ebc = result[i][5];
4757 reg_ec4 = result[i][6];
4758 reg_ecc = result[i][7];
4759 }
4760
4761 if (candidate >= 0) {
4762 reg_e94 = result[candidate][0];
4763 priv->rege94 = reg_e94;
4764 reg_e9c = result[candidate][1];
4765 priv->rege9c = reg_e9c;
4766 reg_ea4 = result[candidate][2];
4767 reg_eac = result[candidate][3];
4768 reg_eb4 = result[candidate][4];
4769 priv->regeb4 = reg_eb4;
4770 reg_ebc = result[candidate][5];
4771 priv->regebc = reg_ebc;
4772 reg_ec4 = result[candidate][6];
4773 reg_ecc = result[candidate][7];
4774 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
4775 dev_dbg(dev,
4776 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
4777 "ecc=%x\n ", __func__, reg_e94, reg_e9c,
4778 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
4779 path_a_ok = true;
4780 path_b_ok = true;
4781 } else {
4782 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
4783 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
4784 }
4785
4786 if (reg_e94 && candidate >= 0)
4787 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
4788 candidate, (reg_ea4 == 0));
4789
4790 if (priv->tx_paths > 1 && reg_eb4)
4791 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
4792 candidate, (reg_ec4 == 0));
4793
4794 rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
4795 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
4796
4797 rtl8xxxu_prepare_calibrate(priv, 0);
4798 }
4799
4800 static void rtl8723bu_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
4801 {
4802 struct device *dev = &priv->udev->dev;
4803 int result[4][8]; /* last is final result */
4804 int i, candidate;
4805 bool path_a_ok, path_b_ok;
4806 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
4807 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
4808 u32 val32, bt_control;
4809 s32 reg_tmp = 0;
4810 bool simu;
4811
4812 rtl8xxxu_prepare_calibrate(priv, 1);
4813
4814 memset(result, 0, sizeof(result));
4815 candidate = -1;
4816
4817 path_a_ok = false;
4818 path_b_ok = false;
4819
4820 bt_control = rtl8xxxu_read32(priv, REG_BT_CONTROL_8723BU);
4821
4822 for (i = 0; i < 3; i++) {
4823 rtl8723bu_phy_iqcalibrate(priv, result, i);
4824
4825 if (i == 1) {
4826 simu = rtl8723bu_simularity_compare(priv, result, 0, 1);
4827 if (simu) {
4828 candidate = 0;
4829 break;
4830 }
4831 }
4832
4833 if (i == 2) {
4834 simu = rtl8723bu_simularity_compare(priv, result, 0, 2);
4835 if (simu) {
4836 candidate = 0;
4837 break;
4838 }
4839
4840 simu = rtl8723bu_simularity_compare(priv, result, 1, 2);
4841 if (simu) {
4842 candidate = 1;
4843 } else {
4844 for (i = 0; i < 8; i++)
4845 reg_tmp += result[3][i];
4846
4847 if (reg_tmp)
4848 candidate = 3;
4849 else
4850 candidate = -1;
4851 }
4852 }
4853 }
4854
4855 for (i = 0; i < 4; i++) {
4856 reg_e94 = result[i][0];
4857 reg_e9c = result[i][1];
4858 reg_ea4 = result[i][2];
4859 reg_eac = result[i][3];
4860 reg_eb4 = result[i][4];
4861 reg_ebc = result[i][5];
4862 reg_ec4 = result[i][6];
4863 reg_ecc = result[i][7];
4864 }
4865
4866 if (candidate >= 0) {
4867 reg_e94 = result[candidate][0];
4868 priv->rege94 = reg_e94;
4869 reg_e9c = result[candidate][1];
4870 priv->rege9c = reg_e9c;
4871 reg_ea4 = result[candidate][2];
4872 reg_eac = result[candidate][3];
4873 reg_eb4 = result[candidate][4];
4874 priv->regeb4 = reg_eb4;
4875 reg_ebc = result[candidate][5];
4876 priv->regebc = reg_ebc;
4877 reg_ec4 = result[candidate][6];
4878 reg_ecc = result[candidate][7];
4879 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
4880 dev_dbg(dev,
4881 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
4882 "ecc=%x\n ", __func__, reg_e94, reg_e9c,
4883 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
4884 path_a_ok = true;
4885 path_b_ok = true;
4886 } else {
4887 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
4888 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
4889 }
4890
4891 if (reg_e94 && candidate >= 0)
4892 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
4893 candidate, (reg_ea4 == 0));
4894
4895 if (priv->tx_paths > 1 && reg_eb4)
4896 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
4897 candidate, (reg_ec4 == 0));
4898
4899 rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
4900 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
4901
4902 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, bt_control);
4903
4904 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4905 val32 |= 0x80000;
4906 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4907 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x18000);
4908 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4909 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xe6177);
4910 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED);
4911 val32 |= 0x20;
4912 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32);
4913 rtl8xxxu_write_rfreg(priv, RF_A, 0x43, 0x300bd);
4914
4915 if (priv->rf_paths > 1) {
4916 dev_dbg(dev, "%s: beware 2T not yet supported\n", __func__);
4917 #ifdef RTL8723BU_PATH_B
4918 if (RF_Path == 0x0) //S1
4919 ODM_SetIQCbyRFpath(pDM_Odm, 0);
4920 else //S0
4921 ODM_SetIQCbyRFpath(pDM_Odm, 1);
4922 #endif
4923 }
4924 rtl8xxxu_prepare_calibrate(priv, 0);
4925 }
4926
4927 static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
4928 {
4929 u32 val32;
4930 u32 rf_amode, rf_bmode = 0, lstf;
4931
4932 /* Check continuous TX and Packet TX */
4933 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
4934
4935 if (lstf & OFDM_LSTF_MASK) {
4936 /* Disable all continuous TX */
4937 val32 = lstf & ~OFDM_LSTF_MASK;
4938 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
4939
4940 /* Read original RF mode Path A */
4941 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);
4942
4943 /* Set RF mode to standby Path A */
4944 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,
4945 (rf_amode & 0x8ffff) | 0x10000);
4946
4947 /* Path-B */
4948 if (priv->tx_paths > 1) {
4949 rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,
4950 RF6052_REG_AC);
4951
4952 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
4953 (rf_bmode & 0x8ffff) | 0x10000);
4954 }
4955 } else {
4956 /* Deal with Packet TX case */
4957 /* block all queues */
4958 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
4959 }
4960
4961 /* Start LC calibration */
4962 if (priv->fops->has_s0s1)
4963 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdfbe0);
4964 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
4965 val32 |= 0x08000;
4966 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
4967
4968 msleep(100);
4969
4970 if (priv->fops->has_s0s1)
4971 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdffe0);
4972
4973 /* Restore original parameters */
4974 if (lstf & OFDM_LSTF_MASK) {
4975 /* Path-A */
4976 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);
4977 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);
4978
4979 /* Path-B */
4980 if (priv->tx_paths > 1)
4981 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
4982 rf_bmode);
4983 } else /* Deal with Packet TX case */
4984 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
4985 }
4986
4987 static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv)
4988 {
4989 int i;
4990 u16 reg;
4991
4992 reg = REG_MACID;
4993
4994 for (i = 0; i < ETH_ALEN; i++)
4995 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]);
4996
4997 return 0;
4998 }
4999
5000 static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid)
5001 {
5002 int i;
5003 u16 reg;
5004
5005 dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);
5006
5007 reg = REG_BSSID;
5008
5009 for (i = 0; i < ETH_ALEN; i++)
5010 rtl8xxxu_write8(priv, reg + i, bssid[i]);
5011
5012 return 0;
5013 }
5014
5015 static void
5016 rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)
5017 {
5018 u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };
5019 u8 max_agg = 0xf;
5020 int i;
5021
5022 ampdu_factor = 1 << (ampdu_factor + 2);
5023 if (ampdu_factor > max_agg)
5024 ampdu_factor = max_agg;
5025
5026 for (i = 0; i < 4; i++) {
5027 if ((vals[i] & 0xf0) > (ampdu_factor << 4))
5028 vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);
5029
5030 if ((vals[i] & 0x0f) > ampdu_factor)
5031 vals[i] = (vals[i] & 0xf0) | ampdu_factor;
5032
5033 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);
5034 }
5035 }
5036
5037 static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)
5038 {
5039 u8 val8;
5040
5041 val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);
5042 val8 &= 0xf8;
5043 val8 |= density;
5044 rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
5045 }
5046
5047 static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
5048 {
5049 u8 val8;
5050 int count, ret;
5051
5052 /* Start of rtl8723AU_card_enable_flow */
5053 /* Act to Cardemu sequence*/
5054 /* Turn off RF */
5055 rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
5056
5057 /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
5058 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
5059 val8 &= ~LEDCFG2_DPDT_SELECT;
5060 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
5061
5062 /* 0x0005[1] = 1 turn off MAC by HW state machine*/
5063 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5064 val8 |= BIT(1);
5065 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5066
5067 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5068 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5069 if ((val8 & BIT(1)) == 0)
5070 break;
5071 udelay(10);
5072 }
5073
5074 if (!count) {
5075 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
5076 __func__);
5077 ret = -EBUSY;
5078 goto exit;
5079 }
5080
5081 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
5082 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5083 val8 |= SYS_ISO_ANALOG_IPS;
5084 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5085
5086 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
5087 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
5088 val8 &= ~LDOA15_ENABLE;
5089 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
5090
5091 exit:
5092 return ret;
5093 }
5094
5095 static int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
5096 {
5097 u8 val8;
5098 u8 val32;
5099 int count, ret;
5100
5101 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5102
5103 /*
5104 * Poll - wait for RX packet to complete
5105 */
5106 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5107 val32 = rtl8xxxu_read32(priv, 0x5f8);
5108 if (!val32)
5109 break;
5110 udelay(10);
5111 }
5112
5113 if (!count) {
5114 dev_warn(&priv->udev->dev,
5115 "%s: RX poll timed out (0x05f8)\n", __func__);
5116 ret = -EBUSY;
5117 goto exit;
5118 }
5119
5120 /* Disable CCK and OFDM, clock gated */
5121 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
5122 val8 &= ~SYS_FUNC_BBRSTB;
5123 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
5124
5125 udelay(2);
5126
5127 /* Reset baseband */
5128 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
5129 val8 &= ~SYS_FUNC_BB_GLB_RSTN;
5130 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
5131
5132 /* Reset MAC TRX */
5133 val8 = rtl8xxxu_read8(priv, REG_CR);
5134 val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;
5135 rtl8xxxu_write8(priv, REG_CR, val8);
5136
5137 /* Reset MAC TRX */
5138 val8 = rtl8xxxu_read8(priv, REG_CR + 1);
5139 val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */
5140 rtl8xxxu_write8(priv, REG_CR + 1, val8);
5141
5142 /* Respond TX OK to scheduler */
5143 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
5144 val8 |= DUAL_TSF_TX_OK;
5145 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
5146
5147 exit:
5148 return ret;
5149 }
5150
5151 static void rtl8723a_disabled_to_emu(struct rtl8xxxu_priv *priv)
5152 {
5153 u8 val8;
5154
5155 /* Clear suspend enable and power down enable*/
5156 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5157 val8 &= ~(BIT(3) | BIT(7));
5158 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5159
5160 /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
5161 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
5162 val8 &= ~BIT(0);
5163 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
5164
5165 /* 0x04[12:11] = 11 enable WL suspend*/
5166 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5167 val8 &= ~(BIT(3) | BIT(4));
5168 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5169 }
5170
5171 static void rtl8192e_disabled_to_emu(struct rtl8xxxu_priv *priv)
5172 {
5173 u8 val8;
5174
5175 /* Clear suspend enable and power down enable*/
5176 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5177 val8 &= ~(BIT(3) | BIT(4));
5178 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5179 }
5180
5181 static int rtl8192e_emu_to_active(struct rtl8xxxu_priv *priv)
5182 {
5183 u8 val8;
5184 u32 val32;
5185 int count, ret = 0;
5186
5187 /* disable HWPDN 0x04[15]=0*/
5188 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5189 val8 &= ~BIT(7);
5190 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5191
5192 /* disable SW LPS 0x04[10]= 0 */
5193 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5194 val8 &= ~BIT(2);
5195 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5196
5197 /* disable WL suspend*/
5198 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5199 val8 &= ~(BIT(3) | BIT(4));
5200 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5201
5202 /* wait till 0x04[17] = 1 power ready*/
5203 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5204 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5205 if (val32 & BIT(17))
5206 break;
5207
5208 udelay(10);
5209 }
5210
5211 if (!count) {
5212 ret = -EBUSY;
5213 goto exit;
5214 }
5215
5216 /* We should be able to optimize the following three entries into one */
5217
5218 /* release WLON reset 0x04[16]= 1*/
5219 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
5220 val8 |= BIT(0);
5221 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
5222
5223 /* set, then poll until 0 */
5224 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5225 val32 |= APS_FSMCO_MAC_ENABLE;
5226 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5227
5228 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5229 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5230 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
5231 ret = 0;
5232 break;
5233 }
5234 udelay(10);
5235 }
5236
5237 if (!count) {
5238 ret = -EBUSY;
5239 goto exit;
5240 }
5241
5242 exit:
5243 return ret;
5244 }
5245
5246 static int rtl8723a_emu_to_active(struct rtl8xxxu_priv *priv)
5247 {
5248 u8 val8;
5249 u32 val32;
5250 int count, ret = 0;
5251
5252 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/
5253 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
5254 val8 |= LDOA15_ENABLE;
5255 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
5256
5257 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
5258 val8 = rtl8xxxu_read8(priv, 0x0067);
5259 val8 &= ~BIT(4);
5260 rtl8xxxu_write8(priv, 0x0067, val8);
5261
5262 mdelay(1);
5263
5264 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
5265 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5266 val8 &= ~SYS_ISO_ANALOG_IPS;
5267 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5268
5269 /* disable SW LPS 0x04[10]= 0 */
5270 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5271 val8 &= ~BIT(2);
5272 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5273
5274 /* wait till 0x04[17] = 1 power ready*/
5275 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5276 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5277 if (val32 & BIT(17))
5278 break;
5279
5280 udelay(10);
5281 }
5282
5283 if (!count) {
5284 ret = -EBUSY;
5285 goto exit;
5286 }
5287
5288 /* We should be able to optimize the following three entries into one */
5289
5290 /* release WLON reset 0x04[16]= 1*/
5291 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
5292 val8 |= BIT(0);
5293 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
5294
5295 /* disable HWPDN 0x04[15]= 0*/
5296 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5297 val8 &= ~BIT(7);
5298 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5299
5300 /* disable WL suspend*/
5301 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5302 val8 &= ~(BIT(3) | BIT(4));
5303 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5304
5305 /* set, then poll until 0 */
5306 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5307 val32 |= APS_FSMCO_MAC_ENABLE;
5308 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5309
5310 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5311 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5312 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
5313 ret = 0;
5314 break;
5315 }
5316 udelay(10);
5317 }
5318
5319 if (!count) {
5320 ret = -EBUSY;
5321 goto exit;
5322 }
5323
5324 /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */
5325 /*
5326 * Note: Vendor driver actually clears this bit, despite the
5327 * documentation claims it's being set!
5328 */
5329 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
5330 val8 |= LEDCFG2_DPDT_SELECT;
5331 val8 &= ~LEDCFG2_DPDT_SELECT;
5332 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
5333
5334 exit:
5335 return ret;
5336 }
5337
5338 static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
5339 {
5340 u8 val8;
5341
5342 /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
5343 rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
5344
5345 /* 0x04[12:11] = 01 enable WL suspend */
5346 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5347 val8 &= ~BIT(4);
5348 val8 |= BIT(3);
5349 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5350
5351 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5352 val8 |= BIT(7);
5353 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5354
5355 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
5356 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
5357 val8 |= BIT(0);
5358 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
5359
5360 return 0;
5361 }
5362
5363 static int rtl8723au_power_on(struct rtl8xxxu_priv *priv)
5364 {
5365 u8 val8;
5366 u16 val16;
5367 u32 val32;
5368 int ret;
5369
5370 /*
5371 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
5372 */
5373 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
5374
5375 rtl8723a_disabled_to_emu(priv);
5376
5377 ret = rtl8723a_emu_to_active(priv);
5378 if (ret)
5379 goto exit;
5380
5381 /*
5382 * 0x0004[19] = 1, reset 8051
5383 */
5384 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
5385 val8 |= BIT(3);
5386 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
5387
5388 /*
5389 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5390 * Set CR bit10 to enable 32k calibration.
5391 */
5392 val16 = rtl8xxxu_read16(priv, REG_CR);
5393 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5394 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
5395 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
5396 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
5397 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
5398 rtl8xxxu_write16(priv, REG_CR, val16);
5399
5400 /* For EFuse PG */
5401 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
5402 val32 &= ~(BIT(28) | BIT(29) | BIT(30));
5403 val32 |= (0x06 << 28);
5404 rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32);
5405 exit:
5406 return ret;
5407 }
5408
5409 #ifdef CONFIG_RTL8XXXU_UNTESTED
5410
5411 static int rtl8192cu_power_on(struct rtl8xxxu_priv *priv)
5412 {
5413 u8 val8;
5414 u16 val16;
5415 u32 val32;
5416 int i;
5417
5418 for (i = 100; i; i--) {
5419 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
5420 if (val8 & APS_FSMCO_PFM_ALDN)
5421 break;
5422 }
5423
5424 if (!i) {
5425 pr_info("%s: Poll failed\n", __func__);
5426 return -ENODEV;
5427 }
5428
5429 /*
5430 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
5431 */
5432 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
5433 rtl8xxxu_write8(priv, REG_SPS0_CTRL, 0x2b);
5434 udelay(100);
5435
5436 val8 = rtl8xxxu_read8(priv, REG_LDOV12D_CTRL);
5437 if (!(val8 & LDOV12D_ENABLE)) {
5438 pr_info("%s: Enabling LDOV12D (%02x)\n", __func__, val8);
5439 val8 |= LDOV12D_ENABLE;
5440 rtl8xxxu_write8(priv, REG_LDOV12D_CTRL, val8);
5441
5442 udelay(100);
5443
5444 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5445 val8 &= ~SYS_ISO_MD2PP;
5446 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5447 }
5448
5449 /*
5450 * Auto enable WLAN
5451 */
5452 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
5453 val16 |= APS_FSMCO_MAC_ENABLE;
5454 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
5455
5456 for (i = 1000; i; i--) {
5457 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
5458 if (!(val16 & APS_FSMCO_MAC_ENABLE))
5459 break;
5460 }
5461 if (!i) {
5462 pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__);
5463 return -EBUSY;
5464 }
5465
5466 /*
5467 * Enable radio, GPIO, LED
5468 */
5469 val16 = APS_FSMCO_HW_SUSPEND | APS_FSMCO_ENABLE_POWERDOWN |
5470 APS_FSMCO_PFM_ALDN;
5471 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
5472
5473 /*
5474 * Release RF digital isolation
5475 */
5476 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
5477 val16 &= ~SYS_ISO_DIOR;
5478 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
5479
5480 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
5481 val8 &= ~APSD_CTRL_OFF;
5482 rtl8xxxu_write8(priv, REG_APSD_CTRL, val8);
5483 for (i = 200; i; i--) {
5484 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
5485 if (!(val8 & APSD_CTRL_OFF_STATUS))
5486 break;
5487 }
5488
5489 if (!i) {
5490 pr_info("%s: APSD_CTRL poll failed\n", __func__);
5491 return -EBUSY;
5492 }
5493
5494 /*
5495 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5496 */
5497 val16 = rtl8xxxu_read16(priv, REG_CR);
5498 val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5499 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | CR_PROTOCOL_ENABLE |
5500 CR_SCHEDULE_ENABLE | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE;
5501 rtl8xxxu_write16(priv, REG_CR, val16);
5502
5503 /*
5504 * Workaround for 8188RU LNA power leakage problem.
5505 */
5506 if (priv->rtlchip == 0x8188c && priv->hi_pa) {
5507 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
5508 val32 &= ~BIT(1);
5509 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
5510 }
5511 return 0;
5512 }
5513
5514 #endif
5515
5516 static int rtl8192eu_power_on(struct rtl8xxxu_priv *priv)
5517 {
5518 u16 val16;
5519 u32 val32;
5520 int ret;
5521
5522 ret = 0;
5523
5524 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
5525 if (val32 & SYS_CFG_SPS_LDO_SEL) {
5526 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0xc3);
5527 } else {
5528 /*
5529 * Raise 1.2V voltage
5530 */
5531 val32 = rtl8xxxu_read32(priv, REG_8192E_LDOV12_CTRL);
5532 val32 &= 0xff0fffff;
5533 val32 |= 0x00500000;
5534 rtl8xxxu_write32(priv, REG_8192E_LDOV12_CTRL, val32);
5535 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0x83);
5536 }
5537
5538 rtl8192e_disabled_to_emu(priv);
5539
5540 ret = rtl8192e_emu_to_active(priv);
5541 if (ret)
5542 goto exit;
5543
5544 rtl8xxxu_write16(priv, REG_CR, 0x0000);
5545
5546 /*
5547 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5548 * Set CR bit10 to enable 32k calibration.
5549 */
5550 val16 = rtl8xxxu_read16(priv, REG_CR);
5551 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5552 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
5553 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
5554 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
5555 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
5556 rtl8xxxu_write16(priv, REG_CR, val16);
5557
5558 exit:
5559 return ret;
5560 }
5561
5562 static void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
5563 {
5564 u8 val8;
5565 u16 val16;
5566 u32 val32;
5567
5568 /*
5569 * Workaround for 8188RU LNA power leakage problem.
5570 */
5571 if (priv->rtlchip == 0x8188c && priv->hi_pa) {
5572 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
5573 val32 |= BIT(1);
5574 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
5575 }
5576
5577 rtl8xxxu_active_to_lps(priv);
5578
5579 /* Turn off RF */
5580 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
5581
5582 /* Reset Firmware if running in RAM */
5583 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
5584 rtl8xxxu_firmware_self_reset(priv);
5585
5586 /* Reset MCU */
5587 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
5588 val16 &= ~SYS_FUNC_CPU_ENABLE;
5589 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
5590
5591 /* Reset MCU ready status */
5592 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
5593
5594 rtl8xxxu_active_to_emu(priv);
5595 rtl8xxxu_emu_to_disabled(priv);
5596
5597 /* Reset MCU IO Wrapper */
5598 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
5599 val8 &= ~BIT(0);
5600 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
5601
5602 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
5603 val8 |= BIT(0);
5604 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
5605
5606 /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */
5607 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
5608 }
5609
5610 static void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv,
5611 u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5)
5612 {
5613 struct h2c_cmd h2c;
5614
5615 memset(&h2c, 0, sizeof(struct h2c_cmd));
5616 h2c.b_type_dma.cmd = H2C_8723B_B_TYPE_TDMA;
5617 h2c.b_type_dma.data1 = arg1;
5618 h2c.b_type_dma.data2 = arg2;
5619 h2c.b_type_dma.data3 = arg3;
5620 h2c.b_type_dma.data4 = arg4;
5621 h2c.b_type_dma.data5 = arg5;
5622 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.b_type_dma));
5623 }
5624
5625 static void rtl8723bu_init_bt(struct rtl8xxxu_priv *priv)
5626 {
5627 struct h2c_cmd h2c;
5628 u32 val32;
5629 u8 val8;
5630
5631 /*
5632 * No indication anywhere as to what 0x0790 does. The 2 antenna
5633 * vendor code preserves bits 6-7 here.
5634 */
5635 rtl8xxxu_write8(priv, 0x0790, 0x05);
5636 /*
5637 * 0x0778 seems to be related to enabling the number of antennas
5638 * In the vendor driver halbtc8723b2ant_InitHwConfig() sets it
5639 * to 0x03, while halbtc8723b1ant_InitHwConfig() sets it to 0x01
5640 */
5641 rtl8xxxu_write8(priv, 0x0778, 0x01);
5642
5643 val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG);
5644 val8 |= BIT(5);
5645 rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8);
5646
5647 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_IQADJ_G1, 0x780);
5648
5649 /*
5650 * Set BT grant to low
5651 */
5652 memset(&h2c, 0, sizeof(struct h2c_cmd));
5653 h2c.bt_grant.cmd = H2C_8723B_BT_GRANT;
5654 h2c.bt_grant.data = 0;
5655 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_grant));
5656
5657 /*
5658 * WLAN action by PTA
5659 */
5660 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x0c);
5661
5662 /*
5663 * BT select S0/S1 controlled by WiFi
5664 */
5665 val8 = rtl8xxxu_read8(priv, 0x0067);
5666 val8 |= BIT(5);
5667 rtl8xxxu_write8(priv, 0x0067, val8);
5668
5669 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
5670 val32 |= BIT(11);
5671 rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
5672
5673 /*
5674 * Bits 6/7 are marked in/out ... but for what?
5675 */
5676 rtl8xxxu_write8(priv, 0x0974, 0xff);
5677
5678 val32 = rtl8xxxu_read32(priv, 0x0944);
5679 val32 |= (BIT(0) | BIT(1));
5680 rtl8xxxu_write32(priv, 0x0944, val32);
5681
5682 rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77);
5683
5684 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
5685 val32 &= ~BIT(24);
5686 val32 |= BIT(23);
5687 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
5688
5689 /*
5690 * Fix external switch Main->S1, Aux->S0
5691 */
5692 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
5693 val8 &= ~BIT(0);
5694 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
5695
5696 memset(&h2c, 0, sizeof(struct h2c_cmd));
5697 h2c.ant_sel_rsv.cmd = H2C_8723B_ANT_SEL_RSV;
5698 h2c.ant_sel_rsv.ant_inverse = 1;
5699 h2c.ant_sel_rsv.int_switch_type = 0;
5700 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ant_sel_rsv));
5701
5702 /*
5703 * 0x280, 0x00, 0x200, 0x80 - not clear
5704 */
5705 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
5706
5707 memset(&h2c, 0, sizeof(struct h2c_cmd));
5708 h2c.ignore_wlan.cmd = H2C_8723B_BT_IGNORE_WLANACT;
5709 h2c.ignore_wlan.data = 0;
5710 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ignore_wlan));
5711
5712 /*
5713 * Software control, antenna at WiFi side
5714 */
5715 rtl8723bu_set_ps_tdma(priv, 0x08, 0x00, 0x00, 0x00, 0x00);
5716
5717 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555);
5718 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x5a5a5a5a);
5719 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
5720 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE4, 0x00000003);
5721 }
5722
5723 static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
5724 {
5725 struct rtl8xxxu_priv *priv = hw->priv;
5726 struct device *dev = &priv->udev->dev;
5727 struct rtl8xxxu_rfregval *rftable;
5728 bool macpower;
5729 int ret;
5730 u8 val8;
5731 u16 val16;
5732 u32 val32;
5733
5734 /* Check if MAC is already powered on */
5735 val8 = rtl8xxxu_read8(priv, REG_CR);
5736
5737 /*
5738 * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
5739 * initialized. First MAC returns 0xea, second MAC returns 0x00
5740 */
5741 if (val8 == 0xea)
5742 macpower = false;
5743 else
5744 macpower = true;
5745
5746 ret = priv->fops->power_on(priv);
5747 if (ret < 0) {
5748 dev_warn(dev, "%s: Failed power on\n", __func__);
5749 goto exit;
5750 }
5751
5752 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
5753 if (!macpower) {
5754 if (priv->ep_tx_normal_queue)
5755 val8 = TX_PAGE_NUM_NORM_PQ;
5756 else
5757 val8 = 0;
5758
5759 rtl8xxxu_write8(priv, REG_RQPN_NPQ, val8);
5760
5761 val32 = (TX_PAGE_NUM_PUBQ << RQPN_NORM_PQ_SHIFT) | RQPN_LOAD;
5762
5763 if (priv->ep_tx_high_queue)
5764 val32 |= (TX_PAGE_NUM_HI_PQ << RQPN_HI_PQ_SHIFT);
5765 if (priv->ep_tx_low_queue)
5766 val32 |= (TX_PAGE_NUM_LO_PQ << RQPN_LO_PQ_SHIFT);
5767
5768 rtl8xxxu_write32(priv, REG_RQPN, val32);
5769
5770 /*
5771 * Set TX buffer boundary
5772 */
5773 val8 = TX_TOTAL_PAGE_NUM + 1;
5774 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);
5775 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);
5776 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);
5777 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);
5778 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);
5779 }
5780
5781 ret = rtl8xxxu_download_firmware(priv);
5782 dev_dbg(dev, "%s: download_fiwmare %i\n", __func__, ret);
5783 if (ret)
5784 goto exit;
5785 ret = rtl8xxxu_start_firmware(priv);
5786 dev_dbg(dev, "%s: start_fiwmare %i\n", __func__, ret);
5787 if (ret)
5788 goto exit;
5789
5790 ret = rtl8xxxu_init_queue_priority(priv);
5791 dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);
5792 if (ret)
5793 goto exit;
5794
5795 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
5796 if (!macpower) {
5797 ret = priv->fops->llt_init(priv, TX_TOTAL_PAGE_NUM);
5798 if (ret) {
5799 dev_warn(dev, "%s: LLT table init failed\n", __func__);
5800 goto exit;
5801 }
5802 }
5803
5804 /* Fix USB interface interference issue */
5805 if (priv->rtlchip == 0x8723a) {
5806 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
5807 rtl8xxxu_write8(priv, 0xfe41, 0x8d);
5808 rtl8xxxu_write8(priv, 0xfe42, 0x80);
5809 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);
5810 } else {
5811 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK);
5812 val32 |= TXDMA_OFFSET_DROP_DATA_EN;
5813 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32);
5814 }
5815
5816 /* Solve too many protocol error on USB bus */
5817 /* Can't do this for 8188/8192 UMC A cut parts */
5818 if (priv->rtlchip == 0x8723a ||
5819 ((priv->rtlchip == 0x8192c || priv->rtlchip == 0x8191c ||
5820 priv->rtlchip == 0x8188c) &&
5821 (priv->chip_cut || !priv->vendor_umc))) {
5822 rtl8xxxu_write8(priv, 0xfe40, 0xe6);
5823 rtl8xxxu_write8(priv, 0xfe41, 0x94);
5824 rtl8xxxu_write8(priv, 0xfe42, 0x80);
5825
5826 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
5827 rtl8xxxu_write8(priv, 0xfe41, 0x19);
5828 rtl8xxxu_write8(priv, 0xfe42, 0x80);
5829
5830 rtl8xxxu_write8(priv, 0xfe40, 0xe5);
5831 rtl8xxxu_write8(priv, 0xfe41, 0x91);
5832 rtl8xxxu_write8(priv, 0xfe42, 0x80);
5833
5834 rtl8xxxu_write8(priv, 0xfe40, 0xe2);
5835 rtl8xxxu_write8(priv, 0xfe41, 0x81);
5836 rtl8xxxu_write8(priv, 0xfe42, 0x80);
5837 }
5838
5839 if (priv->rtlchip == 0x8192e || priv->rtlchip == 0x8723b) {
5840 rtl8xxxu_write32(priv, REG_HIMR0, 0x00);
5841 rtl8xxxu_write32(priv, REG_HIMR1, 0x00);
5842 }
5843
5844 if (priv->fops->phy_init_antenna_selection)
5845 priv->fops->phy_init_antenna_selection(priv);
5846
5847 if (priv->rtlchip == 0x8723b)
5848 ret = rtl8xxxu_init_mac(priv, rtl8723b_mac_init_table);
5849 else
5850 ret = rtl8xxxu_init_mac(priv, rtl8723a_mac_init_table);
5851
5852 dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);
5853 if (ret)
5854 goto exit;
5855
5856 ret = rtl8xxxu_init_phy_bb(priv);
5857 dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);
5858 if (ret)
5859 goto exit;
5860
5861 switch(priv->rtlchip) {
5862 case 0x8723a:
5863 rftable = rtl8723au_radioa_1t_init_table;
5864 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
5865 break;
5866 case 0x8723b:
5867 rftable = rtl8723bu_radioa_1t_init_table;
5868 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
5869 break;
5870 case 0x8188c:
5871 if (priv->hi_pa)
5872 rftable = rtl8188ru_radioa_1t_highpa_table;
5873 else
5874 rftable = rtl8192cu_radioa_1t_init_table;
5875 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
5876 break;
5877 case 0x8191c:
5878 rftable = rtl8192cu_radioa_1t_init_table;
5879 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
5880 break;
5881 case 0x8192c:
5882 rftable = rtl8192cu_radioa_2t_init_table;
5883 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
5884 if (ret)
5885 break;
5886 rftable = rtl8192cu_radiob_2t_init_table;
5887 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B);
5888 break;
5889 default:
5890 ret = -EINVAL;
5891 }
5892
5893 if (ret)
5894 goto exit;
5895
5896 /* Reduce 80M spur */
5897 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d);
5898 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
5899 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82);
5900 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
5901
5902 /* RFSW Control - clear bit 14 ?? */
5903 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
5904 /* 0x07000760 */
5905 val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
5906 FPGA0_RF_ANTSWB | FPGA0_RF_PAPE |
5907 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB | FPGA0_RF_PAPE) <<
5908 FPGA0_RF_BD_CTRL_SHIFT);
5909 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
5910 /* 0x860[6:5]= 00 - why? - this sets antenna B */
5911 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66F60210);
5912
5913 priv->rf_mode_ag[0] = rtl8xxxu_read_rfreg(priv, RF_A,
5914 RF6052_REG_MODE_AG);
5915
5916 /*
5917 * Set RX page boundary
5918 */
5919 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x27ff);
5920 /*
5921 * Transfer page size is always 128
5922 */
5923 val8 = (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_RX_SHIFT) |
5924 (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_TX_SHIFT);
5925 rtl8xxxu_write8(priv, REG_PBP, val8);
5926
5927 /*
5928 * Unit in 8 bytes, not obvious what it is used for
5929 */
5930 rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);
5931
5932 /*
5933 * Enable all interrupts - not obvious USB needs to do this
5934 */
5935 rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);
5936 rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);
5937
5938 rtl8xxxu_set_mac(priv);
5939 rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION);
5940
5941 /*
5942 * Configure initial WMAC settings
5943 */
5944 val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |
5945 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |
5946 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
5947 rtl8xxxu_write32(priv, REG_RCR, val32);
5948
5949 /*
5950 * Accept all multicast
5951 */
5952 rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
5953 rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
5954
5955 /*
5956 * Init adaptive controls
5957 */
5958 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
5959 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
5960 val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;
5961 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
5962
5963 /* CCK = 0x0a, OFDM = 0x10 */
5964 rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);
5965 rtl8xxxu_set_retry(priv, 0x30, 0x30);
5966 rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);
5967
5968 /*
5969 * Init EDCA
5970 */
5971 rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);
5972
5973 /* Set CCK SIFS */
5974 rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);
5975
5976 /* Set OFDM SIFS */
5977 rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);
5978
5979 /* TXOP */
5980 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);
5981 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);
5982 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);
5983 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);
5984
5985 /* Set data auto rate fallback retry count */
5986 rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);
5987 rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);
5988 rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);
5989 rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);
5990
5991 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);
5992 val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;
5993 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);
5994
5995 /* Set ACK timeout */
5996 rtl8xxxu_write8(priv, REG_ACKTO, 0x40);
5997
5998 /*
5999 * Initialize beacon parameters
6000 */
6001 val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
6002 rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
6003 rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
6004 rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
6005 rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
6006 rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
6007
6008 /*
6009 * Enable CCK and OFDM block
6010 */
6011 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
6012 val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);
6013 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
6014
6015 /*
6016 * Invalidate all CAM entries - bit 30 is undocumented
6017 */
6018 rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));
6019
6020 /*
6021 * Start out with default power levels for channel 6, 20MHz
6022 */
6023 rtl8723a_set_tx_power(priv, 1, false);
6024
6025 /* Let the 8051 take control of antenna setting */
6026 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
6027 val8 |= LEDCFG2_DPDT_SELECT;
6028 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
6029
6030 rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);
6031
6032 /* Disable BAR - not sure if this has any effect on USB */
6033 rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
6034
6035 rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
6036
6037 rtl8723a_phy_lc_calibrate(priv);
6038
6039 priv->fops->phy_iq_calibrate(priv);
6040
6041 /*
6042 * This should enable thermal meter
6043 */
6044 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
6045
6046 /* Init BT hw config. */
6047 if (priv->fops->init_bt)
6048 priv->fops->init_bt(priv);
6049
6050 /* Set NAV_UPPER to 30000us */
6051 val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
6052 rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);
6053
6054 if (priv->rtlchip == 0x8723a) {
6055 /*
6056 * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
6057 * but we need to find root cause.
6058 * This is 8723au only.
6059 */
6060 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
6061 if ((val32 & 0xff000000) != 0x83000000) {
6062 val32 |= FPGA_RF_MODE_CCK;
6063 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
6064 }
6065 }
6066
6067 val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
6068 val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;
6069 /* ack for xmit mgmt frames. */
6070 rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);
6071
6072 exit:
6073 return ret;
6074 }
6075
6076 static void rtl8xxxu_disable_device(struct ieee80211_hw *hw)
6077 {
6078 struct rtl8xxxu_priv *priv = hw->priv;
6079
6080 rtl8xxxu_power_off(priv);
6081 }
6082
6083 static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,
6084 struct ieee80211_key_conf *key, const u8 *mac)
6085 {
6086 u32 cmd, val32, addr, ctrl;
6087 int j, i, tmp_debug;
6088
6089 tmp_debug = rtl8xxxu_debug;
6090 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)
6091 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;
6092
6093 /*
6094 * This is a bit of a hack - the lower bits of the cipher
6095 * suite selector happens to match the cipher index in the CAM
6096 */
6097 addr = key->keyidx << CAM_CMD_KEY_SHIFT;
6098 ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;
6099
6100 for (j = 5; j >= 0; j--) {
6101 switch (j) {
6102 case 0:
6103 val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);
6104 break;
6105 case 1:
6106 val32 = mac[2] | (mac[3] << 8) |
6107 (mac[4] << 16) | (mac[5] << 24);
6108 break;
6109 default:
6110 i = (j - 2) << 2;
6111 val32 = key->key[i] | (key->key[i + 1] << 8) |
6112 key->key[i + 2] << 16 | key->key[i + 3] << 24;
6113 break;
6114 }
6115
6116 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);
6117 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);
6118 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);
6119 udelay(100);
6120 }
6121
6122 rtl8xxxu_debug = tmp_debug;
6123 }
6124
6125 static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
6126 struct ieee80211_vif *vif, const u8 *mac)
6127 {
6128 struct rtl8xxxu_priv *priv = hw->priv;
6129 u8 val8;
6130
6131 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6132 val8 |= BEACON_DISABLE_TSF_UPDATE;
6133 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
6134 }
6135
6136 static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
6137 struct ieee80211_vif *vif)
6138 {
6139 struct rtl8xxxu_priv *priv = hw->priv;
6140 u8 val8;
6141
6142 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6143 val8 &= ~BEACON_DISABLE_TSF_UPDATE;
6144 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
6145 }
6146
6147 static void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
6148 u32 ramask, int sgi)
6149 {
6150 struct h2c_cmd h2c;
6151
6152 h2c.ramask.cmd = H2C_SET_RATE_MASK;
6153 h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);
6154 h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);
6155
6156 h2c.ramask.arg = 0x80;
6157 if (sgi)
6158 h2c.ramask.arg |= 0x20;
6159
6160 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",
6161 __func__, ramask, h2c.ramask.arg, sizeof(h2c.ramask));
6162 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ramask));
6163 }
6164
6165 static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
6166 {
6167 u32 val32;
6168 u8 rate_idx = 0;
6169
6170 rate_cfg &= RESPONSE_RATE_BITMAP_ALL;
6171
6172 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
6173 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
6174 val32 |= rate_cfg;
6175 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
6176
6177 dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);
6178
6179 while (rate_cfg) {
6180 rate_cfg = (rate_cfg >> 1);
6181 rate_idx++;
6182 }
6183 rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);
6184 }
6185
6186 static void
6187 rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
6188 struct ieee80211_bss_conf *bss_conf, u32 changed)
6189 {
6190 struct rtl8xxxu_priv *priv = hw->priv;
6191 struct device *dev = &priv->udev->dev;
6192 struct ieee80211_sta *sta;
6193 u32 val32;
6194 u8 val8;
6195
6196 if (changed & BSS_CHANGED_ASSOC) {
6197 struct h2c_cmd h2c;
6198
6199 dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc);
6200
6201 memset(&h2c, 0, sizeof(struct h2c_cmd));
6202 rtl8xxxu_set_linktype(priv, vif->type);
6203
6204 if (bss_conf->assoc) {
6205 u32 ramask;
6206 int sgi = 0;
6207
6208 rcu_read_lock();
6209 sta = ieee80211_find_sta(vif, bss_conf->bssid);
6210 if (!sta) {
6211 dev_info(dev, "%s: ASSOC no sta found\n",
6212 __func__);
6213 rcu_read_unlock();
6214 goto error;
6215 }
6216
6217 if (sta->ht_cap.ht_supported)
6218 dev_info(dev, "%s: HT supported\n", __func__);
6219 if (sta->vht_cap.vht_supported)
6220 dev_info(dev, "%s: VHT supported\n", __func__);
6221
6222 /* TODO: Set bits 28-31 for rate adaptive id */
6223 ramask = (sta->supp_rates[0] & 0xfff) |
6224 sta->ht_cap.mcs.rx_mask[0] << 12 |
6225 sta->ht_cap.mcs.rx_mask[1] << 20;
6226 if (sta->ht_cap.cap &
6227 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
6228 sgi = 1;
6229 rcu_read_unlock();
6230
6231 rtl8xxxu_update_rate_mask(priv, ramask, sgi);
6232
6233 rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
6234
6235 rtl8723a_stop_tx_beacon(priv);
6236
6237 /* joinbss sequence */
6238 rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
6239 0xc000 | bss_conf->aid);
6240
6241 h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;
6242 } else {
6243 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6244 val8 |= BEACON_DISABLE_TSF_UPDATE;
6245 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
6246
6247 h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;
6248 }
6249 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;
6250 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.joinbss));
6251 }
6252
6253 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
6254 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",
6255 bss_conf->use_short_preamble);
6256 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
6257 if (bss_conf->use_short_preamble)
6258 val32 |= RSR_ACK_SHORT_PREAMBLE;
6259 else
6260 val32 &= ~RSR_ACK_SHORT_PREAMBLE;
6261 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
6262 }
6263
6264 if (changed & BSS_CHANGED_ERP_SLOT) {
6265 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",
6266 bss_conf->use_short_slot);
6267
6268 if (bss_conf->use_short_slot)
6269 val8 = 9;
6270 else
6271 val8 = 20;
6272 rtl8xxxu_write8(priv, REG_SLOT, val8);
6273 }
6274
6275 if (changed & BSS_CHANGED_BSSID) {
6276 dev_dbg(dev, "Changed BSSID!\n");
6277 rtl8xxxu_set_bssid(priv, bss_conf->bssid);
6278 }
6279
6280 if (changed & BSS_CHANGED_BASIC_RATES) {
6281 dev_dbg(dev, "Changed BASIC_RATES!\n");
6282 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
6283 }
6284 error:
6285 return;
6286 }
6287
6288 static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
6289 {
6290 u32 rtlqueue;
6291
6292 switch (queue) {
6293 case IEEE80211_AC_VO:
6294 rtlqueue = TXDESC_QUEUE_VO;
6295 break;
6296 case IEEE80211_AC_VI:
6297 rtlqueue = TXDESC_QUEUE_VI;
6298 break;
6299 case IEEE80211_AC_BE:
6300 rtlqueue = TXDESC_QUEUE_BE;
6301 break;
6302 case IEEE80211_AC_BK:
6303 rtlqueue = TXDESC_QUEUE_BK;
6304 break;
6305 default:
6306 rtlqueue = TXDESC_QUEUE_BE;
6307 }
6308
6309 return rtlqueue;
6310 }
6311
6312 static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb)
6313 {
6314 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
6315 u32 queue;
6316
6317 if (ieee80211_is_mgmt(hdr->frame_control))
6318 queue = TXDESC_QUEUE_MGNT;
6319 else
6320 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
6321
6322 return queue;
6323 }
6324
6325 static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_tx_desc *tx_desc)
6326 {
6327 __le16 *ptr = (__le16 *)tx_desc;
6328 u16 csum = 0;
6329 int i;
6330
6331 /*
6332 * Clear csum field before calculation, as the csum field is
6333 * in the middle of the struct.
6334 */
6335 tx_desc->csum = cpu_to_le16(0);
6336
6337 for (i = 0; i < (sizeof(struct rtl8xxxu_tx_desc) / sizeof(u16)); i++)
6338 csum = csum ^ le16_to_cpu(ptr[i]);
6339
6340 tx_desc->csum |= cpu_to_le16(csum);
6341 }
6342
6343 static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)
6344 {
6345 struct rtl8xxxu_tx_urb *tx_urb, *tmp;
6346 unsigned long flags;
6347
6348 spin_lock_irqsave(&priv->tx_urb_lock, flags);
6349 list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {
6350 list_del(&tx_urb->list);
6351 priv->tx_urb_free_count--;
6352 usb_free_urb(&tx_urb->urb);
6353 }
6354 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
6355 }
6356
6357 static struct rtl8xxxu_tx_urb *
6358 rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)
6359 {
6360 struct rtl8xxxu_tx_urb *tx_urb;
6361 unsigned long flags;
6362
6363 spin_lock_irqsave(&priv->tx_urb_lock, flags);
6364 tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,
6365 struct rtl8xxxu_tx_urb, list);
6366 if (tx_urb) {
6367 list_del(&tx_urb->list);
6368 priv->tx_urb_free_count--;
6369 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&
6370 !priv->tx_stopped) {
6371 priv->tx_stopped = true;
6372 ieee80211_stop_queues(priv->hw);
6373 }
6374 }
6375
6376 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
6377
6378 return tx_urb;
6379 }
6380
6381 static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,
6382 struct rtl8xxxu_tx_urb *tx_urb)
6383 {
6384 unsigned long flags;
6385
6386 INIT_LIST_HEAD(&tx_urb->list);
6387
6388 spin_lock_irqsave(&priv->tx_urb_lock, flags);
6389
6390 list_add(&tx_urb->list, &priv->tx_urb_free_list);
6391 priv->tx_urb_free_count++;
6392 if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&
6393 priv->tx_stopped) {
6394 priv->tx_stopped = false;
6395 ieee80211_wake_queues(priv->hw);
6396 }
6397
6398 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
6399 }
6400
6401 static void rtl8xxxu_tx_complete(struct urb *urb)
6402 {
6403 struct sk_buff *skb = (struct sk_buff *)urb->context;
6404 struct ieee80211_tx_info *tx_info;
6405 struct ieee80211_hw *hw;
6406 struct rtl8xxxu_tx_urb *tx_urb =
6407 container_of(urb, struct rtl8xxxu_tx_urb, urb);
6408
6409 tx_info = IEEE80211_SKB_CB(skb);
6410 hw = tx_info->rate_driver_data[0];
6411
6412 skb_pull(skb, sizeof(struct rtl8xxxu_tx_desc));
6413
6414 ieee80211_tx_info_clear_status(tx_info);
6415 tx_info->status.rates[0].idx = -1;
6416 tx_info->status.rates[0].count = 0;
6417
6418 if (!urb->status)
6419 tx_info->flags |= IEEE80211_TX_STAT_ACK;
6420
6421 ieee80211_tx_status_irqsafe(hw, skb);
6422
6423 rtl8xxxu_free_tx_urb(hw->priv, tx_urb);
6424 }
6425
6426 static void rtl8xxxu_dump_action(struct device *dev,
6427 struct ieee80211_hdr *hdr)
6428 {
6429 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
6430 u16 cap, timeout;
6431
6432 if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
6433 return;
6434
6435 switch (mgmt->u.action.u.addba_resp.action_code) {
6436 case WLAN_ACTION_ADDBA_RESP:
6437 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);
6438 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);
6439 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
6440 "timeout %i, tid %02x, buf_size %02x, policy %02x, "
6441 "status %02x\n",
6442 timeout,
6443 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
6444 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
6445 (cap >> 1) & 0x1,
6446 le16_to_cpu(mgmt->u.action.u.addba_resp.status));
6447 break;
6448 case WLAN_ACTION_ADDBA_REQ:
6449 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
6450 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);
6451 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
6452 "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
6453 timeout,
6454 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
6455 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
6456 (cap >> 1) & 0x1);
6457 break;
6458 default:
6459 dev_info(dev, "action frame %02x\n",
6460 mgmt->u.action.u.addba_resp.action_code);
6461 break;
6462 }
6463 }
6464
6465 static void rtl8xxxu_tx(struct ieee80211_hw *hw,
6466 struct ieee80211_tx_control *control,
6467 struct sk_buff *skb)
6468 {
6469 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
6470 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
6471 struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
6472 struct rtl8xxxu_priv *priv = hw->priv;
6473 struct rtl8xxxu_tx_desc *tx_desc;
6474 struct rtl8xxxu_tx_urb *tx_urb;
6475 struct ieee80211_sta *sta = NULL;
6476 struct ieee80211_vif *vif = tx_info->control.vif;
6477 struct device *dev = &priv->udev->dev;
6478 u32 queue, rate;
6479 u16 pktlen = skb->len;
6480 u16 seq_number;
6481 u16 rate_flag = tx_info->control.rates[0].flags;
6482 int ret;
6483
6484 if (skb_headroom(skb) < sizeof(struct rtl8xxxu_tx_desc)) {
6485 dev_warn(dev,
6486 "%s: Not enough headroom (%i) for tx descriptor\n",
6487 __func__, skb_headroom(skb));
6488 goto error;
6489 }
6490
6491 if (unlikely(skb->len > (65535 - sizeof(struct rtl8xxxu_tx_desc)))) {
6492 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",
6493 __func__, skb->len);
6494 goto error;
6495 }
6496
6497 tx_urb = rtl8xxxu_alloc_tx_urb(priv);
6498 if (!tx_urb) {
6499 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);
6500 goto error;
6501 }
6502
6503 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
6504 dev_info(dev, "%s: TX rate: %d (%d), pkt size %d\n",
6505 __func__, tx_rate->bitrate, tx_rate->hw_value, pktlen);
6506
6507 if (ieee80211_is_action(hdr->frame_control))
6508 rtl8xxxu_dump_action(dev, hdr);
6509
6510 tx_info->rate_driver_data[0] = hw;
6511
6512 if (control && control->sta)
6513 sta = control->sta;
6514
6515 tx_desc = (struct rtl8xxxu_tx_desc *)
6516 skb_push(skb, sizeof(struct rtl8xxxu_tx_desc));
6517
6518 memset(tx_desc, 0, sizeof(struct rtl8xxxu_tx_desc));
6519 tx_desc->pkt_size = cpu_to_le16(pktlen);
6520 tx_desc->pkt_offset = sizeof(struct rtl8xxxu_tx_desc);
6521
6522 tx_desc->txdw0 =
6523 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
6524 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
6525 is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
6526 tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
6527
6528 queue = rtl8xxxu_queue_select(hw, skb);
6529 tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
6530
6531 if (tx_info->control.hw_key) {
6532 switch (tx_info->control.hw_key->cipher) {
6533 case WLAN_CIPHER_SUITE_WEP40:
6534 case WLAN_CIPHER_SUITE_WEP104:
6535 case WLAN_CIPHER_SUITE_TKIP:
6536 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
6537 break;
6538 case WLAN_CIPHER_SUITE_CCMP:
6539 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
6540 break;
6541 default:
6542 break;
6543 }
6544 }
6545
6546 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
6547 tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC_SEQ_SHIFT);
6548
6549 if (rate_flag & IEEE80211_TX_RC_MCS)
6550 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
6551 else
6552 rate = tx_rate->hw_value;
6553 tx_desc->txdw5 = cpu_to_le32(rate);
6554
6555 if (ieee80211_is_data(hdr->frame_control))
6556 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
6557
6558 /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
6559 if (ieee80211_is_data_qos(hdr->frame_control) && sta) {
6560 if (sta->ht_cap.ht_supported) {
6561 u32 ampdu, val32;
6562
6563 ampdu = (u32)sta->ht_cap.ampdu_density;
6564 val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;
6565 tx_desc->txdw2 |= cpu_to_le32(val32);
6566 tx_desc->txdw1 |= cpu_to_le32(TXDESC_AGG_ENABLE);
6567 } else
6568 tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
6569 } else
6570 tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
6571
6572 if (ieee80211_is_data_qos(hdr->frame_control))
6573 tx_desc->txdw4 |= cpu_to_le32(TXDESC_QOS);
6574 if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
6575 (sta && vif && vif->bss_conf.use_short_preamble))
6576 tx_desc->txdw4 |= cpu_to_le32(TXDESC_SHORT_PREAMBLE);
6577 if (rate_flag & IEEE80211_TX_RC_SHORT_GI ||
6578 (ieee80211_is_data_qos(hdr->frame_control) &&
6579 sta && sta->ht_cap.cap &
6580 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))) {
6581 tx_desc->txdw5 |= cpu_to_le32(TXDESC_SHORT_GI);
6582 }
6583 if (ieee80211_is_mgmt(hdr->frame_control)) {
6584 tx_desc->txdw5 = cpu_to_le32(tx_rate->hw_value);
6585 tx_desc->txdw4 |= cpu_to_le32(TXDESC_USE_DRIVER_RATE);
6586 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC_RETRY_LIMIT_SHIFT);
6587 tx_desc->txdw5 |= cpu_to_le32(TXDESC_RETRY_LIMIT_ENABLE);
6588 }
6589
6590 if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
6591 /* Use RTS rate 24M - does the mac80211 tell us which to use? */
6592 tx_desc->txdw4 |= cpu_to_le32(DESC_RATE_24M);
6593 tx_desc->txdw4 |= cpu_to_le32(TXDESC_RTS_CTS_ENABLE);
6594 tx_desc->txdw4 |= cpu_to_le32(TXDESC_HW_RTS_ENABLE);
6595 }
6596
6597 rtl8xxxu_calc_tx_desc_csum(tx_desc);
6598
6599 usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
6600 skb->data, skb->len, rtl8xxxu_tx_complete, skb);
6601
6602 usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);
6603 ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);
6604 if (ret) {
6605 usb_unanchor_urb(&tx_urb->urb);
6606 rtl8xxxu_free_tx_urb(priv, tx_urb);
6607 goto error;
6608 }
6609 return;
6610 error:
6611 dev_kfree_skb(skb);
6612 }
6613
6614 static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv,
6615 struct ieee80211_rx_status *rx_status,
6616 struct rtl8xxxu_rx_desc *rx_desc,
6617 struct rtl8723au_phy_stats *phy_stats)
6618 {
6619 if (phy_stats->sgi_en)
6620 rx_status->flag |= RX_FLAG_SHORT_GI;
6621
6622 if (rx_desc->rxmcs < DESC_RATE_6M) {
6623 /*
6624 * Handle PHY stats for CCK rates
6625 */
6626 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
6627
6628 switch (cck_agc_rpt & 0xc0) {
6629 case 0xc0:
6630 rx_status->signal = -46 - (cck_agc_rpt & 0x3e);
6631 break;
6632 case 0x80:
6633 rx_status->signal = -26 - (cck_agc_rpt & 0x3e);
6634 break;
6635 case 0x40:
6636 rx_status->signal = -12 - (cck_agc_rpt & 0x3e);
6637 break;
6638 case 0x00:
6639 rx_status->signal = 16 - (cck_agc_rpt & 0x3e);
6640 break;
6641 }
6642 } else {
6643 rx_status->signal =
6644 (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;
6645 }
6646 }
6647
6648 static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)
6649 {
6650 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
6651 unsigned long flags;
6652
6653 spin_lock_irqsave(&priv->rx_urb_lock, flags);
6654
6655 list_for_each_entry_safe(rx_urb, tmp,
6656 &priv->rx_urb_pending_list, list) {
6657 list_del(&rx_urb->list);
6658 priv->rx_urb_pending_count--;
6659 usb_free_urb(&rx_urb->urb);
6660 }
6661
6662 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
6663 }
6664
6665 static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,
6666 struct rtl8xxxu_rx_urb *rx_urb)
6667 {
6668 struct sk_buff *skb;
6669 unsigned long flags;
6670 int pending = 0;
6671
6672 spin_lock_irqsave(&priv->rx_urb_lock, flags);
6673
6674 if (!priv->shutdown) {
6675 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);
6676 priv->rx_urb_pending_count++;
6677 pending = priv->rx_urb_pending_count;
6678 } else {
6679 skb = (struct sk_buff *)rx_urb->urb.context;
6680 dev_kfree_skb(skb);
6681 usb_free_urb(&rx_urb->urb);
6682 }
6683
6684 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
6685
6686 if (pending > RTL8XXXU_RX_URB_PENDING_WATER)
6687 schedule_work(&priv->rx_urb_wq);
6688 }
6689
6690 static void rtl8xxxu_rx_urb_work(struct work_struct *work)
6691 {
6692 struct rtl8xxxu_priv *priv;
6693 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
6694 struct list_head local;
6695 struct sk_buff *skb;
6696 unsigned long flags;
6697 int ret;
6698
6699 priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);
6700 INIT_LIST_HEAD(&local);
6701
6702 spin_lock_irqsave(&priv->rx_urb_lock, flags);
6703
6704 list_splice_init(&priv->rx_urb_pending_list, &local);
6705 priv->rx_urb_pending_count = 0;
6706
6707 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
6708
6709 list_for_each_entry_safe(rx_urb, tmp, &local, list) {
6710 list_del_init(&rx_urb->list);
6711 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
6712 /*
6713 * If out of memory or temporary error, put it back on the
6714 * queue and try again. Otherwise the device is dead/gone
6715 * and we should drop it.
6716 */
6717 switch (ret) {
6718 case 0:
6719 break;
6720 case -ENOMEM:
6721 case -EAGAIN:
6722 rtl8xxxu_queue_rx_urb(priv, rx_urb);
6723 break;
6724 default:
6725 pr_info("failed to requeue urb %i\n", ret);
6726 skb = (struct sk_buff *)rx_urb->urb.context;
6727 dev_kfree_skb(skb);
6728 usb_free_urb(&rx_urb->urb);
6729 }
6730 }
6731 }
6732
6733 static int rtl8723au_parse_rx_desc(struct rtl8xxxu_priv *priv,
6734 struct sk_buff *skb,
6735 struct ieee80211_rx_status *rx_status)
6736 {
6737 struct rtl8xxxu_rx_desc *rx_desc = (struct rtl8xxxu_rx_desc *)skb->data;
6738 struct rtl8723au_phy_stats *phy_stats;
6739 int drvinfo_sz, desc_shift;
6740
6741 skb_pull(skb, sizeof(struct rtl8xxxu_rx_desc));
6742
6743 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
6744
6745 drvinfo_sz = rx_desc->drvinfo_sz * 8;
6746 desc_shift = rx_desc->shift;
6747 skb_pull(skb, drvinfo_sz + desc_shift);
6748
6749 if (rx_desc->phy_stats)
6750 rtl8xxxu_rx_parse_phystats(priv, rx_status, rx_desc, phy_stats);
6751
6752 rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
6753 rx_status->flag |= RX_FLAG_MACTIME_START;
6754
6755 if (!rx_desc->swdec)
6756 rx_status->flag |= RX_FLAG_DECRYPTED;
6757 if (rx_desc->crc32)
6758 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
6759 if (rx_desc->bw)
6760 rx_status->flag |= RX_FLAG_40MHZ;
6761
6762 if (rx_desc->rxht) {
6763 rx_status->flag |= RX_FLAG_HT;
6764 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
6765 } else {
6766 rx_status->rate_idx = rx_desc->rxmcs;
6767 }
6768
6769 return RX_TYPE_DATA_PKT;
6770 }
6771
6772 static int rtl8723bu_parse_rx_desc(struct rtl8xxxu_priv *priv,
6773 struct sk_buff *skb,
6774 struct ieee80211_rx_status *rx_status)
6775 {
6776 struct rtl8723bu_rx_desc *rx_desc =
6777 (struct rtl8723bu_rx_desc *)skb->data;
6778 struct rtl8723au_phy_stats *phy_stats;
6779 int drvinfo_sz, desc_shift;
6780 int rx_type;
6781
6782 skb_pull(skb, sizeof(struct rtl8723bu_rx_desc));
6783
6784 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
6785
6786 drvinfo_sz = rx_desc->drvinfo_sz * 8;
6787 desc_shift = rx_desc->shift;
6788 skb_pull(skb, drvinfo_sz + desc_shift);
6789
6790 rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
6791 rx_status->flag |= RX_FLAG_MACTIME_START;
6792
6793 if (!rx_desc->swdec)
6794 rx_status->flag |= RX_FLAG_DECRYPTED;
6795 if (rx_desc->crc32)
6796 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
6797 if (rx_desc->bw)
6798 rx_status->flag |= RX_FLAG_40MHZ;
6799
6800 if (rx_desc->rxmcs >= DESC_RATE_MCS0) {
6801 rx_status->flag |= RX_FLAG_HT;
6802 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
6803 } else {
6804 rx_status->rate_idx = rx_desc->rxmcs;
6805 }
6806
6807 if (rx_desc->rpt_sel) {
6808 struct device *dev = &priv->udev->dev;
6809 dev_dbg(dev, "%s: C2H packet\n", __func__);
6810 rx_type = RX_TYPE_C2H;
6811 } else {
6812 rx_type = RX_TYPE_DATA_PKT;
6813 }
6814
6815 return rx_type;
6816 }
6817
6818 static void rtl8xxxu_rx_complete(struct urb *urb)
6819 {
6820 struct rtl8xxxu_rx_urb *rx_urb =
6821 container_of(urb, struct rtl8xxxu_rx_urb, urb);
6822 struct ieee80211_hw *hw = rx_urb->hw;
6823 struct rtl8xxxu_priv *priv = hw->priv;
6824 struct sk_buff *skb = (struct sk_buff *)urb->context;
6825 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
6826 struct device *dev = &priv->udev->dev;
6827 __le32 *_rx_desc_le = (__le32 *)skb->data;
6828 u32 *_rx_desc = (u32 *)skb->data;
6829 int rx_type, i;
6830
6831 for (i = 0; i < (sizeof(struct rtl8xxxu_rx_desc) / sizeof(u32)); i++)
6832 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
6833
6834 skb_put(skb, urb->actual_length);
6835
6836 if (urb->status == 0) {
6837 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
6838
6839 rx_type = priv->fops->parse_rx_desc(priv, skb, rx_status);
6840
6841 rx_status->freq = hw->conf.chandef.chan->center_freq;
6842 rx_status->band = hw->conf.chandef.chan->band;
6843
6844 if (rx_type == RX_TYPE_DATA_PKT)
6845 ieee80211_rx_irqsafe(hw, skb);
6846 else
6847 dev_kfree_skb(skb);
6848
6849 skb = NULL;
6850 rx_urb->urb.context = NULL;
6851 rtl8xxxu_queue_rx_urb(priv, rx_urb);
6852 } else {
6853 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
6854 goto cleanup;
6855 }
6856 return;
6857
6858 cleanup:
6859 usb_free_urb(urb);
6860 dev_kfree_skb(skb);
6861 return;
6862 }
6863
6864 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
6865 struct rtl8xxxu_rx_urb *rx_urb)
6866 {
6867 struct sk_buff *skb;
6868 int skb_size;
6869 int ret;
6870
6871 skb_size = sizeof(struct rtl8xxxu_rx_desc) + RTL_RX_BUFFER_SIZE;
6872 skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);
6873 if (!skb)
6874 return -ENOMEM;
6875
6876 memset(skb->data, 0, sizeof(struct rtl8xxxu_rx_desc));
6877 usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,
6878 skb_size, rtl8xxxu_rx_complete, skb);
6879 usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);
6880 ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);
6881 if (ret)
6882 usb_unanchor_urb(&rx_urb->urb);
6883 return ret;
6884 }
6885
6886 static void rtl8xxxu_int_complete(struct urb *urb)
6887 {
6888 struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;
6889 struct device *dev = &priv->udev->dev;
6890 int ret;
6891
6892 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
6893 if (urb->status == 0) {
6894 usb_anchor_urb(urb, &priv->int_anchor);
6895 ret = usb_submit_urb(urb, GFP_ATOMIC);
6896 if (ret)
6897 usb_unanchor_urb(urb);
6898 } else {
6899 dev_info(dev, "%s: Error %i\n", __func__, urb->status);
6900 }
6901 }
6902
6903
6904 static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
6905 {
6906 struct rtl8xxxu_priv *priv = hw->priv;
6907 struct urb *urb;
6908 u32 val32;
6909 int ret;
6910
6911 urb = usb_alloc_urb(0, GFP_KERNEL);
6912 if (!urb)
6913 return -ENOMEM;
6914
6915 usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,
6916 priv->int_buf, USB_INTR_CONTENT_LENGTH,
6917 rtl8xxxu_int_complete, priv, 1);
6918 usb_anchor_urb(urb, &priv->int_anchor);
6919 ret = usb_submit_urb(urb, GFP_KERNEL);
6920 if (ret) {
6921 usb_unanchor_urb(urb);
6922 goto error;
6923 }
6924
6925 val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
6926 val32 |= USB_HIMR_CPWM;
6927 rtl8xxxu_write32(priv, REG_USB_HIMR, val32);
6928
6929 error:
6930 return ret;
6931 }
6932
6933 static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
6934 struct ieee80211_vif *vif)
6935 {
6936 struct rtl8xxxu_priv *priv = hw->priv;
6937 int ret;
6938 u8 val8;
6939
6940 switch (vif->type) {
6941 case NL80211_IFTYPE_STATION:
6942 rtl8723a_stop_tx_beacon(priv);
6943
6944 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6945 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |
6946 BEACON_DISABLE_TSF_UPDATE;
6947 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
6948 ret = 0;
6949 break;
6950 default:
6951 ret = -EOPNOTSUPP;
6952 }
6953
6954 rtl8xxxu_set_linktype(priv, vif->type);
6955
6956 return ret;
6957 }
6958
6959 static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,
6960 struct ieee80211_vif *vif)
6961 {
6962 struct rtl8xxxu_priv *priv = hw->priv;
6963
6964 dev_dbg(&priv->udev->dev, "%s\n", __func__);
6965 }
6966
6967 static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed)
6968 {
6969 struct rtl8xxxu_priv *priv = hw->priv;
6970 struct device *dev = &priv->udev->dev;
6971 u16 val16;
6972 int ret = 0, channel;
6973 bool ht40;
6974
6975 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
6976 dev_info(dev,
6977 "%s: channel: %i (changed %08x chandef.width %02x)\n",
6978 __func__, hw->conf.chandef.chan->hw_value,
6979 changed, hw->conf.chandef.width);
6980
6981 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
6982 val16 = ((hw->conf.long_frame_max_tx_count <<
6983 RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) |
6984 ((hw->conf.short_frame_max_tx_count <<
6985 RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK);
6986 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
6987 }
6988
6989 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
6990 switch (hw->conf.chandef.width) {
6991 case NL80211_CHAN_WIDTH_20_NOHT:
6992 case NL80211_CHAN_WIDTH_20:
6993 ht40 = false;
6994 break;
6995 case NL80211_CHAN_WIDTH_40:
6996 ht40 = true;
6997 break;
6998 default:
6999 ret = -ENOTSUPP;
7000 goto exit;
7001 }
7002
7003 channel = hw->conf.chandef.chan->hw_value;
7004
7005 rtl8723a_set_tx_power(priv, channel, ht40);
7006
7007 rtl8723au_config_channel(hw);
7008 }
7009
7010 exit:
7011 return ret;
7012 }
7013
7014 static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,
7015 struct ieee80211_vif *vif, u16 queue,
7016 const struct ieee80211_tx_queue_params *param)
7017 {
7018 struct rtl8xxxu_priv *priv = hw->priv;
7019 struct device *dev = &priv->udev->dev;
7020 u32 val32;
7021 u8 aifs, acm_ctrl, acm_bit;
7022
7023 aifs = param->aifs;
7024
7025 val32 = aifs |
7026 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |
7027 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |
7028 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
7029
7030 acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);
7031 dev_dbg(dev,
7032 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
7033 __func__, queue, val32, param->acm, acm_ctrl);
7034
7035 switch (queue) {
7036 case IEEE80211_AC_VO:
7037 acm_bit = ACM_HW_CTRL_VO;
7038 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);
7039 break;
7040 case IEEE80211_AC_VI:
7041 acm_bit = ACM_HW_CTRL_VI;
7042 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);
7043 break;
7044 case IEEE80211_AC_BE:
7045 acm_bit = ACM_HW_CTRL_BE;
7046 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);
7047 break;
7048 case IEEE80211_AC_BK:
7049 acm_bit = ACM_HW_CTRL_BK;
7050 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);
7051 break;
7052 default:
7053 acm_bit = 0;
7054 break;
7055 }
7056
7057 if (param->acm)
7058 acm_ctrl |= acm_bit;
7059 else
7060 acm_ctrl &= ~acm_bit;
7061 rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);
7062
7063 return 0;
7064 }
7065
7066 static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
7067 unsigned int changed_flags,
7068 unsigned int *total_flags, u64 multicast)
7069 {
7070 struct rtl8xxxu_priv *priv = hw->priv;
7071 u32 rcr = rtl8xxxu_read32(priv, REG_RCR);
7072
7073 dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",
7074 __func__, changed_flags, *total_flags);
7075
7076 /*
7077 * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR)
7078 */
7079
7080 if (*total_flags & FIF_FCSFAIL)
7081 rcr |= RCR_ACCEPT_CRC32;
7082 else
7083 rcr &= ~RCR_ACCEPT_CRC32;
7084
7085 /*
7086 * FIF_PLCPFAIL not supported?
7087 */
7088
7089 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
7090 rcr &= ~RCR_CHECK_BSSID_BEACON;
7091 else
7092 rcr |= RCR_CHECK_BSSID_BEACON;
7093
7094 if (*total_flags & FIF_CONTROL)
7095 rcr |= RCR_ACCEPT_CTRL_FRAME;
7096 else
7097 rcr &= ~RCR_ACCEPT_CTRL_FRAME;
7098
7099 if (*total_flags & FIF_OTHER_BSS) {
7100 rcr |= RCR_ACCEPT_AP;
7101 rcr &= ~RCR_CHECK_BSSID_MATCH;
7102 } else {
7103 rcr &= ~RCR_ACCEPT_AP;
7104 rcr |= RCR_CHECK_BSSID_MATCH;
7105 }
7106
7107 if (*total_flags & FIF_PSPOLL)
7108 rcr |= RCR_ACCEPT_PM;
7109 else
7110 rcr &= ~RCR_ACCEPT_PM;
7111
7112 /*
7113 * FIF_PROBE_REQ ignored as probe requests always seem to be accepted
7114 */
7115
7116 rtl8xxxu_write32(priv, REG_RCR, rcr);
7117
7118 *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC |
7119 FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL |
7120 FIF_PROBE_REQ);
7121 }
7122
7123 static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)
7124 {
7125 if (rts > 2347)
7126 return -EINVAL;
7127
7128 return 0;
7129 }
7130
7131 static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
7132 struct ieee80211_vif *vif,
7133 struct ieee80211_sta *sta,
7134 struct ieee80211_key_conf *key)
7135 {
7136 struct rtl8xxxu_priv *priv = hw->priv;
7137 struct device *dev = &priv->udev->dev;
7138 u8 mac_addr[ETH_ALEN];
7139 u8 val8;
7140 u16 val16;
7141 u32 val32;
7142 int retval = -EOPNOTSUPP;
7143
7144 dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",
7145 __func__, cmd, key->cipher, key->keyidx);
7146
7147 if (vif->type != NL80211_IFTYPE_STATION)
7148 return -EOPNOTSUPP;
7149
7150 if (key->keyidx > 3)
7151 return -EOPNOTSUPP;
7152
7153 switch (key->cipher) {
7154 case WLAN_CIPHER_SUITE_WEP40:
7155 case WLAN_CIPHER_SUITE_WEP104:
7156
7157 break;
7158 case WLAN_CIPHER_SUITE_CCMP:
7159 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
7160 break;
7161 case WLAN_CIPHER_SUITE_TKIP:
7162 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
7163 default:
7164 return -EOPNOTSUPP;
7165 }
7166
7167 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
7168 dev_dbg(dev, "%s: pairwise key\n", __func__);
7169 ether_addr_copy(mac_addr, sta->addr);
7170 } else {
7171 dev_dbg(dev, "%s: group key\n", __func__);
7172 eth_broadcast_addr(mac_addr);
7173 }
7174
7175 val16 = rtl8xxxu_read16(priv, REG_CR);
7176 val16 |= CR_SECURITY_ENABLE;
7177 rtl8xxxu_write16(priv, REG_CR, val16);
7178
7179 val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |
7180 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;
7181 val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;
7182 rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);
7183
7184 switch (cmd) {
7185 case SET_KEY:
7186 key->hw_key_idx = key->keyidx;
7187 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
7188 rtl8xxxu_cam_write(priv, key, mac_addr);
7189 retval = 0;
7190 break;
7191 case DISABLE_KEY:
7192 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);
7193 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |
7194 key->keyidx << CAM_CMD_KEY_SHIFT;
7195 rtl8xxxu_write32(priv, REG_CAM_CMD, val32);
7196 retval = 0;
7197 break;
7198 default:
7199 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);
7200 }
7201
7202 return retval;
7203 }
7204
7205 static int
7206 rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
7207 struct ieee80211_ampdu_params *params)
7208 {
7209 struct rtl8xxxu_priv *priv = hw->priv;
7210 struct device *dev = &priv->udev->dev;
7211 u8 ampdu_factor, ampdu_density;
7212 struct ieee80211_sta *sta = params->sta;
7213 enum ieee80211_ampdu_mlme_action action = params->action;
7214
7215 switch (action) {
7216 case IEEE80211_AMPDU_TX_START:
7217 dev_info(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);
7218 ampdu_factor = sta->ht_cap.ampdu_factor;
7219 ampdu_density = sta->ht_cap.ampdu_density;
7220 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);
7221 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);
7222 dev_dbg(dev,
7223 "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
7224 ampdu_factor, ampdu_density);
7225 break;
7226 case IEEE80211_AMPDU_TX_STOP_FLUSH:
7227 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__);
7228 rtl8xxxu_set_ampdu_factor(priv, 0);
7229 rtl8xxxu_set_ampdu_min_space(priv, 0);
7230 break;
7231 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
7232 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n",
7233 __func__);
7234 rtl8xxxu_set_ampdu_factor(priv, 0);
7235 rtl8xxxu_set_ampdu_min_space(priv, 0);
7236 break;
7237 case IEEE80211_AMPDU_RX_START:
7238 dev_info(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);
7239 break;
7240 case IEEE80211_AMPDU_RX_STOP:
7241 dev_info(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);
7242 break;
7243 default:
7244 break;
7245 }
7246 return 0;
7247 }
7248
7249 static int rtl8xxxu_start(struct ieee80211_hw *hw)
7250 {
7251 struct rtl8xxxu_priv *priv = hw->priv;
7252 struct rtl8xxxu_rx_urb *rx_urb;
7253 struct rtl8xxxu_tx_urb *tx_urb;
7254 unsigned long flags;
7255 int ret, i;
7256
7257 ret = 0;
7258
7259 init_usb_anchor(&priv->rx_anchor);
7260 init_usb_anchor(&priv->tx_anchor);
7261 init_usb_anchor(&priv->int_anchor);
7262
7263 rtl8723a_enable_rf(priv);
7264 if (priv->usb_interrupts) {
7265 ret = rtl8xxxu_submit_int_urb(hw);
7266 if (ret)
7267 goto exit;
7268 }
7269
7270 for (i = 0; i < RTL8XXXU_TX_URBS; i++) {
7271 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);
7272 if (!tx_urb) {
7273 if (!i)
7274 ret = -ENOMEM;
7275
7276 goto error_out;
7277 }
7278 usb_init_urb(&tx_urb->urb);
7279 INIT_LIST_HEAD(&tx_urb->list);
7280 tx_urb->hw = hw;
7281 list_add(&tx_urb->list, &priv->tx_urb_free_list);
7282 priv->tx_urb_free_count++;
7283 }
7284
7285 priv->tx_stopped = false;
7286
7287 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7288 priv->shutdown = false;
7289 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7290
7291 for (i = 0; i < RTL8XXXU_RX_URBS; i++) {
7292 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);
7293 if (!rx_urb) {
7294 if (!i)
7295 ret = -ENOMEM;
7296
7297 goto error_out;
7298 }
7299 usb_init_urb(&rx_urb->urb);
7300 INIT_LIST_HEAD(&rx_urb->list);
7301 rx_urb->hw = hw;
7302
7303 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
7304 }
7305 exit:
7306 /*
7307 * Accept all data and mgmt frames
7308 */
7309 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
7310 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
7311
7312 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e);
7313
7314 return ret;
7315
7316 error_out:
7317 rtl8xxxu_free_tx_resources(priv);
7318 /*
7319 * Disable all data and mgmt frames
7320 */
7321 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
7322 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
7323
7324 return ret;
7325 }
7326
7327 static void rtl8xxxu_stop(struct ieee80211_hw *hw)
7328 {
7329 struct rtl8xxxu_priv *priv = hw->priv;
7330 unsigned long flags;
7331
7332 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
7333
7334 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
7335 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
7336
7337 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7338 priv->shutdown = true;
7339 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7340
7341 usb_kill_anchored_urbs(&priv->rx_anchor);
7342 usb_kill_anchored_urbs(&priv->tx_anchor);
7343 if (priv->usb_interrupts)
7344 usb_kill_anchored_urbs(&priv->int_anchor);
7345
7346 rtl8723a_disable_rf(priv);
7347
7348 /*
7349 * Disable interrupts
7350 */
7351 if (priv->usb_interrupts)
7352 rtl8xxxu_write32(priv, REG_USB_HIMR, 0);
7353
7354 rtl8xxxu_free_rx_resources(priv);
7355 rtl8xxxu_free_tx_resources(priv);
7356 }
7357
7358 static const struct ieee80211_ops rtl8xxxu_ops = {
7359 .tx = rtl8xxxu_tx,
7360 .add_interface = rtl8xxxu_add_interface,
7361 .remove_interface = rtl8xxxu_remove_interface,
7362 .config = rtl8xxxu_config,
7363 .conf_tx = rtl8xxxu_conf_tx,
7364 .bss_info_changed = rtl8xxxu_bss_info_changed,
7365 .configure_filter = rtl8xxxu_configure_filter,
7366 .set_rts_threshold = rtl8xxxu_set_rts_threshold,
7367 .start = rtl8xxxu_start,
7368 .stop = rtl8xxxu_stop,
7369 .sw_scan_start = rtl8xxxu_sw_scan_start,
7370 .sw_scan_complete = rtl8xxxu_sw_scan_complete,
7371 .set_key = rtl8xxxu_set_key,
7372 .ampdu_action = rtl8xxxu_ampdu_action,
7373 };
7374
7375 static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
7376 struct usb_interface *interface)
7377 {
7378 struct usb_interface_descriptor *interface_desc;
7379 struct usb_host_interface *host_interface;
7380 struct usb_endpoint_descriptor *endpoint;
7381 struct device *dev = &priv->udev->dev;
7382 int i, j = 0, endpoints;
7383 u8 dir, xtype, num;
7384 int ret = 0;
7385
7386 host_interface = &interface->altsetting[0];
7387 interface_desc = &host_interface->desc;
7388 endpoints = interface_desc->bNumEndpoints;
7389
7390 for (i = 0; i < endpoints; i++) {
7391 endpoint = &host_interface->endpoint[i].desc;
7392
7393 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
7394 num = usb_endpoint_num(endpoint);
7395 xtype = usb_endpoint_type(endpoint);
7396 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7397 dev_dbg(dev,
7398 "%s: endpoint: dir %02x, # %02x, type %02x\n",
7399 __func__, dir, num, xtype);
7400 if (usb_endpoint_dir_in(endpoint) &&
7401 usb_endpoint_xfer_bulk(endpoint)) {
7402 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7403 dev_dbg(dev, "%s: in endpoint num %i\n",
7404 __func__, num);
7405
7406 if (priv->pipe_in) {
7407 dev_warn(dev,
7408 "%s: Too many IN pipes\n", __func__);
7409 ret = -EINVAL;
7410 goto exit;
7411 }
7412
7413 priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);
7414 }
7415
7416 if (usb_endpoint_dir_in(endpoint) &&
7417 usb_endpoint_xfer_int(endpoint)) {
7418 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7419 dev_dbg(dev, "%s: interrupt endpoint num %i\n",
7420 __func__, num);
7421
7422 if (priv->pipe_interrupt) {
7423 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",
7424 __func__);
7425 ret = -EINVAL;
7426 goto exit;
7427 }
7428
7429 priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);
7430 }
7431
7432 if (usb_endpoint_dir_out(endpoint) &&
7433 usb_endpoint_xfer_bulk(endpoint)) {
7434 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7435 dev_dbg(dev, "%s: out endpoint num %i\n",
7436 __func__, num);
7437 if (j >= RTL8XXXU_OUT_ENDPOINTS) {
7438 dev_warn(dev,
7439 "%s: Too many OUT pipes\n", __func__);
7440 ret = -EINVAL;
7441 goto exit;
7442 }
7443 priv->out_ep[j++] = num;
7444 }
7445 }
7446 exit:
7447 priv->nr_out_eps = j;
7448 return ret;
7449 }
7450
7451 static int rtl8xxxu_probe(struct usb_interface *interface,
7452 const struct usb_device_id *id)
7453 {
7454 struct rtl8xxxu_priv *priv;
7455 struct ieee80211_hw *hw;
7456 struct usb_device *udev;
7457 struct ieee80211_supported_band *sband;
7458 int ret = 0;
7459 int untested = 1;
7460
7461 udev = usb_get_dev(interface_to_usbdev(interface));
7462
7463 switch (id->idVendor) {
7464 case USB_VENDOR_ID_REALTEK:
7465 switch(id->idProduct) {
7466 case 0x1724:
7467 case 0x8176:
7468 case 0x8178:
7469 case 0x817f:
7470 untested = 0;
7471 break;
7472 }
7473 break;
7474 case 0x7392:
7475 if (id->idProduct == 0x7811)
7476 untested = 0;
7477 break;
7478 default:
7479 break;
7480 }
7481
7482 if (untested) {
7483 rtl8xxxu_debug |= RTL8XXXU_DEBUG_EFUSE;
7484 dev_info(&udev->dev,
7485 "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
7486 id->idVendor, id->idProduct);
7487 dev_info(&udev->dev,
7488 "Please report results to Jes.Sorensen@gmail.com\n");
7489 }
7490
7491 hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
7492 if (!hw) {
7493 ret = -ENOMEM;
7494 goto exit;
7495 }
7496
7497 priv = hw->priv;
7498 priv->hw = hw;
7499 priv->udev = udev;
7500 priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;
7501 mutex_init(&priv->usb_buf_mutex);
7502 mutex_init(&priv->h2c_mutex);
7503 INIT_LIST_HEAD(&priv->tx_urb_free_list);
7504 spin_lock_init(&priv->tx_urb_lock);
7505 INIT_LIST_HEAD(&priv->rx_urb_pending_list);
7506 spin_lock_init(&priv->rx_urb_lock);
7507 INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
7508
7509 usb_set_intfdata(interface, hw);
7510
7511 ret = rtl8xxxu_parse_usb(priv, interface);
7512 if (ret)
7513 goto exit;
7514
7515 ret = rtl8xxxu_identify_chip(priv);
7516 if (ret) {
7517 dev_err(&udev->dev, "Fatal - failed to identify chip\n");
7518 goto exit;
7519 }
7520
7521 ret = rtl8xxxu_read_efuse(priv);
7522 if (ret) {
7523 dev_err(&udev->dev, "Fatal - failed to read EFuse\n");
7524 goto exit;
7525 }
7526
7527 ret = priv->fops->parse_efuse(priv);
7528 if (ret) {
7529 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
7530 goto exit;
7531 }
7532
7533 rtl8xxxu_print_chipinfo(priv);
7534
7535 ret = priv->fops->load_firmware(priv);
7536 if (ret) {
7537 dev_err(&udev->dev, "Fatal - failed to load firmware\n");
7538 goto exit;
7539 }
7540
7541 ret = rtl8xxxu_init_device(hw);
7542
7543 hw->wiphy->max_scan_ssids = 1;
7544 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
7545 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
7546 hw->queues = 4;
7547
7548 sband = &rtl8xxxu_supported_band;
7549 sband->ht_cap.ht_supported = true;
7550 sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
7551 sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
7552 sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
7553 memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
7554 sband->ht_cap.mcs.rx_mask[0] = 0xff;
7555 sband->ht_cap.mcs.rx_mask[4] = 0x01;
7556 if (priv->rf_paths > 1) {
7557 sband->ht_cap.mcs.rx_mask[1] = 0xff;
7558 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
7559 }
7560 sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
7561 /*
7562 * Some APs will negotiate HT20_40 in a noisy environment leading
7563 * to miserable performance. Rather than defaulting to this, only
7564 * enable it if explicitly requested at module load time.
7565 */
7566 if (rtl8xxxu_ht40_2g) {
7567 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
7568 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
7569 }
7570 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
7571
7572 hw->wiphy->rts_threshold = 2347;
7573
7574 SET_IEEE80211_DEV(priv->hw, &interface->dev);
7575 SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);
7576
7577 hw->extra_tx_headroom = sizeof(struct rtl8xxxu_tx_desc);
7578 ieee80211_hw_set(hw, SIGNAL_DBM);
7579 /*
7580 * The firmware handles rate control
7581 */
7582 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
7583 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
7584
7585 ret = ieee80211_register_hw(priv->hw);
7586 if (ret) {
7587 dev_err(&udev->dev, "%s: Failed to register: %i\n",
7588 __func__, ret);
7589 goto exit;
7590 }
7591
7592 exit:
7593 if (ret < 0)
7594 usb_put_dev(udev);
7595 return ret;
7596 }
7597
7598 static void rtl8xxxu_disconnect(struct usb_interface *interface)
7599 {
7600 struct rtl8xxxu_priv *priv;
7601 struct ieee80211_hw *hw;
7602
7603 hw = usb_get_intfdata(interface);
7604 priv = hw->priv;
7605
7606 rtl8xxxu_disable_device(hw);
7607 usb_set_intfdata(interface, NULL);
7608
7609 dev_info(&priv->udev->dev, "disconnecting\n");
7610
7611 ieee80211_unregister_hw(hw);
7612
7613 kfree(priv->fw_data);
7614 mutex_destroy(&priv->usb_buf_mutex);
7615 mutex_destroy(&priv->h2c_mutex);
7616
7617 usb_put_dev(priv->udev);
7618 ieee80211_free_hw(hw);
7619 }
7620
7621 static struct rtl8xxxu_fileops rtl8723au_fops = {
7622 .parse_efuse = rtl8723au_parse_efuse,
7623 .load_firmware = rtl8723au_load_firmware,
7624 .power_on = rtl8723au_power_on,
7625 .llt_init = rtl8xxxu_init_llt_table,
7626 .phy_iq_calibrate = rtl8723au_phy_iq_calibrate,
7627 .config_channel = rtl8723au_config_channel,
7628 .parse_rx_desc = rtl8723au_parse_rx_desc,
7629 .writeN_block_size = 1024,
7630 .mbox_ext_reg = REG_HMBOX_EXT_0,
7631 .mbox_ext_width = 2,
7632 .adda_1t_init = 0x0b1b25a0,
7633 .adda_1t_path_on = 0x0bdb25a0,
7634 .adda_2t_path_on_a = 0x04db25a4,
7635 .adda_2t_path_on_b = 0x0b1b25a4,
7636 };
7637
7638 static struct rtl8xxxu_fileops rtl8723bu_fops = {
7639 .parse_efuse = rtl8723bu_parse_efuse,
7640 .load_firmware = rtl8723bu_load_firmware,
7641 .power_on = rtl8723au_power_on,
7642 .llt_init = rtl8xxxu_auto_llt_table,
7643 .phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection,
7644 .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate,
7645 .config_channel = rtl8723bu_config_channel,
7646 .init_bt = rtl8723bu_init_bt,
7647 .parse_rx_desc = rtl8723bu_parse_rx_desc,
7648 .writeN_block_size = 1024,
7649 .mbox_ext_reg = REG_HMBOX_EXT0_8723B,
7650 .mbox_ext_width = 4,
7651 .has_s0s1 = 1,
7652 .adda_1t_init = 0x01c00014,
7653 .adda_1t_path_on = 0x01c00014,
7654 .adda_2t_path_on_a = 0x01c00014,
7655 .adda_2t_path_on_b = 0x01c00014,
7656 };
7657
7658 #ifdef CONFIG_RTL8XXXU_UNTESTED
7659
7660 static struct rtl8xxxu_fileops rtl8192cu_fops = {
7661 .parse_efuse = rtl8192cu_parse_efuse,
7662 .load_firmware = rtl8192cu_load_firmware,
7663 .power_on = rtl8192cu_power_on,
7664 .llt_init = rtl8xxxu_init_llt_table,
7665 .phy_iq_calibrate = rtl8723au_phy_iq_calibrate,
7666 .config_channel = rtl8723au_config_channel,
7667 .parse_rx_desc = rtl8723au_parse_rx_desc,
7668 .writeN_block_size = 128,
7669 .mbox_ext_reg = REG_HMBOX_EXT_0,
7670 .mbox_ext_width = 2,
7671 .adda_1t_init = 0x0b1b25a0,
7672 .adda_1t_path_on = 0x0bdb25a0,
7673 .adda_2t_path_on_a = 0x04db25a4,
7674 .adda_2t_path_on_b = 0x0b1b25a4,
7675 };
7676
7677 #endif
7678
7679 static struct rtl8xxxu_fileops rtl8192eu_fops = {
7680 .parse_efuse = rtl8192eu_parse_efuse,
7681 .load_firmware = rtl8192eu_load_firmware,
7682 .power_on = rtl8192eu_power_on,
7683 .llt_init = rtl8xxxu_auto_llt_table,
7684 .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate,
7685 .config_channel = rtl8723bu_config_channel,
7686 .parse_rx_desc = rtl8723bu_parse_rx_desc,
7687 .writeN_block_size = 128,
7688 .mbox_ext_reg = REG_HMBOX_EXT0_8723B,
7689 .mbox_ext_width = 4,
7690 .has_s0s1 = 1,
7691 .adda_1t_init = 0x0fc01616,
7692 .adda_1t_path_on = 0x0fc01616,
7693 .adda_2t_path_on_a = 0x0fc01616,
7694 .adda_2t_path_on_b = 0x0fc01616,
7695 };
7696
7697 static struct usb_device_id dev_table[] = {
7698 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),
7699 .driver_info = (unsigned long)&rtl8723au_fops},
7700 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),
7701 .driver_info = (unsigned long)&rtl8723au_fops},
7702 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),
7703 .driver_info = (unsigned long)&rtl8723au_fops},
7704 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff),
7705 .driver_info = (unsigned long)&rtl8192eu_fops},
7706 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff),
7707 .driver_info = (unsigned long)&rtl8723bu_fops},
7708 #ifdef CONFIG_RTL8XXXU_UNTESTED
7709 /* Still supported by rtlwifi */
7710 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
7711 .driver_info = (unsigned long)&rtl8192cu_fops},
7712 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),
7713 .driver_info = (unsigned long)&rtl8192cu_fops},
7714 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),
7715 .driver_info = (unsigned long)&rtl8192cu_fops},
7716 /* Tested by Larry Finger */
7717 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
7718 .driver_info = (unsigned long)&rtl8192cu_fops},
7719 /* Currently untested 8188 series devices */
7720 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),
7721 .driver_info = (unsigned long)&rtl8192cu_fops},
7722 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),
7723 .driver_info = (unsigned long)&rtl8192cu_fops},
7724 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),
7725 .driver_info = (unsigned long)&rtl8192cu_fops},
7726 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),
7727 .driver_info = (unsigned long)&rtl8192cu_fops},
7728 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),
7729 .driver_info = (unsigned long)&rtl8192cu_fops},
7730 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),
7731 .driver_info = (unsigned long)&rtl8192cu_fops},
7732 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),
7733 .driver_info = (unsigned long)&rtl8192cu_fops},
7734 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),
7735 .driver_info = (unsigned long)&rtl8192cu_fops},
7736 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
7737 .driver_info = (unsigned long)&rtl8192cu_fops},
7738 {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
7739 .driver_info = (unsigned long)&rtl8192cu_fops},
7740 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
7741 .driver_info = (unsigned long)&rtl8192cu_fops},
7742 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
7743 .driver_info = (unsigned long)&rtl8192cu_fops},
7744 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
7745 .driver_info = (unsigned long)&rtl8192cu_fops},
7746 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
7747 .driver_info = (unsigned long)&rtl8192cu_fops},
7748 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
7749 .driver_info = (unsigned long)&rtl8192cu_fops},
7750 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
7751 .driver_info = (unsigned long)&rtl8192cu_fops},
7752 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),
7753 .driver_info = (unsigned long)&rtl8192cu_fops},
7754 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),
7755 .driver_info = (unsigned long)&rtl8192cu_fops},
7756 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
7757 .driver_info = (unsigned long)&rtl8192cu_fops},
7758 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
7759 .driver_info = (unsigned long)&rtl8192cu_fops},
7760 {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
7761 .driver_info = (unsigned long)&rtl8192cu_fops},
7762 {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
7763 .driver_info = (unsigned long)&rtl8192cu_fops},
7764 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
7765 .driver_info = (unsigned long)&rtl8192cu_fops},
7766 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
7767 .driver_info = (unsigned long)&rtl8192cu_fops},
7768 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
7769 .driver_info = (unsigned long)&rtl8192cu_fops},
7770 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
7771 .driver_info = (unsigned long)&rtl8192cu_fops},
7772 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
7773 .driver_info = (unsigned long)&rtl8192cu_fops},
7774 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
7775 .driver_info = (unsigned long)&rtl8192cu_fops},
7776 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
7777 .driver_info = (unsigned long)&rtl8192cu_fops},
7778 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
7779 .driver_info = (unsigned long)&rtl8192cu_fops},
7780 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
7781 .driver_info = (unsigned long)&rtl8192cu_fops},
7782 {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
7783 .driver_info = (unsigned long)&rtl8192cu_fops},
7784 {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
7785 .driver_info = (unsigned long)&rtl8192cu_fops},
7786 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
7787 .driver_info = (unsigned long)&rtl8192cu_fops},
7788 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
7789 .driver_info = (unsigned long)&rtl8192cu_fops},
7790 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
7791 .driver_info = (unsigned long)&rtl8192cu_fops},
7792 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
7793 .driver_info = (unsigned long)&rtl8192cu_fops},
7794 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
7795 .driver_info = (unsigned long)&rtl8192cu_fops},
7796 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
7797 .driver_info = (unsigned long)&rtl8192cu_fops},
7798 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
7799 .driver_info = (unsigned long)&rtl8192cu_fops},
7800 /* Currently untested 8192 series devices */
7801 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
7802 .driver_info = (unsigned long)&rtl8192cu_fops},
7803 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
7804 .driver_info = (unsigned long)&rtl8192cu_fops},
7805 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
7806 .driver_info = (unsigned long)&rtl8192cu_fops},
7807 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
7808 .driver_info = (unsigned long)&rtl8192cu_fops},
7809 {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
7810 .driver_info = (unsigned long)&rtl8192cu_fops},
7811 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
7812 .driver_info = (unsigned long)&rtl8192cu_fops},
7813 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
7814 .driver_info = (unsigned long)&rtl8192cu_fops},
7815 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
7816 .driver_info = (unsigned long)&rtl8192cu_fops},
7817 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
7818 .driver_info = (unsigned long)&rtl8192cu_fops},
7819 {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
7820 .driver_info = (unsigned long)&rtl8192cu_fops},
7821 {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
7822 .driver_info = (unsigned long)&rtl8192cu_fops},
7823 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
7824 .driver_info = (unsigned long)&rtl8192cu_fops},
7825 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
7826 .driver_info = (unsigned long)&rtl8192cu_fops},
7827 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
7828 .driver_info = (unsigned long)&rtl8192cu_fops},
7829 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),
7830 .driver_info = (unsigned long)&rtl8192cu_fops},
7831 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
7832 .driver_info = (unsigned long)&rtl8192cu_fops},
7833 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
7834 .driver_info = (unsigned long)&rtl8192cu_fops},
7835 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
7836 .driver_info = (unsigned long)&rtl8192cu_fops},
7837 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
7838 .driver_info = (unsigned long)&rtl8192cu_fops},
7839 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
7840 .driver_info = (unsigned long)&rtl8192cu_fops},
7841 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
7842 .driver_info = (unsigned long)&rtl8192cu_fops},
7843 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
7844 .driver_info = (unsigned long)&rtl8192cu_fops},
7845 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
7846 .driver_info = (unsigned long)&rtl8192cu_fops},
7847 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
7848 .driver_info = (unsigned long)&rtl8192cu_fops},
7849 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
7850 .driver_info = (unsigned long)&rtl8192cu_fops},
7851 #endif
7852 { }
7853 };
7854
7855 static struct usb_driver rtl8xxxu_driver = {
7856 .name = DRIVER_NAME,
7857 .probe = rtl8xxxu_probe,
7858 .disconnect = rtl8xxxu_disconnect,
7859 .id_table = dev_table,
7860 .disable_hub_initiated_lpm = 1,
7861 };
7862
7863 static int __init rtl8xxxu_module_init(void)
7864 {
7865 int res;
7866
7867 res = usb_register(&rtl8xxxu_driver);
7868 if (res < 0)
7869 pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res);
7870
7871 return res;
7872 }
7873
7874 static void __exit rtl8xxxu_module_exit(void)
7875 {
7876 usb_deregister(&rtl8xxxu_driver);
7877 }
7878
7879
7880 MODULE_DEVICE_TABLE(usb, dev_table);
7881
7882 module_init(rtl8xxxu_module_init);
7883 module_exit(rtl8xxxu_module_exit);
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