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perf/x86: Add option to disable reading branch flags/cycles
[linux-2.6/btrfs-unstable.git] / include / uapi / linux / perf_event.h
blob1afe9623c1a7268cd2ef8949a248ef79216fe2e9
1 /*
2 * Performance events:
3 *
4 * Copyright (C) 2008-2009, Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2011, Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2008-2011, Red Hat, Inc., Peter Zijlstra
7 *
8 * Data type definitions, declarations, prototypes.
9 *
10 * Started by: Thomas Gleixner and Ingo Molnar
11 *
12 * For licencing details see kernel-base/COPYING
13 */
14 #ifndef _UAPI_LINUX_PERF_EVENT_H
15 #define _UAPI_LINUX_PERF_EVENT_H
16
17 #include <linux/types.h>
18 #include <linux/ioctl.h>
19 #include <asm/byteorder.h>
20
21 /*
22 * User-space ABI bits:
23 */
24
25 /*
26 * attr.type
27 */
28 enum perf_type_id {
29 PERF_TYPE_HARDWARE = 0,
30 PERF_TYPE_SOFTWARE = 1,
31 PERF_TYPE_TRACEPOINT = 2,
32 PERF_TYPE_HW_CACHE = 3,
33 PERF_TYPE_RAW = 4,
34 PERF_TYPE_BREAKPOINT = 5,
35
36 PERF_TYPE_MAX, /* non-ABI */
37 };
38
39 /*
40 * Generalized performance event event_id types, used by the
41 * attr.event_id parameter of the sys_perf_event_open()
42 * syscall:
43 */
44 enum perf_hw_id {
45 /*
46 * Common hardware events, generalized by the kernel:
47 */
48 PERF_COUNT_HW_CPU_CYCLES = 0,
49 PERF_COUNT_HW_INSTRUCTIONS = 1,
50 PERF_COUNT_HW_CACHE_REFERENCES = 2,
51 PERF_COUNT_HW_CACHE_MISSES = 3,
52 PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4,
53 PERF_COUNT_HW_BRANCH_MISSES = 5,
54 PERF_COUNT_HW_BUS_CYCLES = 6,
55 PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7,
56 PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8,
57 PERF_COUNT_HW_REF_CPU_CYCLES = 9,
58
59 PERF_COUNT_HW_MAX, /* non-ABI */
60 };
61
62 /*
63 * Generalized hardware cache events:
64 *
65 * { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x
66 * { read, write, prefetch } x
67 * { accesses, misses }
68 */
69 enum perf_hw_cache_id {
70 PERF_COUNT_HW_CACHE_L1D = 0,
71 PERF_COUNT_HW_CACHE_L1I = 1,
72 PERF_COUNT_HW_CACHE_LL = 2,
73 PERF_COUNT_HW_CACHE_DTLB = 3,
74 PERF_COUNT_HW_CACHE_ITLB = 4,
75 PERF_COUNT_HW_CACHE_BPU = 5,
76 PERF_COUNT_HW_CACHE_NODE = 6,
77
78 PERF_COUNT_HW_CACHE_MAX, /* non-ABI */
79 };
80
81 enum perf_hw_cache_op_id {
82 PERF_COUNT_HW_CACHE_OP_READ = 0,
83 PERF_COUNT_HW_CACHE_OP_WRITE = 1,
84 PERF_COUNT_HW_CACHE_OP_PREFETCH = 2,
85
86 PERF_COUNT_HW_CACHE_OP_MAX, /* non-ABI */
87 };
88
89 enum perf_hw_cache_op_result_id {
90 PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0,
91 PERF_COUNT_HW_CACHE_RESULT_MISS = 1,
92
93 PERF_COUNT_HW_CACHE_RESULT_MAX, /* non-ABI */
94 };
95
96 /*
97 * Special "software" events provided by the kernel, even if the hardware
98 * does not support performance events. These events measure various
99 * physical and sw events of the kernel (and allow the profiling of them as
100 * well):
101 */
102 enum perf_sw_ids {
103 PERF_COUNT_SW_CPU_CLOCK = 0,
104 PERF_COUNT_SW_TASK_CLOCK = 1,
105 PERF_COUNT_SW_PAGE_FAULTS = 2,
106 PERF_COUNT_SW_CONTEXT_SWITCHES = 3,
107 PERF_COUNT_SW_CPU_MIGRATIONS = 4,
108 PERF_COUNT_SW_PAGE_FAULTS_MIN = 5,
109 PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6,
110 PERF_COUNT_SW_ALIGNMENT_FAULTS = 7,
111 PERF_COUNT_SW_EMULATION_FAULTS = 8,
112 PERF_COUNT_SW_DUMMY = 9,
113 PERF_COUNT_SW_BPF_OUTPUT = 10,
114
115 PERF_COUNT_SW_MAX, /* non-ABI */
116 };
117
118 /*
119 * Bits that can be set in attr.sample_type to request information
120 * in the overflow packets.
121 */
122 enum perf_event_sample_format {
123 PERF_SAMPLE_IP = 1U << 0,
124 PERF_SAMPLE_TID = 1U << 1,
125 PERF_SAMPLE_TIME = 1U << 2,
126 PERF_SAMPLE_ADDR = 1U << 3,
127 PERF_SAMPLE_READ = 1U << 4,
128 PERF_SAMPLE_CALLCHAIN = 1U << 5,
129 PERF_SAMPLE_ID = 1U << 6,
130 PERF_SAMPLE_CPU = 1U << 7,
131 PERF_SAMPLE_PERIOD = 1U << 8,
132 PERF_SAMPLE_STREAM_ID = 1U << 9,
133 PERF_SAMPLE_RAW = 1U << 10,
134 PERF_SAMPLE_BRANCH_STACK = 1U << 11,
135 PERF_SAMPLE_REGS_USER = 1U << 12,
136 PERF_SAMPLE_STACK_USER = 1U << 13,
137 PERF_SAMPLE_WEIGHT = 1U << 14,
138 PERF_SAMPLE_DATA_SRC = 1U << 15,
139 PERF_SAMPLE_IDENTIFIER = 1U << 16,
140 PERF_SAMPLE_TRANSACTION = 1U << 17,
141 PERF_SAMPLE_REGS_INTR = 1U << 18,
142
143 PERF_SAMPLE_MAX = 1U << 19, /* non-ABI */
144 };
145
146 /*
147 * values to program into branch_sample_type when PERF_SAMPLE_BRANCH is set
148 *
149 * If the user does not pass priv level information via branch_sample_type,
150 * the kernel uses the event's priv level. Branch and event priv levels do
151 * not have to match. Branch priv level is checked for permissions.
152 *
153 * The branch types can be combined, however BRANCH_ANY covers all types
154 * of branches and therefore it supersedes all the other types.
155 */
156 enum perf_branch_sample_type_shift {
157 PERF_SAMPLE_BRANCH_USER_SHIFT = 0, /* user branches */
158 PERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1, /* kernel branches */
159 PERF_SAMPLE_BRANCH_HV_SHIFT = 2, /* hypervisor branches */
160
161 PERF_SAMPLE_BRANCH_ANY_SHIFT = 3, /* any branch types */
162 PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4, /* any call branch */
163 PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5, /* any return branch */
164 PERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6, /* indirect calls */
165 PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7, /* transaction aborts */
166 PERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8, /* in transaction */
167 PERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9, /* not in transaction */
168 PERF_SAMPLE_BRANCH_COND_SHIFT = 10, /* conditional branches */
169
170 PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11, /* call/ret stack */
171 PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12, /* indirect jumps */
172 PERF_SAMPLE_BRANCH_CALL_SHIFT = 13, /* direct call */
173
174 PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14, /* no flags */
175 PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15, /* no cycles */
176
177 PERF_SAMPLE_BRANCH_MAX_SHIFT /* non-ABI */
178 };
179
180 enum perf_branch_sample_type {
181 PERF_SAMPLE_BRANCH_USER = 1U << PERF_SAMPLE_BRANCH_USER_SHIFT,
182 PERF_SAMPLE_BRANCH_KERNEL = 1U << PERF_SAMPLE_BRANCH_KERNEL_SHIFT,
183 PERF_SAMPLE_BRANCH_HV = 1U << PERF_SAMPLE_BRANCH_HV_SHIFT,
184
185 PERF_SAMPLE_BRANCH_ANY = 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT,
186 PERF_SAMPLE_BRANCH_ANY_CALL = 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT,
187 PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT,
188 PERF_SAMPLE_BRANCH_IND_CALL = 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT,
189 PERF_SAMPLE_BRANCH_ABORT_TX = 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT,
190 PERF_SAMPLE_BRANCH_IN_TX = 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT,
191 PERF_SAMPLE_BRANCH_NO_TX = 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT,
192 PERF_SAMPLE_BRANCH_COND = 1U << PERF_SAMPLE_BRANCH_COND_SHIFT,
193
194 PERF_SAMPLE_BRANCH_CALL_STACK = 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT,
195 PERF_SAMPLE_BRANCH_IND_JUMP = 1U << PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT,
196 PERF_SAMPLE_BRANCH_CALL = 1U << PERF_SAMPLE_BRANCH_CALL_SHIFT,
197
198 PERF_SAMPLE_BRANCH_NO_FLAGS = 1U << PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT,
199 PERF_SAMPLE_BRANCH_NO_CYCLES = 1U << PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT,
200
201 PERF_SAMPLE_BRANCH_MAX = 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT,
202 };
203
204 #define PERF_SAMPLE_BRANCH_PLM_ALL \
205 (PERF_SAMPLE_BRANCH_USER|\
206 PERF_SAMPLE_BRANCH_KERNEL|\
207 PERF_SAMPLE_BRANCH_HV)
208
209 /*
210 * Values to determine ABI of the registers dump.
211 */
212 enum perf_sample_regs_abi {
213 PERF_SAMPLE_REGS_ABI_NONE = 0,
214 PERF_SAMPLE_REGS_ABI_32 = 1,
215 PERF_SAMPLE_REGS_ABI_64 = 2,
216 };
217
218 /*
219 * Values for the memory transaction event qualifier, mostly for
220 * abort events. Multiple bits can be set.
221 */
222 enum {
223 PERF_TXN_ELISION = (1 << 0), /* From elision */
224 PERF_TXN_TRANSACTION = (1 << 1), /* From transaction */
225 PERF_TXN_SYNC = (1 << 2), /* Instruction is related */
226 PERF_TXN_ASYNC = (1 << 3), /* Instruction not related */
227 PERF_TXN_RETRY = (1 << 4), /* Retry possible */
228 PERF_TXN_CONFLICT = (1 << 5), /* Conflict abort */
229 PERF_TXN_CAPACITY_WRITE = (1 << 6), /* Capacity write abort */
230 PERF_TXN_CAPACITY_READ = (1 << 7), /* Capacity read abort */
231
232 PERF_TXN_MAX = (1 << 8), /* non-ABI */
233
234 /* bits 32..63 are reserved for the abort code */
235
236 PERF_TXN_ABORT_MASK = (0xffffffffULL << 32),
237 PERF_TXN_ABORT_SHIFT = 32,
238 };
239
240 /*
241 * The format of the data returned by read() on a perf event fd,
242 * as specified by attr.read_format:
243 *
244 * struct read_format {
245 * { u64 value;
246 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED
247 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING
248 * { u64 id; } && PERF_FORMAT_ID
249 * } && !PERF_FORMAT_GROUP
250 *
251 * { u64 nr;
252 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED
253 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING
254 * { u64 value;
255 * { u64 id; } && PERF_FORMAT_ID
256 * } cntr[nr];
257 * } && PERF_FORMAT_GROUP
258 * };
259 */
260 enum perf_event_read_format {
261 PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0,
262 PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1,
263 PERF_FORMAT_ID = 1U << 2,
264 PERF_FORMAT_GROUP = 1U << 3,
265
266 PERF_FORMAT_MAX = 1U << 4, /* non-ABI */
267 };
268
269 #define PERF_ATTR_SIZE_VER0 64 /* sizeof first published struct */
270 #define PERF_ATTR_SIZE_VER1 72 /* add: config2 */
271 #define PERF_ATTR_SIZE_VER2 80 /* add: branch_sample_type */
272 #define PERF_ATTR_SIZE_VER3 96 /* add: sample_regs_user */
273 /* add: sample_stack_user */
274 #define PERF_ATTR_SIZE_VER4 104 /* add: sample_regs_intr */
275 #define PERF_ATTR_SIZE_VER5 112 /* add: aux_watermark */
276
277 /*
278 * Hardware event_id to monitor via a performance monitoring event:
279 */
280 struct perf_event_attr {
281
282 /*
283 * Major type: hardware/software/tracepoint/etc.
284 */
285 __u32 type;
286
287 /*
288 * Size of the attr structure, for fwd/bwd compat.
289 */
290 __u32 size;
291
292 /*
293 * Type specific configuration information.
294 */
295 __u64 config;
296
297 union {
298 __u64 sample_period;
299 __u64 sample_freq;
300 };
301
302 __u64 sample_type;
303 __u64 read_format;
304
305 __u64 disabled : 1, /* off by default */
306 inherit : 1, /* children inherit it */
307 pinned : 1, /* must always be on PMU */
308 exclusive : 1, /* only group on PMU */
309 exclude_user : 1, /* don't count user */
310 exclude_kernel : 1, /* ditto kernel */
311 exclude_hv : 1, /* ditto hypervisor */
312 exclude_idle : 1, /* don't count when idle */
313 mmap : 1, /* include mmap data */
314 comm : 1, /* include comm data */
315 freq : 1, /* use freq, not period */
316 inherit_stat : 1, /* per task counts */
317 enable_on_exec : 1, /* next exec enables */
318 task : 1, /* trace fork/exit */
319 watermark : 1, /* wakeup_watermark */
320 /*
321 * precise_ip:
322 *
323 * 0 - SAMPLE_IP can have arbitrary skid
324 * 1 - SAMPLE_IP must have constant skid
325 * 2 - SAMPLE_IP requested to have 0 skid
326 * 3 - SAMPLE_IP must have 0 skid
327 *
328 * See also PERF_RECORD_MISC_EXACT_IP
329 */
330 precise_ip : 2, /* skid constraint */
331 mmap_data : 1, /* non-exec mmap data */
332 sample_id_all : 1, /* sample_type all events */
333
334 exclude_host : 1, /* don't count in host */
335 exclude_guest : 1, /* don't count in guest */
336
337 exclude_callchain_kernel : 1, /* exclude kernel callchains */
338 exclude_callchain_user : 1, /* exclude user callchains */
339 mmap2 : 1, /* include mmap with inode data */
340 comm_exec : 1, /* flag comm events that are due to an exec */
341 use_clockid : 1, /* use @clockid for time fields */
342 context_switch : 1, /* context switch data */
343 __reserved_1 : 37;
344
345 union {
346 __u32 wakeup_events; /* wakeup every n events */
347 __u32 wakeup_watermark; /* bytes before wakeup */
348 };
349
350 __u32 bp_type;
351 union {
352 __u64 bp_addr;
353 __u64 config1; /* extension of config */
354 };
355 union {
356 __u64 bp_len;
357 __u64 config2; /* extension of config1 */
358 };
359 __u64 branch_sample_type; /* enum perf_branch_sample_type */
360
361 /*
362 * Defines set of user regs to dump on samples.
363 * See asm/perf_regs.h for details.
364 */
365 __u64 sample_regs_user;
366
367 /*
368 * Defines size of the user stack to dump on samples.
369 */
370 __u32 sample_stack_user;
371
372 __s32 clockid;
373 /*
374 * Defines set of regs to dump for each sample
375 * state captured on:
376 * - precise = 0: PMU interrupt
377 * - precise > 0: sampled instruction
378 *
379 * See asm/perf_regs.h for details.
380 */
381 __u64 sample_regs_intr;
382
383 /*
384 * Wakeup watermark for AUX area
385 */
386 __u32 aux_watermark;
387 __u32 __reserved_2; /* align to __u64 */
388 };
389
390 #define perf_flags(attr) (*(&(attr)->read_format + 1))
391
392 /*
393 * Ioctls that can be done on a perf event fd:
394 */
395 #define PERF_EVENT_IOC_ENABLE _IO ('$', 0)
396 #define PERF_EVENT_IOC_DISABLE _IO ('$', 1)
397 #define PERF_EVENT_IOC_REFRESH _IO ('$', 2)
398 #define PERF_EVENT_IOC_RESET _IO ('$', 3)
399 #define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64)
400 #define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5)
401 #define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *)
402 #define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *)
403 #define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, __u32)
404
405 enum perf_event_ioc_flags {
406 PERF_IOC_FLAG_GROUP = 1U << 0,
407 };
408
409 /*
410 * Structure of the page that can be mapped via mmap
411 */
412 struct perf_event_mmap_page {
413 __u32 version; /* version number of this structure */
414 __u32 compat_version; /* lowest version this is compat with */
415
416 /*
417 * Bits needed to read the hw events in user-space.
418 *
419 * u32 seq, time_mult, time_shift, index, width;
420 * u64 count, enabled, running;
421 * u64 cyc, time_offset;
422 * s64 pmc = 0;
423 *
424 * do {
425 * seq = pc->lock;
426 * barrier()
427 *
428 * enabled = pc->time_enabled;
429 * running = pc->time_running;
430 *
431 * if (pc->cap_usr_time && enabled != running) {
432 * cyc = rdtsc();
433 * time_offset = pc->time_offset;
434 * time_mult = pc->time_mult;
435 * time_shift = pc->time_shift;
436 * }
437 *
438 * index = pc->index;
439 * count = pc->offset;
440 * if (pc->cap_user_rdpmc && index) {
441 * width = pc->pmc_width;
442 * pmc = rdpmc(index - 1);
443 * }
444 *
445 * barrier();
446 * } while (pc->lock != seq);
447 *
448 * NOTE: for obvious reason this only works on self-monitoring
449 * processes.
450 */
451 __u32 lock; /* seqlock for synchronization */
452 __u32 index; /* hardware event identifier */
453 __s64 offset; /* add to hardware event value */
454 __u64 time_enabled; /* time event active */
455 __u64 time_running; /* time event on cpu */
456 union {
457 __u64 capabilities;
458 struct {
459 __u64 cap_bit0 : 1, /* Always 0, deprecated, see commit 860f085b74e9 */
460 cap_bit0_is_deprecated : 1, /* Always 1, signals that bit 0 is zero */
461
462 cap_user_rdpmc : 1, /* The RDPMC instruction can be used to read counts */
463 cap_user_time : 1, /* The time_* fields are used */
464 cap_user_time_zero : 1, /* The time_zero field is used */
465 cap_____res : 59;
466 };
467 };
468
469 /*
470 * If cap_user_rdpmc this field provides the bit-width of the value
471 * read using the rdpmc() or equivalent instruction. This can be used
472 * to sign extend the result like:
473 *
474 * pmc <<= 64 - width;
475 * pmc >>= 64 - width; // signed shift right
476 * count += pmc;
477 */
478 __u16 pmc_width;
479
480 /*
481 * If cap_usr_time the below fields can be used to compute the time
482 * delta since time_enabled (in ns) using rdtsc or similar.
483 *
484 * u64 quot, rem;
485 * u64 delta;
486 *
487 * quot = (cyc >> time_shift);
488 * rem = cyc & (((u64)1 << time_shift) - 1);
489 * delta = time_offset + quot * time_mult +
490 * ((rem * time_mult) >> time_shift);
491 *
492 * Where time_offset,time_mult,time_shift and cyc are read in the
493 * seqcount loop described above. This delta can then be added to
494 * enabled and possible running (if index), improving the scaling:
495 *
496 * enabled += delta;
497 * if (index)
498 * running += delta;
499 *
500 * quot = count / running;
501 * rem = count % running;
502 * count = quot * enabled + (rem * enabled) / running;
503 */
504 __u16 time_shift;
505 __u32 time_mult;
506 __u64 time_offset;
507 /*
508 * If cap_usr_time_zero, the hardware clock (e.g. TSC) can be calculated
509 * from sample timestamps.
510 *
511 * time = timestamp - time_zero;
512 * quot = time / time_mult;
513 * rem = time % time_mult;
514 * cyc = (quot << time_shift) + (rem << time_shift) / time_mult;
515 *
516 * And vice versa:
517 *
518 * quot = cyc >> time_shift;
519 * rem = cyc & (((u64)1 << time_shift) - 1);
520 * timestamp = time_zero + quot * time_mult +
521 * ((rem * time_mult) >> time_shift);
522 */
523 __u64 time_zero;
524 __u32 size; /* Header size up to __reserved[] fields. */
525
526 /*
527 * Hole for extension of the self monitor capabilities
528 */
529
530 __u8 __reserved[118*8+4]; /* align to 1k. */
531
532 /*
533 * Control data for the mmap() data buffer.
534 *
535 * User-space reading the @data_head value should issue an smp_rmb(),
536 * after reading this value.
537 *
538 * When the mapping is PROT_WRITE the @data_tail value should be
539 * written by userspace to reflect the last read data, after issueing
540 * an smp_mb() to separate the data read from the ->data_tail store.
541 * In this case the kernel will not over-write unread data.
542 *
543 * See perf_output_put_handle() for the data ordering.
544 *
545 * data_{offset,size} indicate the location and size of the perf record
546 * buffer within the mmapped area.
547 */
548 __u64 data_head; /* head in the data section */
549 __u64 data_tail; /* user-space written tail */
550 __u64 data_offset; /* where the buffer starts */
551 __u64 data_size; /* data buffer size */
552
553 /*
554 * AUX area is defined by aux_{offset,size} fields that should be set
555 * by the userspace, so that
556 *
557 * aux_offset >= data_offset + data_size
558 *
559 * prior to mmap()ing it. Size of the mmap()ed area should be aux_size.
560 *
561 * Ring buffer pointers aux_{head,tail} have the same semantics as
562 * data_{head,tail} and same ordering rules apply.
563 */
564 __u64 aux_head;
565 __u64 aux_tail;
566 __u64 aux_offset;
567 __u64 aux_size;
568 };
569
570 #define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0)
571 #define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0)
572 #define PERF_RECORD_MISC_KERNEL (1 << 0)
573 #define PERF_RECORD_MISC_USER (2 << 0)
574 #define PERF_RECORD_MISC_HYPERVISOR (3 << 0)
575 #define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0)
576 #define PERF_RECORD_MISC_GUEST_USER (5 << 0)
577
578 /*
579 * Indicates that /proc/PID/maps parsing are truncated by time out.
580 */
581 #define PERF_RECORD_MISC_PROC_MAP_PARSE_TIMEOUT (1 << 12)
582 /*
583 * PERF_RECORD_MISC_MMAP_DATA and PERF_RECORD_MISC_COMM_EXEC are used on
584 * different events so can reuse the same bit position.
585 * Ditto PERF_RECORD_MISC_SWITCH_OUT.
586 */
587 #define PERF_RECORD_MISC_MMAP_DATA (1 << 13)
588 #define PERF_RECORD_MISC_COMM_EXEC (1 << 13)
589 #define PERF_RECORD_MISC_SWITCH_OUT (1 << 13)
590 /*
591 * Indicates that the content of PERF_SAMPLE_IP points to
592 * the actual instruction that triggered the event. See also
593 * perf_event_attr::precise_ip.
594 */
595 #define PERF_RECORD_MISC_EXACT_IP (1 << 14)
596 /*
597 * Reserve the last bit to indicate some extended misc field
598 */
599 #define PERF_RECORD_MISC_EXT_RESERVED (1 << 15)
600
601 struct perf_event_header {
602 __u32 type;
603 __u16 misc;
604 __u16 size;
605 };
606
607 enum perf_event_type {
608
609 /*
610 * If perf_event_attr.sample_id_all is set then all event types will
611 * have the sample_type selected fields related to where/when
612 * (identity) an event took place (TID, TIME, ID, STREAM_ID, CPU,
613 * IDENTIFIER) described in PERF_RECORD_SAMPLE below, it will be stashed
614 * just after the perf_event_header and the fields already present for
615 * the existing fields, i.e. at the end of the payload. That way a newer
616 * perf.data file will be supported by older perf tools, with these new
617 * optional fields being ignored.
618 *
619 * struct sample_id {
620 * { u32 pid, tid; } && PERF_SAMPLE_TID
621 * { u64 time; } && PERF_SAMPLE_TIME
622 * { u64 id; } && PERF_SAMPLE_ID
623 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID
624 * { u32 cpu, res; } && PERF_SAMPLE_CPU
625 * { u64 id; } && PERF_SAMPLE_IDENTIFIER
626 * } && perf_event_attr::sample_id_all
627 *
628 * Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. The
629 * advantage of PERF_SAMPLE_IDENTIFIER is that its position is fixed
630 * relative to header.size.
631 */
632
633 /*
634 * The MMAP events record the PROT_EXEC mappings so that we can
635 * correlate userspace IPs to code. They have the following structure:
636 *
637 * struct {
638 * struct perf_event_header header;
639 *
640 * u32 pid, tid;
641 * u64 addr;
642 * u64 len;
643 * u64 pgoff;
644 * char filename[];
645 * struct sample_id sample_id;
646 * };
647 */
648 PERF_RECORD_MMAP = 1,
649
650 /*
651 * struct {
652 * struct perf_event_header header;
653 * u64 id;
654 * u64 lost;
655 * struct sample_id sample_id;
656 * };
657 */
658 PERF_RECORD_LOST = 2,
659
660 /*
661 * struct {
662 * struct perf_event_header header;
663 *
664 * u32 pid, tid;
665 * char comm[];
666 * struct sample_id sample_id;
667 * };
668 */
669 PERF_RECORD_COMM = 3,
670
671 /*
672 * struct {
673 * struct perf_event_header header;
674 * u32 pid, ppid;
675 * u32 tid, ptid;
676 * u64 time;
677 * struct sample_id sample_id;
678 * };
679 */
680 PERF_RECORD_EXIT = 4,
681
682 /*
683 * struct {
684 * struct perf_event_header header;
685 * u64 time;
686 * u64 id;
687 * u64 stream_id;
688 * struct sample_id sample_id;
689 * };
690 */
691 PERF_RECORD_THROTTLE = 5,
692 PERF_RECORD_UNTHROTTLE = 6,
693
694 /*
695 * struct {
696 * struct perf_event_header header;
697 * u32 pid, ppid;
698 * u32 tid, ptid;
699 * u64 time;
700 * struct sample_id sample_id;
701 * };
702 */
703 PERF_RECORD_FORK = 7,
704
705 /*
706 * struct {
707 * struct perf_event_header header;
708 * u32 pid, tid;
709 *
710 * struct read_format values;
711 * struct sample_id sample_id;
712 * };
713 */
714 PERF_RECORD_READ = 8,
715
716 /*
717 * struct {
718 * struct perf_event_header header;
719 *
720 * #
721 * # Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID.
722 * # The advantage of PERF_SAMPLE_IDENTIFIER is that its position
723 * # is fixed relative to header.
724 * #
725 *
726 * { u64 id; } && PERF_SAMPLE_IDENTIFIER
727 * { u64 ip; } && PERF_SAMPLE_IP
728 * { u32 pid, tid; } && PERF_SAMPLE_TID
729 * { u64 time; } && PERF_SAMPLE_TIME
730 * { u64 addr; } && PERF_SAMPLE_ADDR
731 * { u64 id; } && PERF_SAMPLE_ID
732 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID
733 * { u32 cpu, res; } && PERF_SAMPLE_CPU
734 * { u64 period; } && PERF_SAMPLE_PERIOD
735 *
736 * { struct read_format values; } && PERF_SAMPLE_READ
737 *
738 * { u64 nr,
739 * u64 ips[nr]; } && PERF_SAMPLE_CALLCHAIN
740 *
741 * #
742 * # The RAW record below is opaque data wrt the ABI
743 * #
744 * # That is, the ABI doesn't make any promises wrt to
745 * # the stability of its content, it may vary depending
746 * # on event, hardware, kernel version and phase of
747 * # the moon.
748 * #
749 * # In other words, PERF_SAMPLE_RAW contents are not an ABI.
750 * #
751 *
752 * { u32 size;
753 * char data[size];}&& PERF_SAMPLE_RAW
754 *
755 * { u64 nr;
756 * { u64 from, to, flags } lbr[nr];} && PERF_SAMPLE_BRANCH_STACK
757 *
758 * { u64 abi; # enum perf_sample_regs_abi
759 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER
760 *
761 * { u64 size;
762 * char data[size];
763 * u64 dyn_size; } && PERF_SAMPLE_STACK_USER
764 *
765 * { u64 weight; } && PERF_SAMPLE_WEIGHT
766 * { u64 data_src; } && PERF_SAMPLE_DATA_SRC
767 * { u64 transaction; } && PERF_SAMPLE_TRANSACTION
768 * { u64 abi; # enum perf_sample_regs_abi
769 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_INTR
770 * };
771 */
772 PERF_RECORD_SAMPLE = 9,
773
774 /*
775 * The MMAP2 records are an augmented version of MMAP, they add
776 * maj, min, ino numbers to be used to uniquely identify each mapping
777 *
778 * struct {
779 * struct perf_event_header header;
780 *
781 * u32 pid, tid;
782 * u64 addr;
783 * u64 len;
784 * u64 pgoff;
785 * u32 maj;
786 * u32 min;
787 * u64 ino;
788 * u64 ino_generation;
789 * u32 prot, flags;
790 * char filename[];
791 * struct sample_id sample_id;
792 * };
793 */
794 PERF_RECORD_MMAP2 = 10,
795
796 /*
797 * Records that new data landed in the AUX buffer part.
798 *
799 * struct {
800 * struct perf_event_header header;
801 *
802 * u64 aux_offset;
803 * u64 aux_size;
804 * u64 flags;
805 * struct sample_id sample_id;
806 * };
807 */
808 PERF_RECORD_AUX = 11,
809
810 /*
811 * Indicates that instruction trace has started
812 *
813 * struct {
814 * struct perf_event_header header;
815 * u32 pid;
816 * u32 tid;
817 * };
818 */
819 PERF_RECORD_ITRACE_START = 12,
820
821 /*
822 * Records the dropped/lost sample number.
823 *
824 * struct {
825 * struct perf_event_header header;
826 *
827 * u64 lost;
828 * struct sample_id sample_id;
829 * };
830 */
831 PERF_RECORD_LOST_SAMPLES = 13,
832
833 /*
834 * Records a context switch in or out (flagged by
835 * PERF_RECORD_MISC_SWITCH_OUT). See also
836 * PERF_RECORD_SWITCH_CPU_WIDE.
837 *
838 * struct {
839 * struct perf_event_header header;
840 * struct sample_id sample_id;
841 * };
842 */
843 PERF_RECORD_SWITCH = 14,
844
845 /*
846 * CPU-wide version of PERF_RECORD_SWITCH with next_prev_pid and
847 * next_prev_tid that are the next (switching out) or previous
848 * (switching in) pid/tid.
849 *
850 * struct {
851 * struct perf_event_header header;
852 * u32 next_prev_pid;
853 * u32 next_prev_tid;
854 * struct sample_id sample_id;
855 * };
856 */
857 PERF_RECORD_SWITCH_CPU_WIDE = 15,
858
859 PERF_RECORD_MAX, /* non-ABI */
860 };
861
862 #define PERF_MAX_STACK_DEPTH 127
863
864 enum perf_callchain_context {
865 PERF_CONTEXT_HV = (__u64)-32,
866 PERF_CONTEXT_KERNEL = (__u64)-128,
867 PERF_CONTEXT_USER = (__u64)-512,
868
869 PERF_CONTEXT_GUEST = (__u64)-2048,
870 PERF_CONTEXT_GUEST_KERNEL = (__u64)-2176,
871 PERF_CONTEXT_GUEST_USER = (__u64)-2560,
872
873 PERF_CONTEXT_MAX = (__u64)-4095,
874 };
875
876 /**
877 * PERF_RECORD_AUX::flags bits
878 */
879 #define PERF_AUX_FLAG_TRUNCATED 0x01 /* record was truncated to fit */
880 #define PERF_AUX_FLAG_OVERWRITE 0x02 /* snapshot from overwrite mode */
881
882 #define PERF_FLAG_FD_NO_GROUP (1UL << 0)
883 #define PERF_FLAG_FD_OUTPUT (1UL << 1)
884 #define PERF_FLAG_PID_CGROUP (1UL << 2) /* pid=cgroup id, per-cpu mode only */
885 #define PERF_FLAG_FD_CLOEXEC (1UL << 3) /* O_CLOEXEC */
886
887 union perf_mem_data_src {
888 __u64 val;
889 struct {
890 __u64 mem_op:5, /* type of opcode */
891 mem_lvl:14, /* memory hierarchy level */
892 mem_snoop:5, /* snoop mode */
893 mem_lock:2, /* lock instr */
894 mem_dtlb:7, /* tlb access */
895 mem_rsvd:31;
896 };
897 };
898
899 /* type of opcode (load/store/prefetch,code) */
900 #define PERF_MEM_OP_NA 0x01 /* not available */
901 #define PERF_MEM_OP_LOAD 0x02 /* load instruction */
902 #define PERF_MEM_OP_STORE 0x04 /* store instruction */
903 #define PERF_MEM_OP_PFETCH 0x08 /* prefetch */
904 #define PERF_MEM_OP_EXEC 0x10 /* code (execution) */
905 #define PERF_MEM_OP_SHIFT 0
906
907 /* memory hierarchy (memory level, hit or miss) */
908 #define PERF_MEM_LVL_NA 0x01 /* not available */
909 #define PERF_MEM_LVL_HIT 0x02 /* hit level */
910 #define PERF_MEM_LVL_MISS 0x04 /* miss level */
911 #define PERF_MEM_LVL_L1 0x08 /* L1 */
912 #define PERF_MEM_LVL_LFB 0x10 /* Line Fill Buffer */
913 #define PERF_MEM_LVL_L2 0x20 /* L2 */
914 #define PERF_MEM_LVL_L3 0x40 /* L3 */
915 #define PERF_MEM_LVL_LOC_RAM 0x80 /* Local DRAM */
916 #define PERF_MEM_LVL_REM_RAM1 0x100 /* Remote DRAM (1 hop) */
917 #define PERF_MEM_LVL_REM_RAM2 0x200 /* Remote DRAM (2 hops) */
918 #define PERF_MEM_LVL_REM_CCE1 0x400 /* Remote Cache (1 hop) */
919 #define PERF_MEM_LVL_REM_CCE2 0x800 /* Remote Cache (2 hops) */
920 #define PERF_MEM_LVL_IO 0x1000 /* I/O memory */
921 #define PERF_MEM_LVL_UNC 0x2000 /* Uncached memory */
922 #define PERF_MEM_LVL_SHIFT 5
923
924 /* snoop mode */
925 #define PERF_MEM_SNOOP_NA 0x01 /* not available */
926 #define PERF_MEM_SNOOP_NONE 0x02 /* no snoop */
927 #define PERF_MEM_SNOOP_HIT 0x04 /* snoop hit */
928 #define PERF_MEM_SNOOP_MISS 0x08 /* snoop miss */
929 #define PERF_MEM_SNOOP_HITM 0x10 /* snoop hit modified */
930 #define PERF_MEM_SNOOP_SHIFT 19
931
932 /* locked instruction */
933 #define PERF_MEM_LOCK_NA 0x01 /* not available */
934 #define PERF_MEM_LOCK_LOCKED 0x02 /* locked transaction */
935 #define PERF_MEM_LOCK_SHIFT 24
936
937 /* TLB access */
938 #define PERF_MEM_TLB_NA 0x01 /* not available */
939 #define PERF_MEM_TLB_HIT 0x02 /* hit level */
940 #define PERF_MEM_TLB_MISS 0x04 /* miss level */
941 #define PERF_MEM_TLB_L1 0x08 /* L1 */
942 #define PERF_MEM_TLB_L2 0x10 /* L2 */
943 #define PERF_MEM_TLB_WK 0x20 /* Hardware Walker*/
944 #define PERF_MEM_TLB_OS 0x40 /* OS fault handler */
945 #define PERF_MEM_TLB_SHIFT 26
946
947 #define PERF_MEM_S(a, s) \
948 (((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT)
949
950 /*
951 * single taken branch record layout:
952 *
953 * from: source instruction (may not always be a branch insn)
954 * to: branch target
955 * mispred: branch target was mispredicted
956 * predicted: branch target was predicted
957 *
958 * support for mispred, predicted is optional. In case it
959 * is not supported mispred = predicted = 0.
960 *
961 * in_tx: running in a hardware transaction
962 * abort: aborting a hardware transaction
963 * cycles: cycles from last branch (or 0 if not supported)
964 */
965 struct perf_branch_entry {
966 __u64 from;
967 __u64 to;
968 __u64 mispred:1, /* target mispredicted */
969 predicted:1,/* target predicted */
970 in_tx:1, /* in transaction */
971 abort:1, /* transaction abort */
972 cycles:16, /* cycle count to last branch */
973 reserved:44;
974 };
975
976 #endif /* _UAPI_LINUX_PERF_EVENT_H */
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