drivers/crypto/marvell/hash.c

   1 /*
   2  * Hash algorithms supported by the CESA: MD5, SHA1 and SHA256.
   3  *
   4  * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
   5  * Author: Arnaud Ebalard <arno@natisbad.org>
   6  *
   7  * This work is based on an initial version written by
   8  * Sebastian Andrzej Siewior < sebastian at breakpoint dot cc >
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published
  12  * by the Free Software Foundation.
  13  */
  14
  15 #include <crypto/md5.h>
  16 #include <crypto/sha.h>
  17
  18 #include "cesa.h"
  19
  20 struct mv_cesa_ahash_dma_iter {
  21         struct mv_cesa_dma_iter base;
  22         struct mv_cesa_sg_dma_iter src;
  23 };
  24
  25 static inline void
  26 mv_cesa_ahash_req_iter_init(struct mv_cesa_ahash_dma_iter *iter,
  27                             struct ahash_request *req)
  28 {
  29         struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
  30         unsigned int len = req->nbytes + creq->cache_ptr;
  31
  32         if (!creq->last_req)
  33                 len &= ~CESA_HASH_BLOCK_SIZE_MSK;
  34
  35         mv_cesa_req_dma_iter_init(&iter->base, len);
  36         mv_cesa_sg_dma_iter_init(&iter->src, req->src, DMA_TO_DEVICE);
  37         iter->src.op_offset = creq->cache_ptr;
  38 }
  39
  40 static inline bool
  41 mv_cesa_ahash_req_iter_next_op(struct mv_cesa_ahash_dma_iter *iter)
  42 {
  43         iter->src.op_offset = 0;
  44
  45         return mv_cesa_req_dma_iter_next_op(&iter->base);
  46 }
  47
  48 static inline int mv_cesa_ahash_dma_alloc_cache(struct mv_cesa_ahash_req *creq,
  49                                                 gfp_t flags)
  50 {
  51         struct mv_cesa_ahash_dma_req *dreq = &creq->req.dma;
  52
  53         creq->cache = dma_pool_alloc(cesa_dev->dma->cache_pool, flags,
  54                                      &dreq->cache_dma);
  55         if (!creq->cache)
  56                 return -ENOMEM;
  57
  58         return 0;
  59 }
  60
  61 static inline int mv_cesa_ahash_std_alloc_cache(struct mv_cesa_ahash_req *creq,
  62                                                 gfp_t flags)
  63 {
  64         creq->cache = kzalloc(CESA_MAX_HASH_BLOCK_SIZE, flags);
  65         if (!creq->cache)
  66                 return -ENOMEM;
  67
  68         return 0;
  69 }
  70
  71 static int mv_cesa_ahash_alloc_cache(struct ahash_request *req)
  72 {
  73         struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
  74         gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
  75                       GFP_KERNEL : GFP_ATOMIC;
  76         int ret;
  77
  78         if (creq->cache)
  79                 return 0;
  80
  81         if (creq->req.base.type == CESA_DMA_REQ)
  82                 ret = mv_cesa_ahash_dma_alloc_cache(creq, flags);
  83         else
  84                 ret = mv_cesa_ahash_std_alloc_cache(creq, flags);
  85
  86         return ret;
  87 }
  88
  89 static inline void mv_cesa_ahash_dma_free_cache(struct mv_cesa_ahash_req *creq)
  90 {
  91         dma_pool_free(cesa_dev->dma->cache_pool, creq->cache,
  92                       creq->req.dma.cache_dma);
  93 }
  94
  95 static inline void mv_cesa_ahash_std_free_cache(struct mv_cesa_ahash_req *creq)
  96 {
  97         kfree(creq->cache);
  98 }
  99
 100 static void mv_cesa_ahash_free_cache(struct mv_cesa_ahash_req *creq)
 101 {
 102         if (!creq->cache)
 103                 return;
 104
 105         if (creq->req.base.type == CESA_DMA_REQ)
 106                 mv_cesa_ahash_dma_free_cache(creq);
 107         else
 108                 mv_cesa_ahash_std_free_cache(creq);
 109
 110         creq->cache = NULL;
 111 }
 112
 113 static int mv_cesa_ahash_dma_alloc_padding(struct mv_cesa_ahash_dma_req *req,
 114                                            gfp_t flags)
 115 {
 116         if (req->padding)
 117                 return 0;
 118
 119         req->padding = dma_pool_alloc(cesa_dev->dma->padding_pool, flags,
 120                                       &req->padding_dma);
 121         if (!req->padding)
 122                 return -ENOMEM;
 123
 124         return 0;
 125 }
 126
 127 static void mv_cesa_ahash_dma_free_padding(struct mv_cesa_ahash_dma_req *req)
 128 {
 129         if (!req->padding)
 130                 return;
 131
 132         dma_pool_free(cesa_dev->dma->padding_pool, req->padding,
 133                       req->padding_dma);
 134         req->padding = NULL;
 135 }
 136
 137 static inline void mv_cesa_ahash_dma_last_cleanup(struct ahash_request *req)
 138 {
 139         struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
 140
 141         mv_cesa_ahash_dma_free_padding(&creq->req.dma);
 142 }
 143
 144 static inline void mv_cesa_ahash_dma_cleanup(struct ahash_request *req)
 145 {
 146         struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
 147
 148         dma_unmap_sg(cesa_dev->dev, req->src, creq->src_nents, DMA_TO_DEVICE);
 149         mv_cesa_dma_cleanup(&creq->req.dma.base);
 150 }
 151
 152 static inline void mv_cesa_ahash_cleanup(struct ahash_request *req)
 153 {
 154         struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
 155
 156         if (creq->req.base.type == CESA_DMA_REQ)
 157                 mv_cesa_ahash_dma_cleanup(req);
 158 }
 159
 160 static void mv_cesa_ahash_last_cleanup(struct ahash_request *req)
 161 {
 162         struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
 163
 164         mv_cesa_ahash_free_cache(creq);
 165
 166         if (creq->req.base.type == CESA_DMA_REQ)
 167                 mv_cesa_ahash_dma_last_cleanup(req);
 168 }
 169
 170 static int mv_cesa_ahash_pad_len(struct mv_cesa_ahash_req *creq)
 171 {
 172         unsigned int index, padlen;
 173
 174         index = creq->len & CESA_HASH_BLOCK_SIZE_MSK;
 175         padlen = (index < 56) ? (56 - index) : (64 + 56 - index);
 176
 177         return padlen;
 178 }
 179
 180 static int mv_cesa_ahash_pad_req(struct mv_cesa_ahash_req *creq, u8 *buf)
 181 {
 182         unsigned int index, padlen;
 183
 184         buf[0] = 0x80;
 185         /* Pad out to 56 mod 64 */
 186         index = creq->len & CESA_HASH_BLOCK_SIZE_MSK;
 187         padlen = mv_cesa_ahash_pad_len(creq);
 188         memset(buf + 1, 0, padlen - 1);
 189
 190         if (creq->algo_le) {
 191                 __le64 bits = cpu_to_le64(creq->len << 3);
 192                 memcpy(buf + padlen, &bits, sizeof(bits));
 193         } else {
 194                 __be64 bits = cpu_to_be64(creq->len << 3);
 195                 memcpy(buf + padlen, &bits, sizeof(bits));
 196         }
 197
 198         return padlen + 8;
 199 }
 200
 201 static void mv_cesa_ahash_std_step(struct ahash_request *req)
 202 {
 203         struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
 204         struct mv_cesa_ahash_std_req *sreq = &creq->req.std;
 205         struct mv_cesa_engine *engine = sreq->base.engine;
 206         struct mv_cesa_op_ctx *op;
 207         unsigned int new_cache_ptr = 0;
 208         u32 frag_mode;
 209         size_t  len;
 210
 211         if (creq->cache_ptr)
 212                 memcpy(engine->sram + CESA_SA_DATA_SRAM_OFFSET, creq->cache,
 213                        creq->cache_ptr);
 214
 215         len = min_t(size_t, req->nbytes + creq->cache_ptr - sreq->offset,
 216                     CESA_SA_SRAM_PAYLOAD_SIZE);
 217
 218         if (!creq->last_req) {
 219                 new_cache_ptr = len & CESA_HASH_BLOCK_SIZE_MSK;
 220                 len &= ~CESA_HASH_BLOCK_SIZE_MSK;
 221         }
 222
 223         if (len - creq->cache_ptr)
 224                 sreq->offset += sg_pcopy_to_buffer(req->src, creq->src_nents,
 225                                                    engine->sram +
 226                                                    CESA_SA_DATA_SRAM_OFFSET +
 227                                                    creq->cache_ptr,
 228                                                    len - creq->cache_ptr,
 229                                                    sreq->offset);
 230
 231         op = &creq->op_tmpl;
 232
 233         frag_mode = mv_cesa_get_op_cfg(op) & CESA_SA_DESC_CFG_FRAG_MSK;
 234
 235         if (creq->last_req && sreq->offset == req->nbytes &&
 236             creq->len <= CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX) {
 237                 if (frag_mode == CESA_SA_DESC_CFG_FIRST_FRAG)
 238                         frag_mode = CESA_SA_DESC_CFG_NOT_FRAG;
 239                 else if (frag_mode == CESA_SA_DESC_CFG_MID_FRAG)
 240                         frag_mode = CESA_SA_DESC_CFG_LAST_FRAG;
 241         }
 242
 243         if (frag_mode == CESA_SA_DESC_CFG_NOT_FRAG ||
 244             frag_mode == CESA_SA_DESC_CFG_LAST_FRAG) {
 245                 if (len &&
 246                     creq->len <= CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX) {
 247                         mv_cesa_set_mac_op_total_len(op, creq->len);
 248                 } else {
 249                         int trailerlen = mv_cesa_ahash_pad_len(creq) + 8;
 250
 251                         if (len + trailerlen > CESA_SA_SRAM_PAYLOAD_SIZE) {
 252                                 len &= CESA_HASH_BLOCK_SIZE_MSK;
 253                                 new_cache_ptr = 64 - trailerlen;
 254                                 memcpy(creq->cache,
 255                                        engine->sram +
 256                                        CESA_SA_DATA_SRAM_OFFSET + len,
 257                                        new_cache_ptr);
 258                         } else {
 259                                 len += mv_cesa_ahash_pad_req(creq,
 260                                                 engine->sram + len +
 261                                                 CESA_SA_DATA_SRAM_OFFSET);
 262                         }
 263
 264                         if (frag_mode == CESA_SA_DESC_CFG_LAST_FRAG)
 265                                 frag_mode = CESA_SA_DESC_CFG_MID_FRAG;
 266                         else
 267                                 frag_mode = CESA_SA_DESC_CFG_FIRST_FRAG;
 268                 }
 269         }
 270
 271         mv_cesa_set_mac_op_frag_len(op, len);
 272         mv_cesa_update_op_cfg(op, frag_mode, CESA_SA_DESC_CFG_FRAG_MSK);
 273
 274         /* FIXME: only update enc_len field */
 275         memcpy(engine->sram, op, sizeof(*op));
 276
 277         if (frag_mode == CESA_SA_DESC_CFG_FIRST_FRAG)
 278                 mv_cesa_update_op_cfg(op, CESA_SA_DESC_CFG_MID_FRAG,
 279                                       CESA_SA_DESC_CFG_FRAG_MSK);
 280
 281         creq->cache_ptr = new_cache_ptr;
 282
 283         mv_cesa_set_int_mask(engine, CESA_SA_INT_ACCEL0_DONE);
 284         writel_relaxed(CESA_SA_CFG_PARA_DIS, engine->regs + CESA_SA_CFG);
 285         writel(CESA_SA_CMD_EN_CESA_SA_ACCL0, engine->regs + CESA_SA_CMD);
 286 }
 287
 288 static int mv_cesa_ahash_std_process(struct ahash_request *req, u32 status)
 289 {
 290         struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
 291         struct mv_cesa_ahash_std_req *sreq = &creq->req.std;
 292
 293         if (sreq->offset < (req->nbytes - creq->cache_ptr))
 294                 return -EINPROGRESS;
 295
 296         return 0;
 297 }
 298
 299 static inline void mv_cesa_ahash_dma_prepare(struct ahash_request *req)
 300 {
 301         struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
 302         struct mv_cesa_tdma_req *dreq = &creq->req.dma.base;
 303
 304         mv_cesa_dma_prepare(dreq, dreq->base.engine);
 305 }
 306
 307 static void mv_cesa_ahash_std_prepare(struct ahash_request *req)
 308 {
 309         struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
 310         struct mv_cesa_ahash_std_req *sreq = &creq->req.std;
 311         struct mv_cesa_engine *engine = sreq->base.engine;
 312
 313         sreq->offset = 0;
 314         mv_cesa_adjust_op(engine, &creq->op_tmpl);
 315         memcpy(engine->sram, &creq->op_tmpl, sizeof(creq->op_tmpl));
 316 }
 317
 318 static void mv_cesa_ahash_step(struct crypto_async_request *req)
 319 {
 320         struct ahash_request *ahashreq = ahash_request_cast(req);
 321         struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
 322
 323         if (creq->req.base.type == CESA_DMA_REQ)
 324                 mv_cesa_dma_step(&creq->req.dma.base);
 325         else
 326                 mv_cesa_ahash_std_step(ahashreq);
 327 }
 328
 329 static int mv_cesa_ahash_process(struct crypto_async_request *req, u32 status)
 330 {
 331         struct ahash_request *ahashreq = ahash_request_cast(req);
 332         struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
 333         struct mv_cesa_engine *engine = creq->req.base.engine;
 334         unsigned int digsize;
 335         int ret, i;
 336
 337         if (creq->req.base.type == CESA_DMA_REQ)
 338                 ret = mv_cesa_dma_process(&creq->req.dma.base, status);
 339         else
 340                 ret = mv_cesa_ahash_std_process(ahashreq, status);
 341
 342         if (ret == -EINPROGRESS)
 343                 return ret;
 344
 345         digsize = crypto_ahash_digestsize(crypto_ahash_reqtfm(ahashreq));
 346         for (i = 0; i < digsize / 4; i++)
 347                 creq->state[i] = readl_relaxed(engine->regs + CESA_IVDIG(i));
 348
 349         if (creq->cache_ptr)
 350                 sg_pcopy_to_buffer(ahashreq->src, creq->src_nents,
 351                                    creq->cache,
 352                                    creq->cache_ptr,
 353                                    ahashreq->nbytes - creq->cache_ptr);
 354
 355         if (creq->last_req) {
 356                 /*
 357                  * Hardware's MD5 digest is in little endian format, but
 358                  * SHA in big endian format
 359                  */
 360                 if (creq->algo_le) {
 361                         __le32 *result = (void *)ahashreq->result;
 362
 363                         for (i = 0; i < digsize / 4; i++)
 364                                 result[i] = cpu_to_le32(creq->state[i]);
 365                 } else {
 366                         __be32 *result = (void *)ahashreq->result;
 367
 368                         for (i = 0; i < digsize / 4; i++)
 369                                 result[i] = cpu_to_be32(creq->state[i]);
 370                 }
 371         }
 372
 373         return ret;
 374 }
 375
 376 static void mv_cesa_ahash_prepare(struct crypto_async_request *req,
 377                                   struct mv_cesa_engine *engine)
 378 {
 379         struct ahash_request *ahashreq = ahash_request_cast(req);
 380         struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
 381         unsigned int digsize;
 382         int i;
 383
 384         creq->req.base.engine = engine;
 385
 386         if (creq->req.base.type == CESA_DMA_REQ)
 387                 mv_cesa_ahash_dma_prepare(ahashreq);
 388         else
 389                 mv_cesa_ahash_std_prepare(ahashreq);
 390
 391         digsize = crypto_ahash_digestsize(crypto_ahash_reqtfm(ahashreq));
 392         for (i = 0; i < digsize / 4; i++)
 393                 writel_relaxed(creq->state[i], engine->regs + CESA_IVDIG(i));
 394 }
 395
 396 static void mv_cesa_ahash_req_cleanup(struct crypto_async_request *req)
 397 {
 398         struct ahash_request *ahashreq = ahash_request_cast(req);
 399         struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
 400
 401         if (creq->last_req)
 402                 mv_cesa_ahash_last_cleanup(ahashreq);
 403
 404         mv_cesa_ahash_cleanup(ahashreq);
 405 }
 406
 407 static const struct mv_cesa_req_ops mv_cesa_ahash_req_ops = {
 408         .step = mv_cesa_ahash_step,
 409         .process = mv_cesa_ahash_process,
 410         .prepare = mv_cesa_ahash_prepare,
 411         .cleanup = mv_cesa_ahash_req_cleanup,
 412 };
 413
 414 static int mv_cesa_ahash_init(struct ahash_request *req,
 415                               struct mv_cesa_op_ctx *tmpl, bool algo_le)
 416 {
 417         struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
 418
 419         memset(creq, 0, sizeof(*creq));
 420         mv_cesa_update_op_cfg(tmpl,
 421                               CESA_SA_DESC_CFG_OP_MAC_ONLY |
 422                               CESA_SA_DESC_CFG_FIRST_FRAG,
 423                               CESA_SA_DESC_CFG_OP_MSK |
 424                               CESA_SA_DESC_CFG_FRAG_MSK);
 425         mv_cesa_set_mac_op_total_len(tmpl, 0);
 426         mv_cesa_set_mac_op_frag_len(tmpl, 0);
 427         creq->op_tmpl = *tmpl;
 428         creq->len = 0;
 429         creq->algo_le = algo_le;
 430
 431         return 0;
 432 }
 433
 434 static inline int mv_cesa_ahash_cra_init(struct crypto_tfm *tfm)
 435 {
 436         struct mv_cesa_hash_ctx *ctx = crypto_tfm_ctx(tfm);
 437
 438         ctx->base.ops = &mv_cesa_ahash_req_ops;
 439
 440         crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
 441                                  sizeof(struct mv_cesa_ahash_req));
 442         return 0;
 443 }
 444
 445 static int mv_cesa_ahash_cache_req(struct ahash_request *req, bool *cached)
 446 {
 447         struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
 448         int ret;
 449
 450         if (((creq->cache_ptr + req->nbytes) & CESA_HASH_BLOCK_SIZE_MSK) &&
 451             !creq->last_req) {
 452                 ret = mv_cesa_ahash_alloc_cache(req);
 453                 if (ret)
 454                         return ret;
 455         }
 456
 457         if (creq->cache_ptr + req->nbytes < 64 && !creq->last_req) {
 458                 *cached = true;
 459
 460                 if (!req->nbytes)
 461                         return 0;
 462
 463                 sg_pcopy_to_buffer(req->src, creq->src_nents,
 464                                    creq->cache + creq->cache_ptr,
 465                                    req->nbytes, 0);
 466
 467                 creq->cache_ptr += req->nbytes;
 468         }
 469
 470         return 0;
 471 }
 472
 473 static struct mv_cesa_op_ctx *
 474 mv_cesa_dma_add_frag(struct mv_cesa_tdma_chain *chain,
 475                      struct mv_cesa_op_ctx *tmpl, unsigned int frag_len,
 476                      gfp_t flags)
 477 {
 478         struct mv_cesa_op_ctx *op;
 479         int ret;
 480
 481         op = mv_cesa_dma_add_op(chain, tmpl, false, flags);
 482         if (IS_ERR(op))
 483                 return op;
 484
 485         /* Set the operation block fragment length. */
 486         mv_cesa_set_mac_op_frag_len(op, frag_len);
 487
 488         /* Append dummy desc to launch operation */
 489         ret = mv_cesa_dma_add_dummy_launch(chain, flags);
 490         if (ret)
 491                 return ERR_PTR(ret);
 492
 493         if (mv_cesa_mac_op_is_first_frag(tmpl))
 494                 mv_cesa_update_op_cfg(tmpl,
 495                                       CESA_SA_DESC_CFG_MID_FRAG,
 496                                       CESA_SA_DESC_CFG_FRAG_MSK);
 497
 498         return op;
 499 }
 500
 501 static int
 502 mv_cesa_ahash_dma_add_cache(struct mv_cesa_tdma_chain *chain,
 503                             struct mv_cesa_ahash_dma_iter *dma_iter,
 504                             struct mv_cesa_ahash_req *creq,
 505                             gfp_t flags)
 506 {
 507         struct mv_cesa_ahash_dma_req *ahashdreq = &creq->req.dma;
 508
 509         if (!creq->cache_ptr)
 510                 return 0;
 511
 512         return mv_cesa_dma_add_data_transfer(chain,
 513                                              CESA_SA_DATA_SRAM_OFFSET,
 514                                              ahashdreq->cache_dma,
 515                                              creq->cache_ptr,
 516                                              CESA_TDMA_DST_IN_SRAM,
 517                                              flags);
 518 }
 519
 520 static struct mv_cesa_op_ctx *
 521 mv_cesa_ahash_dma_last_req(struct mv_cesa_tdma_chain *chain,
 522                            struct mv_cesa_ahash_dma_iter *dma_iter,
 523                            struct mv_cesa_ahash_req *creq,
 524                            unsigned int frag_len, gfp_t flags)
 525 {
 526         struct mv_cesa_ahash_dma_req *ahashdreq = &creq->req.dma;
 527         unsigned int len, trailerlen, padoff = 0;
 528         struct mv_cesa_op_ctx *op;
 529         int ret;
 530
 531         /*
 532          * If the transfer is smaller than our maximum length, and we have
 533          * some data outstanding, we can ask the engine to finish the hash.
 534          */
 535         if (creq->len <= CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX && frag_len) {
 536                 op = mv_cesa_dma_add_frag(chain, &creq->op_tmpl, frag_len,
 537                                           flags);
 538                 if (IS_ERR(op))
 539                         return op;
 540
 541                 mv_cesa_set_mac_op_total_len(op, creq->len);
 542                 mv_cesa_update_op_cfg(op, mv_cesa_mac_op_is_first_frag(op) ?
 543                                                 CESA_SA_DESC_CFG_NOT_FRAG :
 544                                                 CESA_SA_DESC_CFG_LAST_FRAG,
 545                                       CESA_SA_DESC_CFG_FRAG_MSK);
 546
 547                 return op;
 548         }
 549
 550         /*
 551          * The request is longer than the engine can handle, or we have
 552          * no data outstanding. Manually generate the padding, adding it
 553          * as a "mid" fragment.
 554          */
 555         ret = mv_cesa_ahash_dma_alloc_padding(ahashdreq, flags);
 556         if (ret)
 557                 return ERR_PTR(ret);
 558
 559         trailerlen = mv_cesa_ahash_pad_req(creq, ahashdreq->padding);
 560
 561         len = min(CESA_SA_SRAM_PAYLOAD_SIZE - frag_len, trailerlen);
 562         if (len) {
 563                 ret = mv_cesa_dma_add_data_transfer(chain,
 564                                                 CESA_SA_DATA_SRAM_OFFSET +
 565                                                 frag_len,
 566                                                 ahashdreq->padding_dma,
 567                                                 len, CESA_TDMA_DST_IN_SRAM,
 568                                                 flags);
 569                 if (ret)
 570                         return ERR_PTR(ret);
 571
 572                 op = mv_cesa_dma_add_frag(chain, &creq->op_tmpl, frag_len + len,
 573                                           flags);
 574                 if (IS_ERR(op))
 575                         return op;
 576
 577                 if (len == trailerlen)
 578                         return op;
 579
 580                 padoff += len;
 581         }
 582
 583         ret = mv_cesa_dma_add_data_transfer(chain,
 584                                             CESA_SA_DATA_SRAM_OFFSET,
 585                                             ahashdreq->padding_dma +
 586                                             padoff,
 587                                             trailerlen - padoff,
 588                                             CESA_TDMA_DST_IN_SRAM,
 589                                             flags);
 590         if (ret)
 591                 return ERR_PTR(ret);
 592
 593         return mv_cesa_dma_add_frag(chain, &creq->op_tmpl, trailerlen - padoff,
 594                                     flags);
 595 }
 596
 597 static int mv_cesa_ahash_dma_req_init(struct ahash_request *req)
 598 {
 599         struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
 600         gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
 601                       GFP_KERNEL : GFP_ATOMIC;
 602         struct mv_cesa_ahash_dma_req *ahashdreq = &creq->req.dma;
 603         struct mv_cesa_tdma_req *dreq = &ahashdreq->base;
 604         struct mv_cesa_ahash_dma_iter iter;
 605         struct mv_cesa_op_ctx *op = NULL;
 606         unsigned int frag_len;
 607         int ret;
 608
 609         dreq->chain.first = NULL;
 610         dreq->chain.last = NULL;
 611
 612         if (creq->src_nents) {
 613                 ret = dma_map_sg(cesa_dev->dev, req->src, creq->src_nents,
 614                                  DMA_TO_DEVICE);
 615                 if (!ret) {
 616                         ret = -ENOMEM;
 617                         goto err;
 618                 }
 619         }
 620
 621         mv_cesa_tdma_desc_iter_init(&dreq->chain);
 622         mv_cesa_ahash_req_iter_init(&iter, req);
 623
 624         /*
 625          * Add the cache (left-over data from a previous block) first.
 626          * This will never overflow the SRAM size.
 627          */
 628         ret = mv_cesa_ahash_dma_add_cache(&dreq->chain, &iter, creq, flags);
 629         if (ret)
 630                 goto err_free_tdma;
 631
 632         if (iter.src.sg) {
 633                 /*
 634                  * Add all the new data, inserting an operation block and
 635                  * launch command between each full SRAM block-worth of
 636                  * data. We intentionally do not add the final op block.
 637                  */
 638                 while (true) {
 639                         ret = mv_cesa_dma_add_op_transfers(&dreq->chain,
 640                                                            &iter.base,
 641                                                            &iter.src, flags);
 642                         if (ret)
 643                                 goto err_free_tdma;
 644
 645                         frag_len = iter.base.op_len;
 646
 647                         if (!mv_cesa_ahash_req_iter_next_op(&iter))
 648                                 break;
 649
 650                         op = mv_cesa_dma_add_frag(&dreq->chain, &creq->op_tmpl,
 651                                                   frag_len, flags);
 652                         if (IS_ERR(op)) {
 653                                 ret = PTR_ERR(op);
 654                                 goto err_free_tdma;
 655                         }
 656                 }
 657         } else {
 658                 /* Account for the data that was in the cache. */
 659                 frag_len = iter.base.op_len;
 660         }
 661
 662         /*
 663          * At this point, frag_len indicates whether we have any data
 664          * outstanding which needs an operation.  Queue up the final
 665          * operation, which depends whether this is the final request.
 666          */
 667         if (creq->last_req)
 668                 op = mv_cesa_ahash_dma_last_req(&dreq->chain, &iter, creq,
 669                                                 frag_len, flags);
 670         else if (frag_len)
 671                 op = mv_cesa_dma_add_frag(&dreq->chain, &creq->op_tmpl,
 672                                           frag_len, flags);
 673
 674         if (IS_ERR(op)) {
 675                 ret = PTR_ERR(op);
 676                 goto err_free_tdma;
 677         }
 678
 679         if (op) {
 680                 /* Add dummy desc to wait for crypto operation end */
 681                 ret = mv_cesa_dma_add_dummy_end(&dreq->chain, flags);
 682                 if (ret)
 683                         goto err_free_tdma;
 684         }
 685
 686         if (!creq->last_req)
 687                 creq->cache_ptr = req->nbytes + creq->cache_ptr -
 688                                   iter.base.len;
 689         else
 690                 creq->cache_ptr = 0;
 691
 692         return 0;
 693
 694 err_free_tdma:
 695         mv_cesa_dma_cleanup(dreq);
 696         dma_unmap_sg(cesa_dev->dev, req->src, creq->src_nents, DMA_TO_DEVICE);
 697
 698 err:
 699         mv_cesa_ahash_last_cleanup(req);
 700
 701         return ret;
 702 }
 703
 704 static int mv_cesa_ahash_req_init(struct ahash_request *req, bool *cached)
 705 {
 706         struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
 707         int ret;
 708
 709         if (cesa_dev->caps->has_tdma)
 710                 creq->req.base.type = CESA_DMA_REQ;
 711         else
 712                 creq->req.base.type = CESA_STD_REQ;
 713
 714         creq->src_nents = sg_nents_for_len(req->src, req->nbytes);
 715
 716         ret = mv_cesa_ahash_cache_req(req, cached);
 717         if (ret)
 718                 return ret;
 719
 720         if (*cached)
 721                 return 0;
 722
 723         if (creq->req.base.type == CESA_DMA_REQ)
 724                 ret = mv_cesa_ahash_dma_req_init(req);
 725
 726         return ret;
 727 }
 728
 729 static int mv_cesa_ahash_update(struct ahash_request *req)
 730 {
 731         struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
 732         bool cached = false;
 733         int ret;
 734
 735         creq->len += req->nbytes;
 736         ret = mv_cesa_ahash_req_init(req, &cached);
 737         if (ret)
 738                 return ret;
 739
 740         if (cached)
 741                 return 0;
 742
 743         ret = mv_cesa_queue_req(&req->base);
 744         if (ret && ret != -EINPROGRESS) {
 745                 mv_cesa_ahash_cleanup(req);
 746                 return ret;
 747         }
 748
 749         return ret;
 750 }
 751
 752 static int mv_cesa_ahash_final(struct ahash_request *req)
 753 {
 754         struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
 755         struct mv_cesa_op_ctx *tmpl = &creq->op_tmpl;
 756         bool cached = false;
 757         int ret;
 758
 759         mv_cesa_set_mac_op_total_len(tmpl, creq->len);
 760         creq->last_req = true;
 761         req->nbytes = 0;
 762
 763         ret = mv_cesa_ahash_req_init(req, &cached);
 764         if (ret)
 765                 return ret;
 766
 767         if (cached)
 768                 return 0;
 769
 770         ret = mv_cesa_queue_req(&req->base);
 771         if (ret && ret != -EINPROGRESS)
 772                 mv_cesa_ahash_cleanup(req);
 773
 774         return ret;
 775 }
 776
 777 static int mv_cesa_ahash_finup(struct ahash_request *req)
 778 {
 779         struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
 780         struct mv_cesa_op_ctx *tmpl = &creq->op_tmpl;
 781         bool cached = false;
 782         int ret;
 783
 784         creq->len += req->nbytes;
 785         mv_cesa_set_mac_op_total_len(tmpl, creq->len);
 786         creq->last_req = true;
 787
 788         ret = mv_cesa_ahash_req_init(req, &cached);
 789         if (ret)
 790                 return ret;
 791
 792         if (cached)
 793                 return 0;
 794
 795         ret = mv_cesa_queue_req(&req->base);
 796         if (ret && ret != -EINPROGRESS)
 797                 mv_cesa_ahash_cleanup(req);
 798
 799         return ret;
 800 }
 801
 802 static int mv_cesa_ahash_export(struct ahash_request *req, void *hash,
 803                                 u64 *len, void *cache)
 804 {
 805         struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
 806         struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
 807         unsigned int digsize = crypto_ahash_digestsize(ahash);
 808         unsigned int blocksize;
 809
 810         blocksize = crypto_ahash_blocksize(ahash);
 811
 812         *len = creq->len;
 813         memcpy(hash, creq->state, digsize);
 814         memset(cache, 0, blocksize);
 815         if (creq->cache)
 816                 memcpy(cache, creq->cache, creq->cache_ptr);
 817
 818         return 0;
 819 }
 820
 821 static int mv_cesa_ahash_import(struct ahash_request *req, const void *hash,
 822                                 u64 len, const void *cache)
 823 {
 824         struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
 825         struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
 826         unsigned int digsize = crypto_ahash_digestsize(ahash);
 827         unsigned int blocksize;
 828         unsigned int cache_ptr;
 829         int ret;
 830
 831         ret = crypto_ahash_init(req);
 832         if (ret)
 833                 return ret;
 834
 835         blocksize = crypto_ahash_blocksize(ahash);
 836         if (len >= blocksize)
 837                 mv_cesa_update_op_cfg(&creq->op_tmpl,
 838                                       CESA_SA_DESC_CFG_MID_FRAG,
 839                                       CESA_SA_DESC_CFG_FRAG_MSK);
 840
 841         creq->len = len;
 842         memcpy(creq->state, hash, digsize);
 843         creq->cache_ptr = 0;
 844
 845         cache_ptr = do_div(len, blocksize);
 846         if (!cache_ptr)
 847                 return 0;
 848
 849         ret = mv_cesa_ahash_alloc_cache(req);
 850         if (ret)
 851                 return ret;
 852
 853         memcpy(creq->cache, cache, cache_ptr);
 854         creq->cache_ptr = cache_ptr;
 855
 856         return 0;
 857 }
 858
 859 static int mv_cesa_md5_init(struct ahash_request *req)
 860 {
 861         struct mv_cesa_op_ctx tmpl = { };
 862
 863         mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_MD5);
 864
 865         mv_cesa_ahash_init(req, &tmpl, true);
 866
 867         return 0;
 868 }
 869
 870 static int mv_cesa_md5_export(struct ahash_request *req, void *out)
 871 {
 872         struct md5_state *out_state = out;
 873
 874         return mv_cesa_ahash_export(req, out_state->hash,
 875                                     &out_state->byte_count, out_state->block);
 876 }
 877
 878 static int mv_cesa_md5_import(struct ahash_request *req, const void *in)
 879 {
 880         const struct md5_state *in_state = in;
 881
 882         return mv_cesa_ahash_import(req, in_state->hash, in_state->byte_count,
 883                                     in_state->block);
 884 }
 885
 886 static int mv_cesa_md5_digest(struct ahash_request *req)
 887 {
 888         int ret;
 889
 890         ret = mv_cesa_md5_init(req);
 891         if (ret)
 892                 return ret;
 893
 894         return mv_cesa_ahash_finup(req);
 895 }
 896
 897 struct ahash_alg mv_md5_alg = {
 898         .init = mv_cesa_md5_init,
 899         .update = mv_cesa_ahash_update,
 900         .final = mv_cesa_ahash_final,
 901         .finup = mv_cesa_ahash_finup,
 902         .digest = mv_cesa_md5_digest,
 903         .export = mv_cesa_md5_export,
 904         .import = mv_cesa_md5_import,
 905         .halg = {
 906                 .digestsize = MD5_DIGEST_SIZE,
 907                 .statesize = sizeof(struct md5_state),
 908                 .base = {
 909                         .cra_name = "md5",
 910                         .cra_driver_name = "mv-md5",
 911                         .cra_priority = 300,
 912                         .cra_flags = CRYPTO_ALG_ASYNC |
 913                                      CRYPTO_ALG_KERN_DRIVER_ONLY,
 914                         .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
 915                         .cra_ctxsize = sizeof(struct mv_cesa_hash_ctx),
 916                         .cra_init = mv_cesa_ahash_cra_init,
 917                         .cra_module = THIS_MODULE,
 918                  }
 919         }
 920 };
 921
 922 static int mv_cesa_sha1_init(struct ahash_request *req)
 923 {
 924         struct mv_cesa_op_ctx tmpl = { };
 925
 926         mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_SHA1);
 927
 928         mv_cesa_ahash_init(req, &tmpl, false);
 929
 930         return 0;
 931 }
 932
 933 static int mv_cesa_sha1_export(struct ahash_request *req, void *out)
 934 {
 935         struct sha1_state *out_state = out;
 936
 937         return mv_cesa_ahash_export(req, out_state->state, &out_state->count,
 938                                     out_state->buffer);
 939 }
 940
 941 static int mv_cesa_sha1_import(struct ahash_request *req, const void *in)
 942 {
 943         const struct sha1_state *in_state = in;
 944
 945         return mv_cesa_ahash_import(req, in_state->state, in_state->count,
 946                                     in_state->buffer);
 947 }
 948
 949 static int mv_cesa_sha1_digest(struct ahash_request *req)
 950 {
 951         int ret;
 952
 953         ret = mv_cesa_sha1_init(req);
 954         if (ret)
 955                 return ret;
 956
 957         return mv_cesa_ahash_finup(req);
 958 }
 959
 960 struct ahash_alg mv_sha1_alg = {
 961         .init = mv_cesa_sha1_init,
 962         .update = mv_cesa_ahash_update,
 963         .final = mv_cesa_ahash_final,
 964         .finup = mv_cesa_ahash_finup,
 965         .digest = mv_cesa_sha1_digest,
 966         .export = mv_cesa_sha1_export,
 967         .import = mv_cesa_sha1_import,
 968         .halg = {
 969                 .digestsize = SHA1_DIGEST_SIZE,
 970                 .statesize = sizeof(struct sha1_state),
 971                 .base = {
 972                         .cra_name = "sha1",
 973                         .cra_driver_name = "mv-sha1",
 974                         .cra_priority = 300,
 975                         .cra_flags = CRYPTO_ALG_ASYNC |
 976                                      CRYPTO_ALG_KERN_DRIVER_ONLY,
 977                         .cra_blocksize = SHA1_BLOCK_SIZE,
 978                         .cra_ctxsize = sizeof(struct mv_cesa_hash_ctx),
 979                         .cra_init = mv_cesa_ahash_cra_init,
 980                         .cra_module = THIS_MODULE,
 981                  }
 982         }
 983 };
 984
 985 static int mv_cesa_sha256_init(struct ahash_request *req)
 986 {
 987         struct mv_cesa_op_ctx tmpl = { };
 988
 989         mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_SHA256);
 990
 991         mv_cesa_ahash_init(req, &tmpl, false);
 992
 993         return 0;
 994 }
 995
 996 static int mv_cesa_sha256_digest(struct ahash_request *req)
 997 {
 998         int ret;
 999
1000         ret = mv_cesa_sha256_init(req);
1001         if (ret)
1002                 return ret;
1003
1004         return mv_cesa_ahash_finup(req);
1005 }
1006
1007 static int mv_cesa_sha256_export(struct ahash_request *req, void *out)
1008 {
1009         struct sha256_state *out_state = out;
1010
1011         return mv_cesa_ahash_export(req, out_state->state, &out_state->count,
1012                                     out_state->buf);
1013 }
1014
1015 static int mv_cesa_sha256_import(struct ahash_request *req, const void *in)
1016 {
1017         const struct sha256_state *in_state = in;
1018
1019         return mv_cesa_ahash_import(req, in_state->state, in_state->count,
1020                                     in_state->buf);
1021 }
1022
1023 struct ahash_alg mv_sha256_alg = {
1024         .init = mv_cesa_sha256_init,
1025         .update = mv_cesa_ahash_update,
1026         .final = mv_cesa_ahash_final,
1027         .finup = mv_cesa_ahash_finup,
1028         .digest = mv_cesa_sha256_digest,
1029         .export = mv_cesa_sha256_export,
1030         .import = mv_cesa_sha256_import,
1031         .halg = {
1032                 .digestsize = SHA256_DIGEST_SIZE,
1033                 .statesize = sizeof(struct sha256_state),
1034                 .base = {
1035                         .cra_name = "sha256",
1036                         .cra_driver_name = "mv-sha256",
1037                         .cra_priority = 300,
1038                         .cra_flags = CRYPTO_ALG_ASYNC |
1039                                      CRYPTO_ALG_KERN_DRIVER_ONLY,
1040                         .cra_blocksize = SHA256_BLOCK_SIZE,
1041                         .cra_ctxsize = sizeof(struct mv_cesa_hash_ctx),
1042                         .cra_init = mv_cesa_ahash_cra_init,
1043                         .cra_module = THIS_MODULE,
1044                  }
1045         }
1046 };
1047
1048 struct mv_cesa_ahash_result {
1049         struct completion completion;
1050         int error;
1051 };
1052
1053 static void mv_cesa_hmac_ahash_complete(struct crypto_async_request *req,
1054                                         int error)
1055 {
1056         struct mv_cesa_ahash_result *result = req->data;
1057
1058         if (error == -EINPROGRESS)
1059                 return;
1060
1061         result->error = error;
1062         complete(&result->completion);
1063 }
1064
1065 static int mv_cesa_ahmac_iv_state_init(struct ahash_request *req, u8 *pad,
1066                                        void *state, unsigned int blocksize)
1067 {
1068         struct mv_cesa_ahash_result result;
1069         struct scatterlist sg;
1070         int ret;
1071
1072         ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
1073                                    mv_cesa_hmac_ahash_complete, &result);
1074         sg_init_one(&sg, pad, blocksize);
1075         ahash_request_set_crypt(req, &sg, pad, blocksize);
1076         init_completion(&result.completion);
1077
1078         ret = crypto_ahash_init(req);
1079         if (ret)
1080                 return ret;
1081
1082         ret = crypto_ahash_update(req);
1083         if (ret && ret != -EINPROGRESS)
1084                 return ret;
1085
1086         wait_for_completion_interruptible(&result.completion);
1087         if (result.error)
1088                 return result.error;
1089
1090         ret = crypto_ahash_export(req, state);
1091         if (ret)
1092                 return ret;
1093
1094         return 0;
1095 }
1096
1097 static int mv_cesa_ahmac_pad_init(struct ahash_request *req,
1098                                   const u8 *key, unsigned int keylen,
1099                                   u8 *ipad, u8 *opad,
1100                                   unsigned int blocksize)
1101 {
1102         struct mv_cesa_ahash_result result;
1103         struct scatterlist sg;
1104         int ret;
1105         int i;
1106
1107         if (keylen <= blocksize) {
1108                 memcpy(ipad, key, keylen);
1109         } else {
1110                 u8 *keydup = kmemdup(key, keylen, GFP_KERNEL);
1111
1112                 if (!keydup)
1113                         return -ENOMEM;
1114
1115                 ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
1116                                            mv_cesa_hmac_ahash_complete,
1117                                            &result);
1118                 sg_init_one(&sg, keydup, keylen);
1119                 ahash_request_set_crypt(req, &sg, ipad, keylen);
1120                 init_completion(&result.completion);
1121
1122                 ret = crypto_ahash_digest(req);
1123                 if (ret == -EINPROGRESS) {
1124                         wait_for_completion_interruptible(&result.completion);
1125                         ret = result.error;
1126                 }
1127
1128                 /* Set the memory region to 0 to avoid any leak. */
1129                 memset(keydup, 0, keylen);
1130                 kfree(keydup);
1131
1132                 if (ret)
1133                         return ret;
1134
1135                 keylen = crypto_ahash_digestsize(crypto_ahash_reqtfm(req));
1136         }
1137
1138         memset(ipad + keylen, 0, blocksize - keylen);
1139         memcpy(opad, ipad, blocksize);
1140
1141         for (i = 0; i < blocksize; i++) {
1142                 ipad[i] ^= 0x36;
1143                 opad[i] ^= 0x5c;
1144         }
1145
1146         return 0;
1147 }
1148
1149 static int mv_cesa_ahmac_setkey(const char *hash_alg_name,
1150                                 const u8 *key, unsigned int keylen,
1151                                 void *istate, void *ostate)
1152 {
1153         struct ahash_request *req;
1154         struct crypto_ahash *tfm;
1155         unsigned int blocksize;
1156         u8 *ipad = NULL;
1157         u8 *opad;
1158         int ret;
1159
1160         tfm = crypto_alloc_ahash(hash_alg_name, CRYPTO_ALG_TYPE_AHASH,
1161                                  CRYPTO_ALG_TYPE_AHASH_MASK);
1162         if (IS_ERR(tfm))
1163                 return PTR_ERR(tfm);
1164
1165         req = ahash_request_alloc(tfm, GFP_KERNEL);
1166         if (!req) {
1167                 ret = -ENOMEM;
1168                 goto free_ahash;
1169         }
1170
1171         crypto_ahash_clear_flags(tfm, ~0);
1172
1173         blocksize = crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1174
1175         ipad = kzalloc(2 * blocksize, GFP_KERNEL);
1176         if (!ipad) {
1177                 ret = -ENOMEM;
1178                 goto free_req;
1179         }
1180
1181         opad = ipad + blocksize;
1182
1183         ret = mv_cesa_ahmac_pad_init(req, key, keylen, ipad, opad, blocksize);
1184         if (ret)
1185                 goto free_ipad;
1186
1187         ret = mv_cesa_ahmac_iv_state_init(req, ipad, istate, blocksize);
1188         if (ret)
1189                 goto free_ipad;
1190
1191         ret = mv_cesa_ahmac_iv_state_init(req, opad, ostate, blocksize);
1192
1193 free_ipad:
1194         kfree(ipad);
1195 free_req:
1196         ahash_request_free(req);
1197 free_ahash:
1198         crypto_free_ahash(tfm);
1199
1200         return ret;
1201 }
1202
1203 static int mv_cesa_ahmac_cra_init(struct crypto_tfm *tfm)
1204 {
1205         struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(tfm);
1206
1207         ctx->base.ops = &mv_cesa_ahash_req_ops;
1208
1209         crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1210                                  sizeof(struct mv_cesa_ahash_req));
1211         return 0;
1212 }
1213
1214 static int mv_cesa_ahmac_md5_init(struct ahash_request *req)
1215 {
1216         struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
1217         struct mv_cesa_op_ctx tmpl = { };
1218
1219         mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_HMAC_MD5);
1220         memcpy(tmpl.ctx.hash.iv, ctx->iv, sizeof(ctx->iv));
1221
1222         mv_cesa_ahash_init(req, &tmpl, true);
1223
1224         return 0;
1225 }
1226
1227 static int mv_cesa_ahmac_md5_setkey(struct crypto_ahash *tfm, const u8 *key,
1228                                     unsigned int keylen)
1229 {
1230         struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1231         struct md5_state istate, ostate;
1232         int ret, i;
1233
1234         ret = mv_cesa_ahmac_setkey("mv-md5", key, keylen, &istate, &ostate);
1235         if (ret)
1236                 return ret;
1237
1238         for (i = 0; i < ARRAY_SIZE(istate.hash); i++)
1239                 ctx->iv[i] = be32_to_cpu(istate.hash[i]);
1240
1241         for (i = 0; i < ARRAY_SIZE(ostate.hash); i++)
1242                 ctx->iv[i + 8] = be32_to_cpu(ostate.hash[i]);
1243
1244         return 0;
1245 }
1246
1247 static int mv_cesa_ahmac_md5_digest(struct ahash_request *req)
1248 {
1249         int ret;
1250
1251         ret = mv_cesa_ahmac_md5_init(req);
1252         if (ret)
1253                 return ret;
1254
1255         return mv_cesa_ahash_finup(req);
1256 }
1257
1258 struct ahash_alg mv_ahmac_md5_alg = {
1259         .init = mv_cesa_ahmac_md5_init,
1260         .update = mv_cesa_ahash_update,
1261         .final = mv_cesa_ahash_final,
1262         .finup = mv_cesa_ahash_finup,
1263         .digest = mv_cesa_ahmac_md5_digest,
1264         .setkey = mv_cesa_ahmac_md5_setkey,
1265         .export = mv_cesa_md5_export,
1266         .import = mv_cesa_md5_import,
1267         .halg = {
1268                 .digestsize = MD5_DIGEST_SIZE,
1269                 .statesize = sizeof(struct md5_state),
1270                 .base = {
1271                         .cra_name = "hmac(md5)",
1272                         .cra_driver_name = "mv-hmac-md5",
1273                         .cra_priority = 300,
1274                         .cra_flags = CRYPTO_ALG_ASYNC |
1275                                      CRYPTO_ALG_KERN_DRIVER_ONLY,
1276                         .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
1277                         .cra_ctxsize = sizeof(struct mv_cesa_hmac_ctx),
1278                         .cra_init = mv_cesa_ahmac_cra_init,
1279                         .cra_module = THIS_MODULE,
1280                  }
1281         }
1282 };
1283
1284 static int mv_cesa_ahmac_sha1_init(struct ahash_request *req)
1285 {
1286         struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
1287         struct mv_cesa_op_ctx tmpl = { };
1288
1289         mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_HMAC_SHA1);
1290         memcpy(tmpl.ctx.hash.iv, ctx->iv, sizeof(ctx->iv));
1291
1292         mv_cesa_ahash_init(req, &tmpl, false);
1293
1294         return 0;
1295 }
1296
1297 static int mv_cesa_ahmac_sha1_setkey(struct crypto_ahash *tfm, const u8 *key,
1298                                      unsigned int keylen)
1299 {
1300         struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1301         struct sha1_state istate, ostate;
1302         int ret, i;
1303
1304         ret = mv_cesa_ahmac_setkey("mv-sha1", key, keylen, &istate, &ostate);
1305         if (ret)
1306                 return ret;
1307
1308         for (i = 0; i < ARRAY_SIZE(istate.state); i++)
1309                 ctx->iv[i] = be32_to_cpu(istate.state[i]);
1310
1311         for (i = 0; i < ARRAY_SIZE(ostate.state); i++)
1312                 ctx->iv[i + 8] = be32_to_cpu(ostate.state[i]);
1313
1314         return 0;
1315 }
1316
1317 static int mv_cesa_ahmac_sha1_digest(struct ahash_request *req)
1318 {
1319         int ret;
1320
1321         ret = mv_cesa_ahmac_sha1_init(req);
1322         if (ret)
1323                 return ret;
1324
1325         return mv_cesa_ahash_finup(req);
1326 }
1327
1328 struct ahash_alg mv_ahmac_sha1_alg = {
1329         .init = mv_cesa_ahmac_sha1_init,
1330         .update = mv_cesa_ahash_update,
1331         .final = mv_cesa_ahash_final,
1332         .finup = mv_cesa_ahash_finup,
1333         .digest = mv_cesa_ahmac_sha1_digest,
1334         .setkey = mv_cesa_ahmac_sha1_setkey,
1335         .export = mv_cesa_sha1_export,
1336         .import = mv_cesa_sha1_import,
1337         .halg = {
1338                 .digestsize = SHA1_DIGEST_SIZE,
1339                 .statesize = sizeof(struct sha1_state),
1340                 .base = {
1341                         .cra_name = "hmac(sha1)",
1342                         .cra_driver_name = "mv-hmac-sha1",
1343                         .cra_priority = 300,
1344                         .cra_flags = CRYPTO_ALG_ASYNC |
1345                                      CRYPTO_ALG_KERN_DRIVER_ONLY,
1346                         .cra_blocksize = SHA1_BLOCK_SIZE,
1347                         .cra_ctxsize = sizeof(struct mv_cesa_hmac_ctx),
1348                         .cra_init = mv_cesa_ahmac_cra_init,
1349                         .cra_module = THIS_MODULE,
1350                  }
1351         }
1352 };
1353
1354 static int mv_cesa_ahmac_sha256_setkey(struct crypto_ahash *tfm, const u8 *key,
1355                                        unsigned int keylen)
1356 {
1357         struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1358         struct sha256_state istate, ostate;
1359         int ret, i;
1360
1361         ret = mv_cesa_ahmac_setkey("mv-sha256", key, keylen, &istate, &ostate);
1362         if (ret)
1363                 return ret;
1364
1365         for (i = 0; i < ARRAY_SIZE(istate.state); i++)
1366                 ctx->iv[i] = be32_to_cpu(istate.state[i]);
1367
1368         for (i = 0; i < ARRAY_SIZE(ostate.state); i++)
1369                 ctx->iv[i + 8] = be32_to_cpu(ostate.state[i]);
1370
1371         return 0;
1372 }
1373
1374 static int mv_cesa_ahmac_sha256_init(struct ahash_request *req)
1375 {
1376         struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
1377         struct mv_cesa_op_ctx tmpl = { };
1378
1379         mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_HMAC_SHA256);
1380         memcpy(tmpl.ctx.hash.iv, ctx->iv, sizeof(ctx->iv));
1381
1382         mv_cesa_ahash_init(req, &tmpl, false);
1383
1384         return 0;
1385 }
1386
1387 static int mv_cesa_ahmac_sha256_digest(struct ahash_request *req)
1388 {
1389         int ret;
1390
1391         ret = mv_cesa_ahmac_sha256_init(req);
1392         if (ret)
1393                 return ret;
1394
1395         return mv_cesa_ahash_finup(req);
1396 }
1397
1398 struct ahash_alg mv_ahmac_sha256_alg = {
1399         .init = mv_cesa_ahmac_sha256_init,
1400         .update = mv_cesa_ahash_update,
1401         .final = mv_cesa_ahash_final,
1402         .finup = mv_cesa_ahash_finup,
1403         .digest = mv_cesa_ahmac_sha256_digest,
1404         .setkey = mv_cesa_ahmac_sha256_setkey,
1405         .export = mv_cesa_sha256_export,
1406         .import = mv_cesa_sha256_import,
1407         .halg = {
1408                 .digestsize = SHA256_DIGEST_SIZE,
1409                 .statesize = sizeof(struct sha256_state),
1410                 .base = {
1411                         .cra_name = "hmac(sha256)",
1412                         .cra_driver_name = "mv-hmac-sha256",
1413                         .cra_priority = 300,
1414                         .cra_flags = CRYPTO_ALG_ASYNC |
1415                                      CRYPTO_ALG_KERN_DRIVER_ONLY,
1416                         .cra_blocksize = SHA256_BLOCK_SIZE,
1417                         .cra_ctxsize = sizeof(struct mv_cesa_hmac_ctx),
1418                         .cra_init = mv_cesa_ahmac_cra_init,
1419                         .cra_module = THIS_MODULE,
1420                  }
1421         }
1422 };