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KVM: MMU: Only indicate a fetch fault in page fault error code if nx is enabled
[linux-2.6/btrfs-unstable.git] / arch / x86 / kvm / paging_tmpl.h
blob3a3f6d784d7947445187532561c71cb8b5acf247
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affilates.
11 *
12 * Authors:
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
21 /*
22 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
23 * so the code in this file is compiled twice, once per pte size.
24 */
25
26 #if PTTYPE == 64
27 #define pt_element_t u64
28 #define guest_walker guest_walker64
29 #define FNAME(name) paging##64_##name
30 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
31 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
32 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
33 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
34 #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
35 #define PT_LEVEL_BITS PT64_LEVEL_BITS
36 #ifdef CONFIG_X86_64
37 #define PT_MAX_FULL_LEVELS 4
38 #define CMPXCHG cmpxchg
39 #else
40 #define CMPXCHG cmpxchg64
41 #define PT_MAX_FULL_LEVELS 2
42 #endif
43 #elif PTTYPE == 32
44 #define pt_element_t u32
45 #define guest_walker guest_walker32
46 #define FNAME(name) paging##32_##name
47 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
48 #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
49 #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
50 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
51 #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
52 #define PT_LEVEL_BITS PT32_LEVEL_BITS
53 #define PT_MAX_FULL_LEVELS 2
54 #define CMPXCHG cmpxchg
55 #else
56 #error Invalid PTTYPE value
57 #endif
58
59 #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
60 #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
61
62 /*
63 * The guest_walker structure emulates the behavior of the hardware page
64 * table walker.
65 */
66 struct guest_walker {
67 int level;
68 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
69 pt_element_t ptes[PT_MAX_FULL_LEVELS];
70 gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
71 unsigned pt_access;
72 unsigned pte_access;
73 gfn_t gfn;
74 u32 error_code;
75 };
76
77 static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
78 {
79 return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
80 }
81
82 static bool FNAME(cmpxchg_gpte)(struct kvm *kvm,
83 gfn_t table_gfn, unsigned index,
84 pt_element_t orig_pte, pt_element_t new_pte)
85 {
86 pt_element_t ret;
87 pt_element_t *table;
88 struct page *page;
89
90 page = gfn_to_page(kvm, table_gfn);
91
92 table = kmap_atomic(page, KM_USER0);
93 ret = CMPXCHG(&table[index], orig_pte, new_pte);
94 kunmap_atomic(table, KM_USER0);
95
96 kvm_release_page_dirty(page);
97
98 return (ret != orig_pte);
99 }
100
101 static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte)
102 {
103 unsigned access;
104
105 access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
106 #if PTTYPE == 64
107 if (is_nx(vcpu))
108 access &= ~(gpte >> PT64_NX_SHIFT);
109 #endif
110 return access;
111 }
112
113 /*
114 * Fetch a guest pte for a guest virtual address
115 */
116 static int FNAME(walk_addr)(struct guest_walker *walker,
117 struct kvm_vcpu *vcpu, gva_t addr,
118 int write_fault, int user_fault, int fetch_fault)
119 {
120 pt_element_t pte;
121 gfn_t table_gfn;
122 unsigned index, pt_access, pte_access;
123 gpa_t pte_gpa;
124 int rsvd_fault = 0;
125
126 trace_kvm_mmu_pagetable_walk(addr, write_fault, user_fault,
127 fetch_fault);
128 walk:
129 walker->level = vcpu->arch.mmu.root_level;
130 pte = vcpu->arch.cr3;
131 #if PTTYPE == 64
132 if (!is_long_mode(vcpu)) {
133 pte = kvm_pdptr_read(vcpu, (addr >> 30) & 3);
134 trace_kvm_mmu_paging_element(pte, walker->level);
135 if (!is_present_gpte(pte))
136 goto not_present;
137 --walker->level;
138 }
139 #endif
140 ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
141 (vcpu->arch.cr3 & CR3_NONPAE_RESERVED_BITS) == 0);
142
143 pt_access = ACC_ALL;
144
145 for (;;) {
146 index = PT_INDEX(addr, walker->level);
147
148 table_gfn = gpte_to_gfn(pte);
149 pte_gpa = gfn_to_gpa(table_gfn);
150 pte_gpa += index * sizeof(pt_element_t);
151 walker->table_gfn[walker->level - 1] = table_gfn;
152 walker->pte_gpa[walker->level - 1] = pte_gpa;
153
154 if (kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte)))
155 goto not_present;
156
157 trace_kvm_mmu_paging_element(pte, walker->level);
158
159 if (!is_present_gpte(pte))
160 goto not_present;
161
162 rsvd_fault = is_rsvd_bits_set(vcpu, pte, walker->level);
163 if (rsvd_fault)
164 goto access_error;
165
166 if (write_fault && !is_writable_pte(pte))
167 if (user_fault || is_write_protection(vcpu))
168 goto access_error;
169
170 if (user_fault && !(pte & PT_USER_MASK))
171 goto access_error;
172
173 #if PTTYPE == 64
174 if (fetch_fault && (pte & PT64_NX_MASK))
175 goto access_error;
176 #endif
177
178 if (!(pte & PT_ACCESSED_MASK)) {
179 trace_kvm_mmu_set_accessed_bit(table_gfn, index,
180 sizeof(pte));
181 if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn,
182 index, pte, pte|PT_ACCESSED_MASK))
183 goto walk;
184 mark_page_dirty(vcpu->kvm, table_gfn);
185 pte |= PT_ACCESSED_MASK;
186 }
187
188 pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);
189
190 walker->ptes[walker->level - 1] = pte;
191
192 if ((walker->level == PT_PAGE_TABLE_LEVEL) ||
193 ((walker->level == PT_DIRECTORY_LEVEL) &&
194 is_large_pte(pte) &&
195 (PTTYPE == 64 || is_pse(vcpu))) ||
196 ((walker->level == PT_PDPE_LEVEL) &&
197 is_large_pte(pte) &&
198 is_long_mode(vcpu))) {
199 int lvl = walker->level;
200
201 walker->gfn = gpte_to_gfn_lvl(pte, lvl);
202 walker->gfn += (addr & PT_LVL_OFFSET_MASK(lvl))
203 >> PAGE_SHIFT;
204
205 if (PTTYPE == 32 &&
206 walker->level == PT_DIRECTORY_LEVEL &&
207 is_cpuid_PSE36())
208 walker->gfn += pse36_gfn_delta(pte);
209
210 break;
211 }
212
213 pt_access = pte_access;
214 --walker->level;
215 }
216
217 if (write_fault && !is_dirty_gpte(pte)) {
218 bool ret;
219
220 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
221 ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte,
222 pte|PT_DIRTY_MASK);
223 if (ret)
224 goto walk;
225 mark_page_dirty(vcpu->kvm, table_gfn);
226 pte |= PT_DIRTY_MASK;
227 walker->ptes[walker->level - 1] = pte;
228 }
229
230 walker->pt_access = pt_access;
231 walker->pte_access = pte_access;
232 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
233 __func__, (u64)pte, pte_access, pt_access);
234 return 1;
235
236 not_present:
237 walker->error_code = 0;
238 goto err;
239
240 access_error:
241 walker->error_code = PFERR_PRESENT_MASK;
242
243 err:
244 if (write_fault)
245 walker->error_code |= PFERR_WRITE_MASK;
246 if (user_fault)
247 walker->error_code |= PFERR_USER_MASK;
248 if (fetch_fault && is_nx(vcpu))
249 walker->error_code |= PFERR_FETCH_MASK;
250 if (rsvd_fault)
251 walker->error_code |= PFERR_RSVD_MASK;
252 trace_kvm_mmu_walker_error(walker->error_code);
253 return 0;
254 }
255
256 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
257 u64 *spte, const void *pte)
258 {
259 pt_element_t gpte;
260 unsigned pte_access;
261 pfn_t pfn;
262 u64 new_spte;
263
264 gpte = *(const pt_element_t *)pte;
265 if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) {
266 if (!is_present_gpte(gpte)) {
267 if (sp->unsync)
268 new_spte = shadow_trap_nonpresent_pte;
269 else
270 new_spte = shadow_notrap_nonpresent_pte;
271 __set_spte(spte, new_spte);
272 }
273 return;
274 }
275 pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
276 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
277 if (gpte_to_gfn(gpte) != vcpu->arch.update_pte.gfn)
278 return;
279 pfn = vcpu->arch.update_pte.pfn;
280 if (is_error_pfn(pfn))
281 return;
282 if (mmu_notifier_retry(vcpu, vcpu->arch.update_pte.mmu_seq))
283 return;
284 kvm_get_pfn(pfn);
285 /*
286 * we call mmu_set_spte() with reset_host_protection = true beacuse that
287 * vcpu->arch.update_pte.pfn was fetched from get_user_pages(write = 1).
288 */
289 mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0,
290 is_dirty_gpte(gpte), NULL, PT_PAGE_TABLE_LEVEL,
291 gpte_to_gfn(gpte), pfn, true, true);
292 }
293
294 /*
295 * Fetch a shadow pte for a specific level in the paging hierarchy.
296 */
297 static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
298 struct guest_walker *gw,
299 int user_fault, int write_fault, int hlevel,
300 int *ptwrite, pfn_t pfn)
301 {
302 unsigned access = gw->pt_access;
303 struct kvm_mmu_page *sp;
304 u64 spte, *sptep = NULL;
305 int direct;
306 gfn_t table_gfn;
307 int r;
308 int level;
309 bool dirty = is_dirty_gpte(gw->ptes[gw->level - 1]);
310 unsigned direct_access;
311 pt_element_t curr_pte;
312 struct kvm_shadow_walk_iterator iterator;
313
314 if (!is_present_gpte(gw->ptes[gw->level - 1]))
315 return NULL;
316
317 direct_access = gw->pt_access & gw->pte_access;
318 if (!dirty)
319 direct_access &= ~ACC_WRITE_MASK;
320
321 for_each_shadow_entry(vcpu, addr, iterator) {
322 level = iterator.level;
323 sptep = iterator.sptep;
324 if (iterator.level == hlevel) {
325 mmu_set_spte(vcpu, sptep, access,
326 gw->pte_access & access,
327 user_fault, write_fault,
328 dirty, ptwrite, level,
329 gw->gfn, pfn, false, true);
330 break;
331 }
332
333 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
334 struct kvm_mmu_page *child;
335
336 if (level != gw->level)
337 continue;
338
339 /*
340 * For the direct sp, if the guest pte's dirty bit
341 * changed form clean to dirty, it will corrupt the
342 * sp's access: allow writable in the read-only sp,
343 * so we should update the spte at this point to get
344 * a new sp with the correct access.
345 */
346 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
347 if (child->role.access == direct_access)
348 continue;
349
350 mmu_page_remove_parent_pte(child, sptep);
351 __set_spte(sptep, shadow_trap_nonpresent_pte);
352 kvm_flush_remote_tlbs(vcpu->kvm);
353 }
354
355 if (is_large_pte(*sptep)) {
356 drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte);
357 kvm_flush_remote_tlbs(vcpu->kvm);
358 }
359
360 if (level <= gw->level) {
361 direct = 1;
362 access = direct_access;
363
364 /*
365 * It is a large guest pages backed by small host pages,
366 * So we set @direct(@sp->role.direct)=1, and set
367 * @table_gfn(@sp->gfn)=the base page frame for linear
368 * translations.
369 */
370 table_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
371 access &= gw->pte_access;
372 } else {
373 direct = 0;
374 table_gfn = gw->table_gfn[level - 2];
375 }
376 sp = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
377 direct, access, sptep);
378 if (!direct) {
379 r = kvm_read_guest_atomic(vcpu->kvm,
380 gw->pte_gpa[level - 2],
381 &curr_pte, sizeof(curr_pte));
382 if (r || curr_pte != gw->ptes[level - 2]) {
383 kvm_mmu_put_page(sp, sptep);
384 kvm_release_pfn_clean(pfn);
385 sptep = NULL;
386 break;
387 }
388 }
389
390 spte = __pa(sp->spt)
391 | PT_PRESENT_MASK | PT_ACCESSED_MASK
392 | PT_WRITABLE_MASK | PT_USER_MASK;
393 *sptep = spte;
394 }
395
396 return sptep;
397 }
398
399 /*
400 * Page fault handler. There are several causes for a page fault:
401 * - there is no shadow pte for the guest pte
402 * - write access through a shadow pte marked read only so that we can set
403 * the dirty bit
404 * - write access to a shadow pte marked read only so we can update the page
405 * dirty bitmap, when userspace requests it
406 * - mmio access; in this case we will never install a present shadow pte
407 * - normal guest page fault due to the guest pte marked not present, not
408 * writable, or not executable
409 *
410 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
411 * a negative value on error.
412 */
413 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
414 u32 error_code)
415 {
416 int write_fault = error_code & PFERR_WRITE_MASK;
417 int user_fault = error_code & PFERR_USER_MASK;
418 int fetch_fault = error_code & PFERR_FETCH_MASK;
419 struct guest_walker walker;
420 u64 *sptep;
421 int write_pt = 0;
422 int r;
423 pfn_t pfn;
424 int level = PT_PAGE_TABLE_LEVEL;
425 unsigned long mmu_seq;
426
427 pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
428 kvm_mmu_audit(vcpu, "pre page fault");
429
430 r = mmu_topup_memory_caches(vcpu);
431 if (r)
432 return r;
433
434 /*
435 * Look up the guest pte for the faulting address.
436 */
437 r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
438 fetch_fault);
439
440 /*
441 * The page is not mapped by the guest. Let the guest handle it.
442 */
443 if (!r) {
444 pgprintk("%s: guest page fault\n", __func__);
445 inject_page_fault(vcpu, addr, walker.error_code);
446 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
447 return 0;
448 }
449
450 if (walker.level >= PT_DIRECTORY_LEVEL) {
451 level = min(walker.level, mapping_level(vcpu, walker.gfn));
452 walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
453 }
454
455 mmu_seq = vcpu->kvm->mmu_notifier_seq;
456 smp_rmb();
457 pfn = gfn_to_pfn(vcpu->kvm, walker.gfn);
458
459 /* mmio */
460 if (is_error_pfn(pfn))
461 return kvm_handle_bad_page(vcpu->kvm, walker.gfn, pfn);
462
463 spin_lock(&vcpu->kvm->mmu_lock);
464 if (mmu_notifier_retry(vcpu, mmu_seq))
465 goto out_unlock;
466 kvm_mmu_free_some_pages(vcpu);
467 sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
468 level, &write_pt, pfn);
469 (void)sptep;
470 pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__,
471 sptep, *sptep, write_pt);
472
473 if (!write_pt)
474 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
475
476 ++vcpu->stat.pf_fixed;
477 kvm_mmu_audit(vcpu, "post page fault (fixed)");
478 spin_unlock(&vcpu->kvm->mmu_lock);
479
480 return write_pt;
481
482 out_unlock:
483 spin_unlock(&vcpu->kvm->mmu_lock);
484 kvm_release_pfn_clean(pfn);
485 return 0;
486 }
487
488 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
489 {
490 struct kvm_shadow_walk_iterator iterator;
491 struct kvm_mmu_page *sp;
492 gpa_t pte_gpa = -1;
493 int level;
494 u64 *sptep;
495 int need_flush = 0;
496
497 spin_lock(&vcpu->kvm->mmu_lock);
498
499 for_each_shadow_entry(vcpu, gva, iterator) {
500 level = iterator.level;
501 sptep = iterator.sptep;
502
503 sp = page_header(__pa(sptep));
504 if (is_last_spte(*sptep, level)) {
505 int offset, shift;
506
507 if (!sp->unsync)
508 break;
509
510 shift = PAGE_SHIFT -
511 (PT_LEVEL_BITS - PT64_LEVEL_BITS) * level;
512 offset = sp->role.quadrant << shift;
513
514 pte_gpa = (sp->gfn << PAGE_SHIFT) + offset;
515 pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
516
517 if (is_shadow_present_pte(*sptep)) {
518 if (is_large_pte(*sptep))
519 --vcpu->kvm->stat.lpages;
520 drop_spte(vcpu->kvm, sptep,
521 shadow_trap_nonpresent_pte);
522 need_flush = 1;
523 } else
524 __set_spte(sptep, shadow_trap_nonpresent_pte);
525 break;
526 }
527
528 if (!is_shadow_present_pte(*sptep) || !sp->unsync_children)
529 break;
530 }
531
532 if (need_flush)
533 kvm_flush_remote_tlbs(vcpu->kvm);
534
535 atomic_inc(&vcpu->kvm->arch.invlpg_counter);
536
537 spin_unlock(&vcpu->kvm->mmu_lock);
538
539 if (pte_gpa == -1)
540 return;
541
542 if (mmu_topup_memory_caches(vcpu))
543 return;
544 kvm_mmu_pte_write(vcpu, pte_gpa, NULL, sizeof(pt_element_t), 0);
545 }
546
547 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access,
548 u32 *error)
549 {
550 struct guest_walker walker;
551 gpa_t gpa = UNMAPPED_GVA;
552 int r;
553
554 r = FNAME(walk_addr)(&walker, vcpu, vaddr,
555 !!(access & PFERR_WRITE_MASK),
556 !!(access & PFERR_USER_MASK),
557 !!(access & PFERR_FETCH_MASK));
558
559 if (r) {
560 gpa = gfn_to_gpa(walker.gfn);
561 gpa |= vaddr & ~PAGE_MASK;
562 } else if (error)
563 *error = walker.error_code;
564
565 return gpa;
566 }
567
568 static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
569 struct kvm_mmu_page *sp)
570 {
571 int i, j, offset, r;
572 pt_element_t pt[256 / sizeof(pt_element_t)];
573 gpa_t pte_gpa;
574
575 if (sp->role.direct
576 || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) {
577 nonpaging_prefetch_page(vcpu, sp);
578 return;
579 }
580
581 pte_gpa = gfn_to_gpa(sp->gfn);
582 if (PTTYPE == 32) {
583 offset = sp->role.quadrant << PT64_LEVEL_BITS;
584 pte_gpa += offset * sizeof(pt_element_t);
585 }
586
587 for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) {
588 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt);
589 pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t);
590 for (j = 0; j < ARRAY_SIZE(pt); ++j)
591 if (r || is_present_gpte(pt[j]))
592 sp->spt[i+j] = shadow_trap_nonpresent_pte;
593 else
594 sp->spt[i+j] = shadow_notrap_nonpresent_pte;
595 }
596 }
597
598 /*
599 * Using the cached information from sp->gfns is safe because:
600 * - The spte has a reference to the struct page, so the pfn for a given gfn
601 * can't change unless all sptes pointing to it are nuked first.
602 */
603 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
604 bool clear_unsync)
605 {
606 int i, offset, nr_present;
607 bool reset_host_protection;
608 gpa_t first_pte_gpa;
609
610 offset = nr_present = 0;
611
612 /* direct kvm_mmu_page can not be unsync. */
613 BUG_ON(sp->role.direct);
614
615 if (PTTYPE == 32)
616 offset = sp->role.quadrant << PT64_LEVEL_BITS;
617
618 first_pte_gpa = gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
619
620 for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
621 unsigned pte_access;
622 pt_element_t gpte;
623 gpa_t pte_gpa;
624 gfn_t gfn;
625
626 if (!is_shadow_present_pte(sp->spt[i]))
627 continue;
628
629 pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
630
631 if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
632 sizeof(pt_element_t)))
633 return -EINVAL;
634
635 gfn = gpte_to_gfn(gpte);
636 if (gfn != sp->gfns[i] ||
637 !is_present_gpte(gpte) || !(gpte & PT_ACCESSED_MASK)) {
638 u64 nonpresent;
639
640 if (is_present_gpte(gpte) || !clear_unsync)
641 nonpresent = shadow_trap_nonpresent_pte;
642 else
643 nonpresent = shadow_notrap_nonpresent_pte;
644 drop_spte(vcpu->kvm, &sp->spt[i], nonpresent);
645 continue;
646 }
647
648 nr_present++;
649 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
650 if (!(sp->spt[i] & SPTE_HOST_WRITEABLE)) {
651 pte_access &= ~ACC_WRITE_MASK;
652 reset_host_protection = 0;
653 } else {
654 reset_host_protection = 1;
655 }
656 set_spte(vcpu, &sp->spt[i], pte_access, 0, 0,
657 is_dirty_gpte(gpte), PT_PAGE_TABLE_LEVEL, gfn,
658 spte_to_pfn(sp->spt[i]), true, false,
659 reset_host_protection);
660 }
661
662 return !nr_present;
663 }
664
665 #undef pt_element_t
666 #undef guest_walker
667 #undef FNAME
668 #undef PT_BASE_ADDR_MASK
669 #undef PT_INDEX
670 #undef PT_LEVEL_MASK
671 #undef PT_LVL_ADDR_MASK
672 #undef PT_LVL_OFFSET_MASK
673 #undef PT_LEVEL_BITS
674 #undef PT_MAX_FULL_LEVELS
675 #undef gpte_to_gfn
676 #undef gpte_to_gfn_lvl
677 #undef CMPXCHG
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