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drm: radeon: Fix ring_rptr accesses.
[linux-2.6/btrfs-unstable.git] / drivers / gpu / drm / radeon / radeon_cp.c
blob8a8a82a2c170cf2246bd2a498079d9e4cb130fbd
1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
2 /*
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2007 Advanced Micro Devices, Inc.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Kevin E. Martin <martin@valinux.com>
29 * Gareth Hughes <gareth@valinux.com>
30 */
31
32 #include "drmP.h"
33 #include "drm.h"
34 #include "drm_sarea.h"
35 #include "radeon_drm.h"
36 #include "radeon_drv.h"
37 #include "r300_reg.h"
38
39 #include "radeon_microcode.h"
40
41 #define RADEON_FIFO_DEBUG 0
42
43 static int radeon_do_cleanup_cp(struct drm_device * dev);
44 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
45
46 static u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off)
47 {
48 u32 val;
49
50 if (dev_priv->flags & RADEON_IS_AGP) {
51 val = DRM_READ32(dev_priv->ring_rptr, off);
52 } else {
53 val = *(((volatile u32 *)
54 dev_priv->ring_rptr->handle) +
55 (off / sizeof(u32)));
56 val = le32_to_cpu(val);
57 }
58 return val;
59 }
60
61 u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv)
62 {
63 if (dev_priv->writeback_works)
64 return radeon_read_ring_rptr(dev_priv, 0);
65 else
66 return RADEON_READ(RADEON_CP_RB_RPTR);
67 }
68
69 static void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val)
70 {
71 if (dev_priv->flags & RADEON_IS_AGP)
72 DRM_WRITE32(dev_priv->ring_rptr, off, val);
73 else
74 *(((volatile u32 *) dev_priv->ring_rptr->handle) +
75 (off / sizeof(u32))) = cpu_to_le32(val);
76 }
77
78 void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val)
79 {
80 radeon_write_ring_rptr(dev_priv, 0, val);
81 }
82
83 u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index)
84 {
85 if (dev_priv->writeback_works)
86 return radeon_read_ring_rptr(dev_priv,
87 RADEON_SCRATCHOFF(index));
88 else
89 return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index);
90 }
91
92 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
93 {
94 u32 ret;
95 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
96 ret = RADEON_READ(R520_MC_IND_DATA);
97 RADEON_WRITE(R520_MC_IND_INDEX, 0);
98 return ret;
99 }
100
101 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
102 {
103 u32 ret;
104 RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
105 ret = RADEON_READ(RS480_NB_MC_DATA);
106 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
107 return ret;
108 }
109
110 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
111 {
112 u32 ret;
113 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
114 ret = RADEON_READ(RS690_MC_DATA);
115 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
116 return ret;
117 }
118
119 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
120 {
121 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
122 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
123 return RS690_READ_MCIND(dev_priv, addr);
124 else
125 return RS480_READ_MCIND(dev_priv, addr);
126 }
127
128 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
129 {
130
131 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
132 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
133 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
134 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
135 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
136 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
137 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
138 else
139 return RADEON_READ(RADEON_MC_FB_LOCATION);
140 }
141
142 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
143 {
144 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
145 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
146 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
147 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
148 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
149 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
150 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
151 else
152 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
153 }
154
155 static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
156 {
157 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
158 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
159 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
160 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
161 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
162 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
163 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
164 else
165 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
166 }
167
168 static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
169 {
170 u32 agp_base_hi = upper_32_bits(agp_base);
171 u32 agp_base_lo = agp_base & 0xffffffff;
172
173 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
174 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
175 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
176 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
177 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
178 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
179 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
180 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
181 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
182 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
183 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
184 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
185 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
186 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
187 } else {
188 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
189 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
190 RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
191 }
192 }
193
194 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
195 {
196 drm_radeon_private_t *dev_priv = dev->dev_private;
197
198 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
199 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
200 }
201
202 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
203 {
204 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
205 return RADEON_READ(RADEON_PCIE_DATA);
206 }
207
208 #if RADEON_FIFO_DEBUG
209 static void radeon_status(drm_radeon_private_t * dev_priv)
210 {
211 printk("%s:\n", __func__);
212 printk("RBBM_STATUS = 0x%08x\n",
213 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
214 printk("CP_RB_RTPR = 0x%08x\n",
215 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
216 printk("CP_RB_WTPR = 0x%08x\n",
217 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
218 printk("AIC_CNTL = 0x%08x\n",
219 (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
220 printk("AIC_STAT = 0x%08x\n",
221 (unsigned int)RADEON_READ(RADEON_AIC_STAT));
222 printk("AIC_PT_BASE = 0x%08x\n",
223 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
224 printk("TLB_ADDR = 0x%08x\n",
225 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
226 printk("TLB_DATA = 0x%08x\n",
227 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
228 }
229 #endif
230
231 /* ================================================================
232 * Engine, FIFO control
233 */
234
235 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
236 {
237 u32 tmp;
238 int i;
239
240 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
241
242 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
243 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
244 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
245 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
246
247 for (i = 0; i < dev_priv->usec_timeout; i++) {
248 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
249 & RADEON_RB3D_DC_BUSY)) {
250 return 0;
251 }
252 DRM_UDELAY(1);
253 }
254 } else {
255 /* don't flush or purge cache here or lockup */
256 return 0;
257 }
258
259 #if RADEON_FIFO_DEBUG
260 DRM_ERROR("failed!\n");
261 radeon_status(dev_priv);
262 #endif
263 return -EBUSY;
264 }
265
266 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
267 {
268 int i;
269
270 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
271
272 for (i = 0; i < dev_priv->usec_timeout; i++) {
273 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
274 & RADEON_RBBM_FIFOCNT_MASK);
275 if (slots >= entries)
276 return 0;
277 DRM_UDELAY(1);
278 }
279 DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
280 RADEON_READ(RADEON_RBBM_STATUS),
281 RADEON_READ(R300_VAP_CNTL_STATUS));
282
283 #if RADEON_FIFO_DEBUG
284 DRM_ERROR("failed!\n");
285 radeon_status(dev_priv);
286 #endif
287 return -EBUSY;
288 }
289
290 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
291 {
292 int i, ret;
293
294 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
295
296 ret = radeon_do_wait_for_fifo(dev_priv, 64);
297 if (ret)
298 return ret;
299
300 for (i = 0; i < dev_priv->usec_timeout; i++) {
301 if (!(RADEON_READ(RADEON_RBBM_STATUS)
302 & RADEON_RBBM_ACTIVE)) {
303 radeon_do_pixcache_flush(dev_priv);
304 return 0;
305 }
306 DRM_UDELAY(1);
307 }
308 DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
309 RADEON_READ(RADEON_RBBM_STATUS),
310 RADEON_READ(R300_VAP_CNTL_STATUS));
311
312 #if RADEON_FIFO_DEBUG
313 DRM_ERROR("failed!\n");
314 radeon_status(dev_priv);
315 #endif
316 return -EBUSY;
317 }
318
319 static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
320 {
321 uint32_t gb_tile_config, gb_pipe_sel = 0;
322
323 /* RS4xx/RS6xx/R4xx/R5xx */
324 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
325 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
326 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
327 } else {
328 /* R3xx */
329 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
330 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
331 dev_priv->num_gb_pipes = 2;
332 } else {
333 /* R3Vxx */
334 dev_priv->num_gb_pipes = 1;
335 }
336 }
337 DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
338
339 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
340
341 switch (dev_priv->num_gb_pipes) {
342 case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
343 case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
344 case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
345 default:
346 case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
347 }
348
349 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
350 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
351 RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
352 }
353 RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
354 radeon_do_wait_for_idle(dev_priv);
355 RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
356 RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
357 R300_DC_AUTOFLUSH_ENABLE |
358 R300_DC_DC_DISABLE_IGNORE_PE));
359
360
361 }
362
363 /* ================================================================
364 * CP control, initialization
365 */
366
367 /* Load the microcode for the CP */
368 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
369 {
370 int i;
371 DRM_DEBUG("\n");
372
373 radeon_do_wait_for_idle(dev_priv);
374
375 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
376 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
377 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
378 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
379 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
380 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
381 DRM_INFO("Loading R100 Microcode\n");
382 for (i = 0; i < 256; i++) {
383 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
384 R100_cp_microcode[i][1]);
385 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
386 R100_cp_microcode[i][0]);
387 }
388 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
389 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
390 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
391 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
392 DRM_INFO("Loading R200 Microcode\n");
393 for (i = 0; i < 256; i++) {
394 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
395 R200_cp_microcode[i][1]);
396 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
397 R200_cp_microcode[i][0]);
398 }
399 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
400 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
401 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
402 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
403 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
404 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
405 DRM_INFO("Loading R300 Microcode\n");
406 for (i = 0; i < 256; i++) {
407 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
408 R300_cp_microcode[i][1]);
409 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
410 R300_cp_microcode[i][0]);
411 }
412 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
413 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
414 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
415 DRM_INFO("Loading R400 Microcode\n");
416 for (i = 0; i < 256; i++) {
417 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
418 R420_cp_microcode[i][1]);
419 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
420 R420_cp_microcode[i][0]);
421 }
422 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
423 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
424 DRM_INFO("Loading RS690/RS740 Microcode\n");
425 for (i = 0; i < 256; i++) {
426 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
427 RS690_cp_microcode[i][1]);
428 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
429 RS690_cp_microcode[i][0]);
430 }
431 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
432 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
433 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
434 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
435 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
436 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
437 DRM_INFO("Loading R500 Microcode\n");
438 for (i = 0; i < 256; i++) {
439 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
440 R520_cp_microcode[i][1]);
441 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
442 R520_cp_microcode[i][0]);
443 }
444 }
445 }
446
447 /* Flush any pending commands to the CP. This should only be used just
448 * prior to a wait for idle, as it informs the engine that the command
449 * stream is ending.
450 */
451 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
452 {
453 DRM_DEBUG("\n");
454 #if 0
455 u32 tmp;
456
457 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
458 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
459 #endif
460 }
461
462 /* Wait for the CP to go idle.
463 */
464 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
465 {
466 RING_LOCALS;
467 DRM_DEBUG("\n");
468
469 BEGIN_RING(6);
470
471 RADEON_PURGE_CACHE();
472 RADEON_PURGE_ZCACHE();
473 RADEON_WAIT_UNTIL_IDLE();
474
475 ADVANCE_RING();
476 COMMIT_RING();
477
478 return radeon_do_wait_for_idle(dev_priv);
479 }
480
481 /* Start the Command Processor.
482 */
483 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
484 {
485 RING_LOCALS;
486 DRM_DEBUG("\n");
487
488 radeon_do_wait_for_idle(dev_priv);
489
490 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
491
492 dev_priv->cp_running = 1;
493
494 BEGIN_RING(8);
495 /* isync can only be written through cp on r5xx write it here */
496 OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
497 OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
498 RADEON_ISYNC_ANY3D_IDLE2D |
499 RADEON_ISYNC_WAIT_IDLEGUI |
500 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
501 RADEON_PURGE_CACHE();
502 RADEON_PURGE_ZCACHE();
503 RADEON_WAIT_UNTIL_IDLE();
504 ADVANCE_RING();
505 COMMIT_RING();
506
507 dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
508 }
509
510 /* Reset the Command Processor. This will not flush any pending
511 * commands, so you must wait for the CP command stream to complete
512 * before calling this routine.
513 */
514 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
515 {
516 u32 cur_read_ptr;
517 DRM_DEBUG("\n");
518
519 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
520 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
521 SET_RING_HEAD(dev_priv, cur_read_ptr);
522 dev_priv->ring.tail = cur_read_ptr;
523 }
524
525 /* Stop the Command Processor. This will not flush any pending
526 * commands, so you must flush the command stream and wait for the CP
527 * to go idle before calling this routine.
528 */
529 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
530 {
531 DRM_DEBUG("\n");
532
533 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
534
535 dev_priv->cp_running = 0;
536 }
537
538 /* Reset the engine. This will stop the CP if it is running.
539 */
540 static int radeon_do_engine_reset(struct drm_device * dev)
541 {
542 drm_radeon_private_t *dev_priv = dev->dev_private;
543 u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
544 DRM_DEBUG("\n");
545
546 radeon_do_pixcache_flush(dev_priv);
547
548 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
549 /* may need something similar for newer chips */
550 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
551 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
552
553 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
554 RADEON_FORCEON_MCLKA |
555 RADEON_FORCEON_MCLKB |
556 RADEON_FORCEON_YCLKA |
557 RADEON_FORCEON_YCLKB |
558 RADEON_FORCEON_MC |
559 RADEON_FORCEON_AIC));
560 }
561
562 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
563
564 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
565 RADEON_SOFT_RESET_CP |
566 RADEON_SOFT_RESET_HI |
567 RADEON_SOFT_RESET_SE |
568 RADEON_SOFT_RESET_RE |
569 RADEON_SOFT_RESET_PP |
570 RADEON_SOFT_RESET_E2 |
571 RADEON_SOFT_RESET_RB));
572 RADEON_READ(RADEON_RBBM_SOFT_RESET);
573 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
574 ~(RADEON_SOFT_RESET_CP |
575 RADEON_SOFT_RESET_HI |
576 RADEON_SOFT_RESET_SE |
577 RADEON_SOFT_RESET_RE |
578 RADEON_SOFT_RESET_PP |
579 RADEON_SOFT_RESET_E2 |
580 RADEON_SOFT_RESET_RB)));
581 RADEON_READ(RADEON_RBBM_SOFT_RESET);
582
583 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
584 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
585 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
586 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
587 }
588
589 /* setup the raster pipes */
590 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
591 radeon_init_pipes(dev_priv);
592
593 /* Reset the CP ring */
594 radeon_do_cp_reset(dev_priv);
595
596 /* The CP is no longer running after an engine reset */
597 dev_priv->cp_running = 0;
598
599 /* Reset any pending vertex, indirect buffers */
600 radeon_freelist_reset(dev);
601
602 return 0;
603 }
604
605 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
606 drm_radeon_private_t *dev_priv,
607 struct drm_file *file_priv)
608 {
609 struct drm_radeon_master_private *master_priv;
610 u32 ring_start, cur_read_ptr;
611 u32 tmp;
612
613 /* Initialize the memory controller. With new memory map, the fb location
614 * is not changed, it should have been properly initialized already. Part
615 * of the problem is that the code below is bogus, assuming the GART is
616 * always appended to the fb which is not necessarily the case
617 */
618 if (!dev_priv->new_memmap)
619 radeon_write_fb_location(dev_priv,
620 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
621 | (dev_priv->fb_location >> 16));
622
623 #if __OS_HAS_AGP
624 if (dev_priv->flags & RADEON_IS_AGP) {
625 radeon_write_agp_base(dev_priv, dev->agp->base);
626
627 radeon_write_agp_location(dev_priv,
628 (((dev_priv->gart_vm_start - 1 +
629 dev_priv->gart_size) & 0xffff0000) |
630 (dev_priv->gart_vm_start >> 16)));
631
632 ring_start = (dev_priv->cp_ring->offset
633 - dev->agp->base
634 + dev_priv->gart_vm_start);
635 } else
636 #endif
637 ring_start = (dev_priv->cp_ring->offset
638 - (unsigned long)dev->sg->virtual
639 + dev_priv->gart_vm_start);
640
641 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
642
643 /* Set the write pointer delay */
644 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
645
646 /* Initialize the ring buffer's read and write pointers */
647 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
648 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
649 SET_RING_HEAD(dev_priv, cur_read_ptr);
650 dev_priv->ring.tail = cur_read_ptr;
651
652 #if __OS_HAS_AGP
653 if (dev_priv->flags & RADEON_IS_AGP) {
654 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
655 dev_priv->ring_rptr->offset
656 - dev->agp->base + dev_priv->gart_vm_start);
657 } else
658 #endif
659 {
660 struct drm_sg_mem *entry = dev->sg;
661 unsigned long tmp_ofs, page_ofs;
662
663 tmp_ofs = dev_priv->ring_rptr->offset -
664 (unsigned long)dev->sg->virtual;
665 page_ofs = tmp_ofs >> PAGE_SHIFT;
666
667 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
668 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
669 (unsigned long)entry->busaddr[page_ofs],
670 entry->handle + tmp_ofs);
671 }
672
673 /* Set ring buffer size */
674 #ifdef __BIG_ENDIAN
675 RADEON_WRITE(RADEON_CP_RB_CNTL,
676 RADEON_BUF_SWAP_32BIT |
677 (dev_priv->ring.fetch_size_l2ow << 18) |
678 (dev_priv->ring.rptr_update_l2qw << 8) |
679 dev_priv->ring.size_l2qw);
680 #else
681 RADEON_WRITE(RADEON_CP_RB_CNTL,
682 (dev_priv->ring.fetch_size_l2ow << 18) |
683 (dev_priv->ring.rptr_update_l2qw << 8) |
684 dev_priv->ring.size_l2qw);
685 #endif
686
687
688 /* Initialize the scratch register pointer. This will cause
689 * the scratch register values to be written out to memory
690 * whenever they are updated.
691 *
692 * We simply put this behind the ring read pointer, this works
693 * with PCI GART as well as (whatever kind of) AGP GART
694 */
695 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
696 + RADEON_SCRATCH_REG_OFFSET);
697
698 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
699
700 /* Turn on bus mastering */
701 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
702 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
703 /* rs600/rs690/rs740 */
704 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
705 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
706 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
707 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
708 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
709 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
710 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
711 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
712 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
713 } /* PCIE cards appears to not need this */
714
715 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0);
716 RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
717
718 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
719 RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
720
721 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0);
722 RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
723
724 /* reset sarea copies of these */
725 master_priv = file_priv->master->driver_priv;
726 if (master_priv->sarea_priv) {
727 master_priv->sarea_priv->last_frame = 0;
728 master_priv->sarea_priv->last_dispatch = 0;
729 master_priv->sarea_priv->last_clear = 0;
730 }
731
732 radeon_do_wait_for_idle(dev_priv);
733
734 /* Sync everything up */
735 RADEON_WRITE(RADEON_ISYNC_CNTL,
736 (RADEON_ISYNC_ANY2D_IDLE3D |
737 RADEON_ISYNC_ANY3D_IDLE2D |
738 RADEON_ISYNC_WAIT_IDLEGUI |
739 RADEON_ISYNC_CPSCRATCH_IDLEGUI));
740
741 }
742
743 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
744 {
745 u32 tmp;
746
747 /* Start with assuming that writeback doesn't work */
748 dev_priv->writeback_works = 0;
749
750 /* Writeback doesn't seem to work everywhere, test it here and possibly
751 * enable it if it appears to work
752 */
753 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
754
755 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
756
757 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
758 u32 val;
759
760 val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
761 if (val == 0xdeadbeef)
762 break;
763 DRM_UDELAY(1);
764 }
765
766 if (tmp < dev_priv->usec_timeout) {
767 dev_priv->writeback_works = 1;
768 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
769 } else {
770 dev_priv->writeback_works = 0;
771 DRM_INFO("writeback test failed\n");
772 }
773 if (radeon_no_wb == 1) {
774 dev_priv->writeback_works = 0;
775 DRM_INFO("writeback forced off\n");
776 }
777
778 if (!dev_priv->writeback_works) {
779 /* Disable writeback to avoid unnecessary bus master transfer */
780 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
781 RADEON_RB_NO_UPDATE);
782 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
783 }
784 }
785
786 /* Enable or disable IGP GART on the chip */
787 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
788 {
789 u32 temp;
790
791 if (on) {
792 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
793 dev_priv->gart_vm_start,
794 (long)dev_priv->gart_info.bus_addr,
795 dev_priv->gart_size);
796
797 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
798 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
799 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
800 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
801 RS690_BLOCK_GFX_D3_EN));
802 else
803 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
804
805 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
806 RS480_VA_SIZE_32MB));
807
808 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
809 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
810 RS480_TLB_ENABLE |
811 RS480_GTW_LAC_EN |
812 RS480_1LEVEL_GART));
813
814 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
815 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
816 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
817
818 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
819 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
820 RS480_REQ_TYPE_SNOOP_DIS));
821
822 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
823
824 dev_priv->gart_size = 32*1024*1024;
825 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
826 0xffff0000) | (dev_priv->gart_vm_start >> 16));
827
828 radeon_write_agp_location(dev_priv, temp);
829
830 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
831 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
832 RS480_VA_SIZE_32MB));
833
834 do {
835 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
836 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
837 break;
838 DRM_UDELAY(1);
839 } while (1);
840
841 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
842 RS480_GART_CACHE_INVALIDATE);
843
844 do {
845 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
846 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
847 break;
848 DRM_UDELAY(1);
849 } while (1);
850
851 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
852 } else {
853 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
854 }
855 }
856
857 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
858 {
859 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
860 if (on) {
861
862 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
863 dev_priv->gart_vm_start,
864 (long)dev_priv->gart_info.bus_addr,
865 dev_priv->gart_size);
866 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
867 dev_priv->gart_vm_start);
868 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
869 dev_priv->gart_info.bus_addr);
870 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
871 dev_priv->gart_vm_start);
872 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
873 dev_priv->gart_vm_start +
874 dev_priv->gart_size - 1);
875
876 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
877
878 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
879 RADEON_PCIE_TX_GART_EN);
880 } else {
881 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
882 tmp & ~RADEON_PCIE_TX_GART_EN);
883 }
884 }
885
886 /* Enable or disable PCI GART on the chip */
887 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
888 {
889 u32 tmp;
890
891 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
892 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
893 (dev_priv->flags & RADEON_IS_IGPGART)) {
894 radeon_set_igpgart(dev_priv, on);
895 return;
896 }
897
898 if (dev_priv->flags & RADEON_IS_PCIE) {
899 radeon_set_pciegart(dev_priv, on);
900 return;
901 }
902
903 tmp = RADEON_READ(RADEON_AIC_CNTL);
904
905 if (on) {
906 RADEON_WRITE(RADEON_AIC_CNTL,
907 tmp | RADEON_PCIGART_TRANSLATE_EN);
908
909 /* set PCI GART page-table base address
910 */
911 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
912
913 /* set address range for PCI address translate
914 */
915 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
916 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
917 + dev_priv->gart_size - 1);
918
919 /* Turn off AGP aperture -- is this required for PCI GART?
920 */
921 radeon_write_agp_location(dev_priv, 0xffffffc0);
922 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
923 } else {
924 RADEON_WRITE(RADEON_AIC_CNTL,
925 tmp & ~RADEON_PCIGART_TRANSLATE_EN);
926 }
927 }
928
929 static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
930 struct drm_file *file_priv)
931 {
932 drm_radeon_private_t *dev_priv = dev->dev_private;
933 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
934
935 DRM_DEBUG("\n");
936
937 /* if we require new memory map but we don't have it fail */
938 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
939 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
940 radeon_do_cleanup_cp(dev);
941 return -EINVAL;
942 }
943
944 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
945 DRM_DEBUG("Forcing AGP card to PCI mode\n");
946 dev_priv->flags &= ~RADEON_IS_AGP;
947 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
948 && !init->is_pci) {
949 DRM_DEBUG("Restoring AGP flag\n");
950 dev_priv->flags |= RADEON_IS_AGP;
951 }
952
953 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
954 DRM_ERROR("PCI GART memory not allocated!\n");
955 radeon_do_cleanup_cp(dev);
956 return -EINVAL;
957 }
958
959 dev_priv->usec_timeout = init->usec_timeout;
960 if (dev_priv->usec_timeout < 1 ||
961 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
962 DRM_DEBUG("TIMEOUT problem!\n");
963 radeon_do_cleanup_cp(dev);
964 return -EINVAL;
965 }
966
967 /* Enable vblank on CRTC1 for older X servers
968 */
969 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
970
971 switch(init->func) {
972 case RADEON_INIT_R200_CP:
973 dev_priv->microcode_version = UCODE_R200;
974 break;
975 case RADEON_INIT_R300_CP:
976 dev_priv->microcode_version = UCODE_R300;
977 break;
978 default:
979 dev_priv->microcode_version = UCODE_R100;
980 }
981
982 dev_priv->do_boxes = 0;
983 dev_priv->cp_mode = init->cp_mode;
984
985 /* We don't support anything other than bus-mastering ring mode,
986 * but the ring can be in either AGP or PCI space for the ring
987 * read pointer.
988 */
989 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
990 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
991 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
992 radeon_do_cleanup_cp(dev);
993 return -EINVAL;
994 }
995
996 switch (init->fb_bpp) {
997 case 16:
998 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
999 break;
1000 case 32:
1001 default:
1002 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1003 break;
1004 }
1005 dev_priv->front_offset = init->front_offset;
1006 dev_priv->front_pitch = init->front_pitch;
1007 dev_priv->back_offset = init->back_offset;
1008 dev_priv->back_pitch = init->back_pitch;
1009
1010 switch (init->depth_bpp) {
1011 case 16:
1012 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1013 break;
1014 case 32:
1015 default:
1016 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1017 break;
1018 }
1019 dev_priv->depth_offset = init->depth_offset;
1020 dev_priv->depth_pitch = init->depth_pitch;
1021
1022 /* Hardware state for depth clears. Remove this if/when we no
1023 * longer clear the depth buffer with a 3D rectangle. Hard-code
1024 * all values to prevent unwanted 3D state from slipping through
1025 * and screwing with the clear operation.
1026 */
1027 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1028 (dev_priv->color_fmt << 10) |
1029 (dev_priv->microcode_version ==
1030 UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1031
1032 dev_priv->depth_clear.rb3d_zstencilcntl =
1033 (dev_priv->depth_fmt |
1034 RADEON_Z_TEST_ALWAYS |
1035 RADEON_STENCIL_TEST_ALWAYS |
1036 RADEON_STENCIL_S_FAIL_REPLACE |
1037 RADEON_STENCIL_ZPASS_REPLACE |
1038 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1039
1040 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1041 RADEON_BFACE_SOLID |
1042 RADEON_FFACE_SOLID |
1043 RADEON_FLAT_SHADE_VTX_LAST |
1044 RADEON_DIFFUSE_SHADE_FLAT |
1045 RADEON_ALPHA_SHADE_FLAT |
1046 RADEON_SPECULAR_SHADE_FLAT |
1047 RADEON_FOG_SHADE_FLAT |
1048 RADEON_VTX_PIX_CENTER_OGL |
1049 RADEON_ROUND_MODE_TRUNC |
1050 RADEON_ROUND_PREC_8TH_PIX);
1051
1052
1053 dev_priv->ring_offset = init->ring_offset;
1054 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1055 dev_priv->buffers_offset = init->buffers_offset;
1056 dev_priv->gart_textures_offset = init->gart_textures_offset;
1057
1058 master_priv->sarea = drm_getsarea(dev);
1059 if (!master_priv->sarea) {
1060 DRM_ERROR("could not find sarea!\n");
1061 radeon_do_cleanup_cp(dev);
1062 return -EINVAL;
1063 }
1064
1065 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1066 if (!dev_priv->cp_ring) {
1067 DRM_ERROR("could not find cp ring region!\n");
1068 radeon_do_cleanup_cp(dev);
1069 return -EINVAL;
1070 }
1071 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1072 if (!dev_priv->ring_rptr) {
1073 DRM_ERROR("could not find ring read pointer!\n");
1074 radeon_do_cleanup_cp(dev);
1075 return -EINVAL;
1076 }
1077 dev->agp_buffer_token = init->buffers_offset;
1078 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1079 if (!dev->agp_buffer_map) {
1080 DRM_ERROR("could not find dma buffer region!\n");
1081 radeon_do_cleanup_cp(dev);
1082 return -EINVAL;
1083 }
1084
1085 if (init->gart_textures_offset) {
1086 dev_priv->gart_textures =
1087 drm_core_findmap(dev, init->gart_textures_offset);
1088 if (!dev_priv->gart_textures) {
1089 DRM_ERROR("could not find GART texture region!\n");
1090 radeon_do_cleanup_cp(dev);
1091 return -EINVAL;
1092 }
1093 }
1094
1095 #if __OS_HAS_AGP
1096 if (dev_priv->flags & RADEON_IS_AGP) {
1097 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1098 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1099 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
1100 if (!dev_priv->cp_ring->handle ||
1101 !dev_priv->ring_rptr->handle ||
1102 !dev->agp_buffer_map->handle) {
1103 DRM_ERROR("could not find ioremap agp regions!\n");
1104 radeon_do_cleanup_cp(dev);
1105 return -EINVAL;
1106 }
1107 } else
1108 #endif
1109 {
1110 dev_priv->cp_ring->handle =
1111 (void *)(unsigned long)dev_priv->cp_ring->offset;
1112 dev_priv->ring_rptr->handle =
1113 (void *)(unsigned long)dev_priv->ring_rptr->offset;
1114 dev->agp_buffer_map->handle =
1115 (void *)(unsigned long)dev->agp_buffer_map->offset;
1116
1117 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1118 dev_priv->cp_ring->handle);
1119 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1120 dev_priv->ring_rptr->handle);
1121 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1122 dev->agp_buffer_map->handle);
1123 }
1124
1125 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1126 dev_priv->fb_size =
1127 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1128 - dev_priv->fb_location;
1129
1130 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1131 ((dev_priv->front_offset
1132 + dev_priv->fb_location) >> 10));
1133
1134 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1135 ((dev_priv->back_offset
1136 + dev_priv->fb_location) >> 10));
1137
1138 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1139 ((dev_priv->depth_offset
1140 + dev_priv->fb_location) >> 10));
1141
1142 dev_priv->gart_size = init->gart_size;
1143
1144 /* New let's set the memory map ... */
1145 if (dev_priv->new_memmap) {
1146 u32 base = 0;
1147
1148 DRM_INFO("Setting GART location based on new memory map\n");
1149
1150 /* If using AGP, try to locate the AGP aperture at the same
1151 * location in the card and on the bus, though we have to
1152 * align it down.
1153 */
1154 #if __OS_HAS_AGP
1155 if (dev_priv->flags & RADEON_IS_AGP) {
1156 base = dev->agp->base;
1157 /* Check if valid */
1158 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1159 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1160 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1161 dev->agp->base);
1162 base = 0;
1163 }
1164 }
1165 #endif
1166 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1167 if (base == 0) {
1168 base = dev_priv->fb_location + dev_priv->fb_size;
1169 if (base < dev_priv->fb_location ||
1170 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1171 base = dev_priv->fb_location
1172 - dev_priv->gart_size;
1173 }
1174 dev_priv->gart_vm_start = base & 0xffc00000u;
1175 if (dev_priv->gart_vm_start != base)
1176 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1177 base, dev_priv->gart_vm_start);
1178 } else {
1179 DRM_INFO("Setting GART location based on old memory map\n");
1180 dev_priv->gart_vm_start = dev_priv->fb_location +
1181 RADEON_READ(RADEON_CONFIG_APER_SIZE);
1182 }
1183
1184 #if __OS_HAS_AGP
1185 if (dev_priv->flags & RADEON_IS_AGP)
1186 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1187 - dev->agp->base
1188 + dev_priv->gart_vm_start);
1189 else
1190 #endif
1191 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1192 - (unsigned long)dev->sg->virtual
1193 + dev_priv->gart_vm_start);
1194
1195 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1196 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1197 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1198 dev_priv->gart_buffers_offset);
1199
1200 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1201 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1202 + init->ring_size / sizeof(u32));
1203 dev_priv->ring.size = init->ring_size;
1204 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1205
1206 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1207 dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1208
1209 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1210 dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1211 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1212
1213 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1214
1215 #if __OS_HAS_AGP
1216 if (dev_priv->flags & RADEON_IS_AGP) {
1217 /* Turn off PCI GART */
1218 radeon_set_pcigart(dev_priv, 0);
1219 } else
1220 #endif
1221 {
1222 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1223 /* if we have an offset set from userspace */
1224 if (dev_priv->pcigart_offset_set) {
1225 dev_priv->gart_info.bus_addr =
1226 (resource_size_t)dev_priv->pcigart_offset + dev_priv->fb_location;
1227 dev_priv->gart_info.mapping.offset =
1228 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1229 dev_priv->gart_info.mapping.size =
1230 dev_priv->gart_info.table_size;
1231
1232 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1233 dev_priv->gart_info.addr =
1234 dev_priv->gart_info.mapping.handle;
1235
1236 if (dev_priv->flags & RADEON_IS_PCIE)
1237 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1238 else
1239 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1240 dev_priv->gart_info.gart_table_location =
1241 DRM_ATI_GART_FB;
1242
1243 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1244 dev_priv->gart_info.addr,
1245 dev_priv->pcigart_offset);
1246 } else {
1247 if (dev_priv->flags & RADEON_IS_IGPGART)
1248 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1249 else
1250 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1251 dev_priv->gart_info.gart_table_location =
1252 DRM_ATI_GART_MAIN;
1253 dev_priv->gart_info.addr = NULL;
1254 dev_priv->gart_info.bus_addr = 0;
1255 if (dev_priv->flags & RADEON_IS_PCIE) {
1256 DRM_ERROR
1257 ("Cannot use PCI Express without GART in FB memory\n");
1258 radeon_do_cleanup_cp(dev);
1259 return -EINVAL;
1260 }
1261 }
1262
1263 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1264 DRM_ERROR("failed to init PCI GART!\n");
1265 radeon_do_cleanup_cp(dev);
1266 return -ENOMEM;
1267 }
1268
1269 /* Turn on PCI GART */
1270 radeon_set_pcigart(dev_priv, 1);
1271 }
1272
1273 radeon_cp_load_microcode(dev_priv);
1274 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1275
1276 dev_priv->last_buf = 0;
1277
1278 radeon_do_engine_reset(dev);
1279 radeon_test_writeback(dev_priv);
1280
1281 return 0;
1282 }
1283
1284 static int radeon_do_cleanup_cp(struct drm_device * dev)
1285 {
1286 drm_radeon_private_t *dev_priv = dev->dev_private;
1287 DRM_DEBUG("\n");
1288
1289 /* Make sure interrupts are disabled here because the uninstall ioctl
1290 * may not have been called from userspace and after dev_private
1291 * is freed, it's too late.
1292 */
1293 if (dev->irq_enabled)
1294 drm_irq_uninstall(dev);
1295
1296 #if __OS_HAS_AGP
1297 if (dev_priv->flags & RADEON_IS_AGP) {
1298 if (dev_priv->cp_ring != NULL) {
1299 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1300 dev_priv->cp_ring = NULL;
1301 }
1302 if (dev_priv->ring_rptr != NULL) {
1303 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1304 dev_priv->ring_rptr = NULL;
1305 }
1306 if (dev->agp_buffer_map != NULL) {
1307 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1308 dev->agp_buffer_map = NULL;
1309 }
1310 } else
1311 #endif
1312 {
1313
1314 if (dev_priv->gart_info.bus_addr) {
1315 /* Turn off PCI GART */
1316 radeon_set_pcigart(dev_priv, 0);
1317 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1318 DRM_ERROR("failed to cleanup PCI GART!\n");
1319 }
1320
1321 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1322 {
1323 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1324 dev_priv->gart_info.addr = 0;
1325 }
1326 }
1327 /* only clear to the start of flags */
1328 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1329
1330 return 0;
1331 }
1332
1333 /* This code will reinit the Radeon CP hardware after a resume from disc.
1334 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1335 * here we make sure that all Radeon hardware initialisation is re-done without
1336 * affecting running applications.
1337 *
1338 * Charl P. Botha <http://cpbotha.net>
1339 */
1340 static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
1341 {
1342 drm_radeon_private_t *dev_priv = dev->dev_private;
1343
1344 if (!dev_priv) {
1345 DRM_ERROR("Called with no initialization\n");
1346 return -EINVAL;
1347 }
1348
1349 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1350
1351 #if __OS_HAS_AGP
1352 if (dev_priv->flags & RADEON_IS_AGP) {
1353 /* Turn off PCI GART */
1354 radeon_set_pcigart(dev_priv, 0);
1355 } else
1356 #endif
1357 {
1358 /* Turn on PCI GART */
1359 radeon_set_pcigart(dev_priv, 1);
1360 }
1361
1362 radeon_cp_load_microcode(dev_priv);
1363 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1364
1365 radeon_do_engine_reset(dev);
1366 radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1367
1368 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1369
1370 return 0;
1371 }
1372
1373 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1374 {
1375 drm_radeon_init_t *init = data;
1376
1377 LOCK_TEST_WITH_RETURN(dev, file_priv);
1378
1379 if (init->func == RADEON_INIT_R300_CP)
1380 r300_init_reg_flags(dev);
1381
1382 switch (init->func) {
1383 case RADEON_INIT_CP:
1384 case RADEON_INIT_R200_CP:
1385 case RADEON_INIT_R300_CP:
1386 return radeon_do_init_cp(dev, init, file_priv);
1387 case RADEON_CLEANUP_CP:
1388 return radeon_do_cleanup_cp(dev);
1389 }
1390
1391 return -EINVAL;
1392 }
1393
1394 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1395 {
1396 drm_radeon_private_t *dev_priv = dev->dev_private;
1397 DRM_DEBUG("\n");
1398
1399 LOCK_TEST_WITH_RETURN(dev, file_priv);
1400
1401 if (dev_priv->cp_running) {
1402 DRM_DEBUG("while CP running\n");
1403 return 0;
1404 }
1405 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1406 DRM_DEBUG("called with bogus CP mode (%d)\n",
1407 dev_priv->cp_mode);
1408 return 0;
1409 }
1410
1411 radeon_do_cp_start(dev_priv);
1412
1413 return 0;
1414 }
1415
1416 /* Stop the CP. The engine must have been idled before calling this
1417 * routine.
1418 */
1419 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1420 {
1421 drm_radeon_private_t *dev_priv = dev->dev_private;
1422 drm_radeon_cp_stop_t *stop = data;
1423 int ret;
1424 DRM_DEBUG("\n");
1425
1426 LOCK_TEST_WITH_RETURN(dev, file_priv);
1427
1428 if (!dev_priv->cp_running)
1429 return 0;
1430
1431 /* Flush any pending CP commands. This ensures any outstanding
1432 * commands are exectuted by the engine before we turn it off.
1433 */
1434 if (stop->flush) {
1435 radeon_do_cp_flush(dev_priv);
1436 }
1437
1438 /* If we fail to make the engine go idle, we return an error
1439 * code so that the DRM ioctl wrapper can try again.
1440 */
1441 if (stop->idle) {
1442 ret = radeon_do_cp_idle(dev_priv);
1443 if (ret)
1444 return ret;
1445 }
1446
1447 /* Finally, we can turn off the CP. If the engine isn't idle,
1448 * we will get some dropped triangles as they won't be fully
1449 * rendered before the CP is shut down.
1450 */
1451 radeon_do_cp_stop(dev_priv);
1452
1453 /* Reset the engine */
1454 radeon_do_engine_reset(dev);
1455
1456 return 0;
1457 }
1458
1459 void radeon_do_release(struct drm_device * dev)
1460 {
1461 drm_radeon_private_t *dev_priv = dev->dev_private;
1462 int i, ret;
1463
1464 if (dev_priv) {
1465 if (dev_priv->cp_running) {
1466 /* Stop the cp */
1467 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1468 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1469 #ifdef __linux__
1470 schedule();
1471 #else
1472 tsleep(&ret, PZERO, "rdnrel", 1);
1473 #endif
1474 }
1475 radeon_do_cp_stop(dev_priv);
1476 radeon_do_engine_reset(dev);
1477 }
1478
1479 /* Disable *all* interrupts */
1480 if (dev_priv->mmio) /* remove this after permanent addmaps */
1481 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1482
1483 if (dev_priv->mmio) { /* remove all surfaces */
1484 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1485 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1486 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1487 16 * i, 0);
1488 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1489 16 * i, 0);
1490 }
1491 }
1492
1493 /* Free memory heap structures */
1494 radeon_mem_takedown(&(dev_priv->gart_heap));
1495 radeon_mem_takedown(&(dev_priv->fb_heap));
1496
1497 /* deallocate kernel resources */
1498 radeon_do_cleanup_cp(dev);
1499 }
1500 }
1501
1502 /* Just reset the CP ring. Called as part of an X Server engine reset.
1503 */
1504 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1505 {
1506 drm_radeon_private_t *dev_priv = dev->dev_private;
1507 DRM_DEBUG("\n");
1508
1509 LOCK_TEST_WITH_RETURN(dev, file_priv);
1510
1511 if (!dev_priv) {
1512 DRM_DEBUG("called before init done\n");
1513 return -EINVAL;
1514 }
1515
1516 radeon_do_cp_reset(dev_priv);
1517
1518 /* The CP is no longer running after an engine reset */
1519 dev_priv->cp_running = 0;
1520
1521 return 0;
1522 }
1523
1524 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1525 {
1526 drm_radeon_private_t *dev_priv = dev->dev_private;
1527 DRM_DEBUG("\n");
1528
1529 LOCK_TEST_WITH_RETURN(dev, file_priv);
1530
1531 return radeon_do_cp_idle(dev_priv);
1532 }
1533
1534 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1535 */
1536 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1537 {
1538 return radeon_do_resume_cp(dev, file_priv);
1539 }
1540
1541 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1542 {
1543 DRM_DEBUG("\n");
1544
1545 LOCK_TEST_WITH_RETURN(dev, file_priv);
1546
1547 return radeon_do_engine_reset(dev);
1548 }
1549
1550 /* ================================================================
1551 * Fullscreen mode
1552 */
1553
1554 /* KW: Deprecated to say the least:
1555 */
1556 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1557 {
1558 return 0;
1559 }
1560
1561 /* ================================================================
1562 * Freelist management
1563 */
1564
1565 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1566 * bufs until freelist code is used. Note this hides a problem with
1567 * the scratch register * (used to keep track of last buffer
1568 * completed) being written to before * the last buffer has actually
1569 * completed rendering.
1570 *
1571 * KW: It's also a good way to find free buffers quickly.
1572 *
1573 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1574 * sleep. However, bugs in older versions of radeon_accel.c mean that
1575 * we essentially have to do this, else old clients will break.
1576 *
1577 * However, it does leave open a potential deadlock where all the
1578 * buffers are held by other clients, which can't release them because
1579 * they can't get the lock.
1580 */
1581
1582 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1583 {
1584 struct drm_device_dma *dma = dev->dma;
1585 drm_radeon_private_t *dev_priv = dev->dev_private;
1586 drm_radeon_buf_priv_t *buf_priv;
1587 struct drm_buf *buf;
1588 int i, t;
1589 int start;
1590
1591 if (++dev_priv->last_buf >= dma->buf_count)
1592 dev_priv->last_buf = 0;
1593
1594 start = dev_priv->last_buf;
1595
1596 for (t = 0; t < dev_priv->usec_timeout; t++) {
1597 u32 done_age = GET_SCRATCH(dev_priv, 1);
1598 DRM_DEBUG("done_age = %d\n", done_age);
1599 for (i = start; i < dma->buf_count; i++) {
1600 buf = dma->buflist[i];
1601 buf_priv = buf->dev_private;
1602 if (buf->file_priv == NULL || (buf->pending &&
1603 buf_priv->age <=
1604 done_age)) {
1605 dev_priv->stats.requested_bufs++;
1606 buf->pending = 0;
1607 return buf;
1608 }
1609 start = 0;
1610 }
1611
1612 if (t) {
1613 DRM_UDELAY(1);
1614 dev_priv->stats.freelist_loops++;
1615 }
1616 }
1617
1618 DRM_DEBUG("returning NULL!\n");
1619 return NULL;
1620 }
1621
1622 #if 0
1623 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1624 {
1625 struct drm_device_dma *dma = dev->dma;
1626 drm_radeon_private_t *dev_priv = dev->dev_private;
1627 drm_radeon_buf_priv_t *buf_priv;
1628 struct drm_buf *buf;
1629 int i, t;
1630 int start;
1631 u32 done_age;
1632
1633 done_age = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
1634 if (++dev_priv->last_buf >= dma->buf_count)
1635 dev_priv->last_buf = 0;
1636
1637 start = dev_priv->last_buf;
1638 dev_priv->stats.freelist_loops++;
1639
1640 for (t = 0; t < 2; t++) {
1641 for (i = start; i < dma->buf_count; i++) {
1642 buf = dma->buflist[i];
1643 buf_priv = buf->dev_private;
1644 if (buf->file_priv == 0 || (buf->pending &&
1645 buf_priv->age <=
1646 done_age)) {
1647 dev_priv->stats.requested_bufs++;
1648 buf->pending = 0;
1649 return buf;
1650 }
1651 }
1652 start = 0;
1653 }
1654
1655 return NULL;
1656 }
1657 #endif
1658
1659 void radeon_freelist_reset(struct drm_device * dev)
1660 {
1661 struct drm_device_dma *dma = dev->dma;
1662 drm_radeon_private_t *dev_priv = dev->dev_private;
1663 int i;
1664
1665 dev_priv->last_buf = 0;
1666 for (i = 0; i < dma->buf_count; i++) {
1667 struct drm_buf *buf = dma->buflist[i];
1668 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1669 buf_priv->age = 0;
1670 }
1671 }
1672
1673 /* ================================================================
1674 * CP command submission
1675 */
1676
1677 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1678 {
1679 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1680 int i;
1681 u32 last_head = GET_RING_HEAD(dev_priv);
1682
1683 for (i = 0; i < dev_priv->usec_timeout; i++) {
1684 u32 head = GET_RING_HEAD(dev_priv);
1685
1686 ring->space = (head - ring->tail) * sizeof(u32);
1687 if (ring->space <= 0)
1688 ring->space += ring->size;
1689 if (ring->space > n)
1690 return 0;
1691
1692 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1693
1694 if (head != last_head)
1695 i = 0;
1696 last_head = head;
1697
1698 DRM_UDELAY(1);
1699 }
1700
1701 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1702 #if RADEON_FIFO_DEBUG
1703 radeon_status(dev_priv);
1704 DRM_ERROR("failed!\n");
1705 #endif
1706 return -EBUSY;
1707 }
1708
1709 static int radeon_cp_get_buffers(struct drm_device *dev,
1710 struct drm_file *file_priv,
1711 struct drm_dma * d)
1712 {
1713 int i;
1714 struct drm_buf *buf;
1715
1716 for (i = d->granted_count; i < d->request_count; i++) {
1717 buf = radeon_freelist_get(dev);
1718 if (!buf)
1719 return -EBUSY; /* NOTE: broken client */
1720
1721 buf->file_priv = file_priv;
1722
1723 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1724 sizeof(buf->idx)))
1725 return -EFAULT;
1726 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1727 sizeof(buf->total)))
1728 return -EFAULT;
1729
1730 d->granted_count++;
1731 }
1732 return 0;
1733 }
1734
1735 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1736 {
1737 struct drm_device_dma *dma = dev->dma;
1738 int ret = 0;
1739 struct drm_dma *d = data;
1740
1741 LOCK_TEST_WITH_RETURN(dev, file_priv);
1742
1743 /* Please don't send us buffers.
1744 */
1745 if (d->send_count != 0) {
1746 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1747 DRM_CURRENTPID, d->send_count);
1748 return -EINVAL;
1749 }
1750
1751 /* We'll send you buffers.
1752 */
1753 if (d->request_count < 0 || d->request_count > dma->buf_count) {
1754 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1755 DRM_CURRENTPID, d->request_count, dma->buf_count);
1756 return -EINVAL;
1757 }
1758
1759 d->granted_count = 0;
1760
1761 if (d->request_count) {
1762 ret = radeon_cp_get_buffers(dev, file_priv, d);
1763 }
1764
1765 return ret;
1766 }
1767
1768 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
1769 {
1770 drm_radeon_private_t *dev_priv;
1771 int ret = 0;
1772
1773 dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
1774 if (dev_priv == NULL)
1775 return -ENOMEM;
1776
1777 memset(dev_priv, 0, sizeof(drm_radeon_private_t));
1778 dev->dev_private = (void *)dev_priv;
1779 dev_priv->flags = flags;
1780
1781 switch (flags & RADEON_FAMILY_MASK) {
1782 case CHIP_R100:
1783 case CHIP_RV200:
1784 case CHIP_R200:
1785 case CHIP_R300:
1786 case CHIP_R350:
1787 case CHIP_R420:
1788 case CHIP_R423:
1789 case CHIP_RV410:
1790 case CHIP_RV515:
1791 case CHIP_R520:
1792 case CHIP_RV570:
1793 case CHIP_R580:
1794 dev_priv->flags |= RADEON_HAS_HIERZ;
1795 break;
1796 default:
1797 /* all other chips have no hierarchical z buffer */
1798 break;
1799 }
1800
1801 if (drm_device_is_agp(dev))
1802 dev_priv->flags |= RADEON_IS_AGP;
1803 else if (drm_device_is_pcie(dev))
1804 dev_priv->flags |= RADEON_IS_PCIE;
1805 else
1806 dev_priv->flags |= RADEON_IS_PCI;
1807
1808 ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
1809 drm_get_resource_len(dev, 2), _DRM_REGISTERS,
1810 _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
1811 if (ret != 0)
1812 return ret;
1813
1814 ret = drm_vblank_init(dev, 2);
1815 if (ret) {
1816 radeon_driver_unload(dev);
1817 return ret;
1818 }
1819
1820 DRM_DEBUG("%s card detected\n",
1821 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
1822 return ret;
1823 }
1824
1825 int radeon_master_create(struct drm_device *dev, struct drm_master *master)
1826 {
1827 struct drm_radeon_master_private *master_priv;
1828 unsigned long sareapage;
1829 int ret;
1830
1831 master_priv = drm_calloc(1, sizeof(*master_priv), DRM_MEM_DRIVER);
1832 if (!master_priv)
1833 return -ENOMEM;
1834
1835 /* prebuild the SAREA */
1836 sareapage = max_t(unsigned long, SAREA_MAX, PAGE_SIZE);
1837 ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK|_DRM_DRIVER,
1838 &master_priv->sarea);
1839 if (ret) {
1840 DRM_ERROR("SAREA setup failed\n");
1841 return ret;
1842 }
1843 master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea);
1844 master_priv->sarea_priv->pfCurrentPage = 0;
1845
1846 master->driver_priv = master_priv;
1847 return 0;
1848 }
1849
1850 void radeon_master_destroy(struct drm_device *dev, struct drm_master *master)
1851 {
1852 struct drm_radeon_master_private *master_priv = master->driver_priv;
1853
1854 if (!master_priv)
1855 return;
1856
1857 if (master_priv->sarea_priv &&
1858 master_priv->sarea_priv->pfCurrentPage != 0)
1859 radeon_cp_dispatch_flip(dev, master);
1860
1861 master_priv->sarea_priv = NULL;
1862 if (master_priv->sarea)
1863 drm_rmmap_locked(dev, master_priv->sarea);
1864
1865 drm_free(master_priv, sizeof(*master_priv), DRM_MEM_DRIVER);
1866
1867 master->driver_priv = NULL;
1868 }
1869
1870 /* Create mappings for registers and framebuffer so userland doesn't necessarily
1871 * have to find them.
1872 */
1873 int radeon_driver_firstopen(struct drm_device *dev)
1874 {
1875 int ret;
1876 drm_local_map_t *map;
1877 drm_radeon_private_t *dev_priv = dev->dev_private;
1878
1879 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
1880
1881 dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
1882 ret = drm_addmap(dev, dev_priv->fb_aper_offset,
1883 drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
1884 _DRM_WRITE_COMBINING, &map);
1885 if (ret != 0)
1886 return ret;
1887
1888 return 0;
1889 }
1890
1891 int radeon_driver_unload(struct drm_device *dev)
1892 {
1893 drm_radeon_private_t *dev_priv = dev->dev_private;
1894
1895 DRM_DEBUG("\n");
1896
1897 drm_rmmap(dev, dev_priv->mmio);
1898
1899 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
1900
1901 dev->dev_private = NULL;
1902 return 0;
1903 }
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