1 /* linux/arch/arm/mach-s5p64x0/clock-s5p6450.c
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * S5P6450 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20 #include <linux/sysdev.h>
23 #include <mach/hardware.h>
25 #include <mach/regs-clock.h>
26 #include <mach/s5p64x0-clock.h>
28 #include <plat/cpu-freq.h>
29 #include <plat/clock.h>
32 #include <plat/s5p-clock.h>
33 #include <plat/clock-clksrc.h>
34 #include <plat/s5p6450.h>
36 static struct clksrc_clk clk_mout_dpll
= {
41 .sources
= &clk_src_dpll
,
42 .reg_src
= { .reg
= S5P64X0_CLK_SRC0
, .shift
= 5, .size
= 1 },
45 static u32 epll_div
[][5] = {
46 { 133000000, 27307, 55, 2, 2 },
47 { 100000000, 43691, 41, 2, 2 },
48 { 480000000, 0, 80, 2, 0 },
51 static int s5p6450_epll_set_rate(struct clk
*clk
, unsigned long rate
)
53 unsigned int epll_con
, epll_con_k
;
56 if (clk
->rate
== rate
) /* Return if nothing changed */
59 epll_con
= __raw_readl(S5P64X0_EPLL_CON
);
60 epll_con_k
= __raw_readl(S5P64X0_EPLL_CON_K
);
62 epll_con_k
&= ~(PLL90XX_KDIV_MASK
);
63 epll_con
&= ~(PLL90XX_MDIV_MASK
| PLL90XX_PDIV_MASK
| PLL90XX_SDIV_MASK
);
65 for (i
= 0; i
< ARRAY_SIZE(epll_div
); i
++) {
66 if (epll_div
[i
][0] == rate
) {
67 epll_con_k
|= (epll_div
[i
][1] << PLL90XX_KDIV_SHIFT
);
68 epll_con
|= (epll_div
[i
][2] << PLL90XX_MDIV_SHIFT
) |
69 (epll_div
[i
][3] << PLL90XX_PDIV_SHIFT
) |
70 (epll_div
[i
][4] << PLL90XX_SDIV_SHIFT
);
75 if (i
== ARRAY_SIZE(epll_div
)) {
76 printk(KERN_ERR
"%s: Invalid Clock EPLL Frequency\n", __func__
);
80 __raw_writel(epll_con
, S5P64X0_EPLL_CON
);
81 __raw_writel(epll_con_k
, S5P64X0_EPLL_CON_K
);
83 printk(KERN_WARNING
"EPLL Rate changes from %lu to %lu\n",
91 static struct clk_ops s5p6450_epll_ops
= {
92 .get_rate
= s5p_epll_get_rate
,
93 .set_rate
= s5p6450_epll_set_rate
,
96 static struct clksrc_clk clk_dout_epll
= {
100 .parent
= &clk_mout_epll
.clk
,
102 .reg_div
= { .reg
= S5P64X0_CLK_DIV1
, .shift
= 24, .size
= 4 },
105 static struct clksrc_clk clk_mout_hclk_sel
= {
107 .name
= "mout_hclk_sel",
110 .sources
= &clkset_hclk_low
,
111 .reg_src
= { .reg
= S5P64X0_OTHERS
, .shift
= 15, .size
= 1 },
114 static struct clk
*clkset_hclk_list
[] = {
115 &clk_mout_hclk_sel
.clk
,
119 static struct clksrc_sources clkset_hclk
= {
120 .sources
= clkset_hclk_list
,
121 .nr_sources
= ARRAY_SIZE(clkset_hclk_list
),
124 static struct clksrc_clk clk_hclk
= {
129 .sources
= &clkset_hclk
,
130 .reg_src
= { .reg
= S5P64X0_OTHERS
, .shift
= 14, .size
= 1 },
131 .reg_div
= { .reg
= S5P64X0_CLK_DIV0
, .shift
= 8, .size
= 4 },
134 static struct clksrc_clk clk_pclk
= {
138 .parent
= &clk_hclk
.clk
,
140 .reg_div
= { .reg
= S5P64X0_CLK_DIV0
, .shift
= 12, .size
= 4 },
142 static struct clksrc_clk clk_dout_pwm_ratio0
= {
144 .name
= "clk_dout_pwm_ratio0",
146 .parent
= &clk_mout_hclk_sel
.clk
,
148 .reg_div
= { .reg
= S5P64X0_CLK_DIV3
, .shift
= 16, .size
= 4 },
151 static struct clksrc_clk clk_pclk_to_wdt_pwm
= {
153 .name
= "clk_pclk_to_wdt_pwm",
155 .parent
= &clk_dout_pwm_ratio0
.clk
,
157 .reg_div
= { .reg
= S5P64X0_CLK_DIV3
, .shift
= 20, .size
= 4 },
160 static struct clksrc_clk clk_hclk_low
= {
162 .name
= "clk_hclk_low",
165 .sources
= &clkset_hclk_low
,
166 .reg_src
= { .reg
= S5P64X0_OTHERS
, .shift
= 6, .size
= 1 },
167 .reg_div
= { .reg
= S5P64X0_CLK_DIV3
, .shift
= 8, .size
= 4 },
170 static struct clksrc_clk clk_pclk_low
= {
172 .name
= "clk_pclk_low",
174 .parent
= &clk_hclk_low
.clk
,
176 .reg_div
= { .reg
= S5P64X0_CLK_DIV3
, .shift
= 12, .size
= 4 },
180 * The following clocks will be disabled during clock initialization. It is
181 * recommended to keep the following clocks disabled until the driver requests
182 * for enabling the clock.
184 static struct clk init_clocks_disable
[] = {
188 .parent
= &clk_hclk_low
.clk
,
189 .enable
= s5p64x0_hclk0_ctrl
,
194 .parent
= &clk_hclk_low
.clk
,
195 .enable
= s5p64x0_hclk0_ctrl
,
196 .ctrlbit
= (1 << 12),
200 .parent
= &clk_hclk_low
.clk
,
201 .enable
= s5p64x0_hclk0_ctrl
,
202 .ctrlbit
= (1 << 17),
206 .parent
= &clk_hclk_low
.clk
,
207 .enable
= s5p64x0_hclk0_ctrl
,
208 .ctrlbit
= (1 << 18),
212 .parent
= &clk_hclk_low
.clk
,
213 .enable
= s5p64x0_hclk0_ctrl
,
214 .ctrlbit
= (1 << 19),
218 .parent
= &clk_hclk_low
.clk
,
219 .enable
= s5p64x0_hclk0_ctrl
,
220 .ctrlbit
= (1 << 20),
225 .enable
= s5p64x0_hclk1_ctrl
,
230 .parent
= &clk_pclk_low
.clk
,
231 .enable
= s5p64x0_pclk_ctrl
,
236 .parent
= &clk_pclk_low
.clk
,
237 .enable
= s5p64x0_pclk_ctrl
,
238 .ctrlbit
= (1 << 12),
242 .parent
= &clk_pclk_low
.clk
,
243 .enable
= s5p64x0_pclk_ctrl
,
244 .ctrlbit
= (1 << 17),
248 .parent
= &clk_pclk_low
.clk
,
249 .enable
= s5p64x0_pclk_ctrl
,
250 .ctrlbit
= (1 << 21),
254 .parent
= &clk_pclk_low
.clk
,
255 .enable
= s5p64x0_pclk_ctrl
,
256 .ctrlbit
= (1 << 22),
260 .parent
= &clk_pclk_low
.clk
,
261 .enable
= s5p64x0_pclk_ctrl
,
262 .ctrlbit
= (1 << 26),
266 .parent
= &clk_pclk_low
.clk
,
267 .enable
= s5p64x0_pclk_ctrl
,
268 .ctrlbit
= (1 << 27),
272 .parent
= &clk_pclk
.clk
,
273 .enable
= s5p64x0_pclk_ctrl
,
274 .ctrlbit
= (1 << 30),
279 * The following clocks will be enabled during clock initialization.
281 static struct clk init_clocks
[] = {
285 .parent
= &clk_hclk
.clk
,
286 .enable
= s5p64x0_hclk0_ctrl
,
291 .parent
= &clk_hclk
.clk
,
292 .enable
= s5p64x0_hclk0_ctrl
,
293 .ctrlbit
= (1 << 21),
297 .parent
= &clk_pclk_low
.clk
,
298 .enable
= s5p64x0_pclk_ctrl
,
303 .parent
= &clk_pclk_low
.clk
,
304 .enable
= s5p64x0_pclk_ctrl
,
309 .parent
= &clk_pclk_low
.clk
,
310 .enable
= s5p64x0_pclk_ctrl
,
315 .parent
= &clk_pclk_low
.clk
,
316 .enable
= s5p64x0_pclk_ctrl
,
321 .parent
= &clk_pclk_to_wdt_pwm
.clk
,
322 .enable
= s5p64x0_pclk_ctrl
,
327 .parent
= &clk_pclk_low
.clk
,
328 .enable
= s5p64x0_pclk_ctrl
,
329 .ctrlbit
= (1 << 18),
333 static struct clk
*clkset_uart_list
[] = {
338 static struct clksrc_sources clkset_uart
= {
339 .sources
= clkset_uart_list
,
340 .nr_sources
= ARRAY_SIZE(clkset_uart_list
),
343 static struct clk
*clkset_mali_list
[] = {
349 static struct clksrc_sources clkset_mali
= {
350 .sources
= clkset_mali_list
,
351 .nr_sources
= ARRAY_SIZE(clkset_mali_list
),
354 static struct clk
*clkset_group2_list
[] = {
360 static struct clksrc_sources clkset_group2
= {
361 .sources
= clkset_group2_list
,
362 .nr_sources
= ARRAY_SIZE(clkset_group2_list
),
365 static struct clk
*clkset_dispcon_list
[] = {
372 static struct clksrc_sources clkset_dispcon
= {
373 .sources
= clkset_dispcon_list
,
374 .nr_sources
= ARRAY_SIZE(clkset_dispcon_list
),
377 static struct clk
*clkset_hsmmc44_list
[] = {
385 static struct clksrc_sources clkset_hsmmc44
= {
386 .sources
= clkset_hsmmc44_list
,
387 .nr_sources
= ARRAY_SIZE(clkset_hsmmc44_list
),
390 static struct clk
*clkset_sclk_audio0_list
[] = {
391 [0] = &clk_dout_epll
.clk
,
392 [1] = &clk_dout_mpll
.clk
,
393 [2] = &clk_ext_xtal_mux
,
398 static struct clksrc_sources clkset_sclk_audio0
= {
399 .sources
= clkset_sclk_audio0_list
,
400 .nr_sources
= ARRAY_SIZE(clkset_sclk_audio0_list
),
403 static struct clksrc_clk clk_sclk_audio0
= {
407 .enable
= s5p64x0_sclk_ctrl
,
409 .parent
= &clk_dout_epll
.clk
,
411 .sources
= &clkset_sclk_audio0
,
412 .reg_src
= { .reg
= S5P64X0_CLK_SRC1
, .shift
= 10, .size
= 3 },
413 .reg_div
= { .reg
= S5P64X0_CLK_DIV2
, .shift
= 8, .size
= 4 },
416 static struct clksrc_clk clksrcs
[] = {
421 .ctrlbit
= (1 << 24),
422 .enable
= s5p64x0_sclk_ctrl
,
424 .sources
= &clkset_group2
,
425 .reg_src
= { .reg
= S5P64X0_CLK_SRC0
, .shift
= 18, .size
= 2 },
426 .reg_div
= { .reg
= S5P64X0_CLK_DIV1
, .shift
= 0, .size
= 4 },
431 .ctrlbit
= (1 << 25),
432 .enable
= s5p64x0_sclk_ctrl
,
434 .sources
= &clkset_group2
,
435 .reg_src
= { .reg
= S5P64X0_CLK_SRC0
, .shift
= 20, .size
= 2 },
436 .reg_div
= { .reg
= S5P64X0_CLK_DIV1
, .shift
= 4, .size
= 4 },
441 .ctrlbit
= (1 << 26),
442 .enable
= s5p64x0_sclk_ctrl
,
444 .sources
= &clkset_group2
,
445 .reg_src
= { .reg
= S5P64X0_CLK_SRC0
, .shift
= 22, .size
= 2 },
446 .reg_div
= { .reg
= S5P64X0_CLK_DIV1
, .shift
= 8, .size
= 4 },
452 .enable
= s5p64x0_sclk_ctrl
,
454 .sources
= &clkset_uart
,
455 .reg_src
= { .reg
= S5P64X0_CLK_SRC0
, .shift
= 13, .size
= 1 },
456 .reg_div
= { .reg
= S5P64X0_CLK_DIV2
, .shift
= 16, .size
= 4 },
461 .ctrlbit
= (1 << 20),
462 .enable
= s5p64x0_sclk_ctrl
,
464 .sources
= &clkset_group2
,
465 .reg_src
= { .reg
= S5P64X0_CLK_SRC0
, .shift
= 14, .size
= 2 },
466 .reg_div
= { .reg
= S5P64X0_CLK_DIV2
, .shift
= 0, .size
= 4 },
471 .ctrlbit
= (1 << 21),
472 .enable
= s5p64x0_sclk_ctrl
,
474 .sources
= &clkset_group2
,
475 .reg_src
= { .reg
= S5P64X0_CLK_SRC0
, .shift
= 16, .size
= 2 },
476 .reg_div
= { .reg
= S5P64X0_CLK_DIV2
, .shift
= 4, .size
= 4 },
481 .ctrlbit
= (1 << 10),
482 .enable
= s5p64x0_sclk_ctrl
,
484 .sources
= &clkset_group2
,
485 .reg_src
= { .reg
= S5P64X0_CLK_SRC0
, .shift
= 26, .size
= 2 },
486 .reg_div
= { .reg
= S5P64X0_CLK_DIV1
, .shift
= 12, .size
= 4 },
492 .enable
= s5p64x0_sclk1_ctrl
,
494 .sources
= &clkset_mali
,
495 .reg_src
= { .reg
= S5P64X0_CLK_SRC1
, .shift
= 8, .size
= 2 },
496 .reg_div
= { .reg
= S5P64X0_CLK_DIV3
, .shift
= 4, .size
= 4 },
501 .ctrlbit
= (1 << 12),
502 .enable
= s5p64x0_sclk_ctrl
,
504 .sources
= &clkset_mali
,
505 .reg_src
= { .reg
= S5P64X0_CLK_SRC0
, .shift
= 30, .size
= 2 },
506 .reg_div
= { .reg
= S5P64X0_CLK_DIV2
, .shift
= 20, .size
= 4 },
512 .enable
= s5p64x0_sclk_ctrl
,
514 .sources
= &clkset_group2
,
515 .reg_src
= { .reg
= S5P64X0_CLK_SRC0
, .shift
= 10, .size
= 2 },
516 .reg_div
= { .reg
= S5P64X0_CLK_DIV1
, .shift
= 16, .size
= 4 },
519 .name
= "sclk_camif",
522 .enable
= s5p64x0_sclk_ctrl
,
524 .sources
= &clkset_group2
,
525 .reg_src
= { .reg
= S5P64X0_CLK_SRC0
, .shift
= 28, .size
= 2 },
526 .reg_div
= { .reg
= S5P64X0_CLK_DIV1
, .shift
= 20, .size
= 4 },
529 .name
= "sclk_dispcon",
532 .enable
= s5p64x0_sclk1_ctrl
,
534 .sources
= &clkset_dispcon
,
535 .reg_src
= { .reg
= S5P64X0_CLK_SRC1
, .shift
= 4, .size
= 2 },
536 .reg_div
= { .reg
= S5P64X0_CLK_DIV3
, .shift
= 0, .size
= 4 },
539 .name
= "sclk_hsmmc44",
541 .ctrlbit
= (1 << 30),
542 .enable
= s5p64x0_sclk_ctrl
,
544 .sources
= &clkset_hsmmc44
,
545 .reg_src
= { .reg
= S5P64X0_CLK_SRC0
, .shift
= 6, .size
= 3 },
546 .reg_div
= { .reg
= S5P64X0_CLK_DIV1
, .shift
= 28, .size
= 4 },
550 /* Clock initialization code */
551 static struct clksrc_clk
*sysclks
[] = {
559 &clk_dout_pwm_ratio0
,
560 &clk_pclk_to_wdt_pwm
,
568 void __init_or_cpufreq
s5p6450_setup_clocks(void)
570 struct clk
*xtal_clk
;
575 unsigned long hclk_low
;
577 unsigned long pclk_low
;
585 /* Set S5P6450 functions for clk_fout_epll */
587 clk_fout_epll
.enable
= s5p_epll_enable
;
588 clk_fout_epll
.ops
= &s5p6450_epll_ops
;
590 clk_48m
.enable
= s5p64x0_clk48m_ctrl
;
592 xtal_clk
= clk_get(NULL
, "ext_xtal");
593 BUG_ON(IS_ERR(xtal_clk
));
595 xtal
= clk_get_rate(xtal_clk
);
598 apll
= s5p_get_pll45xx(xtal
, __raw_readl(S5P64X0_APLL_CON
), pll_4502
);
599 mpll
= s5p_get_pll45xx(xtal
, __raw_readl(S5P64X0_MPLL_CON
), pll_4502
);
600 epll
= s5p_get_pll90xx(xtal
, __raw_readl(S5P64X0_EPLL_CON
),
601 __raw_readl(S5P64X0_EPLL_CON_K
));
602 dpll
= s5p_get_pll46xx(xtal
, __raw_readl(S5P6450_DPLL_CON
),
603 __raw_readl(S5P6450_DPLL_CON_K
), pll_4650c
);
605 clk_fout_apll
.rate
= apll
;
606 clk_fout_mpll
.rate
= mpll
;
607 clk_fout_epll
.rate
= epll
;
608 clk_fout_dpll
.rate
= dpll
;
610 printk(KERN_INFO
"S5P6450: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
611 " E=%ld.%ldMHz, D=%ld.%ldMHz\n",
612 print_mhz(apll
), print_mhz(mpll
), print_mhz(epll
),
615 fclk
= clk_get_rate(&clk_armclk
.clk
);
616 hclk
= clk_get_rate(&clk_hclk
.clk
);
617 pclk
= clk_get_rate(&clk_pclk
.clk
);
618 hclk_low
= clk_get_rate(&clk_hclk_low
.clk
);
619 pclk_low
= clk_get_rate(&clk_pclk_low
.clk
);
621 printk(KERN_INFO
"S5P6450: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
622 " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
623 print_mhz(hclk
), print_mhz(hclk_low
),
624 print_mhz(pclk
), print_mhz(pclk_low
));
630 for (ptr
= 0; ptr
< ARRAY_SIZE(clksrcs
); ptr
++)
631 s3c_set_clksrc(&clksrcs
[ptr
], true);
634 void __init
s5p6450_register_clocks(void)
640 for (ptr
= 0; ptr
< ARRAY_SIZE(sysclks
); ptr
++)
641 s3c_register_clksrc(sysclks
[ptr
], 1);
643 s3c_register_clksrc(clksrcs
, ARRAY_SIZE(clksrcs
));
644 s3c_register_clocks(init_clocks
, ARRAY_SIZE(init_clocks
));
646 clkp
= init_clocks_disable
;
647 for (ptr
= 0; ptr
< ARRAY_SIZE(init_clocks_disable
); ptr
++, clkp
++) {
649 ret
= s3c24xx_register_clock(clkp
);
651 printk(KERN_ERR
"Failed to register clock %s (%d)\n",
654 (clkp
->enable
)(clkp
, 0);