2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * Copyright (C) 2014 ARM Limited
14 #include <linux/ctype.h>
15 #include <linux/hrtimer.h>
16 #include <linux/idr.h>
17 #include <linux/interrupt.h>
19 #include <linux/module.h>
20 #include <linux/perf_event.h>
21 #include <linux/platform_device.h>
22 #include <linux/slab.h>
24 #define CCN_NUM_XP_PORTS 2
26 #define CCN_NUM_REGIONS 256
27 #define CCN_REGION_SIZE 0x10000
29 #define CCN_ALL_OLY_ID 0xff00
30 #define CCN_ALL_OLY_ID__OLY_ID__SHIFT 0
31 #define CCN_ALL_OLY_ID__OLY_ID__MASK 0x1f
32 #define CCN_ALL_OLY_ID__NODE_ID__SHIFT 8
33 #define CCN_ALL_OLY_ID__NODE_ID__MASK 0x3f
35 #define CCN_MN_ERRINT_STATUS 0x0008
36 #define CCN_MN_ERRINT_STATUS__INTREQ__DESSERT 0x11
37 #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__ENABLE 0x02
38 #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLED 0x20
39 #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLE 0x22
40 #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_ENABLE 0x04
41 #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_DISABLED 0x40
42 #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_DISABLE 0x44
43 #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE 0x08
44 #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLED 0x80
45 #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLE 0x88
46 #define CCN_MN_OLY_COMP_LIST_63_0 0x01e0
47 #define CCN_MN_ERR_SIG_VAL_63_0 0x0300
48 #define CCN_MN_ERR_SIG_VAL_63_0__DT (1 << 1)
50 #define CCN_DT_ACTIVE_DSM 0x0000
51 #define CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(n) ((n) * 8)
52 #define CCN_DT_ACTIVE_DSM__DSM_ID__MASK 0xff
53 #define CCN_DT_CTL 0x0028
54 #define CCN_DT_CTL__DT_EN (1 << 0)
55 #define CCN_DT_PMEVCNT(n) (0x0100 + (n) * 0x8)
56 #define CCN_DT_PMCCNTR 0x0140
57 #define CCN_DT_PMCCNTRSR 0x0190
58 #define CCN_DT_PMOVSR 0x0198
59 #define CCN_DT_PMOVSR_CLR 0x01a0
60 #define CCN_DT_PMCR 0x01a8
61 #define CCN_DT_PMCR__OVFL_INTR_EN (1 << 6)
62 #define CCN_DT_PMCR__PMU_EN (1 << 0)
63 #define CCN_DT_PMSR 0x01b0
64 #define CCN_DT_PMSR_REQ 0x01b8
65 #define CCN_DT_PMSR_CLR 0x01c0
67 #define CCN_HNF_PMU_EVENT_SEL 0x0600
68 #define CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4)
69 #define CCN_HNF_PMU_EVENT_SEL__ID__MASK 0xf
71 #define CCN_XP_DT_CONFIG 0x0300
72 #define CCN_XP_DT_CONFIG__DT_CFG__SHIFT(n) ((n) * 4)
73 #define CCN_XP_DT_CONFIG__DT_CFG__MASK 0xf
74 #define CCN_XP_DT_CONFIG__DT_CFG__PASS_THROUGH 0x0
75 #define CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT_0_OR_1 0x1
76 #define CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(n) (0x2 + (n))
77 #define CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(n) (0x4 + (n))
78 #define CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(d, n) (0x8 + (d) * 4 + (n))
79 #define CCN_XP_DT_INTERFACE_SEL 0x0308
80 #define CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(n) (0 + (n) * 8)
81 #define CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__MASK 0x1
82 #define CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(n) (1 + (n) * 8)
83 #define CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__MASK 0x1
84 #define CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(n) (2 + (n) * 8)
85 #define CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__MASK 0x3
86 #define CCN_XP_DT_CMP_VAL_L(n) (0x0310 + (n) * 0x40)
87 #define CCN_XP_DT_CMP_VAL_H(n) (0x0318 + (n) * 0x40)
88 #define CCN_XP_DT_CMP_MASK_L(n) (0x0320 + (n) * 0x40)
89 #define CCN_XP_DT_CMP_MASK_H(n) (0x0328 + (n) * 0x40)
90 #define CCN_XP_DT_CONTROL 0x0370
91 #define CCN_XP_DT_CONTROL__DT_ENABLE (1 << 0)
92 #define CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(n) (12 + (n) * 4)
93 #define CCN_XP_DT_CONTROL__WP_ARM_SEL__MASK 0xf
94 #define CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS 0xf
95 #define CCN_XP_PMU_EVENT_SEL 0x0600
96 #define CCN_XP_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 7)
97 #define CCN_XP_PMU_EVENT_SEL__ID__MASK 0x3f
99 #define CCN_SBAS_PMU_EVENT_SEL 0x0600
100 #define CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4)
101 #define CCN_SBAS_PMU_EVENT_SEL__ID__MASK 0xf
103 #define CCN_RNI_PMU_EVENT_SEL 0x0600
104 #define CCN_RNI_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4)
105 #define CCN_RNI_PMU_EVENT_SEL__ID__MASK 0xf
107 #define CCN_TYPE_MN 0x01
108 #define CCN_TYPE_DT 0x02
109 #define CCN_TYPE_HNF 0x04
110 #define CCN_TYPE_HNI 0x05
111 #define CCN_TYPE_XP 0x08
112 #define CCN_TYPE_SBSX 0x0c
113 #define CCN_TYPE_SBAS 0x10
114 #define CCN_TYPE_RNI_1P 0x14
115 #define CCN_TYPE_RNI_2P 0x15
116 #define CCN_TYPE_RNI_3P 0x16
117 #define CCN_TYPE_RND_1P 0x18 /* RN-D = RN-I + DVM */
118 #define CCN_TYPE_RND_2P 0x19
119 #define CCN_TYPE_RND_3P 0x1a
120 #define CCN_TYPE_CYCLES 0xff /* Pseudotype */
122 #define CCN_EVENT_WATCHPOINT 0xfe /* Pseudoevent */
124 #define CCN_NUM_PMU_EVENTS 4
125 #define CCN_NUM_XP_WATCHPOINTS 2 /* See DT.dbg_id.num_watchpoints */
126 #define CCN_NUM_PMU_EVENT_COUNTERS 8 /* See DT.dbg_id.num_pmucntr */
127 #define CCN_IDX_PMU_CYCLE_COUNTER CCN_NUM_PMU_EVENT_COUNTERS
129 #define CCN_NUM_PREDEFINED_MASKS 4
130 #define CCN_IDX_MASK_ANY (CCN_NUM_PMU_EVENT_COUNTERS + 0)
131 #define CCN_IDX_MASK_EXACT (CCN_NUM_PMU_EVENT_COUNTERS + 1)
132 #define CCN_IDX_MASK_ORDER (CCN_NUM_PMU_EVENT_COUNTERS + 2)
133 #define CCN_IDX_MASK_OPCODE (CCN_NUM_PMU_EVENT_COUNTERS + 3)
135 struct arm_ccn_component
{
139 DECLARE_BITMAP(pmu_events_mask
, CCN_NUM_PMU_EVENTS
);
142 DECLARE_BITMAP(dt_cmp_mask
, CCN_NUM_XP_WATCHPOINTS
);
147 #define pmu_to_arm_ccn(_pmu) container_of(container_of(_pmu, \
148 struct arm_ccn_dt, pmu), struct arm_ccn, dt)
154 spinlock_t config_lock
;
156 DECLARE_BITMAP(pmu_counters_mask
, CCN_NUM_PMU_EVENT_COUNTERS
+ 1);
158 struct arm_ccn_component
*source
;
159 struct perf_event
*event
;
160 } pmu_counters
[CCN_NUM_PMU_EVENT_COUNTERS
+ 1];
164 } cmp_mask
[CCN_NUM_PMU_EVENT_COUNTERS
+ CCN_NUM_PREDEFINED_MASKS
];
166 struct hrtimer hrtimer
;
175 unsigned sbas_present
:1;
176 unsigned sbsx_present
:1;
179 struct arm_ccn_component
*node
;
182 struct arm_ccn_component
*xp
;
184 struct arm_ccn_dt dt
;
188 static int arm_ccn_node_to_xp(int node
)
190 return node
/ CCN_NUM_XP_PORTS
;
193 static int arm_ccn_node_to_xp_port(int node
)
195 return node
% CCN_NUM_XP_PORTS
;
200 * Bit shifts and masks in these defines must be kept in sync with
201 * arm_ccn_pmu_config_set() and CCN_FORMAT_ATTRs below!
203 #define CCN_CONFIG_NODE(_config) (((_config) >> 0) & 0xff)
204 #define CCN_CONFIG_XP(_config) (((_config) >> 0) & 0xff)
205 #define CCN_CONFIG_TYPE(_config) (((_config) >> 8) & 0xff)
206 #define CCN_CONFIG_EVENT(_config) (((_config) >> 16) & 0xff)
207 #define CCN_CONFIG_PORT(_config) (((_config) >> 24) & 0x3)
208 #define CCN_CONFIG_VC(_config) (((_config) >> 26) & 0x7)
209 #define CCN_CONFIG_DIR(_config) (((_config) >> 29) & 0x1)
210 #define CCN_CONFIG_MASK(_config) (((_config) >> 30) & 0xf)
212 static void arm_ccn_pmu_config_set(u64
*config
, u32 node_xp
, u32 type
, u32 port
)
214 *config
&= ~((0xff << 0) | (0xff << 8) | (0xff << 24));
215 *config
|= (node_xp
<< 0) | (type
<< 8) | (port
<< 24);
218 static ssize_t
arm_ccn_pmu_format_show(struct device
*dev
,
219 struct device_attribute
*attr
, char *buf
)
221 struct dev_ext_attribute
*ea
= container_of(attr
,
222 struct dev_ext_attribute
, attr
);
224 return snprintf(buf
, PAGE_SIZE
, "%s\n", (char *)ea
->var
);
227 #define CCN_FORMAT_ATTR(_name, _config) \
228 struct dev_ext_attribute arm_ccn_pmu_format_attr_##_name = \
229 { __ATTR(_name, S_IRUGO, arm_ccn_pmu_format_show, \
232 static CCN_FORMAT_ATTR(node
, "config:0-7");
233 static CCN_FORMAT_ATTR(xp
, "config:0-7");
234 static CCN_FORMAT_ATTR(type
, "config:8-15");
235 static CCN_FORMAT_ATTR(event
, "config:16-23");
236 static CCN_FORMAT_ATTR(port
, "config:24-25");
237 static CCN_FORMAT_ATTR(vc
, "config:26-28");
238 static CCN_FORMAT_ATTR(dir
, "config:29-29");
239 static CCN_FORMAT_ATTR(mask
, "config:30-33");
240 static CCN_FORMAT_ATTR(cmp_l
, "config1:0-62");
241 static CCN_FORMAT_ATTR(cmp_h
, "config2:0-59");
243 static struct attribute
*arm_ccn_pmu_format_attrs
[] = {
244 &arm_ccn_pmu_format_attr_node
.attr
.attr
,
245 &arm_ccn_pmu_format_attr_xp
.attr
.attr
,
246 &arm_ccn_pmu_format_attr_type
.attr
.attr
,
247 &arm_ccn_pmu_format_attr_event
.attr
.attr
,
248 &arm_ccn_pmu_format_attr_port
.attr
.attr
,
249 &arm_ccn_pmu_format_attr_vc
.attr
.attr
,
250 &arm_ccn_pmu_format_attr_dir
.attr
.attr
,
251 &arm_ccn_pmu_format_attr_mask
.attr
.attr
,
252 &arm_ccn_pmu_format_attr_cmp_l
.attr
.attr
,
253 &arm_ccn_pmu_format_attr_cmp_h
.attr
.attr
,
257 static struct attribute_group arm_ccn_pmu_format_attr_group
= {
259 .attrs
= arm_ccn_pmu_format_attrs
,
263 struct arm_ccn_pmu_event
{
264 struct device_attribute attr
;
273 #define CCN_EVENT_ATTR(_name) \
274 __ATTR(_name, S_IRUGO, arm_ccn_pmu_event_show, NULL)
277 * Events defined in TRM for MN, HN-I and SBSX are actually watchpoints set on
278 * their ports in XP they are connected to. For the sake of usability they are
279 * explicitly defined here (and translated into a relevant watchpoint in
280 * arm_ccn_pmu_event_init()) so the user can easily request them without deep
281 * knowledge of the flit format.
284 #define CCN_EVENT_MN(_name, _def, _mask) { .attr = CCN_EVENT_ATTR(mn_##_name), \
285 .type = CCN_TYPE_MN, .event = CCN_EVENT_WATCHPOINT, \
286 .num_ports = CCN_NUM_XP_PORTS, .num_vcs = CCN_NUM_VCS, \
287 .def = _def, .mask = _mask, }
289 #define CCN_EVENT_HNI(_name, _def, _mask) { \
290 .attr = CCN_EVENT_ATTR(hni_##_name), .type = CCN_TYPE_HNI, \
291 .event = CCN_EVENT_WATCHPOINT, .num_ports = CCN_NUM_XP_PORTS, \
292 .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, }
294 #define CCN_EVENT_SBSX(_name, _def, _mask) { \
295 .attr = CCN_EVENT_ATTR(sbsx_##_name), .type = CCN_TYPE_SBSX, \
296 .event = CCN_EVENT_WATCHPOINT, .num_ports = CCN_NUM_XP_PORTS, \
297 .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, }
299 #define CCN_EVENT_HNF(_name, _event) { .attr = CCN_EVENT_ATTR(hnf_##_name), \
300 .type = CCN_TYPE_HNF, .event = _event, }
302 #define CCN_EVENT_XP(_name, _event) { .attr = CCN_EVENT_ATTR(xp_##_name), \
303 .type = CCN_TYPE_XP, .event = _event, \
304 .num_ports = CCN_NUM_XP_PORTS, .num_vcs = CCN_NUM_VCS, }
307 * RN-I & RN-D (RN-D = RN-I + DVM) nodes have different type ID depending
308 * on configuration. One of them is picked to represent the whole group,
309 * as they all share the same event types.
311 #define CCN_EVENT_RNI(_name, _event) { .attr = CCN_EVENT_ATTR(rni_##_name), \
312 .type = CCN_TYPE_RNI_3P, .event = _event, }
314 #define CCN_EVENT_SBAS(_name, _event) { .attr = CCN_EVENT_ATTR(sbas_##_name), \
315 .type = CCN_TYPE_SBAS, .event = _event, }
317 #define CCN_EVENT_CYCLES(_name) { .attr = CCN_EVENT_ATTR(_name), \
318 .type = CCN_TYPE_CYCLES }
321 static ssize_t
arm_ccn_pmu_event_show(struct device
*dev
,
322 struct device_attribute
*attr
, char *buf
)
324 struct arm_ccn_pmu_event
*event
= container_of(attr
,
325 struct arm_ccn_pmu_event
, attr
);
328 res
= snprintf(buf
, PAGE_SIZE
, "type=0x%x", event
->type
);
330 res
+= snprintf(buf
+ res
, PAGE_SIZE
- res
, ",event=0x%x",
333 res
+= snprintf(buf
+ res
, PAGE_SIZE
- res
, ",%s",
336 res
+= snprintf(buf
+ res
, PAGE_SIZE
- res
, ",mask=0x%x",
338 res
+= snprintf(buf
+ res
, PAGE_SIZE
- res
, "\n");
343 static umode_t
arm_ccn_pmu_events_is_visible(struct kobject
*kobj
,
344 struct attribute
*attr
, int index
)
346 struct device
*dev
= kobj_to_dev(kobj
);
347 struct arm_ccn
*ccn
= pmu_to_arm_ccn(dev_get_drvdata(dev
));
348 struct device_attribute
*dev_attr
= container_of(attr
,
349 struct device_attribute
, attr
);
350 struct arm_ccn_pmu_event
*event
= container_of(dev_attr
,
351 struct arm_ccn_pmu_event
, attr
);
353 if (event
->type
== CCN_TYPE_SBAS
&& !ccn
->sbas_present
)
355 if (event
->type
== CCN_TYPE_SBSX
&& !ccn
->sbsx_present
)
361 static struct arm_ccn_pmu_event arm_ccn_pmu_events
[] = {
362 CCN_EVENT_MN(eobarrier
, "dir=0,vc=0,cmp_h=0x1c00", CCN_IDX_MASK_OPCODE
),
363 CCN_EVENT_MN(ecbarrier
, "dir=0,vc=0,cmp_h=0x1e00", CCN_IDX_MASK_OPCODE
),
364 CCN_EVENT_MN(dvmop
, "dir=0,vc=0,cmp_h=0x2800", CCN_IDX_MASK_OPCODE
),
365 CCN_EVENT_HNI(txdatflits
, "dir=1,vc=3", CCN_IDX_MASK_ANY
),
366 CCN_EVENT_HNI(rxdatflits
, "dir=0,vc=3", CCN_IDX_MASK_ANY
),
367 CCN_EVENT_HNI(txreqflits
, "dir=1,vc=0", CCN_IDX_MASK_ANY
),
368 CCN_EVENT_HNI(rxreqflits
, "dir=0,vc=0", CCN_IDX_MASK_ANY
),
369 CCN_EVENT_HNI(rxreqflits_order
, "dir=0,vc=0,cmp_h=0x8000",
371 CCN_EVENT_SBSX(txdatflits
, "dir=1,vc=3", CCN_IDX_MASK_ANY
),
372 CCN_EVENT_SBSX(rxdatflits
, "dir=0,vc=3", CCN_IDX_MASK_ANY
),
373 CCN_EVENT_SBSX(txreqflits
, "dir=1,vc=0", CCN_IDX_MASK_ANY
),
374 CCN_EVENT_SBSX(rxreqflits
, "dir=0,vc=0", CCN_IDX_MASK_ANY
),
375 CCN_EVENT_SBSX(rxreqflits_order
, "dir=0,vc=0,cmp_h=0x8000",
377 CCN_EVENT_HNF(cache_miss
, 0x1),
378 CCN_EVENT_HNF(l3_sf_cache_access
, 0x02),
379 CCN_EVENT_HNF(cache_fill
, 0x3),
380 CCN_EVENT_HNF(pocq_retry
, 0x4),
381 CCN_EVENT_HNF(pocq_reqs_recvd
, 0x5),
382 CCN_EVENT_HNF(sf_hit
, 0x6),
383 CCN_EVENT_HNF(sf_evictions
, 0x7),
384 CCN_EVENT_HNF(snoops_sent
, 0x8),
385 CCN_EVENT_HNF(snoops_broadcast
, 0x9),
386 CCN_EVENT_HNF(l3_eviction
, 0xa),
387 CCN_EVENT_HNF(l3_fill_invalid_way
, 0xb),
388 CCN_EVENT_HNF(mc_retries
, 0xc),
389 CCN_EVENT_HNF(mc_reqs
, 0xd),
390 CCN_EVENT_HNF(qos_hh_retry
, 0xe),
391 CCN_EVENT_RNI(rdata_beats_p0
, 0x1),
392 CCN_EVENT_RNI(rdata_beats_p1
, 0x2),
393 CCN_EVENT_RNI(rdata_beats_p2
, 0x3),
394 CCN_EVENT_RNI(rxdat_flits
, 0x4),
395 CCN_EVENT_RNI(txdat_flits
, 0x5),
396 CCN_EVENT_RNI(txreq_flits
, 0x6),
397 CCN_EVENT_RNI(txreq_flits_retried
, 0x7),
398 CCN_EVENT_RNI(rrt_full
, 0x8),
399 CCN_EVENT_RNI(wrt_full
, 0x9),
400 CCN_EVENT_RNI(txreq_flits_replayed
, 0xa),
401 CCN_EVENT_XP(upload_starvation
, 0x1),
402 CCN_EVENT_XP(download_starvation
, 0x2),
403 CCN_EVENT_XP(respin
, 0x3),
404 CCN_EVENT_XP(valid_flit
, 0x4),
405 CCN_EVENT_XP(watchpoint
, CCN_EVENT_WATCHPOINT
),
406 CCN_EVENT_SBAS(rdata_beats_p0
, 0x1),
407 CCN_EVENT_SBAS(rxdat_flits
, 0x4),
408 CCN_EVENT_SBAS(txdat_flits
, 0x5),
409 CCN_EVENT_SBAS(txreq_flits
, 0x6),
410 CCN_EVENT_SBAS(txreq_flits_retried
, 0x7),
411 CCN_EVENT_SBAS(rrt_full
, 0x8),
412 CCN_EVENT_SBAS(wrt_full
, 0x9),
413 CCN_EVENT_SBAS(txreq_flits_replayed
, 0xa),
414 CCN_EVENT_CYCLES(cycles
),
417 /* Populated in arm_ccn_init() */
418 static struct attribute
419 *arm_ccn_pmu_events_attrs
[ARRAY_SIZE(arm_ccn_pmu_events
) + 1];
421 static struct attribute_group arm_ccn_pmu_events_attr_group
= {
423 .is_visible
= arm_ccn_pmu_events_is_visible
,
424 .attrs
= arm_ccn_pmu_events_attrs
,
428 static u64
*arm_ccn_pmu_get_cmp_mask(struct arm_ccn
*ccn
, const char *name
)
432 if (WARN_ON(!name
|| !name
[0] || !isxdigit(name
[0]) || !name
[1]))
434 i
= isdigit(name
[0]) ? name
[0] - '0' : 0xa + tolower(name
[0]) - 'a';
438 return &ccn
->dt
.cmp_mask
[i
].l
;
440 return &ccn
->dt
.cmp_mask
[i
].h
;
446 static ssize_t
arm_ccn_pmu_cmp_mask_show(struct device
*dev
,
447 struct device_attribute
*attr
, char *buf
)
449 struct arm_ccn
*ccn
= pmu_to_arm_ccn(dev_get_drvdata(dev
));
450 u64
*mask
= arm_ccn_pmu_get_cmp_mask(ccn
, attr
->attr
.name
);
452 return mask
? snprintf(buf
, PAGE_SIZE
, "0x%016llx\n", *mask
) : -EINVAL
;
455 static ssize_t
arm_ccn_pmu_cmp_mask_store(struct device
*dev
,
456 struct device_attribute
*attr
, const char *buf
, size_t count
)
458 struct arm_ccn
*ccn
= pmu_to_arm_ccn(dev_get_drvdata(dev
));
459 u64
*mask
= arm_ccn_pmu_get_cmp_mask(ccn
, attr
->attr
.name
);
463 err
= kstrtoull(buf
, 0, mask
);
465 return err
? err
: count
;
468 #define CCN_CMP_MASK_ATTR(_name) \
469 struct device_attribute arm_ccn_pmu_cmp_mask_attr_##_name = \
470 __ATTR(_name, S_IRUGO | S_IWUSR, \
471 arm_ccn_pmu_cmp_mask_show, arm_ccn_pmu_cmp_mask_store)
473 #define CCN_CMP_MASK_ATTR_RO(_name) \
474 struct device_attribute arm_ccn_pmu_cmp_mask_attr_##_name = \
475 __ATTR(_name, S_IRUGO, arm_ccn_pmu_cmp_mask_show, NULL)
477 static CCN_CMP_MASK_ATTR(0l);
478 static CCN_CMP_MASK_ATTR(0h
);
479 static CCN_CMP_MASK_ATTR(1l);
480 static CCN_CMP_MASK_ATTR(1h
);
481 static CCN_CMP_MASK_ATTR(2l);
482 static CCN_CMP_MASK_ATTR(2h
);
483 static CCN_CMP_MASK_ATTR(3l);
484 static CCN_CMP_MASK_ATTR(3h
);
485 static CCN_CMP_MASK_ATTR(4l);
486 static CCN_CMP_MASK_ATTR(4h
);
487 static CCN_CMP_MASK_ATTR(5l);
488 static CCN_CMP_MASK_ATTR(5h
);
489 static CCN_CMP_MASK_ATTR(6l);
490 static CCN_CMP_MASK_ATTR(6h
);
491 static CCN_CMP_MASK_ATTR(7l);
492 static CCN_CMP_MASK_ATTR(7h
);
493 static CCN_CMP_MASK_ATTR_RO(8l);
494 static CCN_CMP_MASK_ATTR_RO(8h
);
495 static CCN_CMP_MASK_ATTR_RO(9l);
496 static CCN_CMP_MASK_ATTR_RO(9h
);
497 static CCN_CMP_MASK_ATTR_RO(al
);
498 static CCN_CMP_MASK_ATTR_RO(ah
);
499 static CCN_CMP_MASK_ATTR_RO(bl
);
500 static CCN_CMP_MASK_ATTR_RO(bh
);
502 static struct attribute
*arm_ccn_pmu_cmp_mask_attrs
[] = {
503 &arm_ccn_pmu_cmp_mask_attr_0l
.attr
, &arm_ccn_pmu_cmp_mask_attr_0h
.attr
,
504 &arm_ccn_pmu_cmp_mask_attr_1l
.attr
, &arm_ccn_pmu_cmp_mask_attr_1h
.attr
,
505 &arm_ccn_pmu_cmp_mask_attr_2l
.attr
, &arm_ccn_pmu_cmp_mask_attr_2h
.attr
,
506 &arm_ccn_pmu_cmp_mask_attr_3l
.attr
, &arm_ccn_pmu_cmp_mask_attr_3h
.attr
,
507 &arm_ccn_pmu_cmp_mask_attr_4l
.attr
, &arm_ccn_pmu_cmp_mask_attr_4h
.attr
,
508 &arm_ccn_pmu_cmp_mask_attr_5l
.attr
, &arm_ccn_pmu_cmp_mask_attr_5h
.attr
,
509 &arm_ccn_pmu_cmp_mask_attr_6l
.attr
, &arm_ccn_pmu_cmp_mask_attr_6h
.attr
,
510 &arm_ccn_pmu_cmp_mask_attr_7l
.attr
, &arm_ccn_pmu_cmp_mask_attr_7h
.attr
,
511 &arm_ccn_pmu_cmp_mask_attr_8l
.attr
, &arm_ccn_pmu_cmp_mask_attr_8h
.attr
,
512 &arm_ccn_pmu_cmp_mask_attr_9l
.attr
, &arm_ccn_pmu_cmp_mask_attr_9h
.attr
,
513 &arm_ccn_pmu_cmp_mask_attr_al
.attr
, &arm_ccn_pmu_cmp_mask_attr_ah
.attr
,
514 &arm_ccn_pmu_cmp_mask_attr_bl
.attr
, &arm_ccn_pmu_cmp_mask_attr_bh
.attr
,
518 static struct attribute_group arm_ccn_pmu_cmp_mask_attr_group
= {
520 .attrs
= arm_ccn_pmu_cmp_mask_attrs
,
525 * Default poll period is 10ms, which is way over the top anyway,
526 * as in the worst case scenario (an event every cycle), with 1GHz
527 * clocked bus, the smallest, 32 bit counter will overflow in
530 static unsigned int arm_ccn_pmu_poll_period_us
= 10000;
531 module_param_named(pmu_poll_period_us
, arm_ccn_pmu_poll_period_us
, uint
,
534 static ktime_t
arm_ccn_pmu_timer_period(void)
536 return ns_to_ktime((u64
)arm_ccn_pmu_poll_period_us
* 1000);
540 static const struct attribute_group
*arm_ccn_pmu_attr_groups
[] = {
541 &arm_ccn_pmu_events_attr_group
,
542 &arm_ccn_pmu_format_attr_group
,
543 &arm_ccn_pmu_cmp_mask_attr_group
,
548 static int arm_ccn_pmu_alloc_bit(unsigned long *bitmap
, unsigned long size
)
553 bit
= find_first_zero_bit(bitmap
, size
);
556 } while (test_and_set_bit(bit
, bitmap
));
561 /* All RN-I and RN-D nodes have identical PMUs */
562 static int arm_ccn_pmu_type_eq(u32 a
, u32 b
)
568 case CCN_TYPE_RNI_1P
:
569 case CCN_TYPE_RNI_2P
:
570 case CCN_TYPE_RNI_3P
:
571 case CCN_TYPE_RND_1P
:
572 case CCN_TYPE_RND_2P
:
573 case CCN_TYPE_RND_3P
:
575 case CCN_TYPE_RNI_1P
:
576 case CCN_TYPE_RNI_2P
:
577 case CCN_TYPE_RNI_3P
:
578 case CCN_TYPE_RND_1P
:
579 case CCN_TYPE_RND_2P
:
580 case CCN_TYPE_RND_3P
:
589 static int arm_ccn_pmu_event_init(struct perf_event
*event
)
592 struct hw_perf_event
*hw
= &event
->hw
;
593 u32 node_xp
, type
, event_id
;
595 struct arm_ccn_component
*source
;
598 if (event
->attr
.type
!= event
->pmu
->type
)
601 ccn
= pmu_to_arm_ccn(event
->pmu
);
603 if (hw
->sample_period
) {
604 dev_warn(ccn
->dev
, "Sampling not supported!\n");
608 if (has_branch_stack(event
) || event
->attr
.exclude_user
||
609 event
->attr
.exclude_kernel
|| event
->attr
.exclude_hv
||
610 event
->attr
.exclude_idle
) {
611 dev_warn(ccn
->dev
, "Can't exclude execution levels!\n");
615 if (event
->cpu
< 0) {
616 dev_warn(ccn
->dev
, "Can't provide per-task data!\n");
620 node_xp
= CCN_CONFIG_NODE(event
->attr
.config
);
621 type
= CCN_CONFIG_TYPE(event
->attr
.config
);
622 event_id
= CCN_CONFIG_EVENT(event
->attr
.config
);
624 /* Validate node/xp vs topology */
627 if (node_xp
>= ccn
->num_xps
) {
628 dev_warn(ccn
->dev
, "Invalid XP ID %d!\n", node_xp
);
632 case CCN_TYPE_CYCLES
:
635 if (node_xp
>= ccn
->num_nodes
) {
636 dev_warn(ccn
->dev
, "Invalid node ID %d!\n", node_xp
);
639 if (!arm_ccn_pmu_type_eq(type
, ccn
->node
[node_xp
].type
)) {
640 dev_warn(ccn
->dev
, "Invalid type 0x%x for node %d!\n",
647 /* Validate event ID vs available for the type */
648 for (i
= 0, valid
= 0; i
< ARRAY_SIZE(arm_ccn_pmu_events
) && !valid
;
650 struct arm_ccn_pmu_event
*e
= &arm_ccn_pmu_events
[i
];
651 u32 port
= CCN_CONFIG_PORT(event
->attr
.config
);
652 u32 vc
= CCN_CONFIG_VC(event
->attr
.config
);
654 if (!arm_ccn_pmu_type_eq(type
, e
->type
))
656 if (event_id
!= e
->event
)
658 if (e
->num_ports
&& port
>= e
->num_ports
) {
659 dev_warn(ccn
->dev
, "Invalid port %d for node/XP %d!\n",
663 if (e
->num_vcs
&& vc
>= e
->num_vcs
) {
664 dev_warn(ccn
->dev
, "Invalid vc %d for node/XP %d!\n",
671 dev_warn(ccn
->dev
, "Invalid event 0x%x for node/XP %d!\n",
676 /* Watchpoint-based event for a node is actually set on XP */
677 if (event_id
== CCN_EVENT_WATCHPOINT
&& type
!= CCN_TYPE_XP
) {
681 port
= arm_ccn_node_to_xp_port(node_xp
);
682 node_xp
= arm_ccn_node_to_xp(node_xp
);
684 arm_ccn_pmu_config_set(&event
->attr
.config
,
685 node_xp
, type
, port
);
688 /* Allocate the cycle counter */
689 if (type
== CCN_TYPE_CYCLES
) {
690 if (test_and_set_bit(CCN_IDX_PMU_CYCLE_COUNTER
,
691 ccn
->dt
.pmu_counters_mask
))
694 hw
->idx
= CCN_IDX_PMU_CYCLE_COUNTER
;
695 ccn
->dt
.pmu_counters
[CCN_IDX_PMU_CYCLE_COUNTER
].event
= event
;
700 /* Allocate an event counter */
701 hw
->idx
= arm_ccn_pmu_alloc_bit(ccn
->dt
.pmu_counters_mask
,
702 CCN_NUM_PMU_EVENT_COUNTERS
);
704 dev_warn(ccn
->dev
, "No more counters available!\n");
708 if (type
== CCN_TYPE_XP
)
709 source
= &ccn
->xp
[node_xp
];
711 source
= &ccn
->node
[node_xp
];
712 ccn
->dt
.pmu_counters
[hw
->idx
].source
= source
;
714 /* Allocate an event source or a watchpoint */
715 if (type
== CCN_TYPE_XP
&& event_id
== CCN_EVENT_WATCHPOINT
)
716 bit
= arm_ccn_pmu_alloc_bit(source
->xp
.dt_cmp_mask
,
717 CCN_NUM_XP_WATCHPOINTS
);
719 bit
= arm_ccn_pmu_alloc_bit(source
->pmu_events_mask
,
722 dev_warn(ccn
->dev
, "No more event sources/watchpoints on node/XP %d!\n",
724 clear_bit(hw
->idx
, ccn
->dt
.pmu_counters_mask
);
727 hw
->config_base
= bit
;
729 ccn
->dt
.pmu_counters
[hw
->idx
].event
= event
;
734 static void arm_ccn_pmu_event_free(struct perf_event
*event
)
736 struct arm_ccn
*ccn
= pmu_to_arm_ccn(event
->pmu
);
737 struct hw_perf_event
*hw
= &event
->hw
;
739 if (hw
->idx
== CCN_IDX_PMU_CYCLE_COUNTER
) {
740 clear_bit(CCN_IDX_PMU_CYCLE_COUNTER
, ccn
->dt
.pmu_counters_mask
);
742 struct arm_ccn_component
*source
=
743 ccn
->dt
.pmu_counters
[hw
->idx
].source
;
745 if (CCN_CONFIG_TYPE(event
->attr
.config
) == CCN_TYPE_XP
&&
746 CCN_CONFIG_EVENT(event
->attr
.config
) ==
747 CCN_EVENT_WATCHPOINT
)
748 clear_bit(hw
->config_base
, source
->xp
.dt_cmp_mask
);
750 clear_bit(hw
->config_base
, source
->pmu_events_mask
);
751 clear_bit(hw
->idx
, ccn
->dt
.pmu_counters_mask
);
754 ccn
->dt
.pmu_counters
[hw
->idx
].source
= NULL
;
755 ccn
->dt
.pmu_counters
[hw
->idx
].event
= NULL
;
758 static u64
arm_ccn_pmu_read_counter(struct arm_ccn
*ccn
, int idx
)
762 if (idx
== CCN_IDX_PMU_CYCLE_COUNTER
) {
764 res
= readq(ccn
->dt
.base
+ CCN_DT_PMCCNTR
);
766 /* 40 bit counter, can do snapshot and read in two parts */
767 writel(0x1, ccn
->dt
.base
+ CCN_DT_PMSR_REQ
);
768 while (!(readl(ccn
->dt
.base
+ CCN_DT_PMSR
) & 0x1))
770 writel(0x1, ccn
->dt
.base
+ CCN_DT_PMSR_CLR
);
771 res
= readl(ccn
->dt
.base
+ CCN_DT_PMCCNTRSR
+ 4) & 0xff;
773 res
|= readl(ccn
->dt
.base
+ CCN_DT_PMCCNTRSR
);
776 res
= readl(ccn
->dt
.base
+ CCN_DT_PMEVCNT(idx
));
782 static void arm_ccn_pmu_event_update(struct perf_event
*event
)
784 struct arm_ccn
*ccn
= pmu_to_arm_ccn(event
->pmu
);
785 struct hw_perf_event
*hw
= &event
->hw
;
786 u64 prev_count
, new_count
, mask
;
789 prev_count
= local64_read(&hw
->prev_count
);
790 new_count
= arm_ccn_pmu_read_counter(ccn
, hw
->idx
);
791 } while (local64_xchg(&hw
->prev_count
, new_count
) != prev_count
);
793 mask
= (1LLU << (hw
->idx
== CCN_IDX_PMU_CYCLE_COUNTER
? 40 : 32)) - 1;
795 local64_add((new_count
- prev_count
) & mask
, &event
->count
);
798 static void arm_ccn_pmu_xp_dt_config(struct perf_event
*event
, int enable
)
800 struct arm_ccn
*ccn
= pmu_to_arm_ccn(event
->pmu
);
801 struct hw_perf_event
*hw
= &event
->hw
;
802 struct arm_ccn_component
*xp
;
805 if (CCN_CONFIG_TYPE(event
->attr
.config
) == CCN_TYPE_XP
)
806 xp
= &ccn
->xp
[CCN_CONFIG_XP(event
->attr
.config
)];
808 xp
= &ccn
->xp
[arm_ccn_node_to_xp(
809 CCN_CONFIG_NODE(event
->attr
.config
))];
812 dt_cfg
= hw
->event_base
;
814 dt_cfg
= CCN_XP_DT_CONFIG__DT_CFG__PASS_THROUGH
;
816 spin_lock(&ccn
->dt
.config_lock
);
818 val
= readl(xp
->base
+ CCN_XP_DT_CONFIG
);
819 val
&= ~(CCN_XP_DT_CONFIG__DT_CFG__MASK
<<
820 CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw
->idx
));
821 val
|= dt_cfg
<< CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw
->idx
);
822 writel(val
, xp
->base
+ CCN_XP_DT_CONFIG
);
824 spin_unlock(&ccn
->dt
.config_lock
);
827 static void arm_ccn_pmu_event_start(struct perf_event
*event
, int flags
)
829 struct arm_ccn
*ccn
= pmu_to_arm_ccn(event
->pmu
);
830 struct hw_perf_event
*hw
= &event
->hw
;
832 local64_set(&event
->hw
.prev_count
,
833 arm_ccn_pmu_read_counter(ccn
, hw
->idx
));
837 hrtimer_start(&ccn
->dt
.hrtimer
, arm_ccn_pmu_timer_period(),
840 /* Set the DT bus input, engaging the counter */
841 arm_ccn_pmu_xp_dt_config(event
, 1);
844 static void arm_ccn_pmu_event_stop(struct perf_event
*event
, int flags
)
846 struct arm_ccn
*ccn
= pmu_to_arm_ccn(event
->pmu
);
847 struct hw_perf_event
*hw
= &event
->hw
;
850 /* Disable counting, setting the DT bus to pass-through mode */
851 arm_ccn_pmu_xp_dt_config(event
, 0);
854 hrtimer_cancel(&ccn
->dt
.hrtimer
);
856 /* Let the DT bus drain */
857 timeout
= arm_ccn_pmu_read_counter(ccn
, CCN_IDX_PMU_CYCLE_COUNTER
) +
859 while (arm_ccn_pmu_read_counter(ccn
, CCN_IDX_PMU_CYCLE_COUNTER
) <
863 if (flags
& PERF_EF_UPDATE
)
864 arm_ccn_pmu_event_update(event
);
866 hw
->state
|= PERF_HES_STOPPED
;
869 static void arm_ccn_pmu_xp_watchpoint_config(struct perf_event
*event
)
871 struct arm_ccn
*ccn
= pmu_to_arm_ccn(event
->pmu
);
872 struct hw_perf_event
*hw
= &event
->hw
;
873 struct arm_ccn_component
*source
=
874 ccn
->dt
.pmu_counters
[hw
->idx
].source
;
875 unsigned long wp
= hw
->config_base
;
877 u64 cmp_l
= event
->attr
.config1
;
878 u64 cmp_h
= event
->attr
.config2
;
879 u64 mask_l
= ccn
->dt
.cmp_mask
[CCN_CONFIG_MASK(event
->attr
.config
)].l
;
880 u64 mask_h
= ccn
->dt
.cmp_mask
[CCN_CONFIG_MASK(event
->attr
.config
)].h
;
882 hw
->event_base
= CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(wp
);
884 /* Direction (RX/TX), device (port) & virtual channel */
885 val
= readl(source
->base
+ CCN_XP_DT_INTERFACE_SEL
);
886 val
&= ~(CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__MASK
<<
887 CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp
));
888 val
|= CCN_CONFIG_DIR(event
->attr
.config
) <<
889 CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp
);
890 val
&= ~(CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__MASK
<<
891 CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp
));
892 val
|= CCN_CONFIG_PORT(event
->attr
.config
) <<
893 CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp
);
894 val
&= ~(CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__MASK
<<
895 CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp
));
896 val
|= CCN_CONFIG_VC(event
->attr
.config
) <<
897 CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp
);
898 writel(val
, source
->base
+ CCN_XP_DT_INTERFACE_SEL
);
900 /* Comparison values */
901 writel(cmp_l
& 0xffffffff, source
->base
+ CCN_XP_DT_CMP_VAL_L(wp
));
902 writel((cmp_l
>> 32) & 0xefffffff,
903 source
->base
+ CCN_XP_DT_CMP_VAL_L(wp
) + 4);
904 writel(cmp_h
& 0xffffffff, source
->base
+ CCN_XP_DT_CMP_VAL_H(wp
));
905 writel((cmp_h
>> 32) & 0x0fffffff,
906 source
->base
+ CCN_XP_DT_CMP_VAL_H(wp
) + 4);
909 writel(mask_l
& 0xffffffff, source
->base
+ CCN_XP_DT_CMP_MASK_L(wp
));
910 writel((mask_l
>> 32) & 0xefffffff,
911 source
->base
+ CCN_XP_DT_CMP_MASK_L(wp
) + 4);
912 writel(mask_h
& 0xffffffff, source
->base
+ CCN_XP_DT_CMP_MASK_H(wp
));
913 writel((mask_h
>> 32) & 0x0fffffff,
914 source
->base
+ CCN_XP_DT_CMP_MASK_H(wp
) + 4);
917 static void arm_ccn_pmu_xp_event_config(struct perf_event
*event
)
919 struct arm_ccn
*ccn
= pmu_to_arm_ccn(event
->pmu
);
920 struct hw_perf_event
*hw
= &event
->hw
;
921 struct arm_ccn_component
*source
=
922 ccn
->dt
.pmu_counters
[hw
->idx
].source
;
925 hw
->event_base
= CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(hw
->config_base
);
927 id
= (CCN_CONFIG_VC(event
->attr
.config
) << 4) |
928 (CCN_CONFIG_PORT(event
->attr
.config
) << 3) |
929 (CCN_CONFIG_EVENT(event
->attr
.config
) << 0);
931 val
= readl(source
->base
+ CCN_XP_PMU_EVENT_SEL
);
932 val
&= ~(CCN_XP_PMU_EVENT_SEL__ID__MASK
<<
933 CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw
->config_base
));
934 val
|= id
<< CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw
->config_base
);
935 writel(val
, source
->base
+ CCN_XP_PMU_EVENT_SEL
);
938 static void arm_ccn_pmu_node_event_config(struct perf_event
*event
)
940 struct arm_ccn
*ccn
= pmu_to_arm_ccn(event
->pmu
);
941 struct hw_perf_event
*hw
= &event
->hw
;
942 struct arm_ccn_component
*source
=
943 ccn
->dt
.pmu_counters
[hw
->idx
].source
;
944 u32 type
= CCN_CONFIG_TYPE(event
->attr
.config
);
947 port
= arm_ccn_node_to_xp_port(CCN_CONFIG_NODE(event
->attr
.config
));
948 hw
->event_base
= CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(port
,
951 /* These *_event_sel regs should be identical, but let's make sure... */
952 BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL
!= CCN_SBAS_PMU_EVENT_SEL
);
953 BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL
!= CCN_RNI_PMU_EVENT_SEL
);
954 BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(1) !=
955 CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(1));
956 BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(1) !=
957 CCN_RNI_PMU_EVENT_SEL__ID__SHIFT(1));
958 BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL__ID__MASK
!=
959 CCN_SBAS_PMU_EVENT_SEL__ID__MASK
);
960 BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL__ID__MASK
!=
961 CCN_RNI_PMU_EVENT_SEL__ID__MASK
);
962 if (WARN_ON(type
!= CCN_TYPE_HNF
&& type
!= CCN_TYPE_SBAS
&&
963 !arm_ccn_pmu_type_eq(type
, CCN_TYPE_RNI_3P
)))
966 /* Set the event id for the pre-allocated counter */
967 val
= readl(source
->base
+ CCN_HNF_PMU_EVENT_SEL
);
968 val
&= ~(CCN_HNF_PMU_EVENT_SEL__ID__MASK
<<
969 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw
->config_base
));
970 val
|= CCN_CONFIG_EVENT(event
->attr
.config
) <<
971 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw
->config_base
);
972 writel(val
, source
->base
+ CCN_HNF_PMU_EVENT_SEL
);
975 static void arm_ccn_pmu_event_config(struct perf_event
*event
)
977 struct arm_ccn
*ccn
= pmu_to_arm_ccn(event
->pmu
);
978 struct hw_perf_event
*hw
= &event
->hw
;
981 /* Cycle counter requires no setup */
982 if (hw
->idx
== CCN_IDX_PMU_CYCLE_COUNTER
)
985 if (CCN_CONFIG_TYPE(event
->attr
.config
) == CCN_TYPE_XP
)
986 xp
= CCN_CONFIG_XP(event
->attr
.config
);
988 xp
= arm_ccn_node_to_xp(CCN_CONFIG_NODE(event
->attr
.config
));
990 spin_lock(&ccn
->dt
.config_lock
);
992 /* Set the DT bus "distance" register */
993 offset
= (hw
->idx
/ 4) * 4;
994 val
= readl(ccn
->dt
.base
+ CCN_DT_ACTIVE_DSM
+ offset
);
995 val
&= ~(CCN_DT_ACTIVE_DSM__DSM_ID__MASK
<<
996 CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw
->idx
% 4));
997 val
|= xp
<< CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw
->idx
% 4);
998 writel(val
, ccn
->dt
.base
+ CCN_DT_ACTIVE_DSM
+ offset
);
1000 if (CCN_CONFIG_TYPE(event
->attr
.config
) == CCN_TYPE_XP
) {
1001 if (CCN_CONFIG_EVENT(event
->attr
.config
) ==
1002 CCN_EVENT_WATCHPOINT
)
1003 arm_ccn_pmu_xp_watchpoint_config(event
);
1005 arm_ccn_pmu_xp_event_config(event
);
1007 arm_ccn_pmu_node_event_config(event
);
1010 spin_unlock(&ccn
->dt
.config_lock
);
1013 static int arm_ccn_pmu_event_add(struct perf_event
*event
, int flags
)
1015 struct hw_perf_event
*hw
= &event
->hw
;
1017 arm_ccn_pmu_event_config(event
);
1019 hw
->state
= PERF_HES_STOPPED
;
1021 if (flags
& PERF_EF_START
)
1022 arm_ccn_pmu_event_start(event
, PERF_EF_UPDATE
);
1027 static void arm_ccn_pmu_event_del(struct perf_event
*event
, int flags
)
1029 arm_ccn_pmu_event_stop(event
, PERF_EF_UPDATE
);
1031 arm_ccn_pmu_event_free(event
);
1034 static void arm_ccn_pmu_event_read(struct perf_event
*event
)
1036 arm_ccn_pmu_event_update(event
);
1039 static irqreturn_t
arm_ccn_pmu_overflow_handler(struct arm_ccn_dt
*dt
)
1041 u32 pmovsr
= readl(dt
->base
+ CCN_DT_PMOVSR
);
1047 writel(pmovsr
, dt
->base
+ CCN_DT_PMOVSR_CLR
);
1049 BUILD_BUG_ON(CCN_IDX_PMU_CYCLE_COUNTER
!= CCN_NUM_PMU_EVENT_COUNTERS
);
1051 for (idx
= 0; idx
< CCN_NUM_PMU_EVENT_COUNTERS
+ 1; idx
++) {
1052 struct perf_event
*event
= dt
->pmu_counters
[idx
].event
;
1053 int overflowed
= pmovsr
& BIT(idx
);
1055 WARN_ON_ONCE(overflowed
&& !event
);
1057 if (!event
|| !overflowed
)
1060 arm_ccn_pmu_event_update(event
);
1066 static enum hrtimer_restart
arm_ccn_pmu_timer_handler(struct hrtimer
*hrtimer
)
1068 struct arm_ccn_dt
*dt
= container_of(hrtimer
, struct arm_ccn_dt
,
1070 unsigned long flags
;
1072 local_irq_save(flags
);
1073 arm_ccn_pmu_overflow_handler(dt
);
1074 local_irq_restore(flags
);
1076 hrtimer_forward_now(hrtimer
, arm_ccn_pmu_timer_period());
1077 return HRTIMER_RESTART
;
1081 static DEFINE_IDA(arm_ccn_pmu_ida
);
1083 static int arm_ccn_pmu_init(struct arm_ccn
*ccn
)
1088 /* Initialize DT subsystem */
1089 ccn
->dt
.base
= ccn
->base
+ CCN_REGION_SIZE
;
1090 spin_lock_init(&ccn
->dt
.config_lock
);
1091 writel(CCN_DT_CTL__DT_EN
, ccn
->dt
.base
+ CCN_DT_CTL
);
1092 writel(CCN_DT_PMCR__OVFL_INTR_EN
| CCN_DT_PMCR__PMU_EN
,
1093 ccn
->dt
.base
+ CCN_DT_PMCR
);
1094 writel(0x1, ccn
->dt
.base
+ CCN_DT_PMSR_CLR
);
1095 for (i
= 0; i
< ccn
->num_xps
; i
++) {
1096 writel(0, ccn
->xp
[i
].base
+ CCN_XP_DT_CONFIG
);
1097 writel((CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS
<<
1098 CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(0)) |
1099 (CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS
<<
1100 CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(1)) |
1101 CCN_XP_DT_CONTROL__DT_ENABLE
,
1102 ccn
->xp
[i
].base
+ CCN_XP_DT_CONTROL
);
1104 ccn
->dt
.cmp_mask
[CCN_IDX_MASK_ANY
].l
= ~0;
1105 ccn
->dt
.cmp_mask
[CCN_IDX_MASK_ANY
].h
= ~0;
1106 ccn
->dt
.cmp_mask
[CCN_IDX_MASK_EXACT
].l
= 0;
1107 ccn
->dt
.cmp_mask
[CCN_IDX_MASK_EXACT
].h
= 0;
1108 ccn
->dt
.cmp_mask
[CCN_IDX_MASK_ORDER
].l
= ~0;
1109 ccn
->dt
.cmp_mask
[CCN_IDX_MASK_ORDER
].h
= ~(0x1 << 15);
1110 ccn
->dt
.cmp_mask
[CCN_IDX_MASK_OPCODE
].l
= ~0;
1111 ccn
->dt
.cmp_mask
[CCN_IDX_MASK_OPCODE
].h
= ~(0x1f << 9);
1113 /* Get a convenient /sys/event_source/devices/ name */
1114 ccn
->dt
.id
= ida_simple_get(&arm_ccn_pmu_ida
, 0, 0, GFP_KERNEL
);
1115 if (ccn
->dt
.id
== 0) {
1118 int len
= snprintf(NULL
, 0, "ccn_%d", ccn
->dt
.id
);
1120 name
= devm_kzalloc(ccn
->dev
, len
+ 1, GFP_KERNEL
);
1121 snprintf(name
, len
+ 1, "ccn_%d", ccn
->dt
.id
);
1124 /* Perf driver registration */
1125 ccn
->dt
.pmu
= (struct pmu
) {
1126 .attr_groups
= arm_ccn_pmu_attr_groups
,
1127 .task_ctx_nr
= perf_invalid_context
,
1128 .event_init
= arm_ccn_pmu_event_init
,
1129 .add
= arm_ccn_pmu_event_add
,
1130 .del
= arm_ccn_pmu_event_del
,
1131 .start
= arm_ccn_pmu_event_start
,
1132 .stop
= arm_ccn_pmu_event_stop
,
1133 .read
= arm_ccn_pmu_event_read
,
1136 /* No overflow interrupt? Have to use a timer instead. */
1137 if (!ccn
->irq_used
) {
1138 dev_info(ccn
->dev
, "No access to interrupts, using timer.\n");
1139 hrtimer_init(&ccn
->dt
.hrtimer
, CLOCK_MONOTONIC
,
1141 ccn
->dt
.hrtimer
.function
= arm_ccn_pmu_timer_handler
;
1144 return perf_pmu_register(&ccn
->dt
.pmu
, name
, -1);
1147 static void arm_ccn_pmu_cleanup(struct arm_ccn
*ccn
)
1151 for (i
= 0; i
< ccn
->num_xps
; i
++)
1152 writel(0, ccn
->xp
[i
].base
+ CCN_XP_DT_CONTROL
);
1153 writel(0, ccn
->dt
.base
+ CCN_DT_PMCR
);
1154 perf_pmu_unregister(&ccn
->dt
.pmu
);
1155 ida_simple_remove(&arm_ccn_pmu_ida
, ccn
->dt
.id
);
1159 static int arm_ccn_for_each_valid_region(struct arm_ccn
*ccn
,
1160 int (*callback
)(struct arm_ccn
*ccn
, int region
,
1161 void __iomem
*base
, u32 type
, u32 id
))
1165 for (region
= 0; region
< CCN_NUM_REGIONS
; region
++) {
1170 val
= readl(ccn
->base
+ CCN_MN_OLY_COMP_LIST_63_0
+
1172 if (!(val
& (1 << (region
% 32))))
1175 base
= ccn
->base
+ region
* CCN_REGION_SIZE
;
1176 val
= readl(base
+ CCN_ALL_OLY_ID
);
1177 type
= (val
>> CCN_ALL_OLY_ID__OLY_ID__SHIFT
) &
1178 CCN_ALL_OLY_ID__OLY_ID__MASK
;
1179 id
= (val
>> CCN_ALL_OLY_ID__NODE_ID__SHIFT
) &
1180 CCN_ALL_OLY_ID__NODE_ID__MASK
;
1182 err
= callback(ccn
, region
, base
, type
, id
);
1190 static int arm_ccn_get_nodes_num(struct arm_ccn
*ccn
, int region
,
1191 void __iomem
*base
, u32 type
, u32 id
)
1194 if (type
== CCN_TYPE_XP
&& id
>= ccn
->num_xps
)
1195 ccn
->num_xps
= id
+ 1;
1196 else if (id
>= ccn
->num_nodes
)
1197 ccn
->num_nodes
= id
+ 1;
1202 static int arm_ccn_init_nodes(struct arm_ccn
*ccn
, int region
,
1203 void __iomem
*base
, u32 type
, u32 id
)
1205 struct arm_ccn_component
*component
;
1207 dev_dbg(ccn
->dev
, "Region %d: id=%u, type=0x%02x\n", region
, id
, type
);
1214 component
= &ccn
->xp
[id
];
1217 ccn
->sbsx_present
= 1;
1218 component
= &ccn
->node
[id
];
1221 ccn
->sbas_present
= 1;
1224 component
= &ccn
->node
[id
];
1228 component
->base
= base
;
1229 component
->type
= type
;
1235 static irqreturn_t
arm_ccn_error_handler(struct arm_ccn
*ccn
,
1236 const u32
*err_sig_val
)
1238 /* This should be really handled by firmware... */
1239 dev_err(ccn
->dev
, "Error reported in %08x%08x%08x%08x%08x%08x.\n",
1240 err_sig_val
[5], err_sig_val
[4], err_sig_val
[3],
1241 err_sig_val
[2], err_sig_val
[1], err_sig_val
[0]);
1242 dev_err(ccn
->dev
, "Disabling interrupt generation for all errors.\n");
1243 writel(CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLE
,
1244 ccn
->base
+ CCN_MN_ERRINT_STATUS
);
1250 static irqreturn_t
arm_ccn_irq_handler(int irq
, void *dev_id
)
1252 irqreturn_t res
= IRQ_NONE
;
1253 struct arm_ccn
*ccn
= dev_id
;
1258 /* PMU overflow is a special case */
1259 err_or
= err_sig_val
[0] = readl(ccn
->base
+ CCN_MN_ERR_SIG_VAL_63_0
);
1260 if (err_or
& CCN_MN_ERR_SIG_VAL_63_0__DT
) {
1261 err_or
&= ~CCN_MN_ERR_SIG_VAL_63_0__DT
;
1262 res
= arm_ccn_pmu_overflow_handler(&ccn
->dt
);
1265 /* Have to read all err_sig_vals to clear them */
1266 for (i
= 1; i
< ARRAY_SIZE(err_sig_val
); i
++) {
1267 err_sig_val
[i
] = readl(ccn
->base
+
1268 CCN_MN_ERR_SIG_VAL_63_0
+ i
* 4);
1269 err_or
|= err_sig_val
[i
];
1272 res
|= arm_ccn_error_handler(ccn
, err_sig_val
);
1274 if (res
!= IRQ_NONE
)
1275 writel(CCN_MN_ERRINT_STATUS__INTREQ__DESSERT
,
1276 ccn
->base
+ CCN_MN_ERRINT_STATUS
);
1282 static int arm_ccn_probe(struct platform_device
*pdev
)
1284 struct arm_ccn
*ccn
;
1285 struct resource
*res
;
1288 ccn
= devm_kzalloc(&pdev
->dev
, sizeof(*ccn
), GFP_KERNEL
);
1291 ccn
->dev
= &pdev
->dev
;
1292 platform_set_drvdata(pdev
, ccn
);
1294 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1298 if (!devm_request_mem_region(ccn
->dev
, res
->start
,
1299 resource_size(res
), pdev
->name
))
1302 ccn
->base
= devm_ioremap(ccn
->dev
, res
->start
,
1303 resource_size(res
));
1307 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
1311 /* Check if we can use the interrupt */
1312 writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLE
,
1313 ccn
->base
+ CCN_MN_ERRINT_STATUS
);
1314 if (readl(ccn
->base
+ CCN_MN_ERRINT_STATUS
) &
1315 CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLED
) {
1316 /* Can set 'disable' bits, so can acknowledge interrupts */
1317 writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE
,
1318 ccn
->base
+ CCN_MN_ERRINT_STATUS
);
1319 err
= devm_request_irq(ccn
->dev
, res
->start
,
1320 arm_ccn_irq_handler
, 0, dev_name(ccn
->dev
),
1329 /* Build topology */
1331 err
= arm_ccn_for_each_valid_region(ccn
, arm_ccn_get_nodes_num
);
1335 ccn
->node
= devm_kzalloc(ccn
->dev
, sizeof(*ccn
->node
) * ccn
->num_nodes
,
1337 ccn
->xp
= devm_kzalloc(ccn
->dev
, sizeof(*ccn
->node
) * ccn
->num_xps
,
1339 if (!ccn
->node
|| !ccn
->xp
)
1342 err
= arm_ccn_for_each_valid_region(ccn
, arm_ccn_init_nodes
);
1346 return arm_ccn_pmu_init(ccn
);
1349 static int arm_ccn_remove(struct platform_device
*pdev
)
1351 struct arm_ccn
*ccn
= platform_get_drvdata(pdev
);
1353 arm_ccn_pmu_cleanup(ccn
);
1358 static const struct of_device_id arm_ccn_match
[] = {
1359 { .compatible
= "arm,ccn-504", },
1363 static struct platform_driver arm_ccn_driver
= {
1366 .of_match_table
= arm_ccn_match
,
1368 .probe
= arm_ccn_probe
,
1369 .remove
= arm_ccn_remove
,
1372 static int __init
arm_ccn_init(void)
1376 for (i
= 0; i
< ARRAY_SIZE(arm_ccn_pmu_events
); i
++)
1377 arm_ccn_pmu_events_attrs
[i
] = &arm_ccn_pmu_events
[i
].attr
.attr
;
1379 return platform_driver_register(&arm_ccn_driver
);
1382 static void __exit
arm_ccn_exit(void)
1384 platform_driver_unregister(&arm_ccn_driver
);
1387 module_init(arm_ccn_init
);
1388 module_exit(arm_ccn_exit
);
1390 MODULE_AUTHOR("Pawel Moll <pawel.moll@arm.com>");
1391 MODULE_LICENSE("GPL");