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Staging: et13x: kill off TXMAC_ERR_INT_t
[linux-2.6/btrfs-unstable.git] / drivers / staging / et131x / et1310_address_map.h
blobd599f312963ea5bbe6dbc85cba0696addab2ac0b
1 /*
2 * Agere Systems Inc.
3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
4 *
5 * Copyright © 2005 Agere Systems Inc.
6 * All rights reserved.
7 * http://www.agere.com
8 *
9 *------------------------------------------------------------------------------
10 *
11 * et1310_address_map.h - Contains the register mapping for the ET1310
12 *
13 *------------------------------------------------------------------------------
14 *
15 * SOFTWARE LICENSE
16 *
17 * This software is provided subject to the following terms and conditions,
18 * which you should read carefully before using the software. Using this
19 * software indicates your acceptance of these terms and conditions. If you do
20 * not agree with these terms and conditions, do not use the software.
21 *
22 * Copyright © 2005 Agere Systems Inc.
23 * All rights reserved.
24 *
25 * Redistribution and use in source or binary forms, with or without
26 * modifications, are permitted provided that the following conditions are met:
27 *
28 * . Redistributions of source code must retain the above copyright notice, this
29 * list of conditions and the following Disclaimer as comments in the code as
30 * well as in the documentation and/or other materials provided with the
31 * distribution.
32 *
33 * . Redistributions in binary form must reproduce the above copyright notice,
34 * this list of conditions and the following Disclaimer in the documentation
35 * and/or other materials provided with the distribution.
36 *
37 * . Neither the name of Agere Systems Inc. nor the names of the contributors
38 * may be used to endorse or promote products derived from this software
39 * without specific prior written permission.
40 *
41 * Disclaimer
42 *
43 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
44 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
45 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
46 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
47 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
48 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
49 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
50 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
51 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
53 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
54 * DAMAGE.
55 *
56 */
57
58 #ifndef _ET1310_ADDRESS_MAP_H_
59 #define _ET1310_ADDRESS_MAP_H_
60
61
62 /* START OF GLOBAL REGISTER ADDRESS MAP */
63
64 /*
65 * 10bit registers
66 *
67 * Tx queue start address reg in global address map at address 0x0000
68 * tx queue end address reg in global address map at address 0x0004
69 * rx queue start address reg in global address map at address 0x0008
70 * rx queue end address reg in global address map at address 0x000C
71 */
72
73 /*
74 * structure for power management control status reg in global address map
75 * located at address 0x0010
76 * jagcore_rx_rdy bit 9
77 * jagcore_tx_rdy bit 8
78 * phy_lped_en bit 7
79 * phy_sw_coma bit 6
80 * rxclk_gate bit 5
81 * txclk_gate bit 4
82 * sysclk_gate bit 3
83 * jagcore_rx_en bit 2
84 * jagcore_tx_en bit 1
85 * gigephy_en bit 0
86 */
87
88 #define ET_PM_PHY_SW_COMA 0x40
89 #define ET_PMCSR_INIT 0x38
90
91 /*
92 * Interrupt status reg at address 0x0018
93 */
94
95 #define ET_INTR_TXDMA_ISR 0x00000008
96 #define ET_INTR_TXDMA_ERR 0x00000010
97 #define ET_INTR_RXDMA_XFR_DONE 0x00000020
98 #define ET_INTR_RXDMA_FB_R0_LOW 0x00000040
99 #define ET_INTR_RXDMA_FB_R1_LOW 0x00000080
100 #define ET_INTR_RXDMA_STAT_LOW 0x00000100
101 #define ET_INTR_RXDMA_ERR 0x00000200
102 #define ET_INTR_WATCHDOG 0x00004000
103 #define ET_INTR_WOL 0x00008000
104 #define ET_INTR_PHY 0x00010000
105 #define ET_INTR_TXMAC 0x00020000
106 #define ET_INTR_RXMAC 0x00040000
107 #define ET_INTR_MAC_STAT 0x00080000
108 #define ET_INTR_SLV_TIMEOUT 0x00100000
109
110 /*
111 * Interrupt mask register at address 0x001C
112 * Interrupt alias clear mask reg at address 0x0020
113 * Interrupt status alias reg at address 0x0024
114 *
115 * Same masks as above
116 */
117
118 /*
119 * Software reset reg at address 0x0028
120 * 0: txdma_sw_reset
121 * 1: rxdma_sw_reset
122 * 2: txmac_sw_reset
123 * 3: rxmac_sw_reset
124 * 4: mac_sw_reset
125 * 5: mac_stat_sw_reset
126 * 6: mmc_sw_reset
127 *31: selfclr_disable
128 */
129
130 /*
131 * SLV Timer reg at address 0x002C (low 24 bits)
132 */
133
134 /*
135 * MSI Configuration reg at address 0x0030
136 */
137
138 #define ET_MSI_VECTOR 0x0000001F
139 #define ET_MSI_TC 0x00070000
140
141 /*
142 * Loopback reg located at address 0x0034
143 */
144
145 #define ET_LOOP_MAC 0x00000001
146 #define ET_LOOP_DMA 0x00000002
147
148 /*
149 * GLOBAL Module of JAGCore Address Mapping
150 * Located at address 0x0000
151 */
152 struct global_regs { /* Location: */
153 u32 txq_start_addr; /* 0x0000 */
154 u32 txq_end_addr; /* 0x0004 */
155 u32 rxq_start_addr; /* 0x0008 */
156 u32 rxq_end_addr; /* 0x000C */
157 u32 pm_csr; /* 0x0010 */
158 u32 unused; /* 0x0014 */
159 u32 int_status; /* 0x0018 */
160 u32 int_mask; /* 0x001C */
161 u32 int_alias_clr_en; /* 0x0020 */
162 u32 int_status_alias; /* 0x0024 */
163 u32 sw_reset; /* 0x0028 */
164 u32 slv_timer; /* 0x002C */
165 u32 msi_config; /* 0x0030 */
166 u32 loopback; /* 0x0034 */
167 u32 watchdog_timer; /* 0x0038 */
168 };
169
170
171 /* START OF TXDMA REGISTER ADDRESS MAP */
172
173 /*
174 * txdma control status reg at address 0x1000
175 */
176
177 #define ET_TXDMA_CSR_HALT 0x00000001
178 #define ET_TXDMA_DROP_TLP 0x00000002
179 #define ET_TXDMA_CACHE_THRS 0x000000F0
180 #define ET_TXDMA_CACHE_SHIFT 4
181 #define ET_TXDMA_SNGL_EPKT 0x00000100
182 #define ET_TXDMA_CLASS 0x00001E00
183
184 /*
185 * structure for txdma packet ring base address hi reg in txdma address map
186 * located at address 0x1004
187 * Defined earlier (u32)
188 */
189
190 /*
191 * structure for txdma packet ring base address low reg in txdma address map
192 * located at address 0x1008
193 * Defined earlier (u32)
194 */
195
196 /*
197 * structure for txdma packet ring number of descriptor reg in txdma address
198 * map. Located at address 0x100C
199 *
200 * 31-10: unused
201 * 9-0: pr ndes
202 */
203
204 #define ET_DMA12_MASK 0x0FFF /* 12 bit mask for DMA12W types */
205 #define ET_DMA12_WRAP 0x1000
206 #define ET_DMA10_MASK 0x03FF /* 10 bit mask for DMA10W types */
207 #define ET_DMA10_WRAP 0x0400
208 #define ET_DMA4_MASK 0x000F /* 4 bit mask for DMA4W types */
209 #define ET_DMA4_WRAP 0x0010
210
211 #define INDEX12(x) ((x) & ET_DMA12_MASK)
212 #define INDEX10(x) ((x) & ET_DMA10_MASK)
213 #define INDEX4(x) ((x) & ET_DMA4_MASK)
214
215 extern inline void add_10bit(u32 *v, int n)
216 {
217 *v = INDEX10(*v + n) | (*v & ET_DMA10_WRAP);
218 }
219
220 extern inline void add_12bit(u32 *v, int n)
221 {
222 *v = INDEX12(*v + n) | (*v & ET_DMA12_WRAP);
223 }
224
225 /*
226 * 10bit DMA with wrap
227 * txdma tx queue write address reg in txdma address map at 0x1010
228 * txdma tx queue write address external reg in txdma address map at 0x1014
229 * txdma tx queue read address reg in txdma address map at 0x1018
230 *
231 * u32
232 * txdma status writeback address hi reg in txdma address map at0x101C
233 * txdma status writeback address lo reg in txdma address map at 0x1020
234 *
235 * 10bit DMA with wrap
236 * txdma service request reg in txdma address map at 0x1024
237 * structure for txdma service complete reg in txdma address map at 0x1028
238 *
239 * 4bit DMA with wrap
240 * txdma tx descriptor cache read index reg in txdma address map at 0x102C
241 * txdma tx descriptor cache write index reg in txdma address map at 0x1030
242 *
243 * txdma error reg in txdma address map at address 0x1034
244 * 0: PyldResend
245 * 1: PyldRewind
246 * 4: DescrResend
247 * 5: DescrRewind
248 * 8: WrbkResend
249 * 9: WrbkRewind
250 */
251
252 /*
253 * Tx DMA Module of JAGCore Address Mapping
254 * Located at address 0x1000
255 */
256 struct txdma_regs { /* Location: */
257 u32 csr; /* 0x1000 */
258 u32 pr_base_hi; /* 0x1004 */
259 u32 pr_base_lo; /* 0x1008 */
260 u32 pr_num_des; /* 0x100C */
261 u32 txq_wr_addr; /* 0x1010 */
262 u32 txq_wr_addr_ext; /* 0x1014 */
263 u32 txq_rd_addr; /* 0x1018 */
264 u32 dma_wb_base_hi; /* 0x101C */
265 u32 dma_wb_base_lo; /* 0x1020 */
266 u32 service_request; /* 0x1024 */
267 u32 service_complete; /* 0x1028 */
268 u32 cache_rd_index; /* 0x102C */
269 u32 cache_wr_index; /* 0x1030 */
270 u32 TxDmaError; /* 0x1034 */
271 u32 DescAbortCount; /* 0x1038 */
272 u32 PayloadAbortCnt; /* 0x103c */
273 u32 WriteBackAbortCnt; /* 0x1040 */
274 u32 DescTimeoutCnt; /* 0x1044 */
275 u32 PayloadTimeoutCnt; /* 0x1048 */
276 u32 WriteBackTimeoutCnt; /* 0x104c */
277 u32 DescErrorCount; /* 0x1050 */
278 u32 PayloadErrorCnt; /* 0x1054 */
279 u32 WriteBackErrorCnt; /* 0x1058 */
280 u32 DroppedTLPCount; /* 0x105c */
281 u32 NewServiceComplete; /* 0x1060 */
282 u32 EthernetPacketCount; /* 0x1064 */
283 };
284
285 /* END OF TXDMA REGISTER ADDRESS MAP */
286
287
288 /* START OF RXDMA REGISTER ADDRESS MAP */
289
290 /*
291 * structure for control status reg in rxdma address map
292 * Located at address 0x2000
293 *
294 * CSR
295 * 0: halt
296 * 1-3: tc
297 * 4: fbr_big_endian
298 * 5: psr_big_endian
299 * 6: pkt_big_endian
300 * 7: dma_big_endian
301 * 8-9: fbr0_size
302 * 10: fbr0_enable
303 * 11-12: fbr1_size
304 * 13: fbr1_enable
305 * 14: unused
306 * 15: pkt_drop_disable
307 * 16: pkt_done_flush
308 * 17: halt_status
309 * 18-31: unused
310 */
311
312
313 /*
314 * structure for dma writeback lo reg in rxdma address map
315 * located at address 0x2004
316 * Defined earlier (u32)
317 */
318
319 /*
320 * structure for dma writeback hi reg in rxdma address map
321 * located at address 0x2008
322 * Defined earlier (u32)
323 */
324
325 /*
326 * structure for number of packets done reg in rxdma address map
327 * located at address 0x200C
328 *
329 * 31-8: unused
330 * 7-0: num done
331 */
332
333 /*
334 * structure for max packet time reg in rxdma address map
335 * located at address 0x2010
336 *
337 * 31-18: unused
338 * 17-0: time done
339 */
340
341 /*
342 * structure for rx queue read address reg in rxdma address map
343 * located at address 0x2014
344 * Defined earlier (u32)
345 */
346
347 /*
348 * structure for rx queue read address external reg in rxdma address map
349 * located at address 0x2018
350 * Defined earlier (u32)
351 */
352
353 /*
354 * structure for rx queue write address reg in rxdma address map
355 * located at address 0x201C
356 * Defined earlier (u32)
357 */
358
359 /*
360 * structure for packet status ring base address lo reg in rxdma address map
361 * located at address 0x2020
362 * Defined earlier (u32)
363 */
364
365 /*
366 * structure for packet status ring base address hi reg in rxdma address map
367 * located at address 0x2024
368 * Defined earlier (u32)
369 */
370
371 /*
372 * structure for packet status ring number of descriptors reg in rxdma address
373 * map. Located at address 0x2028
374 *
375 * 31-12: unused
376 * 11-0: psr ndes
377 */
378
379 /*
380 * structure for packet status ring available offset reg in rxdma address map
381 * located at address 0x202C
382 *
383 * 31-13: unused
384 * 12: psr avail wrap
385 * 11-0: psr avail
386 */
387
388 /*
389 * structure for packet status ring full offset reg in rxdma address map
390 * located at address 0x2030
391 *
392 * 31-13: unused
393 * 12: psr full wrap
394 * 11-0: psr full
395 */
396
397 /*
398 * structure for packet status ring access index reg in rxdma address map
399 * located at address 0x2034
400 *
401 * 31-5: unused
402 * 4-0: psr_ai
403 */
404
405 /*
406 * structure for packet status ring minimum descriptors reg in rxdma address
407 * map. Located at address 0x2038
408 *
409 * 31-12: unused
410 * 11-0: psr_min
411 */
412
413 /*
414 * structure for free buffer ring base lo address reg in rxdma address map
415 * located at address 0x203C
416 * Defined earlier (u32)
417 */
418
419 /*
420 * structure for free buffer ring base hi address reg in rxdma address map
421 * located at address 0x2040
422 * Defined earlier (u32)
423 */
424
425 /*
426 * structure for free buffer ring number of descriptors reg in rxdma address
427 * map. Located at address 0x2044
428 *
429 * 31-10: unused
430 * 9-0: fbr ndesc
431 */
432
433 /*
434 * structure for free buffer ring 0 available offset reg in rxdma address map
435 * located at address 0x2048
436 * Defined earlier (u32)
437 */
438
439 /*
440 * structure for free buffer ring 0 full offset reg in rxdma address map
441 * located at address 0x204C
442 * Defined earlier (u32)
443 */
444
445 /*
446 * structure for free buffer cache 0 full offset reg in rxdma address map
447 * located at address 0x2050
448 *
449 * 31-5: unused
450 * 4-0: fbc rdi
451 */
452
453 /*
454 * structure for free buffer ring 0 minimum descriptor reg in rxdma address map
455 * located at address 0x2054
456 *
457 * 31-10: unused
458 * 9-0: fbr min
459 */
460
461 /*
462 * structure for free buffer ring 1 base address lo reg in rxdma address map
463 * located at address 0x2058 - 0x205C
464 * Defined earlier (RXDMA_FBR_BASE_LO_t and RXDMA_FBR_BASE_HI_t)
465 */
466
467 /*
468 * structure for free buffer ring 1 number of descriptors reg in rxdma address
469 * map. Located at address 0x2060
470 * Defined earlier (RXDMA_FBR_NUM_DES_t)
471 */
472
473 /*
474 * structure for free buffer ring 1 available offset reg in rxdma address map
475 * located at address 0x2064
476 * Defined Earlier (RXDMA_FBR_AVAIL_OFFSET_t)
477 */
478
479 /*
480 * structure for free buffer ring 1 full offset reg in rxdma address map
481 * located at address 0x2068
482 * Defined Earlier (RXDMA_FBR_FULL_OFFSET_t)
483 */
484
485 /*
486 * structure for free buffer cache 1 read index reg in rxdma address map
487 * located at address 0x206C
488 * Defined Earlier (RXDMA_FBC_RD_INDEX_t)
489 */
490
491 /*
492 * structure for free buffer ring 1 minimum descriptor reg in rxdma address map
493 * located at address 0x2070
494 * Defined Earlier (RXDMA_FBR_MIN_DES_t)
495 */
496
497 /*
498 * Rx DMA Module of JAGCore Address Mapping
499 * Located at address 0x2000
500 */
501 struct rxdma_regs { /* Location: */
502 u32 csr; /* 0x2000 */
503 u32 dma_wb_base_lo; /* 0x2004 */
504 u32 dma_wb_base_hi; /* 0x2008 */
505 u32 num_pkt_done; /* 0x200C */
506 u32 max_pkt_time; /* 0x2010 */
507 u32 rxq_rd_addr; /* 0x2014 */
508 u32 rxq_rd_addr_ext; /* 0x2018 */
509 u32 rxq_wr_addr; /* 0x201C */
510 u32 psr_base_lo; /* 0x2020 */
511 u32 psr_base_hi; /* 0x2024 */
512 u32 psr_num_des; /* 0x2028 */
513 u32 psr_avail_offset; /* 0x202C */
514 u32 psr_full_offset; /* 0x2030 */
515 u32 psr_access_index; /* 0x2034 */
516 u32 psr_min_des; /* 0x2038 */
517 u32 fbr0_base_lo; /* 0x203C */
518 u32 fbr0_base_hi; /* 0x2040 */
519 u32 fbr0_num_des; /* 0x2044 */
520 u32 fbr0_avail_offset; /* 0x2048 */
521 u32 fbr0_full_offset; /* 0x204C */
522 u32 fbr0_rd_index; /* 0x2050 */
523 u32 fbr0_min_des; /* 0x2054 */
524 u32 fbr1_base_lo; /* 0x2058 */
525 u32 fbr1_base_hi; /* 0x205C */
526 u32 fbr1_num_des; /* 0x2060 */
527 u32 fbr1_avail_offset; /* 0x2064 */
528 u32 fbr1_full_offset; /* 0x2068 */
529 u32 fbr1_rd_index; /* 0x206C */
530 u32 fbr1_min_des; /* 0x2070 */
531 };
532
533 /* END OF RXDMA REGISTER ADDRESS MAP */
534
535
536 /* START OF TXMAC REGISTER ADDRESS MAP */
537
538 /*
539 * structure for control reg in txmac address map
540 * located at address 0x3000
541 *
542 * bits
543 * 31-8: unused
544 * 7: cklseg_disable
545 * 6: ckbcnt_disable
546 * 5: cksegnum
547 * 4: async_disable
548 * 3: fc_disable
549 * 2: mcif_disable
550 * 1: mif_disable
551 * 0: txmac_en
552 */
553
554 /*
555 * structure for shadow pointer reg in txmac address map
556 * located at address 0x3004
557 * 31-27: reserved
558 * 26-16: txq rd ptr
559 * 15-11: reserved
560 * 10-0: txq wr ptr
561 */
562
563 /*
564 * structure for error count reg in txmac address map
565 * located at address 0x3008
566 *
567 * 31-12: unused
568 * 11-8: reserved
569 * 7-4: txq_underrun
570 * 3-0: fifo_underrun
571 */
572
573 /*
574 * structure for max fill reg in txmac address map
575 * located at address 0x300C
576 * 31-12: unused
577 * 11-0: max fill
578 */
579
580 /*
581 * structure for cf parameter reg in txmac address map
582 * located at address 0x3010
583 * 31-16: cfep
584 * 15-0: cfpt
585 */
586
587 /*
588 * structure for tx test reg in txmac address map
589 * located at address 0x3014
590 * 31-17: unused
591 * 16: reserved1
592 * 15: txtest_en
593 * 14-11: unused
594 * 10-0: txq test pointer
595 */
596
597 /*
598 * structure for error reg in txmac address map
599 * located at address 0x3018
600 *
601 * 31-9: unused
602 * 8: fifo_underrun
603 * 7-6: unused
604 * 5: ctrl2_err
605 * 4: txq_underrun
606 * 3: bcnt_err
607 * 2: lseg_err
608 * 1: segnum_err
609 * 0: seg0_err
610 */
611
612 /*
613 * structure for error interrupt reg in txmac address map
614 * located at address 0x301C
615 *
616 * 31-9: unused
617 * 8: fifo_underrun
618 * 7-6: unused
619 * 5: ctrl2_err
620 * 4: txq_underrun
621 * 3: bcnt_err
622 * 2: lseg_err
623 * 1: segnum_err
624 * 0: seg0_err
625 */
626
627 /*
628 * structure for error interrupt reg in txmac address map
629 * located at address 0x3020
630 *
631 * 31-2: unused
632 * 1: bp_req
633 * 0: bp_xonxoff
634 */
635
636 /*
637 * Tx MAC Module of JAGCore Address Mapping
638 */
639 struct txmac_regs { /* Location: */
640 u32 ctl; /* 0x3000 */
641 u32 shadow_ptr; /* 0x3004 */
642 u32 err_cnt; /* 0x3008 */
643 u32 max_fill; /* 0x300C */
644 u32 cf_param; /* 0x3010 */
645 u32 tx_test; /* 0x3014 */
646 u32 err; /* 0x3018 */
647 u32 err_int; /* 0x301C */
648 u32 bp_ctrl; /* 0x3020 */
649 };
650
651 /* END OF TXMAC REGISTER ADDRESS MAP */
652
653 /* START OF RXMAC REGISTER ADDRESS MAP */
654
655 /*
656 * structure for rxmac control reg in rxmac address map
657 * located at address 0x4000
658 */
659 typedef union _RXMAC_CTRL_t {
660 u32 value;
661 struct {
662 #ifdef _BIT_FIELDS_HTOL
663 u32 reserved:25; /* bits 7-31 */
664 u32 rxmac_int_disable:1; /* bit 6 */
665 u32 async_disable:1; /* bit 5 */
666 u32 mif_disable:1; /* bit 4 */
667 u32 wol_disable:1; /* bit 3 */
668 u32 pkt_filter_disable:1; /* bit 2 */
669 u32 mcif_disable:1; /* bit 1 */
670 u32 rxmac_en:1; /* bit 0 */
671 #else
672 u32 rxmac_en:1; /* bit 0 */
673 u32 mcif_disable:1; /* bit 1 */
674 u32 pkt_filter_disable:1; /* bit 2 */
675 u32 wol_disable:1; /* bit 3 */
676 u32 mif_disable:1; /* bit 4 */
677 u32 async_disable:1; /* bit 5 */
678 u32 rxmac_int_disable:1; /* bit 6 */
679 u32 reserved:25; /* bits 7-31 */
680 #endif
681 } bits;
682 } RXMAC_CTRL_t, *PRXMAC_CTRL_t;
683
684 /*
685 * structure for Wake On Lan Control and CRC 0 reg in rxmac address map
686 * located at address 0x4004
687 */
688 typedef union _RXMAC_WOL_CTL_CRC0_t {
689 u32 value;
690 struct {
691 #ifdef _BIT_FIELDS_HTOL
692 u32 crc0:16; /* bits 16-31 */
693 u32 reserve:4; /* bits 12-15 */
694 u32 ignore_pp:1; /* bit 11 */
695 u32 ignore_mp:1; /* bit 10 */
696 u32 clr_intr:1; /* bit 9 */
697 u32 ignore_link_chg:1; /* bit 8 */
698 u32 ignore_uni:1; /* bit 7 */
699 u32 ignore_multi:1; /* bit 6 */
700 u32 ignore_broad:1; /* bit 5 */
701 u32 valid_crc4:1; /* bit 4 */
702 u32 valid_crc3:1; /* bit 3 */
703 u32 valid_crc2:1; /* bit 2 */
704 u32 valid_crc1:1; /* bit 1 */
705 u32 valid_crc0:1; /* bit 0 */
706 #else
707 u32 valid_crc0:1; /* bit 0 */
708 u32 valid_crc1:1; /* bit 1 */
709 u32 valid_crc2:1; /* bit 2 */
710 u32 valid_crc3:1; /* bit 3 */
711 u32 valid_crc4:1; /* bit 4 */
712 u32 ignore_broad:1; /* bit 5 */
713 u32 ignore_multi:1; /* bit 6 */
714 u32 ignore_uni:1; /* bit 7 */
715 u32 ignore_link_chg:1; /* bit 8 */
716 u32 clr_intr:1; /* bit 9 */
717 u32 ignore_mp:1; /* bit 10 */
718 u32 ignore_pp:1; /* bit 11 */
719 u32 reserve:4; /* bits 12-15 */
720 u32 crc0:16; /* bits 16-31 */
721 #endif
722 } bits;
723 } RXMAC_WOL_CTL_CRC0_t, *PRXMAC_WOL_CTL_CRC0_t;
724
725 /*
726 * structure for CRC 1 and CRC 2 reg in rxmac address map
727 * located at address 0x4008
728 */
729 typedef union _RXMAC_WOL_CRC12_t {
730 u32 value;
731 struct {
732 #ifdef _BIT_FIELDS_HTOL
733 u32 crc2:16; /* bits 16-31 */
734 u32 crc1:16; /* bits 0-15 */
735 #else
736 u32 crc1:16; /* bits 0-15 */
737 u32 crc2:16; /* bits 16-31 */
738 #endif
739 } bits;
740 } RXMAC_WOL_CRC12_t, *PRXMAC_WOL_CRC12_t;
741
742 /*
743 * structure for CRC 3 and CRC 4 reg in rxmac address map
744 * located at address 0x400C
745 */
746 typedef union _RXMAC_WOL_CRC34_t {
747 u32 value;
748 struct {
749 #ifdef _BIT_FIELDS_HTOL
750 u32 crc4:16; /* bits 16-31 */
751 u32 crc3:16; /* bits 0-15 */
752 #else
753 u32 crc3:16; /* bits 0-15 */
754 u32 crc4:16; /* bits 16-31 */
755 #endif
756 } bits;
757 } RXMAC_WOL_CRC34_t, *PRXMAC_WOL_CRC34_t;
758
759 /*
760 * structure for Wake On Lan Source Address Lo reg in rxmac address map
761 * located at address 0x4010
762 */
763 typedef union _RXMAC_WOL_SA_LO_t {
764 u32 value;
765 struct {
766 #ifdef _BIT_FIELDS_HTOL
767 u32 sa3:8; /* bits 24-31 */
768 u32 sa4:8; /* bits 16-23 */
769 u32 sa5:8; /* bits 8-15 */
770 u32 sa6:8; /* bits 0-7 */
771 #else
772 u32 sa6:8; /* bits 0-7 */
773 u32 sa5:8; /* bits 8-15 */
774 u32 sa4:8; /* bits 16-23 */
775 u32 sa3:8; /* bits 24-31 */
776 #endif
777 } bits;
778 } RXMAC_WOL_SA_LO_t, *PRXMAC_WOL_SA_LO_t;
779
780 /*
781 * structure for Wake On Lan Source Address Hi reg in rxmac address map
782 * located at address 0x4014
783 */
784 typedef union _RXMAC_WOL_SA_HI_t {
785 u32 value;
786 struct {
787 #ifdef _BIT_FIELDS_HTOL
788 u32 reserved:16; /* bits 16-31 */
789 u32 sa1:8; /* bits 8-15 */
790 u32 sa2:8; /* bits 0-7 */
791 #else
792 u32 sa2:8; /* bits 0-7 */
793 u32 sa1:8; /* bits 8-15 */
794 u32 reserved:16; /* bits 16-31 */
795 #endif
796 } bits;
797 } RXMAC_WOL_SA_HI_t, *PRXMAC_WOL_SA_HI_t;
798
799 /*
800 * structure for Wake On Lan mask reg in rxmac address map
801 * located at address 0x4018 - 0x4064
802 * Defined earlier (u32)
803 */
804
805 /*
806 * structure for Unicast Paket Filter Address 1 reg in rxmac address map
807 * located at address 0x4068
808 */
809 typedef union _RXMAC_UNI_PF_ADDR1_t {
810 u32 value;
811 struct {
812 #ifdef _BIT_FIELDS_HTOL
813 u32 addr1_3:8; /* bits 24-31 */
814 u32 addr1_4:8; /* bits 16-23 */
815 u32 addr1_5:8; /* bits 8-15 */
816 u32 addr1_6:8; /* bits 0-7 */
817 #else
818 u32 addr1_6:8; /* bits 0-7 */
819 u32 addr1_5:8; /* bits 8-15 */
820 u32 addr1_4:8; /* bits 16-23 */
821 u32 addr1_3:8; /* bits 24-31 */
822 #endif
823 } bits;
824 } RXMAC_UNI_PF_ADDR1_t, *PRXMAC_UNI_PF_ADDR1_t;
825
826 /*
827 * structure for Unicast Paket Filter Address 2 reg in rxmac address map
828 * located at address 0x406C
829 */
830 typedef union _RXMAC_UNI_PF_ADDR2_t {
831 u32 value;
832 struct {
833 #ifdef _BIT_FIELDS_HTOL
834 u32 addr2_3:8; /* bits 24-31 */
835 u32 addr2_4:8; /* bits 16-23 */
836 u32 addr2_5:8; /* bits 8-15 */
837 u32 addr2_6:8; /* bits 0-7 */
838 #else
839 u32 addr2_6:8; /* bits 0-7 */
840 u32 addr2_5:8; /* bits 8-15 */
841 u32 addr2_4:8; /* bits 16-23 */
842 u32 addr2_3:8; /* bits 24-31 */
843 #endif
844 } bits;
845 } RXMAC_UNI_PF_ADDR2_t, *PRXMAC_UNI_PF_ADDR2_t;
846
847 /*
848 * structure for Unicast Paket Filter Address 1 & 2 reg in rxmac address map
849 * located at address 0x4070
850 */
851 typedef union _RXMAC_UNI_PF_ADDR3_t {
852 u32 value;
853 struct {
854 #ifdef _BIT_FIELDS_HTOL
855 u32 addr2_1:8; /* bits 24-31 */
856 u32 addr2_2:8; /* bits 16-23 */
857 u32 addr1_1:8; /* bits 8-15 */
858 u32 addr1_2:8; /* bits 0-7 */
859 #else
860 u32 addr1_2:8; /* bits 0-7 */
861 u32 addr1_1:8; /* bits 8-15 */
862 u32 addr2_2:8; /* bits 16-23 */
863 u32 addr2_1:8; /* bits 24-31 */
864 #endif
865 } bits;
866 } RXMAC_UNI_PF_ADDR3_t, *PRXMAC_UNI_PF_ADDR3_t;
867
868 /*
869 * structure for Multicast Hash reg in rxmac address map
870 * located at address 0x4074 - 0x4080
871 * Defined earlier (u32)
872 */
873
874 /*
875 * structure for Packet Filter Control reg in rxmac address map
876 * located at address 0x4084
877 */
878 typedef union _RXMAC_PF_CTRL_t {
879 u32 value;
880 struct {
881 #ifdef _BIT_FIELDS_HTOL
882 u32 unused2:9; /* bits 23-31 */
883 u32 min_pkt_size:7; /* bits 16-22 */
884 u32 unused1:12; /* bits 4-15 */
885 u32 filter_frag_en:1; /* bit 3 */
886 u32 filter_uni_en:1; /* bit 2 */
887 u32 filter_multi_en:1; /* bit 1 */
888 u32 filter_broad_en:1; /* bit 0 */
889 #else
890 u32 filter_broad_en:1; /* bit 0 */
891 u32 filter_multi_en:1; /* bit 1 */
892 u32 filter_uni_en:1; /* bit 2 */
893 u32 filter_frag_en:1; /* bit 3 */
894 u32 unused1:12; /* bits 4-15 */
895 u32 min_pkt_size:7; /* bits 16-22 */
896 u32 unused2:9; /* bits 23-31 */
897 #endif
898 } bits;
899 } RXMAC_PF_CTRL_t, *PRXMAC_PF_CTRL_t;
900
901 /*
902 * structure for Memory Controller Interface Control Max Segment reg in rxmac
903 * address map. Located at address 0x4088
904 */
905 typedef union _RXMAC_MCIF_CTRL_MAX_SEG_t {
906 u32 value;
907 struct {
908 #ifdef _BIT_FIELDS_HTOL
909 u32 reserved:22; /* bits 10-31 */
910 u32 max_size:8; /* bits 2-9 */
911 u32 fc_en:1; /* bit 1 */
912 u32 seg_en:1; /* bit 0 */
913 #else
914 u32 seg_en:1; /* bit 0 */
915 u32 fc_en:1; /* bit 1 */
916 u32 max_size:8; /* bits 2-9 */
917 u32 reserved:22; /* bits 10-31 */
918 #endif
919 } bits;
920 } RXMAC_MCIF_CTRL_MAX_SEG_t, *PRXMAC_MCIF_CTRL_MAX_SEG_t;
921
922 /*
923 * structure for Memory Controller Interface Water Mark reg in rxmac address
924 * map. Located at address 0x408C
925 */
926 typedef union _RXMAC_MCIF_WATER_MARK_t {
927 u32 value;
928 struct {
929 #ifdef _BIT_FIELDS_HTOL
930 u32 reserved2:6; /* bits 26-31 */
931 u32 mark_hi:10; /* bits 16-25 */
932 u32 reserved1:6; /* bits 10-15 */
933 u32 mark_lo:10; /* bits 0-9 */
934 #else
935 u32 mark_lo:10; /* bits 0-9 */
936 u32 reserved1:6; /* bits 10-15 */
937 u32 mark_hi:10; /* bits 16-25 */
938 u32 reserved2:6; /* bits 26-31 */
939 #endif
940 } bits;
941 } RXMAC_MCIF_WATER_MARK_t, *PRXMAC_MCIF_WATER_MARK_t;
942
943 /*
944 * structure for Rx Queue Dialog reg in rxmac address map.
945 * located at address 0x4090
946 */
947 typedef union _RXMAC_RXQ_DIAG_t {
948 u32 value;
949 struct {
950 #ifdef _BIT_FIELDS_HTOL
951 u32 reserved2:6; /* bits 26-31 */
952 u32 rd_ptr:10; /* bits 16-25 */
953 u32 reserved1:6; /* bits 10-15 */
954 u32 wr_ptr:10; /* bits 0-9 */
955 #else
956 u32 wr_ptr:10; /* bits 0-9 */
957 u32 reserved1:6; /* bits 10-15 */
958 u32 rd_ptr:10; /* bits 16-25 */
959 u32 reserved2:6; /* bits 26-31 */
960 #endif
961 } bits;
962 } RXMAC_RXQ_DIAG_t, *PRXMAC_RXQ_DIAG_t;
963
964 /*
965 * structure for space availiable reg in rxmac address map.
966 * located at address 0x4094
967 */
968 typedef union _RXMAC_SPACE_AVAIL_t {
969 u32 value;
970 struct {
971 #ifdef _BIT_FIELDS_HTOL
972 u32 reserved2:15; /* bits 17-31 */
973 u32 space_avail_en:1; /* bit 16 */
974 u32 reserved1:6; /* bits 10-15 */
975 u32 space_avail:10; /* bits 0-9 */
976 #else
977 u32 space_avail:10; /* bits 0-9 */
978 u32 reserved1:6; /* bits 10-15 */
979 u32 space_avail_en:1; /* bit 16 */
980 u32 reserved2:15; /* bits 17-31 */
981 #endif
982 } bits;
983 } RXMAC_SPACE_AVAIL_t, *PRXMAC_SPACE_AVAIL_t;
984
985 /*
986 * structure for management interface reg in rxmac address map.
987 * located at address 0x4098
988 */
989 typedef union _RXMAC_MIF_CTL_t {
990 u32 value;
991 struct {
992 #ifdef _BIT_FIELDS_HTOL
993 u32 reserve:14; /* bits 18-31 */
994 u32 drop_pkt_en:1; /* bit 17 */
995 u32 drop_pkt_mask:17; /* bits 0-16 */
996 #else
997 u32 drop_pkt_mask:17; /* bits 0-16 */
998 u32 drop_pkt_en:1; /* bit 17 */
999 u32 reserve:14; /* bits 18-31 */
1000 #endif
1001 } bits;
1002 } RXMAC_MIF_CTL_t, *PRXMAC_MIF_CTL_t;
1003
1004 /*
1005 * structure for Error reg in rxmac address map.
1006 * located at address 0x409C
1007 */
1008 typedef union _RXMAC_ERROR_REG_t {
1009 u32 value;
1010 struct {
1011 #ifdef _BIT_FIELDS_HTOL
1012 u32 reserve:28; /* bits 4-31 */
1013 u32 mif:1; /* bit 3 */
1014 u32 async:1; /* bit 2 */
1015 u32 pkt_filter:1; /* bit 1 */
1016 u32 mcif:1; /* bit 0 */
1017 #else
1018 u32 mcif:1; /* bit 0 */
1019 u32 pkt_filter:1; /* bit 1 */
1020 u32 async:1; /* bit 2 */
1021 u32 mif:1; /* bit 3 */
1022 u32 reserve:28; /* bits 4-31 */
1023 #endif
1024 } bits;
1025 } RXMAC_ERROR_REG_t, *PRXMAC_ERROR_REG_t;
1026
1027 /*
1028 * Rx MAC Module of JAGCore Address Mapping
1029 */
1030 typedef struct _RXMAC_t { /* Location: */
1031 RXMAC_CTRL_t ctrl; /* 0x4000 */
1032 RXMAC_WOL_CTL_CRC0_t crc0; /* 0x4004 */
1033 RXMAC_WOL_CRC12_t crc12; /* 0x4008 */
1034 RXMAC_WOL_CRC34_t crc34; /* 0x400C */
1035 RXMAC_WOL_SA_LO_t sa_lo; /* 0x4010 */
1036 RXMAC_WOL_SA_HI_t sa_hi; /* 0x4014 */
1037 u32 mask0_word0; /* 0x4018 */
1038 u32 mask0_word1; /* 0x401C */
1039 u32 mask0_word2; /* 0x4020 */
1040 u32 mask0_word3; /* 0x4024 */
1041 u32 mask1_word0; /* 0x4028 */
1042 u32 mask1_word1; /* 0x402C */
1043 u32 mask1_word2; /* 0x4030 */
1044 u32 mask1_word3; /* 0x4034 */
1045 u32 mask2_word0; /* 0x4038 */
1046 u32 mask2_word1; /* 0x403C */
1047 u32 mask2_word2; /* 0x4040 */
1048 u32 mask2_word3; /* 0x4044 */
1049 u32 mask3_word0; /* 0x4048 */
1050 u32 mask3_word1; /* 0x404C */
1051 u32 mask3_word2; /* 0x4050 */
1052 u32 mask3_word3; /* 0x4054 */
1053 u32 mask4_word0; /* 0x4058 */
1054 u32 mask4_word1; /* 0x405C */
1055 u32 mask4_word2; /* 0x4060 */
1056 u32 mask4_word3; /* 0x4064 */
1057 RXMAC_UNI_PF_ADDR1_t uni_pf_addr1; /* 0x4068 */
1058 RXMAC_UNI_PF_ADDR2_t uni_pf_addr2; /* 0x406C */
1059 RXMAC_UNI_PF_ADDR3_t uni_pf_addr3; /* 0x4070 */
1060 u32 multi_hash1; /* 0x4074 */
1061 u32 multi_hash2; /* 0x4078 */
1062 u32 multi_hash3; /* 0x407C */
1063 u32 multi_hash4; /* 0x4080 */
1064 RXMAC_PF_CTRL_t pf_ctrl; /* 0x4084 */
1065 RXMAC_MCIF_CTRL_MAX_SEG_t mcif_ctrl_max_seg; /* 0x4088 */
1066 RXMAC_MCIF_WATER_MARK_t mcif_water_mark; /* 0x408C */
1067 RXMAC_RXQ_DIAG_t rxq_diag; /* 0x4090 */
1068 RXMAC_SPACE_AVAIL_t space_avail; /* 0x4094 */
1069
1070 RXMAC_MIF_CTL_t mif_ctrl; /* 0x4098 */
1071 RXMAC_ERROR_REG_t err_reg; /* 0x409C */
1072 } RXMAC_t, *PRXMAC_t;
1073
1074 /* END OF RXMAC REGISTER ADDRESS MAP */
1075
1076
1077 /* START OF MAC REGISTER ADDRESS MAP */
1078
1079 /*
1080 * structure for configuration #1 reg in mac address map.
1081 * located at address 0x5000
1082 *
1083 * 31: soft reset
1084 * 30: sim reset
1085 * 29-20: reserved
1086 * 19: reset rx mc
1087 * 18: reset tx mc
1088 * 17: reset rx func
1089 * 16: reset tx fnc
1090 * 15-9: reserved
1091 * 8: loopback
1092 * 7-6: reserved
1093 * 5: rx flow
1094 * 4: tx flow
1095 * 3: syncd rx en
1096 * 2: rx enable
1097 * 1: syncd tx en
1098 * 0: tx enable
1099 */
1100
1101 #define CFG1_LOOPBACK 0x00000100
1102 #define CFG1_RX_FLOW 0x00000020
1103 #define CFG1_TX_FLOW 0x00000010
1104 #define CFG1_RX_ENABLE 0x00000004
1105 #define CFG1_TX_ENABLE 0x00000001
1106 #define CFG1_WAIT 0x0000000A /* RX & TX syncd */
1107
1108 /*
1109 * structure for configuration #2 reg in mac address map.
1110 * located at address 0x5004
1111 * 31-16: reserved
1112 * 15-12: preamble
1113 * 11-10: reserved
1114 * 9-8: if mode
1115 * 7-6: reserved
1116 * 5: huge frame
1117 * 4: length check
1118 * 3: undefined
1119 * 2: pad crc
1120 * 1: crc enable
1121 * 0: full duplex
1122 */
1123
1124
1125 /*
1126 * structure for Interpacket gap reg in mac address map.
1127 * located at address 0x5008
1128 *
1129 * 31: reserved
1130 * 30-24: non B2B ipg 1
1131 * 23: undefined
1132 * 22-16: non B2B ipg 2
1133 * 15-8: Min ifg enforce
1134 * 7-0: B2B ipg
1135 *
1136 * structure for half duplex reg in mac address map.
1137 * located at address 0x500C
1138 * 31-24: reserved
1139 * 23-20: Alt BEB trunc
1140 * 19: Alt BEB enable
1141 * 18: BP no backoff
1142 * 17: no backoff
1143 * 16: excess defer
1144 * 15-12: re-xmit max
1145 * 11-10: reserved
1146 * 9-0: collision window
1147 */
1148
1149 /*
1150 * structure for Maximum Frame Length reg in mac address map.
1151 * located at address 0x5010: bits 0-15 hold the length.
1152 */
1153
1154 /*
1155 * structure for Reserve 1 reg in mac address map.
1156 * located at address 0x5014 - 0x5018
1157 * Defined earlier (u32)
1158 */
1159
1160 /*
1161 * structure for Test reg in mac address map.
1162 * located at address 0x501C
1163 * test: bits 0-2, rest unused
1164 */
1165
1166 /*
1167 * structure for MII Management Configuration reg in mac address map.
1168 * located at address 0x5020
1169 *
1170 * 31: reset MII mgmt
1171 * 30-6: unused
1172 * 5: scan auto increment
1173 * 4: preamble supress
1174 * 3: undefined
1175 * 2-0: mgmt clock reset
1176 */
1177
1178 /*
1179 * structure for MII Management Command reg in mac address map.
1180 * located at address 0x5024
1181 * bit 1: scan cycle
1182 * bit 0: read cycle
1183 */
1184
1185 /*
1186 * structure for MII Management Address reg in mac address map.
1187 * located at address 0x5028
1188 * 31-13: reserved
1189 * 12-8: phy addr
1190 * 7-5: reserved
1191 * 4-0: register
1192 */
1193
1194 #define MII_ADDR(phy,reg) ((phy) << 8 | (reg))
1195
1196 /*
1197 * structure for MII Management Control reg in mac address map.
1198 * located at address 0x502C
1199 * 31-16: reserved
1200 * 15-0: phy control
1201 */
1202
1203 /*
1204 * structure for MII Management Status reg in mac address map.
1205 * located at address 0x5030
1206 * 31-16: reserved
1207 * 15-0: phy control
1208 */
1209
1210 /*
1211 * structure for MII Management Indicators reg in mac address map.
1212 * located at address 0x5034
1213 * 31-3: reserved
1214 * 2: not valid
1215 * 1: scanning
1216 * 0: busy
1217 */
1218
1219 #define MGMT_BUSY 0x00000001 /* busy */
1220 #define MGMT_WAIT 0x00000005 /* busy | not valid */
1221
1222 /*
1223 * structure for Interface Control reg in mac address map.
1224 * located at address 0x5038
1225 *
1226 * 31: reset if module
1227 * 30-28: reserved
1228 * 27: tbi mode
1229 * 26: ghd mode
1230 * 25: lhd mode
1231 * 24: phy mode
1232 * 23: reset per mii
1233 * 22-17: reserved
1234 * 16: speed
1235 * 15: reset pe100x
1236 * 14-11: reserved
1237 * 10: force quiet
1238 * 9: no cipher
1239 * 8: disable link fail
1240 * 7: reset gpsi
1241 * 6-1: reserved
1242 * 0: enable jabber protection
1243 */
1244
1245 /*
1246 * structure for Interface Status reg in mac address map.
1247 * located at address 0x503C
1248 */
1249 typedef union _MAC_IF_STAT_t {
1250 u32 value;
1251 struct {
1252 #ifdef _BIT_FIELDS_HTOL
1253 u32 reserved:22; /* bits 10-31 */
1254 u32 excess_defer:1; /* bit 9 */
1255 u32 clash:1; /* bit 8 */
1256 u32 phy_jabber:1; /* bit 7 */
1257 u32 phy_link_ok:1; /* bit 6 */
1258 u32 phy_full_duplex:1; /* bit 5 */
1259 u32 phy_speed:1; /* bit 4 */
1260 u32 pe100x_link_fail:1; /* bit 3 */
1261 u32 pe10t_loss_carrie:1; /* bit 2 */
1262 u32 pe10t_sqe_error:1; /* bit 1 */
1263 u32 pe10t_jabber:1; /* bit 0 */
1264 #else
1265 u32 pe10t_jabber:1; /* bit 0 */
1266 u32 pe10t_sqe_error:1; /* bit 1 */
1267 u32 pe10t_loss_carrie:1; /* bit 2 */
1268 u32 pe100x_link_fail:1; /* bit 3 */
1269 u32 phy_speed:1; /* bit 4 */
1270 u32 phy_full_duplex:1; /* bit 5 */
1271 u32 phy_link_ok:1; /* bit 6 */
1272 u32 phy_jabber:1; /* bit 7 */
1273 u32 clash:1; /* bit 8 */
1274 u32 excess_defer:1; /* bit 9 */
1275 u32 reserved:22; /* bits 10-31 */
1276 #endif
1277 } bits;
1278 } MAC_IF_STAT_t, *PMAC_IF_STAT_t;
1279
1280 /*
1281 * structure for Mac Station Address, Part 1 reg in mac address map.
1282 * located at address 0x5040
1283 */
1284 typedef union _MAC_STATION_ADDR1_t {
1285 u32 value;
1286 struct {
1287 #ifdef _BIT_FIELDS_HTOL
1288 u32 Octet6:8; /* bits 24-31 */
1289 u32 Octet5:8; /* bits 16-23 */
1290 u32 Octet4:8; /* bits 8-15 */
1291 u32 Octet3:8; /* bits 0-7 */
1292 #else
1293 u32 Octet3:8; /* bits 0-7 */
1294 u32 Octet4:8; /* bits 8-15 */
1295 u32 Octet5:8; /* bits 16-23 */
1296 u32 Octet6:8; /* bits 24-31 */
1297 #endif
1298 } bits;
1299 } MAC_STATION_ADDR1_t, *PMAC_STATION_ADDR1_t;
1300
1301 /*
1302 * structure for Mac Station Address, Part 2 reg in mac address map.
1303 * located at address 0x5044
1304 */
1305 typedef union _MAC_STATION_ADDR2_t {
1306 u32 value;
1307 struct {
1308 #ifdef _BIT_FIELDS_HTOL
1309 u32 Octet2:8; /* bits 24-31 */
1310 u32 Octet1:8; /* bits 16-23 */
1311 u32 reserved:16; /* bits 0-15 */
1312 #else
1313 u32 reserved:16; /* bit 0-15 */
1314 u32 Octet1:8; /* bits 16-23 */
1315 u32 Octet2:8; /* bits 24-31 */
1316 #endif
1317 } bits;
1318 } MAC_STATION_ADDR2_t, *PMAC_STATION_ADDR2_t;
1319
1320 /*
1321 * MAC Module of JAGCore Address Mapping
1322 */
1323 typedef struct _MAC_t { /* Location: */
1324 u32 cfg1; /* 0x5000 */
1325 u32 cfg2; /* 0x5004 */
1326 u32 ipg; /* 0x5008 */
1327 u32 hfdp; /* 0x500C */
1328 u32 max_fm_len; /* 0x5010 */
1329 u32 rsv1; /* 0x5014 */
1330 u32 rsv2; /* 0x5018 */
1331 u32 mac_test; /* 0x501C */
1332 u32 mii_mgmt_cfg; /* 0x5020 */
1333 u32 mii_mgmt_cmd; /* 0x5024 */
1334 u32 mii_mgmt_addr; /* 0x5028 */
1335 u32 mii_mgmt_ctrl; /* 0x502C */
1336 u32 mii_mgmt_stat; /* 0x5030 */
1337 u32 mii_mgmt_indicator; /* 0x5034 */
1338 u32 if_ctrl; /* 0x5038 */
1339 MAC_IF_STAT_t if_stat; /* 0x503C */
1340 MAC_STATION_ADDR1_t station_addr_1; /* 0x5040 */
1341 MAC_STATION_ADDR2_t station_addr_2; /* 0x5044 */
1342 } MAC_t, *PMAC_t;
1343
1344 /* END OF MAC REGISTER ADDRESS MAP */
1345
1346 /* START OF MAC STAT REGISTER ADDRESS MAP */
1347
1348 /*
1349 * structure for Carry Register One and it's Mask Register reg located in mac
1350 * stat address map address 0x6130 and 0x6138.
1351 *
1352 * 31: tr64
1353 * 30: tr127
1354 * 29: tr255
1355 * 28: tr511
1356 * 27: tr1k
1357 * 26: trmax
1358 * 25: trmgv
1359 * 24-17: unused
1360 * 16: rbyt
1361 * 15: rpkt
1362 * 14: rfcs
1363 * 13: rmca
1364 * 12: rbca
1365 * 11: rxcf
1366 * 10: rxpf
1367 * 9: rxuo
1368 * 8: raln
1369 * 7: rflr
1370 * 6: rcde
1371 * 5: rcse
1372 * 4: rund
1373 * 3: rovr
1374 * 2: rfrg
1375 * 1: rjbr
1376 * 0: rdrp
1377 */
1378
1379 /*
1380 * structure for Carry Register Two Mask Register reg in mac stat address map.
1381 * located at address 0x613C
1382 *
1383 * 31-20: unused
1384 * 19: tjbr
1385 * 18: tfcs
1386 * 17: txcf
1387 * 16: tovr
1388 * 15: tund
1389 * 14: trfg
1390 * 13: tbyt
1391 * 12: tpkt
1392 * 11: tmca
1393 * 10: tbca
1394 * 9: txpf
1395 * 8: tdfr
1396 * 7: tedf
1397 * 6: tscl
1398 * 5: tmcl
1399 * 4: tlcl
1400 * 3: txcl
1401 * 2: tncl
1402 * 1: tpfh
1403 * 0: tdrp
1404 */
1405
1406 /*
1407 * MAC STATS Module of JAGCore Address Mapping
1408 */
1409 struct macstat_regs
1410 { /* Location: */
1411 u32 pad[32]; /* 0x6000 - 607C */
1412
1413 /* Tx/Rx 0-64 Byte Frame Counter */
1414 u32 TR64; /* 0x6080 */
1415
1416 /* Tx/Rx 65-127 Byte Frame Counter */
1417 u32 TR127; /* 0x6084 */
1418
1419 /* Tx/Rx 128-255 Byte Frame Counter */
1420 u32 TR255; /* 0x6088 */
1421
1422 /* Tx/Rx 256-511 Byte Frame Counter */
1423 u32 TR511; /* 0x608C */
1424
1425 /* Tx/Rx 512-1023 Byte Frame Counter */
1426 u32 TR1K; /* 0x6090 */
1427
1428 /* Tx/Rx 1024-1518 Byte Frame Counter */
1429 u32 TRMax; /* 0x6094 */
1430
1431 /* Tx/Rx 1519-1522 Byte Good VLAN Frame Count */
1432 u32 TRMgv; /* 0x6098 */
1433
1434 /* Rx Byte Counter */
1435 u32 RByt; /* 0x609C */
1436
1437 /* Rx Packet Counter */
1438 u32 RPkt; /* 0x60A0 */
1439
1440 /* Rx FCS Error Counter */
1441 u32 RFcs; /* 0x60A4 */
1442
1443 /* Rx Multicast Packet Counter */
1444 u32 RMca; /* 0x60A8 */
1445
1446 /* Rx Broadcast Packet Counter */
1447 u32 RBca; /* 0x60AC */
1448
1449 /* Rx Control Frame Packet Counter */
1450 u32 RxCf; /* 0x60B0 */
1451
1452 /* Rx Pause Frame Packet Counter */
1453 u32 RxPf; /* 0x60B4 */
1454
1455 /* Rx Unknown OP Code Counter */
1456 u32 RxUo; /* 0x60B8 */
1457
1458 /* Rx Alignment Error Counter */
1459 u32 RAln; /* 0x60BC */
1460
1461 /* Rx Frame Length Error Counter */
1462 u32 RFlr; /* 0x60C0 */
1463
1464 /* Rx Code Error Counter */
1465 u32 RCde; /* 0x60C4 */
1466
1467 /* Rx Carrier Sense Error Counter */
1468 u32 RCse; /* 0x60C8 */
1469
1470 /* Rx Undersize Packet Counter */
1471 u32 RUnd; /* 0x60CC */
1472
1473 /* Rx Oversize Packet Counter */
1474 u32 ROvr; /* 0x60D0 */
1475
1476 /* Rx Fragment Counter */
1477 u32 RFrg; /* 0x60D4 */
1478
1479 /* Rx Jabber Counter */
1480 u32 RJbr; /* 0x60D8 */
1481
1482 /* Rx Drop */
1483 u32 RDrp; /* 0x60DC */
1484
1485 /* Tx Byte Counter */
1486 u32 TByt; /* 0x60E0 */
1487
1488 /* Tx Packet Counter */
1489 u32 TPkt; /* 0x60E4 */
1490
1491 /* Tx Multicast Packet Counter */
1492 u32 TMca; /* 0x60E8 */
1493
1494 /* Tx Broadcast Packet Counter */
1495 u32 TBca; /* 0x60EC */
1496
1497 /* Tx Pause Control Frame Counter */
1498 u32 TxPf; /* 0x60F0 */
1499
1500 /* Tx Deferral Packet Counter */
1501 u32 TDfr; /* 0x60F4 */
1502
1503 /* Tx Excessive Deferral Packet Counter */
1504 u32 TEdf; /* 0x60F8 */
1505
1506 /* Tx Single Collision Packet Counter */
1507 u32 TScl; /* 0x60FC */
1508
1509 /* Tx Multiple Collision Packet Counter */
1510 u32 TMcl; /* 0x6100 */
1511
1512 /* Tx Late Collision Packet Counter */
1513 u32 TLcl; /* 0x6104 */
1514
1515 /* Tx Excessive Collision Packet Counter */
1516 u32 TXcl; /* 0x6108 */
1517
1518 /* Tx Total Collision Packet Counter */
1519 u32 TNcl; /* 0x610C */
1520
1521 /* Tx Pause Frame Honored Counter */
1522 u32 TPfh; /* 0x6110 */
1523
1524 /* Tx Drop Frame Counter */
1525 u32 TDrp; /* 0x6114 */
1526
1527 /* Tx Jabber Frame Counter */
1528 u32 TJbr; /* 0x6118 */
1529
1530 /* Tx FCS Error Counter */
1531 u32 TFcs; /* 0x611C */
1532
1533 /* Tx Control Frame Counter */
1534 u32 TxCf; /* 0x6120 */
1535
1536 /* Tx Oversize Frame Counter */
1537 u32 TOvr; /* 0x6124 */
1538
1539 /* Tx Undersize Frame Counter */
1540 u32 TUnd; /* 0x6128 */
1541
1542 /* Tx Fragments Frame Counter */
1543 u32 TFrg; /* 0x612C */
1544
1545 /* Carry Register One Register */
1546 u32 Carry1; /* 0x6130 */
1547
1548 /* Carry Register Two Register */
1549 u32 Carry2; /* 0x6134 */
1550
1551 /* Carry Register One Mask Register */
1552 u32 Carry1M; /* 0x6138 */
1553
1554 /* Carry Register Two Mask Register */
1555 u32 Carry2M; /* 0x613C */
1556 };
1557
1558 /* END OF MAC STAT REGISTER ADDRESS MAP */
1559
1560
1561 /* START OF MMC REGISTER ADDRESS MAP */
1562
1563 /*
1564 * Main Memory Controller Control reg in mmc address map.
1565 * located at address 0x7000
1566 */
1567
1568 #define ET_MMC_ENABLE 1
1569 #define ET_MMC_ARB_DISABLE 2
1570 #define ET_MMC_RXMAC_DISABLE 4
1571 #define ET_MMC_TXMAC_DISABLE 8
1572 #define ET_MMC_TXDMA_DISABLE 16
1573 #define ET_MMC_RXDMA_DISABLE 32
1574 #define ET_MMC_FORCE_CE 64
1575
1576 /*
1577 * Main Memory Controller Host Memory Access Address reg in mmc
1578 * address map. Located at address 0x7004. Top 16 bits hold the address bits
1579 */
1580
1581 #define ET_SRAM_REQ_ACCESS 1
1582 #define ET_SRAM_WR_ACCESS 2
1583 #define ET_SRAM_IS_CTRL 4
1584
1585 /*
1586 * structure for Main Memory Controller Host Memory Access Data reg in mmc
1587 * address map. Located at address 0x7008 - 0x7014
1588 * Defined earlier (u32)
1589 */
1590
1591 /*
1592 * Memory Control Module of JAGCore Address Mapping
1593 */
1594 struct mmc_regs { /* Location: */
1595 u32 mmc_ctrl; /* 0x7000 */
1596 u32 sram_access; /* 0x7004 */
1597 u32 sram_word1; /* 0x7008 */
1598 u32 sram_word2; /* 0x700C */
1599 u32 sram_word3; /* 0x7010 */
1600 u32 sram_word4; /* 0x7014 */
1601 };
1602
1603 /* END OF MMC REGISTER ADDRESS MAP */
1604
1605
1606 /*
1607 * JAGCore Address Mapping
1608 */
1609 typedef struct _ADDRESS_MAP_t {
1610 struct global_regs global;
1611 /* unused section of global address map */
1612 u8 unused_global[4096 - sizeof(struct global_regs)];
1613 struct txdma_regs txdma;
1614 /* unused section of txdma address map */
1615 u8 unused_txdma[4096 - sizeof(struct txdma_regs)];
1616 struct rxdma_regs rxdma;
1617 /* unused section of rxdma address map */
1618 u8 unused_rxdma[4096 - sizeof(struct rxdma_regs)];
1619 struct txmac_regs txmac;
1620 /* unused section of txmac address map */
1621 u8 unused_txmac[4096 - sizeof(struct txmac_regs)];
1622 RXMAC_t rxmac;
1623 /* unused section of rxmac address map */
1624 u8 unused_rxmac[4096 - sizeof(RXMAC_t)];
1625 MAC_t mac;
1626 /* unused section of mac address map */
1627 u8 unused_mac[4096 - sizeof(MAC_t)];
1628 struct macstat_regs macstat;
1629 /* unused section of mac stat address map */
1630 u8 unused_mac_stat[4096 - sizeof(struct macstat_regs)];
1631 struct mmc_regs mmc;
1632 /* unused section of mmc address map */
1633 u8 unused_mmc[4096 - sizeof(struct mmc_regs)];
1634 /* unused section of address map */
1635 u8 unused_[1015808];
1636
1637 u8 unused_exp_rom[4096]; /* MGS-size TBD */
1638 u8 unused__[524288]; /* unused section of address map */
1639 } ADDRESS_MAP_t, *PADDRESS_MAP_t;
1640
1641 #endif /* _ET1310_ADDRESS_MAP_H_ */
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