arch/x86/kernel/cpu/intel.c

   1 #include <linux/init.h>
   2 #include <linux/kernel.h>
   3
   4 #include <linux/string.h>
   5 #include <linux/bitops.h>
   6 #include <linux/smp.h>
   7 #include <linux/thread_info.h>
   8 #include <linux/module.h>
   9
  10 #include <asm/processor.h>
  11 #include <asm/pgtable.h>
  12 #include <asm/msr.h>
  13 #include <asm/uaccess.h>
  14 #include <asm/ptrace.h>
  15 #include <asm/ds.h>
  16 #include <asm/bugs.h>
  17
  18 #include "cpu.h"
  19
  20 #ifdef CONFIG_X86_LOCAL_APIC
  21 #include <asm/mpspec.h>
  22 #include <asm/apic.h>
  23 #include <mach_apic.h>
  24 #endif
  25
  26 #ifdef CONFIG_X86_INTEL_USERCOPY
  27 /*
  28  * Alignment at which movsl is preferred for bulk memory copies.
  29  */
  30 struct movsl_mask movsl_mask __read_mostly;
  31 #endif
  32
  33 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
  34 {
  35         /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
  36         if (c->x86 == 15 && c->x86_cache_alignment == 64)
  37                 c->x86_cache_alignment = 128;
  38         if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
  39                 (c->x86 == 0x6 && c->x86_model >= 0x0e))
  40                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
  41 }
  42
  43 /*
  44  *      Early probe support logic for ppro memory erratum #50
  45  *
  46  *      This is called before we do cpu ident work
  47  */
  48
  49 int __cpuinit ppro_with_ram_bug(void)
  50 {
  51         /* Uses data from early_cpu_detect now */
  52         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
  53             boot_cpu_data.x86 == 6 &&
  54             boot_cpu_data.x86_model == 1 &&
  55             boot_cpu_data.x86_mask < 8) {
  56                 printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
  57                 return 1;
  58         }
  59         return 0;
  60 }
  61
  62
  63 /*
  64  * P4 Xeon errata 037 workaround.
  65  * Hardware prefetcher may cause stale data to be loaded into the cache.
  66  */
  67 static void __cpuinit Intel_errata_workarounds(struct cpuinfo_x86 *c)
  68 {
  69         unsigned long lo, hi;
  70
  71         if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
  72                 rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
  73                 if ((lo & (1<<9)) == 0) {
  74                         printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
  75                         printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
  76                         lo |= (1<<9);   /* Disable hw prefetching */
  77                         wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
  78                 }
  79         }
  80 }
  81
  82
  83 /*
  84  * find out the number of processor cores on the die
  85  */
  86 static int __cpuinit num_cpu_cores(struct cpuinfo_x86 *c)
  87 {
  88         unsigned int eax, ebx, ecx, edx;
  89
  90         if (c->cpuid_level < 4)
  91                 return 1;
  92
  93         /* Intel has a non-standard dependency on %ecx for this CPUID level. */
  94         cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
  95         if (eax & 0x1f)
  96                 return ((eax >> 26) + 1);
  97         else
  98                 return 1;
  99 }
 100
 101 #ifdef CONFIG_X86_F00F_BUG
 102 static void __cpuinit trap_init_f00f_bug(void)
 103 {
 104         __set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
 105
 106         /*
 107          * Update the IDT descriptor and reload the IDT so that
 108          * it uses the read-only mapped virtual address.
 109          */
 110         idt_descr.address = fix_to_virt(FIX_F00F_IDT);
 111         load_idt(&idt_descr);
 112 }
 113 #endif
 114
 115 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 116 {
 117         unsigned int l2 = 0;
 118         char *p = NULL;
 119
 120         early_init_intel(c);
 121
 122 #ifdef CONFIG_X86_F00F_BUG
 123         /*
 124          * All current models of Pentium and Pentium with MMX technology CPUs
 125          * have the F0 0F bug, which lets nonprivileged users lock up the system.
 126          * Note that the workaround only should be initialized once...
 127          */
 128         c->f00f_bug = 0;
 129         if (!paravirt_enabled() && c->x86 == 5) {
 130                 static int f00f_workaround_enabled;
 131
 132                 c->f00f_bug = 1;
 133                 if (!f00f_workaround_enabled) {
 134                         trap_init_f00f_bug();
 135                         printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
 136                         f00f_workaround_enabled = 1;
 137                 }
 138         }
 139 #endif
 140
 141         l2 = init_intel_cacheinfo(c);
 142         if (c->cpuid_level > 9) {
 143                 unsigned eax = cpuid_eax(10);
 144                 /* Check for version and the number of counters */
 145                 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
 146                         set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
 147         }
 148
 149         /* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until model 3 mask 3 */
 150         if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
 151                 clear_cpu_cap(c, X86_FEATURE_SEP);
 152
 153         /*
 154          * Names for the Pentium II/Celeron processors
 155          * detectable only by also checking the cache size.
 156          * Dixon is NOT a Celeron.
 157          */
 158         if (c->x86 == 6) {
 159                 switch (c->x86_model) {
 160                 case 5:
 161                         if (c->x86_mask == 0) {
 162                                 if (l2 == 0)
 163                                         p = "Celeron (Covington)";
 164                                 else if (l2 == 256)
 165                                         p = "Mobile Pentium II (Dixon)";
 166                         }
 167                         break;
 168
 169                 case 6:
 170                         if (l2 == 128)
 171                                 p = "Celeron (Mendocino)";
 172                         else if (c->x86_mask == 0 || c->x86_mask == 5)
 173                                 p = "Celeron-A";
 174                         break;
 175
 176                 case 8:
 177                         if (l2 == 128)
 178                                 p = "Celeron (Coppermine)";
 179                         break;
 180                 }
 181         }
 182
 183         if (p)
 184                 strcpy(c->x86_model_id, p);
 185
 186         c->x86_max_cores = num_cpu_cores(c);
 187
 188         detect_ht(c);
 189
 190         /* Work around errata */
 191         Intel_errata_workarounds(c);
 192
 193 #ifdef CONFIG_X86_INTEL_USERCOPY
 194         /*
 195          * Set up the preferred alignment for movsl bulk memory moves
 196          */
 197         switch (c->x86) {
 198         case 4:         /* 486: untested */
 199                 break;
 200         case 5:         /* Old Pentia: untested */
 201                 break;
 202         case 6:         /* PII/PIII only like movsl with 8-byte alignment */
 203                 movsl_mask.mask = 7;
 204                 break;
 205         case 15:        /* P4 is OK down to 8-byte alignment */
 206                 movsl_mask.mask = 7;
 207                 break;
 208         }
 209 #endif
 210
 211         if (cpu_has_xmm2)
 212                 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
 213         if (c->x86 == 15) {
 214                 set_cpu_cap(c, X86_FEATURE_P4);
 215         }
 216         if (c->x86 == 6)
 217                 set_cpu_cap(c, X86_FEATURE_P3);
 218         if (cpu_has_ds) {
 219                 unsigned int l1;
 220                 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
 221                 if (!(l1 & (1<<11)))
 222                         set_cpu_cap(c, X86_FEATURE_BTS);
 223                 if (!(l1 & (1<<12)))
 224                         set_cpu_cap(c, X86_FEATURE_PEBS);
 225         }
 226
 227         if (cpu_has_bts)
 228                 ds_init_intel(c);
 229
 230         /*
 231          * See if we have a good local APIC by checking for buggy Pentia,
 232          * i.e. all B steppings and the C2 stepping of P54C when using their
 233          * integrated APIC (see 11AP erratum in "Pentium Processor
 234          * Specification Update").
 235          */
 236         if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
 237             (c->x86_mask < 0x6 || c->x86_mask == 0xb))
 238                 set_cpu_cap(c, X86_FEATURE_11AP);
 239
 240 #ifdef CONFIG_X86_NUMAQ
 241         numaq_tsc_disable();
 242 #endif
 243 }
 244
 245 static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
 246 {
 247         /*
 248          * Intel PIII Tualatin. This comes in two flavours.
 249          * One has 256kb of cache, the other 512. We have no way
 250          * to determine which, so we use a boottime override
 251          * for the 512kb model, and assume 256 otherwise.
 252          */
 253         if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
 254                 size = 256;
 255         return size;
 256 }
 257
 258 static struct cpu_dev intel_cpu_dev __cpuinitdata = {
 259         .c_vendor       = "Intel",
 260         .c_ident        = { "GenuineIntel" },
 261         .c_models = {
 262                 { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
 263                   {
 264                           [0] = "486 DX-25/33",
 265                           [1] = "486 DX-50",
 266                           [2] = "486 SX",
 267                           [3] = "486 DX/2",
 268                           [4] = "486 SL",
 269                           [5] = "486 SX/2",
 270                           [7] = "486 DX/2-WB",
 271                           [8] = "486 DX/4",
 272                           [9] = "486 DX/4-WB"
 273                   }
 274                 },
 275                 { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
 276                   {
 277                           [0] = "Pentium 60/66 A-step",
 278                           [1] = "Pentium 60/66",
 279                           [2] = "Pentium 75 - 200",
 280                           [3] = "OverDrive PODP5V83",
 281                           [4] = "Pentium MMX",
 282                           [7] = "Mobile Pentium 75 - 200",
 283                           [8] = "Mobile Pentium MMX"
 284                   }
 285                 },
 286                 { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
 287                   {
 288                           [0] = "Pentium Pro A-step",
 289                           [1] = "Pentium Pro",
 290                           [3] = "Pentium II (Klamath)",
 291                           [4] = "Pentium II (Deschutes)",
 292                           [5] = "Pentium II (Deschutes)",
 293                           [6] = "Mobile Pentium II",
 294                           [7] = "Pentium III (Katmai)",
 295                           [8] = "Pentium III (Coppermine)",
 296                           [10] = "Pentium III (Cascades)",
 297                           [11] = "Pentium III (Tualatin)",
 298                   }
 299                 },
 300                 { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
 301                   {
 302                           [0] = "Pentium 4 (Unknown)",
 303                           [1] = "Pentium 4 (Willamette)",
 304                           [2] = "Pentium 4 (Northwood)",
 305                           [4] = "Pentium 4 (Foster)",
 306                           [5] = "Pentium 4 (Foster)",
 307                   }
 308                 },
 309         },
 310         .c_early_init   = early_init_intel,
 311         .c_init         = init_intel,
 312         .c_size_cache   = intel_size_cache,
 313 };
 314
 315 cpu_vendor_dev_register(X86_VENDOR_INTEL, &intel_cpu_dev);
 316
 317 #ifndef CONFIG_X86_CMPXCHG
 318 unsigned long cmpxchg_386_u8(volatile void *ptr, u8 old, u8 new)
 319 {
 320         u8 prev;
 321         unsigned long flags;
 322
 323         /* Poor man's cmpxchg for 386. Unsuitable for SMP */
 324         local_irq_save(flags);
 325         prev = *(u8 *)ptr;
 326         if (prev == old)
 327                 *(u8 *)ptr = new;
 328         local_irq_restore(flags);
 329         return prev;
 330 }
 331 EXPORT_SYMBOL(cmpxchg_386_u8);
 332
 333 unsigned long cmpxchg_386_u16(volatile void *ptr, u16 old, u16 new)
 334 {
 335         u16 prev;
 336         unsigned long flags;
 337
 338         /* Poor man's cmpxchg for 386. Unsuitable for SMP */
 339         local_irq_save(flags);
 340         prev = *(u16 *)ptr;
 341         if (prev == old)
 342                 *(u16 *)ptr = new;
 343         local_irq_restore(flags);
 344         return prev;
 345 }
 346 EXPORT_SYMBOL(cmpxchg_386_u16);
 347
 348 unsigned long cmpxchg_386_u32(volatile void *ptr, u32 old, u32 new)
 349 {
 350         u32 prev;
 351         unsigned long flags;
 352
 353         /* Poor man's cmpxchg for 386. Unsuitable for SMP */
 354         local_irq_save(flags);
 355         prev = *(u32 *)ptr;
 356         if (prev == old)
 357                 *(u32 *)ptr = new;
 358         local_irq_restore(flags);
 359         return prev;
 360 }
 361 EXPORT_SYMBOL(cmpxchg_386_u32);
 362 #endif
 363
 364 #ifndef CONFIG_X86_CMPXCHG64
 365 unsigned long long cmpxchg_486_u64(volatile void *ptr, u64 old, u64 new)
 366 {
 367         u64 prev;
 368         unsigned long flags;
 369
 370         /* Poor man's cmpxchg8b for 386 and 486. Unsuitable for SMP */
 371         local_irq_save(flags);
 372         prev = *(u64 *)ptr;
 373         if (prev == old)
 374                 *(u64 *)ptr = new;
 375         local_irq_restore(flags);
 376         return prev;
 377 }
 378 EXPORT_SYMBOL(cmpxchg_486_u64);
 379 #endif
 380
 381 /* arch_initcall(intel_cpu_init); */
 382