arch/arm/plat-omap/include/mach/clock.h

   1 /*
   2  *  arch/arm/plat-omap/include/mach/clock.h
   3  *
   4  *  Copyright (C) 2004 - 2005 Nokia corporation
   5  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
   6  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #ifndef __ARCH_ARM_OMAP_CLOCK_H
  14 #define __ARCH_ARM_OMAP_CLOCK_H
  15
  16 struct module;
  17 struct clk;
  18 struct clockdomain;
  19
  20 struct clkops {
  21         int                     (*enable)(struct clk *);
  22         void                    (*disable)(struct clk *);
  23 };
  24
  25 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
  26
  27 struct clksel_rate {
  28         u32                     val;
  29         u8                      div;
  30         u8                      flags;
  31 };
  32
  33 struct clksel {
  34         struct clk               *parent;
  35         const struct clksel_rate *rates;
  36 };
  37
  38 struct dpll_data {
  39         void __iomem            *mult_div1_reg;
  40         u32                     mult_mask;
  41         u32                     div1_mask;
  42         unsigned int            rate_tolerance;
  43         unsigned long           last_rounded_rate;
  44         u16                     last_rounded_m;
  45         u8                      last_rounded_n;
  46         u8                      max_divider;
  47         u32                     max_tolerance;
  48         u16                     max_multiplier;
  49 #  if defined(CONFIG_ARCH_OMAP3)
  50         u8                      modes;
  51         void __iomem            *control_reg;
  52         void __iomem            *autoidle_reg;
  53         void __iomem            *idlest_reg;
  54         u32                     enable_mask;
  55         u32                     autoidle_mask;
  56         u32                     freqsel_mask;
  57         u8                      auto_recal_bit;
  58         u8                      recal_en_bit;
  59         u8                      recal_st_bit;
  60         u8                      idlest_bit;
  61 #  endif
  62 };
  63
  64 #endif
  65
  66 struct clk {
  67         struct list_head        node;
  68         const struct clkops     *ops;
  69         const char              *name;
  70         int                     id;
  71         struct clk              *parent;
  72         unsigned long           rate;
  73         __u32                   flags;
  74         void __iomem            *enable_reg;
  75         void                    (*recalc)(struct clk *);
  76         int                     (*set_rate)(struct clk *, unsigned long);
  77         long                    (*round_rate)(struct clk *, unsigned long);
  78         void                    (*init)(struct clk *);
  79         __u8                    enable_bit;
  80         __s8                    usecount;
  81 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
  82         u8                      fixed_div;
  83         void __iomem            *clksel_reg;
  84         u32                     clksel_mask;
  85         const struct clksel     *clksel;
  86         struct dpll_data        *dpll_data;
  87         const char              *clkdm_name;
  88         struct clockdomain      *clkdm;
  89 #else
  90         __u8                    rate_offset;
  91         __u8                    src_offset;
  92 #endif
  93 #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
  94         struct dentry           *dent;  /* For visible tree hierarchy */
  95 #endif
  96 };
  97
  98 struct cpufreq_frequency_table;
  99
 100 struct clk_functions {
 101         int             (*clk_enable)(struct clk *clk);
 102         void            (*clk_disable)(struct clk *clk);
 103         long            (*clk_round_rate)(struct clk *clk, unsigned long rate);
 104         int             (*clk_set_rate)(struct clk *clk, unsigned long rate);
 105         int             (*clk_set_parent)(struct clk *clk, struct clk *parent);
 106         void            (*clk_allow_idle)(struct clk *clk);
 107         void            (*clk_deny_idle)(struct clk *clk);
 108         void            (*clk_disable_unused)(struct clk *clk);
 109 #ifdef CONFIG_CPU_FREQ
 110         void            (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
 111 #endif
 112 };
 113
 114 extern unsigned int mpurate;
 115
 116 extern int clk_init(struct clk_functions *custom_clocks);
 117 extern int clk_register(struct clk *clk);
 118 extern void clk_unregister(struct clk *clk);
 119 extern void propagate_rate(struct clk *clk);
 120 extern void recalculate_root_clocks(void);
 121 extern void followparent_recalc(struct clk *clk);
 122 extern int clk_get_usecount(struct clk *clk);
 123 extern void clk_enable_init_clocks(void);
 124 #ifdef CONFIG_CPU_FREQ
 125 extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
 126 #endif
 127
 128 extern const struct clkops clkops_null;
 129
 130 /* Clock flags */
 131 /* bit 0 is free */
 132 #define RATE_FIXED              (1 << 1)        /* Fixed clock rate */
 133 #define RATE_PROPAGATES         (1 << 2)        /* Program children too */
 134 /* bits 3-4 are free */
 135 #define ENABLE_REG_32BIT        (1 << 5)        /* Use 32-bit access */
 136 #define VIRTUAL_IO_ADDRESS      (1 << 6)        /* Clock in virtual address */
 137 #define CLOCK_IDLE_CONTROL      (1 << 7)
 138 #define CLOCK_NO_IDLE_PARENT    (1 << 8)
 139 #define DELAYED_APP             (1 << 9)        /* Delay application of clock */
 140 #define CONFIG_PARTICIPANT      (1 << 10)       /* Fundamental clock */
 141 #define ENABLE_ON_INIT          (1 << 11)       /* Enable upon framework init */
 142 #define INVERT_ENABLE           (1 << 12)       /* 0 enables, 1 disables */
 143 /* bits 13-31 are currently free */
 144
 145 /* Clksel_rate flags */
 146 #define DEFAULT_RATE            (1 << 0)
 147 #define RATE_IN_242X            (1 << 1)
 148 #define RATE_IN_243X            (1 << 2)
 149 #define RATE_IN_343X            (1 << 3)        /* rates common to all 343X */
 150 #define RATE_IN_3430ES2         (1 << 4)        /* 3430ES2 rates only */
 151
 152 #define RATE_IN_24XX            (RATE_IN_242X | RATE_IN_243X)
 153
 154
 155 /* CM_CLKSEL2_PLL.CORE_CLK_SRC options (24XX) */
 156 #define CORE_CLK_SRC_32K                0
 157 #define CORE_CLK_SRC_DPLL               1
 158 #define CORE_CLK_SRC_DPLL_X2            2
 159
 160 #endif