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advansys: Remove 'TRUE' and 'FALSE' definitions
[linux-2.6/btrfs-unstable.git] / drivers / scsi / advansys.c
blob9c32977694902b57236cc3e9a5e3a598a550f1dd
1 #define DRV_NAME "advansys"
2 #define ASC_VERSION "3.4" /* AdvanSys Driver Version */
3
4 /*
5 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
6 *
7 * Copyright (c) 1995-2000 Advanced System Products, Inc.
8 * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
9 * Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx>
10 * All Rights Reserved.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 */
17
18 /*
19 * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
20 * changed its name to ConnectCom Solutions, Inc.
21 * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets
22 */
23
24 #include <linux/module.h>
25 #include <linux/string.h>
26 #include <linux/kernel.h>
27 #include <linux/types.h>
28 #include <linux/ioport.h>
29 #include <linux/interrupt.h>
30 #include <linux/delay.h>
31 #include <linux/slab.h>
32 #include <linux/mm.h>
33 #include <linux/proc_fs.h>
34 #include <linux/init.h>
35 #include <linux/blkdev.h>
36 #include <linux/isa.h>
37 #include <linux/eisa.h>
38 #include <linux/pci.h>
39 #include <linux/spinlock.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/firmware.h>
42
43 #include <asm/io.h>
44 #include <asm/dma.h>
45
46 #include <scsi/scsi_cmnd.h>
47 #include <scsi/scsi_device.h>
48 #include <scsi/scsi_tcq.h>
49 #include <scsi/scsi.h>
50 #include <scsi/scsi_host.h>
51
52 /* FIXME:
53 *
54 * 1. Although all of the necessary command mapping places have the
55 * appropriate dma_map.. APIs, the driver still processes its internal
56 * queue using bus_to_virt() and virt_to_bus() which are illegal under
57 * the API. The entire queue processing structure will need to be
58 * altered to fix this.
59 * 2. Need to add memory mapping workaround. Test the memory mapping.
60 * If it doesn't work revert to I/O port access. Can a test be done
61 * safely?
62 * 3. Handle an interrupt not working. Keep an interrupt counter in
63 * the interrupt handler. In the timeout function if the interrupt
64 * has not occurred then print a message and run in polled mode.
65 * 4. Need to add support for target mode commands, cf. CAM XPT.
66 * 5. check DMA mapping functions for failure
67 * 6. Use scsi_transport_spi
68 * 7. advansys_info is not safe against multiple simultaneous callers
69 * 8. Add module_param to override ISA/VLB ioport array
70 */
71 #warning this driver is still not properly converted to the DMA API
72
73 /* Enable driver /proc statistics. */
74 #define ADVANSYS_STATS
75
76 /* Enable driver tracing. */
77 #undef ADVANSYS_DEBUG
78
79 typedef unsigned char uchar;
80
81 #define ERR (-1)
82 #define UW_ERR (uint)(0xFFFF)
83 #define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0)
84
85 #define PCI_VENDOR_ID_ASP 0x10cd
86 #define PCI_DEVICE_ID_ASP_1200A 0x1100
87 #define PCI_DEVICE_ID_ASP_ABP940 0x1200
88 #define PCI_DEVICE_ID_ASP_ABP940U 0x1300
89 #define PCI_DEVICE_ID_ASP_ABP940UW 0x2300
90 #define PCI_DEVICE_ID_38C0800_REV1 0x2500
91 #define PCI_DEVICE_ID_38C1600_REV1 0x2700
92
93 /*
94 * Enable CC_VERY_LONG_SG_LIST to support up to 64K element SG lists.
95 * The SRB structure will have to be changed and the ASC_SRB2SCSIQ()
96 * macro re-defined to be able to obtain a ASC_SCSI_Q pointer from the
97 * SRB structure.
98 */
99 #define CC_VERY_LONG_SG_LIST 0
100 #define ASC_SRB2SCSIQ(srb_ptr) (srb_ptr)
101
102 #define PortAddr unsigned int /* port address size */
103 #define inp(port) inb(port)
104 #define outp(port, byte) outb((byte), (port))
105
106 #define inpw(port) inw(port)
107 #define outpw(port, word) outw((word), (port))
108
109 #define ASC_MAX_SG_QUEUE 7
110 #define ASC_MAX_SG_LIST 255
111
112 #define ASC_CS_TYPE unsigned short
113
114 #define ASC_IS_ISA (0x0001)
115 #define ASC_IS_ISAPNP (0x0081)
116 #define ASC_IS_EISA (0x0002)
117 #define ASC_IS_PCI (0x0004)
118 #define ASC_IS_PCI_ULTRA (0x0104)
119 #define ASC_IS_PCMCIA (0x0008)
120 #define ASC_IS_MCA (0x0020)
121 #define ASC_IS_VL (0x0040)
122 #define ASC_IS_WIDESCSI_16 (0x0100)
123 #define ASC_IS_WIDESCSI_32 (0x0200)
124 #define ASC_IS_BIG_ENDIAN (0x8000)
125
126 #define ASC_CHIP_MIN_VER_VL (0x01)
127 #define ASC_CHIP_MAX_VER_VL (0x07)
128 #define ASC_CHIP_MIN_VER_PCI (0x09)
129 #define ASC_CHIP_MAX_VER_PCI (0x0F)
130 #define ASC_CHIP_VER_PCI_BIT (0x08)
131 #define ASC_CHIP_MIN_VER_ISA (0x11)
132 #define ASC_CHIP_MIN_VER_ISA_PNP (0x21)
133 #define ASC_CHIP_MAX_VER_ISA (0x27)
134 #define ASC_CHIP_VER_ISA_BIT (0x30)
135 #define ASC_CHIP_VER_ISAPNP_BIT (0x20)
136 #define ASC_CHIP_VER_ASYN_BUG (0x21)
137 #define ASC_CHIP_VER_PCI 0x08
138 #define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02)
139 #define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03)
140 #define ASC_CHIP_MIN_VER_EISA (0x41)
141 #define ASC_CHIP_MAX_VER_EISA (0x47)
142 #define ASC_CHIP_VER_EISA_BIT (0x40)
143 #define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
144 #define ASC_MAX_VL_DMA_COUNT (0x07FFFFFFL)
145 #define ASC_MAX_PCI_DMA_COUNT (0xFFFFFFFFL)
146 #define ASC_MAX_ISA_DMA_COUNT (0x00FFFFFFL)
147
148 #define ASC_SCSI_ID_BITS 3
149 #define ASC_SCSI_TIX_TYPE uchar
150 #define ASC_ALL_DEVICE_BIT_SET 0xFF
151 #define ASC_SCSI_BIT_ID_TYPE uchar
152 #define ASC_MAX_TID 7
153 #define ASC_MAX_LUN 7
154 #define ASC_SCSI_WIDTH_BIT_SET 0xFF
155 #define ASC_MAX_SENSE_LEN 32
156 #define ASC_MIN_SENSE_LEN 14
157 #define ASC_SCSI_RESET_HOLD_TIME_US 60
158
159 /*
160 * Narrow boards only support 12-byte commands, while wide boards
161 * extend to 16-byte commands.
162 */
163 #define ASC_MAX_CDB_LEN 12
164 #define ADV_MAX_CDB_LEN 16
165
166 #define MS_SDTR_LEN 0x03
167 #define MS_WDTR_LEN 0x02
168
169 #define ASC_SG_LIST_PER_Q 7
170 #define QS_FREE 0x00
171 #define QS_READY 0x01
172 #define QS_DISC1 0x02
173 #define QS_DISC2 0x04
174 #define QS_BUSY 0x08
175 #define QS_ABORTED 0x40
176 #define QS_DONE 0x80
177 #define QC_NO_CALLBACK 0x01
178 #define QC_SG_SWAP_QUEUE 0x02
179 #define QC_SG_HEAD 0x04
180 #define QC_DATA_IN 0x08
181 #define QC_DATA_OUT 0x10
182 #define QC_URGENT 0x20
183 #define QC_MSG_OUT 0x40
184 #define QC_REQ_SENSE 0x80
185 #define QCSG_SG_XFER_LIST 0x02
186 #define QCSG_SG_XFER_MORE 0x04
187 #define QCSG_SG_XFER_END 0x08
188 #define QD_IN_PROGRESS 0x00
189 #define QD_NO_ERROR 0x01
190 #define QD_ABORTED_BY_HOST 0x02
191 #define QD_WITH_ERROR 0x04
192 #define QD_INVALID_REQUEST 0x80
193 #define QD_INVALID_HOST_NUM 0x81
194 #define QD_INVALID_DEVICE 0x82
195 #define QD_ERR_INTERNAL 0xFF
196 #define QHSTA_NO_ERROR 0x00
197 #define QHSTA_M_SEL_TIMEOUT 0x11
198 #define QHSTA_M_DATA_OVER_RUN 0x12
199 #define QHSTA_M_DATA_UNDER_RUN 0x12
200 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
201 #define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14
202 #define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
203 #define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22
204 #define QHSTA_D_HOST_ABORT_FAILED 0x23
205 #define QHSTA_D_EXE_SCSI_Q_FAILED 0x24
206 #define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
207 #define QHSTA_D_ASPI_NO_BUF_POOL 0x26
208 #define QHSTA_M_WTM_TIMEOUT 0x41
209 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
210 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
211 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
212 #define QHSTA_M_TARGET_STATUS_BUSY 0x45
213 #define QHSTA_M_BAD_TAG_CODE 0x46
214 #define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47
215 #define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
216 #define QHSTA_D_LRAM_CMP_ERROR 0x81
217 #define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
218 #define ASC_FLAG_SCSIQ_REQ 0x01
219 #define ASC_FLAG_BIOS_SCSIQ_REQ 0x02
220 #define ASC_FLAG_BIOS_ASYNC_IO 0x04
221 #define ASC_FLAG_SRB_LINEAR_ADDR 0x08
222 #define ASC_FLAG_WIN16 0x10
223 #define ASC_FLAG_WIN32 0x20
224 #define ASC_FLAG_ISA_OVER_16MB 0x40
225 #define ASC_FLAG_DOS_VM_CALLBACK 0x80
226 #define ASC_TAG_FLAG_EXTRA_BYTES 0x10
227 #define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04
228 #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08
229 #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
230 #define ASC_SCSIQ_CPY_BEG 4
231 #define ASC_SCSIQ_SGHD_CPY_BEG 2
232 #define ASC_SCSIQ_B_FWD 0
233 #define ASC_SCSIQ_B_BWD 1
234 #define ASC_SCSIQ_B_STATUS 2
235 #define ASC_SCSIQ_B_QNO 3
236 #define ASC_SCSIQ_B_CNTL 4
237 #define ASC_SCSIQ_B_SG_QUEUE_CNT 5
238 #define ASC_SCSIQ_D_DATA_ADDR 8
239 #define ASC_SCSIQ_D_DATA_CNT 12
240 #define ASC_SCSIQ_B_SENSE_LEN 20
241 #define ASC_SCSIQ_DONE_INFO_BEG 22
242 #define ASC_SCSIQ_D_SRBPTR 22
243 #define ASC_SCSIQ_B_TARGET_IX 26
244 #define ASC_SCSIQ_B_CDB_LEN 28
245 #define ASC_SCSIQ_B_TAG_CODE 29
246 #define ASC_SCSIQ_W_VM_ID 30
247 #define ASC_SCSIQ_DONE_STATUS 32
248 #define ASC_SCSIQ_HOST_STATUS 33
249 #define ASC_SCSIQ_SCSI_STATUS 34
250 #define ASC_SCSIQ_CDB_BEG 36
251 #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
252 #define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60
253 #define ASC_SCSIQ_B_FIRST_SG_WK_QP 48
254 #define ASC_SCSIQ_B_SG_WK_QP 49
255 #define ASC_SCSIQ_B_SG_WK_IX 50
256 #define ASC_SCSIQ_W_ALT_DC1 52
257 #define ASC_SCSIQ_B_LIST_CNT 6
258 #define ASC_SCSIQ_B_CUR_LIST_CNT 7
259 #define ASC_SGQ_B_SG_CNTL 4
260 #define ASC_SGQ_B_SG_HEAD_QP 5
261 #define ASC_SGQ_B_SG_LIST_CNT 6
262 #define ASC_SGQ_B_SG_CUR_LIST_CNT 7
263 #define ASC_SGQ_LIST_BEG 8
264 #define ASC_DEF_SCSI1_QNG 4
265 #define ASC_MAX_SCSI1_QNG 4
266 #define ASC_DEF_SCSI2_QNG 16
267 #define ASC_MAX_SCSI2_QNG 32
268 #define ASC_TAG_CODE_MASK 0x23
269 #define ASC_STOP_REQ_RISC_STOP 0x01
270 #define ASC_STOP_ACK_RISC_STOP 0x03
271 #define ASC_STOP_CLEAN_UP_BUSY_Q 0x10
272 #define ASC_STOP_CLEAN_UP_DISC_Q 0x20
273 #define ASC_STOP_HOST_REQ_RISC_HALT 0x40
274 #define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
275 #define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
276 #define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID))
277 #define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID)
278 #define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID)
279 #define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
280 #define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6))
281
282 typedef struct asc_scsiq_1 {
283 uchar status;
284 uchar q_no;
285 uchar cntl;
286 uchar sg_queue_cnt;
287 uchar target_id;
288 uchar target_lun;
289 __le32 data_addr;
290 __le32 data_cnt;
291 __le32 sense_addr;
292 uchar sense_len;
293 uchar extra_bytes;
294 } ASC_SCSIQ_1;
295
296 typedef struct asc_scsiq_2 {
297 u32 srb_tag;
298 uchar target_ix;
299 uchar flag;
300 uchar cdb_len;
301 uchar tag_code;
302 ushort vm_id;
303 } ASC_SCSIQ_2;
304
305 typedef struct asc_scsiq_3 {
306 uchar done_stat;
307 uchar host_stat;
308 uchar scsi_stat;
309 uchar scsi_msg;
310 } ASC_SCSIQ_3;
311
312 typedef struct asc_scsiq_4 {
313 uchar cdb[ASC_MAX_CDB_LEN];
314 uchar y_first_sg_list_qp;
315 uchar y_working_sg_qp;
316 uchar y_working_sg_ix;
317 uchar y_res;
318 ushort x_req_count;
319 ushort x_reconnect_rtn;
320 __le32 x_saved_data_addr;
321 __le32 x_saved_data_cnt;
322 } ASC_SCSIQ_4;
323
324 typedef struct asc_q_done_info {
325 ASC_SCSIQ_2 d2;
326 ASC_SCSIQ_3 d3;
327 uchar q_status;
328 uchar q_no;
329 uchar cntl;
330 uchar sense_len;
331 uchar extra_bytes;
332 uchar res;
333 u32 remain_bytes;
334 } ASC_QDONE_INFO;
335
336 typedef struct asc_sg_list {
337 __le32 addr;
338 __le32 bytes;
339 } ASC_SG_LIST;
340
341 typedef struct asc_sg_head {
342 ushort entry_cnt;
343 ushort queue_cnt;
344 ushort entry_to_copy;
345 ushort res;
346 ASC_SG_LIST sg_list[0];
347 } ASC_SG_HEAD;
348
349 typedef struct asc_scsi_q {
350 ASC_SCSIQ_1 q1;
351 ASC_SCSIQ_2 q2;
352 uchar *cdbptr;
353 ASC_SG_HEAD *sg_head;
354 ushort remain_sg_entry_cnt;
355 ushort next_sg_index;
356 } ASC_SCSI_Q;
357
358 typedef struct asc_scsi_req_q {
359 ASC_SCSIQ_1 r1;
360 ASC_SCSIQ_2 r2;
361 uchar *cdbptr;
362 ASC_SG_HEAD *sg_head;
363 uchar *sense_ptr;
364 ASC_SCSIQ_3 r3;
365 uchar cdb[ASC_MAX_CDB_LEN];
366 uchar sense[ASC_MIN_SENSE_LEN];
367 } ASC_SCSI_REQ_Q;
368
369 typedef struct asc_scsi_bios_req_q {
370 ASC_SCSIQ_1 r1;
371 ASC_SCSIQ_2 r2;
372 uchar *cdbptr;
373 ASC_SG_HEAD *sg_head;
374 uchar *sense_ptr;
375 ASC_SCSIQ_3 r3;
376 uchar cdb[ASC_MAX_CDB_LEN];
377 uchar sense[ASC_MIN_SENSE_LEN];
378 } ASC_SCSI_BIOS_REQ_Q;
379
380 typedef struct asc_risc_q {
381 uchar fwd;
382 uchar bwd;
383 ASC_SCSIQ_1 i1;
384 ASC_SCSIQ_2 i2;
385 ASC_SCSIQ_3 i3;
386 ASC_SCSIQ_4 i4;
387 } ASC_RISC_Q;
388
389 typedef struct asc_sg_list_q {
390 uchar seq_no;
391 uchar q_no;
392 uchar cntl;
393 uchar sg_head_qp;
394 uchar sg_list_cnt;
395 uchar sg_cur_list_cnt;
396 } ASC_SG_LIST_Q;
397
398 typedef struct asc_risc_sg_list_q {
399 uchar fwd;
400 uchar bwd;
401 ASC_SG_LIST_Q sg;
402 ASC_SG_LIST sg_list[7];
403 } ASC_RISC_SG_LIST_Q;
404
405 #define ASCQ_ERR_Q_STATUS 0x0D
406 #define ASCQ_ERR_CUR_QNG 0x17
407 #define ASCQ_ERR_SG_Q_LINKS 0x18
408 #define ASCQ_ERR_ISR_RE_ENTRY 0x1A
409 #define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B
410 #define ASCQ_ERR_ISR_ON_CRITICAL 0x1C
411
412 /*
413 * Warning code values are set in ASC_DVC_VAR 'warn_code'.
414 */
415 #define ASC_WARN_NO_ERROR 0x0000
416 #define ASC_WARN_IO_PORT_ROTATE 0x0001
417 #define ASC_WARN_EEPROM_CHKSUM 0x0002
418 #define ASC_WARN_IRQ_MODIFIED 0x0004
419 #define ASC_WARN_AUTO_CONFIG 0x0008
420 #define ASC_WARN_CMD_QNG_CONFLICT 0x0010
421 #define ASC_WARN_EEPROM_RECOVER 0x0020
422 #define ASC_WARN_CFG_MSW_RECOVER 0x0040
423
424 /*
425 * Error code values are set in {ASC/ADV}_DVC_VAR 'err_code'.
426 */
427 #define ASC_IERR_NO_CARRIER 0x0001 /* No more carrier memory */
428 #define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */
429 #define ASC_IERR_SET_PC_ADDR 0x0004
430 #define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */
431 #define ASC_IERR_ILLEGAL_CONNECTION 0x0010 /* Illegal cable connection */
432 #define ASC_IERR_SINGLE_END_DEVICE 0x0020 /* SE device on DIFF bus */
433 #define ASC_IERR_REVERSED_CABLE 0x0040 /* Narrow flat cable reversed */
434 #define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */
435 #define ASC_IERR_HVD_DEVICE 0x0100 /* HVD device on LVD port */
436 #define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */
437 #define ASC_IERR_NO_BUS_TYPE 0x0400
438 #define ASC_IERR_BIST_PRE_TEST 0x0800 /* BIST pre-test error */
439 #define ASC_IERR_BIST_RAM_TEST 0x1000 /* BIST RAM test error */
440 #define ASC_IERR_BAD_CHIPTYPE 0x2000 /* Invalid chip_type setting */
441
442 #define ASC_DEF_MAX_TOTAL_QNG (0xF0)
443 #define ASC_MIN_TAG_Q_PER_DVC (0x04)
444 #define ASC_MIN_FREE_Q (0x02)
445 #define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
446 #define ASC_MAX_TOTAL_QNG 240
447 #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
448 #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8
449 #define ASC_MAX_PCI_INRAM_TOTAL_QNG 20
450 #define ASC_MAX_INRAM_TAG_QNG 16
451 #define ASC_IOADR_GAP 0x10
452 #define ASC_SYN_MAX_OFFSET 0x0F
453 #define ASC_DEF_SDTR_OFFSET 0x0F
454 #define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02
455 #define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
456
457 /* The narrow chip only supports a limited selection of transfer rates.
458 * These are encoded in the range 0..7 or 0..15 depending whether the chip
459 * is Ultra-capable or not. These tables let us convert from one to the other.
460 */
461 static const unsigned char asc_syn_xfer_period[8] = {
462 25, 30, 35, 40, 50, 60, 70, 85
463 };
464
465 static const unsigned char asc_syn_ultra_xfer_period[16] = {
466 12, 19, 25, 32, 38, 44, 50, 57, 63, 69, 75, 82, 88, 94, 100, 107
467 };
468
469 typedef struct ext_msg {
470 uchar msg_type;
471 uchar msg_len;
472 uchar msg_req;
473 union {
474 struct {
475 uchar sdtr_xfer_period;
476 uchar sdtr_req_ack_offset;
477 } sdtr;
478 struct {
479 uchar wdtr_width;
480 } wdtr;
481 struct {
482 uchar mdp_b3;
483 uchar mdp_b2;
484 uchar mdp_b1;
485 uchar mdp_b0;
486 } mdp;
487 } u_ext_msg;
488 uchar res;
489 } EXT_MSG;
490
491 #define xfer_period u_ext_msg.sdtr.sdtr_xfer_period
492 #define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset
493 #define wdtr_width u_ext_msg.wdtr.wdtr_width
494 #define mdp_b3 u_ext_msg.mdp_b3
495 #define mdp_b2 u_ext_msg.mdp_b2
496 #define mdp_b1 u_ext_msg.mdp_b1
497 #define mdp_b0 u_ext_msg.mdp_b0
498
499 typedef struct asc_dvc_cfg {
500 ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
501 ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
502 ASC_SCSI_BIT_ID_TYPE disc_enable;
503 ASC_SCSI_BIT_ID_TYPE sdtr_enable;
504 uchar chip_scsi_id;
505 uchar isa_dma_speed;
506 uchar isa_dma_channel;
507 uchar chip_version;
508 ushort mcode_date;
509 ushort mcode_version;
510 uchar max_tag_qng[ASC_MAX_TID + 1];
511 uchar sdtr_period_offset[ASC_MAX_TID + 1];
512 uchar adapter_info[6];
513 } ASC_DVC_CFG;
514
515 #define ASC_DEF_DVC_CNTL 0xFFFF
516 #define ASC_DEF_CHIP_SCSI_ID 7
517 #define ASC_DEF_ISA_DMA_SPEED 4
518 #define ASC_INIT_STATE_BEG_GET_CFG 0x0001
519 #define ASC_INIT_STATE_END_GET_CFG 0x0002
520 #define ASC_INIT_STATE_BEG_SET_CFG 0x0004
521 #define ASC_INIT_STATE_END_SET_CFG 0x0008
522 #define ASC_INIT_STATE_BEG_LOAD_MC 0x0010
523 #define ASC_INIT_STATE_END_LOAD_MC 0x0020
524 #define ASC_INIT_STATE_BEG_INQUIRY 0x0040
525 #define ASC_INIT_STATE_END_INQUIRY 0x0080
526 #define ASC_INIT_RESET_SCSI_DONE 0x0100
527 #define ASC_INIT_STATE_WITHOUT_EEP 0x8000
528 #define ASC_BUG_FIX_IF_NOT_DWB 0x0001
529 #define ASC_BUG_FIX_ASYN_USE_SYN 0x0002
530 #define ASC_MIN_TAGGED_CMD 7
531 #define ASC_MAX_SCSI_RESET_WAIT 30
532 #define ASC_OVERRUN_BSIZE 64
533
534 struct asc_dvc_var; /* Forward Declaration. */
535
536 typedef struct asc_dvc_var {
537 PortAddr iop_base;
538 ushort err_code;
539 ushort dvc_cntl;
540 ushort bug_fix_cntl;
541 ushort bus_type;
542 ASC_SCSI_BIT_ID_TYPE init_sdtr;
543 ASC_SCSI_BIT_ID_TYPE sdtr_done;
544 ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
545 ASC_SCSI_BIT_ID_TYPE unit_not_ready;
546 ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
547 ASC_SCSI_BIT_ID_TYPE start_motor;
548 uchar *overrun_buf;
549 dma_addr_t overrun_dma;
550 uchar scsi_reset_wait;
551 uchar chip_no;
552 bool is_in_int;
553 uchar max_total_qng;
554 uchar cur_total_qng;
555 uchar in_critical_cnt;
556 uchar last_q_shortage;
557 ushort init_state;
558 uchar cur_dvc_qng[ASC_MAX_TID + 1];
559 uchar max_dvc_qng[ASC_MAX_TID + 1];
560 ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
561 ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
562 const uchar *sdtr_period_tbl;
563 ASC_DVC_CFG *cfg;
564 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
565 char redo_scam;
566 ushort res2;
567 uchar dos_int13_table[ASC_MAX_TID + 1];
568 unsigned int max_dma_count;
569 ASC_SCSI_BIT_ID_TYPE no_scam;
570 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
571 uchar min_sdtr_index;
572 uchar max_sdtr_index;
573 struct asc_board *drv_ptr;
574 unsigned int uc_break;
575 } ASC_DVC_VAR;
576
577 typedef struct asc_dvc_inq_info {
578 uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
579 } ASC_DVC_INQ_INFO;
580
581 typedef struct asc_cap_info {
582 u32 lba;
583 u32 blk_size;
584 } ASC_CAP_INFO;
585
586 typedef struct asc_cap_info_array {
587 ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
588 } ASC_CAP_INFO_ARRAY;
589
590 #define ASC_MCNTL_NO_SEL_TIMEOUT (ushort)0x0001
591 #define ASC_MCNTL_NULL_TARGET (ushort)0x0002
592 #define ASC_CNTL_INITIATOR (ushort)0x0001
593 #define ASC_CNTL_BIOS_GT_1GB (ushort)0x0002
594 #define ASC_CNTL_BIOS_GT_2_DISK (ushort)0x0004
595 #define ASC_CNTL_BIOS_REMOVABLE (ushort)0x0008
596 #define ASC_CNTL_NO_SCAM (ushort)0x0010
597 #define ASC_CNTL_INT_MULTI_Q (ushort)0x0080
598 #define ASC_CNTL_NO_LUN_SUPPORT (ushort)0x0040
599 #define ASC_CNTL_NO_VERIFY_COPY (ushort)0x0100
600 #define ASC_CNTL_RESET_SCSI (ushort)0x0200
601 #define ASC_CNTL_INIT_INQUIRY (ushort)0x0400
602 #define ASC_CNTL_INIT_VERBOSE (ushort)0x0800
603 #define ASC_CNTL_SCSI_PARITY (ushort)0x1000
604 #define ASC_CNTL_BURST_MODE (ushort)0x2000
605 #define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
606 #define ASC_EEP_DVC_CFG_BEG_VL 2
607 #define ASC_EEP_MAX_DVC_ADDR_VL 15
608 #define ASC_EEP_DVC_CFG_BEG 32
609 #define ASC_EEP_MAX_DVC_ADDR 45
610 #define ASC_EEP_MAX_RETRY 20
611
612 /*
613 * These macros keep the chip SCSI id and ISA DMA speed
614 * bitfields in board order. C bitfields aren't portable
615 * between big and little-endian platforms so they are
616 * not used.
617 */
618
619 #define ASC_EEP_GET_CHIP_ID(cfg) ((cfg)->id_speed & 0x0f)
620 #define ASC_EEP_GET_DMA_SPD(cfg) (((cfg)->id_speed & 0xf0) >> 4)
621 #define ASC_EEP_SET_CHIP_ID(cfg, sid) \
622 ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
623 #define ASC_EEP_SET_DMA_SPD(cfg, spd) \
624 ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
625
626 typedef struct asceep_config {
627 ushort cfg_lsw;
628 ushort cfg_msw;
629 uchar init_sdtr;
630 uchar disc_enable;
631 uchar use_cmd_qng;
632 uchar start_motor;
633 uchar max_total_qng;
634 uchar max_tag_qng;
635 uchar bios_scan;
636 uchar power_up_wait;
637 uchar no_scam;
638 uchar id_speed; /* low order 4 bits is chip scsi id */
639 /* high order 4 bits is isa dma speed */
640 uchar dos_int13_table[ASC_MAX_TID + 1];
641 uchar adapter_info[6];
642 ushort cntl;
643 ushort chksum;
644 } ASCEEP_CONFIG;
645
646 #define ASC_EEP_CMD_READ 0x80
647 #define ASC_EEP_CMD_WRITE 0x40
648 #define ASC_EEP_CMD_WRITE_ABLE 0x30
649 #define ASC_EEP_CMD_WRITE_DISABLE 0x00
650 #define ASCV_MSGOUT_BEG 0x0000
651 #define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
652 #define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
653 #define ASCV_BREAK_SAVED_CODE (ushort)0x0006
654 #define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8)
655 #define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3)
656 #define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4)
657 #define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8)
658 #define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8)
659 #define ASCV_MAX_DVC_QNG_BEG (ushort)0x0020
660 #define ASCV_BREAK_ADDR (ushort)0x0028
661 #define ASCV_BREAK_NOTIFY_COUNT (ushort)0x002A
662 #define ASCV_BREAK_CONTROL (ushort)0x002C
663 #define ASCV_BREAK_HIT_COUNT (ushort)0x002E
664
665 #define ASCV_ASCDVC_ERR_CODE_W (ushort)0x0030
666 #define ASCV_MCODE_CHKSUM_W (ushort)0x0032
667 #define ASCV_MCODE_SIZE_W (ushort)0x0034
668 #define ASCV_STOP_CODE_B (ushort)0x0036
669 #define ASCV_DVC_ERR_CODE_B (ushort)0x0037
670 #define ASCV_OVERRUN_PADDR_D (ushort)0x0038
671 #define ASCV_OVERRUN_BSIZE_D (ushort)0x003C
672 #define ASCV_HALTCODE_W (ushort)0x0040
673 #define ASCV_CHKSUM_W (ushort)0x0042
674 #define ASCV_MC_DATE_W (ushort)0x0044
675 #define ASCV_MC_VER_W (ushort)0x0046
676 #define ASCV_NEXTRDY_B (ushort)0x0048
677 #define ASCV_DONENEXT_B (ushort)0x0049
678 #define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
679 #define ASCV_SCSIBUSY_B (ushort)0x004B
680 #define ASCV_Q_DONE_IN_PROGRESS_B (ushort)0x004C
681 #define ASCV_CURCDB_B (ushort)0x004D
682 #define ASCV_RCLUN_B (ushort)0x004E
683 #define ASCV_BUSY_QHEAD_B (ushort)0x004F
684 #define ASCV_DISC1_QHEAD_B (ushort)0x0050
685 #define ASCV_DISC_ENABLE_B (ushort)0x0052
686 #define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
687 #define ASCV_HOSTSCSI_ID_B (ushort)0x0055
688 #define ASCV_MCODE_CNTL_B (ushort)0x0056
689 #define ASCV_NULL_TARGET_B (ushort)0x0057
690 #define ASCV_FREE_Q_HEAD_W (ushort)0x0058
691 #define ASCV_DONE_Q_TAIL_W (ushort)0x005A
692 #define ASCV_FREE_Q_HEAD_B (ushort)(ASCV_FREE_Q_HEAD_W+1)
693 #define ASCV_DONE_Q_TAIL_B (ushort)(ASCV_DONE_Q_TAIL_W+1)
694 #define ASCV_HOST_FLAG_B (ushort)0x005D
695 #define ASCV_TOTAL_READY_Q_B (ushort)0x0064
696 #define ASCV_VER_SERIAL_B (ushort)0x0065
697 #define ASCV_HALTCODE_SAVED_W (ushort)0x0066
698 #define ASCV_WTM_FLAG_B (ushort)0x0068
699 #define ASCV_RISC_FLAG_B (ushort)0x006A
700 #define ASCV_REQ_SG_LIST_QP (ushort)0x006B
701 #define ASC_HOST_FLAG_IN_ISR 0x01
702 #define ASC_HOST_FLAG_ACK_INT 0x02
703 #define ASC_RISC_FLAG_GEN_INT 0x01
704 #define ASC_RISC_FLAG_REQ_SG_LIST 0x02
705 #define IOP_CTRL (0x0F)
706 #define IOP_STATUS (0x0E)
707 #define IOP_INT_ACK IOP_STATUS
708 #define IOP_REG_IFC (0x0D)
709 #define IOP_SYN_OFFSET (0x0B)
710 #define IOP_EXTRA_CONTROL (0x0D)
711 #define IOP_REG_PC (0x0C)
712 #define IOP_RAM_ADDR (0x0A)
713 #define IOP_RAM_DATA (0x08)
714 #define IOP_EEP_DATA (0x06)
715 #define IOP_EEP_CMD (0x07)
716 #define IOP_VERSION (0x03)
717 #define IOP_CONFIG_HIGH (0x04)
718 #define IOP_CONFIG_LOW (0x02)
719 #define IOP_SIG_BYTE (0x01)
720 #define IOP_SIG_WORD (0x00)
721 #define IOP_REG_DC1 (0x0E)
722 #define IOP_REG_DC0 (0x0C)
723 #define IOP_REG_SB (0x0B)
724 #define IOP_REG_DA1 (0x0A)
725 #define IOP_REG_DA0 (0x08)
726 #define IOP_REG_SC (0x09)
727 #define IOP_DMA_SPEED (0x07)
728 #define IOP_REG_FLAG (0x07)
729 #define IOP_FIFO_H (0x06)
730 #define IOP_FIFO_L (0x04)
731 #define IOP_REG_ID (0x05)
732 #define IOP_REG_QP (0x03)
733 #define IOP_REG_IH (0x02)
734 #define IOP_REG_IX (0x01)
735 #define IOP_REG_AX (0x00)
736 #define IFC_REG_LOCK (0x00)
737 #define IFC_REG_UNLOCK (0x09)
738 #define IFC_WR_EN_FILTER (0x10)
739 #define IFC_RD_NO_EEPROM (0x10)
740 #define IFC_SLEW_RATE (0x20)
741 #define IFC_ACT_NEG (0x40)
742 #define IFC_INP_FILTER (0x80)
743 #define IFC_INIT_DEFAULT (IFC_ACT_NEG | IFC_REG_UNLOCK)
744 #define SC_SEL (uchar)(0x80)
745 #define SC_BSY (uchar)(0x40)
746 #define SC_ACK (uchar)(0x20)
747 #define SC_REQ (uchar)(0x10)
748 #define SC_ATN (uchar)(0x08)
749 #define SC_IO (uchar)(0x04)
750 #define SC_CD (uchar)(0x02)
751 #define SC_MSG (uchar)(0x01)
752 #define SEC_SCSI_CTL (uchar)(0x80)
753 #define SEC_ACTIVE_NEGATE (uchar)(0x40)
754 #define SEC_SLEW_RATE (uchar)(0x20)
755 #define SEC_ENABLE_FILTER (uchar)(0x10)
756 #define ASC_HALT_EXTMSG_IN (ushort)0x8000
757 #define ASC_HALT_CHK_CONDITION (ushort)0x8100
758 #define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
759 #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX (ushort)0x8300
760 #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX (ushort)0x8400
761 #define ASC_HALT_SDTR_REJECTED (ushort)0x4000
762 #define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
763 #define ASC_MAX_QNO 0xF8
764 #define ASC_DATA_SEC_BEG (ushort)0x0080
765 #define ASC_DATA_SEC_END (ushort)0x0080
766 #define ASC_CODE_SEC_BEG (ushort)0x0080
767 #define ASC_CODE_SEC_END (ushort)0x0080
768 #define ASC_QADR_BEG (0x4000)
769 #define ASC_QADR_USED (ushort)(ASC_MAX_QNO * 64)
770 #define ASC_QADR_END (ushort)0x7FFF
771 #define ASC_QLAST_ADR (ushort)0x7FC0
772 #define ASC_QBLK_SIZE 0x40
773 #define ASC_BIOS_DATA_QBEG 0xF8
774 #define ASC_MIN_ACTIVE_QNO 0x01
775 #define ASC_QLINK_END 0xFF
776 #define ASC_EEPROM_WORDS 0x10
777 #define ASC_MAX_MGS_LEN 0x10
778 #define ASC_BIOS_ADDR_DEF 0xDC00
779 #define ASC_BIOS_SIZE 0x3800
780 #define ASC_BIOS_RAM_OFF 0x3800
781 #define ASC_BIOS_RAM_SIZE 0x800
782 #define ASC_BIOS_MIN_ADDR 0xC000
783 #define ASC_BIOS_MAX_ADDR 0xEC00
784 #define ASC_BIOS_BANK_SIZE 0x0400
785 #define ASC_MCODE_START_ADDR 0x0080
786 #define ASC_CFG0_HOST_INT_ON 0x0020
787 #define ASC_CFG0_BIOS_ON 0x0040
788 #define ASC_CFG0_VERA_BURST_ON 0x0080
789 #define ASC_CFG0_SCSI_PARITY_ON 0x0800
790 #define ASC_CFG1_SCSI_TARGET_ON 0x0080
791 #define ASC_CFG1_LRAM_8BITS_ON 0x0800
792 #define ASC_CFG_MSW_CLR_MASK 0x3080
793 #define CSW_TEST1 (ASC_CS_TYPE)0x8000
794 #define CSW_AUTO_CONFIG (ASC_CS_TYPE)0x4000
795 #define CSW_RESERVED1 (ASC_CS_TYPE)0x2000
796 #define CSW_IRQ_WRITTEN (ASC_CS_TYPE)0x1000
797 #define CSW_33MHZ_SELECTED (ASC_CS_TYPE)0x0800
798 #define CSW_TEST2 (ASC_CS_TYPE)0x0400
799 #define CSW_TEST3 (ASC_CS_TYPE)0x0200
800 #define CSW_RESERVED2 (ASC_CS_TYPE)0x0100
801 #define CSW_DMA_DONE (ASC_CS_TYPE)0x0080
802 #define CSW_FIFO_RDY (ASC_CS_TYPE)0x0040
803 #define CSW_EEP_READ_DONE (ASC_CS_TYPE)0x0020
804 #define CSW_HALTED (ASC_CS_TYPE)0x0010
805 #define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
806 #define CSW_PARITY_ERR (ASC_CS_TYPE)0x0004
807 #define CSW_SCSI_RESET_LATCH (ASC_CS_TYPE)0x0002
808 #define CSW_INT_PENDING (ASC_CS_TYPE)0x0001
809 #define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
810 #define CIW_INT_ACK (ASC_CS_TYPE)0x0100
811 #define CIW_TEST1 (ASC_CS_TYPE)0x0200
812 #define CIW_TEST2 (ASC_CS_TYPE)0x0400
813 #define CIW_SEL_33MHZ (ASC_CS_TYPE)0x0800
814 #define CIW_IRQ_ACT (ASC_CS_TYPE)0x1000
815 #define CC_CHIP_RESET (uchar)0x80
816 #define CC_SCSI_RESET (uchar)0x40
817 #define CC_HALT (uchar)0x20
818 #define CC_SINGLE_STEP (uchar)0x10
819 #define CC_DMA_ABLE (uchar)0x08
820 #define CC_TEST (uchar)0x04
821 #define CC_BANK_ONE (uchar)0x02
822 #define CC_DIAG (uchar)0x01
823 #define ASC_1000_ID0W 0x04C1
824 #define ASC_1000_ID0W_FIX 0x00C1
825 #define ASC_1000_ID1B 0x25
826 #define ASC_EISA_REV_IOP_MASK (0x0C83)
827 #define ASC_EISA_CFG_IOP_MASK (0x0C86)
828 #define ASC_GET_EISA_SLOT(iop) (PortAddr)((iop) & 0xF000)
829 #define INS_HALTINT (ushort)0x6281
830 #define INS_HALT (ushort)0x6280
831 #define INS_SINT (ushort)0x6200
832 #define INS_RFLAG_WTM (ushort)0x7380
833 #define ASC_MC_SAVE_CODE_WSIZE 0x500
834 #define ASC_MC_SAVE_DATA_WSIZE 0x40
835
836 typedef struct asc_mc_saved {
837 ushort data[ASC_MC_SAVE_DATA_WSIZE];
838 ushort code[ASC_MC_SAVE_CODE_WSIZE];
839 } ASC_MC_SAVED;
840
841 #define AscGetQDoneInProgress(port) AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
842 #define AscPutQDoneInProgress(port, val) AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
843 #define AscGetVarFreeQHead(port) AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
844 #define AscGetVarDoneQTail(port) AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
845 #define AscPutVarFreeQHead(port, val) AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
846 #define AscPutVarDoneQTail(port, val) AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
847 #define AscGetRiscVarFreeQHead(port) AscReadLramByte((port), ASCV_NEXTRDY_B)
848 #define AscGetRiscVarDoneQTail(port) AscReadLramByte((port), ASCV_DONENEXT_B)
849 #define AscPutRiscVarFreeQHead(port, val) AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
850 #define AscPutRiscVarDoneQTail(port, val) AscWriteLramByte((port), ASCV_DONENEXT_B, val)
851 #define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data))
852 #define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id))
853 #define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data)
854 #define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id))
855 #define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE)
856 #define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD)
857 #define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION)
858 #define AscGetChipCfgLsw(port) (ushort)inpw((port)+IOP_CONFIG_LOW)
859 #define AscGetChipCfgMsw(port) (ushort)inpw((port)+IOP_CONFIG_HIGH)
860 #define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data)
861 #define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data)
862 #define AscGetChipEEPCmd(port) (uchar)inp((port)+IOP_EEP_CMD)
863 #define AscSetChipEEPCmd(port, data) outp((port)+IOP_EEP_CMD, data)
864 #define AscGetChipEEPData(port) (ushort)inpw((port)+IOP_EEP_DATA)
865 #define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data)
866 #define AscGetChipLramAddr(port) (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
867 #define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
868 #define AscGetChipLramData(port) (ushort)inpw((port)+IOP_RAM_DATA)
869 #define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data)
870 #define AscGetChipIFC(port) (uchar)inp((port)+IOP_REG_IFC)
871 #define AscSetChipIFC(port, data) outp((port)+IOP_REG_IFC, data)
872 #define AscGetChipStatus(port) (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
873 #define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val)
874 #define AscGetChipControl(port) (uchar)inp((port)+IOP_CTRL)
875 #define AscSetChipControl(port, cc_val) outp((port)+IOP_CTRL, cc_val)
876 #define AscGetChipSyn(port) (uchar)inp((port)+IOP_SYN_OFFSET)
877 #define AscSetChipSyn(port, data) outp((port)+IOP_SYN_OFFSET, data)
878 #define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data)
879 #define AscGetPCAddr(port) (ushort)inpw((port)+IOP_REG_PC)
880 #define AscIsIntPending(port) (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
881 #define AscGetChipScsiID(port) ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
882 #define AscGetExtraControl(port) (uchar)inp((port)+IOP_EXTRA_CONTROL)
883 #define AscSetExtraControl(port, data) outp((port)+IOP_EXTRA_CONTROL, data)
884 #define AscReadChipAX(port) (ushort)inpw((port)+IOP_REG_AX)
885 #define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data)
886 #define AscReadChipIX(port) (uchar)inp((port)+IOP_REG_IX)
887 #define AscWriteChipIX(port, data) outp((port)+IOP_REG_IX, data)
888 #define AscReadChipIH(port) (ushort)inpw((port)+IOP_REG_IH)
889 #define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data)
890 #define AscReadChipQP(port) (uchar)inp((port)+IOP_REG_QP)
891 #define AscWriteChipQP(port, data) outp((port)+IOP_REG_QP, data)
892 #define AscReadChipFIFO_L(port) (ushort)inpw((port)+IOP_REG_FIFO_L)
893 #define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data)
894 #define AscReadChipFIFO_H(port) (ushort)inpw((port)+IOP_REG_FIFO_H)
895 #define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data)
896 #define AscReadChipDmaSpeed(port) (uchar)inp((port)+IOP_DMA_SPEED)
897 #define AscWriteChipDmaSpeed(port, data) outp((port)+IOP_DMA_SPEED, data)
898 #define AscReadChipDA0(port) (ushort)inpw((port)+IOP_REG_DA0)
899 #define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data)
900 #define AscReadChipDA1(port) (ushort)inpw((port)+IOP_REG_DA1)
901 #define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data)
902 #define AscReadChipDC0(port) (ushort)inpw((port)+IOP_REG_DC0)
903 #define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data)
904 #define AscReadChipDC1(port) (ushort)inpw((port)+IOP_REG_DC1)
905 #define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data)
906 #define AscReadChipDvcID(port) (uchar)inp((port)+IOP_REG_ID)
907 #define AscWriteChipDvcID(port, data) outp((port)+IOP_REG_ID, data)
908
909 /*
910 * These macros are used to convert a virtual address to a
911 * 32-bit value. This currently can be used on Linux Alpha
912 * which uses 64-bit virtual address but a 32-bit bus address.
913 * This is likely to break in the future, but doing this now
914 * will give us time to change the HW and FW to handle 64-bit
915 * addresses.
916 */
917 #define ADV_U32_TO_VADDR bus_to_virt
918
919 #define AdvPortAddr void __iomem * /* Virtual memory address size */
920
921 /*
922 * Define Adv Library required memory access macros.
923 */
924 #define ADV_MEM_READB(addr) readb(addr)
925 #define ADV_MEM_READW(addr) readw(addr)
926 #define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
927 #define ADV_MEM_WRITEW(addr, word) writew(word, addr)
928 #define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
929
930 /*
931 * Define total number of simultaneous maximum element scatter-gather
932 * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
933 * maximum number of outstanding commands per wide host adapter. Each
934 * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
935 * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
936 * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
937 * structures or 255 scatter-gather elements.
938 */
939 #define ADV_TOT_SG_BLOCK ASC_DEF_MAX_HOST_QNG
940
941 /*
942 * Define maximum number of scatter-gather elements per request.
943 */
944 #define ADV_MAX_SG_LIST 255
945 #define NO_OF_SG_PER_BLOCK 15
946
947 #define ADV_EEP_DVC_CFG_BEGIN (0x00)
948 #define ADV_EEP_DVC_CFG_END (0x15)
949 #define ADV_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */
950 #define ADV_EEP_MAX_WORD_ADDR (0x1E)
951
952 #define ADV_EEP_DELAY_MS 100
953
954 #define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */
955 #define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */
956 /*
957 * For the ASC3550 Bit 13 is Termination Polarity control bit.
958 * For later ICs Bit 13 controls whether the CIS (Card Information
959 * Service Section) is loaded from EEPROM.
960 */
961 #define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */
962 #define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */
963 /*
964 * ASC38C1600 Bit 11
965 *
966 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
967 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
968 * Function 0 will specify INT B.
969 *
970 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
971 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
972 * Function 1 will specify INT A.
973 */
974 #define ADV_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */
975
976 typedef struct adveep_3550_config {
977 /* Word Offset, Description */
978
979 ushort cfg_lsw; /* 00 power up initialization */
980 /* bit 13 set - Term Polarity Control */
981 /* bit 14 set - BIOS Enable */
982 /* bit 15 set - Big Endian Mode */
983 ushort cfg_msw; /* 01 unused */
984 ushort disc_enable; /* 02 disconnect enable */
985 ushort wdtr_able; /* 03 Wide DTR able */
986 ushort sdtr_able; /* 04 Synchronous DTR able */
987 ushort start_motor; /* 05 send start up motor */
988 ushort tagqng_able; /* 06 tag queuing able */
989 ushort bios_scan; /* 07 BIOS device control */
990 ushort scam_tolerant; /* 08 no scam */
991
992 uchar adapter_scsi_id; /* 09 Host Adapter ID */
993 uchar bios_boot_delay; /* power up wait */
994
995 uchar scsi_reset_delay; /* 10 reset delay */
996 uchar bios_id_lun; /* first boot device scsi id & lun */
997 /* high nibble is lun */
998 /* low nibble is scsi id */
999
1000 uchar termination; /* 11 0 - automatic */
1001 /* 1 - low off / high off */
1002 /* 2 - low off / high on */
1003 /* 3 - low on / high on */
1004 /* There is no low on / high off */
1005
1006 uchar reserved1; /* reserved byte (not used) */
1007
1008 ushort bios_ctrl; /* 12 BIOS control bits */
1009 /* bit 0 BIOS don't act as initiator. */
1010 /* bit 1 BIOS > 1 GB support */
1011 /* bit 2 BIOS > 2 Disk Support */
1012 /* bit 3 BIOS don't support removables */
1013 /* bit 4 BIOS support bootable CD */
1014 /* bit 5 BIOS scan enabled */
1015 /* bit 6 BIOS support multiple LUNs */
1016 /* bit 7 BIOS display of message */
1017 /* bit 8 SCAM disabled */
1018 /* bit 9 Reset SCSI bus during init. */
1019 /* bit 10 */
1020 /* bit 11 No verbose initialization. */
1021 /* bit 12 SCSI parity enabled */
1022 /* bit 13 */
1023 /* bit 14 */
1024 /* bit 15 */
1025 ushort ultra_able; /* 13 ULTRA speed able */
1026 ushort reserved2; /* 14 reserved */
1027 uchar max_host_qng; /* 15 maximum host queuing */
1028 uchar max_dvc_qng; /* maximum per device queuing */
1029 ushort dvc_cntl; /* 16 control bit for driver */
1030 ushort bug_fix; /* 17 control bit for bug fix */
1031 ushort serial_number_word1; /* 18 Board serial number word 1 */
1032 ushort serial_number_word2; /* 19 Board serial number word 2 */
1033 ushort serial_number_word3; /* 20 Board serial number word 3 */
1034 ushort check_sum; /* 21 EEP check sum */
1035 uchar oem_name[16]; /* 22 OEM name */
1036 ushort dvc_err_code; /* 30 last device driver error code */
1037 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1038 ushort adv_err_addr; /* 32 last uc error address */
1039 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1040 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1041 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1042 ushort num_of_err; /* 36 number of error */
1043 } ADVEEP_3550_CONFIG;
1044
1045 typedef struct adveep_38C0800_config {
1046 /* Word Offset, Description */
1047
1048 ushort cfg_lsw; /* 00 power up initialization */
1049 /* bit 13 set - Load CIS */
1050 /* bit 14 set - BIOS Enable */
1051 /* bit 15 set - Big Endian Mode */
1052 ushort cfg_msw; /* 01 unused */
1053 ushort disc_enable; /* 02 disconnect enable */
1054 ushort wdtr_able; /* 03 Wide DTR able */
1055 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1056 ushort start_motor; /* 05 send start up motor */
1057 ushort tagqng_able; /* 06 tag queuing able */
1058 ushort bios_scan; /* 07 BIOS device control */
1059 ushort scam_tolerant; /* 08 no scam */
1060
1061 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1062 uchar bios_boot_delay; /* power up wait */
1063
1064 uchar scsi_reset_delay; /* 10 reset delay */
1065 uchar bios_id_lun; /* first boot device scsi id & lun */
1066 /* high nibble is lun */
1067 /* low nibble is scsi id */
1068
1069 uchar termination_se; /* 11 0 - automatic */
1070 /* 1 - low off / high off */
1071 /* 2 - low off / high on */
1072 /* 3 - low on / high on */
1073 /* There is no low on / high off */
1074
1075 uchar termination_lvd; /* 11 0 - automatic */
1076 /* 1 - low off / high off */
1077 /* 2 - low off / high on */
1078 /* 3 - low on / high on */
1079 /* There is no low on / high off */
1080
1081 ushort bios_ctrl; /* 12 BIOS control bits */
1082 /* bit 0 BIOS don't act as initiator. */
1083 /* bit 1 BIOS > 1 GB support */
1084 /* bit 2 BIOS > 2 Disk Support */
1085 /* bit 3 BIOS don't support removables */
1086 /* bit 4 BIOS support bootable CD */
1087 /* bit 5 BIOS scan enabled */
1088 /* bit 6 BIOS support multiple LUNs */
1089 /* bit 7 BIOS display of message */
1090 /* bit 8 SCAM disabled */
1091 /* bit 9 Reset SCSI bus during init. */
1092 /* bit 10 */
1093 /* bit 11 No verbose initialization. */
1094 /* bit 12 SCSI parity enabled */
1095 /* bit 13 */
1096 /* bit 14 */
1097 /* bit 15 */
1098 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1099 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1100 uchar max_host_qng; /* 15 maximum host queueing */
1101 uchar max_dvc_qng; /* maximum per device queuing */
1102 ushort dvc_cntl; /* 16 control bit for driver */
1103 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1104 ushort serial_number_word1; /* 18 Board serial number word 1 */
1105 ushort serial_number_word2; /* 19 Board serial number word 2 */
1106 ushort serial_number_word3; /* 20 Board serial number word 3 */
1107 ushort check_sum; /* 21 EEP check sum */
1108 uchar oem_name[16]; /* 22 OEM name */
1109 ushort dvc_err_code; /* 30 last device driver error code */
1110 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1111 ushort adv_err_addr; /* 32 last uc error address */
1112 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1113 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1114 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1115 ushort reserved36; /* 36 reserved */
1116 ushort reserved37; /* 37 reserved */
1117 ushort reserved38; /* 38 reserved */
1118 ushort reserved39; /* 39 reserved */
1119 ushort reserved40; /* 40 reserved */
1120 ushort reserved41; /* 41 reserved */
1121 ushort reserved42; /* 42 reserved */
1122 ushort reserved43; /* 43 reserved */
1123 ushort reserved44; /* 44 reserved */
1124 ushort reserved45; /* 45 reserved */
1125 ushort reserved46; /* 46 reserved */
1126 ushort reserved47; /* 47 reserved */
1127 ushort reserved48; /* 48 reserved */
1128 ushort reserved49; /* 49 reserved */
1129 ushort reserved50; /* 50 reserved */
1130 ushort reserved51; /* 51 reserved */
1131 ushort reserved52; /* 52 reserved */
1132 ushort reserved53; /* 53 reserved */
1133 ushort reserved54; /* 54 reserved */
1134 ushort reserved55; /* 55 reserved */
1135 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1136 ushort cisprt_msw; /* 57 CIS PTR MSW */
1137 ushort subsysvid; /* 58 SubSystem Vendor ID */
1138 ushort subsysid; /* 59 SubSystem ID */
1139 ushort reserved60; /* 60 reserved */
1140 ushort reserved61; /* 61 reserved */
1141 ushort reserved62; /* 62 reserved */
1142 ushort reserved63; /* 63 reserved */
1143 } ADVEEP_38C0800_CONFIG;
1144
1145 typedef struct adveep_38C1600_config {
1146 /* Word Offset, Description */
1147
1148 ushort cfg_lsw; /* 00 power up initialization */
1149 /* bit 11 set - Func. 0 INTB, Func. 1 INTA */
1150 /* clear - Func. 0 INTA, Func. 1 INTB */
1151 /* bit 13 set - Load CIS */
1152 /* bit 14 set - BIOS Enable */
1153 /* bit 15 set - Big Endian Mode */
1154 ushort cfg_msw; /* 01 unused */
1155 ushort disc_enable; /* 02 disconnect enable */
1156 ushort wdtr_able; /* 03 Wide DTR able */
1157 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1158 ushort start_motor; /* 05 send start up motor */
1159 ushort tagqng_able; /* 06 tag queuing able */
1160 ushort bios_scan; /* 07 BIOS device control */
1161 ushort scam_tolerant; /* 08 no scam */
1162
1163 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1164 uchar bios_boot_delay; /* power up wait */
1165
1166 uchar scsi_reset_delay; /* 10 reset delay */
1167 uchar bios_id_lun; /* first boot device scsi id & lun */
1168 /* high nibble is lun */
1169 /* low nibble is scsi id */
1170
1171 uchar termination_se; /* 11 0 - automatic */
1172 /* 1 - low off / high off */
1173 /* 2 - low off / high on */
1174 /* 3 - low on / high on */
1175 /* There is no low on / high off */
1176
1177 uchar termination_lvd; /* 11 0 - automatic */
1178 /* 1 - low off / high off */
1179 /* 2 - low off / high on */
1180 /* 3 - low on / high on */
1181 /* There is no low on / high off */
1182
1183 ushort bios_ctrl; /* 12 BIOS control bits */
1184 /* bit 0 BIOS don't act as initiator. */
1185 /* bit 1 BIOS > 1 GB support */
1186 /* bit 2 BIOS > 2 Disk Support */
1187 /* bit 3 BIOS don't support removables */
1188 /* bit 4 BIOS support bootable CD */
1189 /* bit 5 BIOS scan enabled */
1190 /* bit 6 BIOS support multiple LUNs */
1191 /* bit 7 BIOS display of message */
1192 /* bit 8 SCAM disabled */
1193 /* bit 9 Reset SCSI bus during init. */
1194 /* bit 10 Basic Integrity Checking disabled */
1195 /* bit 11 No verbose initialization. */
1196 /* bit 12 SCSI parity enabled */
1197 /* bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
1198 /* bit 14 */
1199 /* bit 15 */
1200 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1201 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1202 uchar max_host_qng; /* 15 maximum host queueing */
1203 uchar max_dvc_qng; /* maximum per device queuing */
1204 ushort dvc_cntl; /* 16 control bit for driver */
1205 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1206 ushort serial_number_word1; /* 18 Board serial number word 1 */
1207 ushort serial_number_word2; /* 19 Board serial number word 2 */
1208 ushort serial_number_word3; /* 20 Board serial number word 3 */
1209 ushort check_sum; /* 21 EEP check sum */
1210 uchar oem_name[16]; /* 22 OEM name */
1211 ushort dvc_err_code; /* 30 last device driver error code */
1212 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1213 ushort adv_err_addr; /* 32 last uc error address */
1214 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1215 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1216 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1217 ushort reserved36; /* 36 reserved */
1218 ushort reserved37; /* 37 reserved */
1219 ushort reserved38; /* 38 reserved */
1220 ushort reserved39; /* 39 reserved */
1221 ushort reserved40; /* 40 reserved */
1222 ushort reserved41; /* 41 reserved */
1223 ushort reserved42; /* 42 reserved */
1224 ushort reserved43; /* 43 reserved */
1225 ushort reserved44; /* 44 reserved */
1226 ushort reserved45; /* 45 reserved */
1227 ushort reserved46; /* 46 reserved */
1228 ushort reserved47; /* 47 reserved */
1229 ushort reserved48; /* 48 reserved */
1230 ushort reserved49; /* 49 reserved */
1231 ushort reserved50; /* 50 reserved */
1232 ushort reserved51; /* 51 reserved */
1233 ushort reserved52; /* 52 reserved */
1234 ushort reserved53; /* 53 reserved */
1235 ushort reserved54; /* 54 reserved */
1236 ushort reserved55; /* 55 reserved */
1237 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1238 ushort cisprt_msw; /* 57 CIS PTR MSW */
1239 ushort subsysvid; /* 58 SubSystem Vendor ID */
1240 ushort subsysid; /* 59 SubSystem ID */
1241 ushort reserved60; /* 60 reserved */
1242 ushort reserved61; /* 61 reserved */
1243 ushort reserved62; /* 62 reserved */
1244 ushort reserved63; /* 63 reserved */
1245 } ADVEEP_38C1600_CONFIG;
1246
1247 /*
1248 * EEPROM Commands
1249 */
1250 #define ASC_EEP_CMD_DONE 0x0200
1251
1252 /* bios_ctrl */
1253 #define BIOS_CTRL_BIOS 0x0001
1254 #define BIOS_CTRL_EXTENDED_XLAT 0x0002
1255 #define BIOS_CTRL_GT_2_DISK 0x0004
1256 #define BIOS_CTRL_BIOS_REMOVABLE 0x0008
1257 #define BIOS_CTRL_BOOTABLE_CD 0x0010
1258 #define BIOS_CTRL_MULTIPLE_LUN 0x0040
1259 #define BIOS_CTRL_DISPLAY_MSG 0x0080
1260 #define BIOS_CTRL_NO_SCAM 0x0100
1261 #define BIOS_CTRL_RESET_SCSI_BUS 0x0200
1262 #define BIOS_CTRL_INIT_VERBOSE 0x0800
1263 #define BIOS_CTRL_SCSI_PARITY 0x1000
1264 #define BIOS_CTRL_AIPP_DIS 0x2000
1265
1266 #define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */
1267
1268 #define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1269
1270 /*
1271 * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
1272 * a special 16K Adv Library and Microcode version. After the issue is
1273 * resolved, should restore 32K support.
1274 *
1275 * #define ADV_38C1600_MEMSIZE 0x8000L * 32 KB Internal Memory *
1276 */
1277 #define ADV_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1278
1279 /*
1280 * Byte I/O register address from base of 'iop_base'.
1281 */
1282 #define IOPB_INTR_STATUS_REG 0x00
1283 #define IOPB_CHIP_ID_1 0x01
1284 #define IOPB_INTR_ENABLES 0x02
1285 #define IOPB_CHIP_TYPE_REV 0x03
1286 #define IOPB_RES_ADDR_4 0x04
1287 #define IOPB_RES_ADDR_5 0x05
1288 #define IOPB_RAM_DATA 0x06
1289 #define IOPB_RES_ADDR_7 0x07
1290 #define IOPB_FLAG_REG 0x08
1291 #define IOPB_RES_ADDR_9 0x09
1292 #define IOPB_RISC_CSR 0x0A
1293 #define IOPB_RES_ADDR_B 0x0B
1294 #define IOPB_RES_ADDR_C 0x0C
1295 #define IOPB_RES_ADDR_D 0x0D
1296 #define IOPB_SOFT_OVER_WR 0x0E
1297 #define IOPB_RES_ADDR_F 0x0F
1298 #define IOPB_MEM_CFG 0x10
1299 #define IOPB_RES_ADDR_11 0x11
1300 #define IOPB_GPIO_DATA 0x12
1301 #define IOPB_RES_ADDR_13 0x13
1302 #define IOPB_FLASH_PAGE 0x14
1303 #define IOPB_RES_ADDR_15 0x15
1304 #define IOPB_GPIO_CNTL 0x16
1305 #define IOPB_RES_ADDR_17 0x17
1306 #define IOPB_FLASH_DATA 0x18
1307 #define IOPB_RES_ADDR_19 0x19
1308 #define IOPB_RES_ADDR_1A 0x1A
1309 #define IOPB_RES_ADDR_1B 0x1B
1310 #define IOPB_RES_ADDR_1C 0x1C
1311 #define IOPB_RES_ADDR_1D 0x1D
1312 #define IOPB_RES_ADDR_1E 0x1E
1313 #define IOPB_RES_ADDR_1F 0x1F
1314 #define IOPB_DMA_CFG0 0x20
1315 #define IOPB_DMA_CFG1 0x21
1316 #define IOPB_TICKLE 0x22
1317 #define IOPB_DMA_REG_WR 0x23
1318 #define IOPB_SDMA_STATUS 0x24
1319 #define IOPB_SCSI_BYTE_CNT 0x25
1320 #define IOPB_HOST_BYTE_CNT 0x26
1321 #define IOPB_BYTE_LEFT_TO_XFER 0x27
1322 #define IOPB_BYTE_TO_XFER_0 0x28
1323 #define IOPB_BYTE_TO_XFER_1 0x29
1324 #define IOPB_BYTE_TO_XFER_2 0x2A
1325 #define IOPB_BYTE_TO_XFER_3 0x2B
1326 #define IOPB_ACC_GRP 0x2C
1327 #define IOPB_RES_ADDR_2D 0x2D
1328 #define IOPB_DEV_ID 0x2E
1329 #define IOPB_RES_ADDR_2F 0x2F
1330 #define IOPB_SCSI_DATA 0x30
1331 #define IOPB_RES_ADDR_31 0x31
1332 #define IOPB_RES_ADDR_32 0x32
1333 #define IOPB_SCSI_DATA_HSHK 0x33
1334 #define IOPB_SCSI_CTRL 0x34
1335 #define IOPB_RES_ADDR_35 0x35
1336 #define IOPB_RES_ADDR_36 0x36
1337 #define IOPB_RES_ADDR_37 0x37
1338 #define IOPB_RAM_BIST 0x38
1339 #define IOPB_PLL_TEST 0x39
1340 #define IOPB_PCI_INT_CFG 0x3A
1341 #define IOPB_RES_ADDR_3B 0x3B
1342 #define IOPB_RFIFO_CNT 0x3C
1343 #define IOPB_RES_ADDR_3D 0x3D
1344 #define IOPB_RES_ADDR_3E 0x3E
1345 #define IOPB_RES_ADDR_3F 0x3F
1346
1347 /*
1348 * Word I/O register address from base of 'iop_base'.
1349 */
1350 #define IOPW_CHIP_ID_0 0x00 /* CID0 */
1351 #define IOPW_CTRL_REG 0x02 /* CC */
1352 #define IOPW_RAM_ADDR 0x04 /* LA */
1353 #define IOPW_RAM_DATA 0x06 /* LD */
1354 #define IOPW_RES_ADDR_08 0x08
1355 #define IOPW_RISC_CSR 0x0A /* CSR */
1356 #define IOPW_SCSI_CFG0 0x0C /* CFG0 */
1357 #define IOPW_SCSI_CFG1 0x0E /* CFG1 */
1358 #define IOPW_RES_ADDR_10 0x10
1359 #define IOPW_SEL_MASK 0x12 /* SM */
1360 #define IOPW_RES_ADDR_14 0x14
1361 #define IOPW_FLASH_ADDR 0x16 /* FA */
1362 #define IOPW_RES_ADDR_18 0x18
1363 #define IOPW_EE_CMD 0x1A /* EC */
1364 #define IOPW_EE_DATA 0x1C /* ED */
1365 #define IOPW_SFIFO_CNT 0x1E /* SFC */
1366 #define IOPW_RES_ADDR_20 0x20
1367 #define IOPW_Q_BASE 0x22 /* QB */
1368 #define IOPW_QP 0x24 /* QP */
1369 #define IOPW_IX 0x26 /* IX */
1370 #define IOPW_SP 0x28 /* SP */
1371 #define IOPW_PC 0x2A /* PC */
1372 #define IOPW_RES_ADDR_2C 0x2C
1373 #define IOPW_RES_ADDR_2E 0x2E
1374 #define IOPW_SCSI_DATA 0x30 /* SD */
1375 #define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */
1376 #define IOPW_SCSI_CTRL 0x34 /* SC */
1377 #define IOPW_HSHK_CFG 0x36 /* HCFG */
1378 #define IOPW_SXFR_STATUS 0x36 /* SXS */
1379 #define IOPW_SXFR_CNTL 0x38 /* SXL */
1380 #define IOPW_SXFR_CNTH 0x3A /* SXH */
1381 #define IOPW_RES_ADDR_3C 0x3C
1382 #define IOPW_RFIFO_DATA 0x3E /* RFD */
1383
1384 /*
1385 * Doubleword I/O register address from base of 'iop_base'.
1386 */
1387 #define IOPDW_RES_ADDR_0 0x00
1388 #define IOPDW_RAM_DATA 0x04
1389 #define IOPDW_RES_ADDR_8 0x08
1390 #define IOPDW_RES_ADDR_C 0x0C
1391 #define IOPDW_RES_ADDR_10 0x10
1392 #define IOPDW_COMMA 0x14
1393 #define IOPDW_COMMB 0x18
1394 #define IOPDW_RES_ADDR_1C 0x1C
1395 #define IOPDW_SDMA_ADDR0 0x20
1396 #define IOPDW_SDMA_ADDR1 0x24
1397 #define IOPDW_SDMA_COUNT 0x28
1398 #define IOPDW_SDMA_ERROR 0x2C
1399 #define IOPDW_RDMA_ADDR0 0x30
1400 #define IOPDW_RDMA_ADDR1 0x34
1401 #define IOPDW_RDMA_COUNT 0x38
1402 #define IOPDW_RDMA_ERROR 0x3C
1403
1404 #define ADV_CHIP_ID_BYTE 0x25
1405 #define ADV_CHIP_ID_WORD 0x04C1
1406
1407 #define ADV_INTR_ENABLE_HOST_INTR 0x01
1408 #define ADV_INTR_ENABLE_SEL_INTR 0x02
1409 #define ADV_INTR_ENABLE_DPR_INTR 0x04
1410 #define ADV_INTR_ENABLE_RTA_INTR 0x08
1411 #define ADV_INTR_ENABLE_RMA_INTR 0x10
1412 #define ADV_INTR_ENABLE_RST_INTR 0x20
1413 #define ADV_INTR_ENABLE_DPE_INTR 0x40
1414 #define ADV_INTR_ENABLE_GLOBAL_INTR 0x80
1415
1416 #define ADV_INTR_STATUS_INTRA 0x01
1417 #define ADV_INTR_STATUS_INTRB 0x02
1418 #define ADV_INTR_STATUS_INTRC 0x04
1419
1420 #define ADV_RISC_CSR_STOP (0x0000)
1421 #define ADV_RISC_TEST_COND (0x2000)
1422 #define ADV_RISC_CSR_RUN (0x4000)
1423 #define ADV_RISC_CSR_SINGLE_STEP (0x8000)
1424
1425 #define ADV_CTRL_REG_HOST_INTR 0x0100
1426 #define ADV_CTRL_REG_SEL_INTR 0x0200
1427 #define ADV_CTRL_REG_DPR_INTR 0x0400
1428 #define ADV_CTRL_REG_RTA_INTR 0x0800
1429 #define ADV_CTRL_REG_RMA_INTR 0x1000
1430 #define ADV_CTRL_REG_RES_BIT14 0x2000
1431 #define ADV_CTRL_REG_DPE_INTR 0x4000
1432 #define ADV_CTRL_REG_POWER_DONE 0x8000
1433 #define ADV_CTRL_REG_ANY_INTR 0xFF00
1434
1435 #define ADV_CTRL_REG_CMD_RESET 0x00C6
1436 #define ADV_CTRL_REG_CMD_WR_IO_REG 0x00C5
1437 #define ADV_CTRL_REG_CMD_RD_IO_REG 0x00C4
1438 #define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3
1439 #define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2
1440
1441 #define ADV_TICKLE_NOP 0x00
1442 #define ADV_TICKLE_A 0x01
1443 #define ADV_TICKLE_B 0x02
1444 #define ADV_TICKLE_C 0x03
1445
1446 #define AdvIsIntPending(port) \
1447 (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
1448
1449 /*
1450 * SCSI_CFG0 Register bit definitions
1451 */
1452 #define TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */
1453 #define PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */
1454 #define EVEN_PARITY 0x1000 /* Select Even Parity */
1455 #define WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */
1456 #define QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */
1457 #define PRIM_MODE 0x0100 /* Primitive SCSI mode */
1458 #define SCAM_EN 0x0080 /* Enable SCAM selection */
1459 #define SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
1460 #define CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
1461 #define OUR_ID_EN 0x0010 /* Enable OUR_ID bits */
1462 #define OUR_ID 0x000F /* SCSI ID */
1463
1464 /*
1465 * SCSI_CFG1 Register bit definitions
1466 */
1467 #define BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */
1468 #define TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
1469 #define SLEW_RATE 0x1000 /* SCSI output buffer slew rate */
1470 #define FILTER_SEL 0x0C00 /* Filter Period Selection */
1471 #define FLTR_DISABLE 0x0000 /* Input Filtering Disabled */
1472 #define FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
1473 #define FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
1474 #define ACTIVE_DBL 0x0200 /* Disable Active Negation */
1475 #define DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */
1476 #define DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */
1477 #define TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */
1478 #define TERM_CTL 0x0030 /* External SCSI Termination Bits */
1479 #define TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */
1480 #define TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */
1481 #define CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */
1482
1483 /*
1484 * Addendum for ASC-38C0800 Chip
1485 *
1486 * The ASC-38C1600 Chip uses the same definitions except that the
1487 * bus mode override bits [12:10] have been moved to byte register
1488 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
1489 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
1490 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
1491 * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
1492 * and [1:0]. Bits [14], [7:6], [3:2] are unused.
1493 */
1494 #define DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */
1495 #define HVD_LVD_SE 0x1C00 /* Device Detect Bits */
1496 #define HVD 0x1000 /* HVD Device Detect */
1497 #define LVD 0x0800 /* LVD Device Detect */
1498 #define SE 0x0400 /* SE Device Detect */
1499 #define TERM_LVD 0x00C0 /* LVD Termination Bits */
1500 #define TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */
1501 #define TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */
1502 #define TERM_SE 0x0030 /* SE Termination Bits */
1503 #define TERM_SE_HI 0x0020 /* Enable SE Upper Termination */
1504 #define TERM_SE_LO 0x0010 /* Enable SE Lower Termination */
1505 #define C_DET_LVD 0x000C /* LVD Cable Detect Bits */
1506 #define C_DET3 0x0008 /* Cable Detect for LVD External Wide */
1507 #define C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */
1508 #define C_DET_SE 0x0003 /* SE Cable Detect Bits */
1509 #define C_DET1 0x0002 /* Cable Detect for SE Internal Wide */
1510 #define C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */
1511
1512 #define CABLE_ILLEGAL_A 0x7
1513 /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */
1514
1515 #define CABLE_ILLEGAL_B 0xB
1516 /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */
1517
1518 /*
1519 * MEM_CFG Register bit definitions
1520 */
1521 #define BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */
1522 #define FAST_EE_CLK 0x20 /* Diagnostic Bit */
1523 #define RAM_SZ 0x1C /* Specify size of RAM to RISC */
1524 #define RAM_SZ_2KB 0x00 /* 2 KB */
1525 #define RAM_SZ_4KB 0x04 /* 4 KB */
1526 #define RAM_SZ_8KB 0x08 /* 8 KB */
1527 #define RAM_SZ_16KB 0x0C /* 16 KB */
1528 #define RAM_SZ_32KB 0x10 /* 32 KB */
1529 #define RAM_SZ_64KB 0x14 /* 64 KB */
1530
1531 /*
1532 * DMA_CFG0 Register bit definitions
1533 *
1534 * This register is only accessible to the host.
1535 */
1536 #define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */
1537 #define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */
1538 #define FIFO_THRESH_16B 0x00 /* 16 bytes */
1539 #define FIFO_THRESH_32B 0x20 /* 32 bytes */
1540 #define FIFO_THRESH_48B 0x30 /* 48 bytes */
1541 #define FIFO_THRESH_64B 0x40 /* 64 bytes */
1542 #define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */
1543 #define FIFO_THRESH_96B 0x60 /* 96 bytes */
1544 #define FIFO_THRESH_112B 0x70 /* 112 bytes */
1545 #define START_CTL 0x0C /* DMA start conditions */
1546 #define START_CTL_TH 0x00 /* Wait threshold level (default) */
1547 #define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */
1548 #define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */
1549 #define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */
1550 #define READ_CMD 0x03 /* Memory Read Method */
1551 #define READ_CMD_MR 0x00 /* Memory Read */
1552 #define READ_CMD_MRL 0x02 /* Memory Read Long */
1553 #define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */
1554
1555 /*
1556 * ASC-38C0800 RAM BIST Register bit definitions
1557 */
1558 #define RAM_TEST_MODE 0x80
1559 #define PRE_TEST_MODE 0x40
1560 #define NORMAL_MODE 0x00
1561 #define RAM_TEST_DONE 0x10
1562 #define RAM_TEST_STATUS 0x0F
1563 #define RAM_TEST_HOST_ERROR 0x08
1564 #define RAM_TEST_INTRAM_ERROR 0x04
1565 #define RAM_TEST_RISC_ERROR 0x02
1566 #define RAM_TEST_SCSI_ERROR 0x01
1567 #define RAM_TEST_SUCCESS 0x00
1568 #define PRE_TEST_VALUE 0x05
1569 #define NORMAL_VALUE 0x00
1570
1571 /*
1572 * ASC38C1600 Definitions
1573 *
1574 * IOPB_PCI_INT_CFG Bit Field Definitions
1575 */
1576
1577 #define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */
1578
1579 /*
1580 * Bit 1 can be set to change the interrupt for the Function to operate in
1581 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
1582 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
1583 * mode, otherwise the operating mode is undefined.
1584 */
1585 #define TOTEMPOLE 0x02
1586
1587 /*
1588 * Bit 0 can be used to change the Int Pin for the Function. The value is
1589 * 0 by default for both Functions with Function 0 using INT A and Function
1590 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
1591 * INT A is used.
1592 *
1593 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
1594 * value specified in the PCI Configuration Space.
1595 */
1596 #define INTAB 0x01
1597
1598 /*
1599 * Adv Library Status Definitions
1600 */
1601 #define ADV_TRUE 1
1602 #define ADV_FALSE 0
1603 #define ADV_SUCCESS 1
1604 #define ADV_BUSY 0
1605 #define ADV_ERROR (-1)
1606
1607 /*
1608 * ADV_DVC_VAR 'warn_code' values
1609 */
1610 #define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */
1611 #define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */
1612 #define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */
1613 #define ASC_WARN_ERROR 0xFFFF /* ADV_ERROR return */
1614
1615 #define ADV_MAX_TID 15 /* max. target identifier */
1616 #define ADV_MAX_LUN 7 /* max. logical unit number */
1617
1618 /*
1619 * Fixed locations of microcode operating variables.
1620 */
1621 #define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */
1622 #define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */
1623 #define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */
1624 #define ASC_MC_VERSION_DATE 0x0038 /* microcode version */
1625 #define ASC_MC_VERSION_NUM 0x003A /* microcode number */
1626 #define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
1627 #define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
1628 #define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */
1629 #define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */
1630 #define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */
1631 #define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */
1632 #define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */
1633 #define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */
1634 #define ASC_MC_CHIP_TYPE 0x009A
1635 #define ASC_MC_INTRB_CODE 0x009B
1636 #define ASC_MC_WDTR_ABLE 0x009C
1637 #define ASC_MC_SDTR_ABLE 0x009E
1638 #define ASC_MC_TAGQNG_ABLE 0x00A0
1639 #define ASC_MC_DISC_ENABLE 0x00A2
1640 #define ASC_MC_IDLE_CMD_STATUS 0x00A4
1641 #define ASC_MC_IDLE_CMD 0x00A6
1642 #define ASC_MC_IDLE_CMD_PARAMETER 0x00A8
1643 #define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC
1644 #define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE
1645 #define ASC_MC_DEFAULT_MEM_CFG 0x00B0
1646 #define ASC_MC_DEFAULT_SEL_MASK 0x00B2
1647 #define ASC_MC_SDTR_DONE 0x00B6
1648 #define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0
1649 #define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0
1650 #define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100
1651 #define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */
1652 #define ASC_MC_WDTR_DONE 0x0124
1653 #define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */
1654 #define ASC_MC_ICQ 0x0160
1655 #define ASC_MC_IRQ 0x0164
1656 #define ASC_MC_PPR_ABLE 0x017A
1657
1658 /*
1659 * BIOS LRAM variable absolute offsets.
1660 */
1661 #define BIOS_CODESEG 0x54
1662 #define BIOS_CODELEN 0x56
1663 #define BIOS_SIGNATURE 0x58
1664 #define BIOS_VERSION 0x5A
1665
1666 /*
1667 * Microcode Control Flags
1668 *
1669 * Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
1670 * and handled by the microcode.
1671 */
1672 #define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */
1673 #define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */
1674
1675 /*
1676 * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
1677 */
1678 #define HSHK_CFG_WIDE_XFR 0x8000
1679 #define HSHK_CFG_RATE 0x0F00
1680 #define HSHK_CFG_OFFSET 0x001F
1681
1682 #define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */
1683 #define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */
1684 #define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */
1685 #define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */
1686
1687 #define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */
1688 #define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */
1689 #define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
1690 #define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */
1691 #define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
1692
1693 #define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */
1694 #define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */
1695 #define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */
1696 #define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */
1697 #define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */
1698 /*
1699 * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
1700 * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
1701 */
1702 #define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */
1703 #define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */
1704
1705 /*
1706 * All fields here are accessed by the board microcode and need to be
1707 * little-endian.
1708 */
1709 typedef struct adv_carr_t {
1710 __le32 carr_va; /* Carrier Virtual Address */
1711 __le32 carr_pa; /* Carrier Physical Address */
1712 __le32 areq_vpa; /* ASC_SCSI_REQ_Q Virtual or Physical Address */
1713 /*
1714 * next_vpa [31:4] Carrier Virtual or Physical Next Pointer
1715 *
1716 * next_vpa [3:1] Reserved Bits
1717 * next_vpa [0] Done Flag set in Response Queue.
1718 */
1719 __le32 next_vpa;
1720 } ADV_CARR_T;
1721
1722 /*
1723 * Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
1724 */
1725 #define ASC_NEXT_VPA_MASK 0xFFFFFFF0
1726
1727 #define ASC_RQ_DONE 0x00000001
1728 #define ASC_RQ_GOOD 0x00000002
1729 #define ASC_CQ_STOPPER 0x00000000
1730
1731 #define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_VPA_MASK)
1732
1733 /*
1734 * Each carrier is 64 bytes, and we need three additional
1735 * carrier for icq, irq, and the termination carrier.
1736 */
1737 #define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 3)
1738
1739 #define ADV_CARRIER_BUFSIZE \
1740 (ADV_CARRIER_COUNT * sizeof(ADV_CARR_T))
1741
1742 /*
1743 * ASC_SCSI_REQ_Q 'a_flag' definitions
1744 *
1745 * The Adv Library should limit use to the lower nibble (4 bits) of
1746 * a_flag. Drivers are free to use the upper nibble (4 bits) of a_flag.
1747 */
1748 #define ADV_POLL_REQUEST 0x01 /* poll for request completion */
1749 #define ADV_SCSIQ_DONE 0x02 /* request done */
1750 #define ADV_DONT_RETRY 0x08 /* don't do retry */
1751
1752 #define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */
1753 #define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */
1754 #define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */
1755
1756 /*
1757 * Adapter temporary configuration structure
1758 *
1759 * This structure can be discarded after initialization. Don't add
1760 * fields here needed after initialization.
1761 *
1762 * Field naming convention:
1763 *
1764 * *_enable indicates the field enables or disables a feature. The
1765 * value of the field is never reset.
1766 */
1767 typedef struct adv_dvc_cfg {
1768 ushort disc_enable; /* enable disconnection */
1769 uchar chip_version; /* chip version */
1770 uchar termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
1771 ushort control_flag; /* Microcode Control Flag */
1772 ushort mcode_date; /* Microcode date */
1773 ushort mcode_version; /* Microcode version */
1774 ushort serial1; /* EEPROM serial number word 1 */
1775 ushort serial2; /* EEPROM serial number word 2 */
1776 ushort serial3; /* EEPROM serial number word 3 */
1777 } ADV_DVC_CFG;
1778
1779 struct adv_dvc_var;
1780 struct adv_scsi_req_q;
1781
1782 typedef struct adv_sg_block {
1783 uchar reserved1;
1784 uchar reserved2;
1785 uchar reserved3;
1786 uchar sg_cnt; /* Valid entries in block. */
1787 __le32 sg_ptr; /* Pointer to next sg block. */
1788 struct {
1789 __le32 sg_addr; /* SG element address. */
1790 __le32 sg_count; /* SG element count. */
1791 } sg_list[NO_OF_SG_PER_BLOCK];
1792 } ADV_SG_BLOCK;
1793
1794 /*
1795 * ADV_SCSI_REQ_Q - microcode request structure
1796 *
1797 * All fields in this structure up to byte 60 are used by the microcode.
1798 * The microcode makes assumptions about the size and ordering of fields
1799 * in this structure. Do not change the structure definition here without
1800 * coordinating the change with the microcode.
1801 *
1802 * All fields accessed by microcode must be maintained in little_endian
1803 * order.
1804 */
1805 typedef struct adv_scsi_req_q {
1806 uchar cntl; /* Ucode flags and state (ASC_MC_QC_*). */
1807 uchar target_cmd;
1808 uchar target_id; /* Device target identifier. */
1809 uchar target_lun; /* Device target logical unit number. */
1810 __le32 data_addr; /* Data buffer physical address. */
1811 __le32 data_cnt; /* Data count. Ucode sets to residual. */
1812 __le32 sense_addr;
1813 __le32 carr_pa;
1814 uchar mflag;
1815 uchar sense_len;
1816 uchar cdb_len; /* SCSI CDB length. Must <= 16 bytes. */
1817 uchar scsi_cntl;
1818 uchar done_status; /* Completion status. */
1819 uchar scsi_status; /* SCSI status byte. */
1820 uchar host_status; /* Ucode host status. */
1821 uchar sg_working_ix;
1822 uchar cdb[12]; /* SCSI CDB bytes 0-11. */
1823 __le32 sg_real_addr; /* SG list physical address. */
1824 __le32 scsiq_rptr;
1825 uchar cdb16[4]; /* SCSI CDB bytes 12-15. */
1826 __le32 scsiq_ptr;
1827 __le32 carr_va;
1828 /*
1829 * End of microcode structure - 60 bytes. The rest of the structure
1830 * is used by the Adv Library and ignored by the microcode.
1831 */
1832 u32 srb_tag;
1833 uchar a_flag;
1834 uchar pad[3]; /* Pad out to a word boundary. */
1835 ADV_SG_BLOCK *sg_list_ptr; /* SG list virtual address. */
1836 } ADV_SCSI_REQ_Q;
1837
1838 /*
1839 * The following two structures are used to process Wide Board requests.
1840 *
1841 * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
1842 * and microcode with the ADV_SCSI_REQ_Q field 'srb_tag' set to the
1843 * SCSI request tag. The adv_req_t structure 'cmndp' field in turn points
1844 * to the Mid-Level SCSI request structure.
1845 *
1846 * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
1847 * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
1848 * up to 255 scatter-gather elements may be used per request or
1849 * ADV_SCSI_REQ_Q.
1850 *
1851 * Both structures must be 32 byte aligned.
1852 */
1853 typedef struct adv_sgblk {
1854 ADV_SG_BLOCK sg_block; /* Sgblock structure. */
1855 dma_addr_t sg_addr; /* Physical address */
1856 struct adv_sgblk *next_sgblkp; /* Next scatter-gather structure. */
1857 } adv_sgblk_t;
1858
1859 typedef struct adv_req {
1860 ADV_SCSI_REQ_Q scsi_req_q; /* Adv Library request structure. */
1861 uchar align[24]; /* Request structure padding. */
1862 struct scsi_cmnd *cmndp; /* Mid-Level SCSI command pointer. */
1863 dma_addr_t req_addr;
1864 adv_sgblk_t *sgblkp; /* Adv Library scatter-gather pointer. */
1865 } adv_req_t __aligned(32);
1866
1867 /*
1868 * Adapter operation variable structure.
1869 *
1870 * One structure is required per host adapter.
1871 *
1872 * Field naming convention:
1873 *
1874 * *_able indicates both whether a feature should be enabled or disabled
1875 * and whether a device isi capable of the feature. At initialization
1876 * this field may be set, but later if a device is found to be incapable
1877 * of the feature, the field is cleared.
1878 */
1879 typedef struct adv_dvc_var {
1880 AdvPortAddr iop_base; /* I/O port address */
1881 ushort err_code; /* fatal error code */
1882 ushort bios_ctrl; /* BIOS control word, EEPROM word 12 */
1883 ushort wdtr_able; /* try WDTR for a device */
1884 ushort sdtr_able; /* try SDTR for a device */
1885 ushort ultra_able; /* try SDTR Ultra speed for a device */
1886 ushort sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */
1887 ushort sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */
1888 ushort sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */
1889 ushort sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */
1890 ushort tagqng_able; /* try tagged queuing with a device */
1891 ushort ppr_able; /* PPR message capable per TID bitmask. */
1892 uchar max_dvc_qng; /* maximum number of tagged commands per device */
1893 ushort start_motor; /* start motor command allowed */
1894 uchar scsi_reset_wait; /* delay in seconds after scsi bus reset */
1895 uchar chip_no; /* should be assigned by caller */
1896 uchar max_host_qng; /* maximum number of Q'ed command allowed */
1897 ushort no_scam; /* scam_tolerant of EEPROM */
1898 struct asc_board *drv_ptr; /* driver pointer to private structure */
1899 uchar chip_scsi_id; /* chip SCSI target ID */
1900 uchar chip_type;
1901 uchar bist_err_code;
1902 ADV_CARR_T *carrier;
1903 ADV_CARR_T *carr_freelist; /* Carrier free list. */
1904 dma_addr_t carrier_addr;
1905 ADV_CARR_T *icq_sp; /* Initiator command queue stopper pointer. */
1906 ADV_CARR_T *irq_sp; /* Initiator response queue stopper pointer. */
1907 ushort carr_pending_cnt; /* Count of pending carriers. */
1908 /*
1909 * Note: The following fields will not be used after initialization. The
1910 * driver may discard the buffer after initialization is done.
1911 */
1912 ADV_DVC_CFG *cfg; /* temporary configuration structure */
1913 } ADV_DVC_VAR;
1914
1915 /*
1916 * Microcode idle loop commands
1917 */
1918 #define IDLE_CMD_COMPLETED 0
1919 #define IDLE_CMD_STOP_CHIP 0x0001
1920 #define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002
1921 #define IDLE_CMD_SEND_INT 0x0004
1922 #define IDLE_CMD_ABORT 0x0008
1923 #define IDLE_CMD_DEVICE_RESET 0x0010
1924 #define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */
1925 #define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */
1926 #define IDLE_CMD_SCSIREQ 0x0080
1927
1928 #define IDLE_CMD_STATUS_SUCCESS 0x0001
1929 #define IDLE_CMD_STATUS_FAILURE 0x0002
1930
1931 /*
1932 * AdvSendIdleCmd() flag definitions.
1933 */
1934 #define ADV_NOWAIT 0x01
1935
1936 /*
1937 * Wait loop time out values.
1938 */
1939 #define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */
1940 #define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */
1941 #define SCSI_MAX_RETRY 10 /* retry count */
1942
1943 #define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */
1944 #define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */
1945 #define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */
1946 #define ADV_RDMA_IN_CARR_AND_Q_INVALID 0x04 /* RDMAed-in data invalid. */
1947
1948 #define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */
1949
1950 /* Read byte from a register. */
1951 #define AdvReadByteRegister(iop_base, reg_off) \
1952 (ADV_MEM_READB((iop_base) + (reg_off)))
1953
1954 /* Write byte to a register. */
1955 #define AdvWriteByteRegister(iop_base, reg_off, byte) \
1956 (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
1957
1958 /* Read word (2 bytes) from a register. */
1959 #define AdvReadWordRegister(iop_base, reg_off) \
1960 (ADV_MEM_READW((iop_base) + (reg_off)))
1961
1962 /* Write word (2 bytes) to a register. */
1963 #define AdvWriteWordRegister(iop_base, reg_off, word) \
1964 (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
1965
1966 /* Write dword (4 bytes) to a register. */
1967 #define AdvWriteDWordRegister(iop_base, reg_off, dword) \
1968 (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
1969
1970 /* Read byte from LRAM. */
1971 #define AdvReadByteLram(iop_base, addr, byte) \
1972 do { \
1973 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
1974 (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
1975 } while (0)
1976
1977 /* Write byte to LRAM. */
1978 #define AdvWriteByteLram(iop_base, addr, byte) \
1979 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
1980 ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
1981
1982 /* Read word (2 bytes) from LRAM. */
1983 #define AdvReadWordLram(iop_base, addr, word) \
1984 do { \
1985 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
1986 (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
1987 } while (0)
1988
1989 /* Write word (2 bytes) to LRAM. */
1990 #define AdvWriteWordLram(iop_base, addr, word) \
1991 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
1992 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
1993
1994 /* Write little-endian double word (4 bytes) to LRAM */
1995 /* Because of unspecified C language ordering don't use auto-increment. */
1996 #define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
1997 ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
1998 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
1999 cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
2000 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
2001 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2002 cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
2003
2004 /* Read word (2 bytes) from LRAM assuming that the address is already set. */
2005 #define AdvReadWordAutoIncLram(iop_base) \
2006 (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
2007
2008 /* Write word (2 bytes) to LRAM assuming that the address is already set. */
2009 #define AdvWriteWordAutoIncLram(iop_base, word) \
2010 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2011
2012 /*
2013 * Define macro to check for Condor signature.
2014 *
2015 * Evaluate to ADV_TRUE if a Condor chip is found the specified port
2016 * address 'iop_base'. Otherwise evalue to ADV_FALSE.
2017 */
2018 #define AdvFindSignature(iop_base) \
2019 (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
2020 ADV_CHIP_ID_BYTE) && \
2021 (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
2022 ADV_CHIP_ID_WORD)) ? ADV_TRUE : ADV_FALSE)
2023
2024 /*
2025 * Define macro to Return the version number of the chip at 'iop_base'.
2026 *
2027 * The second parameter 'bus_type' is currently unused.
2028 */
2029 #define AdvGetChipVersion(iop_base, bus_type) \
2030 AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
2031
2032 /*
2033 * Abort an SRB in the chip's RISC Memory. The 'srb_tag' argument must
2034 * match the ASC_SCSI_REQ_Q 'srb_tag' field.
2035 *
2036 * If the request has not yet been sent to the device it will simply be
2037 * aborted from RISC memory. If the request is disconnected it will be
2038 * aborted on reselection by sending an Abort Message to the target ID.
2039 *
2040 * Return value:
2041 * ADV_TRUE(1) - Queue was successfully aborted.
2042 * ADV_FALSE(0) - Queue was not found on the active queue list.
2043 */
2044 #define AdvAbortQueue(asc_dvc, srb_tag) \
2045 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
2046 (ADV_DCNT) (srb_tag))
2047
2048 /*
2049 * Send a Bus Device Reset Message to the specified target ID.
2050 *
2051 * All outstanding commands will be purged if sending the
2052 * Bus Device Reset Message is successful.
2053 *
2054 * Return Value:
2055 * ADV_TRUE(1) - All requests on the target are purged.
2056 * ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
2057 * are not purged.
2058 */
2059 #define AdvResetDevice(asc_dvc, target_id) \
2060 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
2061 (ADV_DCNT) (target_id))
2062
2063 /*
2064 * SCSI Wide Type definition.
2065 */
2066 #define ADV_SCSI_BIT_ID_TYPE ushort
2067
2068 /*
2069 * AdvInitScsiTarget() 'cntl_flag' options.
2070 */
2071 #define ADV_SCAN_LUN 0x01
2072 #define ADV_CAPINFO_NOLUN 0x02
2073
2074 /*
2075 * Convert target id to target id bit mask.
2076 */
2077 #define ADV_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADV_MAX_TID))
2078
2079 /*
2080 * ASC_SCSI_REQ_Q 'done_status' and 'host_status' return values.
2081 */
2082
2083 #define QD_NO_STATUS 0x00 /* Request not completed yet. */
2084 #define QD_NO_ERROR 0x01
2085 #define QD_ABORTED_BY_HOST 0x02
2086 #define QD_WITH_ERROR 0x04
2087
2088 #define QHSTA_NO_ERROR 0x00
2089 #define QHSTA_M_SEL_TIMEOUT 0x11
2090 #define QHSTA_M_DATA_OVER_RUN 0x12
2091 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
2092 #define QHSTA_M_QUEUE_ABORTED 0x15
2093 #define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */
2094 #define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */
2095 #define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */
2096 #define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */
2097 #define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */
2098 #define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */
2099 #define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */
2100 /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
2101 #define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */
2102 #define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */
2103 #define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */
2104 #define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */
2105 #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */
2106 #define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */
2107 #define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */
2108 #define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */
2109 #define QHSTA_M_WTM_TIMEOUT 0x41
2110 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
2111 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
2112 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
2113 #define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */
2114 #define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */
2115 #define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */
2116
2117 /* Return the address that is aligned at the next doubleword >= to 'addr'. */
2118 #define ADV_32BALIGN(addr) (((ulong) (addr) + 0x1F) & ~0x1F)
2119
2120 /*
2121 * Total contiguous memory needed for driver SG blocks.
2122 *
2123 * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
2124 * number of scatter-gather elements the driver supports in a
2125 * single request.
2126 */
2127
2128 #define ADV_SG_LIST_MAX_BYTE_SIZE \
2129 (sizeof(ADV_SG_BLOCK) * \
2130 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
2131
2132 /* struct asc_board flags */
2133 #define ASC_IS_WIDE_BOARD 0x04 /* AdvanSys Wide Board */
2134
2135 #define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
2136
2137 #define NO_ISA_DMA 0xff /* No ISA DMA Channel Used */
2138
2139 #define ASC_INFO_SIZE 128 /* advansys_info() line size */
2140
2141 /* Asc Library return codes */
2142 #define ASC_TRUE 1
2143 #define ASC_FALSE 0
2144 #define ASC_NOERROR 1
2145 #define ASC_BUSY 0
2146 #define ASC_ERROR (-1)
2147
2148 /* struct scsi_cmnd function return codes */
2149 #define STATUS_BYTE(byte) (byte)
2150 #define MSG_BYTE(byte) ((byte) << 8)
2151 #define HOST_BYTE(byte) ((byte) << 16)
2152 #define DRIVER_BYTE(byte) ((byte) << 24)
2153
2154 #define ASC_STATS(shost, counter) ASC_STATS_ADD(shost, counter, 1)
2155 #ifndef ADVANSYS_STATS
2156 #define ASC_STATS_ADD(shost, counter, count)
2157 #else /* ADVANSYS_STATS */
2158 #define ASC_STATS_ADD(shost, counter, count) \
2159 (((struct asc_board *) shost_priv(shost))->asc_stats.counter += (count))
2160 #endif /* ADVANSYS_STATS */
2161
2162 /* If the result wraps when calculating tenths, return 0. */
2163 #define ASC_TENTHS(num, den) \
2164 (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
2165 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
2166
2167 /*
2168 * Display a message to the console.
2169 */
2170 #define ASC_PRINT(s) \
2171 { \
2172 printk("advansys: "); \
2173 printk(s); \
2174 }
2175
2176 #define ASC_PRINT1(s, a1) \
2177 { \
2178 printk("advansys: "); \
2179 printk((s), (a1)); \
2180 }
2181
2182 #define ASC_PRINT2(s, a1, a2) \
2183 { \
2184 printk("advansys: "); \
2185 printk((s), (a1), (a2)); \
2186 }
2187
2188 #define ASC_PRINT3(s, a1, a2, a3) \
2189 { \
2190 printk("advansys: "); \
2191 printk((s), (a1), (a2), (a3)); \
2192 }
2193
2194 #define ASC_PRINT4(s, a1, a2, a3, a4) \
2195 { \
2196 printk("advansys: "); \
2197 printk((s), (a1), (a2), (a3), (a4)); \
2198 }
2199
2200 #ifndef ADVANSYS_DEBUG
2201
2202 #define ASC_DBG(lvl, s...)
2203 #define ASC_DBG_PRT_SCSI_HOST(lvl, s)
2204 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
2205 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2206 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
2207 #define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2208 #define ASC_DBG_PRT_HEX(lvl, name, start, length)
2209 #define ASC_DBG_PRT_CDB(lvl, cdb, len)
2210 #define ASC_DBG_PRT_SENSE(lvl, sense, len)
2211 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
2212
2213 #else /* ADVANSYS_DEBUG */
2214
2215 /*
2216 * Debugging Message Levels:
2217 * 0: Errors Only
2218 * 1: High-Level Tracing
2219 * 2-N: Verbose Tracing
2220 */
2221
2222 #define ASC_DBG(lvl, format, arg...) { \
2223 if (asc_dbglvl >= (lvl)) \
2224 printk(KERN_DEBUG "%s: %s: " format, DRV_NAME, \
2225 __func__ , ## arg); \
2226 }
2227
2228 #define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
2229 { \
2230 if (asc_dbglvl >= (lvl)) { \
2231 asc_prt_scsi_host(s); \
2232 } \
2233 }
2234
2235 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
2236 { \
2237 if (asc_dbglvl >= (lvl)) { \
2238 asc_prt_asc_scsi_q(scsiqp); \
2239 } \
2240 }
2241
2242 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
2243 { \
2244 if (asc_dbglvl >= (lvl)) { \
2245 asc_prt_asc_qdone_info(qdone); \
2246 } \
2247 }
2248
2249 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
2250 { \
2251 if (asc_dbglvl >= (lvl)) { \
2252 asc_prt_adv_scsi_req_q(scsiqp); \
2253 } \
2254 }
2255
2256 #define ASC_DBG_PRT_HEX(lvl, name, start, length) \
2257 { \
2258 if (asc_dbglvl >= (lvl)) { \
2259 asc_prt_hex((name), (start), (length)); \
2260 } \
2261 }
2262
2263 #define ASC_DBG_PRT_CDB(lvl, cdb, len) \
2264 ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
2265
2266 #define ASC_DBG_PRT_SENSE(lvl, sense, len) \
2267 ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
2268
2269 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
2270 ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
2271 #endif /* ADVANSYS_DEBUG */
2272
2273 #ifdef ADVANSYS_STATS
2274
2275 /* Per board statistics structure */
2276 struct asc_stats {
2277 /* Driver Entrypoint Statistics */
2278 unsigned int queuecommand; /* # calls to advansys_queuecommand() */
2279 unsigned int reset; /* # calls to advansys_eh_bus_reset() */
2280 unsigned int biosparam; /* # calls to advansys_biosparam() */
2281 unsigned int interrupt; /* # advansys_interrupt() calls */
2282 unsigned int callback; /* # calls to asc/adv_isr_callback() */
2283 unsigned int done; /* # calls to request's scsi_done function */
2284 unsigned int build_error; /* # asc/adv_build_req() ASC_ERROR returns. */
2285 unsigned int adv_build_noreq; /* # adv_build_req() adv_req_t alloc. fail. */
2286 unsigned int adv_build_nosg; /* # adv_build_req() adv_sgblk_t alloc. fail. */
2287 /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
2288 unsigned int exe_noerror; /* # ASC_NOERROR returns. */
2289 unsigned int exe_busy; /* # ASC_BUSY returns. */
2290 unsigned int exe_error; /* # ASC_ERROR returns. */
2291 unsigned int exe_unknown; /* # unknown returns. */
2292 /* Data Transfer Statistics */
2293 unsigned int xfer_cnt; /* # I/O requests received */
2294 unsigned int xfer_elem; /* # scatter-gather elements */
2295 unsigned int xfer_sect; /* # 512-byte blocks */
2296 };
2297 #endif /* ADVANSYS_STATS */
2298
2299 /*
2300 * Structure allocated for each board.
2301 *
2302 * This structure is allocated by scsi_host_alloc() at the end
2303 * of the 'Scsi_Host' structure starting at the 'hostdata'
2304 * field. It is guaranteed to be allocated from DMA-able memory.
2305 */
2306 struct asc_board {
2307 struct device *dev;
2308 struct Scsi_Host *shost;
2309 uint flags; /* Board flags */
2310 unsigned int irq;
2311 union {
2312 ASC_DVC_VAR asc_dvc_var; /* Narrow board */
2313 ADV_DVC_VAR adv_dvc_var; /* Wide board */
2314 } dvc_var;
2315 union {
2316 ASC_DVC_CFG asc_dvc_cfg; /* Narrow board */
2317 ADV_DVC_CFG adv_dvc_cfg; /* Wide board */
2318 } dvc_cfg;
2319 ushort asc_n_io_port; /* Number I/O ports. */
2320 ADV_SCSI_BIT_ID_TYPE init_tidmask; /* Target init./valid mask */
2321 ushort reqcnt[ADV_MAX_TID + 1]; /* Starvation request count */
2322 ADV_SCSI_BIT_ID_TYPE queue_full; /* Queue full mask */
2323 ushort queue_full_cnt[ADV_MAX_TID + 1]; /* Queue full count */
2324 union {
2325 ASCEEP_CONFIG asc_eep; /* Narrow EEPROM config. */
2326 ADVEEP_3550_CONFIG adv_3550_eep; /* 3550 EEPROM config. */
2327 ADVEEP_38C0800_CONFIG adv_38C0800_eep; /* 38C0800 EEPROM config. */
2328 ADVEEP_38C1600_CONFIG adv_38C1600_eep; /* 38C1600 EEPROM config. */
2329 } eep_config;
2330 /* /proc/scsi/advansys/[0...] */
2331 #ifdef ADVANSYS_STATS
2332 struct asc_stats asc_stats; /* Board statistics */
2333 #endif /* ADVANSYS_STATS */
2334 /*
2335 * The following fields are used only for Narrow Boards.
2336 */
2337 uchar sdtr_data[ASC_MAX_TID + 1]; /* SDTR information */
2338 /*
2339 * The following fields are used only for Wide Boards.
2340 */
2341 void __iomem *ioremap_addr; /* I/O Memory remap address. */
2342 ushort ioport; /* I/O Port address. */
2343 adv_req_t *adv_reqp; /* Request structures. */
2344 dma_addr_t adv_reqp_addr;
2345 size_t adv_reqp_size;
2346 struct dma_pool *adv_sgblk_pool; /* Scatter-gather structures. */
2347 ushort bios_signature; /* BIOS Signature. */
2348 ushort bios_version; /* BIOS Version. */
2349 ushort bios_codeseg; /* BIOS Code Segment. */
2350 ushort bios_codelen; /* BIOS Code Segment Length. */
2351 };
2352
2353 #define asc_dvc_to_board(asc_dvc) container_of(asc_dvc, struct asc_board, \
2354 dvc_var.asc_dvc_var)
2355 #define adv_dvc_to_board(adv_dvc) container_of(adv_dvc, struct asc_board, \
2356 dvc_var.adv_dvc_var)
2357 #define adv_dvc_to_pdev(adv_dvc) to_pci_dev(adv_dvc_to_board(adv_dvc)->dev)
2358
2359 #ifdef ADVANSYS_DEBUG
2360 static int asc_dbglvl = 3;
2361
2362 /*
2363 * asc_prt_asc_dvc_var()
2364 */
2365 static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
2366 {
2367 printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h);
2368
2369 printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl "
2370 "%d,\n", h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
2371
2372 printk(" bus_type %d, init_sdtr 0x%x,\n", h->bus_type,
2373 (unsigned)h->init_sdtr);
2374
2375 printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, "
2376 "chip_no 0x%x,\n", (unsigned)h->sdtr_done,
2377 (unsigned)h->use_tagged_qng, (unsigned)h->unit_not_ready,
2378 (unsigned)h->chip_no);
2379
2380 printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait "
2381 "%u,\n", (unsigned)h->queue_full_or_busy,
2382 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2383
2384 printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, "
2385 "in_critical_cnt %u,\n", (unsigned)h->is_in_int,
2386 (unsigned)h->max_total_qng, (unsigned)h->cur_total_qng,
2387 (unsigned)h->in_critical_cnt);
2388
2389 printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, "
2390 "pci_fix_asyn_xfer 0x%x,\n", (unsigned)h->last_q_shortage,
2391 (unsigned)h->init_state, (unsigned)h->no_scam,
2392 (unsigned)h->pci_fix_asyn_xfer);
2393
2394 printk(" cfg 0x%lx\n", (ulong)h->cfg);
2395 }
2396
2397 /*
2398 * asc_prt_asc_dvc_cfg()
2399 */
2400 static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
2401 {
2402 printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h);
2403
2404 printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
2405 h->can_tagged_qng, h->cmd_qng_enabled);
2406 printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n",
2407 h->disc_enable, h->sdtr_enable);
2408
2409 printk(" chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, "
2410 "chip_version %d,\n", h->chip_scsi_id, h->isa_dma_speed,
2411 h->isa_dma_channel, h->chip_version);
2412
2413 printk(" mcode_date 0x%x, mcode_version %d\n",
2414 h->mcode_date, h->mcode_version);
2415 }
2416
2417 /*
2418 * asc_prt_adv_dvc_var()
2419 *
2420 * Display an ADV_DVC_VAR structure.
2421 */
2422 static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h)
2423 {
2424 printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h);
2425
2426 printk(" iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
2427 (ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able);
2428
2429 printk(" sdtr_able 0x%x, wdtr_able 0x%x\n",
2430 (unsigned)h->sdtr_able, (unsigned)h->wdtr_able);
2431
2432 printk(" start_motor 0x%x, scsi_reset_wait 0x%x\n",
2433 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2434
2435 printk(" max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%p\n",
2436 (unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng,
2437 h->carr_freelist);
2438
2439 printk(" icq_sp 0x%p, irq_sp 0x%p\n", h->icq_sp, h->irq_sp);
2440
2441 printk(" no_scam 0x%x, tagqng_able 0x%x\n",
2442 (unsigned)h->no_scam, (unsigned)h->tagqng_able);
2443
2444 printk(" chip_scsi_id 0x%x, cfg 0x%lx\n",
2445 (unsigned)h->chip_scsi_id, (ulong)h->cfg);
2446 }
2447
2448 /*
2449 * asc_prt_adv_dvc_cfg()
2450 *
2451 * Display an ADV_DVC_CFG structure.
2452 */
2453 static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h)
2454 {
2455 printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h);
2456
2457 printk(" disc_enable 0x%x, termination 0x%x\n",
2458 h->disc_enable, h->termination);
2459
2460 printk(" chip_version 0x%x, mcode_date 0x%x\n",
2461 h->chip_version, h->mcode_date);
2462
2463 printk(" mcode_version 0x%x, control_flag 0x%x\n",
2464 h->mcode_version, h->control_flag);
2465 }
2466
2467 /*
2468 * asc_prt_scsi_host()
2469 */
2470 static void asc_prt_scsi_host(struct Scsi_Host *s)
2471 {
2472 struct asc_board *boardp = shost_priv(s);
2473
2474 printk("Scsi_Host at addr 0x%p, device %s\n", s, dev_name(boardp->dev));
2475 printk(" host_busy %u, host_no %d,\n",
2476 atomic_read(&s->host_busy), s->host_no);
2477
2478 printk(" base 0x%lx, io_port 0x%lx, irq %d,\n",
2479 (ulong)s->base, (ulong)s->io_port, boardp->irq);
2480
2481 printk(" dma_channel %d, this_id %d, can_queue %d,\n",
2482 s->dma_channel, s->this_id, s->can_queue);
2483
2484 printk(" cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n",
2485 s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma);
2486
2487 if (ASC_NARROW_BOARD(boardp)) {
2488 asc_prt_asc_dvc_var(&boardp->dvc_var.asc_dvc_var);
2489 asc_prt_asc_dvc_cfg(&boardp->dvc_cfg.asc_dvc_cfg);
2490 } else {
2491 asc_prt_adv_dvc_var(&boardp->dvc_var.adv_dvc_var);
2492 asc_prt_adv_dvc_cfg(&boardp->dvc_cfg.adv_dvc_cfg);
2493 }
2494 }
2495
2496 /*
2497 * asc_prt_hex()
2498 *
2499 * Print hexadecimal output in 4 byte groupings 32 bytes
2500 * or 8 double-words per line.
2501 */
2502 static void asc_prt_hex(char *f, uchar *s, int l)
2503 {
2504 int i;
2505 int j;
2506 int k;
2507 int m;
2508
2509 printk("%s: (%d bytes)\n", f, l);
2510
2511 for (i = 0; i < l; i += 32) {
2512
2513 /* Display a maximum of 8 double-words per line. */
2514 if ((k = (l - i) / 4) >= 8) {
2515 k = 8;
2516 m = 0;
2517 } else {
2518 m = (l - i) % 4;
2519 }
2520
2521 for (j = 0; j < k; j++) {
2522 printk(" %2.2X%2.2X%2.2X%2.2X",
2523 (unsigned)s[i + (j * 4)],
2524 (unsigned)s[i + (j * 4) + 1],
2525 (unsigned)s[i + (j * 4) + 2],
2526 (unsigned)s[i + (j * 4) + 3]);
2527 }
2528
2529 switch (m) {
2530 case 0:
2531 default:
2532 break;
2533 case 1:
2534 printk(" %2.2X", (unsigned)s[i + (j * 4)]);
2535 break;
2536 case 2:
2537 printk(" %2.2X%2.2X",
2538 (unsigned)s[i + (j * 4)],
2539 (unsigned)s[i + (j * 4) + 1]);
2540 break;
2541 case 3:
2542 printk(" %2.2X%2.2X%2.2X",
2543 (unsigned)s[i + (j * 4) + 1],
2544 (unsigned)s[i + (j * 4) + 2],
2545 (unsigned)s[i + (j * 4) + 3]);
2546 break;
2547 }
2548
2549 printk("\n");
2550 }
2551 }
2552
2553 /*
2554 * asc_prt_asc_scsi_q()
2555 */
2556 static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q)
2557 {
2558 ASC_SG_HEAD *sgp;
2559 int i;
2560
2561 printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q);
2562
2563 printk
2564 (" target_ix 0x%x, target_lun %u, srb_tag 0x%x, tag_code 0x%x,\n",
2565 q->q2.target_ix, q->q1.target_lun, q->q2.srb_tag,
2566 q->q2.tag_code);
2567
2568 printk
2569 (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2570 (ulong)le32_to_cpu(q->q1.data_addr),
2571 (ulong)le32_to_cpu(q->q1.data_cnt),
2572 (ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len);
2573
2574 printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
2575 (ulong)q->cdbptr, q->q2.cdb_len,
2576 (ulong)q->sg_head, q->q1.sg_queue_cnt);
2577
2578 if (q->sg_head) {
2579 sgp = q->sg_head;
2580 printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp);
2581 printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt,
2582 sgp->queue_cnt);
2583 for (i = 0; i < sgp->entry_cnt; i++) {
2584 printk(" [%u]: addr 0x%lx, bytes %lu\n",
2585 i, (ulong)le32_to_cpu(sgp->sg_list[i].addr),
2586 (ulong)le32_to_cpu(sgp->sg_list[i].bytes));
2587 }
2588
2589 }
2590 }
2591
2592 /*
2593 * asc_prt_asc_qdone_info()
2594 */
2595 static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
2596 {
2597 printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q);
2598 printk(" srb_tag 0x%x, target_ix %u, cdb_len %u, tag_code %u,\n",
2599 q->d2.srb_tag, q->d2.target_ix, q->d2.cdb_len,
2600 q->d2.tag_code);
2601 printk
2602 (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
2603 q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg);
2604 }
2605
2606 /*
2607 * asc_prt_adv_sgblock()
2608 *
2609 * Display an ADV_SG_BLOCK structure.
2610 */
2611 static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b)
2612 {
2613 int i;
2614
2615 printk(" ADV_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
2616 (ulong)b, sgblockno);
2617 printk(" sg_cnt %u, sg_ptr 0x%lx\n",
2618 b->sg_cnt, (ulong)le32_to_cpu(b->sg_ptr));
2619 BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK);
2620 if (b->sg_ptr != 0)
2621 BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK);
2622 for (i = 0; i < b->sg_cnt; i++) {
2623 printk(" [%u]: sg_addr 0x%lx, sg_count 0x%lx\n",
2624 i, (ulong)b->sg_list[i].sg_addr,
2625 (ulong)b->sg_list[i].sg_count);
2626 }
2627 }
2628
2629 /*
2630 * asc_prt_adv_scsi_req_q()
2631 *
2632 * Display an ADV_SCSI_REQ_Q structure.
2633 */
2634 static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q)
2635 {
2636 int sg_blk_cnt;
2637 struct adv_sg_block *sg_ptr;
2638 adv_sgblk_t *sgblkp;
2639
2640 printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q);
2641
2642 printk(" target_id %u, target_lun %u, srb_tag 0x%x, a_flag 0x%x\n",
2643 q->target_id, q->target_lun, q->srb_tag, q->a_flag);
2644
2645 printk(" cntl 0x%x, data_addr 0x%lx\n",
2646 q->cntl, (ulong)le32_to_cpu(q->data_addr));
2647
2648 printk(" data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2649 (ulong)le32_to_cpu(q->data_cnt),
2650 (ulong)le32_to_cpu(q->sense_addr), q->sense_len);
2651
2652 printk
2653 (" cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
2654 q->cdb_len, q->done_status, q->host_status, q->scsi_status);
2655
2656 printk(" sg_working_ix 0x%x, target_cmd %u\n",
2657 q->sg_working_ix, q->target_cmd);
2658
2659 printk(" scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
2660 (ulong)le32_to_cpu(q->scsiq_rptr),
2661 (ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr);
2662
2663 /* Display the request's ADV_SG_BLOCK structures. */
2664 if (q->sg_list_ptr != NULL) {
2665 sgblkp = container_of(q->sg_list_ptr, adv_sgblk_t, sg_block);
2666 sg_blk_cnt = 0;
2667 while (sgblkp) {
2668 sg_ptr = &sgblkp->sg_block;
2669 asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
2670 if (sg_ptr->sg_ptr == 0) {
2671 break;
2672 }
2673 sgblkp = sgblkp->next_sgblkp;
2674 sg_blk_cnt++;
2675 }
2676 }
2677 }
2678 #endif /* ADVANSYS_DEBUG */
2679
2680 /*
2681 * advansys_info()
2682 *
2683 * Return suitable for printing on the console with the argument
2684 * adapter's configuration information.
2685 *
2686 * Note: The information line should not exceed ASC_INFO_SIZE bytes,
2687 * otherwise the static 'info' array will be overrun.
2688 */
2689 static const char *advansys_info(struct Scsi_Host *shost)
2690 {
2691 static char info[ASC_INFO_SIZE];
2692 struct asc_board *boardp = shost_priv(shost);
2693 ASC_DVC_VAR *asc_dvc_varp;
2694 ADV_DVC_VAR *adv_dvc_varp;
2695 char *busname;
2696 char *widename = NULL;
2697
2698 if (ASC_NARROW_BOARD(boardp)) {
2699 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
2700 ASC_DBG(1, "begin\n");
2701 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
2702 if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) ==
2703 ASC_IS_ISAPNP) {
2704 busname = "ISA PnP";
2705 } else {
2706 busname = "ISA";
2707 }
2708 sprintf(info,
2709 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X",
2710 ASC_VERSION, busname,
2711 (ulong)shost->io_port,
2712 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2713 boardp->irq, shost->dma_channel);
2714 } else {
2715 if (asc_dvc_varp->bus_type & ASC_IS_VL) {
2716 busname = "VL";
2717 } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) {
2718 busname = "EISA";
2719 } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
2720 if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
2721 == ASC_IS_PCI_ULTRA) {
2722 busname = "PCI Ultra";
2723 } else {
2724 busname = "PCI";
2725 }
2726 } else {
2727 busname = "?";
2728 shost_printk(KERN_ERR, shost, "unknown bus "
2729 "type %d\n", asc_dvc_varp->bus_type);
2730 }
2731 sprintf(info,
2732 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
2733 ASC_VERSION, busname, (ulong)shost->io_port,
2734 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2735 boardp->irq);
2736 }
2737 } else {
2738 /*
2739 * Wide Adapter Information
2740 *
2741 * Memory-mapped I/O is used instead of I/O space to access
2742 * the adapter, but display the I/O Port range. The Memory
2743 * I/O address is displayed through the driver /proc file.
2744 */
2745 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
2746 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2747 widename = "Ultra-Wide";
2748 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
2749 widename = "Ultra2-Wide";
2750 } else {
2751 widename = "Ultra3-Wide";
2752 }
2753 sprintf(info,
2754 "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
2755 ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base,
2756 (ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, boardp->irq);
2757 }
2758 BUG_ON(strlen(info) >= ASC_INFO_SIZE);
2759 ASC_DBG(1, "end\n");
2760 return info;
2761 }
2762
2763 #ifdef CONFIG_PROC_FS
2764
2765 /*
2766 * asc_prt_board_devices()
2767 *
2768 * Print driver information for devices attached to the board.
2769 */
2770 static void asc_prt_board_devices(struct seq_file *m, struct Scsi_Host *shost)
2771 {
2772 struct asc_board *boardp = shost_priv(shost);
2773 int chip_scsi_id;
2774 int i;
2775
2776 seq_printf(m,
2777 "\nDevice Information for AdvanSys SCSI Host %d:\n",
2778 shost->host_no);
2779
2780 if (ASC_NARROW_BOARD(boardp)) {
2781 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
2782 } else {
2783 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
2784 }
2785
2786 seq_puts(m, "Target IDs Detected:");
2787 for (i = 0; i <= ADV_MAX_TID; i++) {
2788 if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i))
2789 seq_printf(m, " %X,", i);
2790 }
2791 seq_printf(m, " (%X=Host Adapter)\n", chip_scsi_id);
2792 }
2793
2794 /*
2795 * Display Wide Board BIOS Information.
2796 */
2797 static void asc_prt_adv_bios(struct seq_file *m, struct Scsi_Host *shost)
2798 {
2799 struct asc_board *boardp = shost_priv(shost);
2800 ushort major, minor, letter;
2801
2802 seq_puts(m, "\nROM BIOS Version: ");
2803
2804 /*
2805 * If the BIOS saved a valid signature, then fill in
2806 * the BIOS code segment base address.
2807 */
2808 if (boardp->bios_signature != 0x55AA) {
2809 seq_puts(m, "Disabled or Pre-3.1\n"
2810 "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n"
2811 "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
2812 } else {
2813 major = (boardp->bios_version >> 12) & 0xF;
2814 minor = (boardp->bios_version >> 8) & 0xF;
2815 letter = (boardp->bios_version & 0xFF);
2816
2817 seq_printf(m, "%d.%d%c\n",
2818 major, minor,
2819 letter >= 26 ? '?' : letter + 'A');
2820 /*
2821 * Current available ROM BIOS release is 3.1I for UW
2822 * and 3.2I for U2W. This code doesn't differentiate
2823 * UW and U2W boards.
2824 */
2825 if (major < 3 || (major <= 3 && minor < 1) ||
2826 (major <= 3 && minor <= 1 && letter < ('I' - 'A'))) {
2827 seq_puts(m, "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n"
2828 "ftp://ftp.connectcom.net/pub\n");
2829 }
2830 }
2831 }
2832
2833 /*
2834 * Add serial number to information bar if signature AAh
2835 * is found in at bit 15-9 (7 bits) of word 1.
2836 *
2837 * Serial Number consists fo 12 alpha-numeric digits.
2838 *
2839 * 1 - Product type (A,B,C,D..) Word0: 15-13 (3 bits)
2840 * 2 - MFG Location (A,B,C,D..) Word0: 12-10 (3 bits)
2841 * 3-4 - Product ID (0-99) Word0: 9-0 (10 bits)
2842 * 5 - Product revision (A-J) Word0: " "
2843 *
2844 * Signature Word1: 15-9 (7 bits)
2845 * 6 - Year (0-9) Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
2846 * 7-8 - Week of the year (1-52) Word1: 5-0 (6 bits)
2847 *
2848 * 9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
2849 *
2850 * Note 1: Only production cards will have a serial number.
2851 *
2852 * Note 2: Signature is most significant 7 bits (0xFE).
2853 *
2854 * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
2855 */
2856 static int asc_get_eeprom_string(ushort *serialnum, uchar *cp)
2857 {
2858 ushort w, num;
2859
2860 if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) {
2861 return ASC_FALSE;
2862 } else {
2863 /*
2864 * First word - 6 digits.
2865 */
2866 w = serialnum[0];
2867
2868 /* Product type - 1st digit. */
2869 if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') {
2870 /* Product type is P=Prototype */
2871 *cp += 0x8;
2872 }
2873 cp++;
2874
2875 /* Manufacturing location - 2nd digit. */
2876 *cp++ = 'A' + ((w & 0x1C00) >> 10);
2877
2878 /* Product ID - 3rd, 4th digits. */
2879 num = w & 0x3FF;
2880 *cp++ = '0' + (num / 100);
2881 num %= 100;
2882 *cp++ = '0' + (num / 10);
2883
2884 /* Product revision - 5th digit. */
2885 *cp++ = 'A' + (num % 10);
2886
2887 /*
2888 * Second word
2889 */
2890 w = serialnum[1];
2891
2892 /*
2893 * Year - 6th digit.
2894 *
2895 * If bit 15 of third word is set, then the
2896 * last digit of the year is greater than 7.
2897 */
2898 if (serialnum[2] & 0x8000) {
2899 *cp++ = '8' + ((w & 0x1C0) >> 6);
2900 } else {
2901 *cp++ = '0' + ((w & 0x1C0) >> 6);
2902 }
2903
2904 /* Week of year - 7th, 8th digits. */
2905 num = w & 0x003F;
2906 *cp++ = '0' + num / 10;
2907 num %= 10;
2908 *cp++ = '0' + num;
2909
2910 /*
2911 * Third word
2912 */
2913 w = serialnum[2] & 0x7FFF;
2914
2915 /* Serial number - 9th digit. */
2916 *cp++ = 'A' + (w / 1000);
2917
2918 /* 10th, 11th, 12th digits. */
2919 num = w % 1000;
2920 *cp++ = '0' + num / 100;
2921 num %= 100;
2922 *cp++ = '0' + num / 10;
2923 num %= 10;
2924 *cp++ = '0' + num;
2925
2926 *cp = '\0'; /* Null Terminate the string. */
2927 return ASC_TRUE;
2928 }
2929 }
2930
2931 /*
2932 * asc_prt_asc_board_eeprom()
2933 *
2934 * Print board EEPROM configuration.
2935 */
2936 static void asc_prt_asc_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
2937 {
2938 struct asc_board *boardp = shost_priv(shost);
2939 ASC_DVC_VAR *asc_dvc_varp;
2940 ASCEEP_CONFIG *ep;
2941 int i;
2942 #ifdef CONFIG_ISA
2943 int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 };
2944 #endif /* CONFIG_ISA */
2945 uchar serialstr[13];
2946
2947 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
2948 ep = &boardp->eep_config.asc_eep;
2949
2950 seq_printf(m,
2951 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
2952 shost->host_no);
2953
2954 if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr)
2955 == ASC_TRUE)
2956 seq_printf(m, " Serial Number: %s\n", serialstr);
2957 else if (ep->adapter_info[5] == 0xBB)
2958 seq_puts(m,
2959 " Default Settings Used for EEPROM-less Adapter.\n");
2960 else
2961 seq_puts(m, " Serial Number Signature Not Present.\n");
2962
2963 seq_printf(m,
2964 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
2965 ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng,
2966 ep->max_tag_qng);
2967
2968 seq_printf(m,
2969 " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam);
2970
2971 seq_puts(m, " Target ID: ");
2972 for (i = 0; i <= ASC_MAX_TID; i++)
2973 seq_printf(m, " %d", i);
2974
2975 seq_puts(m, "\n Disconnects: ");
2976 for (i = 0; i <= ASC_MAX_TID; i++)
2977 seq_printf(m, " %c",
2978 (ep->disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2979
2980 seq_puts(m, "\n Command Queuing: ");
2981 for (i = 0; i <= ASC_MAX_TID; i++)
2982 seq_printf(m, " %c",
2983 (ep->use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2984
2985 seq_puts(m, "\n Start Motor: ");
2986 for (i = 0; i <= ASC_MAX_TID; i++)
2987 seq_printf(m, " %c",
2988 (ep->start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2989
2990 seq_puts(m, "\n Synchronous Transfer:");
2991 for (i = 0; i <= ASC_MAX_TID; i++)
2992 seq_printf(m, " %c",
2993 (ep->init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2994 seq_putc(m, '\n');
2995
2996 #ifdef CONFIG_ISA
2997 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
2998 seq_printf(m,
2999 " Host ISA DMA speed: %d MB/S\n",
3000 isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]);
3001 }
3002 #endif /* CONFIG_ISA */
3003 }
3004
3005 /*
3006 * asc_prt_adv_board_eeprom()
3007 *
3008 * Print board EEPROM configuration.
3009 */
3010 static void asc_prt_adv_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
3011 {
3012 struct asc_board *boardp = shost_priv(shost);
3013 ADV_DVC_VAR *adv_dvc_varp;
3014 int i;
3015 char *termstr;
3016 uchar serialstr[13];
3017 ADVEEP_3550_CONFIG *ep_3550 = NULL;
3018 ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL;
3019 ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL;
3020 ushort word;
3021 ushort *wordp;
3022 ushort sdtr_speed = 0;
3023
3024 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
3025 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3026 ep_3550 = &boardp->eep_config.adv_3550_eep;
3027 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3028 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
3029 } else {
3030 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
3031 }
3032
3033 seq_printf(m,
3034 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3035 shost->host_no);
3036
3037 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3038 wordp = &ep_3550->serial_number_word1;
3039 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3040 wordp = &ep_38C0800->serial_number_word1;
3041 } else {
3042 wordp = &ep_38C1600->serial_number_word1;
3043 }
3044
3045 if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE)
3046 seq_printf(m, " Serial Number: %s\n", serialstr);
3047 else
3048 seq_puts(m, " Serial Number Signature Not Present.\n");
3049
3050 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
3051 seq_printf(m,
3052 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3053 ep_3550->adapter_scsi_id,
3054 ep_3550->max_host_qng, ep_3550->max_dvc_qng);
3055 else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
3056 seq_printf(m,
3057 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3058 ep_38C0800->adapter_scsi_id,
3059 ep_38C0800->max_host_qng,
3060 ep_38C0800->max_dvc_qng);
3061 else
3062 seq_printf(m,
3063 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3064 ep_38C1600->adapter_scsi_id,
3065 ep_38C1600->max_host_qng,
3066 ep_38C1600->max_dvc_qng);
3067 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3068 word = ep_3550->termination;
3069 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3070 word = ep_38C0800->termination_lvd;
3071 } else {
3072 word = ep_38C1600->termination_lvd;
3073 }
3074 switch (word) {
3075 case 1:
3076 termstr = "Low Off/High Off";
3077 break;
3078 case 2:
3079 termstr = "Low Off/High On";
3080 break;
3081 case 3:
3082 termstr = "Low On/High On";
3083 break;
3084 default:
3085 case 0:
3086 termstr = "Automatic";
3087 break;
3088 }
3089
3090 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
3091 seq_printf(m,
3092 " termination: %u (%s), bios_ctrl: 0x%x\n",
3093 ep_3550->termination, termstr,
3094 ep_3550->bios_ctrl);
3095 else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
3096 seq_printf(m,
3097 " termination: %u (%s), bios_ctrl: 0x%x\n",
3098 ep_38C0800->termination_lvd, termstr,
3099 ep_38C0800->bios_ctrl);
3100 else
3101 seq_printf(m,
3102 " termination: %u (%s), bios_ctrl: 0x%x\n",
3103 ep_38C1600->termination_lvd, termstr,
3104 ep_38C1600->bios_ctrl);
3105
3106 seq_puts(m, " Target ID: ");
3107 for (i = 0; i <= ADV_MAX_TID; i++)
3108 seq_printf(m, " %X", i);
3109 seq_putc(m, '\n');
3110
3111 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3112 word = ep_3550->disc_enable;
3113 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3114 word = ep_38C0800->disc_enable;
3115 } else {
3116 word = ep_38C1600->disc_enable;
3117 }
3118 seq_puts(m, " Disconnects: ");
3119 for (i = 0; i <= ADV_MAX_TID; i++)
3120 seq_printf(m, " %c",
3121 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3122 seq_putc(m, '\n');
3123
3124 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3125 word = ep_3550->tagqng_able;
3126 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3127 word = ep_38C0800->tagqng_able;
3128 } else {
3129 word = ep_38C1600->tagqng_able;
3130 }
3131 seq_puts(m, " Command Queuing: ");
3132 for (i = 0; i <= ADV_MAX_TID; i++)
3133 seq_printf(m, " %c",
3134 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3135 seq_putc(m, '\n');
3136
3137 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3138 word = ep_3550->start_motor;
3139 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3140 word = ep_38C0800->start_motor;
3141 } else {
3142 word = ep_38C1600->start_motor;
3143 }
3144 seq_puts(m, " Start Motor: ");
3145 for (i = 0; i <= ADV_MAX_TID; i++)
3146 seq_printf(m, " %c",
3147 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3148 seq_putc(m, '\n');
3149
3150 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3151 seq_puts(m, " Synchronous Transfer:");
3152 for (i = 0; i <= ADV_MAX_TID; i++)
3153 seq_printf(m, " %c",
3154 (ep_3550->sdtr_able & ADV_TID_TO_TIDMASK(i)) ?
3155 'Y' : 'N');
3156 seq_putc(m, '\n');
3157 }
3158
3159 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3160 seq_puts(m, " Ultra Transfer: ");
3161 for (i = 0; i <= ADV_MAX_TID; i++)
3162 seq_printf(m, " %c",
3163 (ep_3550->ultra_able & ADV_TID_TO_TIDMASK(i))
3164 ? 'Y' : 'N');
3165 seq_putc(m, '\n');
3166 }
3167
3168 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3169 word = ep_3550->wdtr_able;
3170 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3171 word = ep_38C0800->wdtr_able;
3172 } else {
3173 word = ep_38C1600->wdtr_able;
3174 }
3175 seq_puts(m, " Wide Transfer: ");
3176 for (i = 0; i <= ADV_MAX_TID; i++)
3177 seq_printf(m, " %c",
3178 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3179 seq_putc(m, '\n');
3180
3181 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 ||
3182 adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600) {
3183 seq_puts(m, " Synchronous Transfer Speed (Mhz):\n ");
3184 for (i = 0; i <= ADV_MAX_TID; i++) {
3185 char *speed_str;
3186
3187 if (i == 0) {
3188 sdtr_speed = adv_dvc_varp->sdtr_speed1;
3189 } else if (i == 4) {
3190 sdtr_speed = adv_dvc_varp->sdtr_speed2;
3191 } else if (i == 8) {
3192 sdtr_speed = adv_dvc_varp->sdtr_speed3;
3193 } else if (i == 12) {
3194 sdtr_speed = adv_dvc_varp->sdtr_speed4;
3195 }
3196 switch (sdtr_speed & ADV_MAX_TID) {
3197 case 0:
3198 speed_str = "Off";
3199 break;
3200 case 1:
3201 speed_str = " 5";
3202 break;
3203 case 2:
3204 speed_str = " 10";
3205 break;
3206 case 3:
3207 speed_str = " 20";
3208 break;
3209 case 4:
3210 speed_str = " 40";
3211 break;
3212 case 5:
3213 speed_str = " 80";
3214 break;
3215 default:
3216 speed_str = "Unk";
3217 break;
3218 }
3219 seq_printf(m, "%X:%s ", i, speed_str);
3220 if (i == 7)
3221 seq_puts(m, "\n ");
3222 sdtr_speed >>= 4;
3223 }
3224 seq_putc(m, '\n');
3225 }
3226 }
3227
3228 /*
3229 * asc_prt_driver_conf()
3230 */
3231 static void asc_prt_driver_conf(struct seq_file *m, struct Scsi_Host *shost)
3232 {
3233 struct asc_board *boardp = shost_priv(shost);
3234 int chip_scsi_id;
3235
3236 seq_printf(m,
3237 "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
3238 shost->host_no);
3239
3240 seq_printf(m,
3241 " host_busy %u, max_id %u, max_lun %llu, max_channel %u\n",
3242 atomic_read(&shost->host_busy), shost->max_id,
3243 shost->max_lun, shost->max_channel);
3244
3245 seq_printf(m,
3246 " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
3247 shost->unique_id, shost->can_queue, shost->this_id,
3248 shost->sg_tablesize, shost->cmd_per_lun);
3249
3250 seq_printf(m,
3251 " unchecked_isa_dma %d, use_clustering %d\n",
3252 shost->unchecked_isa_dma, shost->use_clustering);
3253
3254 seq_printf(m,
3255 " flags 0x%x, last_reset 0x%lx, jiffies 0x%lx, asc_n_io_port 0x%x\n",
3256 boardp->flags, shost->last_reset, jiffies,
3257 boardp->asc_n_io_port);
3258
3259 seq_printf(m, " io_port 0x%lx\n", shost->io_port);
3260
3261 if (ASC_NARROW_BOARD(boardp)) {
3262 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
3263 } else {
3264 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
3265 }
3266 }
3267
3268 /*
3269 * asc_prt_asc_board_info()
3270 *
3271 * Print dynamic board configuration information.
3272 */
3273 static void asc_prt_asc_board_info(struct seq_file *m, struct Scsi_Host *shost)
3274 {
3275 struct asc_board *boardp = shost_priv(shost);
3276 int chip_scsi_id;
3277 ASC_DVC_VAR *v;
3278 ASC_DVC_CFG *c;
3279 int i;
3280 int renegotiate = 0;
3281
3282 v = &boardp->dvc_var.asc_dvc_var;
3283 c = &boardp->dvc_cfg.asc_dvc_cfg;
3284 chip_scsi_id = c->chip_scsi_id;
3285
3286 seq_printf(m,
3287 "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3288 shost->host_no);
3289
3290 seq_printf(m, " chip_version %u, mcode_date 0x%x, "
3291 "mcode_version 0x%x, err_code %u\n",
3292 c->chip_version, c->mcode_date, c->mcode_version,
3293 v->err_code);
3294
3295 /* Current number of commands waiting for the host. */
3296 seq_printf(m,
3297 " Total Command Pending: %d\n", v->cur_total_qng);
3298
3299 seq_puts(m, " Command Queuing:");
3300 for (i = 0; i <= ASC_MAX_TID; i++) {
3301 if ((chip_scsi_id == i) ||
3302 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3303 continue;
3304 }
3305 seq_printf(m, " %X:%c",
3306 i,
3307 (v->use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3308 }
3309
3310 /* Current number of commands waiting for a device. */
3311 seq_puts(m, "\n Command Queue Pending:");
3312 for (i = 0; i <= ASC_MAX_TID; i++) {
3313 if ((chip_scsi_id == i) ||
3314 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3315 continue;
3316 }
3317 seq_printf(m, " %X:%u", i, v->cur_dvc_qng[i]);
3318 }
3319
3320 /* Current limit on number of commands that can be sent to a device. */
3321 seq_puts(m, "\n Command Queue Limit:");
3322 for (i = 0; i <= ASC_MAX_TID; i++) {
3323 if ((chip_scsi_id == i) ||
3324 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3325 continue;
3326 }
3327 seq_printf(m, " %X:%u", i, v->max_dvc_qng[i]);
3328 }
3329
3330 /* Indicate whether the device has returned queue full status. */
3331 seq_puts(m, "\n Command Queue Full:");
3332 for (i = 0; i <= ASC_MAX_TID; i++) {
3333 if ((chip_scsi_id == i) ||
3334 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3335 continue;
3336 }
3337 if (boardp->queue_full & ADV_TID_TO_TIDMASK(i))
3338 seq_printf(m, " %X:Y-%d",
3339 i, boardp->queue_full_cnt[i]);
3340 else
3341 seq_printf(m, " %X:N", i);
3342 }
3343
3344 seq_puts(m, "\n Synchronous Transfer:");
3345 for (i = 0; i <= ASC_MAX_TID; i++) {
3346 if ((chip_scsi_id == i) ||
3347 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3348 continue;
3349 }
3350 seq_printf(m, " %X:%c",
3351 i,
3352 (v->sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3353 }
3354 seq_putc(m, '\n');
3355
3356 for (i = 0; i <= ASC_MAX_TID; i++) {
3357 uchar syn_period_ix;
3358
3359 if ((chip_scsi_id == i) ||
3360 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3361 ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
3362 continue;
3363 }
3364
3365 seq_printf(m, " %X:", i);
3366
3367 if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0) {
3368 seq_puts(m, " Asynchronous");
3369 } else {
3370 syn_period_ix =
3371 (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index -
3372 1);
3373
3374 seq_printf(m,
3375 " Transfer Period Factor: %d (%d.%d Mhz),",
3376 v->sdtr_period_tbl[syn_period_ix],
3377 250 / v->sdtr_period_tbl[syn_period_ix],
3378 ASC_TENTHS(250,
3379 v->sdtr_period_tbl[syn_period_ix]));
3380
3381 seq_printf(m, " REQ/ACK Offset: %d",
3382 boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET);
3383 }
3384
3385 if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3386 seq_puts(m, "*\n");
3387 renegotiate = 1;
3388 } else {
3389 seq_putc(m, '\n');
3390 }
3391 }
3392
3393 if (renegotiate) {
3394 seq_puts(m, " * = Re-negotiation pending before next command.\n");
3395 }
3396 }
3397
3398 /*
3399 * asc_prt_adv_board_info()
3400 *
3401 * Print dynamic board configuration information.
3402 */
3403 static void asc_prt_adv_board_info(struct seq_file *m, struct Scsi_Host *shost)
3404 {
3405 struct asc_board *boardp = shost_priv(shost);
3406 int i;
3407 ADV_DVC_VAR *v;
3408 ADV_DVC_CFG *c;
3409 AdvPortAddr iop_base;
3410 ushort chip_scsi_id;
3411 ushort lramword;
3412 uchar lrambyte;
3413 ushort tagqng_able;
3414 ushort sdtr_able, wdtr_able;
3415 ushort wdtr_done, sdtr_done;
3416 ushort period = 0;
3417 int renegotiate = 0;
3418
3419 v = &boardp->dvc_var.adv_dvc_var;
3420 c = &boardp->dvc_cfg.adv_dvc_cfg;
3421 iop_base = v->iop_base;
3422 chip_scsi_id = v->chip_scsi_id;
3423
3424 seq_printf(m,
3425 "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3426 shost->host_no);
3427
3428 seq_printf(m,
3429 " iop_base 0x%lx, cable_detect: %X, err_code %u\n",
3430 (unsigned long)v->iop_base,
3431 AdvReadWordRegister(iop_base,IOPW_SCSI_CFG1) & CABLE_DETECT,
3432 v->err_code);
3433
3434 seq_printf(m, " chip_version %u, mcode_date 0x%x, "
3435 "mcode_version 0x%x\n", c->chip_version,
3436 c->mcode_date, c->mcode_version);
3437
3438 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
3439 seq_puts(m, " Queuing Enabled:");
3440 for (i = 0; i <= ADV_MAX_TID; i++) {
3441 if ((chip_scsi_id == i) ||
3442 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3443 continue;
3444 }
3445
3446 seq_printf(m, " %X:%c",
3447 i,
3448 (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3449 }
3450
3451 seq_puts(m, "\n Queue Limit:");
3452 for (i = 0; i <= ADV_MAX_TID; i++) {
3453 if ((chip_scsi_id == i) ||
3454 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3455 continue;
3456 }
3457
3458 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i,
3459 lrambyte);
3460
3461 seq_printf(m, " %X:%d", i, lrambyte);
3462 }
3463
3464 seq_puts(m, "\n Command Pending:");
3465 for (i = 0; i <= ADV_MAX_TID; i++) {
3466 if ((chip_scsi_id == i) ||
3467 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3468 continue;
3469 }
3470
3471 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i,
3472 lrambyte);
3473
3474 seq_printf(m, " %X:%d", i, lrambyte);
3475 }
3476 seq_putc(m, '\n');
3477
3478 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
3479 seq_puts(m, " Wide Enabled:");
3480 for (i = 0; i <= ADV_MAX_TID; i++) {
3481 if ((chip_scsi_id == i) ||
3482 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3483 continue;
3484 }
3485
3486 seq_printf(m, " %X:%c",
3487 i,
3488 (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3489 }
3490 seq_putc(m, '\n');
3491
3492 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done);
3493 seq_puts(m, " Transfer Bit Width:");
3494 for (i = 0; i <= ADV_MAX_TID; i++) {
3495 if ((chip_scsi_id == i) ||
3496 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3497 continue;
3498 }
3499
3500 AdvReadWordLram(iop_base,
3501 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3502 lramword);
3503
3504 seq_printf(m, " %X:%d",
3505 i, (lramword & 0x8000) ? 16 : 8);
3506
3507 if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) &&
3508 (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3509 seq_putc(m, '*');
3510 renegotiate = 1;
3511 }
3512 }
3513 seq_putc(m, '\n');
3514
3515 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
3516 seq_puts(m, " Synchronous Enabled:");
3517 for (i = 0; i <= ADV_MAX_TID; i++) {
3518 if ((chip_scsi_id == i) ||
3519 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3520 continue;
3521 }
3522
3523 seq_printf(m, " %X:%c",
3524 i,
3525 (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3526 }
3527 seq_putc(m, '\n');
3528
3529 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done);
3530 for (i = 0; i <= ADV_MAX_TID; i++) {
3531
3532 AdvReadWordLram(iop_base,
3533 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3534 lramword);
3535 lramword &= ~0x8000;
3536
3537 if ((chip_scsi_id == i) ||
3538 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3539 ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
3540 continue;
3541 }
3542
3543 seq_printf(m, " %X:", i);
3544
3545 if ((lramword & 0x1F) == 0) { /* Check for REQ/ACK Offset 0. */
3546 seq_puts(m, " Asynchronous");
3547 } else {
3548 seq_puts(m, " Transfer Period Factor: ");
3549
3550 if ((lramword & 0x1F00) == 0x1100) { /* 80 Mhz */
3551 seq_puts(m, "9 (80.0 Mhz),");
3552 } else if ((lramword & 0x1F00) == 0x1000) { /* 40 Mhz */
3553 seq_puts(m, "10 (40.0 Mhz),");
3554 } else { /* 20 Mhz or below. */
3555
3556 period = (((lramword >> 8) * 25) + 50) / 4;
3557
3558 if (period == 0) { /* Should never happen. */
3559 seq_printf(m, "%d (? Mhz), ", period);
3560 } else {
3561 seq_printf(m,
3562 "%d (%d.%d Mhz),",
3563 period, 250 / period,
3564 ASC_TENTHS(250, period));
3565 }
3566 }
3567
3568 seq_printf(m, " REQ/ACK Offset: %d",
3569 lramword & 0x1F);
3570 }
3571
3572 if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3573 seq_puts(m, "*\n");
3574 renegotiate = 1;
3575 } else {
3576 seq_putc(m, '\n');
3577 }
3578 }
3579
3580 if (renegotiate) {
3581 seq_puts(m, " * = Re-negotiation pending before next command.\n");
3582 }
3583 }
3584
3585 #ifdef ADVANSYS_STATS
3586 /*
3587 * asc_prt_board_stats()
3588 */
3589 static void asc_prt_board_stats(struct seq_file *m, struct Scsi_Host *shost)
3590 {
3591 struct asc_board *boardp = shost_priv(shost);
3592 struct asc_stats *s = &boardp->asc_stats;
3593
3594 seq_printf(m,
3595 "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n",
3596 shost->host_no);
3597
3598 seq_printf(m,
3599 " queuecommand %u, reset %u, biosparam %u, interrupt %u\n",
3600 s->queuecommand, s->reset, s->biosparam,
3601 s->interrupt);
3602
3603 seq_printf(m,
3604 " callback %u, done %u, build_error %u, build_noreq %u, build_nosg %u\n",
3605 s->callback, s->done, s->build_error,
3606 s->adv_build_noreq, s->adv_build_nosg);
3607
3608 seq_printf(m,
3609 " exe_noerror %u, exe_busy %u, exe_error %u, exe_unknown %u\n",
3610 s->exe_noerror, s->exe_busy, s->exe_error,
3611 s->exe_unknown);
3612
3613 /*
3614 * Display data transfer statistics.
3615 */
3616 if (s->xfer_cnt > 0) {
3617 seq_printf(m, " xfer_cnt %u, xfer_elem %u, ",
3618 s->xfer_cnt, s->xfer_elem);
3619
3620 seq_printf(m, "xfer_bytes %u.%01u kb\n",
3621 s->xfer_sect / 2, ASC_TENTHS(s->xfer_sect, 2));
3622
3623 /* Scatter gather transfer statistics */
3624 seq_printf(m, " avg_num_elem %u.%01u, ",
3625 s->xfer_elem / s->xfer_cnt,
3626 ASC_TENTHS(s->xfer_elem, s->xfer_cnt));
3627
3628 seq_printf(m, "avg_elem_size %u.%01u kb, ",
3629 (s->xfer_sect / 2) / s->xfer_elem,
3630 ASC_TENTHS((s->xfer_sect / 2), s->xfer_elem));
3631
3632 seq_printf(m, "avg_xfer_size %u.%01u kb\n",
3633 (s->xfer_sect / 2) / s->xfer_cnt,
3634 ASC_TENTHS((s->xfer_sect / 2), s->xfer_cnt));
3635 }
3636 }
3637 #endif /* ADVANSYS_STATS */
3638
3639 /*
3640 * advansys_show_info() - /proc/scsi/advansys/{0,1,2,3,...}
3641 *
3642 * m: seq_file to print into
3643 * shost: Scsi_Host
3644 *
3645 * Return the number of bytes read from or written to a
3646 * /proc/scsi/advansys/[0...] file.
3647 */
3648 static int
3649 advansys_show_info(struct seq_file *m, struct Scsi_Host *shost)
3650 {
3651 struct asc_board *boardp = shost_priv(shost);
3652
3653 ASC_DBG(1, "begin\n");
3654
3655 /*
3656 * User read of /proc/scsi/advansys/[0...] file.
3657 */
3658
3659 /*
3660 * Get board configuration information.
3661 *
3662 * advansys_info() returns the board string from its own static buffer.
3663 */
3664 /* Copy board information. */
3665 seq_printf(m, "%s\n", (char *)advansys_info(shost));
3666 /*
3667 * Display Wide Board BIOS Information.
3668 */
3669 if (!ASC_NARROW_BOARD(boardp))
3670 asc_prt_adv_bios(m, shost);
3671
3672 /*
3673 * Display driver information for each device attached to the board.
3674 */
3675 asc_prt_board_devices(m, shost);
3676
3677 /*
3678 * Display EEPROM configuration for the board.
3679 */
3680 if (ASC_NARROW_BOARD(boardp))
3681 asc_prt_asc_board_eeprom(m, shost);
3682 else
3683 asc_prt_adv_board_eeprom(m, shost);
3684
3685 /*
3686 * Display driver configuration and information for the board.
3687 */
3688 asc_prt_driver_conf(m, shost);
3689
3690 #ifdef ADVANSYS_STATS
3691 /*
3692 * Display driver statistics for the board.
3693 */
3694 asc_prt_board_stats(m, shost);
3695 #endif /* ADVANSYS_STATS */
3696
3697 /*
3698 * Display Asc Library dynamic configuration information
3699 * for the board.
3700 */
3701 if (ASC_NARROW_BOARD(boardp))
3702 asc_prt_asc_board_info(m, shost);
3703 else
3704 asc_prt_adv_board_info(m, shost);
3705 return 0;
3706 }
3707 #endif /* CONFIG_PROC_FS */
3708
3709 static void asc_scsi_done(struct scsi_cmnd *scp)
3710 {
3711 scsi_dma_unmap(scp);
3712 ASC_STATS(scp->device->host, done);
3713 scp->scsi_done(scp);
3714 }
3715
3716 static void AscSetBank(PortAddr iop_base, uchar bank)
3717 {
3718 uchar val;
3719
3720 val = AscGetChipControl(iop_base) &
3721 (~
3722 (CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET |
3723 CC_CHIP_RESET));
3724 if (bank == 1) {
3725 val |= CC_BANK_ONE;
3726 } else if (bank == 2) {
3727 val |= CC_DIAG | CC_BANK_ONE;
3728 } else {
3729 val &= ~CC_BANK_ONE;
3730 }
3731 AscSetChipControl(iop_base, val);
3732 }
3733
3734 static void AscSetChipIH(PortAddr iop_base, ushort ins_code)
3735 {
3736 AscSetBank(iop_base, 1);
3737 AscWriteChipIH(iop_base, ins_code);
3738 AscSetBank(iop_base, 0);
3739 }
3740
3741 static int AscStartChip(PortAddr iop_base)
3742 {
3743 AscSetChipControl(iop_base, 0);
3744 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
3745 return (0);
3746 }
3747 return (1);
3748 }
3749
3750 static bool AscStopChip(PortAddr iop_base)
3751 {
3752 uchar cc_val;
3753
3754 cc_val =
3755 AscGetChipControl(iop_base) &
3756 (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG));
3757 AscSetChipControl(iop_base, (uchar)(cc_val | CC_HALT));
3758 AscSetChipIH(iop_base, INS_HALT);
3759 AscSetChipIH(iop_base, INS_RFLAG_WTM);
3760 if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) {
3761 return false;
3762 }
3763 return true;
3764 }
3765
3766 static bool AscIsChipHalted(PortAddr iop_base)
3767 {
3768 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
3769 if ((AscGetChipControl(iop_base) & CC_HALT) != 0) {
3770 return true;
3771 }
3772 }
3773 return false;
3774 }
3775
3776 static bool AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc)
3777 {
3778 PortAddr iop_base;
3779 int i = 10;
3780
3781 iop_base = asc_dvc->iop_base;
3782 while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE)
3783 && (i-- > 0)) {
3784 mdelay(100);
3785 }
3786 AscStopChip(iop_base);
3787 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT);
3788 udelay(60);
3789 AscSetChipIH(iop_base, INS_RFLAG_WTM);
3790 AscSetChipIH(iop_base, INS_HALT);
3791 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT);
3792 AscSetChipControl(iop_base, CC_HALT);
3793 mdelay(200);
3794 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
3795 AscSetChipStatus(iop_base, 0);
3796 return (AscIsChipHalted(iop_base));
3797 }
3798
3799 static int AscFindSignature(PortAddr iop_base)
3800 {
3801 ushort sig_word;
3802
3803 ASC_DBG(1, "AscGetChipSignatureByte(0x%x) 0x%x\n",
3804 iop_base, AscGetChipSignatureByte(iop_base));
3805 if (AscGetChipSignatureByte(iop_base) == (uchar)ASC_1000_ID1B) {
3806 ASC_DBG(1, "AscGetChipSignatureWord(0x%x) 0x%x\n",
3807 iop_base, AscGetChipSignatureWord(iop_base));
3808 sig_word = AscGetChipSignatureWord(iop_base);
3809 if ((sig_word == (ushort)ASC_1000_ID0W) ||
3810 (sig_word == (ushort)ASC_1000_ID0W_FIX)) {
3811 return (1);
3812 }
3813 }
3814 return (0);
3815 }
3816
3817 static void AscEnableInterrupt(PortAddr iop_base)
3818 {
3819 ushort cfg;
3820
3821 cfg = AscGetChipCfgLsw(iop_base);
3822 AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON);
3823 }
3824
3825 static void AscDisableInterrupt(PortAddr iop_base)
3826 {
3827 ushort cfg;
3828
3829 cfg = AscGetChipCfgLsw(iop_base);
3830 AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON));
3831 }
3832
3833 static uchar AscReadLramByte(PortAddr iop_base, ushort addr)
3834 {
3835 unsigned char byte_data;
3836 unsigned short word_data;
3837
3838 if (isodd_word(addr)) {
3839 AscSetChipLramAddr(iop_base, addr - 1);
3840 word_data = AscGetChipLramData(iop_base);
3841 byte_data = (word_data >> 8) & 0xFF;
3842 } else {
3843 AscSetChipLramAddr(iop_base, addr);
3844 word_data = AscGetChipLramData(iop_base);
3845 byte_data = word_data & 0xFF;
3846 }
3847 return byte_data;
3848 }
3849
3850 static ushort AscReadLramWord(PortAddr iop_base, ushort addr)
3851 {
3852 ushort word_data;
3853
3854 AscSetChipLramAddr(iop_base, addr);
3855 word_data = AscGetChipLramData(iop_base);
3856 return (word_data);
3857 }
3858
3859 #if CC_VERY_LONG_SG_LIST
3860 static u32 AscReadLramDWord(PortAddr iop_base, ushort addr)
3861 {
3862 ushort val_low, val_high;
3863 u32 dword_data;
3864
3865 AscSetChipLramAddr(iop_base, addr);
3866 val_low = AscGetChipLramData(iop_base);
3867 val_high = AscGetChipLramData(iop_base);
3868 dword_data = ((u32) val_high << 16) | (u32) val_low;
3869 return (dword_data);
3870 }
3871 #endif /* CC_VERY_LONG_SG_LIST */
3872
3873 static void
3874 AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words)
3875 {
3876 int i;
3877
3878 AscSetChipLramAddr(iop_base, s_addr);
3879 for (i = 0; i < words; i++) {
3880 AscSetChipLramData(iop_base, set_wval);
3881 }
3882 }
3883
3884 static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val)
3885 {
3886 AscSetChipLramAddr(iop_base, addr);
3887 AscSetChipLramData(iop_base, word_val);
3888 }
3889
3890 static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val)
3891 {
3892 ushort word_data;
3893
3894 if (isodd_word(addr)) {
3895 addr--;
3896 word_data = AscReadLramWord(iop_base, addr);
3897 word_data &= 0x00FF;
3898 word_data |= (((ushort)byte_val << 8) & 0xFF00);
3899 } else {
3900 word_data = AscReadLramWord(iop_base, addr);
3901 word_data &= 0xFF00;
3902 word_data |= ((ushort)byte_val & 0x00FF);
3903 }
3904 AscWriteLramWord(iop_base, addr, word_data);
3905 }
3906
3907 /*
3908 * Copy 2 bytes to LRAM.
3909 *
3910 * The source data is assumed to be in little-endian order in memory
3911 * and is maintained in little-endian order when written to LRAM.
3912 */
3913 static void
3914 AscMemWordCopyPtrToLram(PortAddr iop_base, ushort s_addr,
3915 const uchar *s_buffer, int words)
3916 {
3917 int i;
3918
3919 AscSetChipLramAddr(iop_base, s_addr);
3920 for (i = 0; i < 2 * words; i += 2) {
3921 /*
3922 * On a little-endian system the second argument below
3923 * produces a little-endian ushort which is written to
3924 * LRAM in little-endian order. On a big-endian system
3925 * the second argument produces a big-endian ushort which
3926 * is "transparently" byte-swapped by outpw() and written
3927 * in little-endian order to LRAM.
3928 */
3929 outpw(iop_base + IOP_RAM_DATA,
3930 ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);
3931 }
3932 }
3933
3934 /*
3935 * Copy 4 bytes to LRAM.
3936 *
3937 * The source data is assumed to be in little-endian order in memory
3938 * and is maintained in little-endian order when written to LRAM.
3939 */
3940 static void
3941 AscMemDWordCopyPtrToLram(PortAddr iop_base,
3942 ushort s_addr, uchar *s_buffer, int dwords)
3943 {
3944 int i;
3945
3946 AscSetChipLramAddr(iop_base, s_addr);
3947 for (i = 0; i < 4 * dwords; i += 4) {
3948 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]); /* LSW */
3949 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]); /* MSW */
3950 }
3951 }
3952
3953 /*
3954 * Copy 2 bytes from LRAM.
3955 *
3956 * The source data is assumed to be in little-endian order in LRAM
3957 * and is maintained in little-endian order when written to memory.
3958 */
3959 static void
3960 AscMemWordCopyPtrFromLram(PortAddr iop_base,
3961 ushort s_addr, uchar *d_buffer, int words)
3962 {
3963 int i;
3964 ushort word;
3965
3966 AscSetChipLramAddr(iop_base, s_addr);
3967 for (i = 0; i < 2 * words; i += 2) {
3968 word = inpw(iop_base + IOP_RAM_DATA);
3969 d_buffer[i] = word & 0xff;
3970 d_buffer[i + 1] = (word >> 8) & 0xff;
3971 }
3972 }
3973
3974 static u32 AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words)
3975 {
3976 u32 sum = 0;
3977 int i;
3978
3979 for (i = 0; i < words; i++, s_addr += 2) {
3980 sum += AscReadLramWord(iop_base, s_addr);
3981 }
3982 return (sum);
3983 }
3984
3985 static ushort AscInitLram(ASC_DVC_VAR *asc_dvc)
3986 {
3987 uchar i;
3988 ushort s_addr;
3989 PortAddr iop_base;
3990 ushort warn_code;
3991
3992 iop_base = asc_dvc->iop_base;
3993 warn_code = 0;
3994 AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0,
3995 (ushort)(((int)(asc_dvc->max_total_qng + 2 + 1) *
3996 64) >> 1));
3997 i = ASC_MIN_ACTIVE_QNO;
3998 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
3999 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4000 (uchar)(i + 1));
4001 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4002 (uchar)(asc_dvc->max_total_qng));
4003 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4004 (uchar)i);
4005 i++;
4006 s_addr += ASC_QBLK_SIZE;
4007 for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
4008 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4009 (uchar)(i + 1));
4010 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4011 (uchar)(i - 1));
4012 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4013 (uchar)i);
4014 }
4015 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4016 (uchar)ASC_QLINK_END);
4017 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4018 (uchar)(asc_dvc->max_total_qng - 1));
4019 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4020 (uchar)asc_dvc->max_total_qng);
4021 i++;
4022 s_addr += ASC_QBLK_SIZE;
4023 for (; i <= (uchar)(asc_dvc->max_total_qng + 3);
4024 i++, s_addr += ASC_QBLK_SIZE) {
4025 AscWriteLramByte(iop_base,
4026 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_FWD), i);
4027 AscWriteLramByte(iop_base,
4028 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_BWD), i);
4029 AscWriteLramByte(iop_base,
4030 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_QNO), i);
4031 }
4032 return warn_code;
4033 }
4034
4035 static u32
4036 AscLoadMicroCode(PortAddr iop_base, ushort s_addr,
4037 const uchar *mcode_buf, ushort mcode_size)
4038 {
4039 u32 chksum;
4040 ushort mcode_word_size;
4041 ushort mcode_chksum;
4042
4043 /* Write the microcode buffer starting at LRAM address 0. */
4044 mcode_word_size = (ushort)(mcode_size >> 1);
4045 AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size);
4046 AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size);
4047
4048 chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size);
4049 ASC_DBG(1, "chksum 0x%lx\n", (ulong)chksum);
4050 mcode_chksum = (ushort)AscMemSumLramWord(iop_base,
4051 (ushort)ASC_CODE_SEC_BEG,
4052 (ushort)((mcode_size -
4053 s_addr - (ushort)
4054 ASC_CODE_SEC_BEG) /
4055 2));
4056 ASC_DBG(1, "mcode_chksum 0x%lx\n", (ulong)mcode_chksum);
4057 AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum);
4058 AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size);
4059 return chksum;
4060 }
4061
4062 static void AscInitQLinkVar(ASC_DVC_VAR *asc_dvc)
4063 {
4064 PortAddr iop_base;
4065 int i;
4066 ushort lram_addr;
4067
4068 iop_base = asc_dvc->iop_base;
4069 AscPutRiscVarFreeQHead(iop_base, 1);
4070 AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng);
4071 AscPutVarFreeQHead(iop_base, 1);
4072 AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng);
4073 AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B,
4074 (uchar)((int)asc_dvc->max_total_qng + 1));
4075 AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B,
4076 (uchar)((int)asc_dvc->max_total_qng + 2));
4077 AscWriteLramByte(iop_base, (ushort)ASCV_TOTAL_READY_Q_B,
4078 asc_dvc->max_total_qng);
4079 AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0);
4080 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
4081 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0);
4082 AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0);
4083 AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0);
4084 AscPutQDoneInProgress(iop_base, 0);
4085 lram_addr = ASC_QADR_BEG;
4086 for (i = 0; i < 32; i++, lram_addr += 2) {
4087 AscWriteLramWord(iop_base, lram_addr, 0);
4088 }
4089 }
4090
4091 static ushort AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc)
4092 {
4093 int i;
4094 ushort warn_code;
4095 PortAddr iop_base;
4096 __le32 phy_addr;
4097 __le32 phy_size;
4098 struct asc_board *board = asc_dvc_to_board(asc_dvc);
4099
4100 iop_base = asc_dvc->iop_base;
4101 warn_code = 0;
4102 for (i = 0; i <= ASC_MAX_TID; i++) {
4103 AscPutMCodeInitSDTRAtID(iop_base, i,
4104 asc_dvc->cfg->sdtr_period_offset[i]);
4105 }
4106
4107 AscInitQLinkVar(asc_dvc);
4108 AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B,
4109 asc_dvc->cfg->disc_enable);
4110 AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B,
4111 ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id));
4112
4113 /* Ensure overrun buffer is aligned on an 8 byte boundary. */
4114 BUG_ON((unsigned long)asc_dvc->overrun_buf & 7);
4115 asc_dvc->overrun_dma = dma_map_single(board->dev, asc_dvc->overrun_buf,
4116 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
4117 if (dma_mapping_error(board->dev, asc_dvc->overrun_dma)) {
4118 warn_code = -ENOMEM;
4119 goto err_dma_map;
4120 }
4121 phy_addr = cpu_to_le32(asc_dvc->overrun_dma);
4122 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D,
4123 (uchar *)&phy_addr, 1);
4124 phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE);
4125 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D,
4126 (uchar *)&phy_size, 1);
4127
4128 asc_dvc->cfg->mcode_date =
4129 AscReadLramWord(iop_base, (ushort)ASCV_MC_DATE_W);
4130 asc_dvc->cfg->mcode_version =
4131 AscReadLramWord(iop_base, (ushort)ASCV_MC_VER_W);
4132
4133 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
4134 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
4135 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
4136 warn_code = UW_ERR;
4137 goto err_mcode_start;
4138 }
4139 if (AscStartChip(iop_base) != 1) {
4140 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
4141 warn_code = UW_ERR;
4142 goto err_mcode_start;
4143 }
4144
4145 return warn_code;
4146
4147 err_mcode_start:
4148 dma_unmap_single(board->dev, asc_dvc->overrun_dma,
4149 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
4150 err_dma_map:
4151 asc_dvc->overrun_dma = 0;
4152 return warn_code;
4153 }
4154
4155 static ushort AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc)
4156 {
4157 const struct firmware *fw;
4158 const char fwname[] = "advansys/mcode.bin";
4159 int err;
4160 unsigned long chksum;
4161 ushort warn_code;
4162 PortAddr iop_base;
4163
4164 iop_base = asc_dvc->iop_base;
4165 warn_code = 0;
4166 if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) &&
4167 !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) {
4168 AscResetChipAndScsiBus(asc_dvc);
4169 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
4170 }
4171 asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC;
4172 if (asc_dvc->err_code != 0)
4173 return UW_ERR;
4174 if (!AscFindSignature(asc_dvc->iop_base)) {
4175 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
4176 return warn_code;
4177 }
4178 AscDisableInterrupt(iop_base);
4179 warn_code |= AscInitLram(asc_dvc);
4180 if (asc_dvc->err_code != 0)
4181 return UW_ERR;
4182
4183 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4184 if (err) {
4185 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4186 fwname, err);
4187 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4188 return err;
4189 }
4190 if (fw->size < 4) {
4191 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4192 fw->size, fwname);
4193 release_firmware(fw);
4194 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4195 return -EINVAL;
4196 }
4197 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4198 (fw->data[1] << 8) | fw->data[0];
4199 ASC_DBG(1, "_asc_mcode_chksum 0x%lx\n", (ulong)chksum);
4200 if (AscLoadMicroCode(iop_base, 0, &fw->data[4],
4201 fw->size - 4) != chksum) {
4202 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4203 release_firmware(fw);
4204 return warn_code;
4205 }
4206 release_firmware(fw);
4207 warn_code |= AscInitMicroCodeVar(asc_dvc);
4208 if (!asc_dvc->overrun_dma)
4209 return warn_code;
4210 asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC;
4211 AscEnableInterrupt(iop_base);
4212 return warn_code;
4213 }
4214
4215 /*
4216 * Load the Microcode
4217 *
4218 * Write the microcode image to RISC memory starting at address 0.
4219 *
4220 * The microcode is stored compressed in the following format:
4221 *
4222 * 254 word (508 byte) table indexed by byte code followed
4223 * by the following byte codes:
4224 *
4225 * 1-Byte Code:
4226 * 00: Emit word 0 in table.
4227 * 01: Emit word 1 in table.
4228 * .
4229 * FD: Emit word 253 in table.
4230 *
4231 * Multi-Byte Code:
4232 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
4233 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
4234 *
4235 * Returns 0 or an error if the checksum doesn't match
4236 */
4237 static int AdvLoadMicrocode(AdvPortAddr iop_base, const unsigned char *buf,
4238 int size, int memsize, int chksum)
4239 {
4240 int i, j, end, len = 0;
4241 u32 sum;
4242
4243 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4244
4245 for (i = 253 * 2; i < size; i++) {
4246 if (buf[i] == 0xff) {
4247 unsigned short word = (buf[i + 3] << 8) | buf[i + 2];
4248 for (j = 0; j < buf[i + 1]; j++) {
4249 AdvWriteWordAutoIncLram(iop_base, word);
4250 len += 2;
4251 }
4252 i += 3;
4253 } else if (buf[i] == 0xfe) {
4254 unsigned short word = (buf[i + 2] << 8) | buf[i + 1];
4255 AdvWriteWordAutoIncLram(iop_base, word);
4256 i += 2;
4257 len += 2;
4258 } else {
4259 unsigned int off = buf[i] * 2;
4260 unsigned short word = (buf[off + 1] << 8) | buf[off];
4261 AdvWriteWordAutoIncLram(iop_base, word);
4262 len += 2;
4263 }
4264 }
4265
4266 end = len;
4267
4268 while (len < memsize) {
4269 AdvWriteWordAutoIncLram(iop_base, 0);
4270 len += 2;
4271 }
4272
4273 /* Verify the microcode checksum. */
4274 sum = 0;
4275 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4276
4277 for (len = 0; len < end; len += 2) {
4278 sum += AdvReadWordAutoIncLram(iop_base);
4279 }
4280
4281 if (sum != chksum)
4282 return ASC_IERR_MCODE_CHKSUM;
4283
4284 return 0;
4285 }
4286
4287 static void AdvBuildCarrierFreelist(struct adv_dvc_var *adv_dvc)
4288 {
4289 off_t carr_offset = 0, next_offset;
4290 dma_addr_t carr_paddr;
4291 int carr_num = ADV_CARRIER_BUFSIZE / sizeof(ADV_CARR_T), i;
4292
4293 for (i = 0; i < carr_num; i++) {
4294 carr_offset = i * sizeof(ADV_CARR_T);
4295 /* Get physical address of the carrier 'carrp'. */
4296 carr_paddr = adv_dvc->carrier_addr + carr_offset;
4297
4298 adv_dvc->carrier[i].carr_pa = cpu_to_le32(carr_paddr);
4299 adv_dvc->carrier[i].carr_va = cpu_to_le32(carr_offset);
4300 adv_dvc->carrier[i].areq_vpa = 0;
4301 next_offset = carr_offset + sizeof(ADV_CARR_T);
4302 if (i == carr_num)
4303 next_offset = ~0;
4304 adv_dvc->carrier[i].next_vpa = cpu_to_le32(next_offset);
4305 }
4306 /*
4307 * We cannot have a carrier with 'carr_va' of '0', as
4308 * a reference to this carrier would be interpreted as
4309 * list termination.
4310 * So start at carrier 1 with the freelist.
4311 */
4312 adv_dvc->carr_freelist = &adv_dvc->carrier[1];
4313 }
4314
4315 static ADV_CARR_T *adv_get_carrier(struct adv_dvc_var *adv_dvc, u32 offset)
4316 {
4317 int index;
4318
4319 BUG_ON(offset > ADV_CARRIER_BUFSIZE);
4320
4321 index = offset / sizeof(ADV_CARR_T);
4322 return &adv_dvc->carrier[index];
4323 }
4324
4325 static ADV_CARR_T *adv_get_next_carrier(struct adv_dvc_var *adv_dvc)
4326 {
4327 ADV_CARR_T *carrp = adv_dvc->carr_freelist;
4328 u32 next_vpa = le32_to_cpu(carrp->next_vpa);
4329
4330 if (next_vpa == 0 || next_vpa == ~0) {
4331 ASC_DBG(1, "invalid vpa offset 0x%x\n", next_vpa);
4332 return NULL;
4333 }
4334
4335 adv_dvc->carr_freelist = adv_get_carrier(adv_dvc, next_vpa);
4336 /*
4337 * insert stopper carrier to terminate list
4338 */
4339 carrp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
4340
4341 return carrp;
4342 }
4343
4344 /*
4345 * 'offset' is the index in the request pointer array
4346 */
4347 static adv_req_t * adv_get_reqp(struct adv_dvc_var *adv_dvc, u32 offset)
4348 {
4349 struct asc_board *boardp = adv_dvc->drv_ptr;
4350
4351 BUG_ON(offset > adv_dvc->max_host_qng);
4352 return &boardp->adv_reqp[offset];
4353 }
4354
4355 /*
4356 * Send an idle command to the chip and wait for completion.
4357 *
4358 * Command completion is polled for once per microsecond.
4359 *
4360 * The function can be called from anywhere including an interrupt handler.
4361 * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
4362 * functions to prevent reentrancy.
4363 *
4364 * Return Values:
4365 * ADV_TRUE - command completed successfully
4366 * ADV_FALSE - command failed
4367 * ADV_ERROR - command timed out
4368 */
4369 static int
4370 AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
4371 ushort idle_cmd, u32 idle_cmd_parameter)
4372 {
4373 int result, i, j;
4374 AdvPortAddr iop_base;
4375
4376 iop_base = asc_dvc->iop_base;
4377
4378 /*
4379 * Clear the idle command status which is set by the microcode
4380 * to a non-zero value to indicate when the command is completed.
4381 * The non-zero result is one of the IDLE_CMD_STATUS_* values
4382 */
4383 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort)0);
4384
4385 /*
4386 * Write the idle command value after the idle command parameter
4387 * has been written to avoid a race condition. If the order is not
4388 * followed, the microcode may process the idle command before the
4389 * parameters have been written to LRAM.
4390 */
4391 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER,
4392 cpu_to_le32(idle_cmd_parameter));
4393 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd);
4394
4395 /*
4396 * Tickle the RISC to tell it to process the idle command.
4397 */
4398 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B);
4399 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
4400 /*
4401 * Clear the tickle value. In the ASC-3550 the RISC flag
4402 * command 'clr_tickle_b' does not work unless the host
4403 * value is cleared.
4404 */
4405 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
4406 }
4407
4408 /* Wait for up to 100 millisecond for the idle command to timeout. */
4409 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) {
4410 /* Poll once each microsecond for command completion. */
4411 for (j = 0; j < SCSI_US_PER_MSEC; j++) {
4412 AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS,
4413 result);
4414 if (result != 0)
4415 return result;
4416 udelay(1);
4417 }
4418 }
4419
4420 BUG(); /* The idle command should never timeout. */
4421 return ADV_ERROR;
4422 }
4423
4424 /*
4425 * Reset SCSI Bus and purge all outstanding requests.
4426 *
4427 * Return Value:
4428 * ADV_TRUE(1) - All requests are purged and SCSI Bus is reset.
4429 * ADV_FALSE(0) - Microcode command failed.
4430 * ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
4431 * may be hung which requires driver recovery.
4432 */
4433 static int AdvResetSB(ADV_DVC_VAR *asc_dvc)
4434 {
4435 int status;
4436
4437 /*
4438 * Send the SCSI Bus Reset idle start idle command which asserts
4439 * the SCSI Bus Reset signal.
4440 */
4441 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_START, 0L);
4442 if (status != ADV_TRUE) {
4443 return status;
4444 }
4445
4446 /*
4447 * Delay for the specified SCSI Bus Reset hold time.
4448 *
4449 * The hold time delay is done on the host because the RISC has no
4450 * microsecond accurate timer.
4451 */
4452 udelay(ASC_SCSI_RESET_HOLD_TIME_US);
4453
4454 /*
4455 * Send the SCSI Bus Reset end idle command which de-asserts
4456 * the SCSI Bus Reset signal and purges any pending requests.
4457 */
4458 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_END, 0L);
4459 if (status != ADV_TRUE) {
4460 return status;
4461 }
4462
4463 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
4464
4465 return status;
4466 }
4467
4468 /*
4469 * Initialize the ASC-3550.
4470 *
4471 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
4472 *
4473 * For a non-fatal error return a warning code. If there are no warnings
4474 * then 0 is returned.
4475 *
4476 * Needed after initialization for error recovery.
4477 */
4478 static int AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc)
4479 {
4480 const struct firmware *fw;
4481 const char fwname[] = "advansys/3550.bin";
4482 AdvPortAddr iop_base;
4483 ushort warn_code;
4484 int begin_addr;
4485 int end_addr;
4486 ushort code_sum;
4487 int word;
4488 int i;
4489 int err;
4490 unsigned long chksum;
4491 ushort scsi_cfg1;
4492 uchar tid;
4493 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
4494 ushort wdtr_able = 0, sdtr_able, tagqng_able;
4495 uchar max_cmd[ADV_MAX_TID + 1];
4496
4497 /* If there is already an error, don't continue. */
4498 if (asc_dvc->err_code != 0)
4499 return ADV_ERROR;
4500
4501 /*
4502 * The caller must set 'chip_type' to ADV_CHIP_ASC3550.
4503 */
4504 if (asc_dvc->chip_type != ADV_CHIP_ASC3550) {
4505 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
4506 return ADV_ERROR;
4507 }
4508
4509 warn_code = 0;
4510 iop_base = asc_dvc->iop_base;
4511
4512 /*
4513 * Save the RISC memory BIOS region before writing the microcode.
4514 * The BIOS may already be loaded and using its RISC LRAM region
4515 * so its region must be saved and restored.
4516 *
4517 * Note: This code makes the assumption, which is currently true,
4518 * that a chip reset does not clear RISC LRAM.
4519 */
4520 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4521 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4522 bios_mem[i]);
4523 }
4524
4525 /*
4526 * Save current per TID negotiated values.
4527 */
4528 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 0x55AA) {
4529 ushort bios_version, major, minor;
4530
4531 bios_version =
4532 bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM) / 2];
4533 major = (bios_version >> 12) & 0xF;
4534 minor = (bios_version >> 8) & 0xF;
4535 if (major < 3 || (major == 3 && minor == 1)) {
4536 /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */
4537 AdvReadWordLram(iop_base, 0x120, wdtr_able);
4538 } else {
4539 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4540 }
4541 }
4542 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4543 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
4544 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4545 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
4546 max_cmd[tid]);
4547 }
4548
4549 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4550 if (err) {
4551 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4552 fwname, err);
4553 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
4554 return err;
4555 }
4556 if (fw->size < 4) {
4557 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4558 fw->size, fwname);
4559 release_firmware(fw);
4560 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
4561 return -EINVAL;
4562 }
4563 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4564 (fw->data[1] << 8) | fw->data[0];
4565 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
4566 fw->size - 4, ADV_3550_MEMSIZE,
4567 chksum);
4568 release_firmware(fw);
4569 if (asc_dvc->err_code)
4570 return ADV_ERROR;
4571
4572 /*
4573 * Restore the RISC memory BIOS region.
4574 */
4575 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4576 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4577 bios_mem[i]);
4578 }
4579
4580 /*
4581 * Calculate and write the microcode code checksum to the microcode
4582 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
4583 */
4584 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
4585 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
4586 code_sum = 0;
4587 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
4588 for (word = begin_addr; word < end_addr; word += 2) {
4589 code_sum += AdvReadWordAutoIncLram(iop_base);
4590 }
4591 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
4592
4593 /*
4594 * Read and save microcode version and date.
4595 */
4596 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
4597 asc_dvc->cfg->mcode_date);
4598 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
4599 asc_dvc->cfg->mcode_version);
4600
4601 /*
4602 * Set the chip type to indicate the ASC3550.
4603 */
4604 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550);
4605
4606 /*
4607 * If the PCI Configuration Command Register "Parity Error Response
4608 * Control" Bit was clear (0), then set the microcode variable
4609 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
4610 * to ignore DMA parity errors.
4611 */
4612 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
4613 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
4614 word |= CONTROL_FLAG_IGNORE_PERR;
4615 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
4616 }
4617
4618 /*
4619 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO
4620 * threshold of 128 bytes. This register is only accessible to the host.
4621 */
4622 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
4623 START_CTL_EMFU | READ_CMD_MRM);
4624
4625 /*
4626 * Microcode operating variables for WDTR, SDTR, and command tag
4627 * queuing will be set in slave_configure() based on what a
4628 * device reports it is capable of in Inquiry byte 7.
4629 *
4630 * If SCSI Bus Resets have been disabled, then directly set
4631 * SDTR and WDTR from the EEPROM configuration. This will allow
4632 * the BIOS and warm boot to work without a SCSI bus hang on
4633 * the Inquiry caused by host and target mismatched DTR values.
4634 * Without the SCSI Bus Reset, before an Inquiry a device can't
4635 * be assumed to be in Asynchronous, Narrow mode.
4636 */
4637 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
4638 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
4639 asc_dvc->wdtr_able);
4640 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
4641 asc_dvc->sdtr_able);
4642 }
4643
4644 /*
4645 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
4646 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
4647 * bitmask. These values determine the maximum SDTR speed negotiated
4648 * with a device.
4649 *
4650 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
4651 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
4652 * without determining here whether the device supports SDTR.
4653 *
4654 * 4-bit speed SDTR speed name
4655 * =========== ===============
4656 * 0000b (0x0) SDTR disabled
4657 * 0001b (0x1) 5 Mhz
4658 * 0010b (0x2) 10 Mhz
4659 * 0011b (0x3) 20 Mhz (Ultra)
4660 * 0100b (0x4) 40 Mhz (LVD/Ultra2)
4661 * 0101b (0x5) 80 Mhz (LVD2/Ultra3)
4662 * 0110b (0x6) Undefined
4663 * .
4664 * 1111b (0xF) Undefined
4665 */
4666 word = 0;
4667 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4668 if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able) {
4669 /* Set Ultra speed for TID 'tid'. */
4670 word |= (0x3 << (4 * (tid % 4)));
4671 } else {
4672 /* Set Fast speed for TID 'tid'. */
4673 word |= (0x2 << (4 * (tid % 4)));
4674 }
4675 if (tid == 3) { /* Check if done with sdtr_speed1. */
4676 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word);
4677 word = 0;
4678 } else if (tid == 7) { /* Check if done with sdtr_speed2. */
4679 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word);
4680 word = 0;
4681 } else if (tid == 11) { /* Check if done with sdtr_speed3. */
4682 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word);
4683 word = 0;
4684 } else if (tid == 15) { /* Check if done with sdtr_speed4. */
4685 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word);
4686 /* End of loop. */
4687 }
4688 }
4689
4690 /*
4691 * Set microcode operating variable for the disconnect per TID bitmask.
4692 */
4693 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
4694 asc_dvc->cfg->disc_enable);
4695
4696 /*
4697 * Set SCSI_CFG0 Microcode Default Value.
4698 *
4699 * The microcode will set the SCSI_CFG0 register using this value
4700 * after it is started below.
4701 */
4702 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
4703 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
4704 asc_dvc->chip_scsi_id);
4705
4706 /*
4707 * Determine SCSI_CFG1 Microcode Default Value.
4708 *
4709 * The microcode will set the SCSI_CFG1 register using this value
4710 * after it is started below.
4711 */
4712
4713 /* Read current SCSI_CFG1 Register value. */
4714 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
4715
4716 /*
4717 * If all three connectors are in use, return an error.
4718 */
4719 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
4720 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) {
4721 asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION;
4722 return ADV_ERROR;
4723 }
4724
4725 /*
4726 * If the internal narrow cable is reversed all of the SCSI_CTRL
4727 * register signals will be set. Check for and return an error if
4728 * this condition is found.
4729 */
4730 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
4731 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
4732 return ADV_ERROR;
4733 }
4734
4735 /*
4736 * If this is a differential board and a single-ended device
4737 * is attached to one of the connectors, return an error.
4738 */
4739 if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0) {
4740 asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE;
4741 return ADV_ERROR;
4742 }
4743
4744 /*
4745 * If automatic termination control is enabled, then set the
4746 * termination value based on a table listed in a_condor.h.
4747 *
4748 * If manual termination was specified with an EEPROM setting
4749 * then 'termination' was set-up in AdvInitFrom3550EEPROM() and
4750 * is ready to be 'ored' into SCSI_CFG1.
4751 */
4752 if (asc_dvc->cfg->termination == 0) {
4753 /*
4754 * The software always controls termination by setting TERM_CTL_SEL.
4755 * If TERM_CTL_SEL were set to 0, the hardware would set termination.
4756 */
4757 asc_dvc->cfg->termination |= TERM_CTL_SEL;
4758
4759 switch (scsi_cfg1 & CABLE_DETECT) {
4760 /* TERM_CTL_H: on, TERM_CTL_L: on */
4761 case 0x3:
4762 case 0x7:
4763 case 0xB:
4764 case 0xD:
4765 case 0xE:
4766 case 0xF:
4767 asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L);
4768 break;
4769
4770 /* TERM_CTL_H: on, TERM_CTL_L: off */
4771 case 0x1:
4772 case 0x5:
4773 case 0x9:
4774 case 0xA:
4775 case 0xC:
4776 asc_dvc->cfg->termination |= TERM_CTL_H;
4777 break;
4778
4779 /* TERM_CTL_H: off, TERM_CTL_L: off */
4780 case 0x2:
4781 case 0x6:
4782 break;
4783 }
4784 }
4785
4786 /*
4787 * Clear any set TERM_CTL_H and TERM_CTL_L bits.
4788 */
4789 scsi_cfg1 &= ~TERM_CTL;
4790
4791 /*
4792 * Invert the TERM_CTL_H and TERM_CTL_L bits and then
4793 * set 'scsi_cfg1'. The TERM_POL bit does not need to be
4794 * referenced, because the hardware internally inverts
4795 * the Termination High and Low bits if TERM_POL is set.
4796 */
4797 scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL));
4798
4799 /*
4800 * Set SCSI_CFG1 Microcode Default Value
4801 *
4802 * Set filter value and possibly modified termination control
4803 * bits in the Microcode SCSI_CFG1 Register Value.
4804 *
4805 * The microcode will set the SCSI_CFG1 register using this value
4806 * after it is started below.
4807 */
4808 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1,
4809 FLTR_DISABLE | scsi_cfg1);
4810
4811 /*
4812 * Set MEM_CFG Microcode Default Value
4813 *
4814 * The microcode will set the MEM_CFG register using this value
4815 * after it is started below.
4816 *
4817 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
4818 * are defined.
4819 *
4820 * ASC-3550 has 8KB internal memory.
4821 */
4822 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
4823 BIOS_EN | RAM_SZ_8KB);
4824
4825 /*
4826 * Set SEL_MASK Microcode Default Value
4827 *
4828 * The microcode will set the SEL_MASK register using this value
4829 * after it is started below.
4830 */
4831 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
4832 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
4833
4834 AdvBuildCarrierFreelist(asc_dvc);
4835
4836 /*
4837 * Set-up the Host->RISC Initiator Command Queue (ICQ).
4838 */
4839
4840 asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc);
4841 if (!asc_dvc->icq_sp) {
4842 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
4843 return ADV_ERROR;
4844 }
4845
4846 /*
4847 * Set RISC ICQ physical address start value.
4848 */
4849 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
4850
4851 /*
4852 * Set-up the RISC->Host Initiator Response Queue (IRQ).
4853 */
4854 asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc);
4855 if (!asc_dvc->irq_sp) {
4856 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
4857 return ADV_ERROR;
4858 }
4859
4860 /*
4861 * Set RISC IRQ physical address start value.
4862 */
4863 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
4864 asc_dvc->carr_pending_cnt = 0;
4865
4866 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
4867 (ADV_INTR_ENABLE_HOST_INTR |
4868 ADV_INTR_ENABLE_GLOBAL_INTR));
4869
4870 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
4871 AdvWriteWordRegister(iop_base, IOPW_PC, word);
4872
4873 /* finally, finally, gentlemen, start your engine */
4874 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
4875
4876 /*
4877 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
4878 * Resets should be performed. The RISC has to be running
4879 * to issue a SCSI Bus Reset.
4880 */
4881 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
4882 /*
4883 * If the BIOS Signature is present in memory, restore the
4884 * BIOS Handshake Configuration Table and do not perform
4885 * a SCSI Bus Reset.
4886 */
4887 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
4888 0x55AA) {
4889 /*
4890 * Restore per TID negotiated values.
4891 */
4892 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4893 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4894 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
4895 tagqng_able);
4896 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4897 AdvWriteByteLram(iop_base,
4898 ASC_MC_NUMBER_OF_MAX_CMD + tid,
4899 max_cmd[tid]);
4900 }
4901 } else {
4902 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
4903 warn_code = ASC_WARN_BUSRESET_ERROR;
4904 }
4905 }
4906 }
4907
4908 return warn_code;
4909 }
4910
4911 /*
4912 * Initialize the ASC-38C0800.
4913 *
4914 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
4915 *
4916 * For a non-fatal error return a warning code. If there are no warnings
4917 * then 0 is returned.
4918 *
4919 * Needed after initialization for error recovery.
4920 */
4921 static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc)
4922 {
4923 const struct firmware *fw;
4924 const char fwname[] = "advansys/38C0800.bin";
4925 AdvPortAddr iop_base;
4926 ushort warn_code;
4927 int begin_addr;
4928 int end_addr;
4929 ushort code_sum;
4930 int word;
4931 int i;
4932 int err;
4933 unsigned long chksum;
4934 ushort scsi_cfg1;
4935 uchar byte;
4936 uchar tid;
4937 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
4938 ushort wdtr_able, sdtr_able, tagqng_able;
4939 uchar max_cmd[ADV_MAX_TID + 1];
4940
4941 /* If there is already an error, don't continue. */
4942 if (asc_dvc->err_code != 0)
4943 return ADV_ERROR;
4944
4945 /*
4946 * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800.
4947 */
4948 if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800) {
4949 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
4950 return ADV_ERROR;
4951 }
4952
4953 warn_code = 0;
4954 iop_base = asc_dvc->iop_base;
4955
4956 /*
4957 * Save the RISC memory BIOS region before writing the microcode.
4958 * The BIOS may already be loaded and using its RISC LRAM region
4959 * so its region must be saved and restored.
4960 *
4961 * Note: This code makes the assumption, which is currently true,
4962 * that a chip reset does not clear RISC LRAM.
4963 */
4964 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4965 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4966 bios_mem[i]);
4967 }
4968
4969 /*
4970 * Save current per TID negotiated values.
4971 */
4972 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4973 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4974 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
4975 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4976 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
4977 max_cmd[tid]);
4978 }
4979
4980 /*
4981 * RAM BIST (RAM Built-In Self Test)
4982 *
4983 * Address : I/O base + offset 0x38h register (byte).
4984 * Function: Bit 7-6(RW) : RAM mode
4985 * Normal Mode : 0x00
4986 * Pre-test Mode : 0x40
4987 * RAM Test Mode : 0x80
4988 * Bit 5 : unused
4989 * Bit 4(RO) : Done bit
4990 * Bit 3-0(RO) : Status
4991 * Host Error : 0x08
4992 * Int_RAM Error : 0x04
4993 * RISC Error : 0x02
4994 * SCSI Error : 0x01
4995 * No Error : 0x00
4996 *
4997 * Note: RAM BIST code should be put right here, before loading the
4998 * microcode and after saving the RISC memory BIOS region.
4999 */
5000
5001 /*
5002 * LRAM Pre-test
5003 *
5004 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
5005 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
5006 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
5007 * to NORMAL_MODE, return an error too.
5008 */
5009 for (i = 0; i < 2; i++) {
5010 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
5011 mdelay(10); /* Wait for 10ms before reading back. */
5012 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5013 if ((byte & RAM_TEST_DONE) == 0
5014 || (byte & 0x0F) != PRE_TEST_VALUE) {
5015 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5016 return ADV_ERROR;
5017 }
5018
5019 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5020 mdelay(10); /* Wait for 10ms before reading back. */
5021 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
5022 != NORMAL_VALUE) {
5023 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5024 return ADV_ERROR;
5025 }
5026 }
5027
5028 /*
5029 * LRAM Test - It takes about 1.5 ms to run through the test.
5030 *
5031 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
5032 * If Done bit not set or Status not 0, save register byte, set the
5033 * err_code, and return an error.
5034 */
5035 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
5036 mdelay(10); /* Wait for 10ms before checking status. */
5037
5038 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5039 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
5040 /* Get here if Done bit not set or Status not 0. */
5041 asc_dvc->bist_err_code = byte; /* for BIOS display message */
5042 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
5043 return ADV_ERROR;
5044 }
5045
5046 /* We need to reset back to normal mode after LRAM test passes. */
5047 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5048
5049 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
5050 if (err) {
5051 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
5052 fwname, err);
5053 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5054 return err;
5055 }
5056 if (fw->size < 4) {
5057 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
5058 fw->size, fwname);
5059 release_firmware(fw);
5060 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5061 return -EINVAL;
5062 }
5063 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
5064 (fw->data[1] << 8) | fw->data[0];
5065 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
5066 fw->size - 4, ADV_38C0800_MEMSIZE,
5067 chksum);
5068 release_firmware(fw);
5069 if (asc_dvc->err_code)
5070 return ADV_ERROR;
5071
5072 /*
5073 * Restore the RISC memory BIOS region.
5074 */
5075 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5076 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5077 bios_mem[i]);
5078 }
5079
5080 /*
5081 * Calculate and write the microcode code checksum to the microcode
5082 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
5083 */
5084 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
5085 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
5086 code_sum = 0;
5087 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
5088 for (word = begin_addr; word < end_addr; word += 2) {
5089 code_sum += AdvReadWordAutoIncLram(iop_base);
5090 }
5091 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
5092
5093 /*
5094 * Read microcode version and date.
5095 */
5096 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
5097 asc_dvc->cfg->mcode_date);
5098 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
5099 asc_dvc->cfg->mcode_version);
5100
5101 /*
5102 * Set the chip type to indicate the ASC38C0800.
5103 */
5104 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800);
5105
5106 /*
5107 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
5108 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
5109 * cable detection and then we are able to read C_DET[3:0].
5110 *
5111 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
5112 * Microcode Default Value' section below.
5113 */
5114 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5115 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
5116 scsi_cfg1 | DIS_TERM_DRV);
5117
5118 /*
5119 * If the PCI Configuration Command Register "Parity Error Response
5120 * Control" Bit was clear (0), then set the microcode variable
5121 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
5122 * to ignore DMA parity errors.
5123 */
5124 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
5125 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5126 word |= CONTROL_FLAG_IGNORE_PERR;
5127 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5128 }
5129
5130 /*
5131 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2]
5132 * bits for the default FIFO threshold.
5133 *
5134 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
5135 *
5136 * For DMA Errata #4 set the BC_THRESH_ENB bit.
5137 */
5138 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
5139 BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH |
5140 READ_CMD_MRM);
5141
5142 /*
5143 * Microcode operating variables for WDTR, SDTR, and command tag
5144 * queuing will be set in slave_configure() based on what a
5145 * device reports it is capable of in Inquiry byte 7.
5146 *
5147 * If SCSI Bus Resets have been disabled, then directly set
5148 * SDTR and WDTR from the EEPROM configuration. This will allow
5149 * the BIOS and warm boot to work without a SCSI bus hang on
5150 * the Inquiry caused by host and target mismatched DTR values.
5151 * Without the SCSI Bus Reset, before an Inquiry a device can't
5152 * be assumed to be in Asynchronous, Narrow mode.
5153 */
5154 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
5155 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
5156 asc_dvc->wdtr_able);
5157 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
5158 asc_dvc->sdtr_able);
5159 }
5160
5161 /*
5162 * Set microcode operating variables for DISC and SDTR_SPEED1,
5163 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
5164 * configuration values.
5165 *
5166 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
5167 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
5168 * without determining here whether the device supports SDTR.
5169 */
5170 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
5171 asc_dvc->cfg->disc_enable);
5172 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
5173 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
5174 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
5175 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
5176
5177 /*
5178 * Set SCSI_CFG0 Microcode Default Value.
5179 *
5180 * The microcode will set the SCSI_CFG0 register using this value
5181 * after it is started below.
5182 */
5183 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
5184 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
5185 asc_dvc->chip_scsi_id);
5186
5187 /*
5188 * Determine SCSI_CFG1 Microcode Default Value.
5189 *
5190 * The microcode will set the SCSI_CFG1 register using this value
5191 * after it is started below.
5192 */
5193
5194 /* Read current SCSI_CFG1 Register value. */
5195 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5196
5197 /*
5198 * If the internal narrow cable is reversed all of the SCSI_CTRL
5199 * register signals will be set. Check for and return an error if
5200 * this condition is found.
5201 */
5202 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
5203 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
5204 return ADV_ERROR;
5205 }
5206
5207 /*
5208 * All kind of combinations of devices attached to one of four
5209 * connectors are acceptable except HVD device attached. For example,
5210 * LVD device can be attached to SE connector while SE device attached
5211 * to LVD connector. If LVD device attached to SE connector, it only
5212 * runs up to Ultra speed.
5213 *
5214 * If an HVD device is attached to one of LVD connectors, return an
5215 * error. However, there is no way to detect HVD device attached to
5216 * SE connectors.
5217 */
5218 if (scsi_cfg1 & HVD) {
5219 asc_dvc->err_code = ASC_IERR_HVD_DEVICE;
5220 return ADV_ERROR;
5221 }
5222
5223 /*
5224 * If either SE or LVD automatic termination control is enabled, then
5225 * set the termination value based on a table listed in a_condor.h.
5226 *
5227 * If manual termination was specified with an EEPROM setting then
5228 * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready
5229 * to be 'ored' into SCSI_CFG1.
5230 */
5231 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
5232 /* SE automatic termination control is enabled. */
5233 switch (scsi_cfg1 & C_DET_SE) {
5234 /* TERM_SE_HI: on, TERM_SE_LO: on */
5235 case 0x1:
5236 case 0x2:
5237 case 0x3:
5238 asc_dvc->cfg->termination |= TERM_SE;
5239 break;
5240
5241 /* TERM_SE_HI: on, TERM_SE_LO: off */
5242 case 0x0:
5243 asc_dvc->cfg->termination |= TERM_SE_HI;
5244 break;
5245 }
5246 }
5247
5248 if ((asc_dvc->cfg->termination & TERM_LVD) == 0) {
5249 /* LVD automatic termination control is enabled. */
5250 switch (scsi_cfg1 & C_DET_LVD) {
5251 /* TERM_LVD_HI: on, TERM_LVD_LO: on */
5252 case 0x4:
5253 case 0x8:
5254 case 0xC:
5255 asc_dvc->cfg->termination |= TERM_LVD;
5256 break;
5257
5258 /* TERM_LVD_HI: off, TERM_LVD_LO: off */
5259 case 0x0:
5260 break;
5261 }
5262 }
5263
5264 /*
5265 * Clear any set TERM_SE and TERM_LVD bits.
5266 */
5267 scsi_cfg1 &= (~TERM_SE & ~TERM_LVD);
5268
5269 /*
5270 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
5271 */
5272 scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0);
5273
5274 /*
5275 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE
5276 * bits and set possibly modified termination control bits in the
5277 * Microcode SCSI_CFG1 Register Value.
5278 */
5279 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE);
5280
5281 /*
5282 * Set SCSI_CFG1 Microcode Default Value
5283 *
5284 * Set possibly modified termination control and reset DIS_TERM_DRV
5285 * bits in the Microcode SCSI_CFG1 Register Value.
5286 *
5287 * The microcode will set the SCSI_CFG1 register using this value
5288 * after it is started below.
5289 */
5290 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
5291
5292 /*
5293 * Set MEM_CFG Microcode Default Value
5294 *
5295 * The microcode will set the MEM_CFG register using this value
5296 * after it is started below.
5297 *
5298 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
5299 * are defined.
5300 *
5301 * ASC-38C0800 has 16KB internal memory.
5302 */
5303 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5304 BIOS_EN | RAM_SZ_16KB);
5305
5306 /*
5307 * Set SEL_MASK Microcode Default Value
5308 *
5309 * The microcode will set the SEL_MASK register using this value
5310 * after it is started below.
5311 */
5312 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
5313 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
5314
5315 AdvBuildCarrierFreelist(asc_dvc);
5316
5317 /*
5318 * Set-up the Host->RISC Initiator Command Queue (ICQ).
5319 */
5320
5321 asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc);
5322 if (!asc_dvc->icq_sp) {
5323 ASC_DBG(0, "Failed to get ICQ carrier\n");
5324 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5325 return ADV_ERROR;
5326 }
5327
5328 /*
5329 * Set RISC ICQ physical address start value.
5330 * carr_pa is LE, must be native before write
5331 */
5332 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
5333
5334 /*
5335 * Set-up the RISC->Host Initiator Response Queue (IRQ).
5336 */
5337 asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc);
5338 if (!asc_dvc->irq_sp) {
5339 ASC_DBG(0, "Failed to get IRQ carrier\n");
5340 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5341 return ADV_ERROR;
5342 }
5343
5344 /*
5345 * Set RISC IRQ physical address start value.
5346 *
5347 * carr_pa is LE, must be native before write *
5348 */
5349 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
5350 asc_dvc->carr_pending_cnt = 0;
5351
5352 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
5353 (ADV_INTR_ENABLE_HOST_INTR |
5354 ADV_INTR_ENABLE_GLOBAL_INTR));
5355
5356 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
5357 AdvWriteWordRegister(iop_base, IOPW_PC, word);
5358
5359 /* finally, finally, gentlemen, start your engine */
5360 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
5361
5362 /*
5363 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
5364 * Resets should be performed. The RISC has to be running
5365 * to issue a SCSI Bus Reset.
5366 */
5367 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
5368 /*
5369 * If the BIOS Signature is present in memory, restore the
5370 * BIOS Handshake Configuration Table and do not perform
5371 * a SCSI Bus Reset.
5372 */
5373 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
5374 0x55AA) {
5375 /*
5376 * Restore per TID negotiated values.
5377 */
5378 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5379 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5380 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
5381 tagqng_able);
5382 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5383 AdvWriteByteLram(iop_base,
5384 ASC_MC_NUMBER_OF_MAX_CMD + tid,
5385 max_cmd[tid]);
5386 }
5387 } else {
5388 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
5389 warn_code = ASC_WARN_BUSRESET_ERROR;
5390 }
5391 }
5392 }
5393
5394 return warn_code;
5395 }
5396
5397 /*
5398 * Initialize the ASC-38C1600.
5399 *
5400 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
5401 *
5402 * For a non-fatal error return a warning code. If there are no warnings
5403 * then 0 is returned.
5404 *
5405 * Needed after initialization for error recovery.
5406 */
5407 static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc)
5408 {
5409 const struct firmware *fw;
5410 const char fwname[] = "advansys/38C1600.bin";
5411 AdvPortAddr iop_base;
5412 ushort warn_code;
5413 int begin_addr;
5414 int end_addr;
5415 ushort code_sum;
5416 long word;
5417 int i;
5418 int err;
5419 unsigned long chksum;
5420 ushort scsi_cfg1;
5421 uchar byte;
5422 uchar tid;
5423 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
5424 ushort wdtr_able, sdtr_able, ppr_able, tagqng_able;
5425 uchar max_cmd[ASC_MAX_TID + 1];
5426
5427 /* If there is already an error, don't continue. */
5428 if (asc_dvc->err_code != 0) {
5429 return ADV_ERROR;
5430 }
5431
5432 /*
5433 * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600.
5434 */
5435 if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
5436 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
5437 return ADV_ERROR;
5438 }
5439
5440 warn_code = 0;
5441 iop_base = asc_dvc->iop_base;
5442
5443 /*
5444 * Save the RISC memory BIOS region before writing the microcode.
5445 * The BIOS may already be loaded and using its RISC LRAM region
5446 * so its region must be saved and restored.
5447 *
5448 * Note: This code makes the assumption, which is currently true,
5449 * that a chip reset does not clear RISC LRAM.
5450 */
5451 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5452 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5453 bios_mem[i]);
5454 }
5455
5456 /*
5457 * Save current per TID negotiated values.
5458 */
5459 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5460 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5461 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5462 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5463 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
5464 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5465 max_cmd[tid]);
5466 }
5467
5468 /*
5469 * RAM BIST (Built-In Self Test)
5470 *
5471 * Address : I/O base + offset 0x38h register (byte).
5472 * Function: Bit 7-6(RW) : RAM mode
5473 * Normal Mode : 0x00
5474 * Pre-test Mode : 0x40
5475 * RAM Test Mode : 0x80
5476 * Bit 5 : unused
5477 * Bit 4(RO) : Done bit
5478 * Bit 3-0(RO) : Status
5479 * Host Error : 0x08
5480 * Int_RAM Error : 0x04
5481 * RISC Error : 0x02
5482 * SCSI Error : 0x01
5483 * No Error : 0x00
5484 *
5485 * Note: RAM BIST code should be put right here, before loading the
5486 * microcode and after saving the RISC memory BIOS region.
5487 */
5488
5489 /*
5490 * LRAM Pre-test
5491 *
5492 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
5493 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
5494 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
5495 * to NORMAL_MODE, return an error too.
5496 */
5497 for (i = 0; i < 2; i++) {
5498 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
5499 mdelay(10); /* Wait for 10ms before reading back. */
5500 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5501 if ((byte & RAM_TEST_DONE) == 0
5502 || (byte & 0x0F) != PRE_TEST_VALUE) {
5503 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5504 return ADV_ERROR;
5505 }
5506
5507 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5508 mdelay(10); /* Wait for 10ms before reading back. */
5509 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
5510 != NORMAL_VALUE) {
5511 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5512 return ADV_ERROR;
5513 }
5514 }
5515
5516 /*
5517 * LRAM Test - It takes about 1.5 ms to run through the test.
5518 *
5519 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
5520 * If Done bit not set or Status not 0, save register byte, set the
5521 * err_code, and return an error.
5522 */
5523 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
5524 mdelay(10); /* Wait for 10ms before checking status. */
5525
5526 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5527 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
5528 /* Get here if Done bit not set or Status not 0. */
5529 asc_dvc->bist_err_code = byte; /* for BIOS display message */
5530 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
5531 return ADV_ERROR;
5532 }
5533
5534 /* We need to reset back to normal mode after LRAM test passes. */
5535 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5536
5537 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
5538 if (err) {
5539 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
5540 fwname, err);
5541 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5542 return err;
5543 }
5544 if (fw->size < 4) {
5545 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
5546 fw->size, fwname);
5547 release_firmware(fw);
5548 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5549 return -EINVAL;
5550 }
5551 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
5552 (fw->data[1] << 8) | fw->data[0];
5553 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
5554 fw->size - 4, ADV_38C1600_MEMSIZE,
5555 chksum);
5556 release_firmware(fw);
5557 if (asc_dvc->err_code)
5558 return ADV_ERROR;
5559
5560 /*
5561 * Restore the RISC memory BIOS region.
5562 */
5563 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5564 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5565 bios_mem[i]);
5566 }
5567
5568 /*
5569 * Calculate and write the microcode code checksum to the microcode
5570 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
5571 */
5572 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
5573 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
5574 code_sum = 0;
5575 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
5576 for (word = begin_addr; word < end_addr; word += 2) {
5577 code_sum += AdvReadWordAutoIncLram(iop_base);
5578 }
5579 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
5580
5581 /*
5582 * Read microcode version and date.
5583 */
5584 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
5585 asc_dvc->cfg->mcode_date);
5586 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
5587 asc_dvc->cfg->mcode_version);
5588
5589 /*
5590 * Set the chip type to indicate the ASC38C1600.
5591 */
5592 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600);
5593
5594 /*
5595 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
5596 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
5597 * cable detection and then we are able to read C_DET[3:0].
5598 *
5599 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
5600 * Microcode Default Value' section below.
5601 */
5602 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5603 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
5604 scsi_cfg1 | DIS_TERM_DRV);
5605
5606 /*
5607 * If the PCI Configuration Command Register "Parity Error Response
5608 * Control" Bit was clear (0), then set the microcode variable
5609 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
5610 * to ignore DMA parity errors.
5611 */
5612 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
5613 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5614 word |= CONTROL_FLAG_IGNORE_PERR;
5615 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5616 }
5617
5618 /*
5619 * If the BIOS control flag AIPP (Asynchronous Information
5620 * Phase Protection) disable bit is not set, then set the firmware
5621 * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable
5622 * AIPP checking and encoding.
5623 */
5624 if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) {
5625 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5626 word |= CONTROL_FLAG_ENABLE_AIPP;
5627 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5628 }
5629
5630 /*
5631 * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4],
5632 * and START_CTL_TH [3:2].
5633 */
5634 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
5635 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
5636
5637 /*
5638 * Microcode operating variables for WDTR, SDTR, and command tag
5639 * queuing will be set in slave_configure() based on what a
5640 * device reports it is capable of in Inquiry byte 7.
5641 *
5642 * If SCSI Bus Resets have been disabled, then directly set
5643 * SDTR and WDTR from the EEPROM configuration. This will allow
5644 * the BIOS and warm boot to work without a SCSI bus hang on
5645 * the Inquiry caused by host and target mismatched DTR values.
5646 * Without the SCSI Bus Reset, before an Inquiry a device can't
5647 * be assumed to be in Asynchronous, Narrow mode.
5648 */
5649 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
5650 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
5651 asc_dvc->wdtr_able);
5652 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
5653 asc_dvc->sdtr_able);
5654 }
5655
5656 /*
5657 * Set microcode operating variables for DISC and SDTR_SPEED1,
5658 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
5659 * configuration values.
5660 *
5661 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
5662 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
5663 * without determining here whether the device supports SDTR.
5664 */
5665 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
5666 asc_dvc->cfg->disc_enable);
5667 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
5668 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
5669 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
5670 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
5671
5672 /*
5673 * Set SCSI_CFG0 Microcode Default Value.
5674 *
5675 * The microcode will set the SCSI_CFG0 register using this value
5676 * after it is started below.
5677 */
5678 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
5679 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
5680 asc_dvc->chip_scsi_id);
5681
5682 /*
5683 * Calculate SCSI_CFG1 Microcode Default Value.
5684 *
5685 * The microcode will set the SCSI_CFG1 register using this value
5686 * after it is started below.
5687 *
5688 * Each ASC-38C1600 function has only two cable detect bits.
5689 * The bus mode override bits are in IOPB_SOFT_OVER_WR.
5690 */
5691 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5692
5693 /*
5694 * If the cable is reversed all of the SCSI_CTRL register signals
5695 * will be set. Check for and return an error if this condition is
5696 * found.
5697 */
5698 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
5699 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
5700 return ADV_ERROR;
5701 }
5702
5703 /*
5704 * Each ASC-38C1600 function has two connectors. Only an HVD device
5705 * can not be connected to either connector. An LVD device or SE device
5706 * may be connected to either connecor. If an SE device is connected,
5707 * then at most Ultra speed (20 Mhz) can be used on both connectors.
5708 *
5709 * If an HVD device is attached, return an error.
5710 */
5711 if (scsi_cfg1 & HVD) {
5712 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
5713 return ADV_ERROR;
5714 }
5715
5716 /*
5717 * Each function in the ASC-38C1600 uses only the SE cable detect and
5718 * termination because there are two connectors for each function. Each
5719 * function may use either LVD or SE mode. Corresponding the SE automatic
5720 * termination control EEPROM bits are used for each function. Each
5721 * function has its own EEPROM. If SE automatic control is enabled for
5722 * the function, then set the termination value based on a table listed
5723 * in a_condor.h.
5724 *
5725 * If manual termination is specified in the EEPROM for the function,
5726 * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is
5727 * ready to be 'ored' into SCSI_CFG1.
5728 */
5729 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
5730 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
5731 /* SE automatic termination control is enabled. */
5732 switch (scsi_cfg1 & C_DET_SE) {
5733 /* TERM_SE_HI: on, TERM_SE_LO: on */
5734 case 0x1:
5735 case 0x2:
5736 case 0x3:
5737 asc_dvc->cfg->termination |= TERM_SE;
5738 break;
5739
5740 case 0x0:
5741 if (PCI_FUNC(pdev->devfn) == 0) {
5742 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
5743 } else {
5744 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
5745 asc_dvc->cfg->termination |= TERM_SE_HI;
5746 }
5747 break;
5748 }
5749 }
5750
5751 /*
5752 * Clear any set TERM_SE bits.
5753 */
5754 scsi_cfg1 &= ~TERM_SE;
5755
5756 /*
5757 * Invert the TERM_SE bits and then set 'scsi_cfg1'.
5758 */
5759 scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE);
5760
5761 /*
5762 * Clear Big Endian and Terminator Polarity bits and set possibly
5763 * modified termination control bits in the Microcode SCSI_CFG1
5764 * Register Value.
5765 *
5766 * Big Endian bit is not used even on big endian machines.
5767 */
5768 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL);
5769
5770 /*
5771 * Set SCSI_CFG1 Microcode Default Value
5772 *
5773 * Set possibly modified termination control bits in the Microcode
5774 * SCSI_CFG1 Register Value.
5775 *
5776 * The microcode will set the SCSI_CFG1 register using this value
5777 * after it is started below.
5778 */
5779 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
5780
5781 /*
5782 * Set MEM_CFG Microcode Default Value
5783 *
5784 * The microcode will set the MEM_CFG register using this value
5785 * after it is started below.
5786 *
5787 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
5788 * are defined.
5789 *
5790 * ASC-38C1600 has 32KB internal memory.
5791 *
5792 * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come
5793 * out a special 16K Adv Library and Microcode version. After the issue
5794 * resolved, we should turn back to the 32K support. Both a_condor.h and
5795 * mcode.sas files also need to be updated.
5796 *
5797 * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5798 * BIOS_EN | RAM_SZ_32KB);
5799 */
5800 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5801 BIOS_EN | RAM_SZ_16KB);
5802
5803 /*
5804 * Set SEL_MASK Microcode Default Value
5805 *
5806 * The microcode will set the SEL_MASK register using this value
5807 * after it is started below.
5808 */
5809 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
5810 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
5811
5812 AdvBuildCarrierFreelist(asc_dvc);
5813
5814 /*
5815 * Set-up the Host->RISC Initiator Command Queue (ICQ).
5816 */
5817 asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc);
5818 if (!asc_dvc->icq_sp) {
5819 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5820 return ADV_ERROR;
5821 }
5822
5823 /*
5824 * Set RISC ICQ physical address start value. Initialize the
5825 * COMMA register to the same value otherwise the RISC will
5826 * prematurely detect a command is available.
5827 */
5828 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
5829 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
5830 le32_to_cpu(asc_dvc->icq_sp->carr_pa));
5831
5832 /*
5833 * Set-up the RISC->Host Initiator Response Queue (IRQ).
5834 */
5835 asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc);
5836 if (!asc_dvc->irq_sp) {
5837 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5838 return ADV_ERROR;
5839 }
5840
5841 /*
5842 * Set RISC IRQ physical address start value.
5843 */
5844 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
5845 asc_dvc->carr_pending_cnt = 0;
5846
5847 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
5848 (ADV_INTR_ENABLE_HOST_INTR |
5849 ADV_INTR_ENABLE_GLOBAL_INTR));
5850 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
5851 AdvWriteWordRegister(iop_base, IOPW_PC, word);
5852
5853 /* finally, finally, gentlemen, start your engine */
5854 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
5855
5856 /*
5857 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
5858 * Resets should be performed. The RISC has to be running
5859 * to issue a SCSI Bus Reset.
5860 */
5861 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
5862 /*
5863 * If the BIOS Signature is present in memory, restore the
5864 * per TID microcode operating variables.
5865 */
5866 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
5867 0x55AA) {
5868 /*
5869 * Restore per TID negotiated values.
5870 */
5871 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5872 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5873 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5874 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
5875 tagqng_able);
5876 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
5877 AdvWriteByteLram(iop_base,
5878 ASC_MC_NUMBER_OF_MAX_CMD + tid,
5879 max_cmd[tid]);
5880 }
5881 } else {
5882 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
5883 warn_code = ASC_WARN_BUSRESET_ERROR;
5884 }
5885 }
5886 }
5887
5888 return warn_code;
5889 }
5890
5891 /*
5892 * Reset chip and SCSI Bus.
5893 *
5894 * Return Value:
5895 * ADV_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful.
5896 * ADV_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure.
5897 */
5898 static int AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc)
5899 {
5900 int status;
5901 ushort wdtr_able, sdtr_able, tagqng_able;
5902 ushort ppr_able = 0;
5903 uchar tid, max_cmd[ADV_MAX_TID + 1];
5904 AdvPortAddr iop_base;
5905 ushort bios_sig;
5906
5907 iop_base = asc_dvc->iop_base;
5908
5909 /*
5910 * Save current per TID negotiated values.
5911 */
5912 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5913 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5914 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
5915 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5916 }
5917 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5918 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5919 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5920 max_cmd[tid]);
5921 }
5922
5923 /*
5924 * Force the AdvInitAsc3550/38C0800Driver() function to
5925 * perform a SCSI Bus Reset by clearing the BIOS signature word.
5926 * The initialization functions assumes a SCSI Bus Reset is not
5927 * needed if the BIOS signature word is present.
5928 */
5929 AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
5930 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0);
5931
5932 /*
5933 * Stop chip and reset it.
5934 */
5935 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP);
5936 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET);
5937 mdelay(100);
5938 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
5939 ADV_CTRL_REG_CMD_WR_IO_REG);
5940
5941 /*
5942 * Reset Adv Library error code, if any, and try
5943 * re-initializing the chip.
5944 */
5945 asc_dvc->err_code = 0;
5946 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
5947 status = AdvInitAsc38C1600Driver(asc_dvc);
5948 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
5949 status = AdvInitAsc38C0800Driver(asc_dvc);
5950 } else {
5951 status = AdvInitAsc3550Driver(asc_dvc);
5952 }
5953
5954 /* Translate initialization return value to status value. */
5955 if (status == 0) {
5956 status = ADV_TRUE;
5957 } else {
5958 status = ADV_FALSE;
5959 }
5960
5961 /*
5962 * Restore the BIOS signature word.
5963 */
5964 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
5965
5966 /*
5967 * Restore per TID negotiated values.
5968 */
5969 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5970 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5971 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
5972 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5973 }
5974 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5975 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5976 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5977 max_cmd[tid]);
5978 }
5979
5980 return status;
5981 }
5982
5983 /*
5984 * adv_async_callback() - Adv Library asynchronous event callback function.
5985 */
5986 static void adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code)
5987 {
5988 switch (code) {
5989 case ADV_ASYNC_SCSI_BUS_RESET_DET:
5990 /*
5991 * The firmware detected a SCSI Bus reset.
5992 */
5993 ASC_DBG(0, "ADV_ASYNC_SCSI_BUS_RESET_DET\n");
5994 break;
5995
5996 case ADV_ASYNC_RDMA_FAILURE:
5997 /*
5998 * Handle RDMA failure by resetting the SCSI Bus and
5999 * possibly the chip if it is unresponsive. Log the error
6000 * with a unique code.
6001 */
6002 ASC_DBG(0, "ADV_ASYNC_RDMA_FAILURE\n");
6003 AdvResetChipAndSB(adv_dvc_varp);
6004 break;
6005
6006 case ADV_HOST_SCSI_BUS_RESET:
6007 /*
6008 * Host generated SCSI bus reset occurred.
6009 */
6010 ASC_DBG(0, "ADV_HOST_SCSI_BUS_RESET\n");
6011 break;
6012
6013 default:
6014 ASC_DBG(0, "unknown code 0x%x\n", code);
6015 break;
6016 }
6017 }
6018
6019 /*
6020 * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR().
6021 *
6022 * Callback function for the Wide SCSI Adv Library.
6023 */
6024 static void adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp)
6025 {
6026 struct asc_board *boardp = adv_dvc_varp->drv_ptr;
6027 u32 srb_tag;
6028 adv_req_t *reqp;
6029 adv_sgblk_t *sgblkp;
6030 struct scsi_cmnd *scp;
6031 u32 resid_cnt;
6032 dma_addr_t sense_addr;
6033
6034 ASC_DBG(1, "adv_dvc_varp 0x%p, scsiqp 0x%p\n",
6035 adv_dvc_varp, scsiqp);
6036 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
6037
6038 /*
6039 * Get the adv_req_t structure for the command that has been
6040 * completed. The adv_req_t structure actually contains the
6041 * completed ADV_SCSI_REQ_Q structure.
6042 */
6043 srb_tag = le32_to_cpu(scsiqp->srb_tag);
6044 scp = scsi_host_find_tag(boardp->shost, scsiqp->srb_tag);
6045
6046 ASC_DBG(1, "scp 0x%p\n", scp);
6047 if (scp == NULL) {
6048 ASC_PRINT
6049 ("adv_isr_callback: scp is NULL; adv_req_t dropped.\n");
6050 return;
6051 }
6052 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
6053
6054 reqp = (adv_req_t *)scp->host_scribble;
6055 ASC_DBG(1, "reqp 0x%lx\n", (ulong)reqp);
6056 if (reqp == NULL) {
6057 ASC_PRINT("adv_isr_callback: reqp is NULL\n");
6058 return;
6059 }
6060 /*
6061 * Remove backreferences to avoid duplicate
6062 * command completions.
6063 */
6064 scp->host_scribble = NULL;
6065 reqp->cmndp = NULL;
6066
6067 ASC_STATS(boardp->shost, callback);
6068 ASC_DBG(1, "shost 0x%p\n", boardp->shost);
6069
6070 sense_addr = le32_to_cpu(scsiqp->sense_addr);
6071 dma_unmap_single(boardp->dev, sense_addr,
6072 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
6073
6074 /*
6075 * 'done_status' contains the command's ending status.
6076 */
6077 switch (scsiqp->done_status) {
6078 case QD_NO_ERROR:
6079 ASC_DBG(2, "QD_NO_ERROR\n");
6080 scp->result = 0;
6081
6082 /*
6083 * Check for an underrun condition.
6084 *
6085 * If there was no error and an underrun condition, then
6086 * then return the number of underrun bytes.
6087 */
6088 resid_cnt = le32_to_cpu(scsiqp->data_cnt);
6089 if (scsi_bufflen(scp) != 0 && resid_cnt != 0 &&
6090 resid_cnt <= scsi_bufflen(scp)) {
6091 ASC_DBG(1, "underrun condition %lu bytes\n",
6092 (ulong)resid_cnt);
6093 scsi_set_resid(scp, resid_cnt);
6094 }
6095 break;
6096
6097 case QD_WITH_ERROR:
6098 ASC_DBG(2, "QD_WITH_ERROR\n");
6099 switch (scsiqp->host_status) {
6100 case QHSTA_NO_ERROR:
6101 if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) {
6102 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
6103 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
6104 SCSI_SENSE_BUFFERSIZE);
6105 /*
6106 * Note: The 'status_byte()' macro used by
6107 * target drivers defined in scsi.h shifts the
6108 * status byte returned by host drivers right
6109 * by 1 bit. This is why target drivers also
6110 * use right shifted status byte definitions.
6111 * For instance target drivers use
6112 * CHECK_CONDITION, defined to 0x1, instead of
6113 * the SCSI defined check condition value of
6114 * 0x2. Host drivers are supposed to return
6115 * the status byte as it is defined by SCSI.
6116 */
6117 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
6118 STATUS_BYTE(scsiqp->scsi_status);
6119 } else {
6120 scp->result = STATUS_BYTE(scsiqp->scsi_status);
6121 }
6122 break;
6123
6124 default:
6125 /* Some other QHSTA error occurred. */
6126 ASC_DBG(1, "host_status 0x%x\n", scsiqp->host_status);
6127 scp->result = HOST_BYTE(DID_BAD_TARGET);
6128 break;
6129 }
6130 break;
6131
6132 case QD_ABORTED_BY_HOST:
6133 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
6134 scp->result =
6135 HOST_BYTE(DID_ABORT) | STATUS_BYTE(scsiqp->scsi_status);
6136 break;
6137
6138 default:
6139 ASC_DBG(1, "done_status 0x%x\n", scsiqp->done_status);
6140 scp->result =
6141 HOST_BYTE(DID_ERROR) | STATUS_BYTE(scsiqp->scsi_status);
6142 break;
6143 }
6144
6145 /*
6146 * If the 'init_tidmask' bit isn't already set for the target and the
6147 * current request finished normally, then set the bit for the target
6148 * to indicate that a device is present.
6149 */
6150 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
6151 scsiqp->done_status == QD_NO_ERROR &&
6152 scsiqp->host_status == QHSTA_NO_ERROR) {
6153 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
6154 }
6155
6156 asc_scsi_done(scp);
6157
6158 /*
6159 * Free all 'adv_sgblk_t' structures allocated for the request.
6160 */
6161 while ((sgblkp = reqp->sgblkp) != NULL) {
6162 /* Remove 'sgblkp' from the request list. */
6163 reqp->sgblkp = sgblkp->next_sgblkp;
6164
6165 dma_pool_free(boardp->adv_sgblk_pool, sgblkp,
6166 sgblkp->sg_addr);
6167 }
6168
6169 ASC_DBG(1, "done\n");
6170 }
6171
6172 /*
6173 * Adv Library Interrupt Service Routine
6174 *
6175 * This function is called by a driver's interrupt service routine.
6176 * The function disables and re-enables interrupts.
6177 *
6178 * When a microcode idle command is completed, the ADV_DVC_VAR
6179 * 'idle_cmd_done' field is set to ADV_TRUE.
6180 *
6181 * Note: AdvISR() can be called when interrupts are disabled or even
6182 * when there is no hardware interrupt condition present. It will
6183 * always check for completed idle commands and microcode requests.
6184 * This is an important feature that shouldn't be changed because it
6185 * allows commands to be completed from polling mode loops.
6186 *
6187 * Return:
6188 * ADV_TRUE(1) - interrupt was pending
6189 * ADV_FALSE(0) - no interrupt was pending
6190 */
6191 static int AdvISR(ADV_DVC_VAR *asc_dvc)
6192 {
6193 AdvPortAddr iop_base;
6194 uchar int_stat;
6195 ushort target_bit;
6196 ADV_CARR_T *free_carrp;
6197 __le32 irq_next_vpa;
6198 ADV_SCSI_REQ_Q *scsiq;
6199 adv_req_t *reqp;
6200
6201 iop_base = asc_dvc->iop_base;
6202
6203 /* Reading the register clears the interrupt. */
6204 int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG);
6205
6206 if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB |
6207 ADV_INTR_STATUS_INTRC)) == 0) {
6208 return ADV_FALSE;
6209 }
6210
6211 /*
6212 * Notify the driver of an asynchronous microcode condition by
6213 * calling the adv_async_callback function. The function
6214 * is passed the microcode ASC_MC_INTRB_CODE byte value.
6215 */
6216 if (int_stat & ADV_INTR_STATUS_INTRB) {
6217 uchar intrb_code;
6218
6219 AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code);
6220
6221 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
6222 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
6223 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE &&
6224 asc_dvc->carr_pending_cnt != 0) {
6225 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
6226 ADV_TICKLE_A);
6227 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
6228 AdvWriteByteRegister(iop_base,
6229 IOPB_TICKLE,
6230 ADV_TICKLE_NOP);
6231 }
6232 }
6233 }
6234
6235 adv_async_callback(asc_dvc, intrb_code);
6236 }
6237
6238 /*
6239 * Check if the IRQ stopper carrier contains a completed request.
6240 */
6241 while (((irq_next_vpa =
6242 le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ASC_RQ_DONE) != 0) {
6243 /*
6244 * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure.
6245 * The RISC will have set 'areq_vpa' to a virtual address.
6246 *
6247 * The firmware will have copied the ASC_SCSI_REQ_Q.scsiq_ptr
6248 * field to the carrier ADV_CARR_T.areq_vpa field. The conversion
6249 * below complements the conversion of ASC_SCSI_REQ_Q.scsiq_ptr'
6250 * in AdvExeScsiQueue().
6251 */
6252 u32 pa_offset = le32_to_cpu(asc_dvc->irq_sp->areq_vpa);
6253 ASC_DBG(1, "irq_sp %p areq_vpa %u\n",
6254 asc_dvc->irq_sp, pa_offset);
6255 reqp = adv_get_reqp(asc_dvc, pa_offset);
6256 scsiq = &reqp->scsi_req_q;
6257
6258 /*
6259 * Request finished with good status and the queue was not
6260 * DMAed to host memory by the firmware. Set all status fields
6261 * to indicate good status.
6262 */
6263 if ((irq_next_vpa & ASC_RQ_GOOD) != 0) {
6264 scsiq->done_status = QD_NO_ERROR;
6265 scsiq->host_status = scsiq->scsi_status = 0;
6266 scsiq->data_cnt = 0L;
6267 }
6268
6269 /*
6270 * Advance the stopper pointer to the next carrier
6271 * ignoring the lower four bits. Free the previous
6272 * stopper carrier.
6273 */
6274 free_carrp = asc_dvc->irq_sp;
6275 asc_dvc->irq_sp = adv_get_carrier(asc_dvc,
6276 ASC_GET_CARRP(irq_next_vpa));
6277
6278 free_carrp->next_vpa = asc_dvc->carr_freelist->carr_va;
6279 asc_dvc->carr_freelist = free_carrp;
6280 asc_dvc->carr_pending_cnt--;
6281
6282 target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id);
6283
6284 /*
6285 * Clear request microcode control flag.
6286 */
6287 scsiq->cntl = 0;
6288
6289 /*
6290 * Notify the driver of the completed request by passing
6291 * the ADV_SCSI_REQ_Q pointer to its callback function.
6292 */
6293 scsiq->a_flag |= ADV_SCSIQ_DONE;
6294 adv_isr_callback(asc_dvc, scsiq);
6295 /*
6296 * Note: After the driver callback function is called, 'scsiq'
6297 * can no longer be referenced.
6298 *
6299 * Fall through and continue processing other completed
6300 * requests...
6301 */
6302 }
6303 return ADV_TRUE;
6304 }
6305
6306 static int AscSetLibErrorCode(ASC_DVC_VAR *asc_dvc, ushort err_code)
6307 {
6308 if (asc_dvc->err_code == 0) {
6309 asc_dvc->err_code = err_code;
6310 AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W,
6311 err_code);
6312 }
6313 return err_code;
6314 }
6315
6316 static void AscAckInterrupt(PortAddr iop_base)
6317 {
6318 uchar host_flag;
6319 uchar risc_flag;
6320 ushort loop;
6321
6322 loop = 0;
6323 do {
6324 risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B);
6325 if (loop++ > 0x7FFF) {
6326 break;
6327 }
6328 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0);
6329 host_flag =
6330 AscReadLramByte(iop_base,
6331 ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT);
6332 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
6333 (uchar)(host_flag | ASC_HOST_FLAG_ACK_INT));
6334 AscSetChipStatus(iop_base, CIW_INT_ACK);
6335 loop = 0;
6336 while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) {
6337 AscSetChipStatus(iop_base, CIW_INT_ACK);
6338 if (loop++ > 3) {
6339 break;
6340 }
6341 }
6342 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
6343 }
6344
6345 static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time)
6346 {
6347 const uchar *period_table;
6348 int max_index;
6349 int min_index;
6350 int i;
6351
6352 period_table = asc_dvc->sdtr_period_tbl;
6353 max_index = (int)asc_dvc->max_sdtr_index;
6354 min_index = (int)asc_dvc->min_sdtr_index;
6355 if ((syn_time <= period_table[max_index])) {
6356 for (i = min_index; i < (max_index - 1); i++) {
6357 if (syn_time <= period_table[i]) {
6358 return (uchar)i;
6359 }
6360 }
6361 return (uchar)max_index;
6362 } else {
6363 return (uchar)(max_index + 1);
6364 }
6365 }
6366
6367 static uchar
6368 AscMsgOutSDTR(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar sdtr_offset)
6369 {
6370 EXT_MSG sdtr_buf;
6371 uchar sdtr_period_index;
6372 PortAddr iop_base;
6373
6374 iop_base = asc_dvc->iop_base;
6375 sdtr_buf.msg_type = EXTENDED_MESSAGE;
6376 sdtr_buf.msg_len = MS_SDTR_LEN;
6377 sdtr_buf.msg_req = EXTENDED_SDTR;
6378 sdtr_buf.xfer_period = sdtr_period;
6379 sdtr_offset &= ASC_SYN_MAX_OFFSET;
6380 sdtr_buf.req_ack_offset = sdtr_offset;
6381 sdtr_period_index = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
6382 if (sdtr_period_index <= asc_dvc->max_sdtr_index) {
6383 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
6384 (uchar *)&sdtr_buf,
6385 sizeof(EXT_MSG) >> 1);
6386 return ((sdtr_period_index << 4) | sdtr_offset);
6387 } else {
6388 sdtr_buf.req_ack_offset = 0;
6389 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
6390 (uchar *)&sdtr_buf,
6391 sizeof(EXT_MSG) >> 1);
6392 return 0;
6393 }
6394 }
6395
6396 static uchar
6397 AscCalSDTRData(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar syn_offset)
6398 {
6399 uchar byte;
6400 uchar sdtr_period_ix;
6401
6402 sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
6403 if (sdtr_period_ix > asc_dvc->max_sdtr_index)
6404 return 0xFF;
6405 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
6406 return byte;
6407 }
6408
6409 static bool AscSetChipSynRegAtID(PortAddr iop_base, uchar id, uchar sdtr_data)
6410 {
6411 ASC_SCSI_BIT_ID_TYPE org_id;
6412 int i;
6413 bool sta = true;
6414
6415 AscSetBank(iop_base, 1);
6416 org_id = AscReadChipDvcID(iop_base);
6417 for (i = 0; i <= ASC_MAX_TID; i++) {
6418 if (org_id == (0x01 << i))
6419 break;
6420 }
6421 org_id = (ASC_SCSI_BIT_ID_TYPE) i;
6422 AscWriteChipDvcID(iop_base, id);
6423 if (AscReadChipDvcID(iop_base) == (0x01 << id)) {
6424 AscSetBank(iop_base, 0);
6425 AscSetChipSyn(iop_base, sdtr_data);
6426 if (AscGetChipSyn(iop_base) != sdtr_data) {
6427 sta = false;
6428 }
6429 } else {
6430 sta = false;
6431 }
6432 AscSetBank(iop_base, 1);
6433 AscWriteChipDvcID(iop_base, org_id);
6434 AscSetBank(iop_base, 0);
6435 return (sta);
6436 }
6437
6438 static void AscSetChipSDTR(PortAddr iop_base, uchar sdtr_data, uchar tid_no)
6439 {
6440 AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
6441 AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data);
6442 }
6443
6444 static int AscIsrChipHalted(ASC_DVC_VAR *asc_dvc)
6445 {
6446 EXT_MSG ext_msg;
6447 EXT_MSG out_msg;
6448 ushort halt_q_addr;
6449 bool sdtr_accept;
6450 ushort int_halt_code;
6451 ASC_SCSI_BIT_ID_TYPE scsi_busy;
6452 ASC_SCSI_BIT_ID_TYPE target_id;
6453 PortAddr iop_base;
6454 uchar tag_code;
6455 uchar q_status;
6456 uchar halt_qp;
6457 uchar sdtr_data;
6458 uchar target_ix;
6459 uchar q_cntl, tid_no;
6460 uchar cur_dvc_qng;
6461 uchar asyn_sdtr;
6462 uchar scsi_status;
6463 struct asc_board *boardp;
6464
6465 BUG_ON(!asc_dvc->drv_ptr);
6466 boardp = asc_dvc->drv_ptr;
6467
6468 iop_base = asc_dvc->iop_base;
6469 int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W);
6470
6471 halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B);
6472 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp);
6473 target_ix = AscReadLramByte(iop_base,
6474 (ushort)(halt_q_addr +
6475 (ushort)ASC_SCSIQ_B_TARGET_IX));
6476 q_cntl = AscReadLramByte(iop_base,
6477 (ushort)(halt_q_addr + (ushort)ASC_SCSIQ_B_CNTL));
6478 tid_no = ASC_TIX_TO_TID(target_ix);
6479 target_id = (uchar)ASC_TID_TO_TARGET_ID(tid_no);
6480 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6481 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB;
6482 } else {
6483 asyn_sdtr = 0;
6484 }
6485 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) {
6486 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6487 AscSetChipSDTR(iop_base, 0, tid_no);
6488 boardp->sdtr_data[tid_no] = 0;
6489 }
6490 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6491 return (0);
6492 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) {
6493 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6494 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6495 boardp->sdtr_data[tid_no] = asyn_sdtr;
6496 }
6497 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6498 return (0);
6499 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) {
6500 AscMemWordCopyPtrFromLram(iop_base,
6501 ASCV_MSGIN_BEG,
6502 (uchar *)&ext_msg,
6503 sizeof(EXT_MSG) >> 1);
6504
6505 if (ext_msg.msg_type == EXTENDED_MESSAGE &&
6506 ext_msg.msg_req == EXTENDED_SDTR &&
6507 ext_msg.msg_len == MS_SDTR_LEN) {
6508 sdtr_accept = true;
6509 if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) {
6510
6511 sdtr_accept = false;
6512 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
6513 }
6514 if ((ext_msg.xfer_period <
6515 asc_dvc->sdtr_period_tbl[asc_dvc->min_sdtr_index])
6516 || (ext_msg.xfer_period >
6517 asc_dvc->sdtr_period_tbl[asc_dvc->
6518 max_sdtr_index])) {
6519 sdtr_accept = false;
6520 ext_msg.xfer_period =
6521 asc_dvc->sdtr_period_tbl[asc_dvc->
6522 min_sdtr_index];
6523 }
6524 if (sdtr_accept) {
6525 sdtr_data =
6526 AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
6527 ext_msg.req_ack_offset);
6528 if ((sdtr_data == 0xFF)) {
6529
6530 q_cntl |= QC_MSG_OUT;
6531 asc_dvc->init_sdtr &= ~target_id;
6532 asc_dvc->sdtr_done &= ~target_id;
6533 AscSetChipSDTR(iop_base, asyn_sdtr,
6534 tid_no);
6535 boardp->sdtr_data[tid_no] = asyn_sdtr;
6536 }
6537 }
6538 if (ext_msg.req_ack_offset == 0) {
6539
6540 q_cntl &= ~QC_MSG_OUT;
6541 asc_dvc->init_sdtr &= ~target_id;
6542 asc_dvc->sdtr_done &= ~target_id;
6543 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6544 } else {
6545 if (sdtr_accept && (q_cntl & QC_MSG_OUT)) {
6546 q_cntl &= ~QC_MSG_OUT;
6547 asc_dvc->sdtr_done |= target_id;
6548 asc_dvc->init_sdtr |= target_id;
6549 asc_dvc->pci_fix_asyn_xfer &=
6550 ~target_id;
6551 sdtr_data =
6552 AscCalSDTRData(asc_dvc,
6553 ext_msg.xfer_period,
6554 ext_msg.
6555 req_ack_offset);
6556 AscSetChipSDTR(iop_base, sdtr_data,
6557 tid_no);
6558 boardp->sdtr_data[tid_no] = sdtr_data;
6559 } else {
6560 q_cntl |= QC_MSG_OUT;
6561 AscMsgOutSDTR(asc_dvc,
6562 ext_msg.xfer_period,
6563 ext_msg.req_ack_offset);
6564 asc_dvc->pci_fix_asyn_xfer &=
6565 ~target_id;
6566 sdtr_data =
6567 AscCalSDTRData(asc_dvc,
6568 ext_msg.xfer_period,
6569 ext_msg.
6570 req_ack_offset);
6571 AscSetChipSDTR(iop_base, sdtr_data,
6572 tid_no);
6573 boardp->sdtr_data[tid_no] = sdtr_data;
6574 asc_dvc->sdtr_done |= target_id;
6575 asc_dvc->init_sdtr |= target_id;
6576 }
6577 }
6578
6579 AscWriteLramByte(iop_base,
6580 (ushort)(halt_q_addr +
6581 (ushort)ASC_SCSIQ_B_CNTL),
6582 q_cntl);
6583 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6584 return (0);
6585 } else if (ext_msg.msg_type == EXTENDED_MESSAGE &&
6586 ext_msg.msg_req == EXTENDED_WDTR &&
6587 ext_msg.msg_len == MS_WDTR_LEN) {
6588
6589 ext_msg.wdtr_width = 0;
6590 AscMemWordCopyPtrToLram(iop_base,
6591 ASCV_MSGOUT_BEG,
6592 (uchar *)&ext_msg,
6593 sizeof(EXT_MSG) >> 1);
6594 q_cntl |= QC_MSG_OUT;
6595 AscWriteLramByte(iop_base,
6596 (ushort)(halt_q_addr +
6597 (ushort)ASC_SCSIQ_B_CNTL),
6598 q_cntl);
6599 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6600 return (0);
6601 } else {
6602
6603 ext_msg.msg_type = MESSAGE_REJECT;
6604 AscMemWordCopyPtrToLram(iop_base,
6605 ASCV_MSGOUT_BEG,
6606 (uchar *)&ext_msg,
6607 sizeof(EXT_MSG) >> 1);
6608 q_cntl |= QC_MSG_OUT;
6609 AscWriteLramByte(iop_base,
6610 (ushort)(halt_q_addr +
6611 (ushort)ASC_SCSIQ_B_CNTL),
6612 q_cntl);
6613 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6614 return (0);
6615 }
6616 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) {
6617
6618 q_cntl |= QC_REQ_SENSE;
6619
6620 if ((asc_dvc->init_sdtr & target_id) != 0) {
6621
6622 asc_dvc->sdtr_done &= ~target_id;
6623
6624 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
6625 q_cntl |= QC_MSG_OUT;
6626 AscMsgOutSDTR(asc_dvc,
6627 asc_dvc->
6628 sdtr_period_tbl[(sdtr_data >> 4) &
6629 (uchar)(asc_dvc->
6630 max_sdtr_index -
6631 1)],
6632 (uchar)(sdtr_data & (uchar)
6633 ASC_SYN_MAX_OFFSET));
6634 }
6635
6636 AscWriteLramByte(iop_base,
6637 (ushort)(halt_q_addr +
6638 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
6639
6640 tag_code = AscReadLramByte(iop_base,
6641 (ushort)(halt_q_addr + (ushort)
6642 ASC_SCSIQ_B_TAG_CODE));
6643 tag_code &= 0xDC;
6644 if ((asc_dvc->pci_fix_asyn_xfer & target_id)
6645 && !(asc_dvc->pci_fix_asyn_xfer_always & target_id)
6646 ) {
6647
6648 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT
6649 | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX);
6650
6651 }
6652 AscWriteLramByte(iop_base,
6653 (ushort)(halt_q_addr +
6654 (ushort)ASC_SCSIQ_B_TAG_CODE),
6655 tag_code);
6656
6657 q_status = AscReadLramByte(iop_base,
6658 (ushort)(halt_q_addr + (ushort)
6659 ASC_SCSIQ_B_STATUS));
6660 q_status |= (QS_READY | QS_BUSY);
6661 AscWriteLramByte(iop_base,
6662 (ushort)(halt_q_addr +
6663 (ushort)ASC_SCSIQ_B_STATUS),
6664 q_status);
6665
6666 scsi_busy = AscReadLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B);
6667 scsi_busy &= ~target_id;
6668 AscWriteLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B, scsi_busy);
6669
6670 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6671 return (0);
6672 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) {
6673
6674 AscMemWordCopyPtrFromLram(iop_base,
6675 ASCV_MSGOUT_BEG,
6676 (uchar *)&out_msg,
6677 sizeof(EXT_MSG) >> 1);
6678
6679 if ((out_msg.msg_type == EXTENDED_MESSAGE) &&
6680 (out_msg.msg_len == MS_SDTR_LEN) &&
6681 (out_msg.msg_req == EXTENDED_SDTR)) {
6682
6683 asc_dvc->init_sdtr &= ~target_id;
6684 asc_dvc->sdtr_done &= ~target_id;
6685 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6686 boardp->sdtr_data[tid_no] = asyn_sdtr;
6687 }
6688 q_cntl &= ~QC_MSG_OUT;
6689 AscWriteLramByte(iop_base,
6690 (ushort)(halt_q_addr +
6691 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
6692 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6693 return (0);
6694 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) {
6695
6696 scsi_status = AscReadLramByte(iop_base,
6697 (ushort)((ushort)halt_q_addr +
6698 (ushort)
6699 ASC_SCSIQ_SCSI_STATUS));
6700 cur_dvc_qng =
6701 AscReadLramByte(iop_base,
6702 (ushort)((ushort)ASC_QADR_BEG +
6703 (ushort)target_ix));
6704 if ((cur_dvc_qng > 0) && (asc_dvc->cur_dvc_qng[tid_no] > 0)) {
6705
6706 scsi_busy = AscReadLramByte(iop_base,
6707 (ushort)ASCV_SCSIBUSY_B);
6708 scsi_busy |= target_id;
6709 AscWriteLramByte(iop_base,
6710 (ushort)ASCV_SCSIBUSY_B, scsi_busy);
6711 asc_dvc->queue_full_or_busy |= target_id;
6712
6713 if (scsi_status == SAM_STAT_TASK_SET_FULL) {
6714 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) {
6715 cur_dvc_qng -= 1;
6716 asc_dvc->max_dvc_qng[tid_no] =
6717 cur_dvc_qng;
6718
6719 AscWriteLramByte(iop_base,
6720 (ushort)((ushort)
6721 ASCV_MAX_DVC_QNG_BEG
6722 + (ushort)
6723 tid_no),
6724 cur_dvc_qng);
6725
6726 /*
6727 * Set the device queue depth to the
6728 * number of active requests when the
6729 * QUEUE FULL condition was encountered.
6730 */
6731 boardp->queue_full |= target_id;
6732 boardp->queue_full_cnt[tid_no] =
6733 cur_dvc_qng;
6734 }
6735 }
6736 }
6737 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6738 return (0);
6739 }
6740 #if CC_VERY_LONG_SG_LIST
6741 else if (int_halt_code == ASC_HALT_HOST_COPY_SG_LIST_TO_RISC) {
6742 uchar q_no;
6743 ushort q_addr;
6744 uchar sg_wk_q_no;
6745 uchar first_sg_wk_q_no;
6746 ASC_SCSI_Q *scsiq; /* Ptr to driver request. */
6747 ASC_SG_HEAD *sg_head; /* Ptr to driver SG request. */
6748 ASC_SG_LIST_Q scsi_sg_q; /* Structure written to queue. */
6749 ushort sg_list_dwords;
6750 ushort sg_entry_cnt;
6751 uchar next_qp;
6752 int i;
6753
6754 q_no = AscReadLramByte(iop_base, (ushort)ASCV_REQ_SG_LIST_QP);
6755 if (q_no == ASC_QLINK_END)
6756 return 0;
6757
6758 q_addr = ASC_QNO_TO_QADDR(q_no);
6759
6760 /*
6761 * Convert the request's SRB pointer to a host ASC_SCSI_REQ
6762 * structure pointer using a macro provided by the driver.
6763 * The ASC_SCSI_REQ pointer provides a pointer to the
6764 * host ASC_SG_HEAD structure.
6765 */
6766 /* Read request's SRB pointer. */
6767 scsiq = (ASC_SCSI_Q *)
6768 ASC_SRB2SCSIQ(ASC_U32_TO_VADDR(AscReadLramDWord(iop_base,
6769 (ushort)
6770 (q_addr +
6771 ASC_SCSIQ_D_SRBPTR))));
6772
6773 /*
6774 * Get request's first and working SG queue.
6775 */
6776 sg_wk_q_no = AscReadLramByte(iop_base,
6777 (ushort)(q_addr +
6778 ASC_SCSIQ_B_SG_WK_QP));
6779
6780 first_sg_wk_q_no = AscReadLramByte(iop_base,
6781 (ushort)(q_addr +
6782 ASC_SCSIQ_B_FIRST_SG_WK_QP));
6783
6784 /*
6785 * Reset request's working SG queue back to the
6786 * first SG queue.
6787 */
6788 AscWriteLramByte(iop_base,
6789 (ushort)(q_addr +
6790 (ushort)ASC_SCSIQ_B_SG_WK_QP),
6791 first_sg_wk_q_no);
6792
6793 sg_head = scsiq->sg_head;
6794
6795 /*
6796 * Set sg_entry_cnt to the number of SG elements
6797 * that will be completed on this interrupt.
6798 *
6799 * Note: The allocated SG queues contain ASC_MAX_SG_LIST - 1
6800 * SG elements. The data_cnt and data_addr fields which
6801 * add 1 to the SG element capacity are not used when
6802 * restarting SG handling after a halt.
6803 */
6804 if (scsiq->remain_sg_entry_cnt > (ASC_MAX_SG_LIST - 1)) {
6805 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
6806
6807 /*
6808 * Keep track of remaining number of SG elements that
6809 * will need to be handled on the next interrupt.
6810 */
6811 scsiq->remain_sg_entry_cnt -= (ASC_MAX_SG_LIST - 1);
6812 } else {
6813 sg_entry_cnt = scsiq->remain_sg_entry_cnt;
6814 scsiq->remain_sg_entry_cnt = 0;
6815 }
6816
6817 /*
6818 * Copy SG elements into the list of allocated SG queues.
6819 *
6820 * Last index completed is saved in scsiq->next_sg_index.
6821 */
6822 next_qp = first_sg_wk_q_no;
6823 q_addr = ASC_QNO_TO_QADDR(next_qp);
6824 scsi_sg_q.sg_head_qp = q_no;
6825 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
6826 for (i = 0; i < sg_head->queue_cnt; i++) {
6827 scsi_sg_q.seq_no = i + 1;
6828 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
6829 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
6830 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
6831 /*
6832 * After very first SG queue RISC FW uses next
6833 * SG queue first element then checks sg_list_cnt
6834 * against zero and then decrements, so set
6835 * sg_list_cnt 1 less than number of SG elements
6836 * in each SG queue.
6837 */
6838 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1;
6839 scsi_sg_q.sg_cur_list_cnt =
6840 ASC_SG_LIST_PER_Q - 1;
6841 } else {
6842 /*
6843 * This is the last SG queue in the list of
6844 * allocated SG queues. If there are more
6845 * SG elements than will fit in the allocated
6846 * queues, then set the QCSG_SG_XFER_MORE flag.
6847 */
6848 if (scsiq->remain_sg_entry_cnt != 0) {
6849 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
6850 } else {
6851 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
6852 }
6853 /* equals sg_entry_cnt * 2 */
6854 sg_list_dwords = sg_entry_cnt << 1;
6855 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1;
6856 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1;
6857 sg_entry_cnt = 0;
6858 }
6859
6860 scsi_sg_q.q_no = next_qp;
6861 AscMemWordCopyPtrToLram(iop_base,
6862 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
6863 (uchar *)&scsi_sg_q,
6864 sizeof(ASC_SG_LIST_Q) >> 1);
6865
6866 AscMemDWordCopyPtrToLram(iop_base,
6867 q_addr + ASC_SGQ_LIST_BEG,
6868 (uchar *)&sg_head->
6869 sg_list[scsiq->next_sg_index],
6870 sg_list_dwords);
6871
6872 scsiq->next_sg_index += ASC_SG_LIST_PER_Q;
6873
6874 /*
6875 * If the just completed SG queue contained the
6876 * last SG element, then no more SG queues need
6877 * to be written.
6878 */
6879 if (scsi_sg_q.cntl & QCSG_SG_XFER_END) {
6880 break;
6881 }
6882
6883 next_qp = AscReadLramByte(iop_base,
6884 (ushort)(q_addr +
6885 ASC_SCSIQ_B_FWD));
6886 q_addr = ASC_QNO_TO_QADDR(next_qp);
6887 }
6888
6889 /*
6890 * Clear the halt condition so the RISC will be restarted
6891 * after the return.
6892 */
6893 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6894 return (0);
6895 }
6896 #endif /* CC_VERY_LONG_SG_LIST */
6897 return (0);
6898 }
6899
6900 /*
6901 * void
6902 * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
6903 *
6904 * Calling/Exit State:
6905 * none
6906 *
6907 * Description:
6908 * Input an ASC_QDONE_INFO structure from the chip
6909 */
6910 static void
6911 DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
6912 {
6913 int i;
6914 ushort word;
6915
6916 AscSetChipLramAddr(iop_base, s_addr);
6917 for (i = 0; i < 2 * words; i += 2) {
6918 if (i == 10) {
6919 continue;
6920 }
6921 word = inpw(iop_base + IOP_RAM_DATA);
6922 inbuf[i] = word & 0xff;
6923 inbuf[i + 1] = (word >> 8) & 0xff;
6924 }
6925 ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words);
6926 }
6927
6928 static uchar
6929 _AscCopyLramScsiDoneQ(PortAddr iop_base,
6930 ushort q_addr,
6931 ASC_QDONE_INFO *scsiq, unsigned int max_dma_count)
6932 {
6933 ushort _val;
6934 uchar sg_queue_cnt;
6935
6936 DvcGetQinfo(iop_base,
6937 q_addr + ASC_SCSIQ_DONE_INFO_BEG,
6938 (uchar *)scsiq,
6939 (sizeof(ASC_SCSIQ_2) + sizeof(ASC_SCSIQ_3)) / 2);
6940
6941 _val = AscReadLramWord(iop_base,
6942 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS));
6943 scsiq->q_status = (uchar)_val;
6944 scsiq->q_no = (uchar)(_val >> 8);
6945 _val = AscReadLramWord(iop_base,
6946 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_CNTL));
6947 scsiq->cntl = (uchar)_val;
6948 sg_queue_cnt = (uchar)(_val >> 8);
6949 _val = AscReadLramWord(iop_base,
6950 (ushort)(q_addr +
6951 (ushort)ASC_SCSIQ_B_SENSE_LEN));
6952 scsiq->sense_len = (uchar)_val;
6953 scsiq->extra_bytes = (uchar)(_val >> 8);
6954
6955 /*
6956 * Read high word of remain bytes from alternate location.
6957 */
6958 scsiq->remain_bytes = (((u32)AscReadLramWord(iop_base,
6959 (ushort)(q_addr +
6960 (ushort)
6961 ASC_SCSIQ_W_ALT_DC1)))
6962 << 16);
6963 /*
6964 * Read low word of remain bytes from original location.
6965 */
6966 scsiq->remain_bytes += AscReadLramWord(iop_base,
6967 (ushort)(q_addr + (ushort)
6968 ASC_SCSIQ_DW_REMAIN_XFER_CNT));
6969
6970 scsiq->remain_bytes &= max_dma_count;
6971 return sg_queue_cnt;
6972 }
6973
6974 /*
6975 * asc_isr_callback() - Second Level Interrupt Handler called by AscISR().
6976 *
6977 * Interrupt callback function for the Narrow SCSI Asc Library.
6978 */
6979 static void asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep)
6980 {
6981 struct asc_board *boardp = asc_dvc_varp->drv_ptr;
6982 u32 srb_tag;
6983 struct scsi_cmnd *scp;
6984
6985 ASC_DBG(1, "asc_dvc_varp 0x%p, qdonep 0x%p\n", asc_dvc_varp, qdonep);
6986 ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep);
6987
6988 /*
6989 * Decrease the srb_tag by 1 to find the SCSI command
6990 */
6991 srb_tag = qdonep->d2.srb_tag - 1;
6992 scp = scsi_host_find_tag(boardp->shost, srb_tag);
6993 if (!scp)
6994 return;
6995
6996 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
6997
6998 ASC_STATS(boardp->shost, callback);
6999
7000 dma_unmap_single(boardp->dev, scp->SCp.dma_handle,
7001 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
7002 /*
7003 * 'qdonep' contains the command's ending status.
7004 */
7005 switch (qdonep->d3.done_stat) {
7006 case QD_NO_ERROR:
7007 ASC_DBG(2, "QD_NO_ERROR\n");
7008 scp->result = 0;
7009
7010 /*
7011 * Check for an underrun condition.
7012 *
7013 * If there was no error and an underrun condition, then
7014 * return the number of underrun bytes.
7015 */
7016 if (scsi_bufflen(scp) != 0 && qdonep->remain_bytes != 0 &&
7017 qdonep->remain_bytes <= scsi_bufflen(scp)) {
7018 ASC_DBG(1, "underrun condition %u bytes\n",
7019 (unsigned)qdonep->remain_bytes);
7020 scsi_set_resid(scp, qdonep->remain_bytes);
7021 }
7022 break;
7023
7024 case QD_WITH_ERROR:
7025 ASC_DBG(2, "QD_WITH_ERROR\n");
7026 switch (qdonep->d3.host_stat) {
7027 case QHSTA_NO_ERROR:
7028 if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) {
7029 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
7030 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
7031 SCSI_SENSE_BUFFERSIZE);
7032 /*
7033 * Note: The 'status_byte()' macro used by
7034 * target drivers defined in scsi.h shifts the
7035 * status byte returned by host drivers right
7036 * by 1 bit. This is why target drivers also
7037 * use right shifted status byte definitions.
7038 * For instance target drivers use
7039 * CHECK_CONDITION, defined to 0x1, instead of
7040 * the SCSI defined check condition value of
7041 * 0x2. Host drivers are supposed to return
7042 * the status byte as it is defined by SCSI.
7043 */
7044 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
7045 STATUS_BYTE(qdonep->d3.scsi_stat);
7046 } else {
7047 scp->result = STATUS_BYTE(qdonep->d3.scsi_stat);
7048 }
7049 break;
7050
7051 default:
7052 /* QHSTA error occurred */
7053 ASC_DBG(1, "host_stat 0x%x\n", qdonep->d3.host_stat);
7054 scp->result = HOST_BYTE(DID_BAD_TARGET);
7055 break;
7056 }
7057 break;
7058
7059 case QD_ABORTED_BY_HOST:
7060 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
7061 scp->result =
7062 HOST_BYTE(DID_ABORT) | MSG_BYTE(qdonep->d3.
7063 scsi_msg) |
7064 STATUS_BYTE(qdonep->d3.scsi_stat);
7065 break;
7066
7067 default:
7068 ASC_DBG(1, "done_stat 0x%x\n", qdonep->d3.done_stat);
7069 scp->result =
7070 HOST_BYTE(DID_ERROR) | MSG_BYTE(qdonep->d3.
7071 scsi_msg) |
7072 STATUS_BYTE(qdonep->d3.scsi_stat);
7073 break;
7074 }
7075
7076 /*
7077 * If the 'init_tidmask' bit isn't already set for the target and the
7078 * current request finished normally, then set the bit for the target
7079 * to indicate that a device is present.
7080 */
7081 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
7082 qdonep->d3.done_stat == QD_NO_ERROR &&
7083 qdonep->d3.host_stat == QHSTA_NO_ERROR) {
7084 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
7085 }
7086
7087 asc_scsi_done(scp);
7088 }
7089
7090 static int AscIsrQDone(ASC_DVC_VAR *asc_dvc)
7091 {
7092 uchar next_qp;
7093 uchar n_q_used;
7094 uchar sg_list_qp;
7095 uchar sg_queue_cnt;
7096 uchar q_cnt;
7097 uchar done_q_tail;
7098 uchar tid_no;
7099 ASC_SCSI_BIT_ID_TYPE scsi_busy;
7100 ASC_SCSI_BIT_ID_TYPE target_id;
7101 PortAddr iop_base;
7102 ushort q_addr;
7103 ushort sg_q_addr;
7104 uchar cur_target_qng;
7105 ASC_QDONE_INFO scsiq_buf;
7106 ASC_QDONE_INFO *scsiq;
7107 bool false_overrun;
7108
7109 iop_base = asc_dvc->iop_base;
7110 n_q_used = 1;
7111 scsiq = (ASC_QDONE_INFO *)&scsiq_buf;
7112 done_q_tail = (uchar)AscGetVarDoneQTail(iop_base);
7113 q_addr = ASC_QNO_TO_QADDR(done_q_tail);
7114 next_qp = AscReadLramByte(iop_base,
7115 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_FWD));
7116 if (next_qp != ASC_QLINK_END) {
7117 AscPutVarDoneQTail(iop_base, next_qp);
7118 q_addr = ASC_QNO_TO_QADDR(next_qp);
7119 sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq,
7120 asc_dvc->max_dma_count);
7121 AscWriteLramByte(iop_base,
7122 (ushort)(q_addr +
7123 (ushort)ASC_SCSIQ_B_STATUS),
7124 (uchar)(scsiq->
7125 q_status & (uchar)~(QS_READY |
7126 QS_ABORTED)));
7127 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix);
7128 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix);
7129 if ((scsiq->cntl & QC_SG_HEAD) != 0) {
7130 sg_q_addr = q_addr;
7131 sg_list_qp = next_qp;
7132 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) {
7133 sg_list_qp = AscReadLramByte(iop_base,
7134 (ushort)(sg_q_addr
7135 + (ushort)
7136 ASC_SCSIQ_B_FWD));
7137 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp);
7138 if (sg_list_qp == ASC_QLINK_END) {
7139 AscSetLibErrorCode(asc_dvc,
7140 ASCQ_ERR_SG_Q_LINKS);
7141 scsiq->d3.done_stat = QD_WITH_ERROR;
7142 scsiq->d3.host_stat =
7143 QHSTA_D_QDONE_SG_LIST_CORRUPTED;
7144 goto FATAL_ERR_QDONE;
7145 }
7146 AscWriteLramByte(iop_base,
7147 (ushort)(sg_q_addr + (ushort)
7148 ASC_SCSIQ_B_STATUS),
7149 QS_FREE);
7150 }
7151 n_q_used = sg_queue_cnt + 1;
7152 AscPutVarDoneQTail(iop_base, sg_list_qp);
7153 }
7154 if (asc_dvc->queue_full_or_busy & target_id) {
7155 cur_target_qng = AscReadLramByte(iop_base,
7156 (ushort)((ushort)
7157 ASC_QADR_BEG
7158 + (ushort)
7159 scsiq->d2.
7160 target_ix));
7161 if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) {
7162 scsi_busy = AscReadLramByte(iop_base, (ushort)
7163 ASCV_SCSIBUSY_B);
7164 scsi_busy &= ~target_id;
7165 AscWriteLramByte(iop_base,
7166 (ushort)ASCV_SCSIBUSY_B,
7167 scsi_busy);
7168 asc_dvc->queue_full_or_busy &= ~target_id;
7169 }
7170 }
7171 if (asc_dvc->cur_total_qng >= n_q_used) {
7172 asc_dvc->cur_total_qng -= n_q_used;
7173 if (asc_dvc->cur_dvc_qng[tid_no] != 0) {
7174 asc_dvc->cur_dvc_qng[tid_no]--;
7175 }
7176 } else {
7177 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CUR_QNG);
7178 scsiq->d3.done_stat = QD_WITH_ERROR;
7179 goto FATAL_ERR_QDONE;
7180 }
7181 if ((scsiq->d2.srb_tag == 0UL) ||
7182 ((scsiq->q_status & QS_ABORTED) != 0)) {
7183 return (0x11);
7184 } else if (scsiq->q_status == QS_DONE) {
7185 /*
7186 * This is also curious.
7187 * false_overrun will _always_ be set to 'false'
7188 */
7189 false_overrun = false;
7190 if (scsiq->extra_bytes != 0) {
7191 scsiq->remain_bytes += scsiq->extra_bytes;
7192 }
7193 if (scsiq->d3.done_stat == QD_WITH_ERROR) {
7194 if (scsiq->d3.host_stat ==
7195 QHSTA_M_DATA_OVER_RUN) {
7196 if ((scsiq->
7197 cntl & (QC_DATA_IN | QC_DATA_OUT))
7198 == 0) {
7199 scsiq->d3.done_stat =
7200 QD_NO_ERROR;
7201 scsiq->d3.host_stat =
7202 QHSTA_NO_ERROR;
7203 } else if (false_overrun) {
7204 scsiq->d3.done_stat =
7205 QD_NO_ERROR;
7206 scsiq->d3.host_stat =
7207 QHSTA_NO_ERROR;
7208 }
7209 } else if (scsiq->d3.host_stat ==
7210 QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) {
7211 AscStopChip(iop_base);
7212 AscSetChipControl(iop_base,
7213 (uchar)(CC_SCSI_RESET
7214 | CC_HALT));
7215 udelay(60);
7216 AscSetChipControl(iop_base, CC_HALT);
7217 AscSetChipStatus(iop_base,
7218 CIW_CLR_SCSI_RESET_INT);
7219 AscSetChipStatus(iop_base, 0);
7220 AscSetChipControl(iop_base, 0);
7221 }
7222 }
7223 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
7224 asc_isr_callback(asc_dvc, scsiq);
7225 } else {
7226 if ((AscReadLramByte(iop_base,
7227 (ushort)(q_addr + (ushort)
7228 ASC_SCSIQ_CDB_BEG))
7229 == START_STOP)) {
7230 asc_dvc->unit_not_ready &= ~target_id;
7231 if (scsiq->d3.done_stat != QD_NO_ERROR) {
7232 asc_dvc->start_motor &=
7233 ~target_id;
7234 }
7235 }
7236 }
7237 return (1);
7238 } else {
7239 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_Q_STATUS);
7240 FATAL_ERR_QDONE:
7241 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
7242 asc_isr_callback(asc_dvc, scsiq);
7243 }
7244 return (0x80);
7245 }
7246 }
7247 return (0);
7248 }
7249
7250 static int AscISR(ASC_DVC_VAR *asc_dvc)
7251 {
7252 ASC_CS_TYPE chipstat;
7253 PortAddr iop_base;
7254 ushort saved_ram_addr;
7255 uchar ctrl_reg;
7256 uchar saved_ctrl_reg;
7257 int int_pending;
7258 int status;
7259 uchar host_flag;
7260
7261 iop_base = asc_dvc->iop_base;
7262 int_pending = ASC_FALSE;
7263
7264 if (AscIsIntPending(iop_base) == 0)
7265 return int_pending;
7266
7267 if ((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0) {
7268 return ASC_ERROR;
7269 }
7270 if (asc_dvc->in_critical_cnt != 0) {
7271 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL);
7272 return ASC_ERROR;
7273 }
7274 if (asc_dvc->is_in_int) {
7275 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY);
7276 return ASC_ERROR;
7277 }
7278 asc_dvc->is_in_int = true;
7279 ctrl_reg = AscGetChipControl(iop_base);
7280 saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET |
7281 CC_SINGLE_STEP | CC_DIAG | CC_TEST));
7282 chipstat = AscGetChipStatus(iop_base);
7283 if (chipstat & CSW_SCSI_RESET_LATCH) {
7284 if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) {
7285 int i = 10;
7286 int_pending = ASC_TRUE;
7287 asc_dvc->sdtr_done = 0;
7288 saved_ctrl_reg &= (uchar)(~CC_HALT);
7289 while ((AscGetChipStatus(iop_base) &
7290 CSW_SCSI_RESET_ACTIVE) && (i-- > 0)) {
7291 mdelay(100);
7292 }
7293 AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT));
7294 AscSetChipControl(iop_base, CC_HALT);
7295 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
7296 AscSetChipStatus(iop_base, 0);
7297 chipstat = AscGetChipStatus(iop_base);
7298 }
7299 }
7300 saved_ram_addr = AscGetChipLramAddr(iop_base);
7301 host_flag = AscReadLramByte(iop_base,
7302 ASCV_HOST_FLAG_B) &
7303 (uchar)(~ASC_HOST_FLAG_IN_ISR);
7304 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
7305 (uchar)(host_flag | (uchar)ASC_HOST_FLAG_IN_ISR));
7306 if ((chipstat & CSW_INT_PENDING) || (int_pending)) {
7307 AscAckInterrupt(iop_base);
7308 int_pending = ASC_TRUE;
7309 if ((chipstat & CSW_HALTED) && (ctrl_reg & CC_SINGLE_STEP)) {
7310 if (AscIsrChipHalted(asc_dvc) == ERR) {
7311 goto ISR_REPORT_QDONE_FATAL_ERROR;
7312 } else {
7313 saved_ctrl_reg &= (uchar)(~CC_HALT);
7314 }
7315 } else {
7316 ISR_REPORT_QDONE_FATAL_ERROR:
7317 if ((asc_dvc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) != 0) {
7318 while (((status =
7319 AscIsrQDone(asc_dvc)) & 0x01) != 0) {
7320 }
7321 } else {
7322 do {
7323 if ((status =
7324 AscIsrQDone(asc_dvc)) == 1) {
7325 break;
7326 }
7327 } while (status == 0x11);
7328 }
7329 if ((status & 0x80) != 0)
7330 int_pending = ASC_ERROR;
7331 }
7332 }
7333 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
7334 AscSetChipLramAddr(iop_base, saved_ram_addr);
7335 AscSetChipControl(iop_base, saved_ctrl_reg);
7336 asc_dvc->is_in_int = false;
7337 return int_pending;
7338 }
7339
7340 /*
7341 * advansys_reset()
7342 *
7343 * Reset the host associated with the command 'scp'.
7344 *
7345 * This function runs its own thread. Interrupts must be blocked but
7346 * sleeping is allowed and no locking other than for host structures is
7347 * required. Returns SUCCESS or FAILED.
7348 */
7349 static int advansys_reset(struct scsi_cmnd *scp)
7350 {
7351 struct Scsi_Host *shost = scp->device->host;
7352 struct asc_board *boardp = shost_priv(shost);
7353 unsigned long flags;
7354 int status;
7355 int ret = SUCCESS;
7356
7357 ASC_DBG(1, "0x%p\n", scp);
7358
7359 ASC_STATS(shost, reset);
7360
7361 scmd_printk(KERN_INFO, scp, "SCSI host reset started...\n");
7362
7363 if (ASC_NARROW_BOARD(boardp)) {
7364 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
7365
7366 /* Reset the chip and SCSI bus. */
7367 ASC_DBG(1, "before AscInitAsc1000Driver()\n");
7368 status = AscInitAsc1000Driver(asc_dvc);
7369
7370 /* Refer to ASC_IERR_* definitions for meaning of 'err_code'. */
7371 if (asc_dvc->err_code || !asc_dvc->overrun_dma) {
7372 scmd_printk(KERN_INFO, scp, "SCSI host reset error: "
7373 "0x%x, status: 0x%x\n", asc_dvc->err_code,
7374 status);
7375 ret = FAILED;
7376 } else if (status) {
7377 scmd_printk(KERN_INFO, scp, "SCSI host reset warning: "
7378 "0x%x\n", status);
7379 } else {
7380 scmd_printk(KERN_INFO, scp, "SCSI host reset "
7381 "successful\n");
7382 }
7383
7384 ASC_DBG(1, "after AscInitAsc1000Driver()\n");
7385 } else {
7386 /*
7387 * If the suggest reset bus flags are set, then reset the bus.
7388 * Otherwise only reset the device.
7389 */
7390 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
7391
7392 /*
7393 * Reset the chip and SCSI bus.
7394 */
7395 ASC_DBG(1, "before AdvResetChipAndSB()\n");
7396 switch (AdvResetChipAndSB(adv_dvc)) {
7397 case ASC_TRUE:
7398 scmd_printk(KERN_INFO, scp, "SCSI host reset "
7399 "successful\n");
7400 break;
7401 case ASC_FALSE:
7402 default:
7403 scmd_printk(KERN_INFO, scp, "SCSI host reset error\n");
7404 ret = FAILED;
7405 break;
7406 }
7407 spin_lock_irqsave(shost->host_lock, flags);
7408 AdvISR(adv_dvc);
7409 spin_unlock_irqrestore(shost->host_lock, flags);
7410 }
7411
7412 ASC_DBG(1, "ret %d\n", ret);
7413
7414 return ret;
7415 }
7416
7417 /*
7418 * advansys_biosparam()
7419 *
7420 * Translate disk drive geometry if the "BIOS greater than 1 GB"
7421 * support is enabled for a drive.
7422 *
7423 * ip (information pointer) is an int array with the following definition:
7424 * ip[0]: heads
7425 * ip[1]: sectors
7426 * ip[2]: cylinders
7427 */
7428 static int
7429 advansys_biosparam(struct scsi_device *sdev, struct block_device *bdev,
7430 sector_t capacity, int ip[])
7431 {
7432 struct asc_board *boardp = shost_priv(sdev->host);
7433
7434 ASC_DBG(1, "begin\n");
7435 ASC_STATS(sdev->host, biosparam);
7436 if (ASC_NARROW_BOARD(boardp)) {
7437 if ((boardp->dvc_var.asc_dvc_var.dvc_cntl &
7438 ASC_CNTL_BIOS_GT_1GB) && capacity > 0x200000) {
7439 ip[0] = 255;
7440 ip[1] = 63;
7441 } else {
7442 ip[0] = 64;
7443 ip[1] = 32;
7444 }
7445 } else {
7446 if ((boardp->dvc_var.adv_dvc_var.bios_ctrl &
7447 BIOS_CTRL_EXTENDED_XLAT) && capacity > 0x200000) {
7448 ip[0] = 255;
7449 ip[1] = 63;
7450 } else {
7451 ip[0] = 64;
7452 ip[1] = 32;
7453 }
7454 }
7455 ip[2] = (unsigned long)capacity / (ip[0] * ip[1]);
7456 ASC_DBG(1, "end\n");
7457 return 0;
7458 }
7459
7460 /*
7461 * First-level interrupt handler.
7462 *
7463 * 'dev_id' is a pointer to the interrupting adapter's Scsi_Host.
7464 */
7465 static irqreturn_t advansys_interrupt(int irq, void *dev_id)
7466 {
7467 struct Scsi_Host *shost = dev_id;
7468 struct asc_board *boardp = shost_priv(shost);
7469 irqreturn_t result = IRQ_NONE;
7470
7471 ASC_DBG(2, "boardp 0x%p\n", boardp);
7472 spin_lock(shost->host_lock);
7473 if (ASC_NARROW_BOARD(boardp)) {
7474 if (AscIsIntPending(shost->io_port)) {
7475 result = IRQ_HANDLED;
7476 ASC_STATS(shost, interrupt);
7477 ASC_DBG(1, "before AscISR()\n");
7478 AscISR(&boardp->dvc_var.asc_dvc_var);
7479 }
7480 } else {
7481 ASC_DBG(1, "before AdvISR()\n");
7482 if (AdvISR(&boardp->dvc_var.adv_dvc_var)) {
7483 result = IRQ_HANDLED;
7484 ASC_STATS(shost, interrupt);
7485 }
7486 }
7487 spin_unlock(shost->host_lock);
7488
7489 ASC_DBG(1, "end\n");
7490 return result;
7491 }
7492
7493 static bool AscHostReqRiscHalt(PortAddr iop_base)
7494 {
7495 int count = 0;
7496 bool sta = false;
7497 uchar saved_stop_code;
7498
7499 if (AscIsChipHalted(iop_base))
7500 return true;
7501 saved_stop_code = AscReadLramByte(iop_base, ASCV_STOP_CODE_B);
7502 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
7503 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP);
7504 do {
7505 if (AscIsChipHalted(iop_base)) {
7506 sta = true;
7507 break;
7508 }
7509 mdelay(100);
7510 } while (count++ < 20);
7511 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code);
7512 return sta;
7513 }
7514
7515 static bool
7516 AscSetRunChipSynRegAtID(PortAddr iop_base, uchar tid_no, uchar sdtr_data)
7517 {
7518 bool sta = false;
7519
7520 if (AscHostReqRiscHalt(iop_base)) {
7521 sta = AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
7522 AscStartChip(iop_base);
7523 }
7524 return sta;
7525 }
7526
7527 static void AscAsyncFix(ASC_DVC_VAR *asc_dvc, struct scsi_device *sdev)
7528 {
7529 char type = sdev->type;
7530 ASC_SCSI_BIT_ID_TYPE tid_bits = 1 << sdev->id;
7531
7532 if (!(asc_dvc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN))
7533 return;
7534 if (asc_dvc->init_sdtr & tid_bits)
7535 return;
7536
7537 if ((type == TYPE_ROM) && (strncmp(sdev->vendor, "HP ", 3) == 0))
7538 asc_dvc->pci_fix_asyn_xfer_always |= tid_bits;
7539
7540 asc_dvc->pci_fix_asyn_xfer |= tid_bits;
7541 if ((type == TYPE_PROCESSOR) || (type == TYPE_SCANNER) ||
7542 (type == TYPE_ROM) || (type == TYPE_TAPE))
7543 asc_dvc->pci_fix_asyn_xfer &= ~tid_bits;
7544
7545 if (asc_dvc->pci_fix_asyn_xfer & tid_bits)
7546 AscSetRunChipSynRegAtID(asc_dvc->iop_base, sdev->id,
7547 ASYN_SDTR_DATA_FIX_PCI_REV_AB);
7548 }
7549
7550 static void
7551 advansys_narrow_slave_configure(struct scsi_device *sdev, ASC_DVC_VAR *asc_dvc)
7552 {
7553 ASC_SCSI_BIT_ID_TYPE tid_bit = 1 << sdev->id;
7554 ASC_SCSI_BIT_ID_TYPE orig_use_tagged_qng = asc_dvc->use_tagged_qng;
7555
7556 if (sdev->lun == 0) {
7557 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr = asc_dvc->init_sdtr;
7558 if ((asc_dvc->cfg->sdtr_enable & tid_bit) && sdev->sdtr) {
7559 asc_dvc->init_sdtr |= tid_bit;
7560 } else {
7561 asc_dvc->init_sdtr &= ~tid_bit;
7562 }
7563
7564 if (orig_init_sdtr != asc_dvc->init_sdtr)
7565 AscAsyncFix(asc_dvc, sdev);
7566 }
7567
7568 if (sdev->tagged_supported) {
7569 if (asc_dvc->cfg->cmd_qng_enabled & tid_bit) {
7570 if (sdev->lun == 0) {
7571 asc_dvc->cfg->can_tagged_qng |= tid_bit;
7572 asc_dvc->use_tagged_qng |= tid_bit;
7573 }
7574 scsi_change_queue_depth(sdev,
7575 asc_dvc->max_dvc_qng[sdev->id]);
7576 }
7577 } else {
7578 if (sdev->lun == 0) {
7579 asc_dvc->cfg->can_tagged_qng &= ~tid_bit;
7580 asc_dvc->use_tagged_qng &= ~tid_bit;
7581 }
7582 }
7583
7584 if ((sdev->lun == 0) &&
7585 (orig_use_tagged_qng != asc_dvc->use_tagged_qng)) {
7586 AscWriteLramByte(asc_dvc->iop_base, ASCV_DISC_ENABLE_B,
7587 asc_dvc->cfg->disc_enable);
7588 AscWriteLramByte(asc_dvc->iop_base, ASCV_USE_TAGGED_QNG_B,
7589 asc_dvc->use_tagged_qng);
7590 AscWriteLramByte(asc_dvc->iop_base, ASCV_CAN_TAGGED_QNG_B,
7591 asc_dvc->cfg->can_tagged_qng);
7592
7593 asc_dvc->max_dvc_qng[sdev->id] =
7594 asc_dvc->cfg->max_tag_qng[sdev->id];
7595 AscWriteLramByte(asc_dvc->iop_base,
7596 (ushort)(ASCV_MAX_DVC_QNG_BEG + sdev->id),
7597 asc_dvc->max_dvc_qng[sdev->id]);
7598 }
7599 }
7600
7601 /*
7602 * Wide Transfers
7603 *
7604 * If the EEPROM enabled WDTR for the device and the device supports wide
7605 * bus (16 bit) transfers, then turn on the device's 'wdtr_able' bit and
7606 * write the new value to the microcode.
7607 */
7608 static void
7609 advansys_wide_enable_wdtr(AdvPortAddr iop_base, unsigned short tidmask)
7610 {
7611 unsigned short cfg_word;
7612 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
7613 if ((cfg_word & tidmask) != 0)
7614 return;
7615
7616 cfg_word |= tidmask;
7617 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
7618
7619 /*
7620 * Clear the microcode SDTR and WDTR negotiation done indicators for
7621 * the target to cause it to negotiate with the new setting set above.
7622 * WDTR when accepted causes the target to enter asynchronous mode, so
7623 * SDTR must be negotiated.
7624 */
7625 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7626 cfg_word &= ~tidmask;
7627 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7628 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
7629 cfg_word &= ~tidmask;
7630 AdvWriteWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
7631 }
7632
7633 /*
7634 * Synchronous Transfers
7635 *
7636 * If the EEPROM enabled SDTR for the device and the device
7637 * supports synchronous transfers, then turn on the device's
7638 * 'sdtr_able' bit. Write the new value to the microcode.
7639 */
7640 static void
7641 advansys_wide_enable_sdtr(AdvPortAddr iop_base, unsigned short tidmask)
7642 {
7643 unsigned short cfg_word;
7644 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
7645 if ((cfg_word & tidmask) != 0)
7646 return;
7647
7648 cfg_word |= tidmask;
7649 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
7650
7651 /*
7652 * Clear the microcode "SDTR negotiation" done indicator for the
7653 * target to cause it to negotiate with the new setting set above.
7654 */
7655 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7656 cfg_word &= ~tidmask;
7657 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7658 }
7659
7660 /*
7661 * PPR (Parallel Protocol Request) Capable
7662 *
7663 * If the device supports DT mode, then it must be PPR capable.
7664 * The PPR message will be used in place of the SDTR and WDTR
7665 * messages to negotiate synchronous speed and offset, transfer
7666 * width, and protocol options.
7667 */
7668 static void advansys_wide_enable_ppr(ADV_DVC_VAR *adv_dvc,
7669 AdvPortAddr iop_base, unsigned short tidmask)
7670 {
7671 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
7672 adv_dvc->ppr_able |= tidmask;
7673 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
7674 }
7675
7676 static void
7677 advansys_wide_slave_configure(struct scsi_device *sdev, ADV_DVC_VAR *adv_dvc)
7678 {
7679 AdvPortAddr iop_base = adv_dvc->iop_base;
7680 unsigned short tidmask = 1 << sdev->id;
7681
7682 if (sdev->lun == 0) {
7683 /*
7684 * Handle WDTR, SDTR, and Tag Queuing. If the feature
7685 * is enabled in the EEPROM and the device supports the
7686 * feature, then enable it in the microcode.
7687 */
7688
7689 if ((adv_dvc->wdtr_able & tidmask) && sdev->wdtr)
7690 advansys_wide_enable_wdtr(iop_base, tidmask);
7691 if ((adv_dvc->sdtr_able & tidmask) && sdev->sdtr)
7692 advansys_wide_enable_sdtr(iop_base, tidmask);
7693 if (adv_dvc->chip_type == ADV_CHIP_ASC38C1600 && sdev->ppr)
7694 advansys_wide_enable_ppr(adv_dvc, iop_base, tidmask);
7695
7696 /*
7697 * Tag Queuing is disabled for the BIOS which runs in polled
7698 * mode and would see no benefit from Tag Queuing. Also by
7699 * disabling Tag Queuing in the BIOS devices with Tag Queuing
7700 * bugs will at least work with the BIOS.
7701 */
7702 if ((adv_dvc->tagqng_able & tidmask) &&
7703 sdev->tagged_supported) {
7704 unsigned short cfg_word;
7705 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
7706 cfg_word |= tidmask;
7707 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
7708 cfg_word);
7709 AdvWriteByteLram(iop_base,
7710 ASC_MC_NUMBER_OF_MAX_CMD + sdev->id,
7711 adv_dvc->max_dvc_qng);
7712 }
7713 }
7714
7715 if ((adv_dvc->tagqng_able & tidmask) && sdev->tagged_supported)
7716 scsi_change_queue_depth(sdev, adv_dvc->max_dvc_qng);
7717 }
7718
7719 /*
7720 * Set the number of commands to queue per device for the
7721 * specified host adapter.
7722 */
7723 static int advansys_slave_configure(struct scsi_device *sdev)
7724 {
7725 struct asc_board *boardp = shost_priv(sdev->host);
7726
7727 if (ASC_NARROW_BOARD(boardp))
7728 advansys_narrow_slave_configure(sdev,
7729 &boardp->dvc_var.asc_dvc_var);
7730 else
7731 advansys_wide_slave_configure(sdev,
7732 &boardp->dvc_var.adv_dvc_var);
7733
7734 return 0;
7735 }
7736
7737 static __le32 advansys_get_sense_buffer_dma(struct scsi_cmnd *scp)
7738 {
7739 struct asc_board *board = shost_priv(scp->device->host);
7740 scp->SCp.dma_handle = dma_map_single(board->dev, scp->sense_buffer,
7741 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
7742 dma_cache_sync(board->dev, scp->sense_buffer,
7743 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
7744 return cpu_to_le32(scp->SCp.dma_handle);
7745 }
7746
7747 static int asc_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
7748 struct asc_scsi_q *asc_scsi_q)
7749 {
7750 struct asc_dvc_var *asc_dvc = &boardp->dvc_var.asc_dvc_var;
7751 int use_sg;
7752 u32 srb_tag;
7753
7754 memset(asc_scsi_q, 0, sizeof(*asc_scsi_q));
7755
7756 /*
7757 * Set the srb_tag to the command tag + 1, as
7758 * srb_tag '0' is used internally by the chip.
7759 */
7760 srb_tag = scp->request->tag + 1;
7761 asc_scsi_q->q2.srb_tag = srb_tag;
7762
7763 /*
7764 * Build the ASC_SCSI_Q request.
7765 */
7766 asc_scsi_q->cdbptr = &scp->cmnd[0];
7767 asc_scsi_q->q2.cdb_len = scp->cmd_len;
7768 asc_scsi_q->q1.target_id = ASC_TID_TO_TARGET_ID(scp->device->id);
7769 asc_scsi_q->q1.target_lun = scp->device->lun;
7770 asc_scsi_q->q2.target_ix =
7771 ASC_TIDLUN_TO_IX(scp->device->id, scp->device->lun);
7772 asc_scsi_q->q1.sense_addr = advansys_get_sense_buffer_dma(scp);
7773 asc_scsi_q->q1.sense_len = SCSI_SENSE_BUFFERSIZE;
7774
7775 /*
7776 * If there are any outstanding requests for the current target,
7777 * then every 255th request send an ORDERED request. This heuristic
7778 * tries to retain the benefit of request sorting while preventing
7779 * request starvation. 255 is the max number of tags or pending commands
7780 * a device may have outstanding.
7781 *
7782 * The request count is incremented below for every successfully
7783 * started request.
7784 *
7785 */
7786 if ((asc_dvc->cur_dvc_qng[scp->device->id] > 0) &&
7787 (boardp->reqcnt[scp->device->id] % 255) == 0) {
7788 asc_scsi_q->q2.tag_code = ORDERED_QUEUE_TAG;
7789 } else {
7790 asc_scsi_q->q2.tag_code = SIMPLE_QUEUE_TAG;
7791 }
7792
7793 /* Build ASC_SCSI_Q */
7794 use_sg = scsi_dma_map(scp);
7795 if (use_sg != 0) {
7796 int sgcnt;
7797 struct scatterlist *slp;
7798 struct asc_sg_head *asc_sg_head;
7799
7800 if (use_sg > scp->device->host->sg_tablesize) {
7801 scmd_printk(KERN_ERR, scp, "use_sg %d > "
7802 "sg_tablesize %d\n", use_sg,
7803 scp->device->host->sg_tablesize);
7804 scsi_dma_unmap(scp);
7805 scp->result = HOST_BYTE(DID_ERROR);
7806 return ASC_ERROR;
7807 }
7808
7809 asc_sg_head = kzalloc(sizeof(asc_scsi_q->sg_head) +
7810 use_sg * sizeof(struct asc_sg_list), GFP_ATOMIC);
7811 if (!asc_sg_head) {
7812 scsi_dma_unmap(scp);
7813 scp->result = HOST_BYTE(DID_SOFT_ERROR);
7814 return ASC_ERROR;
7815 }
7816
7817 asc_scsi_q->q1.cntl |= QC_SG_HEAD;
7818 asc_scsi_q->sg_head = asc_sg_head;
7819 asc_scsi_q->q1.data_cnt = 0;
7820 asc_scsi_q->q1.data_addr = 0;
7821 /* This is a byte value, otherwise it would need to be swapped. */
7822 asc_sg_head->entry_cnt = asc_scsi_q->q1.sg_queue_cnt = use_sg;
7823 ASC_STATS_ADD(scp->device->host, xfer_elem,
7824 asc_sg_head->entry_cnt);
7825
7826 /*
7827 * Convert scatter-gather list into ASC_SG_HEAD list.
7828 */
7829 scsi_for_each_sg(scp, slp, use_sg, sgcnt) {
7830 asc_sg_head->sg_list[sgcnt].addr =
7831 cpu_to_le32(sg_dma_address(slp));
7832 asc_sg_head->sg_list[sgcnt].bytes =
7833 cpu_to_le32(sg_dma_len(slp));
7834 ASC_STATS_ADD(scp->device->host, xfer_sect,
7835 DIV_ROUND_UP(sg_dma_len(slp), 512));
7836 }
7837 }
7838
7839 ASC_STATS(scp->device->host, xfer_cnt);
7840
7841 ASC_DBG_PRT_ASC_SCSI_Q(2, asc_scsi_q);
7842 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
7843
7844 return ASC_NOERROR;
7845 }
7846
7847 /*
7848 * Build scatter-gather list for Adv Library (Wide Board).
7849 *
7850 * Additional ADV_SG_BLOCK structures will need to be allocated
7851 * if the total number of scatter-gather elements exceeds
7852 * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are
7853 * assumed to be physically contiguous.
7854 *
7855 * Return:
7856 * ADV_SUCCESS(1) - SG List successfully created
7857 * ADV_ERROR(-1) - SG List creation failed
7858 */
7859 static int
7860 adv_get_sglist(struct asc_board *boardp, adv_req_t *reqp,
7861 ADV_SCSI_REQ_Q *scsiqp, struct scsi_cmnd *scp, int use_sg)
7862 {
7863 adv_sgblk_t *sgblkp, *prev_sgblkp;
7864 struct scatterlist *slp;
7865 int sg_elem_cnt;
7866 ADV_SG_BLOCK *sg_block, *prev_sg_block;
7867 dma_addr_t sgblk_paddr;
7868 int i;
7869
7870 slp = scsi_sglist(scp);
7871 sg_elem_cnt = use_sg;
7872 prev_sgblkp = NULL;
7873 prev_sg_block = NULL;
7874 reqp->sgblkp = NULL;
7875
7876 for (;;) {
7877 /*
7878 * Allocate a 'adv_sgblk_t' structure from the board free
7879 * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK
7880 * (15) scatter-gather elements.
7881 */
7882 sgblkp = dma_pool_alloc(boardp->adv_sgblk_pool, GFP_ATOMIC,
7883 &sgblk_paddr);
7884 if (!sgblkp) {
7885 ASC_DBG(1, "no free adv_sgblk_t\n");
7886 ASC_STATS(scp->device->host, adv_build_nosg);
7887
7888 /*
7889 * Allocation failed. Free 'adv_sgblk_t' structures
7890 * already allocated for the request.
7891 */
7892 while ((sgblkp = reqp->sgblkp) != NULL) {
7893 /* Remove 'sgblkp' from the request list. */
7894 reqp->sgblkp = sgblkp->next_sgblkp;
7895 sgblkp->next_sgblkp = NULL;
7896 dma_pool_free(boardp->adv_sgblk_pool, sgblkp,
7897 sgblkp->sg_addr);
7898 }
7899 return ASC_BUSY;
7900 }
7901 /* Complete 'adv_sgblk_t' board allocation. */
7902 sgblkp->sg_addr = sgblk_paddr;
7903 sgblkp->next_sgblkp = NULL;
7904 sg_block = &sgblkp->sg_block;
7905
7906 /*
7907 * Check if this is the first 'adv_sgblk_t' for the
7908 * request.
7909 */
7910 if (reqp->sgblkp == NULL) {
7911 /* Request's first scatter-gather block. */
7912 reqp->sgblkp = sgblkp;
7913
7914 /*
7915 * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical
7916 * address pointers.
7917 */
7918 scsiqp->sg_list_ptr = sg_block;
7919 scsiqp->sg_real_addr = cpu_to_le32(sgblk_paddr);
7920 } else {
7921 /* Request's second or later scatter-gather block. */
7922 prev_sgblkp->next_sgblkp = sgblkp;
7923
7924 /*
7925 * Point the previous ADV_SG_BLOCK structure to
7926 * the newly allocated ADV_SG_BLOCK structure.
7927 */
7928 prev_sg_block->sg_ptr = cpu_to_le32(sgblk_paddr);
7929 }
7930
7931 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) {
7932 sg_block->sg_list[i].sg_addr =
7933 cpu_to_le32(sg_dma_address(slp));
7934 sg_block->sg_list[i].sg_count =
7935 cpu_to_le32(sg_dma_len(slp));
7936 ASC_STATS_ADD(scp->device->host, xfer_sect,
7937 DIV_ROUND_UP(sg_dma_len(slp), 512));
7938
7939 if (--sg_elem_cnt == 0) {
7940 /*
7941 * Last ADV_SG_BLOCK and scatter-gather entry.
7942 */
7943 sg_block->sg_cnt = i + 1;
7944 sg_block->sg_ptr = 0L; /* Last ADV_SG_BLOCK in list. */
7945 return ADV_SUCCESS;
7946 }
7947 slp++;
7948 }
7949 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
7950 prev_sg_block = sg_block;
7951 prev_sgblkp = sgblkp;
7952 }
7953 }
7954
7955 /*
7956 * Build a request structure for the Adv Library (Wide Board).
7957 *
7958 * If an adv_req_t can not be allocated to issue the request,
7959 * then return ASC_BUSY. If an error occurs, then return ASC_ERROR.
7960 *
7961 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the
7962 * microcode for DMA addresses or math operations are byte swapped
7963 * to little-endian order.
7964 */
7965 static int
7966 adv_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
7967 adv_req_t **adv_reqpp)
7968 {
7969 u32 srb_tag = scp->request->tag;
7970 adv_req_t *reqp;
7971 ADV_SCSI_REQ_Q *scsiqp;
7972 int ret;
7973 int use_sg;
7974 dma_addr_t sense_addr;
7975
7976 /*
7977 * Allocate an adv_req_t structure from the board to execute
7978 * the command.
7979 */
7980 reqp = &boardp->adv_reqp[srb_tag];
7981 if (reqp->cmndp && reqp->cmndp != scp ) {
7982 ASC_DBG(1, "no free adv_req_t\n");
7983 ASC_STATS(scp->device->host, adv_build_noreq);
7984 return ASC_BUSY;
7985 }
7986
7987 reqp->req_addr = boardp->adv_reqp_addr + (srb_tag * sizeof(adv_req_t));
7988
7989 scsiqp = &reqp->scsi_req_q;
7990
7991 /*
7992 * Initialize the structure.
7993 */
7994 scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0;
7995
7996 /*
7997 * Set the srb_tag to the command tag.
7998 */
7999 scsiqp->srb_tag = srb_tag;
8000
8001 /*
8002 * Set 'host_scribble' to point to the adv_req_t structure.
8003 */
8004 reqp->cmndp = scp;
8005 scp->host_scribble = (void *)reqp;
8006
8007 /*
8008 * Build the ADV_SCSI_REQ_Q request.
8009 */
8010
8011 /* Set CDB length and copy it to the request structure. */
8012 scsiqp->cdb_len = scp->cmd_len;
8013 /* Copy first 12 CDB bytes to cdb[]. */
8014 memcpy(scsiqp->cdb, scp->cmnd, scp->cmd_len < 12 ? scp->cmd_len : 12);
8015 /* Copy last 4 CDB bytes, if present, to cdb16[]. */
8016 if (scp->cmd_len > 12) {
8017 int cdb16_len = scp->cmd_len - 12;
8018
8019 memcpy(scsiqp->cdb16, &scp->cmnd[12], cdb16_len);
8020 }
8021
8022 scsiqp->target_id = scp->device->id;
8023 scsiqp->target_lun = scp->device->lun;
8024
8025 sense_addr = dma_map_single(boardp->dev, scp->sense_buffer,
8026 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
8027 scsiqp->sense_addr = cpu_to_le32(sense_addr);
8028 scsiqp->sense_len = cpu_to_le32(SCSI_SENSE_BUFFERSIZE);
8029
8030 /* Build ADV_SCSI_REQ_Q */
8031
8032 use_sg = scsi_dma_map(scp);
8033 if (use_sg == 0) {
8034 /* Zero-length transfer */
8035 reqp->sgblkp = NULL;
8036 scsiqp->data_cnt = 0;
8037
8038 scsiqp->data_addr = 0;
8039 scsiqp->sg_list_ptr = NULL;
8040 scsiqp->sg_real_addr = 0;
8041 } else {
8042 if (use_sg > ADV_MAX_SG_LIST) {
8043 scmd_printk(KERN_ERR, scp, "use_sg %d > "
8044 "ADV_MAX_SG_LIST %d\n", use_sg,
8045 scp->device->host->sg_tablesize);
8046 scsi_dma_unmap(scp);
8047 scp->result = HOST_BYTE(DID_ERROR);
8048 reqp->cmndp = NULL;
8049 scp->host_scribble = NULL;
8050
8051 return ASC_ERROR;
8052 }
8053
8054 scsiqp->data_cnt = cpu_to_le32(scsi_bufflen(scp));
8055
8056 ret = adv_get_sglist(boardp, reqp, scsiqp, scp, use_sg);
8057 if (ret != ADV_SUCCESS) {
8058 scsi_dma_unmap(scp);
8059 scp->result = HOST_BYTE(DID_ERROR);
8060 reqp->cmndp = NULL;
8061 scp->host_scribble = NULL;
8062
8063 return ret;
8064 }
8065
8066 ASC_STATS_ADD(scp->device->host, xfer_elem, use_sg);
8067 }
8068
8069 ASC_STATS(scp->device->host, xfer_cnt);
8070
8071 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
8072 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
8073
8074 *adv_reqpp = reqp;
8075
8076 return ASC_NOERROR;
8077 }
8078
8079 static int AscSgListToQueue(int sg_list)
8080 {
8081 int n_sg_list_qs;
8082
8083 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q);
8084 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0)
8085 n_sg_list_qs++;
8086 return n_sg_list_qs + 1;
8087 }
8088
8089 static uint
8090 AscGetNumOfFreeQueue(ASC_DVC_VAR *asc_dvc, uchar target_ix, uchar n_qs)
8091 {
8092 uint cur_used_qs;
8093 uint cur_free_qs;
8094 ASC_SCSI_BIT_ID_TYPE target_id;
8095 uchar tid_no;
8096
8097 target_id = ASC_TIX_TO_TARGET_ID(target_ix);
8098 tid_no = ASC_TIX_TO_TID(target_ix);
8099 if ((asc_dvc->unit_not_ready & target_id) ||
8100 (asc_dvc->queue_full_or_busy & target_id)) {
8101 return 0;
8102 }
8103 if (n_qs == 1) {
8104 cur_used_qs = (uint) asc_dvc->cur_total_qng +
8105 (uint) asc_dvc->last_q_shortage + (uint) ASC_MIN_FREE_Q;
8106 } else {
8107 cur_used_qs = (uint) asc_dvc->cur_total_qng +
8108 (uint) ASC_MIN_FREE_Q;
8109 }
8110 if ((uint) (cur_used_qs + n_qs) <= (uint) asc_dvc->max_total_qng) {
8111 cur_free_qs = (uint) asc_dvc->max_total_qng - cur_used_qs;
8112 if (asc_dvc->cur_dvc_qng[tid_no] >=
8113 asc_dvc->max_dvc_qng[tid_no]) {
8114 return 0;
8115 }
8116 return cur_free_qs;
8117 }
8118 if (n_qs > 1) {
8119 if ((n_qs > asc_dvc->last_q_shortage)
8120 && (n_qs <= (asc_dvc->max_total_qng - ASC_MIN_FREE_Q))) {
8121 asc_dvc->last_q_shortage = n_qs;
8122 }
8123 }
8124 return 0;
8125 }
8126
8127 static uchar AscAllocFreeQueue(PortAddr iop_base, uchar free_q_head)
8128 {
8129 ushort q_addr;
8130 uchar next_qp;
8131 uchar q_status;
8132
8133 q_addr = ASC_QNO_TO_QADDR(free_q_head);
8134 q_status = (uchar)AscReadLramByte(iop_base,
8135 (ushort)(q_addr +
8136 ASC_SCSIQ_B_STATUS));
8137 next_qp = AscReadLramByte(iop_base, (ushort)(q_addr + ASC_SCSIQ_B_FWD));
8138 if (((q_status & QS_READY) == 0) && (next_qp != ASC_QLINK_END))
8139 return next_qp;
8140 return ASC_QLINK_END;
8141 }
8142
8143 static uchar
8144 AscAllocMultipleFreeQueue(PortAddr iop_base, uchar free_q_head, uchar n_free_q)
8145 {
8146 uchar i;
8147
8148 for (i = 0; i < n_free_q; i++) {
8149 free_q_head = AscAllocFreeQueue(iop_base, free_q_head);
8150 if (free_q_head == ASC_QLINK_END)
8151 break;
8152 }
8153 return free_q_head;
8154 }
8155
8156 /*
8157 * void
8158 * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
8159 *
8160 * Calling/Exit State:
8161 * none
8162 *
8163 * Description:
8164 * Output an ASC_SCSI_Q structure to the chip
8165 */
8166 static void
8167 DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
8168 {
8169 int i;
8170
8171 ASC_DBG_PRT_HEX(2, "DvcPutScsiQ", outbuf, 2 * words);
8172 AscSetChipLramAddr(iop_base, s_addr);
8173 for (i = 0; i < 2 * words; i += 2) {
8174 if (i == 4 || i == 20) {
8175 continue;
8176 }
8177 outpw(iop_base + IOP_RAM_DATA,
8178 ((ushort)outbuf[i + 1] << 8) | outbuf[i]);
8179 }
8180 }
8181
8182 static int AscPutReadyQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
8183 {
8184 ushort q_addr;
8185 uchar tid_no;
8186 uchar sdtr_data;
8187 uchar syn_period_ix;
8188 uchar syn_offset;
8189 PortAddr iop_base;
8190
8191 iop_base = asc_dvc->iop_base;
8192 if (((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) &&
8193 ((asc_dvc->sdtr_done & scsiq->q1.target_id) == 0)) {
8194 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix);
8195 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
8196 syn_period_ix =
8197 (sdtr_data >> 4) & (asc_dvc->max_sdtr_index - 1);
8198 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
8199 AscMsgOutSDTR(asc_dvc,
8200 asc_dvc->sdtr_period_tbl[syn_period_ix],
8201 syn_offset);
8202 scsiq->q1.cntl |= QC_MSG_OUT;
8203 }
8204 q_addr = ASC_QNO_TO_QADDR(q_no);
8205 if ((scsiq->q1.target_id & asc_dvc->use_tagged_qng) == 0) {
8206 scsiq->q2.tag_code &= ~SIMPLE_QUEUE_TAG;
8207 }
8208 scsiq->q1.status = QS_FREE;
8209 AscMemWordCopyPtrToLram(iop_base,
8210 q_addr + ASC_SCSIQ_CDB_BEG,
8211 (uchar *)scsiq->cdbptr, scsiq->q2.cdb_len >> 1);
8212
8213 DvcPutScsiQ(iop_base,
8214 q_addr + ASC_SCSIQ_CPY_BEG,
8215 (uchar *)&scsiq->q1.cntl,
8216 ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1);
8217 AscWriteLramWord(iop_base,
8218 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS),
8219 (ushort)(((ushort)scsiq->q1.
8220 q_no << 8) | (ushort)QS_READY));
8221 return 1;
8222 }
8223
8224 static int
8225 AscPutReadySgListQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
8226 {
8227 int sta;
8228 int i;
8229 ASC_SG_HEAD *sg_head;
8230 ASC_SG_LIST_Q scsi_sg_q;
8231 __le32 saved_data_addr;
8232 __le32 saved_data_cnt;
8233 PortAddr iop_base;
8234 ushort sg_list_dwords;
8235 ushort sg_index;
8236 ushort sg_entry_cnt;
8237 ushort q_addr;
8238 uchar next_qp;
8239
8240 iop_base = asc_dvc->iop_base;
8241 sg_head = scsiq->sg_head;
8242 saved_data_addr = scsiq->q1.data_addr;
8243 saved_data_cnt = scsiq->q1.data_cnt;
8244 scsiq->q1.data_addr = sg_head->sg_list[0].addr;
8245 scsiq->q1.data_cnt = sg_head->sg_list[0].bytes;
8246 #if CC_VERY_LONG_SG_LIST
8247 /*
8248 * If sg_head->entry_cnt is greater than ASC_MAX_SG_LIST
8249 * then not all SG elements will fit in the allocated queues.
8250 * The rest of the SG elements will be copied when the RISC
8251 * completes the SG elements that fit and halts.
8252 */
8253 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
8254 /*
8255 * Set sg_entry_cnt to be the number of SG elements that
8256 * will fit in the allocated SG queues. It is minus 1, because
8257 * the first SG element is handled above. ASC_MAX_SG_LIST is
8258 * already inflated by 1 to account for this. For example it
8259 * may be 50 which is 1 + 7 queues * 7 SG elements.
8260 */
8261 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
8262
8263 /*
8264 * Keep track of remaining number of SG elements that will
8265 * need to be handled from a_isr.c.
8266 */
8267 scsiq->remain_sg_entry_cnt =
8268 sg_head->entry_cnt - ASC_MAX_SG_LIST;
8269 } else {
8270 #endif /* CC_VERY_LONG_SG_LIST */
8271 /*
8272 * Set sg_entry_cnt to be the number of SG elements that
8273 * will fit in the allocated SG queues. It is minus 1, because
8274 * the first SG element is handled above.
8275 */
8276 sg_entry_cnt = sg_head->entry_cnt - 1;
8277 #if CC_VERY_LONG_SG_LIST
8278 }
8279 #endif /* CC_VERY_LONG_SG_LIST */
8280 if (sg_entry_cnt != 0) {
8281 scsiq->q1.cntl |= QC_SG_HEAD;
8282 q_addr = ASC_QNO_TO_QADDR(q_no);
8283 sg_index = 1;
8284 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt;
8285 scsi_sg_q.sg_head_qp = q_no;
8286 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
8287 for (i = 0; i < sg_head->queue_cnt; i++) {
8288 scsi_sg_q.seq_no = i + 1;
8289 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
8290 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
8291 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
8292 if (i == 0) {
8293 scsi_sg_q.sg_list_cnt =
8294 ASC_SG_LIST_PER_Q;
8295 scsi_sg_q.sg_cur_list_cnt =
8296 ASC_SG_LIST_PER_Q;
8297 } else {
8298 scsi_sg_q.sg_list_cnt =
8299 ASC_SG_LIST_PER_Q - 1;
8300 scsi_sg_q.sg_cur_list_cnt =
8301 ASC_SG_LIST_PER_Q - 1;
8302 }
8303 } else {
8304 #if CC_VERY_LONG_SG_LIST
8305 /*
8306 * This is the last SG queue in the list of
8307 * allocated SG queues. If there are more
8308 * SG elements than will fit in the allocated
8309 * queues, then set the QCSG_SG_XFER_MORE flag.
8310 */
8311 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
8312 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
8313 } else {
8314 #endif /* CC_VERY_LONG_SG_LIST */
8315 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
8316 #if CC_VERY_LONG_SG_LIST
8317 }
8318 #endif /* CC_VERY_LONG_SG_LIST */
8319 sg_list_dwords = sg_entry_cnt << 1;
8320 if (i == 0) {
8321 scsi_sg_q.sg_list_cnt = sg_entry_cnt;
8322 scsi_sg_q.sg_cur_list_cnt =
8323 sg_entry_cnt;
8324 } else {
8325 scsi_sg_q.sg_list_cnt =
8326 sg_entry_cnt - 1;
8327 scsi_sg_q.sg_cur_list_cnt =
8328 sg_entry_cnt - 1;
8329 }
8330 sg_entry_cnt = 0;
8331 }
8332 next_qp = AscReadLramByte(iop_base,
8333 (ushort)(q_addr +
8334 ASC_SCSIQ_B_FWD));
8335 scsi_sg_q.q_no = next_qp;
8336 q_addr = ASC_QNO_TO_QADDR(next_qp);
8337 AscMemWordCopyPtrToLram(iop_base,
8338 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
8339 (uchar *)&scsi_sg_q,
8340 sizeof(ASC_SG_LIST_Q) >> 1);
8341 AscMemDWordCopyPtrToLram(iop_base,
8342 q_addr + ASC_SGQ_LIST_BEG,
8343 (uchar *)&sg_head->
8344 sg_list[sg_index],
8345 sg_list_dwords);
8346 sg_index += ASC_SG_LIST_PER_Q;
8347 scsiq->next_sg_index = sg_index;
8348 }
8349 } else {
8350 scsiq->q1.cntl &= ~QC_SG_HEAD;
8351 }
8352 sta = AscPutReadyQueue(asc_dvc, scsiq, q_no);
8353 scsiq->q1.data_addr = saved_data_addr;
8354 scsiq->q1.data_cnt = saved_data_cnt;
8355 return (sta);
8356 }
8357
8358 static int
8359 AscSendScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar n_q_required)
8360 {
8361 PortAddr iop_base;
8362 uchar free_q_head;
8363 uchar next_qp;
8364 uchar tid_no;
8365 uchar target_ix;
8366 int sta;
8367
8368 iop_base = asc_dvc->iop_base;
8369 target_ix = scsiq->q2.target_ix;
8370 tid_no = ASC_TIX_TO_TID(target_ix);
8371 sta = 0;
8372 free_q_head = (uchar)AscGetVarFreeQHead(iop_base);
8373 if (n_q_required > 1) {
8374 next_qp = AscAllocMultipleFreeQueue(iop_base, free_q_head,
8375 (uchar)n_q_required);
8376 if (next_qp != ASC_QLINK_END) {
8377 asc_dvc->last_q_shortage = 0;
8378 scsiq->sg_head->queue_cnt = n_q_required - 1;
8379 scsiq->q1.q_no = free_q_head;
8380 sta = AscPutReadySgListQueue(asc_dvc, scsiq,
8381 free_q_head);
8382 }
8383 } else if (n_q_required == 1) {
8384 next_qp = AscAllocFreeQueue(iop_base, free_q_head);
8385 if (next_qp != ASC_QLINK_END) {
8386 scsiq->q1.q_no = free_q_head;
8387 sta = AscPutReadyQueue(asc_dvc, scsiq, free_q_head);
8388 }
8389 }
8390 if (sta == 1) {
8391 AscPutVarFreeQHead(iop_base, next_qp);
8392 asc_dvc->cur_total_qng += n_q_required;
8393 asc_dvc->cur_dvc_qng[tid_no]++;
8394 }
8395 return sta;
8396 }
8397
8398 #define ASC_SYN_OFFSET_ONE_DISABLE_LIST 16
8399 static uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] = {
8400 INQUIRY,
8401 REQUEST_SENSE,
8402 READ_CAPACITY,
8403 READ_TOC,
8404 MODE_SELECT,
8405 MODE_SENSE,
8406 MODE_SELECT_10,
8407 MODE_SENSE_10,
8408 0xFF,
8409 0xFF,
8410 0xFF,
8411 0xFF,
8412 0xFF,
8413 0xFF,
8414 0xFF,
8415 0xFF
8416 };
8417
8418 static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq)
8419 {
8420 PortAddr iop_base;
8421 int sta;
8422 int n_q_required;
8423 bool disable_syn_offset_one_fix;
8424 int i;
8425 u32 addr;
8426 ushort sg_entry_cnt = 0;
8427 ushort sg_entry_cnt_minus_one = 0;
8428 uchar target_ix;
8429 uchar tid_no;
8430 uchar sdtr_data;
8431 uchar extra_bytes;
8432 uchar scsi_cmd;
8433 uchar disable_cmd;
8434 ASC_SG_HEAD *sg_head;
8435 unsigned long data_cnt;
8436
8437 iop_base = asc_dvc->iop_base;
8438 sg_head = scsiq->sg_head;
8439 if (asc_dvc->err_code != 0)
8440 return (ERR);
8441 scsiq->q1.q_no = 0;
8442 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) {
8443 scsiq->q1.extra_bytes = 0;
8444 }
8445 sta = 0;
8446 target_ix = scsiq->q2.target_ix;
8447 tid_no = ASC_TIX_TO_TID(target_ix);
8448 n_q_required = 1;
8449 if (scsiq->cdbptr[0] == REQUEST_SENSE) {
8450 if ((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) {
8451 asc_dvc->sdtr_done &= ~scsiq->q1.target_id;
8452 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
8453 AscMsgOutSDTR(asc_dvc,
8454 asc_dvc->
8455 sdtr_period_tbl[(sdtr_data >> 4) &
8456 (uchar)(asc_dvc->
8457 max_sdtr_index -
8458 1)],
8459 (uchar)(sdtr_data & (uchar)
8460 ASC_SYN_MAX_OFFSET));
8461 scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT);
8462 }
8463 }
8464 if (asc_dvc->in_critical_cnt != 0) {
8465 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY);
8466 return (ERR);
8467 }
8468 asc_dvc->in_critical_cnt++;
8469 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
8470 if ((sg_entry_cnt = sg_head->entry_cnt) == 0) {
8471 asc_dvc->in_critical_cnt--;
8472 return (ERR);
8473 }
8474 #if !CC_VERY_LONG_SG_LIST
8475 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
8476 asc_dvc->in_critical_cnt--;
8477 return (ERR);
8478 }
8479 #endif /* !CC_VERY_LONG_SG_LIST */
8480 if (sg_entry_cnt == 1) {
8481 scsiq->q1.data_addr = sg_head->sg_list[0].addr;
8482 scsiq->q1.data_cnt = sg_head->sg_list[0].bytes;
8483 scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE);
8484 }
8485 sg_entry_cnt_minus_one = sg_entry_cnt - 1;
8486 }
8487 scsi_cmd = scsiq->cdbptr[0];
8488 disable_syn_offset_one_fix = false;
8489 if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) &&
8490 !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) {
8491 if (scsiq->q1.cntl & QC_SG_HEAD) {
8492 data_cnt = 0;
8493 for (i = 0; i < sg_entry_cnt; i++) {
8494 data_cnt += le32_to_cpu(sg_head->sg_list[i].
8495 bytes);
8496 }
8497 } else {
8498 data_cnt = le32_to_cpu(scsiq->q1.data_cnt);
8499 }
8500 if (data_cnt != 0UL) {
8501 if (data_cnt < 512UL) {
8502 disable_syn_offset_one_fix = true;
8503 } else {
8504 for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST;
8505 i++) {
8506 disable_cmd =
8507 _syn_offset_one_disable_cmd[i];
8508 if (disable_cmd == 0xFF) {
8509 break;
8510 }
8511 if (scsi_cmd == disable_cmd) {
8512 disable_syn_offset_one_fix =
8513 true;
8514 break;
8515 }
8516 }
8517 }
8518 }
8519 }
8520 if (disable_syn_offset_one_fix) {
8521 scsiq->q2.tag_code &= ~SIMPLE_QUEUE_TAG;
8522 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX |
8523 ASC_TAG_FLAG_DISABLE_DISCONNECT);
8524 } else {
8525 scsiq->q2.tag_code &= 0x27;
8526 }
8527 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
8528 if (asc_dvc->bug_fix_cntl) {
8529 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
8530 if ((scsi_cmd == READ_6) ||
8531 (scsi_cmd == READ_10)) {
8532 addr = le32_to_cpu(sg_head->
8533 sg_list
8534 [sg_entry_cnt_minus_one].
8535 addr) +
8536 le32_to_cpu(sg_head->
8537 sg_list
8538 [sg_entry_cnt_minus_one].
8539 bytes);
8540 extra_bytes =
8541 (uchar)((ushort)addr & 0x0003);
8542 if ((extra_bytes != 0)
8543 &&
8544 ((scsiq->q2.
8545 tag_code &
8546 ASC_TAG_FLAG_EXTRA_BYTES)
8547 == 0)) {
8548 scsiq->q2.tag_code |=
8549 ASC_TAG_FLAG_EXTRA_BYTES;
8550 scsiq->q1.extra_bytes =
8551 extra_bytes;
8552 data_cnt =
8553 le32_to_cpu(sg_head->
8554 sg_list
8555 [sg_entry_cnt_minus_one].
8556 bytes);
8557 data_cnt -= extra_bytes;
8558 sg_head->
8559 sg_list
8560 [sg_entry_cnt_minus_one].
8561 bytes =
8562 cpu_to_le32(data_cnt);
8563 }
8564 }
8565 }
8566 }
8567 sg_head->entry_to_copy = sg_head->entry_cnt;
8568 #if CC_VERY_LONG_SG_LIST
8569 /*
8570 * Set the sg_entry_cnt to the maximum possible. The rest of
8571 * the SG elements will be copied when the RISC completes the
8572 * SG elements that fit and halts.
8573 */
8574 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
8575 sg_entry_cnt = ASC_MAX_SG_LIST;
8576 }
8577 #endif /* CC_VERY_LONG_SG_LIST */
8578 n_q_required = AscSgListToQueue(sg_entry_cnt);
8579 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, n_q_required) >=
8580 (uint) n_q_required)
8581 || ((scsiq->q1.cntl & QC_URGENT) != 0)) {
8582 if ((sta =
8583 AscSendScsiQueue(asc_dvc, scsiq,
8584 n_q_required)) == 1) {
8585 asc_dvc->in_critical_cnt--;
8586 return (sta);
8587 }
8588 }
8589 } else {
8590 if (asc_dvc->bug_fix_cntl) {
8591 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
8592 if ((scsi_cmd == READ_6) ||
8593 (scsi_cmd == READ_10)) {
8594 addr =
8595 le32_to_cpu(scsiq->q1.data_addr) +
8596 le32_to_cpu(scsiq->q1.data_cnt);
8597 extra_bytes =
8598 (uchar)((ushort)addr & 0x0003);
8599 if ((extra_bytes != 0)
8600 &&
8601 ((scsiq->q2.
8602 tag_code &
8603 ASC_TAG_FLAG_EXTRA_BYTES)
8604 == 0)) {
8605 data_cnt =
8606 le32_to_cpu(scsiq->q1.
8607 data_cnt);
8608 if (((ushort)data_cnt & 0x01FF)
8609 == 0) {
8610 scsiq->q2.tag_code |=
8611 ASC_TAG_FLAG_EXTRA_BYTES;
8612 data_cnt -= extra_bytes;
8613 scsiq->q1.data_cnt =
8614 cpu_to_le32
8615 (data_cnt);
8616 scsiq->q1.extra_bytes =
8617 extra_bytes;
8618 }
8619 }
8620 }
8621 }
8622 }
8623 n_q_required = 1;
8624 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, 1) >= 1) ||
8625 ((scsiq->q1.cntl & QC_URGENT) != 0)) {
8626 if ((sta = AscSendScsiQueue(asc_dvc, scsiq,
8627 n_q_required)) == 1) {
8628 asc_dvc->in_critical_cnt--;
8629 return (sta);
8630 }
8631 }
8632 }
8633 asc_dvc->in_critical_cnt--;
8634 return (sta);
8635 }
8636
8637 /*
8638 * AdvExeScsiQueue() - Send a request to the RISC microcode program.
8639 *
8640 * Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q,
8641 * add the carrier to the ICQ (Initiator Command Queue), and tickle the
8642 * RISC to notify it a new command is ready to be executed.
8643 *
8644 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
8645 * set to SCSI_MAX_RETRY.
8646 *
8647 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the microcode
8648 * for DMA addresses or math operations are byte swapped to little-endian
8649 * order.
8650 *
8651 * Return:
8652 * ADV_SUCCESS(1) - The request was successfully queued.
8653 * ADV_BUSY(0) - Resource unavailable; Retry again after pending
8654 * request completes.
8655 * ADV_ERROR(-1) - Invalid ADV_SCSI_REQ_Q request structure
8656 * host IC error.
8657 */
8658 static int AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc, adv_req_t *reqp)
8659 {
8660 AdvPortAddr iop_base;
8661 ADV_CARR_T *new_carrp;
8662 ADV_SCSI_REQ_Q *scsiq = &reqp->scsi_req_q;
8663
8664 /*
8665 * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID.
8666 */
8667 if (scsiq->target_id > ADV_MAX_TID) {
8668 scsiq->host_status = QHSTA_M_INVALID_DEVICE;
8669 scsiq->done_status = QD_WITH_ERROR;
8670 return ADV_ERROR;
8671 }
8672
8673 iop_base = asc_dvc->iop_base;
8674
8675 /*
8676 * Allocate a carrier ensuring at least one carrier always
8677 * remains on the freelist and initialize fields.
8678 */
8679 new_carrp = adv_get_next_carrier(asc_dvc);
8680 if (!new_carrp) {
8681 ASC_DBG(1, "No free carriers\n");
8682 return ADV_BUSY;
8683 }
8684
8685 asc_dvc->carr_pending_cnt++;
8686
8687 /*
8688 * Clear the ADV_SCSI_REQ_Q done flag.
8689 */
8690 scsiq->a_flag &= ~ADV_SCSIQ_DONE;
8691
8692 /* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */
8693 scsiq->scsiq_ptr = cpu_to_le32(scsiq->srb_tag);
8694 scsiq->scsiq_rptr = cpu_to_le32(reqp->req_addr);
8695
8696 scsiq->carr_va = asc_dvc->icq_sp->carr_va;
8697 scsiq->carr_pa = asc_dvc->icq_sp->carr_pa;
8698
8699 /*
8700 * Use the current stopper to send the ADV_SCSI_REQ_Q command to
8701 * the microcode. The newly allocated stopper will become the new
8702 * stopper.
8703 */
8704 asc_dvc->icq_sp->areq_vpa = scsiq->scsiq_rptr;
8705
8706 /*
8707 * Set the 'next_vpa' pointer for the old stopper to be the
8708 * physical address of the new stopper. The RISC can only
8709 * follow physical addresses.
8710 */
8711 asc_dvc->icq_sp->next_vpa = new_carrp->carr_pa;
8712
8713 /*
8714 * Set the host adapter stopper pointer to point to the new carrier.
8715 */
8716 asc_dvc->icq_sp = new_carrp;
8717
8718 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
8719 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
8720 /*
8721 * Tickle the RISC to tell it to read its Command Queue Head pointer.
8722 */
8723 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
8724 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
8725 /*
8726 * Clear the tickle value. In the ASC-3550 the RISC flag
8727 * command 'clr_tickle_a' does not work unless the host
8728 * value is cleared.
8729 */
8730 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
8731 ADV_TICKLE_NOP);
8732 }
8733 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
8734 /*
8735 * Notify the RISC a carrier is ready by writing the physical
8736 * address of the new carrier stopper to the COMMA register.
8737 */
8738 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
8739 le32_to_cpu(new_carrp->carr_pa));
8740 }
8741
8742 return ADV_SUCCESS;
8743 }
8744
8745 /*
8746 * Execute a single 'Scsi_Cmnd'.
8747 */
8748 static int asc_execute_scsi_cmnd(struct scsi_cmnd *scp)
8749 {
8750 int ret, err_code;
8751 struct asc_board *boardp = shost_priv(scp->device->host);
8752
8753 ASC_DBG(1, "scp 0x%p\n", scp);
8754
8755 if (ASC_NARROW_BOARD(boardp)) {
8756 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
8757 struct asc_scsi_q asc_scsi_q;
8758
8759 /* asc_build_req() can not return ASC_BUSY. */
8760 ret = asc_build_req(boardp, scp, &asc_scsi_q);
8761 if (ret == ASC_ERROR) {
8762 ASC_STATS(scp->device->host, build_error);
8763 return ASC_ERROR;
8764 }
8765
8766 ret = AscExeScsiQueue(asc_dvc, &asc_scsi_q);
8767 kfree(asc_scsi_q.sg_head);
8768 err_code = asc_dvc->err_code;
8769 } else {
8770 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
8771 adv_req_t *adv_reqp;
8772
8773 switch (adv_build_req(boardp, scp, &adv_reqp)) {
8774 case ASC_NOERROR:
8775 ASC_DBG(3, "adv_build_req ASC_NOERROR\n");
8776 break;
8777 case ASC_BUSY:
8778 ASC_DBG(1, "adv_build_req ASC_BUSY\n");
8779 /*
8780 * The asc_stats fields 'adv_build_noreq' and
8781 * 'adv_build_nosg' count wide board busy conditions.
8782 * They are updated in adv_build_req and
8783 * adv_get_sglist, respectively.
8784 */
8785 return ASC_BUSY;
8786 case ASC_ERROR:
8787 default:
8788 ASC_DBG(1, "adv_build_req ASC_ERROR\n");
8789 ASC_STATS(scp->device->host, build_error);
8790 return ASC_ERROR;
8791 }
8792
8793 ret = AdvExeScsiQueue(adv_dvc, adv_reqp);
8794 err_code = adv_dvc->err_code;
8795 }
8796
8797 switch (ret) {
8798 case ASC_NOERROR:
8799 ASC_STATS(scp->device->host, exe_noerror);
8800 /*
8801 * Increment monotonically increasing per device
8802 * successful request counter. Wrapping doesn't matter.
8803 */
8804 boardp->reqcnt[scp->device->id]++;
8805 ASC_DBG(1, "ExeScsiQueue() ASC_NOERROR\n");
8806 break;
8807 case ASC_BUSY:
8808 ASC_DBG(1, "ExeScsiQueue() ASC_BUSY\n");
8809 ASC_STATS(scp->device->host, exe_busy);
8810 break;
8811 case ASC_ERROR:
8812 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() ASC_ERROR, "
8813 "err_code 0x%x\n", err_code);
8814 ASC_STATS(scp->device->host, exe_error);
8815 scp->result = HOST_BYTE(DID_ERROR);
8816 break;
8817 default:
8818 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() unknown, "
8819 "err_code 0x%x\n", err_code);
8820 ASC_STATS(scp->device->host, exe_unknown);
8821 scp->result = HOST_BYTE(DID_ERROR);
8822 break;
8823 }
8824
8825 ASC_DBG(1, "end\n");
8826 return ret;
8827 }
8828
8829 /*
8830 * advansys_queuecommand() - interrupt-driven I/O entrypoint.
8831 *
8832 * This function always returns 0. Command return status is saved
8833 * in the 'scp' result field.
8834 */
8835 static int
8836 advansys_queuecommand_lck(struct scsi_cmnd *scp, void (*done)(struct scsi_cmnd *))
8837 {
8838 struct Scsi_Host *shost = scp->device->host;
8839 int asc_res, result = 0;
8840
8841 ASC_STATS(shost, queuecommand);
8842 scp->scsi_done = done;
8843
8844 asc_res = asc_execute_scsi_cmnd(scp);
8845
8846 switch (asc_res) {
8847 case ASC_NOERROR:
8848 break;
8849 case ASC_BUSY:
8850 result = SCSI_MLQUEUE_HOST_BUSY;
8851 break;
8852 case ASC_ERROR:
8853 default:
8854 asc_scsi_done(scp);
8855 break;
8856 }
8857
8858 return result;
8859 }
8860
8861 static DEF_SCSI_QCMD(advansys_queuecommand)
8862
8863 static ushort AscGetEisaChipCfg(PortAddr iop_base)
8864 {
8865 PortAddr eisa_cfg_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
8866 (PortAddr) (ASC_EISA_CFG_IOP_MASK);
8867 return inpw(eisa_cfg_iop);
8868 }
8869
8870 /*
8871 * Return the BIOS address of the adapter at the specified
8872 * I/O port and with the specified bus type.
8873 */
8874 static unsigned short AscGetChipBiosAddress(PortAddr iop_base,
8875 unsigned short bus_type)
8876 {
8877 unsigned short cfg_lsw;
8878 unsigned short bios_addr;
8879
8880 /*
8881 * The PCI BIOS is re-located by the motherboard BIOS. Because
8882 * of this the driver can not determine where a PCI BIOS is
8883 * loaded and executes.
8884 */
8885 if (bus_type & ASC_IS_PCI)
8886 return 0;
8887
8888 if ((bus_type & ASC_IS_EISA) != 0) {
8889 cfg_lsw = AscGetEisaChipCfg(iop_base);
8890 cfg_lsw &= 0x000F;
8891 bios_addr = ASC_BIOS_MIN_ADDR + cfg_lsw * ASC_BIOS_BANK_SIZE;
8892 return bios_addr;
8893 }
8894
8895 cfg_lsw = AscGetChipCfgLsw(iop_base);
8896
8897 /*
8898 * ISA PnP uses the top bit as the 32K BIOS flag
8899 */
8900 if (bus_type == ASC_IS_ISAPNP)
8901 cfg_lsw &= 0x7FFF;
8902 bios_addr = ASC_BIOS_MIN_ADDR + (cfg_lsw >> 12) * ASC_BIOS_BANK_SIZE;
8903 return bios_addr;
8904 }
8905
8906 static uchar AscSetChipScsiID(PortAddr iop_base, uchar new_host_id)
8907 {
8908 ushort cfg_lsw;
8909
8910 if (AscGetChipScsiID(iop_base) == new_host_id) {
8911 return (new_host_id);
8912 }
8913 cfg_lsw = AscGetChipCfgLsw(iop_base);
8914 cfg_lsw &= 0xF8FF;
8915 cfg_lsw |= (ushort)((new_host_id & ASC_MAX_TID) << 8);
8916 AscSetChipCfgLsw(iop_base, cfg_lsw);
8917 return (AscGetChipScsiID(iop_base));
8918 }
8919
8920 static unsigned char AscGetChipScsiCtrl(PortAddr iop_base)
8921 {
8922 unsigned char sc;
8923
8924 AscSetBank(iop_base, 1);
8925 sc = inp(iop_base + IOP_REG_SC);
8926 AscSetBank(iop_base, 0);
8927 return sc;
8928 }
8929
8930 static unsigned char AscGetChipVersion(PortAddr iop_base,
8931 unsigned short bus_type)
8932 {
8933 if (bus_type & ASC_IS_EISA) {
8934 PortAddr eisa_iop;
8935 unsigned char revision;
8936 eisa_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
8937 (PortAddr) ASC_EISA_REV_IOP_MASK;
8938 revision = inp(eisa_iop);
8939 return ASC_CHIP_MIN_VER_EISA - 1 + revision;
8940 }
8941 return AscGetChipVerNo(iop_base);
8942 }
8943
8944 #ifdef CONFIG_ISA
8945 static void AscEnableIsaDma(uchar dma_channel)
8946 {
8947 if (dma_channel < 4) {
8948 outp(0x000B, (ushort)(0xC0 | dma_channel));
8949 outp(0x000A, dma_channel);
8950 } else if (dma_channel < 8) {
8951 outp(0x00D6, (ushort)(0xC0 | (dma_channel - 4)));
8952 outp(0x00D4, (ushort)(dma_channel - 4));
8953 }
8954 }
8955 #endif /* CONFIG_ISA */
8956
8957 static int AscStopQueueExe(PortAddr iop_base)
8958 {
8959 int count = 0;
8960
8961 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) == 0) {
8962 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
8963 ASC_STOP_REQ_RISC_STOP);
8964 do {
8965 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) &
8966 ASC_STOP_ACK_RISC_STOP) {
8967 return (1);
8968 }
8969 mdelay(100);
8970 } while (count++ < 20);
8971 }
8972 return (0);
8973 }
8974
8975 static unsigned int AscGetMaxDmaCount(ushort bus_type)
8976 {
8977 if (bus_type & ASC_IS_ISA)
8978 return ASC_MAX_ISA_DMA_COUNT;
8979 else if (bus_type & (ASC_IS_EISA | ASC_IS_VL))
8980 return ASC_MAX_VL_DMA_COUNT;
8981 return ASC_MAX_PCI_DMA_COUNT;
8982 }
8983
8984 #ifdef CONFIG_ISA
8985 static ushort AscGetIsaDmaChannel(PortAddr iop_base)
8986 {
8987 ushort channel;
8988
8989 channel = AscGetChipCfgLsw(iop_base) & 0x0003;
8990 if (channel == 0x03)
8991 return (0);
8992 else if (channel == 0x00)
8993 return (7);
8994 return (channel + 4);
8995 }
8996
8997 static ushort AscSetIsaDmaChannel(PortAddr iop_base, ushort dma_channel)
8998 {
8999 ushort cfg_lsw;
9000 uchar value;
9001
9002 if ((dma_channel >= 5) && (dma_channel <= 7)) {
9003 if (dma_channel == 7)
9004 value = 0x00;
9005 else
9006 value = dma_channel - 4;
9007 cfg_lsw = AscGetChipCfgLsw(iop_base) & 0xFFFC;
9008 cfg_lsw |= value;
9009 AscSetChipCfgLsw(iop_base, cfg_lsw);
9010 return (AscGetIsaDmaChannel(iop_base));
9011 }
9012 return 0;
9013 }
9014
9015 static uchar AscGetIsaDmaSpeed(PortAddr iop_base)
9016 {
9017 uchar speed_value;
9018
9019 AscSetBank(iop_base, 1);
9020 speed_value = AscReadChipDmaSpeed(iop_base);
9021 speed_value &= 0x07;
9022 AscSetBank(iop_base, 0);
9023 return speed_value;
9024 }
9025
9026 static uchar AscSetIsaDmaSpeed(PortAddr iop_base, uchar speed_value)
9027 {
9028 speed_value &= 0x07;
9029 AscSetBank(iop_base, 1);
9030 AscWriteChipDmaSpeed(iop_base, speed_value);
9031 AscSetBank(iop_base, 0);
9032 return AscGetIsaDmaSpeed(iop_base);
9033 }
9034 #endif /* CONFIG_ISA */
9035
9036 static ushort AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc)
9037 {
9038 int i;
9039 PortAddr iop_base;
9040 ushort warn_code;
9041 uchar chip_version;
9042
9043 iop_base = asc_dvc->iop_base;
9044 warn_code = 0;
9045 asc_dvc->err_code = 0;
9046 if ((asc_dvc->bus_type &
9047 (ASC_IS_ISA | ASC_IS_PCI | ASC_IS_EISA | ASC_IS_VL)) == 0) {
9048 asc_dvc->err_code |= ASC_IERR_NO_BUS_TYPE;
9049 }
9050 AscSetChipControl(iop_base, CC_HALT);
9051 AscSetChipStatus(iop_base, 0);
9052 asc_dvc->bug_fix_cntl = 0;
9053 asc_dvc->pci_fix_asyn_xfer = 0;
9054 asc_dvc->pci_fix_asyn_xfer_always = 0;
9055 /* asc_dvc->init_state initialized in AscInitGetConfig(). */
9056 asc_dvc->sdtr_done = 0;
9057 asc_dvc->cur_total_qng = 0;
9058 asc_dvc->is_in_int = false;
9059 asc_dvc->in_critical_cnt = 0;
9060 asc_dvc->last_q_shortage = 0;
9061 asc_dvc->use_tagged_qng = 0;
9062 asc_dvc->no_scam = 0;
9063 asc_dvc->unit_not_ready = 0;
9064 asc_dvc->queue_full_or_busy = 0;
9065 asc_dvc->redo_scam = 0;
9066 asc_dvc->res2 = 0;
9067 asc_dvc->min_sdtr_index = 0;
9068 asc_dvc->cfg->can_tagged_qng = 0;
9069 asc_dvc->cfg->cmd_qng_enabled = 0;
9070 asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL;
9071 asc_dvc->init_sdtr = 0;
9072 asc_dvc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG;
9073 asc_dvc->scsi_reset_wait = 3;
9074 asc_dvc->start_motor = ASC_SCSI_WIDTH_BIT_SET;
9075 asc_dvc->max_dma_count = AscGetMaxDmaCount(asc_dvc->bus_type);
9076 asc_dvc->cfg->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET;
9077 asc_dvc->cfg->disc_enable = ASC_SCSI_WIDTH_BIT_SET;
9078 asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID;
9079 chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type);
9080 asc_dvc->cfg->chip_version = chip_version;
9081 asc_dvc->sdtr_period_tbl = asc_syn_xfer_period;
9082 asc_dvc->max_sdtr_index = 7;
9083 if ((asc_dvc->bus_type & ASC_IS_PCI) &&
9084 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) {
9085 asc_dvc->bus_type = ASC_IS_PCI_ULTRA;
9086 asc_dvc->sdtr_period_tbl = asc_syn_ultra_xfer_period;
9087 asc_dvc->max_sdtr_index = 15;
9088 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) {
9089 AscSetExtraControl(iop_base,
9090 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
9091 } else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) {
9092 AscSetExtraControl(iop_base,
9093 (SEC_ACTIVE_NEGATE |
9094 SEC_ENABLE_FILTER));
9095 }
9096 }
9097 if (asc_dvc->bus_type == ASC_IS_PCI) {
9098 AscSetExtraControl(iop_base,
9099 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
9100 }
9101
9102 asc_dvc->cfg->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED;
9103 #ifdef CONFIG_ISA
9104 if ((asc_dvc->bus_type & ASC_IS_ISA) != 0) {
9105 if (chip_version >= ASC_CHIP_MIN_VER_ISA_PNP) {
9106 AscSetChipIFC(iop_base, IFC_INIT_DEFAULT);
9107 asc_dvc->bus_type = ASC_IS_ISAPNP;
9108 }
9109 asc_dvc->cfg->isa_dma_channel =
9110 (uchar)AscGetIsaDmaChannel(iop_base);
9111 }
9112 #endif /* CONFIG_ISA */
9113 for (i = 0; i <= ASC_MAX_TID; i++) {
9114 asc_dvc->cur_dvc_qng[i] = 0;
9115 asc_dvc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG;
9116 asc_dvc->scsiq_busy_head[i] = (ASC_SCSI_Q *)0L;
9117 asc_dvc->scsiq_busy_tail[i] = (ASC_SCSI_Q *)0L;
9118 asc_dvc->cfg->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG;
9119 }
9120 return warn_code;
9121 }
9122
9123 static int AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg)
9124 {
9125 int retry;
9126
9127 for (retry = 0; retry < ASC_EEP_MAX_RETRY; retry++) {
9128 unsigned char read_back;
9129 AscSetChipEEPCmd(iop_base, cmd_reg);
9130 mdelay(1);
9131 read_back = AscGetChipEEPCmd(iop_base);
9132 if (read_back == cmd_reg)
9133 return 1;
9134 }
9135 return 0;
9136 }
9137
9138 static void AscWaitEEPRead(void)
9139 {
9140 mdelay(1);
9141 }
9142
9143 static ushort AscReadEEPWord(PortAddr iop_base, uchar addr)
9144 {
9145 ushort read_wval;
9146 uchar cmd_reg;
9147
9148 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
9149 AscWaitEEPRead();
9150 cmd_reg = addr | ASC_EEP_CMD_READ;
9151 AscWriteEEPCmdReg(iop_base, cmd_reg);
9152 AscWaitEEPRead();
9153 read_wval = AscGetChipEEPData(iop_base);
9154 AscWaitEEPRead();
9155 return read_wval;
9156 }
9157
9158 static ushort AscGetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
9159 ushort bus_type)
9160 {
9161 ushort wval;
9162 ushort sum;
9163 ushort *wbuf;
9164 int cfg_beg;
9165 int cfg_end;
9166 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
9167 int s_addr;
9168
9169 wbuf = (ushort *)cfg_buf;
9170 sum = 0;
9171 /* Read two config words; Byte-swapping done by AscReadEEPWord(). */
9172 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9173 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
9174 sum += *wbuf;
9175 }
9176 if (bus_type & ASC_IS_VL) {
9177 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9178 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9179 } else {
9180 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9181 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9182 }
9183 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9184 wval = AscReadEEPWord(iop_base, (uchar)s_addr);
9185 if (s_addr <= uchar_end_in_config) {
9186 /*
9187 * Swap all char fields - must unswap bytes already swapped
9188 * by AscReadEEPWord().
9189 */
9190 *wbuf = le16_to_cpu(wval);
9191 } else {
9192 /* Don't swap word field at the end - cntl field. */
9193 *wbuf = wval;
9194 }
9195 sum += wval; /* Checksum treats all EEPROM data as words. */
9196 }
9197 /*
9198 * Read the checksum word which will be compared against 'sum'
9199 * by the caller. Word field already swapped.
9200 */
9201 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
9202 return sum;
9203 }
9204
9205 static int AscTestExternalLram(ASC_DVC_VAR *asc_dvc)
9206 {
9207 PortAddr iop_base;
9208 ushort q_addr;
9209 ushort saved_word;
9210 int sta;
9211
9212 iop_base = asc_dvc->iop_base;
9213 sta = 0;
9214 q_addr = ASC_QNO_TO_QADDR(241);
9215 saved_word = AscReadLramWord(iop_base, q_addr);
9216 AscSetChipLramAddr(iop_base, q_addr);
9217 AscSetChipLramData(iop_base, 0x55AA);
9218 mdelay(10);
9219 AscSetChipLramAddr(iop_base, q_addr);
9220 if (AscGetChipLramData(iop_base) == 0x55AA) {
9221 sta = 1;
9222 AscWriteLramWord(iop_base, q_addr, saved_word);
9223 }
9224 return (sta);
9225 }
9226
9227 static void AscWaitEEPWrite(void)
9228 {
9229 mdelay(20);
9230 }
9231
9232 static int AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg)
9233 {
9234 ushort read_back;
9235 int retry;
9236
9237 retry = 0;
9238 while (true) {
9239 AscSetChipEEPData(iop_base, data_reg);
9240 mdelay(1);
9241 read_back = AscGetChipEEPData(iop_base);
9242 if (read_back == data_reg) {
9243 return (1);
9244 }
9245 if (retry++ > ASC_EEP_MAX_RETRY) {
9246 return (0);
9247 }
9248 }
9249 }
9250
9251 static ushort AscWriteEEPWord(PortAddr iop_base, uchar addr, ushort word_val)
9252 {
9253 ushort read_wval;
9254
9255 read_wval = AscReadEEPWord(iop_base, addr);
9256 if (read_wval != word_val) {
9257 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_ABLE);
9258 AscWaitEEPRead();
9259 AscWriteEEPDataReg(iop_base, word_val);
9260 AscWaitEEPRead();
9261 AscWriteEEPCmdReg(iop_base,
9262 (uchar)((uchar)ASC_EEP_CMD_WRITE | addr));
9263 AscWaitEEPWrite();
9264 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
9265 AscWaitEEPRead();
9266 return (AscReadEEPWord(iop_base, addr));
9267 }
9268 return (read_wval);
9269 }
9270
9271 static int AscSetEEPConfigOnce(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
9272 ushort bus_type)
9273 {
9274 int n_error;
9275 ushort *wbuf;
9276 ushort word;
9277 ushort sum;
9278 int s_addr;
9279 int cfg_beg;
9280 int cfg_end;
9281 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
9282
9283 wbuf = (ushort *)cfg_buf;
9284 n_error = 0;
9285 sum = 0;
9286 /* Write two config words; AscWriteEEPWord() will swap bytes. */
9287 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9288 sum += *wbuf;
9289 if (*wbuf != AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
9290 n_error++;
9291 }
9292 }
9293 if (bus_type & ASC_IS_VL) {
9294 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9295 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9296 } else {
9297 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9298 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9299 }
9300 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9301 if (s_addr <= uchar_end_in_config) {
9302 /*
9303 * This is a char field. Swap char fields before they are
9304 * swapped again by AscWriteEEPWord().
9305 */
9306 word = cpu_to_le16(*wbuf);
9307 if (word !=
9308 AscWriteEEPWord(iop_base, (uchar)s_addr, word)) {
9309 n_error++;
9310 }
9311 } else {
9312 /* Don't swap word field at the end - cntl field. */
9313 if (*wbuf !=
9314 AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
9315 n_error++;
9316 }
9317 }
9318 sum += *wbuf; /* Checksum calculated from word values. */
9319 }
9320 /* Write checksum word. It will be swapped by AscWriteEEPWord(). */
9321 *wbuf = sum;
9322 if (sum != AscWriteEEPWord(iop_base, (uchar)s_addr, sum)) {
9323 n_error++;
9324 }
9325
9326 /* Read EEPROM back again. */
9327 wbuf = (ushort *)cfg_buf;
9328 /*
9329 * Read two config words; Byte-swapping done by AscReadEEPWord().
9330 */
9331 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9332 if (*wbuf != AscReadEEPWord(iop_base, (uchar)s_addr)) {
9333 n_error++;
9334 }
9335 }
9336 if (bus_type & ASC_IS_VL) {
9337 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9338 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9339 } else {
9340 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9341 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9342 }
9343 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9344 if (s_addr <= uchar_end_in_config) {
9345 /*
9346 * Swap all char fields. Must unswap bytes already swapped
9347 * by AscReadEEPWord().
9348 */
9349 word =
9350 le16_to_cpu(AscReadEEPWord
9351 (iop_base, (uchar)s_addr));
9352 } else {
9353 /* Don't swap word field at the end - cntl field. */
9354 word = AscReadEEPWord(iop_base, (uchar)s_addr);
9355 }
9356 if (*wbuf != word) {
9357 n_error++;
9358 }
9359 }
9360 /* Read checksum; Byte swapping not needed. */
9361 if (AscReadEEPWord(iop_base, (uchar)s_addr) != sum) {
9362 n_error++;
9363 }
9364 return n_error;
9365 }
9366
9367 static int AscSetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
9368 ushort bus_type)
9369 {
9370 int retry;
9371 int n_error;
9372
9373 retry = 0;
9374 while (true) {
9375 if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf,
9376 bus_type)) == 0) {
9377 break;
9378 }
9379 if (++retry > ASC_EEP_MAX_RETRY) {
9380 break;
9381 }
9382 }
9383 return n_error;
9384 }
9385
9386 static ushort AscInitFromEEP(ASC_DVC_VAR *asc_dvc)
9387 {
9388 ASCEEP_CONFIG eep_config_buf;
9389 ASCEEP_CONFIG *eep_config;
9390 PortAddr iop_base;
9391 ushort chksum;
9392 ushort warn_code;
9393 ushort cfg_msw, cfg_lsw;
9394 int i;
9395 int write_eep = 0;
9396
9397 iop_base = asc_dvc->iop_base;
9398 warn_code = 0;
9399 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE);
9400 AscStopQueueExe(iop_base);
9401 if ((AscStopChip(iop_base)) ||
9402 (AscGetChipScsiCtrl(iop_base) != 0)) {
9403 asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE;
9404 AscResetChipAndScsiBus(asc_dvc);
9405 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
9406 }
9407 if (!AscIsChipHalted(iop_base)) {
9408 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
9409 return (warn_code);
9410 }
9411 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
9412 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
9413 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
9414 return (warn_code);
9415 }
9416 eep_config = (ASCEEP_CONFIG *)&eep_config_buf;
9417 cfg_msw = AscGetChipCfgMsw(iop_base);
9418 cfg_lsw = AscGetChipCfgLsw(iop_base);
9419 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
9420 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9421 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
9422 AscSetChipCfgMsw(iop_base, cfg_msw);
9423 }
9424 chksum = AscGetEEPConfig(iop_base, eep_config, asc_dvc->bus_type);
9425 ASC_DBG(1, "chksum 0x%x\n", chksum);
9426 if (chksum == 0) {
9427 chksum = 0xaa55;
9428 }
9429 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
9430 warn_code |= ASC_WARN_AUTO_CONFIG;
9431 if (asc_dvc->cfg->chip_version == 3) {
9432 if (eep_config->cfg_lsw != cfg_lsw) {
9433 warn_code |= ASC_WARN_EEPROM_RECOVER;
9434 eep_config->cfg_lsw =
9435 AscGetChipCfgLsw(iop_base);
9436 }
9437 if (eep_config->cfg_msw != cfg_msw) {
9438 warn_code |= ASC_WARN_EEPROM_RECOVER;
9439 eep_config->cfg_msw =
9440 AscGetChipCfgMsw(iop_base);
9441 }
9442 }
9443 }
9444 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9445 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON;
9446 ASC_DBG(1, "eep_config->chksum 0x%x\n", eep_config->chksum);
9447 if (chksum != eep_config->chksum) {
9448 if (AscGetChipVersion(iop_base, asc_dvc->bus_type) ==
9449 ASC_CHIP_VER_PCI_ULTRA_3050) {
9450 ASC_DBG(1, "chksum error ignored; EEPROM-less board\n");
9451 eep_config->init_sdtr = 0xFF;
9452 eep_config->disc_enable = 0xFF;
9453 eep_config->start_motor = 0xFF;
9454 eep_config->use_cmd_qng = 0;
9455 eep_config->max_total_qng = 0xF0;
9456 eep_config->max_tag_qng = 0x20;
9457 eep_config->cntl = 0xBFFF;
9458 ASC_EEP_SET_CHIP_ID(eep_config, 7);
9459 eep_config->no_scam = 0;
9460 eep_config->adapter_info[0] = 0;
9461 eep_config->adapter_info[1] = 0;
9462 eep_config->adapter_info[2] = 0;
9463 eep_config->adapter_info[3] = 0;
9464 eep_config->adapter_info[4] = 0;
9465 /* Indicate EEPROM-less board. */
9466 eep_config->adapter_info[5] = 0xBB;
9467 } else {
9468 ASC_PRINT
9469 ("AscInitFromEEP: EEPROM checksum error; Will try to re-write EEPROM.\n");
9470 write_eep = 1;
9471 warn_code |= ASC_WARN_EEPROM_CHKSUM;
9472 }
9473 }
9474 asc_dvc->cfg->sdtr_enable = eep_config->init_sdtr;
9475 asc_dvc->cfg->disc_enable = eep_config->disc_enable;
9476 asc_dvc->cfg->cmd_qng_enabled = eep_config->use_cmd_qng;
9477 asc_dvc->cfg->isa_dma_speed = ASC_EEP_GET_DMA_SPD(eep_config);
9478 asc_dvc->start_motor = eep_config->start_motor;
9479 asc_dvc->dvc_cntl = eep_config->cntl;
9480 asc_dvc->no_scam = eep_config->no_scam;
9481 asc_dvc->cfg->adapter_info[0] = eep_config->adapter_info[0];
9482 asc_dvc->cfg->adapter_info[1] = eep_config->adapter_info[1];
9483 asc_dvc->cfg->adapter_info[2] = eep_config->adapter_info[2];
9484 asc_dvc->cfg->adapter_info[3] = eep_config->adapter_info[3];
9485 asc_dvc->cfg->adapter_info[4] = eep_config->adapter_info[4];
9486 asc_dvc->cfg->adapter_info[5] = eep_config->adapter_info[5];
9487 if (!AscTestExternalLram(asc_dvc)) {
9488 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) ==
9489 ASC_IS_PCI_ULTRA)) {
9490 eep_config->max_total_qng =
9491 ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
9492 eep_config->max_tag_qng =
9493 ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG;
9494 } else {
9495 eep_config->cfg_msw |= 0x0800;
9496 cfg_msw |= 0x0800;
9497 AscSetChipCfgMsw(iop_base, cfg_msw);
9498 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG;
9499 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG;
9500 }
9501 } else {
9502 }
9503 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) {
9504 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG;
9505 }
9506 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) {
9507 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG;
9508 }
9509 if (eep_config->max_tag_qng > eep_config->max_total_qng) {
9510 eep_config->max_tag_qng = eep_config->max_total_qng;
9511 }
9512 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) {
9513 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC;
9514 }
9515 asc_dvc->max_total_qng = eep_config->max_total_qng;
9516 if ((eep_config->use_cmd_qng & eep_config->disc_enable) !=
9517 eep_config->use_cmd_qng) {
9518 eep_config->disc_enable = eep_config->use_cmd_qng;
9519 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
9520 }
9521 ASC_EEP_SET_CHIP_ID(eep_config,
9522 ASC_EEP_GET_CHIP_ID(eep_config) & ASC_MAX_TID);
9523 asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config);
9524 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) &&
9525 !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) {
9526 asc_dvc->min_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX;
9527 }
9528
9529 for (i = 0; i <= ASC_MAX_TID; i++) {
9530 asc_dvc->dos_int13_table[i] = eep_config->dos_int13_table[i];
9531 asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng;
9532 asc_dvc->cfg->sdtr_period_offset[i] =
9533 (uchar)(ASC_DEF_SDTR_OFFSET |
9534 (asc_dvc->min_sdtr_index << 4));
9535 }
9536 eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
9537 if (write_eep) {
9538 if ((i = AscSetEEPConfig(iop_base, eep_config,
9539 asc_dvc->bus_type)) != 0) {
9540 ASC_PRINT1
9541 ("AscInitFromEEP: Failed to re-write EEPROM with %d errors.\n",
9542 i);
9543 } else {
9544 ASC_PRINT
9545 ("AscInitFromEEP: Successfully re-wrote EEPROM.\n");
9546 }
9547 }
9548 return (warn_code);
9549 }
9550
9551 static int AscInitGetConfig(struct Scsi_Host *shost)
9552 {
9553 struct asc_board *board = shost_priv(shost);
9554 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
9555 unsigned short warn_code = 0;
9556
9557 asc_dvc->init_state = ASC_INIT_STATE_BEG_GET_CFG;
9558 if (asc_dvc->err_code != 0)
9559 return asc_dvc->err_code;
9560
9561 if (AscFindSignature(asc_dvc->iop_base)) {
9562 warn_code |= AscInitAscDvcVar(asc_dvc);
9563 warn_code |= AscInitFromEEP(asc_dvc);
9564 asc_dvc->init_state |= ASC_INIT_STATE_END_GET_CFG;
9565 if (asc_dvc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT)
9566 asc_dvc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
9567 } else {
9568 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
9569 }
9570
9571 switch (warn_code) {
9572 case 0: /* No error */
9573 break;
9574 case ASC_WARN_IO_PORT_ROTATE:
9575 shost_printk(KERN_WARNING, shost, "I/O port address "
9576 "modified\n");
9577 break;
9578 case ASC_WARN_AUTO_CONFIG:
9579 shost_printk(KERN_WARNING, shost, "I/O port increment switch "
9580 "enabled\n");
9581 break;
9582 case ASC_WARN_EEPROM_CHKSUM:
9583 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
9584 break;
9585 case ASC_WARN_IRQ_MODIFIED:
9586 shost_printk(KERN_WARNING, shost, "IRQ modified\n");
9587 break;
9588 case ASC_WARN_CMD_QNG_CONFLICT:
9589 shost_printk(KERN_WARNING, shost, "tag queuing enabled w/o "
9590 "disconnects\n");
9591 break;
9592 default:
9593 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
9594 warn_code);
9595 break;
9596 }
9597
9598 if (asc_dvc->err_code != 0)
9599 shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
9600 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
9601
9602 return asc_dvc->err_code;
9603 }
9604
9605 static int AscInitSetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
9606 {
9607 struct asc_board *board = shost_priv(shost);
9608 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
9609 PortAddr iop_base = asc_dvc->iop_base;
9610 unsigned short cfg_msw;
9611 unsigned short warn_code = 0;
9612
9613 asc_dvc->init_state |= ASC_INIT_STATE_BEG_SET_CFG;
9614 if (asc_dvc->err_code != 0)
9615 return asc_dvc->err_code;
9616 if (!AscFindSignature(asc_dvc->iop_base)) {
9617 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
9618 return asc_dvc->err_code;
9619 }
9620
9621 cfg_msw = AscGetChipCfgMsw(iop_base);
9622 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
9623 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9624 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
9625 AscSetChipCfgMsw(iop_base, cfg_msw);
9626 }
9627 if ((asc_dvc->cfg->cmd_qng_enabled & asc_dvc->cfg->disc_enable) !=
9628 asc_dvc->cfg->cmd_qng_enabled) {
9629 asc_dvc->cfg->disc_enable = asc_dvc->cfg->cmd_qng_enabled;
9630 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
9631 }
9632 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
9633 warn_code |= ASC_WARN_AUTO_CONFIG;
9634 }
9635 #ifdef CONFIG_PCI
9636 if (asc_dvc->bus_type & ASC_IS_PCI) {
9637 cfg_msw &= 0xFFC0;
9638 AscSetChipCfgMsw(iop_base, cfg_msw);
9639 if ((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) {
9640 } else {
9641 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
9642 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
9643 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB;
9644 asc_dvc->bug_fix_cntl |=
9645 ASC_BUG_FIX_ASYN_USE_SYN;
9646 }
9647 }
9648 } else
9649 #endif /* CONFIG_PCI */
9650 if (asc_dvc->bus_type == ASC_IS_ISAPNP) {
9651 if (AscGetChipVersion(iop_base, asc_dvc->bus_type)
9652 == ASC_CHIP_VER_ASYN_BUG) {
9653 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
9654 }
9655 }
9656 if (AscSetChipScsiID(iop_base, asc_dvc->cfg->chip_scsi_id) !=
9657 asc_dvc->cfg->chip_scsi_id) {
9658 asc_dvc->err_code |= ASC_IERR_SET_SCSI_ID;
9659 }
9660 #ifdef CONFIG_ISA
9661 if (asc_dvc->bus_type & ASC_IS_ISA) {
9662 AscSetIsaDmaChannel(iop_base, asc_dvc->cfg->isa_dma_channel);
9663 AscSetIsaDmaSpeed(iop_base, asc_dvc->cfg->isa_dma_speed);
9664 }
9665 #endif /* CONFIG_ISA */
9666
9667 asc_dvc->init_state |= ASC_INIT_STATE_END_SET_CFG;
9668
9669 switch (warn_code) {
9670 case 0: /* No error. */
9671 break;
9672 case ASC_WARN_IO_PORT_ROTATE:
9673 shost_printk(KERN_WARNING, shost, "I/O port address "
9674 "modified\n");
9675 break;
9676 case ASC_WARN_AUTO_CONFIG:
9677 shost_printk(KERN_WARNING, shost, "I/O port increment switch "
9678 "enabled\n");
9679 break;
9680 case ASC_WARN_EEPROM_CHKSUM:
9681 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
9682 break;
9683 case ASC_WARN_IRQ_MODIFIED:
9684 shost_printk(KERN_WARNING, shost, "IRQ modified\n");
9685 break;
9686 case ASC_WARN_CMD_QNG_CONFLICT:
9687 shost_printk(KERN_WARNING, shost, "tag queuing w/o "
9688 "disconnects\n");
9689 break;
9690 default:
9691 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
9692 warn_code);
9693 break;
9694 }
9695
9696 if (asc_dvc->err_code != 0)
9697 shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
9698 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
9699
9700 return asc_dvc->err_code;
9701 }
9702
9703 /*
9704 * EEPROM Configuration.
9705 *
9706 * All drivers should use this structure to set the default EEPROM
9707 * configuration. The BIOS now uses this structure when it is built.
9708 * Additional structure information can be found in a_condor.h where
9709 * the structure is defined.
9710 *
9711 * The *_Field_IsChar structs are needed to correct for endianness.
9712 * These values are read from the board 16 bits at a time directly
9713 * into the structs. Because some fields are char, the values will be
9714 * in the wrong order. The *_Field_IsChar tells when to flip the
9715 * bytes. Data read and written to PCI memory is automatically swapped
9716 * on big-endian platforms so char fields read as words are actually being
9717 * unswapped on big-endian platforms.
9718 */
9719 static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config = {
9720 ADV_EEPROM_BIOS_ENABLE, /* cfg_lsw */
9721 0x0000, /* cfg_msw */
9722 0xFFFF, /* disc_enable */
9723 0xFFFF, /* wdtr_able */
9724 0xFFFF, /* sdtr_able */
9725 0xFFFF, /* start_motor */
9726 0xFFFF, /* tagqng_able */
9727 0xFFFF, /* bios_scan */
9728 0, /* scam_tolerant */
9729 7, /* adapter_scsi_id */
9730 0, /* bios_boot_delay */
9731 3, /* scsi_reset_delay */
9732 0, /* bios_id_lun */
9733 0, /* termination */
9734 0, /* reserved1 */
9735 0xFFE7, /* bios_ctrl */
9736 0xFFFF, /* ultra_able */
9737 0, /* reserved2 */
9738 ASC_DEF_MAX_HOST_QNG, /* max_host_qng */
9739 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
9740 0, /* dvc_cntl */
9741 0, /* bug_fix */
9742 0, /* serial_number_word1 */
9743 0, /* serial_number_word2 */
9744 0, /* serial_number_word3 */
9745 0, /* check_sum */
9746 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
9747 , /* oem_name[16] */
9748 0, /* dvc_err_code */
9749 0, /* adv_err_code */
9750 0, /* adv_err_addr */
9751 0, /* saved_dvc_err_code */
9752 0, /* saved_adv_err_code */
9753 0, /* saved_adv_err_addr */
9754 0 /* num_of_err */
9755 };
9756
9757 static ADVEEP_3550_CONFIG ADVEEP_3550_Config_Field_IsChar = {
9758 0, /* cfg_lsw */
9759 0, /* cfg_msw */
9760 0, /* -disc_enable */
9761 0, /* wdtr_able */
9762 0, /* sdtr_able */
9763 0, /* start_motor */
9764 0, /* tagqng_able */
9765 0, /* bios_scan */
9766 0, /* scam_tolerant */
9767 1, /* adapter_scsi_id */
9768 1, /* bios_boot_delay */
9769 1, /* scsi_reset_delay */
9770 1, /* bios_id_lun */
9771 1, /* termination */
9772 1, /* reserved1 */
9773 0, /* bios_ctrl */
9774 0, /* ultra_able */
9775 0, /* reserved2 */
9776 1, /* max_host_qng */
9777 1, /* max_dvc_qng */
9778 0, /* dvc_cntl */
9779 0, /* bug_fix */
9780 0, /* serial_number_word1 */
9781 0, /* serial_number_word2 */
9782 0, /* serial_number_word3 */
9783 0, /* check_sum */
9784 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
9785 , /* oem_name[16] */
9786 0, /* dvc_err_code */
9787 0, /* adv_err_code */
9788 0, /* adv_err_addr */
9789 0, /* saved_dvc_err_code */
9790 0, /* saved_adv_err_code */
9791 0, /* saved_adv_err_addr */
9792 0 /* num_of_err */
9793 };
9794
9795 static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config = {
9796 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
9797 0x0000, /* 01 cfg_msw */
9798 0xFFFF, /* 02 disc_enable */
9799 0xFFFF, /* 03 wdtr_able */
9800 0x4444, /* 04 sdtr_speed1 */
9801 0xFFFF, /* 05 start_motor */
9802 0xFFFF, /* 06 tagqng_able */
9803 0xFFFF, /* 07 bios_scan */
9804 0, /* 08 scam_tolerant */
9805 7, /* 09 adapter_scsi_id */
9806 0, /* bios_boot_delay */
9807 3, /* 10 scsi_reset_delay */
9808 0, /* bios_id_lun */
9809 0, /* 11 termination_se */
9810 0, /* termination_lvd */
9811 0xFFE7, /* 12 bios_ctrl */
9812 0x4444, /* 13 sdtr_speed2 */
9813 0x4444, /* 14 sdtr_speed3 */
9814 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
9815 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
9816 0, /* 16 dvc_cntl */
9817 0x4444, /* 17 sdtr_speed4 */
9818 0, /* 18 serial_number_word1 */
9819 0, /* 19 serial_number_word2 */
9820 0, /* 20 serial_number_word3 */
9821 0, /* 21 check_sum */
9822 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
9823 , /* 22-29 oem_name[16] */
9824 0, /* 30 dvc_err_code */
9825 0, /* 31 adv_err_code */
9826 0, /* 32 adv_err_addr */
9827 0, /* 33 saved_dvc_err_code */
9828 0, /* 34 saved_adv_err_code */
9829 0, /* 35 saved_adv_err_addr */
9830 0, /* 36 reserved */
9831 0, /* 37 reserved */
9832 0, /* 38 reserved */
9833 0, /* 39 reserved */
9834 0, /* 40 reserved */
9835 0, /* 41 reserved */
9836 0, /* 42 reserved */
9837 0, /* 43 reserved */
9838 0, /* 44 reserved */
9839 0, /* 45 reserved */
9840 0, /* 46 reserved */
9841 0, /* 47 reserved */
9842 0, /* 48 reserved */
9843 0, /* 49 reserved */
9844 0, /* 50 reserved */
9845 0, /* 51 reserved */
9846 0, /* 52 reserved */
9847 0, /* 53 reserved */
9848 0, /* 54 reserved */
9849 0, /* 55 reserved */
9850 0, /* 56 cisptr_lsw */
9851 0, /* 57 cisprt_msw */
9852 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
9853 PCI_DEVICE_ID_38C0800_REV1, /* 59 subsysid */
9854 0, /* 60 reserved */
9855 0, /* 61 reserved */
9856 0, /* 62 reserved */
9857 0 /* 63 reserved */
9858 };
9859
9860 static ADVEEP_38C0800_CONFIG ADVEEP_38C0800_Config_Field_IsChar = {
9861 0, /* 00 cfg_lsw */
9862 0, /* 01 cfg_msw */
9863 0, /* 02 disc_enable */
9864 0, /* 03 wdtr_able */
9865 0, /* 04 sdtr_speed1 */
9866 0, /* 05 start_motor */
9867 0, /* 06 tagqng_able */
9868 0, /* 07 bios_scan */
9869 0, /* 08 scam_tolerant */
9870 1, /* 09 adapter_scsi_id */
9871 1, /* bios_boot_delay */
9872 1, /* 10 scsi_reset_delay */
9873 1, /* bios_id_lun */
9874 1, /* 11 termination_se */
9875 1, /* termination_lvd */
9876 0, /* 12 bios_ctrl */
9877 0, /* 13 sdtr_speed2 */
9878 0, /* 14 sdtr_speed3 */
9879 1, /* 15 max_host_qng */
9880 1, /* max_dvc_qng */
9881 0, /* 16 dvc_cntl */
9882 0, /* 17 sdtr_speed4 */
9883 0, /* 18 serial_number_word1 */
9884 0, /* 19 serial_number_word2 */
9885 0, /* 20 serial_number_word3 */
9886 0, /* 21 check_sum */
9887 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
9888 , /* 22-29 oem_name[16] */
9889 0, /* 30 dvc_err_code */
9890 0, /* 31 adv_err_code */
9891 0, /* 32 adv_err_addr */
9892 0, /* 33 saved_dvc_err_code */
9893 0, /* 34 saved_adv_err_code */
9894 0, /* 35 saved_adv_err_addr */
9895 0, /* 36 reserved */
9896 0, /* 37 reserved */
9897 0, /* 38 reserved */
9898 0, /* 39 reserved */
9899 0, /* 40 reserved */
9900 0, /* 41 reserved */
9901 0, /* 42 reserved */
9902 0, /* 43 reserved */
9903 0, /* 44 reserved */
9904 0, /* 45 reserved */
9905 0, /* 46 reserved */
9906 0, /* 47 reserved */
9907 0, /* 48 reserved */
9908 0, /* 49 reserved */
9909 0, /* 50 reserved */
9910 0, /* 51 reserved */
9911 0, /* 52 reserved */
9912 0, /* 53 reserved */
9913 0, /* 54 reserved */
9914 0, /* 55 reserved */
9915 0, /* 56 cisptr_lsw */
9916 0, /* 57 cisprt_msw */
9917 0, /* 58 subsysvid */
9918 0, /* 59 subsysid */
9919 0, /* 60 reserved */
9920 0, /* 61 reserved */
9921 0, /* 62 reserved */
9922 0 /* 63 reserved */
9923 };
9924
9925 static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config = {
9926 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
9927 0x0000, /* 01 cfg_msw */
9928 0xFFFF, /* 02 disc_enable */
9929 0xFFFF, /* 03 wdtr_able */
9930 0x5555, /* 04 sdtr_speed1 */
9931 0xFFFF, /* 05 start_motor */
9932 0xFFFF, /* 06 tagqng_able */
9933 0xFFFF, /* 07 bios_scan */
9934 0, /* 08 scam_tolerant */
9935 7, /* 09 adapter_scsi_id */
9936 0, /* bios_boot_delay */
9937 3, /* 10 scsi_reset_delay */
9938 0, /* bios_id_lun */
9939 0, /* 11 termination_se */
9940 0, /* termination_lvd */
9941 0xFFE7, /* 12 bios_ctrl */
9942 0x5555, /* 13 sdtr_speed2 */
9943 0x5555, /* 14 sdtr_speed3 */
9944 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
9945 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
9946 0, /* 16 dvc_cntl */
9947 0x5555, /* 17 sdtr_speed4 */
9948 0, /* 18 serial_number_word1 */
9949 0, /* 19 serial_number_word2 */
9950 0, /* 20 serial_number_word3 */
9951 0, /* 21 check_sum */
9952 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
9953 , /* 22-29 oem_name[16] */
9954 0, /* 30 dvc_err_code */
9955 0, /* 31 adv_err_code */
9956 0, /* 32 adv_err_addr */
9957 0, /* 33 saved_dvc_err_code */
9958 0, /* 34 saved_adv_err_code */
9959 0, /* 35 saved_adv_err_addr */
9960 0, /* 36 reserved */
9961 0, /* 37 reserved */
9962 0, /* 38 reserved */
9963 0, /* 39 reserved */
9964 0, /* 40 reserved */
9965 0, /* 41 reserved */
9966 0, /* 42 reserved */
9967 0, /* 43 reserved */
9968 0, /* 44 reserved */
9969 0, /* 45 reserved */
9970 0, /* 46 reserved */
9971 0, /* 47 reserved */
9972 0, /* 48 reserved */
9973 0, /* 49 reserved */
9974 0, /* 50 reserved */
9975 0, /* 51 reserved */
9976 0, /* 52 reserved */
9977 0, /* 53 reserved */
9978 0, /* 54 reserved */
9979 0, /* 55 reserved */
9980 0, /* 56 cisptr_lsw */
9981 0, /* 57 cisprt_msw */
9982 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
9983 PCI_DEVICE_ID_38C1600_REV1, /* 59 subsysid */
9984 0, /* 60 reserved */
9985 0, /* 61 reserved */
9986 0, /* 62 reserved */
9987 0 /* 63 reserved */
9988 };
9989
9990 static ADVEEP_38C1600_CONFIG ADVEEP_38C1600_Config_Field_IsChar = {
9991 0, /* 00 cfg_lsw */
9992 0, /* 01 cfg_msw */
9993 0, /* 02 disc_enable */
9994 0, /* 03 wdtr_able */
9995 0, /* 04 sdtr_speed1 */
9996 0, /* 05 start_motor */
9997 0, /* 06 tagqng_able */
9998 0, /* 07 bios_scan */
9999 0, /* 08 scam_tolerant */
10000 1, /* 09 adapter_scsi_id */
10001 1, /* bios_boot_delay */
10002 1, /* 10 scsi_reset_delay */
10003 1, /* bios_id_lun */
10004 1, /* 11 termination_se */
10005 1, /* termination_lvd */
10006 0, /* 12 bios_ctrl */
10007 0, /* 13 sdtr_speed2 */
10008 0, /* 14 sdtr_speed3 */
10009 1, /* 15 max_host_qng */
10010 1, /* max_dvc_qng */
10011 0, /* 16 dvc_cntl */
10012 0, /* 17 sdtr_speed4 */
10013 0, /* 18 serial_number_word1 */
10014 0, /* 19 serial_number_word2 */
10015 0, /* 20 serial_number_word3 */
10016 0, /* 21 check_sum */
10017 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
10018 , /* 22-29 oem_name[16] */
10019 0, /* 30 dvc_err_code */
10020 0, /* 31 adv_err_code */
10021 0, /* 32 adv_err_addr */
10022 0, /* 33 saved_dvc_err_code */
10023 0, /* 34 saved_adv_err_code */
10024 0, /* 35 saved_adv_err_addr */
10025 0, /* 36 reserved */
10026 0, /* 37 reserved */
10027 0, /* 38 reserved */
10028 0, /* 39 reserved */
10029 0, /* 40 reserved */
10030 0, /* 41 reserved */
10031 0, /* 42 reserved */
10032 0, /* 43 reserved */
10033 0, /* 44 reserved */
10034 0, /* 45 reserved */
10035 0, /* 46 reserved */
10036 0, /* 47 reserved */
10037 0, /* 48 reserved */
10038 0, /* 49 reserved */
10039 0, /* 50 reserved */
10040 0, /* 51 reserved */
10041 0, /* 52 reserved */
10042 0, /* 53 reserved */
10043 0, /* 54 reserved */
10044 0, /* 55 reserved */
10045 0, /* 56 cisptr_lsw */
10046 0, /* 57 cisprt_msw */
10047 0, /* 58 subsysvid */
10048 0, /* 59 subsysid */
10049 0, /* 60 reserved */
10050 0, /* 61 reserved */
10051 0, /* 62 reserved */
10052 0 /* 63 reserved */
10053 };
10054
10055 #ifdef CONFIG_PCI
10056 /*
10057 * Wait for EEPROM command to complete
10058 */
10059 static void AdvWaitEEPCmd(AdvPortAddr iop_base)
10060 {
10061 int eep_delay_ms;
10062
10063 for (eep_delay_ms = 0; eep_delay_ms < ADV_EEP_DELAY_MS; eep_delay_ms++) {
10064 if (AdvReadWordRegister(iop_base, IOPW_EE_CMD) &
10065 ASC_EEP_CMD_DONE) {
10066 break;
10067 }
10068 mdelay(1);
10069 }
10070 if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) ==
10071 0)
10072 BUG();
10073 }
10074
10075 /*
10076 * Read the EEPROM from specified location
10077 */
10078 static ushort AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr)
10079 {
10080 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10081 ASC_EEP_CMD_READ | eep_word_addr);
10082 AdvWaitEEPCmd(iop_base);
10083 return AdvReadWordRegister(iop_base, IOPW_EE_DATA);
10084 }
10085
10086 /*
10087 * Write the EEPROM from 'cfg_buf'.
10088 */
10089 static void AdvSet3550EEPConfig(AdvPortAddr iop_base,
10090 ADVEEP_3550_CONFIG *cfg_buf)
10091 {
10092 ushort *wbuf;
10093 ushort addr, chksum;
10094 ushort *charfields;
10095
10096 wbuf = (ushort *)cfg_buf;
10097 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
10098 chksum = 0;
10099
10100 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
10101 AdvWaitEEPCmd(iop_base);
10102
10103 /*
10104 * Write EEPROM from word 0 to word 20.
10105 */
10106 for (addr = ADV_EEP_DVC_CFG_BEGIN;
10107 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
10108 ushort word;
10109
10110 if (*charfields++) {
10111 word = cpu_to_le16(*wbuf);
10112 } else {
10113 word = *wbuf;
10114 }
10115 chksum += *wbuf; /* Checksum is calculated from word values. */
10116 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10117 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10118 ASC_EEP_CMD_WRITE | addr);
10119 AdvWaitEEPCmd(iop_base);
10120 mdelay(ADV_EEP_DELAY_MS);
10121 }
10122
10123 /*
10124 * Write EEPROM checksum at word 21.
10125 */
10126 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
10127 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
10128 AdvWaitEEPCmd(iop_base);
10129 wbuf++;
10130 charfields++;
10131
10132 /*
10133 * Write EEPROM OEM name at words 22 to 29.
10134 */
10135 for (addr = ADV_EEP_DVC_CTL_BEGIN;
10136 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
10137 ushort word;
10138
10139 if (*charfields++) {
10140 word = cpu_to_le16(*wbuf);
10141 } else {
10142 word = *wbuf;
10143 }
10144 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10145 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10146 ASC_EEP_CMD_WRITE | addr);
10147 AdvWaitEEPCmd(iop_base);
10148 }
10149 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
10150 AdvWaitEEPCmd(iop_base);
10151 }
10152
10153 /*
10154 * Write the EEPROM from 'cfg_buf'.
10155 */
10156 static void AdvSet38C0800EEPConfig(AdvPortAddr iop_base,
10157 ADVEEP_38C0800_CONFIG *cfg_buf)
10158 {
10159 ushort *wbuf;
10160 ushort *charfields;
10161 ushort addr, chksum;
10162
10163 wbuf = (ushort *)cfg_buf;
10164 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
10165 chksum = 0;
10166
10167 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
10168 AdvWaitEEPCmd(iop_base);
10169
10170 /*
10171 * Write EEPROM from word 0 to word 20.
10172 */
10173 for (addr = ADV_EEP_DVC_CFG_BEGIN;
10174 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
10175 ushort word;
10176
10177 if (*charfields++) {
10178 word = cpu_to_le16(*wbuf);
10179 } else {
10180 word = *wbuf;
10181 }
10182 chksum += *wbuf; /* Checksum is calculated from word values. */
10183 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10184 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10185 ASC_EEP_CMD_WRITE | addr);
10186 AdvWaitEEPCmd(iop_base);
10187 mdelay(ADV_EEP_DELAY_MS);
10188 }
10189
10190 /*
10191 * Write EEPROM checksum at word 21.
10192 */
10193 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
10194 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
10195 AdvWaitEEPCmd(iop_base);
10196 wbuf++;
10197 charfields++;
10198
10199 /*
10200 * Write EEPROM OEM name at words 22 to 29.
10201 */
10202 for (addr = ADV_EEP_DVC_CTL_BEGIN;
10203 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
10204 ushort word;
10205
10206 if (*charfields++) {
10207 word = cpu_to_le16(*wbuf);
10208 } else {
10209 word = *wbuf;
10210 }
10211 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10212 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10213 ASC_EEP_CMD_WRITE | addr);
10214 AdvWaitEEPCmd(iop_base);
10215 }
10216 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
10217 AdvWaitEEPCmd(iop_base);
10218 }
10219
10220 /*
10221 * Write the EEPROM from 'cfg_buf'.
10222 */
10223 static void AdvSet38C1600EEPConfig(AdvPortAddr iop_base,
10224 ADVEEP_38C1600_CONFIG *cfg_buf)
10225 {
10226 ushort *wbuf;
10227 ushort *charfields;
10228 ushort addr, chksum;
10229
10230 wbuf = (ushort *)cfg_buf;
10231 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
10232 chksum = 0;
10233
10234 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
10235 AdvWaitEEPCmd(iop_base);
10236
10237 /*
10238 * Write EEPROM from word 0 to word 20.
10239 */
10240 for (addr = ADV_EEP_DVC_CFG_BEGIN;
10241 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
10242 ushort word;
10243
10244 if (*charfields++) {
10245 word = cpu_to_le16(*wbuf);
10246 } else {
10247 word = *wbuf;
10248 }
10249 chksum += *wbuf; /* Checksum is calculated from word values. */
10250 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10251 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10252 ASC_EEP_CMD_WRITE | addr);
10253 AdvWaitEEPCmd(iop_base);
10254 mdelay(ADV_EEP_DELAY_MS);
10255 }
10256
10257 /*
10258 * Write EEPROM checksum at word 21.
10259 */
10260 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
10261 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
10262 AdvWaitEEPCmd(iop_base);
10263 wbuf++;
10264 charfields++;
10265
10266 /*
10267 * Write EEPROM OEM name at words 22 to 29.
10268 */
10269 for (addr = ADV_EEP_DVC_CTL_BEGIN;
10270 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
10271 ushort word;
10272
10273 if (*charfields++) {
10274 word = cpu_to_le16(*wbuf);
10275 } else {
10276 word = *wbuf;
10277 }
10278 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10279 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10280 ASC_EEP_CMD_WRITE | addr);
10281 AdvWaitEEPCmd(iop_base);
10282 }
10283 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
10284 AdvWaitEEPCmd(iop_base);
10285 }
10286
10287 /*
10288 * Read EEPROM configuration into the specified buffer.
10289 *
10290 * Return a checksum based on the EEPROM configuration read.
10291 */
10292 static ushort AdvGet3550EEPConfig(AdvPortAddr iop_base,
10293 ADVEEP_3550_CONFIG *cfg_buf)
10294 {
10295 ushort wval, chksum;
10296 ushort *wbuf;
10297 int eep_addr;
10298 ushort *charfields;
10299
10300 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
10301 wbuf = (ushort *)cfg_buf;
10302 chksum = 0;
10303
10304 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10305 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10306 wval = AdvReadEEPWord(iop_base, eep_addr);
10307 chksum += wval; /* Checksum is calculated from word values. */
10308 if (*charfields++) {
10309 *wbuf = le16_to_cpu(wval);
10310 } else {
10311 *wbuf = wval;
10312 }
10313 }
10314 /* Read checksum word. */
10315 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10316 wbuf++;
10317 charfields++;
10318
10319 /* Read rest of EEPROM not covered by the checksum. */
10320 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10321 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10322 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10323 if (*charfields++) {
10324 *wbuf = le16_to_cpu(*wbuf);
10325 }
10326 }
10327 return chksum;
10328 }
10329
10330 /*
10331 * Read EEPROM configuration into the specified buffer.
10332 *
10333 * Return a checksum based on the EEPROM configuration read.
10334 */
10335 static ushort AdvGet38C0800EEPConfig(AdvPortAddr iop_base,
10336 ADVEEP_38C0800_CONFIG *cfg_buf)
10337 {
10338 ushort wval, chksum;
10339 ushort *wbuf;
10340 int eep_addr;
10341 ushort *charfields;
10342
10343 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
10344 wbuf = (ushort *)cfg_buf;
10345 chksum = 0;
10346
10347 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10348 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10349 wval = AdvReadEEPWord(iop_base, eep_addr);
10350 chksum += wval; /* Checksum is calculated from word values. */
10351 if (*charfields++) {
10352 *wbuf = le16_to_cpu(wval);
10353 } else {
10354 *wbuf = wval;
10355 }
10356 }
10357 /* Read checksum word. */
10358 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10359 wbuf++;
10360 charfields++;
10361
10362 /* Read rest of EEPROM not covered by the checksum. */
10363 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10364 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10365 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10366 if (*charfields++) {
10367 *wbuf = le16_to_cpu(*wbuf);
10368 }
10369 }
10370 return chksum;
10371 }
10372
10373 /*
10374 * Read EEPROM configuration into the specified buffer.
10375 *
10376 * Return a checksum based on the EEPROM configuration read.
10377 */
10378 static ushort AdvGet38C1600EEPConfig(AdvPortAddr iop_base,
10379 ADVEEP_38C1600_CONFIG *cfg_buf)
10380 {
10381 ushort wval, chksum;
10382 ushort *wbuf;
10383 int eep_addr;
10384 ushort *charfields;
10385
10386 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
10387 wbuf = (ushort *)cfg_buf;
10388 chksum = 0;
10389
10390 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10391 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10392 wval = AdvReadEEPWord(iop_base, eep_addr);
10393 chksum += wval; /* Checksum is calculated from word values. */
10394 if (*charfields++) {
10395 *wbuf = le16_to_cpu(wval);
10396 } else {
10397 *wbuf = wval;
10398 }
10399 }
10400 /* Read checksum word. */
10401 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10402 wbuf++;
10403 charfields++;
10404
10405 /* Read rest of EEPROM not covered by the checksum. */
10406 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10407 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10408 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10409 if (*charfields++) {
10410 *wbuf = le16_to_cpu(*wbuf);
10411 }
10412 }
10413 return chksum;
10414 }
10415
10416 /*
10417 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
10418 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
10419 * all of this is done.
10420 *
10421 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
10422 *
10423 * For a non-fatal error return a warning code. If there are no warnings
10424 * then 0 is returned.
10425 *
10426 * Note: Chip is stopped on entry.
10427 */
10428 static int AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc)
10429 {
10430 AdvPortAddr iop_base;
10431 ushort warn_code;
10432 ADVEEP_3550_CONFIG eep_config;
10433
10434 iop_base = asc_dvc->iop_base;
10435
10436 warn_code = 0;
10437
10438 /*
10439 * Read the board's EEPROM configuration.
10440 *
10441 * Set default values if a bad checksum is found.
10442 */
10443 if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum) {
10444 warn_code |= ASC_WARN_EEPROM_CHKSUM;
10445
10446 /*
10447 * Set EEPROM default values.
10448 */
10449 memcpy(&eep_config, &Default_3550_EEPROM_Config,
10450 sizeof(ADVEEP_3550_CONFIG));
10451
10452 /*
10453 * Assume the 6 byte board serial number that was read from
10454 * EEPROM is correct even if the EEPROM checksum failed.
10455 */
10456 eep_config.serial_number_word3 =
10457 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
10458
10459 eep_config.serial_number_word2 =
10460 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
10461
10462 eep_config.serial_number_word1 =
10463 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
10464
10465 AdvSet3550EEPConfig(iop_base, &eep_config);
10466 }
10467 /*
10468 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
10469 * EEPROM configuration that was read.
10470 *
10471 * This is the mapping of EEPROM fields to Adv Library fields.
10472 */
10473 asc_dvc->wdtr_able = eep_config.wdtr_able;
10474 asc_dvc->sdtr_able = eep_config.sdtr_able;
10475 asc_dvc->ultra_able = eep_config.ultra_able;
10476 asc_dvc->tagqng_able = eep_config.tagqng_able;
10477 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10478 asc_dvc->max_host_qng = eep_config.max_host_qng;
10479 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10480 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
10481 asc_dvc->start_motor = eep_config.start_motor;
10482 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10483 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10484 asc_dvc->no_scam = eep_config.scam_tolerant;
10485 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
10486 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
10487 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
10488
10489 /*
10490 * Set the host maximum queuing (max. 253, min. 16) and the per device
10491 * maximum queuing (max. 63, min. 4).
10492 */
10493 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10494 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10495 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10496 /* If the value is zero, assume it is uninitialized. */
10497 if (eep_config.max_host_qng == 0) {
10498 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10499 } else {
10500 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
10501 }
10502 }
10503
10504 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10505 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10506 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10507 /* If the value is zero, assume it is uninitialized. */
10508 if (eep_config.max_dvc_qng == 0) {
10509 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10510 } else {
10511 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10512 }
10513 }
10514
10515 /*
10516 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10517 * set 'max_dvc_qng' to 'max_host_qng'.
10518 */
10519 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10520 eep_config.max_dvc_qng = eep_config.max_host_qng;
10521 }
10522
10523 /*
10524 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
10525 * values based on possibly adjusted EEPROM values.
10526 */
10527 asc_dvc->max_host_qng = eep_config.max_host_qng;
10528 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10529
10530 /*
10531 * If the EEPROM 'termination' field is set to automatic (0), then set
10532 * the ADV_DVC_CFG 'termination' field to automatic also.
10533 *
10534 * If the termination is specified with a non-zero 'termination'
10535 * value check that a legal value is set and set the ADV_DVC_CFG
10536 * 'termination' field appropriately.
10537 */
10538 if (eep_config.termination == 0) {
10539 asc_dvc->cfg->termination = 0; /* auto termination */
10540 } else {
10541 /* Enable manual control with low off / high off. */
10542 if (eep_config.termination == 1) {
10543 asc_dvc->cfg->termination = TERM_CTL_SEL;
10544
10545 /* Enable manual control with low off / high on. */
10546 } else if (eep_config.termination == 2) {
10547 asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H;
10548
10549 /* Enable manual control with low on / high on. */
10550 } else if (eep_config.termination == 3) {
10551 asc_dvc->cfg->termination =
10552 TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L;
10553 } else {
10554 /*
10555 * The EEPROM 'termination' field contains a bad value. Use
10556 * automatic termination instead.
10557 */
10558 asc_dvc->cfg->termination = 0;
10559 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10560 }
10561 }
10562
10563 return warn_code;
10564 }
10565
10566 /*
10567 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
10568 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
10569 * all of this is done.
10570 *
10571 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
10572 *
10573 * For a non-fatal error return a warning code. If there are no warnings
10574 * then 0 is returned.
10575 *
10576 * Note: Chip is stopped on entry.
10577 */
10578 static int AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc)
10579 {
10580 AdvPortAddr iop_base;
10581 ushort warn_code;
10582 ADVEEP_38C0800_CONFIG eep_config;
10583 uchar tid, termination;
10584 ushort sdtr_speed = 0;
10585
10586 iop_base = asc_dvc->iop_base;
10587
10588 warn_code = 0;
10589
10590 /*
10591 * Read the board's EEPROM configuration.
10592 *
10593 * Set default values if a bad checksum is found.
10594 */
10595 if (AdvGet38C0800EEPConfig(iop_base, &eep_config) !=
10596 eep_config.check_sum) {
10597 warn_code |= ASC_WARN_EEPROM_CHKSUM;
10598
10599 /*
10600 * Set EEPROM default values.
10601 */
10602 memcpy(&eep_config, &Default_38C0800_EEPROM_Config,
10603 sizeof(ADVEEP_38C0800_CONFIG));
10604
10605 /*
10606 * Assume the 6 byte board serial number that was read from
10607 * EEPROM is correct even if the EEPROM checksum failed.
10608 */
10609 eep_config.serial_number_word3 =
10610 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
10611
10612 eep_config.serial_number_word2 =
10613 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
10614
10615 eep_config.serial_number_word1 =
10616 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
10617
10618 AdvSet38C0800EEPConfig(iop_base, &eep_config);
10619 }
10620 /*
10621 * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the
10622 * EEPROM configuration that was read.
10623 *
10624 * This is the mapping of EEPROM fields to Adv Library fields.
10625 */
10626 asc_dvc->wdtr_able = eep_config.wdtr_able;
10627 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
10628 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
10629 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
10630 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
10631 asc_dvc->tagqng_able = eep_config.tagqng_able;
10632 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10633 asc_dvc->max_host_qng = eep_config.max_host_qng;
10634 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10635 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
10636 asc_dvc->start_motor = eep_config.start_motor;
10637 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10638 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10639 asc_dvc->no_scam = eep_config.scam_tolerant;
10640 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
10641 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
10642 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
10643
10644 /*
10645 * For every Target ID if any of its 'sdtr_speed[1234]' bits
10646 * are set, then set an 'sdtr_able' bit for it.
10647 */
10648 asc_dvc->sdtr_able = 0;
10649 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
10650 if (tid == 0) {
10651 sdtr_speed = asc_dvc->sdtr_speed1;
10652 } else if (tid == 4) {
10653 sdtr_speed = asc_dvc->sdtr_speed2;
10654 } else if (tid == 8) {
10655 sdtr_speed = asc_dvc->sdtr_speed3;
10656 } else if (tid == 12) {
10657 sdtr_speed = asc_dvc->sdtr_speed4;
10658 }
10659 if (sdtr_speed & ADV_MAX_TID) {
10660 asc_dvc->sdtr_able |= (1 << tid);
10661 }
10662 sdtr_speed >>= 4;
10663 }
10664
10665 /*
10666 * Set the host maximum queuing (max. 253, min. 16) and the per device
10667 * maximum queuing (max. 63, min. 4).
10668 */
10669 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10670 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10671 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10672 /* If the value is zero, assume it is uninitialized. */
10673 if (eep_config.max_host_qng == 0) {
10674 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10675 } else {
10676 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
10677 }
10678 }
10679
10680 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10681 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10682 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10683 /* If the value is zero, assume it is uninitialized. */
10684 if (eep_config.max_dvc_qng == 0) {
10685 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10686 } else {
10687 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10688 }
10689 }
10690
10691 /*
10692 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10693 * set 'max_dvc_qng' to 'max_host_qng'.
10694 */
10695 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10696 eep_config.max_dvc_qng = eep_config.max_host_qng;
10697 }
10698
10699 /*
10700 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
10701 * values based on possibly adjusted EEPROM values.
10702 */
10703 asc_dvc->max_host_qng = eep_config.max_host_qng;
10704 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10705
10706 /*
10707 * If the EEPROM 'termination' field is set to automatic (0), then set
10708 * the ADV_DVC_CFG 'termination' field to automatic also.
10709 *
10710 * If the termination is specified with a non-zero 'termination'
10711 * value check that a legal value is set and set the ADV_DVC_CFG
10712 * 'termination' field appropriately.
10713 */
10714 if (eep_config.termination_se == 0) {
10715 termination = 0; /* auto termination for SE */
10716 } else {
10717 /* Enable manual control with low off / high off. */
10718 if (eep_config.termination_se == 1) {
10719 termination = 0;
10720
10721 /* Enable manual control with low off / high on. */
10722 } else if (eep_config.termination_se == 2) {
10723 termination = TERM_SE_HI;
10724
10725 /* Enable manual control with low on / high on. */
10726 } else if (eep_config.termination_se == 3) {
10727 termination = TERM_SE;
10728 } else {
10729 /*
10730 * The EEPROM 'termination_se' field contains a bad value.
10731 * Use automatic termination instead.
10732 */
10733 termination = 0;
10734 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10735 }
10736 }
10737
10738 if (eep_config.termination_lvd == 0) {
10739 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
10740 } else {
10741 /* Enable manual control with low off / high off. */
10742 if (eep_config.termination_lvd == 1) {
10743 asc_dvc->cfg->termination = termination;
10744
10745 /* Enable manual control with low off / high on. */
10746 } else if (eep_config.termination_lvd == 2) {
10747 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
10748
10749 /* Enable manual control with low on / high on. */
10750 } else if (eep_config.termination_lvd == 3) {
10751 asc_dvc->cfg->termination = termination | TERM_LVD;
10752 } else {
10753 /*
10754 * The EEPROM 'termination_lvd' field contains a bad value.
10755 * Use automatic termination instead.
10756 */
10757 asc_dvc->cfg->termination = termination;
10758 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10759 }
10760 }
10761
10762 return warn_code;
10763 }
10764
10765 /*
10766 * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and
10767 * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while
10768 * all of this is done.
10769 *
10770 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
10771 *
10772 * For a non-fatal error return a warning code. If there are no warnings
10773 * then 0 is returned.
10774 *
10775 * Note: Chip is stopped on entry.
10776 */
10777 static int AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc)
10778 {
10779 AdvPortAddr iop_base;
10780 ushort warn_code;
10781 ADVEEP_38C1600_CONFIG eep_config;
10782 uchar tid, termination;
10783 ushort sdtr_speed = 0;
10784
10785 iop_base = asc_dvc->iop_base;
10786
10787 warn_code = 0;
10788
10789 /*
10790 * Read the board's EEPROM configuration.
10791 *
10792 * Set default values if a bad checksum is found.
10793 */
10794 if (AdvGet38C1600EEPConfig(iop_base, &eep_config) !=
10795 eep_config.check_sum) {
10796 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
10797 warn_code |= ASC_WARN_EEPROM_CHKSUM;
10798
10799 /*
10800 * Set EEPROM default values.
10801 */
10802 memcpy(&eep_config, &Default_38C1600_EEPROM_Config,
10803 sizeof(ADVEEP_38C1600_CONFIG));
10804
10805 if (PCI_FUNC(pdev->devfn) != 0) {
10806 u8 ints;
10807 /*
10808 * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60
10809 * and old Mac system booting problem. The Expansion
10810 * ROM must be disabled in Function 1 for these systems
10811 */
10812 eep_config.cfg_lsw &= ~ADV_EEPROM_BIOS_ENABLE;
10813 /*
10814 * Clear the INTAB (bit 11) if the GPIO 0 input
10815 * indicates the Function 1 interrupt line is wired
10816 * to INTB.
10817 *
10818 * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input:
10819 * 1 - Function 1 interrupt line wired to INT A.
10820 * 0 - Function 1 interrupt line wired to INT B.
10821 *
10822 * Note: Function 0 is always wired to INTA.
10823 * Put all 5 GPIO bits in input mode and then read
10824 * their input values.
10825 */
10826 AdvWriteByteRegister(iop_base, IOPB_GPIO_CNTL, 0);
10827 ints = AdvReadByteRegister(iop_base, IOPB_GPIO_DATA);
10828 if ((ints & 0x01) == 0)
10829 eep_config.cfg_lsw &= ~ADV_EEPROM_INTAB;
10830 }
10831
10832 /*
10833 * Assume the 6 byte board serial number that was read from
10834 * EEPROM is correct even if the EEPROM checksum failed.
10835 */
10836 eep_config.serial_number_word3 =
10837 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
10838 eep_config.serial_number_word2 =
10839 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
10840 eep_config.serial_number_word1 =
10841 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
10842
10843 AdvSet38C1600EEPConfig(iop_base, &eep_config);
10844 }
10845
10846 /*
10847 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
10848 * EEPROM configuration that was read.
10849 *
10850 * This is the mapping of EEPROM fields to Adv Library fields.
10851 */
10852 asc_dvc->wdtr_able = eep_config.wdtr_able;
10853 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
10854 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
10855 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
10856 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
10857 asc_dvc->ppr_able = 0;
10858 asc_dvc->tagqng_able = eep_config.tagqng_able;
10859 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10860 asc_dvc->max_host_qng = eep_config.max_host_qng;
10861 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10862 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ASC_MAX_TID);
10863 asc_dvc->start_motor = eep_config.start_motor;
10864 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10865 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10866 asc_dvc->no_scam = eep_config.scam_tolerant;
10867
10868 /*
10869 * For every Target ID if any of its 'sdtr_speed[1234]' bits
10870 * are set, then set an 'sdtr_able' bit for it.
10871 */
10872 asc_dvc->sdtr_able = 0;
10873 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
10874 if (tid == 0) {
10875 sdtr_speed = asc_dvc->sdtr_speed1;
10876 } else if (tid == 4) {
10877 sdtr_speed = asc_dvc->sdtr_speed2;
10878 } else if (tid == 8) {
10879 sdtr_speed = asc_dvc->sdtr_speed3;
10880 } else if (tid == 12) {
10881 sdtr_speed = asc_dvc->sdtr_speed4;
10882 }
10883 if (sdtr_speed & ASC_MAX_TID) {
10884 asc_dvc->sdtr_able |= (1 << tid);
10885 }
10886 sdtr_speed >>= 4;
10887 }
10888
10889 /*
10890 * Set the host maximum queuing (max. 253, min. 16) and the per device
10891 * maximum queuing (max. 63, min. 4).
10892 */
10893 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10894 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10895 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10896 /* If the value is zero, assume it is uninitialized. */
10897 if (eep_config.max_host_qng == 0) {
10898 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10899 } else {
10900 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
10901 }
10902 }
10903
10904 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10905 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10906 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10907 /* If the value is zero, assume it is uninitialized. */
10908 if (eep_config.max_dvc_qng == 0) {
10909 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10910 } else {
10911 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10912 }
10913 }
10914
10915 /*
10916 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10917 * set 'max_dvc_qng' to 'max_host_qng'.
10918 */
10919 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10920 eep_config.max_dvc_qng = eep_config.max_host_qng;
10921 }
10922
10923 /*
10924 * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng'
10925 * values based on possibly adjusted EEPROM values.
10926 */
10927 asc_dvc->max_host_qng = eep_config.max_host_qng;
10928 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10929
10930 /*
10931 * If the EEPROM 'termination' field is set to automatic (0), then set
10932 * the ASC_DVC_CFG 'termination' field to automatic also.
10933 *
10934 * If the termination is specified with a non-zero 'termination'
10935 * value check that a legal value is set and set the ASC_DVC_CFG
10936 * 'termination' field appropriately.
10937 */
10938 if (eep_config.termination_se == 0) {
10939 termination = 0; /* auto termination for SE */
10940 } else {
10941 /* Enable manual control with low off / high off. */
10942 if (eep_config.termination_se == 1) {
10943 termination = 0;
10944
10945 /* Enable manual control with low off / high on. */
10946 } else if (eep_config.termination_se == 2) {
10947 termination = TERM_SE_HI;
10948
10949 /* Enable manual control with low on / high on. */
10950 } else if (eep_config.termination_se == 3) {
10951 termination = TERM_SE;
10952 } else {
10953 /*
10954 * The EEPROM 'termination_se' field contains a bad value.
10955 * Use automatic termination instead.
10956 */
10957 termination = 0;
10958 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10959 }
10960 }
10961
10962 if (eep_config.termination_lvd == 0) {
10963 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
10964 } else {
10965 /* Enable manual control with low off / high off. */
10966 if (eep_config.termination_lvd == 1) {
10967 asc_dvc->cfg->termination = termination;
10968
10969 /* Enable manual control with low off / high on. */
10970 } else if (eep_config.termination_lvd == 2) {
10971 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
10972
10973 /* Enable manual control with low on / high on. */
10974 } else if (eep_config.termination_lvd == 3) {
10975 asc_dvc->cfg->termination = termination | TERM_LVD;
10976 } else {
10977 /*
10978 * The EEPROM 'termination_lvd' field contains a bad value.
10979 * Use automatic termination instead.
10980 */
10981 asc_dvc->cfg->termination = termination;
10982 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10983 }
10984 }
10985
10986 return warn_code;
10987 }
10988
10989 /*
10990 * Initialize the ADV_DVC_VAR structure.
10991 *
10992 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
10993 *
10994 * For a non-fatal error return a warning code. If there are no warnings
10995 * then 0 is returned.
10996 */
10997 static int AdvInitGetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
10998 {
10999 struct asc_board *board = shost_priv(shost);
11000 ADV_DVC_VAR *asc_dvc = &board->dvc_var.adv_dvc_var;
11001 unsigned short warn_code = 0;
11002 AdvPortAddr iop_base = asc_dvc->iop_base;
11003 u16 cmd;
11004 int status;
11005
11006 asc_dvc->err_code = 0;
11007
11008 /*
11009 * Save the state of the PCI Configuration Command Register
11010 * "Parity Error Response Control" Bit. If the bit is clear (0),
11011 * in AdvInitAsc3550/38C0800Driver() tell the microcode to ignore
11012 * DMA parity errors.
11013 */
11014 asc_dvc->cfg->control_flag = 0;
11015 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
11016 if ((cmd & PCI_COMMAND_PARITY) == 0)
11017 asc_dvc->cfg->control_flag |= CONTROL_FLAG_IGNORE_PERR;
11018
11019 asc_dvc->cfg->chip_version =
11020 AdvGetChipVersion(iop_base, asc_dvc->bus_type);
11021
11022 ASC_DBG(1, "iopb_chip_id_1: 0x%x 0x%x\n",
11023 (ushort)AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1),
11024 (ushort)ADV_CHIP_ID_BYTE);
11025
11026 ASC_DBG(1, "iopw_chip_id_0: 0x%x 0x%x\n",
11027 (ushort)AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0),
11028 (ushort)ADV_CHIP_ID_WORD);
11029
11030 /*
11031 * Reset the chip to start and allow register writes.
11032 */
11033 if (AdvFindSignature(iop_base) == 0) {
11034 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
11035 return ADV_ERROR;
11036 } else {
11037 /*
11038 * The caller must set 'chip_type' to a valid setting.
11039 */
11040 if (asc_dvc->chip_type != ADV_CHIP_ASC3550 &&
11041 asc_dvc->chip_type != ADV_CHIP_ASC38C0800 &&
11042 asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
11043 asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE;
11044 return ADV_ERROR;
11045 }
11046
11047 /*
11048 * Reset Chip.
11049 */
11050 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
11051 ADV_CTRL_REG_CMD_RESET);
11052 mdelay(100);
11053 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
11054 ADV_CTRL_REG_CMD_WR_IO_REG);
11055
11056 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
11057 status = AdvInitFrom38C1600EEP(asc_dvc);
11058 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
11059 status = AdvInitFrom38C0800EEP(asc_dvc);
11060 } else {
11061 status = AdvInitFrom3550EEP(asc_dvc);
11062 }
11063 warn_code |= status;
11064 }
11065
11066 if (warn_code != 0)
11067 shost_printk(KERN_WARNING, shost, "warning: 0x%x\n", warn_code);
11068
11069 if (asc_dvc->err_code)
11070 shost_printk(KERN_ERR, shost, "error code 0x%x\n",
11071 asc_dvc->err_code);
11072
11073 return asc_dvc->err_code;
11074 }
11075 #endif
11076
11077 static struct scsi_host_template advansys_template = {
11078 .proc_name = DRV_NAME,
11079 #ifdef CONFIG_PROC_FS
11080 .show_info = advansys_show_info,
11081 #endif
11082 .name = DRV_NAME,
11083 .info = advansys_info,
11084 .queuecommand = advansys_queuecommand,
11085 .eh_host_reset_handler = advansys_reset,
11086 .bios_param = advansys_biosparam,
11087 .slave_configure = advansys_slave_configure,
11088 /*
11089 * Because the driver may control an ISA adapter 'unchecked_isa_dma'
11090 * must be set. The flag will be cleared in advansys_board_found
11091 * for non-ISA adapters.
11092 */
11093 .unchecked_isa_dma = true,
11094 /*
11095 * All adapters controlled by this driver are capable of large
11096 * scatter-gather lists. According to the mid-level SCSI documentation
11097 * this obviates any performance gain provided by setting
11098 * 'use_clustering'. But empirically while CPU utilization is increased
11099 * by enabling clustering, I/O throughput increases as well.
11100 */
11101 .use_clustering = ENABLE_CLUSTERING,
11102 .use_blk_tags = 1,
11103 };
11104
11105 static int advansys_wide_init_chip(struct Scsi_Host *shost)
11106 {
11107 struct asc_board *board = shost_priv(shost);
11108 struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
11109 size_t sgblk_pool_size;
11110 int warn_code, err_code;
11111
11112 /*
11113 * Allocate buffer carrier structures. The total size
11114 * is about 8 KB, so allocate all at once.
11115 */
11116 adv_dvc->carrier = dma_alloc_coherent(board->dev,
11117 ADV_CARRIER_BUFSIZE, &adv_dvc->carrier_addr, GFP_KERNEL);
11118 ASC_DBG(1, "carrier 0x%p\n", adv_dvc->carrier);
11119
11120 if (!adv_dvc->carrier)
11121 goto kmalloc_failed;
11122
11123 /*
11124 * Allocate up to 'max_host_qng' request structures for the Wide
11125 * board. The total size is about 16 KB, so allocate all at once.
11126 * If the allocation fails decrement and try again.
11127 */
11128 board->adv_reqp_size = adv_dvc->max_host_qng * sizeof(adv_req_t);
11129 if (board->adv_reqp_size & 0x1f) {
11130 ASC_DBG(1, "unaligned reqp %lu bytes\n", sizeof(adv_req_t));
11131 board->adv_reqp_size = ADV_32BALIGN(board->adv_reqp_size);
11132 }
11133 board->adv_reqp = dma_alloc_coherent(board->dev, board->adv_reqp_size,
11134 &board->adv_reqp_addr, GFP_KERNEL);
11135
11136 if (!board->adv_reqp)
11137 goto kmalloc_failed;
11138
11139 ASC_DBG(1, "reqp 0x%p, req_cnt %d, bytes %lu\n", board->adv_reqp,
11140 adv_dvc->max_host_qng, board->adv_reqp_size);
11141
11142 /*
11143 * Allocate up to ADV_TOT_SG_BLOCK request structures for
11144 * the Wide board. Each structure is about 136 bytes.
11145 */
11146 sgblk_pool_size = sizeof(adv_sgblk_t) * ADV_TOT_SG_BLOCK;
11147 board->adv_sgblk_pool = dma_pool_create("adv_sgblk", board->dev,
11148 sgblk_pool_size, 32, 0);
11149
11150 ASC_DBG(1, "sg_cnt %d * %lu = %lu bytes\n", ADV_TOT_SG_BLOCK,
11151 sizeof(adv_sgblk_t), sgblk_pool_size);
11152
11153 if (!board->adv_sgblk_pool)
11154 goto kmalloc_failed;
11155
11156 if (adv_dvc->chip_type == ADV_CHIP_ASC3550) {
11157 ASC_DBG(2, "AdvInitAsc3550Driver()\n");
11158 warn_code = AdvInitAsc3550Driver(adv_dvc);
11159 } else if (adv_dvc->chip_type == ADV_CHIP_ASC38C0800) {
11160 ASC_DBG(2, "AdvInitAsc38C0800Driver()\n");
11161 warn_code = AdvInitAsc38C0800Driver(adv_dvc);
11162 } else {
11163 ASC_DBG(2, "AdvInitAsc38C1600Driver()\n");
11164 warn_code = AdvInitAsc38C1600Driver(adv_dvc);
11165 }
11166 err_code = adv_dvc->err_code;
11167
11168 if (warn_code || err_code) {
11169 shost_printk(KERN_WARNING, shost, "error: warn 0x%x, error "
11170 "0x%x\n", warn_code, err_code);
11171 }
11172
11173 goto exit;
11174
11175 kmalloc_failed:
11176 shost_printk(KERN_ERR, shost, "error: kmalloc() failed\n");
11177 err_code = ADV_ERROR;
11178 exit:
11179 return err_code;
11180 }
11181
11182 static void advansys_wide_free_mem(struct asc_board *board)
11183 {
11184 struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
11185
11186 if (adv_dvc->carrier) {
11187 dma_free_coherent(board->dev, ADV_CARRIER_BUFSIZE,
11188 adv_dvc->carrier, adv_dvc->carrier_addr);
11189 adv_dvc->carrier = NULL;
11190 }
11191 if (board->adv_reqp) {
11192 dma_free_coherent(board->dev, board->adv_reqp_size,
11193 board->adv_reqp, board->adv_reqp_addr);
11194 board->adv_reqp = NULL;
11195 }
11196 if (board->adv_sgblk_pool) {
11197 dma_pool_destroy(board->adv_sgblk_pool);
11198 board->adv_sgblk_pool = NULL;
11199 }
11200 }
11201
11202 static int advansys_board_found(struct Scsi_Host *shost, unsigned int iop,
11203 int bus_type)
11204 {
11205 struct pci_dev *pdev;
11206 struct asc_board *boardp = shost_priv(shost);
11207 ASC_DVC_VAR *asc_dvc_varp = NULL;
11208 ADV_DVC_VAR *adv_dvc_varp = NULL;
11209 int share_irq, warn_code, ret;
11210
11211 pdev = (bus_type == ASC_IS_PCI) ? to_pci_dev(boardp->dev) : NULL;
11212
11213 if (ASC_NARROW_BOARD(boardp)) {
11214 ASC_DBG(1, "narrow board\n");
11215 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
11216 asc_dvc_varp->bus_type = bus_type;
11217 asc_dvc_varp->drv_ptr = boardp;
11218 asc_dvc_varp->cfg = &boardp->dvc_cfg.asc_dvc_cfg;
11219 asc_dvc_varp->iop_base = iop;
11220 } else {
11221 #ifdef CONFIG_PCI
11222 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
11223 adv_dvc_varp->drv_ptr = boardp;
11224 adv_dvc_varp->cfg = &boardp->dvc_cfg.adv_dvc_cfg;
11225 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW) {
11226 ASC_DBG(1, "wide board ASC-3550\n");
11227 adv_dvc_varp->chip_type = ADV_CHIP_ASC3550;
11228 } else if (pdev->device == PCI_DEVICE_ID_38C0800_REV1) {
11229 ASC_DBG(1, "wide board ASC-38C0800\n");
11230 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C0800;
11231 } else {
11232 ASC_DBG(1, "wide board ASC-38C1600\n");
11233 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C1600;
11234 }
11235
11236 boardp->asc_n_io_port = pci_resource_len(pdev, 1);
11237 boardp->ioremap_addr = pci_ioremap_bar(pdev, 1);
11238 if (!boardp->ioremap_addr) {
11239 shost_printk(KERN_ERR, shost, "ioremap(%lx, %d) "
11240 "returned NULL\n",
11241 (long)pci_resource_start(pdev, 1),
11242 boardp->asc_n_io_port);
11243 ret = -ENODEV;
11244 goto err_shost;
11245 }
11246 adv_dvc_varp->iop_base = (AdvPortAddr)boardp->ioremap_addr;
11247 ASC_DBG(1, "iop_base: 0x%p\n", adv_dvc_varp->iop_base);
11248
11249 /*
11250 * Even though it isn't used to access wide boards, other
11251 * than for the debug line below, save I/O Port address so
11252 * that it can be reported.
11253 */
11254 boardp->ioport = iop;
11255
11256 ASC_DBG(1, "iopb_chip_id_1 0x%x, iopw_chip_id_0 0x%x\n",
11257 (ushort)inp(iop + 1), (ushort)inpw(iop));
11258 #endif /* CONFIG_PCI */
11259 }
11260
11261 if (ASC_NARROW_BOARD(boardp)) {
11262 /*
11263 * Set the board bus type and PCI IRQ before
11264 * calling AscInitGetConfig().
11265 */
11266 switch (asc_dvc_varp->bus_type) {
11267 #ifdef CONFIG_ISA
11268 case ASC_IS_ISA:
11269 shost->unchecked_isa_dma = true;
11270 share_irq = 0;
11271 break;
11272 case ASC_IS_VL:
11273 shost->unchecked_isa_dma = false;
11274 share_irq = 0;
11275 break;
11276 case ASC_IS_EISA:
11277 shost->unchecked_isa_dma = false;
11278 share_irq = IRQF_SHARED;
11279 break;
11280 #endif /* CONFIG_ISA */
11281 #ifdef CONFIG_PCI
11282 case ASC_IS_PCI:
11283 shost->unchecked_isa_dma = false;
11284 share_irq = IRQF_SHARED;
11285 break;
11286 #endif /* CONFIG_PCI */
11287 default:
11288 shost_printk(KERN_ERR, shost, "unknown adapter type: "
11289 "%d\n", asc_dvc_varp->bus_type);
11290 shost->unchecked_isa_dma = false;
11291 share_irq = 0;
11292 break;
11293 }
11294
11295 /*
11296 * NOTE: AscInitGetConfig() may change the board's
11297 * bus_type value. The bus_type value should no
11298 * longer be used. If the bus_type field must be
11299 * referenced only use the bit-wise AND operator "&".
11300 */
11301 ASC_DBG(2, "AscInitGetConfig()\n");
11302 ret = AscInitGetConfig(shost) ? -ENODEV : 0;
11303 } else {
11304 #ifdef CONFIG_PCI
11305 /*
11306 * For Wide boards set PCI information before calling
11307 * AdvInitGetConfig().
11308 */
11309 shost->unchecked_isa_dma = false;
11310 share_irq = IRQF_SHARED;
11311 ASC_DBG(2, "AdvInitGetConfig()\n");
11312
11313 ret = AdvInitGetConfig(pdev, shost) ? -ENODEV : 0;
11314 #endif /* CONFIG_PCI */
11315 }
11316
11317 if (ret)
11318 goto err_unmap;
11319
11320 /*
11321 * Save the EEPROM configuration so that it can be displayed
11322 * from /proc/scsi/advansys/[0...].
11323 */
11324 if (ASC_NARROW_BOARD(boardp)) {
11325
11326 ASCEEP_CONFIG *ep;
11327
11328 /*
11329 * Set the adapter's target id bit in the 'init_tidmask' field.
11330 */
11331 boardp->init_tidmask |=
11332 ADV_TID_TO_TIDMASK(asc_dvc_varp->cfg->chip_scsi_id);
11333
11334 /*
11335 * Save EEPROM settings for the board.
11336 */
11337 ep = &boardp->eep_config.asc_eep;
11338
11339 ep->init_sdtr = asc_dvc_varp->cfg->sdtr_enable;
11340 ep->disc_enable = asc_dvc_varp->cfg->disc_enable;
11341 ep->use_cmd_qng = asc_dvc_varp->cfg->cmd_qng_enabled;
11342 ASC_EEP_SET_DMA_SPD(ep, asc_dvc_varp->cfg->isa_dma_speed);
11343 ep->start_motor = asc_dvc_varp->start_motor;
11344 ep->cntl = asc_dvc_varp->dvc_cntl;
11345 ep->no_scam = asc_dvc_varp->no_scam;
11346 ep->max_total_qng = asc_dvc_varp->max_total_qng;
11347 ASC_EEP_SET_CHIP_ID(ep, asc_dvc_varp->cfg->chip_scsi_id);
11348 /* 'max_tag_qng' is set to the same value for every device. */
11349 ep->max_tag_qng = asc_dvc_varp->cfg->max_tag_qng[0];
11350 ep->adapter_info[0] = asc_dvc_varp->cfg->adapter_info[0];
11351 ep->adapter_info[1] = asc_dvc_varp->cfg->adapter_info[1];
11352 ep->adapter_info[2] = asc_dvc_varp->cfg->adapter_info[2];
11353 ep->adapter_info[3] = asc_dvc_varp->cfg->adapter_info[3];
11354 ep->adapter_info[4] = asc_dvc_varp->cfg->adapter_info[4];
11355 ep->adapter_info[5] = asc_dvc_varp->cfg->adapter_info[5];
11356
11357 /*
11358 * Modify board configuration.
11359 */
11360 ASC_DBG(2, "AscInitSetConfig()\n");
11361 ret = AscInitSetConfig(pdev, shost) ? -ENODEV : 0;
11362 if (ret)
11363 goto err_unmap;
11364 } else {
11365 ADVEEP_3550_CONFIG *ep_3550;
11366 ADVEEP_38C0800_CONFIG *ep_38C0800;
11367 ADVEEP_38C1600_CONFIG *ep_38C1600;
11368
11369 /*
11370 * Save Wide EEP Configuration Information.
11371 */
11372 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
11373 ep_3550 = &boardp->eep_config.adv_3550_eep;
11374
11375 ep_3550->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
11376 ep_3550->max_host_qng = adv_dvc_varp->max_host_qng;
11377 ep_3550->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11378 ep_3550->termination = adv_dvc_varp->cfg->termination;
11379 ep_3550->disc_enable = adv_dvc_varp->cfg->disc_enable;
11380 ep_3550->bios_ctrl = adv_dvc_varp->bios_ctrl;
11381 ep_3550->wdtr_able = adv_dvc_varp->wdtr_able;
11382 ep_3550->sdtr_able = adv_dvc_varp->sdtr_able;
11383 ep_3550->ultra_able = adv_dvc_varp->ultra_able;
11384 ep_3550->tagqng_able = adv_dvc_varp->tagqng_able;
11385 ep_3550->start_motor = adv_dvc_varp->start_motor;
11386 ep_3550->scsi_reset_delay =
11387 adv_dvc_varp->scsi_reset_wait;
11388 ep_3550->serial_number_word1 =
11389 adv_dvc_varp->cfg->serial1;
11390 ep_3550->serial_number_word2 =
11391 adv_dvc_varp->cfg->serial2;
11392 ep_3550->serial_number_word3 =
11393 adv_dvc_varp->cfg->serial3;
11394 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
11395 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
11396
11397 ep_38C0800->adapter_scsi_id =
11398 adv_dvc_varp->chip_scsi_id;
11399 ep_38C0800->max_host_qng = adv_dvc_varp->max_host_qng;
11400 ep_38C0800->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11401 ep_38C0800->termination_lvd =
11402 adv_dvc_varp->cfg->termination;
11403 ep_38C0800->disc_enable =
11404 adv_dvc_varp->cfg->disc_enable;
11405 ep_38C0800->bios_ctrl = adv_dvc_varp->bios_ctrl;
11406 ep_38C0800->wdtr_able = adv_dvc_varp->wdtr_able;
11407 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
11408 ep_38C0800->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
11409 ep_38C0800->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
11410 ep_38C0800->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
11411 ep_38C0800->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
11412 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
11413 ep_38C0800->start_motor = adv_dvc_varp->start_motor;
11414 ep_38C0800->scsi_reset_delay =
11415 adv_dvc_varp->scsi_reset_wait;
11416 ep_38C0800->serial_number_word1 =
11417 adv_dvc_varp->cfg->serial1;
11418 ep_38C0800->serial_number_word2 =
11419 adv_dvc_varp->cfg->serial2;
11420 ep_38C0800->serial_number_word3 =
11421 adv_dvc_varp->cfg->serial3;
11422 } else {
11423 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
11424
11425 ep_38C1600->adapter_scsi_id =
11426 adv_dvc_varp->chip_scsi_id;
11427 ep_38C1600->max_host_qng = adv_dvc_varp->max_host_qng;
11428 ep_38C1600->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11429 ep_38C1600->termination_lvd =
11430 adv_dvc_varp->cfg->termination;
11431 ep_38C1600->disc_enable =
11432 adv_dvc_varp->cfg->disc_enable;
11433 ep_38C1600->bios_ctrl = adv_dvc_varp->bios_ctrl;
11434 ep_38C1600->wdtr_able = adv_dvc_varp->wdtr_able;
11435 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
11436 ep_38C1600->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
11437 ep_38C1600->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
11438 ep_38C1600->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
11439 ep_38C1600->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
11440 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
11441 ep_38C1600->start_motor = adv_dvc_varp->start_motor;
11442 ep_38C1600->scsi_reset_delay =
11443 adv_dvc_varp->scsi_reset_wait;
11444 ep_38C1600->serial_number_word1 =
11445 adv_dvc_varp->cfg->serial1;
11446 ep_38C1600->serial_number_word2 =
11447 adv_dvc_varp->cfg->serial2;
11448 ep_38C1600->serial_number_word3 =
11449 adv_dvc_varp->cfg->serial3;
11450 }
11451
11452 /*
11453 * Set the adapter's target id bit in the 'init_tidmask' field.
11454 */
11455 boardp->init_tidmask |=
11456 ADV_TID_TO_TIDMASK(adv_dvc_varp->chip_scsi_id);
11457 }
11458
11459 /*
11460 * Channels are numbered beginning with 0. For AdvanSys one host
11461 * structure supports one channel. Multi-channel boards have a
11462 * separate host structure for each channel.
11463 */
11464 shost->max_channel = 0;
11465 if (ASC_NARROW_BOARD(boardp)) {
11466 shost->max_id = ASC_MAX_TID + 1;
11467 shost->max_lun = ASC_MAX_LUN + 1;
11468 shost->max_cmd_len = ASC_MAX_CDB_LEN;
11469
11470 shost->io_port = asc_dvc_varp->iop_base;
11471 boardp->asc_n_io_port = ASC_IOADR_GAP;
11472 shost->this_id = asc_dvc_varp->cfg->chip_scsi_id;
11473
11474 /* Set maximum number of queues the adapter can handle. */
11475 shost->can_queue = asc_dvc_varp->max_total_qng;
11476 } else {
11477 shost->max_id = ADV_MAX_TID + 1;
11478 shost->max_lun = ADV_MAX_LUN + 1;
11479 shost->max_cmd_len = ADV_MAX_CDB_LEN;
11480
11481 /*
11482 * Save the I/O Port address and length even though
11483 * I/O ports are not used to access Wide boards.
11484 * Instead the Wide boards are accessed with
11485 * PCI Memory Mapped I/O.
11486 */
11487 shost->io_port = iop;
11488
11489 shost->this_id = adv_dvc_varp->chip_scsi_id;
11490
11491 /* Set maximum number of queues the adapter can handle. */
11492 shost->can_queue = adv_dvc_varp->max_host_qng;
11493 }
11494 ret = scsi_init_shared_tag_map(shost, shost->can_queue);
11495 if (ret) {
11496 shost_printk(KERN_ERR, shost, "init tag map failed\n");
11497 goto err_free_dma;
11498 }
11499
11500 /*
11501 * Following v1.3.89, 'cmd_per_lun' is no longer needed
11502 * and should be set to zero.
11503 *
11504 * But because of a bug introduced in v1.3.89 if the driver is
11505 * compiled as a module and 'cmd_per_lun' is zero, the Mid-Level
11506 * SCSI function 'allocate_device' will panic. To allow the driver
11507 * to work as a module in these kernels set 'cmd_per_lun' to 1.
11508 *
11509 * Note: This is wrong. cmd_per_lun should be set to the depth
11510 * you want on untagged devices always.
11511 #ifdef MODULE
11512 */
11513 shost->cmd_per_lun = 1;
11514 /* #else
11515 shost->cmd_per_lun = 0;
11516 #endif */
11517
11518 /*
11519 * Set the maximum number of scatter-gather elements the
11520 * adapter can handle.
11521 */
11522 if (ASC_NARROW_BOARD(boardp)) {
11523 /*
11524 * Allow two commands with 'sg_tablesize' scatter-gather
11525 * elements to be executed simultaneously. This value is
11526 * the theoretical hardware limit. It may be decreased
11527 * below.
11528 */
11529 shost->sg_tablesize =
11530 (((asc_dvc_varp->max_total_qng - 2) / 2) *
11531 ASC_SG_LIST_PER_Q) + 1;
11532 } else {
11533 shost->sg_tablesize = ADV_MAX_SG_LIST;
11534 }
11535
11536 /*
11537 * The value of 'sg_tablesize' can not exceed the SCSI
11538 * mid-level driver definition of SG_ALL. SG_ALL also
11539 * must not be exceeded, because it is used to define the
11540 * size of the scatter-gather table in 'struct asc_sg_head'.
11541 */
11542 if (shost->sg_tablesize > SG_ALL) {
11543 shost->sg_tablesize = SG_ALL;
11544 }
11545
11546 ASC_DBG(1, "sg_tablesize: %d\n", shost->sg_tablesize);
11547
11548 /* BIOS start address. */
11549 if (ASC_NARROW_BOARD(boardp)) {
11550 shost->base = AscGetChipBiosAddress(asc_dvc_varp->iop_base,
11551 asc_dvc_varp->bus_type);
11552 } else {
11553 /*
11554 * Fill-in BIOS board variables. The Wide BIOS saves
11555 * information in LRAM that is used by the driver.
11556 */
11557 AdvReadWordLram(adv_dvc_varp->iop_base,
11558 BIOS_SIGNATURE, boardp->bios_signature);
11559 AdvReadWordLram(adv_dvc_varp->iop_base,
11560 BIOS_VERSION, boardp->bios_version);
11561 AdvReadWordLram(adv_dvc_varp->iop_base,
11562 BIOS_CODESEG, boardp->bios_codeseg);
11563 AdvReadWordLram(adv_dvc_varp->iop_base,
11564 BIOS_CODELEN, boardp->bios_codelen);
11565
11566 ASC_DBG(1, "bios_signature 0x%x, bios_version 0x%x\n",
11567 boardp->bios_signature, boardp->bios_version);
11568
11569 ASC_DBG(1, "bios_codeseg 0x%x, bios_codelen 0x%x\n",
11570 boardp->bios_codeseg, boardp->bios_codelen);
11571
11572 /*
11573 * If the BIOS saved a valid signature, then fill in
11574 * the BIOS code segment base address.
11575 */
11576 if (boardp->bios_signature == 0x55AA) {
11577 /*
11578 * Convert x86 realmode code segment to a linear
11579 * address by shifting left 4.
11580 */
11581 shost->base = ((ulong)boardp->bios_codeseg << 4);
11582 } else {
11583 shost->base = 0;
11584 }
11585 }
11586
11587 /*
11588 * Register Board Resources - I/O Port, DMA, IRQ
11589 */
11590
11591 /* Register DMA Channel for Narrow boards. */
11592 shost->dma_channel = NO_ISA_DMA; /* Default to no ISA DMA. */
11593 #ifdef CONFIG_ISA
11594 if (ASC_NARROW_BOARD(boardp)) {
11595 /* Register DMA channel for ISA bus. */
11596 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
11597 shost->dma_channel = asc_dvc_varp->cfg->isa_dma_channel;
11598 ret = request_dma(shost->dma_channel, DRV_NAME);
11599 if (ret) {
11600 shost_printk(KERN_ERR, shost, "request_dma() "
11601 "%d failed %d\n",
11602 shost->dma_channel, ret);
11603 goto err_unmap;
11604 }
11605 AscEnableIsaDma(shost->dma_channel);
11606 }
11607 }
11608 #endif /* CONFIG_ISA */
11609
11610 /* Register IRQ Number. */
11611 ASC_DBG(2, "request_irq(%d, %p)\n", boardp->irq, shost);
11612
11613 ret = request_irq(boardp->irq, advansys_interrupt, share_irq,
11614 DRV_NAME, shost);
11615
11616 if (ret) {
11617 if (ret == -EBUSY) {
11618 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11619 "already in use\n", boardp->irq);
11620 } else if (ret == -EINVAL) {
11621 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11622 "not valid\n", boardp->irq);
11623 } else {
11624 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11625 "failed with %d\n", boardp->irq, ret);
11626 }
11627 goto err_free_dma;
11628 }
11629
11630 /*
11631 * Initialize board RISC chip and enable interrupts.
11632 */
11633 if (ASC_NARROW_BOARD(boardp)) {
11634 ASC_DBG(2, "AscInitAsc1000Driver()\n");
11635
11636 asc_dvc_varp->overrun_buf = kzalloc(ASC_OVERRUN_BSIZE, GFP_KERNEL);
11637 if (!asc_dvc_varp->overrun_buf) {
11638 ret = -ENOMEM;
11639 goto err_free_irq;
11640 }
11641 warn_code = AscInitAsc1000Driver(asc_dvc_varp);
11642
11643 if (warn_code || asc_dvc_varp->err_code) {
11644 shost_printk(KERN_ERR, shost, "error: init_state 0x%x, "
11645 "warn 0x%x, error 0x%x\n",
11646 asc_dvc_varp->init_state, warn_code,
11647 asc_dvc_varp->err_code);
11648 if (!asc_dvc_varp->overrun_dma) {
11649 ret = -ENODEV;
11650 goto err_free_mem;
11651 }
11652 }
11653 } else {
11654 if (advansys_wide_init_chip(shost)) {
11655 ret = -ENODEV;
11656 goto err_free_mem;
11657 }
11658 }
11659
11660 ASC_DBG_PRT_SCSI_HOST(2, shost);
11661
11662 ret = scsi_add_host(shost, boardp->dev);
11663 if (ret)
11664 goto err_free_mem;
11665
11666 scsi_scan_host(shost);
11667 return 0;
11668
11669 err_free_mem:
11670 if (ASC_NARROW_BOARD(boardp)) {
11671 if (asc_dvc_varp->overrun_dma)
11672 dma_unmap_single(boardp->dev, asc_dvc_varp->overrun_dma,
11673 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
11674 kfree(asc_dvc_varp->overrun_buf);
11675 } else
11676 advansys_wide_free_mem(boardp);
11677 err_free_irq:
11678 free_irq(boardp->irq, shost);
11679 err_free_dma:
11680 #ifdef CONFIG_ISA
11681 if (shost->dma_channel != NO_ISA_DMA)
11682 free_dma(shost->dma_channel);
11683 #endif
11684 err_unmap:
11685 if (boardp->ioremap_addr)
11686 iounmap(boardp->ioremap_addr);
11687 err_shost:
11688 return ret;
11689 }
11690
11691 /*
11692 * advansys_release()
11693 *
11694 * Release resources allocated for a single AdvanSys adapter.
11695 */
11696 static int advansys_release(struct Scsi_Host *shost)
11697 {
11698 struct asc_board *board = shost_priv(shost);
11699 ASC_DBG(1, "begin\n");
11700 scsi_remove_host(shost);
11701 free_irq(board->irq, shost);
11702 #ifdef CONFIG_ISA
11703 if (shost->dma_channel != NO_ISA_DMA) {
11704 ASC_DBG(1, "free_dma()\n");
11705 free_dma(shost->dma_channel);
11706 }
11707 #endif
11708 if (ASC_NARROW_BOARD(board)) {
11709 dma_unmap_single(board->dev,
11710 board->dvc_var.asc_dvc_var.overrun_dma,
11711 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
11712 kfree(board->dvc_var.asc_dvc_var.overrun_buf);
11713 } else {
11714 iounmap(board->ioremap_addr);
11715 advansys_wide_free_mem(board);
11716 }
11717 scsi_host_put(shost);
11718 ASC_DBG(1, "end\n");
11719 return 0;
11720 }
11721
11722 #define ASC_IOADR_TABLE_MAX_IX 11
11723
11724 static PortAddr _asc_def_iop_base[ASC_IOADR_TABLE_MAX_IX] = {
11725 0x100, 0x0110, 0x120, 0x0130, 0x140, 0x0150, 0x0190,
11726 0x0210, 0x0230, 0x0250, 0x0330
11727 };
11728
11729 /*
11730 * The ISA IRQ number is found in bits 2 and 3 of the CfgLsw. It decodes as:
11731 * 00: 10
11732 * 01: 11
11733 * 10: 12
11734 * 11: 15
11735 */
11736 static unsigned int advansys_isa_irq_no(PortAddr iop_base)
11737 {
11738 unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
11739 unsigned int chip_irq = ((cfg_lsw >> 2) & 0x03) + 10;
11740 if (chip_irq == 13)
11741 chip_irq = 15;
11742 return chip_irq;
11743 }
11744
11745 static int advansys_isa_probe(struct device *dev, unsigned int id)
11746 {
11747 int err = -ENODEV;
11748 PortAddr iop_base = _asc_def_iop_base[id];
11749 struct Scsi_Host *shost;
11750 struct asc_board *board;
11751
11752 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
11753 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
11754 return -ENODEV;
11755 }
11756 ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
11757 if (!AscFindSignature(iop_base))
11758 goto release_region;
11759 if (!(AscGetChipVersion(iop_base, ASC_IS_ISA) & ASC_CHIP_VER_ISA_BIT))
11760 goto release_region;
11761
11762 err = -ENOMEM;
11763 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
11764 if (!shost)
11765 goto release_region;
11766
11767 board = shost_priv(shost);
11768 board->irq = advansys_isa_irq_no(iop_base);
11769 board->dev = dev;
11770 board->shost = shost;
11771
11772 err = advansys_board_found(shost, iop_base, ASC_IS_ISA);
11773 if (err)
11774 goto free_host;
11775
11776 dev_set_drvdata(dev, shost);
11777 return 0;
11778
11779 free_host:
11780 scsi_host_put(shost);
11781 release_region:
11782 release_region(iop_base, ASC_IOADR_GAP);
11783 return err;
11784 }
11785
11786 static int advansys_isa_remove(struct device *dev, unsigned int id)
11787 {
11788 int ioport = _asc_def_iop_base[id];
11789 advansys_release(dev_get_drvdata(dev));
11790 release_region(ioport, ASC_IOADR_GAP);
11791 return 0;
11792 }
11793
11794 static struct isa_driver advansys_isa_driver = {
11795 .probe = advansys_isa_probe,
11796 .remove = advansys_isa_remove,
11797 .driver = {
11798 .owner = THIS_MODULE,
11799 .name = DRV_NAME,
11800 },
11801 };
11802
11803 /*
11804 * The VLB IRQ number is found in bits 2 to 4 of the CfgLsw. It decodes as:
11805 * 000: invalid
11806 * 001: 10
11807 * 010: 11
11808 * 011: 12
11809 * 100: invalid
11810 * 101: 14
11811 * 110: 15
11812 * 111: invalid
11813 */
11814 static unsigned int advansys_vlb_irq_no(PortAddr iop_base)
11815 {
11816 unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
11817 unsigned int chip_irq = ((cfg_lsw >> 2) & 0x07) + 9;
11818 if ((chip_irq < 10) || (chip_irq == 13) || (chip_irq > 15))
11819 return 0;
11820 return chip_irq;
11821 }
11822
11823 static int advansys_vlb_probe(struct device *dev, unsigned int id)
11824 {
11825 int err = -ENODEV;
11826 PortAddr iop_base = _asc_def_iop_base[id];
11827 struct Scsi_Host *shost;
11828 struct asc_board *board;
11829
11830 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
11831 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
11832 return -ENODEV;
11833 }
11834 ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
11835 if (!AscFindSignature(iop_base))
11836 goto release_region;
11837 /*
11838 * I don't think this condition can actually happen, but the old
11839 * driver did it, and the chances of finding a VLB setup in 2007
11840 * to do testing with is slight to none.
11841 */
11842 if (AscGetChipVersion(iop_base, ASC_IS_VL) > ASC_CHIP_MAX_VER_VL)
11843 goto release_region;
11844
11845 err = -ENOMEM;
11846 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
11847 if (!shost)
11848 goto release_region;
11849
11850 board = shost_priv(shost);
11851 board->irq = advansys_vlb_irq_no(iop_base);
11852 board->dev = dev;
11853 board->shost = shost;
11854
11855 err = advansys_board_found(shost, iop_base, ASC_IS_VL);
11856 if (err)
11857 goto free_host;
11858
11859 dev_set_drvdata(dev, shost);
11860 return 0;
11861
11862 free_host:
11863 scsi_host_put(shost);
11864 release_region:
11865 release_region(iop_base, ASC_IOADR_GAP);
11866 return -ENODEV;
11867 }
11868
11869 static struct isa_driver advansys_vlb_driver = {
11870 .probe = advansys_vlb_probe,
11871 .remove = advansys_isa_remove,
11872 .driver = {
11873 .owner = THIS_MODULE,
11874 .name = "advansys_vlb",
11875 },
11876 };
11877
11878 static struct eisa_device_id advansys_eisa_table[] = {
11879 { "ABP7401" },
11880 { "ABP7501" },
11881 { "" }
11882 };
11883
11884 MODULE_DEVICE_TABLE(eisa, advansys_eisa_table);
11885
11886 /*
11887 * EISA is a little more tricky than PCI; each EISA device may have two
11888 * channels, and this driver is written to make each channel its own Scsi_Host
11889 */
11890 struct eisa_scsi_data {
11891 struct Scsi_Host *host[2];
11892 };
11893
11894 /*
11895 * The EISA IRQ number is found in bits 8 to 10 of the CfgLsw. It decodes as:
11896 * 000: 10
11897 * 001: 11
11898 * 010: 12
11899 * 011: invalid
11900 * 100: 14
11901 * 101: 15
11902 * 110: invalid
11903 * 111: invalid
11904 */
11905 static unsigned int advansys_eisa_irq_no(struct eisa_device *edev)
11906 {
11907 unsigned short cfg_lsw = inw(edev->base_addr + 0xc86);
11908 unsigned int chip_irq = ((cfg_lsw >> 8) & 0x07) + 10;
11909 if ((chip_irq == 13) || (chip_irq > 15))
11910 return 0;
11911 return chip_irq;
11912 }
11913
11914 static int advansys_eisa_probe(struct device *dev)
11915 {
11916 int i, ioport, irq = 0;
11917 int err;
11918 struct eisa_device *edev = to_eisa_device(dev);
11919 struct eisa_scsi_data *data;
11920
11921 err = -ENOMEM;
11922 data = kzalloc(sizeof(*data), GFP_KERNEL);
11923 if (!data)
11924 goto fail;
11925 ioport = edev->base_addr + 0xc30;
11926
11927 err = -ENODEV;
11928 for (i = 0; i < 2; i++, ioport += 0x20) {
11929 struct asc_board *board;
11930 struct Scsi_Host *shost;
11931 if (!request_region(ioport, ASC_IOADR_GAP, DRV_NAME)) {
11932 printk(KERN_WARNING "Region %x-%x busy\n", ioport,
11933 ioport + ASC_IOADR_GAP - 1);
11934 continue;
11935 }
11936 if (!AscFindSignature(ioport)) {
11937 release_region(ioport, ASC_IOADR_GAP);
11938 continue;
11939 }
11940
11941 /*
11942 * I don't know why we need to do this for EISA chips, but
11943 * not for any others. It looks to be equivalent to
11944 * AscGetChipCfgMsw, but I may have overlooked something,
11945 * so I'm not converting it until I get an EISA board to
11946 * test with.
11947 */
11948 inw(ioport + 4);
11949
11950 if (!irq)
11951 irq = advansys_eisa_irq_no(edev);
11952
11953 err = -ENOMEM;
11954 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
11955 if (!shost)
11956 goto release_region;
11957
11958 board = shost_priv(shost);
11959 board->irq = irq;
11960 board->dev = dev;
11961 board->shost = shost;
11962
11963 err = advansys_board_found(shost, ioport, ASC_IS_EISA);
11964 if (!err) {
11965 data->host[i] = shost;
11966 continue;
11967 }
11968
11969 scsi_host_put(shost);
11970 release_region:
11971 release_region(ioport, ASC_IOADR_GAP);
11972 break;
11973 }
11974
11975 if (err)
11976 goto free_data;
11977 dev_set_drvdata(dev, data);
11978 return 0;
11979
11980 free_data:
11981 kfree(data->host[0]);
11982 kfree(data->host[1]);
11983 kfree(data);
11984 fail:
11985 return err;
11986 }
11987
11988 static int advansys_eisa_remove(struct device *dev)
11989 {
11990 int i;
11991 struct eisa_scsi_data *data = dev_get_drvdata(dev);
11992
11993 for (i = 0; i < 2; i++) {
11994 int ioport;
11995 struct Scsi_Host *shost = data->host[i];
11996 if (!shost)
11997 continue;
11998 ioport = shost->io_port;
11999 advansys_release(shost);
12000 release_region(ioport, ASC_IOADR_GAP);
12001 }
12002
12003 kfree(data);
12004 return 0;
12005 }
12006
12007 static struct eisa_driver advansys_eisa_driver = {
12008 .id_table = advansys_eisa_table,
12009 .driver = {
12010 .name = DRV_NAME,
12011 .probe = advansys_eisa_probe,
12012 .remove = advansys_eisa_remove,
12013 }
12014 };
12015
12016 /* PCI Devices supported by this driver */
12017 static struct pci_device_id advansys_pci_tbl[] = {
12018 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_1200A,
12019 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12020 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940,
12021 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12022 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940U,
12023 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12024 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940UW,
12025 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12026 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C0800_REV1,
12027 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12028 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C1600_REV1,
12029 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12030 {}
12031 };
12032
12033 MODULE_DEVICE_TABLE(pci, advansys_pci_tbl);
12034
12035 static void advansys_set_latency(struct pci_dev *pdev)
12036 {
12037 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
12038 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
12039 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0);
12040 } else {
12041 u8 latency;
12042 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency);
12043 if (latency < 0x20)
12044 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20);
12045 }
12046 }
12047
12048 static int advansys_pci_probe(struct pci_dev *pdev,
12049 const struct pci_device_id *ent)
12050 {
12051 int err, ioport;
12052 struct Scsi_Host *shost;
12053 struct asc_board *board;
12054
12055 err = pci_enable_device(pdev);
12056 if (err)
12057 goto fail;
12058 err = pci_request_regions(pdev, DRV_NAME);
12059 if (err)
12060 goto disable_device;
12061 pci_set_master(pdev);
12062 advansys_set_latency(pdev);
12063
12064 err = -ENODEV;
12065 if (pci_resource_len(pdev, 0) == 0)
12066 goto release_region;
12067
12068 ioport = pci_resource_start(pdev, 0);
12069
12070 err = -ENOMEM;
12071 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
12072 if (!shost)
12073 goto release_region;
12074
12075 board = shost_priv(shost);
12076 board->irq = pdev->irq;
12077 board->dev = &pdev->dev;
12078 board->shost = shost;
12079
12080 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW ||
12081 pdev->device == PCI_DEVICE_ID_38C0800_REV1 ||
12082 pdev->device == PCI_DEVICE_ID_38C1600_REV1) {
12083 board->flags |= ASC_IS_WIDE_BOARD;
12084 }
12085
12086 err = advansys_board_found(shost, ioport, ASC_IS_PCI);
12087 if (err)
12088 goto free_host;
12089
12090 pci_set_drvdata(pdev, shost);
12091 return 0;
12092
12093 free_host:
12094 scsi_host_put(shost);
12095 release_region:
12096 pci_release_regions(pdev);
12097 disable_device:
12098 pci_disable_device(pdev);
12099 fail:
12100 return err;
12101 }
12102
12103 static void advansys_pci_remove(struct pci_dev *pdev)
12104 {
12105 advansys_release(pci_get_drvdata(pdev));
12106 pci_release_regions(pdev);
12107 pci_disable_device(pdev);
12108 }
12109
12110 static struct pci_driver advansys_pci_driver = {
12111 .name = DRV_NAME,
12112 .id_table = advansys_pci_tbl,
12113 .probe = advansys_pci_probe,
12114 .remove = advansys_pci_remove,
12115 };
12116
12117 static int __init advansys_init(void)
12118 {
12119 int error;
12120
12121 error = isa_register_driver(&advansys_isa_driver,
12122 ASC_IOADR_TABLE_MAX_IX);
12123 if (error)
12124 goto fail;
12125
12126 error = isa_register_driver(&advansys_vlb_driver,
12127 ASC_IOADR_TABLE_MAX_IX);
12128 if (error)
12129 goto unregister_isa;
12130
12131 error = eisa_driver_register(&advansys_eisa_driver);
12132 if (error)
12133 goto unregister_vlb;
12134
12135 error = pci_register_driver(&advansys_pci_driver);
12136 if (error)
12137 goto unregister_eisa;
12138
12139 return 0;
12140
12141 unregister_eisa:
12142 eisa_driver_unregister(&advansys_eisa_driver);
12143 unregister_vlb:
12144 isa_unregister_driver(&advansys_vlb_driver);
12145 unregister_isa:
12146 isa_unregister_driver(&advansys_isa_driver);
12147 fail:
12148 return error;
12149 }
12150
12151 static void __exit advansys_exit(void)
12152 {
12153 pci_unregister_driver(&advansys_pci_driver);
12154 eisa_driver_unregister(&advansys_eisa_driver);
12155 isa_unregister_driver(&advansys_vlb_driver);
12156 isa_unregister_driver(&advansys_isa_driver);
12157 }
12158
12159 module_init(advansys_init);
12160 module_exit(advansys_exit);
12161
12162 MODULE_LICENSE("GPL");
12163 MODULE_FIRMWARE("advansys/mcode.bin");
12164 MODULE_FIRMWARE("advansys/3550.bin");
12165 MODULE_FIRMWARE("advansys/38C0800.bin");
12166 MODULE_FIRMWARE("advansys/38C1600.bin");
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