drivers/net/wireless/ath/ath10k/hw.h

   1 /*
   2  * Copyright (c) 2005-2011 Atheros Communications Inc.
   3  * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
   4  *
   5  * Permission to use, copy, modify, and/or distribute this software for any
   6  * purpose with or without fee is hereby granted, provided that the above
   7  * copyright notice and this permission notice appear in all copies.
   8  *
   9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16  */
  17
  18 #ifndef _HW_H_
  19 #define _HW_H_
  20
  21 #include "targaddrs.h"
  22
  23 #define ATH10K_FW_DIR                   "ath10k"
  24
  25 #define QCA988X_2_0_DEVICE_ID   (0x003c)
  26 #define QCA6164_2_1_DEVICE_ID   (0x0041)
  27 #define QCA6174_2_1_DEVICE_ID   (0x003e)
  28 #define QCA99X0_2_0_DEVICE_ID   (0x0040)
  29 #define QCA9888_2_0_DEVICE_ID   (0x0056)
  30 #define QCA9984_1_0_DEVICE_ID   (0x0046)
  31 #define QCA9377_1_0_DEVICE_ID   (0x0042)
  32 #define QCA9887_1_0_DEVICE_ID   (0x0050)
  33
  34 /* QCA988X 1.0 definitions (unsupported) */
  35 #define QCA988X_HW_1_0_CHIP_ID_REV      0x0
  36
  37 /* QCA988X 2.0 definitions */
  38 #define QCA988X_HW_2_0_VERSION          0x4100016c
  39 #define QCA988X_HW_2_0_CHIP_ID_REV      0x2
  40 #define QCA988X_HW_2_0_FW_DIR           ATH10K_FW_DIR "/QCA988X/hw2.0"
  41 #define QCA988X_HW_2_0_BOARD_DATA_FILE  "board.bin"
  42 #define QCA988X_HW_2_0_PATCH_LOAD_ADDR  0x1234
  43
  44 /* QCA9887 1.0 definitions */
  45 #define QCA9887_HW_1_0_VERSION          0x4100016d
  46 #define QCA9887_HW_1_0_CHIP_ID_REV      0
  47 #define QCA9887_HW_1_0_FW_DIR           ATH10K_FW_DIR "/QCA9887/hw1.0"
  48 #define QCA9887_HW_1_0_BOARD_DATA_FILE  "board.bin"
  49 #define QCA9887_HW_1_0_PATCH_LOAD_ADDR  0x1234
  50
  51 /* QCA6174 target BMI version signatures */
  52 #define QCA6174_HW_1_0_VERSION          0x05000000
  53 #define QCA6174_HW_1_1_VERSION          0x05000001
  54 #define QCA6174_HW_1_3_VERSION          0x05000003
  55 #define QCA6174_HW_2_1_VERSION          0x05010000
  56 #define QCA6174_HW_3_0_VERSION          0x05020000
  57 #define QCA6174_HW_3_2_VERSION          0x05030000
  58
  59 /* QCA9377 target BMI version signatures */
  60 #define QCA9377_HW_1_0_DEV_VERSION      0x05020000
  61 #define QCA9377_HW_1_1_DEV_VERSION      0x05020001
  62
  63 enum qca6174_pci_rev {
  64         QCA6174_PCI_REV_1_1 = 0x11,
  65         QCA6174_PCI_REV_1_3 = 0x13,
  66         QCA6174_PCI_REV_2_0 = 0x20,
  67         QCA6174_PCI_REV_3_0 = 0x30,
  68 };
  69
  70 enum qca6174_chip_id_rev {
  71         QCA6174_HW_1_0_CHIP_ID_REV = 0,
  72         QCA6174_HW_1_1_CHIP_ID_REV = 1,
  73         QCA6174_HW_1_3_CHIP_ID_REV = 2,
  74         QCA6174_HW_2_1_CHIP_ID_REV = 4,
  75         QCA6174_HW_2_2_CHIP_ID_REV = 5,
  76         QCA6174_HW_3_0_CHIP_ID_REV = 8,
  77         QCA6174_HW_3_1_CHIP_ID_REV = 9,
  78         QCA6174_HW_3_2_CHIP_ID_REV = 10,
  79 };
  80
  81 enum qca9377_chip_id_rev {
  82         QCA9377_HW_1_0_CHIP_ID_REV = 0x0,
  83         QCA9377_HW_1_1_CHIP_ID_REV = 0x1,
  84 };
  85
  86 #define QCA6174_HW_2_1_FW_DIR           "ath10k/QCA6174/hw2.1"
  87 #define QCA6174_HW_2_1_BOARD_DATA_FILE  "board.bin"
  88 #define QCA6174_HW_2_1_PATCH_LOAD_ADDR  0x1234
  89
  90 #define QCA6174_HW_3_0_FW_DIR           "ath10k/QCA6174/hw3.0"
  91 #define QCA6174_HW_3_0_BOARD_DATA_FILE  "board.bin"
  92 #define QCA6174_HW_3_0_PATCH_LOAD_ADDR  0x1234
  93
  94 /* QCA99X0 1.0 definitions (unsupported) */
  95 #define QCA99X0_HW_1_0_CHIP_ID_REV     0x0
  96
  97 /* QCA99X0 2.0 definitions */
  98 #define QCA99X0_HW_2_0_DEV_VERSION     0x01000000
  99 #define QCA99X0_HW_2_0_CHIP_ID_REV     0x1
 100 #define QCA99X0_HW_2_0_FW_DIR          ATH10K_FW_DIR "/QCA99X0/hw2.0"
 101 #define QCA99X0_HW_2_0_BOARD_DATA_FILE "board.bin"
 102 #define QCA99X0_HW_2_0_PATCH_LOAD_ADDR  0x1234
 103
 104 /* QCA9984 1.0 defines */
 105 #define QCA9984_HW_1_0_DEV_VERSION      0x1000000
 106 #define QCA9984_HW_DEV_TYPE             0xa
 107 #define QCA9984_HW_1_0_CHIP_ID_REV      0x0
 108 #define QCA9984_HW_1_0_FW_DIR           ATH10K_FW_DIR "/QCA9984/hw1.0"
 109 #define QCA9984_HW_1_0_BOARD_DATA_FILE "board.bin"
 110 #define QCA9984_HW_1_0_PATCH_LOAD_ADDR  0x1234
 111
 112 /* QCA9888 2.0 defines */
 113 #define QCA9888_HW_2_0_DEV_VERSION      0x1000000
 114 #define QCA9888_HW_DEV_TYPE             0xc
 115 #define QCA9888_HW_2_0_CHIP_ID_REV      0x0
 116 #define QCA9888_HW_2_0_FW_DIR           ATH10K_FW_DIR "/QCA9888/hw2.0"
 117 #define QCA9888_HW_2_0_BOARD_DATA_FILE "board.bin"
 118 #define QCA9888_HW_2_0_PATCH_LOAD_ADDR  0x1234
 119
 120 /* QCA9377 1.0 definitions */
 121 #define QCA9377_HW_1_0_FW_DIR          ATH10K_FW_DIR "/QCA9377/hw1.0"
 122 #define QCA9377_HW_1_0_BOARD_DATA_FILE "board.bin"
 123 #define QCA9377_HW_1_0_PATCH_LOAD_ADDR  0x1234
 124
 125 /* QCA4019 1.0 definitions */
 126 #define QCA4019_HW_1_0_DEV_VERSION     0x01000000
 127 #define QCA4019_HW_1_0_FW_DIR          ATH10K_FW_DIR "/QCA4019/hw1.0"
 128 #define QCA4019_HW_1_0_BOARD_DATA_FILE "board.bin"
 129 #define QCA4019_HW_1_0_PATCH_LOAD_ADDR  0x1234
 130
 131 #define ATH10K_FW_FILE_BASE             "firmware"
 132 #define ATH10K_FW_API_MAX               6
 133 #define ATH10K_FW_API_MIN               2
 134
 135 #define ATH10K_FW_API2_FILE             "firmware-2.bin"
 136 #define ATH10K_FW_API3_FILE             "firmware-3.bin"
 137
 138 /* added support for ATH10K_FW_IE_WMI_OP_VERSION */
 139 #define ATH10K_FW_API4_FILE             "firmware-4.bin"
 140
 141 /* HTT id conflict fix for management frames over HTT */
 142 #define ATH10K_FW_API5_FILE             "firmware-5.bin"
 143
 144 /* the firmware-6.bin blob */
 145 #define ATH10K_FW_API6_FILE             "firmware-6.bin"
 146
 147 #define ATH10K_FW_UTF_FILE              "utf.bin"
 148 #define ATH10K_FW_UTF_API2_FILE         "utf-2.bin"
 149
 150 /* includes also the null byte */
 151 #define ATH10K_FIRMWARE_MAGIC               "QCA-ATH10K"
 152 #define ATH10K_BOARD_MAGIC                  "QCA-ATH10K-BOARD"
 153
 154 #define ATH10K_BOARD_API2_FILE         "board-2.bin"
 155
 156 #define REG_DUMP_COUNT_QCA988X 60
 157
 158 struct ath10k_fw_ie {
 159         __le32 id;
 160         __le32 len;
 161         u8 data[0];
 162 };
 163
 164 enum ath10k_fw_ie_type {
 165         ATH10K_FW_IE_FW_VERSION = 0,
 166         ATH10K_FW_IE_TIMESTAMP = 1,
 167         ATH10K_FW_IE_FEATURES = 2,
 168         ATH10K_FW_IE_FW_IMAGE = 3,
 169         ATH10K_FW_IE_OTP_IMAGE = 4,
 170
 171         /* WMI "operations" interface version, 32 bit value. Supported from
 172          * FW API 4 and above.
 173          */
 174         ATH10K_FW_IE_WMI_OP_VERSION = 5,
 175
 176         /* HTT "operations" interface version, 32 bit value. Supported from
 177          * FW API 5 and above.
 178          */
 179         ATH10K_FW_IE_HTT_OP_VERSION = 6,
 180
 181         /* Code swap image for firmware binary */
 182         ATH10K_FW_IE_FW_CODE_SWAP_IMAGE = 7,
 183 };
 184
 185 enum ath10k_fw_wmi_op_version {
 186         ATH10K_FW_WMI_OP_VERSION_UNSET = 0,
 187
 188         ATH10K_FW_WMI_OP_VERSION_MAIN = 1,
 189         ATH10K_FW_WMI_OP_VERSION_10_1 = 2,
 190         ATH10K_FW_WMI_OP_VERSION_10_2 = 3,
 191         ATH10K_FW_WMI_OP_VERSION_TLV = 4,
 192         ATH10K_FW_WMI_OP_VERSION_10_2_4 = 5,
 193         ATH10K_FW_WMI_OP_VERSION_10_4 = 6,
 194
 195         /* keep last */
 196         ATH10K_FW_WMI_OP_VERSION_MAX,
 197 };
 198
 199 enum ath10k_fw_htt_op_version {
 200         ATH10K_FW_HTT_OP_VERSION_UNSET = 0,
 201
 202         ATH10K_FW_HTT_OP_VERSION_MAIN = 1,
 203
 204         /* also used in 10.2 and 10.2.4 branches */
 205         ATH10K_FW_HTT_OP_VERSION_10_1 = 2,
 206
 207         ATH10K_FW_HTT_OP_VERSION_TLV = 3,
 208
 209         ATH10K_FW_HTT_OP_VERSION_10_4 = 4,
 210
 211         /* keep last */
 212         ATH10K_FW_HTT_OP_VERSION_MAX,
 213 };
 214
 215 enum ath10k_bd_ie_type {
 216         /* contains sub IEs of enum ath10k_bd_ie_board_type */
 217         ATH10K_BD_IE_BOARD = 0,
 218 };
 219
 220 enum ath10k_bd_ie_board_type {
 221         ATH10K_BD_IE_BOARD_NAME = 0,
 222         ATH10K_BD_IE_BOARD_DATA = 1,
 223 };
 224
 225 enum ath10k_hw_rev {
 226         ATH10K_HW_QCA988X,
 227         ATH10K_HW_QCA6174,
 228         ATH10K_HW_QCA99X0,
 229         ATH10K_HW_QCA9888,
 230         ATH10K_HW_QCA9984,
 231         ATH10K_HW_QCA9377,
 232         ATH10K_HW_QCA4019,
 233         ATH10K_HW_QCA9887,
 234         ATH10K_HW_WCN3990,
 235 };
 236
 237 struct ath10k_hw_regs {
 238         u32 rtc_soc_base_address;
 239         u32 rtc_wmac_base_address;
 240         u32 soc_core_base_address;
 241         u32 wlan_mac_base_address;
 242         u32 ce_wrapper_base_address;
 243         u32 ce0_base_address;
 244         u32 ce1_base_address;
 245         u32 ce2_base_address;
 246         u32 ce3_base_address;
 247         u32 ce4_base_address;
 248         u32 ce5_base_address;
 249         u32 ce6_base_address;
 250         u32 ce7_base_address;
 251         u32 ce8_base_address;
 252         u32 ce9_base_address;
 253         u32 ce10_base_address;
 254         u32 ce11_base_address;
 255         u32 soc_reset_control_si0_rst_mask;
 256         u32 soc_reset_control_ce_rst_mask;
 257         u32 soc_chip_id_address;
 258         u32 scratch_3_address;
 259         u32 fw_indicator_address;
 260         u32 pcie_local_base_address;
 261         u32 ce_wrap_intr_sum_host_msi_lsb;
 262         u32 ce_wrap_intr_sum_host_msi_mask;
 263         u32 pcie_intr_fw_mask;
 264         u32 pcie_intr_ce_mask_all;
 265         u32 pcie_intr_clr_address;
 266         u32 cpu_pll_init_address;
 267         u32 cpu_speed_address;
 268         u32 core_clk_div_address;
 269 };
 270
 271 extern const struct ath10k_hw_regs qca988x_regs;
 272 extern const struct ath10k_hw_regs qca6174_regs;
 273 extern const struct ath10k_hw_regs qca99x0_regs;
 274 extern const struct ath10k_hw_regs qca4019_regs;
 275 extern const struct ath10k_hw_regs wcn3990_regs;
 276
 277 struct ath10k_hw_ce_regs_addr_map {
 278         u32 msb;
 279         u32 lsb;
 280         u32 mask;
 281 };
 282
 283 struct ath10k_hw_ce_ctrl1 {
 284         u32 addr;
 285         u32 hw_mask;
 286         u32 sw_mask;
 287         u32 hw_wr_mask;
 288         u32 sw_wr_mask;
 289         u32 reset_mask;
 290         u32 reset;
 291         struct ath10k_hw_ce_regs_addr_map *src_ring;
 292         struct ath10k_hw_ce_regs_addr_map *dst_ring;
 293         struct ath10k_hw_ce_regs_addr_map *dmax; };
 294
 295 struct ath10k_hw_ce_cmd_halt {
 296         u32 status_reset;
 297         u32 msb;
 298         u32 mask;
 299         struct ath10k_hw_ce_regs_addr_map *status; };
 300
 301 struct ath10k_hw_ce_host_ie {
 302         u32 copy_complete_reset;
 303         struct ath10k_hw_ce_regs_addr_map *copy_complete; };
 304
 305 struct ath10k_hw_ce_host_wm_regs {
 306         u32 dstr_lmask;
 307         u32 dstr_hmask;
 308         u32 srcr_lmask;
 309         u32 srcr_hmask;
 310         u32 cc_mask;
 311         u32 wm_mask;
 312         u32 addr;
 313 };
 314
 315 struct ath10k_hw_ce_misc_regs {
 316         u32 axi_err;
 317         u32 dstr_add_err;
 318         u32 srcr_len_err;
 319         u32 dstr_mlen_vio;
 320         u32 dstr_overflow;
 321         u32 srcr_overflow;
 322         u32 err_mask;
 323         u32 addr;
 324 };
 325
 326 struct ath10k_hw_ce_dst_src_wm_regs {
 327         u32 addr;
 328         u32 low_rst;
 329         u32 high_rst;
 330         struct ath10k_hw_ce_regs_addr_map *wm_low;
 331         struct ath10k_hw_ce_regs_addr_map *wm_high; };
 332
 333 struct ath10k_hw_ce_regs {
 334         u32 sr_base_addr;
 335         u32 sr_size_addr;
 336         u32 dr_base_addr;
 337         u32 dr_size_addr;
 338         u32 ce_cmd_addr;
 339         u32 misc_ie_addr;
 340         u32 sr_wr_index_addr;
 341         u32 dst_wr_index_addr;
 342         u32 current_srri_addr;
 343         u32 current_drri_addr;
 344         u32 ddr_addr_for_rri_low;
 345         u32 ddr_addr_for_rri_high;
 346         u32 ce_rri_low;
 347         u32 ce_rri_high;
 348         u32 host_ie_addr;
 349         struct ath10k_hw_ce_host_wm_regs *wm_regs;
 350         struct ath10k_hw_ce_misc_regs *misc_regs;
 351         struct ath10k_hw_ce_ctrl1 *ctrl1_regs;
 352         struct ath10k_hw_ce_cmd_halt *cmd_halt;
 353         struct ath10k_hw_ce_host_ie *host_ie;
 354         struct ath10k_hw_ce_dst_src_wm_regs *wm_srcr;
 355         struct ath10k_hw_ce_dst_src_wm_regs *wm_dstr; };
 356
 357 struct ath10k_hw_values {
 358         u32 rtc_state_val_on;
 359         u8 ce_count;
 360         u8 msi_assign_ce_max;
 361         u8 num_target_ce_config_wlan;
 362         u16 ce_desc_meta_data_mask;
 363         u8 ce_desc_meta_data_lsb;
 364 };
 365
 366 extern const struct ath10k_hw_values qca988x_values;
 367 extern const struct ath10k_hw_values qca6174_values;
 368 extern const struct ath10k_hw_values qca99x0_values;
 369 extern const struct ath10k_hw_values qca9888_values;
 370 extern const struct ath10k_hw_values qca4019_values;
 371 extern const struct ath10k_hw_values wcn3990_values;
 372 extern struct ath10k_hw_ce_regs wcn3990_ce_regs;
 373 extern struct ath10k_hw_ce_regs qcax_ce_regs;
 374
 375 void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
 376                                 u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev);
 377
 378 #define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X)
 379 #define QCA_REV_9887(ar) ((ar)->hw_rev == ATH10K_HW_QCA9887)
 380 #define QCA_REV_6174(ar) ((ar)->hw_rev == ATH10K_HW_QCA6174)
 381 #define QCA_REV_99X0(ar) ((ar)->hw_rev == ATH10K_HW_QCA99X0)
 382 #define QCA_REV_9888(ar) ((ar)->hw_rev == ATH10K_HW_QCA9888)
 383 #define QCA_REV_9984(ar) ((ar)->hw_rev == ATH10K_HW_QCA9984)
 384 #define QCA_REV_9377(ar) ((ar)->hw_rev == ATH10K_HW_QCA9377)
 385 #define QCA_REV_40XX(ar) ((ar)->hw_rev == ATH10K_HW_QCA4019)
 386 #define QCA_REV_WCN3990(ar) ((ar)->hw_rev == ATH10K_HW_WCN3990)
 387
 388 /* Known peculiarities:
 389  *  - raw appears in nwifi decap, raw and nwifi appear in ethernet decap
 390  *  - raw have FCS, nwifi doesn't
 391  *  - ethernet frames have 802.11 header decapped and parts (base hdr, cipher
 392  *    param, llc/snap) are aligned to 4byte boundaries each
 393  */
 394 enum ath10k_hw_txrx_mode {
 395         ATH10K_HW_TXRX_RAW = 0,
 396
 397         /* Native Wifi decap mode is used to align IP frames to 4-byte
 398          * boundaries and avoid a very expensive re-alignment in mac80211.
 399          */
 400         ATH10K_HW_TXRX_NATIVE_WIFI = 1,
 401         ATH10K_HW_TXRX_ETHERNET = 2,
 402
 403         /* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */
 404         ATH10K_HW_TXRX_MGMT = 3,
 405 };
 406
 407 enum ath10k_mcast2ucast_mode {
 408         ATH10K_MCAST2UCAST_DISABLED = 0,
 409         ATH10K_MCAST2UCAST_ENABLED = 1,
 410 };
 411
 412 enum ath10k_hw_rate_ofdm {
 413         ATH10K_HW_RATE_OFDM_48M = 0,
 414         ATH10K_HW_RATE_OFDM_24M,
 415         ATH10K_HW_RATE_OFDM_12M,
 416         ATH10K_HW_RATE_OFDM_6M,
 417         ATH10K_HW_RATE_OFDM_54M,
 418         ATH10K_HW_RATE_OFDM_36M,
 419         ATH10K_HW_RATE_OFDM_18M,
 420         ATH10K_HW_RATE_OFDM_9M,
 421 };
 422
 423 enum ath10k_hw_rate_cck {
 424         ATH10K_HW_RATE_CCK_LP_11M = 0,
 425         ATH10K_HW_RATE_CCK_LP_5_5M,
 426         ATH10K_HW_RATE_CCK_LP_2M,
 427         ATH10K_HW_RATE_CCK_LP_1M,
 428         ATH10K_HW_RATE_CCK_SP_11M,
 429         ATH10K_HW_RATE_CCK_SP_5_5M,
 430         ATH10K_HW_RATE_CCK_SP_2M,
 431 };
 432
 433 enum ath10k_hw_rate_rev2_cck {
 434         ATH10K_HW_RATE_REV2_CCK_LP_1M = 1,
 435         ATH10K_HW_RATE_REV2_CCK_LP_2M,
 436         ATH10K_HW_RATE_REV2_CCK_LP_5_5M,
 437         ATH10K_HW_RATE_REV2_CCK_LP_11M,
 438         ATH10K_HW_RATE_REV2_CCK_SP_2M,
 439         ATH10K_HW_RATE_REV2_CCK_SP_5_5M,
 440         ATH10K_HW_RATE_REV2_CCK_SP_11M,
 441 };
 442
 443 enum ath10k_hw_cc_wraparound_type {
 444         ATH10K_HW_CC_WRAP_DISABLED = 0,
 445
 446         /* This type is when the HW chip has a quirky Cycle Counter
 447          * wraparound which resets to 0x7fffffff instead of 0. All
 448          * other CC related counters (e.g. Rx Clear Count) are divided
 449          * by 2 so they never wraparound themselves.
 450          */
 451         ATH10K_HW_CC_WRAP_SHIFTED_ALL = 1,
 452
 453         /* Each hw counter wrapsaround independently. When the
 454          * counter overflows the repestive counter is right shifted
 455          * by 1, i.e reset to 0x7fffffff, and other counters will be
 456          * running unaffected. In this type of wraparound, it should
 457          * be possible to report accurate Rx busy time unlike the
 458          * first type.
 459          */
 460         ATH10K_HW_CC_WRAP_SHIFTED_EACH = 2,
 461 };
 462
 463 enum ath10k_hw_refclk_speed {
 464         ATH10K_HW_REFCLK_UNKNOWN = -1,
 465         ATH10K_HW_REFCLK_48_MHZ = 0,
 466         ATH10K_HW_REFCLK_19_2_MHZ = 1,
 467         ATH10K_HW_REFCLK_24_MHZ = 2,
 468         ATH10K_HW_REFCLK_26_MHZ = 3,
 469         ATH10K_HW_REFCLK_37_4_MHZ = 4,
 470         ATH10K_HW_REFCLK_38_4_MHZ = 5,
 471         ATH10K_HW_REFCLK_40_MHZ = 6,
 472         ATH10K_HW_REFCLK_52_MHZ = 7,
 473
 474         /* must be the last one */
 475         ATH10K_HW_REFCLK_COUNT,
 476 };
 477
 478 struct ath10k_hw_clk_params {
 479         u32 refclk;
 480         u32 div;
 481         u32 rnfrac;
 482         u32 settle_time;
 483         u32 refdiv;
 484         u32 outdiv;
 485 };
 486
 487 struct ath10k_hw_params {
 488         u32 id;
 489         u16 dev_id;
 490         const char *name;
 491         u32 patch_load_addr;
 492         int uart_pin;
 493         u32 otp_exe_param;
 494
 495         /* Type of hw cycle counter wraparound logic, for more info
 496          * refer enum ath10k_hw_cc_wraparound_type.
 497          */
 498         enum ath10k_hw_cc_wraparound_type cc_wraparound_type;
 499
 500         /* Some of chip expects fragment descriptor to be continuous
 501          * memory for any TX operation. Set continuous_frag_desc flag
 502          * for the hardware which have such requirement.
 503          */
 504         bool continuous_frag_desc;
 505
 506         /* CCK hardware rate table mapping for the newer chipsets
 507          * like QCA99X0, QCA4019 got revised. The CCK h/w rate values
 508          * are in a proper order with respect to the rate/preamble
 509          */
 510         bool cck_rate_map_rev2;
 511
 512         u32 channel_counters_freq_hz;
 513
 514         /* Mgmt tx descriptors threshold for limiting probe response
 515          * frames.
 516          */
 517         u32 max_probe_resp_desc_thres;
 518
 519         u32 tx_chain_mask;
 520         u32 rx_chain_mask;
 521         u32 max_spatial_stream;
 522         u32 cal_data_len;
 523
 524         struct ath10k_hw_params_fw {
 525                 const char *dir;
 526                 const char *board;
 527                 size_t board_size;
 528                 size_t board_ext_size;
 529         } fw;
 530
 531         /* qca99x0 family chips deliver broadcast/multicast management
 532          * frames encrypted and expect software do decryption.
 533          */
 534         bool sw_decrypt_mcast_mgmt;
 535
 536         const struct ath10k_hw_ops *hw_ops;
 537
 538         /* Number of bytes used for alignment in rx_hdr_status of rx desc. */
 539         int decap_align_bytes;
 540
 541         /* hw specific clock control parameters */
 542         const struct ath10k_hw_clk_params *hw_clk;
 543         int target_cpu_freq;
 544
 545         /* Number of bytes to be discarded for each FFT sample */
 546         int spectral_bin_discard;
 547
 548         /* The board may have a restricted NSS for 160 or 80+80 vs what it
 549          * can do for 80Mhz.
 550          */
 551         int vht160_mcs_rx_highest;
 552         int vht160_mcs_tx_highest;
 553 };
 554
 555 struct htt_rx_desc;
 556
 557 /* Defines needed for Rx descriptor abstraction */
 558 struct ath10k_hw_ops {
 559         int (*rx_desc_get_l3_pad_bytes)(struct htt_rx_desc *rxd);
 560         void (*set_coverage_class)(struct ath10k *ar, s16 value);
 561         int (*enable_pll_clk)(struct ath10k *ar);
 562 };
 563
 564 extern const struct ath10k_hw_ops qca988x_ops;
 565 extern const struct ath10k_hw_ops qca99x0_ops;
 566 extern const struct ath10k_hw_ops qca6174_ops;
 567
 568 extern const struct ath10k_hw_clk_params qca6174_clk[];
 569
 570 static inline int
 571 ath10k_rx_desc_get_l3_pad_bytes(struct ath10k_hw_params *hw,
 572                                 struct htt_rx_desc *rxd)
 573 {
 574         if (hw->hw_ops->rx_desc_get_l3_pad_bytes)
 575                 return hw->hw_ops->rx_desc_get_l3_pad_bytes(rxd);
 576         return 0;
 577 }
 578
 579 /* Target specific defines for MAIN firmware */
 580 #define TARGET_NUM_VDEVS                        8
 581 #define TARGET_NUM_PEER_AST                     2
 582 #define TARGET_NUM_WDS_ENTRIES                  32
 583 #define TARGET_DMA_BURST_SIZE                   0
 584 #define TARGET_MAC_AGGR_DELIM                   0
 585 #define TARGET_AST_SKID_LIMIT                   16
 586 #define TARGET_NUM_STATIONS                     16
 587 #define TARGET_NUM_PEERS                        ((TARGET_NUM_STATIONS) + \
 588                                                  (TARGET_NUM_VDEVS))
 589 #define TARGET_NUM_OFFLOAD_PEERS                0
 590 #define TARGET_NUM_OFFLOAD_REORDER_BUFS         0
 591 #define TARGET_NUM_PEER_KEYS                    2
 592 #define TARGET_NUM_TIDS                         ((TARGET_NUM_PEERS) * 2)
 593 #define TARGET_TX_CHAIN_MASK                    (BIT(0) | BIT(1) | BIT(2))
 594 #define TARGET_RX_CHAIN_MASK                    (BIT(0) | BIT(1) | BIT(2))
 595 #define TARGET_RX_TIMEOUT_LO_PRI                100
 596 #define TARGET_RX_TIMEOUT_HI_PRI                40
 597
 598 #define TARGET_SCAN_MAX_PENDING_REQS            4
 599 #define TARGET_BMISS_OFFLOAD_MAX_VDEV           3
 600 #define TARGET_ROAM_OFFLOAD_MAX_VDEV            3
 601 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES     8
 602 #define TARGET_GTK_OFFLOAD_MAX_VDEV             3
 603 #define TARGET_NUM_MCAST_GROUPS                 0
 604 #define TARGET_NUM_MCAST_TABLE_ELEMS            0
 605 #define TARGET_MCAST2UCAST_MODE                 ATH10K_MCAST2UCAST_DISABLED
 606 #define TARGET_TX_DBG_LOG_SIZE                  1024
 607 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0
 608 #define TARGET_VOW_CONFIG                       0
 609 #define TARGET_NUM_MSDU_DESC                    (1024 + 400)
 610 #define TARGET_MAX_FRAG_ENTRIES                 0
 611
 612 /* Target specific defines for 10.X firmware */
 613 #define TARGET_10X_NUM_VDEVS                    16
 614 #define TARGET_10X_NUM_PEER_AST                 2
 615 #define TARGET_10X_NUM_WDS_ENTRIES              32
 616 #define TARGET_10X_DMA_BURST_SIZE               0
 617 #define TARGET_10X_MAC_AGGR_DELIM               0
 618 #define TARGET_10X_AST_SKID_LIMIT               128
 619 #define TARGET_10X_NUM_STATIONS                 128
 620 #define TARGET_10X_TX_STATS_NUM_STATIONS        118
 621 #define TARGET_10X_NUM_PEERS                    ((TARGET_10X_NUM_STATIONS) + \
 622                                                  (TARGET_10X_NUM_VDEVS))
 623 #define TARGET_10X_TX_STATS_NUM_PEERS           ((TARGET_10X_TX_STATS_NUM_STATIONS) + \
 624                                                  (TARGET_10X_NUM_VDEVS))
 625 #define TARGET_10X_NUM_OFFLOAD_PEERS            0
 626 #define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS     0
 627 #define TARGET_10X_NUM_PEER_KEYS                2
 628 #define TARGET_10X_NUM_TIDS_MAX                 256
 629 #define TARGET_10X_NUM_TIDS                     min((TARGET_10X_NUM_TIDS_MAX), \
 630                                                     (TARGET_10X_NUM_PEERS) * 2)
 631 #define TARGET_10X_TX_STATS_NUM_TIDS            min((TARGET_10X_NUM_TIDS_MAX), \
 632                                                     (TARGET_10X_TX_STATS_NUM_PEERS) * 2)
 633 #define TARGET_10X_TX_CHAIN_MASK                (BIT(0) | BIT(1) | BIT(2))
 634 #define TARGET_10X_RX_CHAIN_MASK                (BIT(0) | BIT(1) | BIT(2))
 635 #define TARGET_10X_RX_TIMEOUT_LO_PRI            100
 636 #define TARGET_10X_RX_TIMEOUT_HI_PRI            40
 637 #define TARGET_10X_SCAN_MAX_PENDING_REQS        4
 638 #define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV       2
 639 #define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV        2
 640 #define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES 8
 641 #define TARGET_10X_GTK_OFFLOAD_MAX_VDEV         3
 642 #define TARGET_10X_NUM_MCAST_GROUPS             0
 643 #define TARGET_10X_NUM_MCAST_TABLE_ELEMS        0
 644 #define TARGET_10X_MCAST2UCAST_MODE             ATH10K_MCAST2UCAST_DISABLED
 645 #define TARGET_10X_TX_DBG_LOG_SIZE              1024
 646 #define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
 647 #define TARGET_10X_VOW_CONFIG                   0
 648 #define TARGET_10X_NUM_MSDU_DESC                (1024 + 400)
 649 #define TARGET_10X_MAX_FRAG_ENTRIES             0
 650
 651 /* 10.2 parameters */
 652 #define TARGET_10_2_DMA_BURST_SIZE              0
 653
 654 /* Target specific defines for WMI-TLV firmware */
 655 #define TARGET_TLV_NUM_VDEVS                    4
 656 #define TARGET_TLV_NUM_STATIONS                 32
 657 #define TARGET_TLV_NUM_PEERS                    33
 658 #define TARGET_TLV_NUM_TDLS_VDEVS               1
 659 #define TARGET_TLV_NUM_TIDS                     ((TARGET_TLV_NUM_PEERS) * 2)
 660 #define TARGET_TLV_NUM_MSDU_DESC                (1024 + 32)
 661 #define TARGET_TLV_NUM_WOW_PATTERNS             22
 662
 663 /* Diagnostic Window */
 664 #define CE_DIAG_PIPE    7
 665
 666 #define NUM_TARGET_CE_CONFIG_WLAN ar->hw_values->num_target_ce_config_wlan
 667
 668 /* Target specific defines for 10.4 firmware */
 669 #define TARGET_10_4_NUM_VDEVS                   16
 670 #define TARGET_10_4_NUM_STATIONS                32
 671 #define TARGET_10_4_NUM_PEERS                   ((TARGET_10_4_NUM_STATIONS) + \
 672                                                  (TARGET_10_4_NUM_VDEVS))
 673 #define TARGET_10_4_ACTIVE_PEERS                0
 674
 675 #define TARGET_10_4_NUM_QCACHE_PEERS_MAX        512
 676 #define TARGET_10_4_QCACHE_ACTIVE_PEERS         50
 677 #define TARGET_10_4_QCACHE_ACTIVE_PEERS_PFC     35
 678 #define TARGET_10_4_NUM_OFFLOAD_PEERS           0
 679 #define TARGET_10_4_NUM_OFFLOAD_REORDER_BUFFS   0
 680 #define TARGET_10_4_NUM_PEER_KEYS               2
 681 #define TARGET_10_4_TGT_NUM_TIDS                ((TARGET_10_4_NUM_PEERS) * 2)
 682 #define TARGET_10_4_NUM_MSDU_DESC               (1024 + 400)
 683 #define TARGET_10_4_NUM_MSDU_DESC_PFC           2500
 684 #define TARGET_10_4_AST_SKID_LIMIT              32
 685
 686 /* 100 ms for video, best-effort, and background */
 687 #define TARGET_10_4_RX_TIMEOUT_LO_PRI           100
 688
 689 /* 40 ms for voice */
 690 #define TARGET_10_4_RX_TIMEOUT_HI_PRI           40
 691
 692 #define TARGET_10_4_RX_DECAP_MODE               ATH10K_HW_TXRX_NATIVE_WIFI
 693 #define TARGET_10_4_SCAN_MAX_REQS               4
 694 #define TARGET_10_4_BMISS_OFFLOAD_MAX_VDEV      3
 695 #define TARGET_10_4_ROAM_OFFLOAD_MAX_VDEV       3
 696 #define TARGET_10_4_ROAM_OFFLOAD_MAX_PROFILES   8
 697
 698 /* Note: mcast to ucast is disabled by default */
 699 #define TARGET_10_4_NUM_MCAST_GROUPS            0
 700 #define TARGET_10_4_NUM_MCAST_TABLE_ELEMS       0
 701 #define TARGET_10_4_MCAST2UCAST_MODE            0
 702
 703 #define TARGET_10_4_TX_DBG_LOG_SIZE             1024
 704 #define TARGET_10_4_NUM_WDS_ENTRIES             32
 705 #define TARGET_10_4_DMA_BURST_SIZE              0
 706 #define TARGET_10_4_MAC_AGGR_DELIM              0
 707 #define TARGET_10_4_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
 708 #define TARGET_10_4_VOW_CONFIG                  0
 709 #define TARGET_10_4_GTK_OFFLOAD_MAX_VDEV        3
 710 #define TARGET_10_4_11AC_TX_MAX_FRAGS           2
 711 #define TARGET_10_4_MAX_PEER_EXT_STATS          16
 712 #define TARGET_10_4_SMART_ANT_CAP               0
 713 #define TARGET_10_4_BK_MIN_FREE                 0
 714 #define TARGET_10_4_BE_MIN_FREE                 0
 715 #define TARGET_10_4_VI_MIN_FREE                 0
 716 #define TARGET_10_4_VO_MIN_FREE                 0
 717 #define TARGET_10_4_RX_BATCH_MODE               1
 718 #define TARGET_10_4_THERMAL_THROTTLING_CONFIG   0
 719 #define TARGET_10_4_ATF_CONFIG                  0
 720 #define TARGET_10_4_IPHDR_PAD_CONFIG            1
 721 #define TARGET_10_4_QWRAP_CONFIG                0
 722
 723 /* TDLS config */
 724 #define TARGET_10_4_NUM_TDLS_VDEVS              1
 725 #define TARGET_10_4_NUM_TDLS_BUFFER_STA         1
 726 #define TARGET_10_4_NUM_TDLS_SLEEP_STA          1
 727
 728 /* Maximum number of Copy Engine's supported */
 729 #define CE_COUNT_MAX 12
 730
 731 /* Number of Copy Engines supported */
 732 #define CE_COUNT ar->hw_values->ce_count
 733
 734 /*
 735  * Granted MSIs are assigned as follows:
 736  * Firmware uses the first
 737  * Remaining MSIs, if any, are used by Copy Engines
 738  * This mapping is known to both Target firmware and Host software.
 739  * It may be changed as long as Host and Target are kept in sync.
 740  */
 741 /* MSI for firmware (errors, etc.) */
 742 #define MSI_ASSIGN_FW           0
 743
 744 /* MSIs for Copy Engines */
 745 #define MSI_ASSIGN_CE_INITIAL   1
 746 #define MSI_ASSIGN_CE_MAX       ar->hw_values->msi_assign_ce_max
 747
 748 /* as of IP3.7.1 */
 749 #define RTC_STATE_V_ON                          ar->hw_values->rtc_state_val_on
 750
 751 #define RTC_STATE_V_LSB                         0
 752 #define RTC_STATE_V_MASK                        0x00000007
 753 #define RTC_STATE_ADDRESS                       0x0000
 754 #define PCIE_SOC_WAKE_V_MASK                    0x00000001
 755 #define PCIE_SOC_WAKE_ADDRESS                   0x0004
 756 #define PCIE_SOC_WAKE_RESET                     0x00000000
 757 #define SOC_GLOBAL_RESET_ADDRESS                0x0008
 758
 759 #define RTC_SOC_BASE_ADDRESS                    ar->regs->rtc_soc_base_address
 760 #define RTC_WMAC_BASE_ADDRESS                   ar->regs->rtc_wmac_base_address
 761 #define MAC_COEX_BASE_ADDRESS                   0x00006000
 762 #define BT_COEX_BASE_ADDRESS                    0x00007000
 763 #define SOC_PCIE_BASE_ADDRESS                   0x00008000
 764 #define SOC_CORE_BASE_ADDRESS                   ar->regs->soc_core_base_address
 765 #define WLAN_UART_BASE_ADDRESS                  0x0000c000
 766 #define WLAN_SI_BASE_ADDRESS                    0x00010000
 767 #define WLAN_GPIO_BASE_ADDRESS                  0x00014000
 768 #define WLAN_ANALOG_INTF_BASE_ADDRESS           0x0001c000
 769 #define WLAN_MAC_BASE_ADDRESS                   ar->regs->wlan_mac_base_address
 770 #define EFUSE_BASE_ADDRESS                      0x00030000
 771 #define FPGA_REG_BASE_ADDRESS                   0x00039000
 772 #define WLAN_UART2_BASE_ADDRESS                 0x00054c00
 773 #define CE_WRAPPER_BASE_ADDRESS                 ar->regs->ce_wrapper_base_address
 774 #define CE0_BASE_ADDRESS                        ar->regs->ce0_base_address
 775 #define CE1_BASE_ADDRESS                        ar->regs->ce1_base_address
 776 #define CE2_BASE_ADDRESS                        ar->regs->ce2_base_address
 777 #define CE3_BASE_ADDRESS                        ar->regs->ce3_base_address
 778 #define CE4_BASE_ADDRESS                        ar->regs->ce4_base_address
 779 #define CE5_BASE_ADDRESS                        ar->regs->ce5_base_address
 780 #define CE6_BASE_ADDRESS                        ar->regs->ce6_base_address
 781 #define CE7_BASE_ADDRESS                        ar->regs->ce7_base_address
 782 #define DBI_BASE_ADDRESS                        0x00060000
 783 #define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS      0x0006c000
 784 #define PCIE_LOCAL_BASE_ADDRESS         ar->regs->pcie_local_base_address
 785
 786 #define SOC_RESET_CONTROL_ADDRESS               0x00000000
 787 #define SOC_RESET_CONTROL_OFFSET                0x00000000
 788 #define SOC_RESET_CONTROL_SI0_RST_MASK          ar->regs->soc_reset_control_si0_rst_mask
 789 #define SOC_RESET_CONTROL_CE_RST_MASK           ar->regs->soc_reset_control_ce_rst_mask
 790 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK     0x00000040
 791 #define SOC_CPU_CLOCK_OFFSET                    0x00000020
 792 #define SOC_CPU_CLOCK_STANDARD_LSB              0
 793 #define SOC_CPU_CLOCK_STANDARD_MASK             0x00000003
 794 #define SOC_CLOCK_CONTROL_OFFSET                0x00000028
 795 #define SOC_CLOCK_CONTROL_SI0_CLK_MASK          0x00000001
 796 #define SOC_SYSTEM_SLEEP_OFFSET                 0x000000c4
 797 #define SOC_LPO_CAL_OFFSET                      0x000000e0
 798 #define SOC_LPO_CAL_ENABLE_LSB                  20
 799 #define SOC_LPO_CAL_ENABLE_MASK                 0x00100000
 800 #define SOC_LF_TIMER_CONTROL0_ADDRESS           0x00000050
 801 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK       0x00000004
 802
 803 #define SOC_CHIP_ID_ADDRESS                     ar->regs->soc_chip_id_address
 804 #define SOC_CHIP_ID_REV_LSB                     8
 805 #define SOC_CHIP_ID_REV_MASK                    0x00000f00
 806
 807 #define WLAN_RESET_CONTROL_COLD_RST_MASK        0x00000008
 808 #define WLAN_RESET_CONTROL_WARM_RST_MASK        0x00000004
 809 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB           0
 810 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK          0x00000001
 811
 812 #define WLAN_GPIO_PIN0_ADDRESS                  0x00000028
 813 #define WLAN_GPIO_PIN0_CONFIG_LSB               11
 814 #define WLAN_GPIO_PIN0_CONFIG_MASK              0x00007800
 815 #define WLAN_GPIO_PIN0_PAD_PULL_LSB             5
 816 #define WLAN_GPIO_PIN0_PAD_PULL_MASK            0x00000060
 817 #define WLAN_GPIO_PIN1_ADDRESS                  0x0000002c
 818 #define WLAN_GPIO_PIN1_CONFIG_MASK              0x00007800
 819 #define WLAN_GPIO_PIN10_ADDRESS                 0x00000050
 820 #define WLAN_GPIO_PIN11_ADDRESS                 0x00000054
 821 #define WLAN_GPIO_PIN12_ADDRESS                 0x00000058
 822 #define WLAN_GPIO_PIN13_ADDRESS                 0x0000005c
 823
 824 #define CLOCK_GPIO_OFFSET                       0xffffffff
 825 #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB            0
 826 #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK           0
 827
 828 #define SI_CONFIG_OFFSET                        0x00000000
 829 #define SI_CONFIG_ERR_INT_LSB                   19
 830 #define SI_CONFIG_ERR_INT_MASK                  0x00080000
 831 #define SI_CONFIG_BIDIR_OD_DATA_LSB             18
 832 #define SI_CONFIG_BIDIR_OD_DATA_MASK            0x00040000
 833 #define SI_CONFIG_I2C_LSB                       16
 834 #define SI_CONFIG_I2C_MASK                      0x00010000
 835 #define SI_CONFIG_POS_SAMPLE_LSB                7
 836 #define SI_CONFIG_POS_SAMPLE_MASK               0x00000080
 837 #define SI_CONFIG_INACTIVE_DATA_LSB             5
 838 #define SI_CONFIG_INACTIVE_DATA_MASK            0x00000020
 839 #define SI_CONFIG_INACTIVE_CLK_LSB              4
 840 #define SI_CONFIG_INACTIVE_CLK_MASK             0x00000010
 841 #define SI_CONFIG_DIVIDER_LSB                   0
 842 #define SI_CONFIG_DIVIDER_MASK                  0x0000000f
 843 #define SI_CS_OFFSET                            0x00000004
 844 #define SI_CS_DONE_ERR_LSB                      10
 845 #define SI_CS_DONE_ERR_MASK                     0x00000400
 846 #define SI_CS_DONE_INT_LSB                      9
 847 #define SI_CS_DONE_INT_MASK                     0x00000200
 848 #define SI_CS_START_LSB                         8
 849 #define SI_CS_START_MASK                        0x00000100
 850 #define SI_CS_RX_CNT_LSB                        4
 851 #define SI_CS_RX_CNT_MASK                       0x000000f0
 852 #define SI_CS_TX_CNT_LSB                        0
 853 #define SI_CS_TX_CNT_MASK                       0x0000000f
 854
 855 #define SI_TX_DATA0_OFFSET                      0x00000008
 856 #define SI_TX_DATA1_OFFSET                      0x0000000c
 857 #define SI_RX_DATA0_OFFSET                      0x00000010
 858 #define SI_RX_DATA1_OFFSET                      0x00000014
 859
 860 #define CORE_CTRL_CPU_INTR_MASK                 0x00002000
 861 #define CORE_CTRL_PCIE_REG_31_MASK              0x00000800
 862 #define CORE_CTRL_ADDRESS                       0x0000
 863 #define PCIE_INTR_ENABLE_ADDRESS                0x0008
 864 #define PCIE_INTR_CAUSE_ADDRESS                 0x000c
 865 #define PCIE_INTR_CLR_ADDRESS                   ar->regs->pcie_intr_clr_address
 866 #define SCRATCH_3_ADDRESS                       ar->regs->scratch_3_address
 867 #define CPU_INTR_ADDRESS                        0x0010
 868
 869 #define CCNT_TO_MSEC(ar, x) ((x) / ar->hw_params.channel_counters_freq_hz)
 870
 871 /* Firmware indications to the Host via SCRATCH_3 register. */
 872 #define FW_INDICATOR_ADDRESS                    ar->regs->fw_indicator_address
 873 #define FW_IND_EVENT_PENDING                    1
 874 #define FW_IND_INITIALIZED                      2
 875 #define FW_IND_HOST_READY                       0x80000000
 876
 877 /* HOST_REG interrupt from firmware */
 878 #define PCIE_INTR_FIRMWARE_MASK                 ar->regs->pcie_intr_fw_mask
 879 #define PCIE_INTR_CE_MASK_ALL                   ar->regs->pcie_intr_ce_mask_all
 880
 881 #define DRAM_BASE_ADDRESS                       0x00400000
 882
 883 #define PCIE_BAR_REG_ADDRESS                    0x40030
 884
 885 #define MISSING 0
 886
 887 #define SYSTEM_SLEEP_OFFSET                     SOC_SYSTEM_SLEEP_OFFSET
 888 #define WLAN_SYSTEM_SLEEP_OFFSET                SOC_SYSTEM_SLEEP_OFFSET
 889 #define WLAN_RESET_CONTROL_OFFSET               SOC_RESET_CONTROL_OFFSET
 890 #define CLOCK_CONTROL_OFFSET                    SOC_CLOCK_CONTROL_OFFSET
 891 #define CLOCK_CONTROL_SI0_CLK_MASK              SOC_CLOCK_CONTROL_SI0_CLK_MASK
 892 #define RESET_CONTROL_MBOX_RST_MASK             MISSING
 893 #define RESET_CONTROL_SI0_RST_MASK              SOC_RESET_CONTROL_SI0_RST_MASK
 894 #define GPIO_BASE_ADDRESS                       WLAN_GPIO_BASE_ADDRESS
 895 #define GPIO_PIN0_OFFSET                        WLAN_GPIO_PIN0_ADDRESS
 896 #define GPIO_PIN1_OFFSET                        WLAN_GPIO_PIN1_ADDRESS
 897 #define GPIO_PIN0_CONFIG_LSB                    WLAN_GPIO_PIN0_CONFIG_LSB
 898 #define GPIO_PIN0_CONFIG_MASK                   WLAN_GPIO_PIN0_CONFIG_MASK
 899 #define GPIO_PIN0_PAD_PULL_LSB                  WLAN_GPIO_PIN0_PAD_PULL_LSB
 900 #define GPIO_PIN0_PAD_PULL_MASK                 WLAN_GPIO_PIN0_PAD_PULL_MASK
 901 #define GPIO_PIN1_CONFIG_MASK                   WLAN_GPIO_PIN1_CONFIG_MASK
 902 #define SI_BASE_ADDRESS                         WLAN_SI_BASE_ADDRESS
 903 #define SCRATCH_BASE_ADDRESS                    SOC_CORE_BASE_ADDRESS
 904 #define LOCAL_SCRATCH_OFFSET                    0x18
 905 #define CPU_CLOCK_OFFSET                        SOC_CPU_CLOCK_OFFSET
 906 #define LPO_CAL_OFFSET                          SOC_LPO_CAL_OFFSET
 907 #define GPIO_PIN10_OFFSET                       WLAN_GPIO_PIN10_ADDRESS
 908 #define GPIO_PIN11_OFFSET                       WLAN_GPIO_PIN11_ADDRESS
 909 #define GPIO_PIN12_OFFSET                       WLAN_GPIO_PIN12_ADDRESS
 910 #define GPIO_PIN13_OFFSET                       WLAN_GPIO_PIN13_ADDRESS
 911 #define CPU_CLOCK_STANDARD_LSB                  SOC_CPU_CLOCK_STANDARD_LSB
 912 #define CPU_CLOCK_STANDARD_MASK                 SOC_CPU_CLOCK_STANDARD_MASK
 913 #define LPO_CAL_ENABLE_LSB                      SOC_LPO_CAL_ENABLE_LSB
 914 #define LPO_CAL_ENABLE_MASK                     SOC_LPO_CAL_ENABLE_MASK
 915 #define ANALOG_INTF_BASE_ADDRESS                WLAN_ANALOG_INTF_BASE_ADDRESS
 916 #define MBOX_BASE_ADDRESS                       MISSING
 917 #define INT_STATUS_ENABLE_ERROR_LSB             MISSING
 918 #define INT_STATUS_ENABLE_ERROR_MASK            MISSING
 919 #define INT_STATUS_ENABLE_CPU_LSB               MISSING
 920 #define INT_STATUS_ENABLE_CPU_MASK              MISSING
 921 #define INT_STATUS_ENABLE_COUNTER_LSB           MISSING
 922 #define INT_STATUS_ENABLE_COUNTER_MASK          MISSING
 923 #define INT_STATUS_ENABLE_MBOX_DATA_LSB         MISSING
 924 #define INT_STATUS_ENABLE_MBOX_DATA_MASK        MISSING
 925 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB    MISSING
 926 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK   MISSING
 927 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB     MISSING
 928 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK    MISSING
 929 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB       MISSING
 930 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK      MISSING
 931 #define INT_STATUS_ENABLE_ADDRESS               MISSING
 932 #define CPU_INT_STATUS_ENABLE_BIT_LSB           MISSING
 933 #define CPU_INT_STATUS_ENABLE_BIT_MASK          MISSING
 934 #define HOST_INT_STATUS_ADDRESS                 MISSING
 935 #define CPU_INT_STATUS_ADDRESS                  MISSING
 936 #define ERROR_INT_STATUS_ADDRESS                MISSING
 937 #define ERROR_INT_STATUS_WAKEUP_MASK            MISSING
 938 #define ERROR_INT_STATUS_WAKEUP_LSB             MISSING
 939 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK      MISSING
 940 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB       MISSING
 941 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK       MISSING
 942 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB        MISSING
 943 #define COUNT_DEC_ADDRESS                       MISSING
 944 #define HOST_INT_STATUS_CPU_MASK                MISSING
 945 #define HOST_INT_STATUS_CPU_LSB                 MISSING
 946 #define HOST_INT_STATUS_ERROR_MASK              MISSING
 947 #define HOST_INT_STATUS_ERROR_LSB               MISSING
 948 #define HOST_INT_STATUS_COUNTER_MASK            MISSING
 949 #define HOST_INT_STATUS_COUNTER_LSB             MISSING
 950 #define RX_LOOKAHEAD_VALID_ADDRESS              MISSING
 951 #define WINDOW_DATA_ADDRESS                     MISSING
 952 #define WINDOW_READ_ADDR_ADDRESS                MISSING
 953 #define WINDOW_WRITE_ADDR_ADDRESS               MISSING
 954
 955 #define QCA9887_1_0_I2C_SDA_GPIO_PIN            5
 956 #define QCA9887_1_0_I2C_SDA_PIN_CONFIG          3
 957 #define QCA9887_1_0_SI_CLK_GPIO_PIN             17
 958 #define QCA9887_1_0_SI_CLK_PIN_CONFIG           3
 959 #define QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS 0x00000010
 960
 961 #define QCA9887_EEPROM_SELECT_READ              0xa10000a0
 962 #define QCA9887_EEPROM_ADDR_HI_MASK             0x0000ff00
 963 #define QCA9887_EEPROM_ADDR_HI_LSB              8
 964 #define QCA9887_EEPROM_ADDR_LO_MASK             0x00ff0000
 965 #define QCA9887_EEPROM_ADDR_LO_LSB              16
 966
 967 #define MBOX_RESET_CONTROL_ADDRESS              0x00000000
 968 #define MBOX_HOST_INT_STATUS_ADDRESS            0x00000800
 969 #define MBOX_HOST_INT_STATUS_ERROR_LSB          7
 970 #define MBOX_HOST_INT_STATUS_ERROR_MASK         0x00000080
 971 #define MBOX_HOST_INT_STATUS_CPU_LSB            6
 972 #define MBOX_HOST_INT_STATUS_CPU_MASK           0x00000040
 973 #define MBOX_HOST_INT_STATUS_COUNTER_LSB        4
 974 #define MBOX_HOST_INT_STATUS_COUNTER_MASK       0x00000010
 975 #define MBOX_CPU_INT_STATUS_ADDRESS             0x00000801
 976 #define MBOX_ERROR_INT_STATUS_ADDRESS           0x00000802
 977 #define MBOX_ERROR_INT_STATUS_WAKEUP_LSB        2
 978 #define MBOX_ERROR_INT_STATUS_WAKEUP_MASK       0x00000004
 979 #define MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_LSB  1
 980 #define MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002
 981 #define MBOX_ERROR_INT_STATUS_TX_OVERFLOW_LSB   0
 982 #define MBOX_ERROR_INT_STATUS_TX_OVERFLOW_MASK  0x00000001
 983 #define MBOX_COUNTER_INT_STATUS_ADDRESS         0x00000803
 984 #define MBOX_COUNTER_INT_STATUS_COUNTER_LSB     0
 985 #define MBOX_COUNTER_INT_STATUS_COUNTER_MASK    0x000000ff
 986 #define MBOX_RX_LOOKAHEAD_VALID_ADDRESS         0x00000805
 987 #define MBOX_INT_STATUS_ENABLE_ADDRESS          0x00000828
 988 #define MBOX_INT_STATUS_ENABLE_ERROR_LSB        7
 989 #define MBOX_INT_STATUS_ENABLE_ERROR_MASK       0x00000080
 990 #define MBOX_INT_STATUS_ENABLE_CPU_LSB          6
 991 #define MBOX_INT_STATUS_ENABLE_CPU_MASK         0x00000040
 992 #define MBOX_INT_STATUS_ENABLE_INT_LSB          5
 993 #define MBOX_INT_STATUS_ENABLE_INT_MASK         0x00000020
 994 #define MBOX_INT_STATUS_ENABLE_COUNTER_LSB      4
 995 #define MBOX_INT_STATUS_ENABLE_COUNTER_MASK     0x00000010
 996 #define MBOX_INT_STATUS_ENABLE_MBOX_DATA_LSB    0
 997 #define MBOX_INT_STATUS_ENABLE_MBOX_DATA_MASK   0x0000000f
 998 #define MBOX_CPU_INT_STATUS_ENABLE_ADDRESS      0x00000819
 999 #define MBOX_CPU_INT_STATUS_ENABLE_BIT_LSB      0
1000 #define MBOX_CPU_INT_STATUS_ENABLE_BIT_MASK     0x000000ff
1001 #define MBOX_ERROR_STATUS_ENABLE_ADDRESS        0x0000081a
1002 #define MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB  1
1003 #define MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002
1004 #define MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB   0
1005 #define MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK  0x00000001
1006 #define MBOX_COUNTER_INT_STATUS_ENABLE_ADDRESS  0x0000081b
1007 #define MBOX_COUNTER_INT_STATUS_ENABLE_BIT_LSB  0
1008 #define MBOX_COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
1009 #define MBOX_COUNT_ADDRESS                      0x00000820
1010 #define MBOX_COUNT_DEC_ADDRESS                  0x00000840
1011 #define MBOX_WINDOW_DATA_ADDRESS                0x00000874
1012 #define MBOX_WINDOW_WRITE_ADDR_ADDRESS          0x00000878
1013 #define MBOX_WINDOW_READ_ADDR_ADDRESS           0x0000087c
1014 #define MBOX_CPU_DBG_SEL_ADDRESS                0x00000883
1015 #define MBOX_CPU_DBG_ADDRESS                    0x00000884
1016 #define MBOX_RTC_BASE_ADDRESS                   0x00000000
1017 #define MBOX_GPIO_BASE_ADDRESS                  0x00005000
1018 #define MBOX_MBOX_BASE_ADDRESS                  0x00008000
1019
1020 #define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB)
1021
1022 /* Register definitions for first generation ath10k cards. These cards include
1023  * a mac thich has a register allocation similar to ath9k and at least some
1024  * registers including the ones relevant for modifying the coverage class are
1025  * identical to the ath9k definitions.
1026  * These registers are usually managed by the ath10k firmware. However by
1027  * overriding them it is possible to support coverage class modifications.
1028  */
1029 #define WAVE1_PCU_ACK_CTS_TIMEOUT               0x8014
1030 #define WAVE1_PCU_ACK_CTS_TIMEOUT_MAX           0x00003FFF
1031 #define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_MASK      0x00003FFF
1032 #define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_LSB       0
1033 #define WAVE1_PCU_ACK_CTS_TIMEOUT_CTS_MASK      0x3FFF0000
1034 #define WAVE1_PCU_ACK_CTS_TIMEOUT_CTS_LSB       16
1035
1036 #define WAVE1_PCU_GBL_IFS_SLOT                  0x1070
1037 #define WAVE1_PCU_GBL_IFS_SLOT_MASK             0x0000FFFF
1038 #define WAVE1_PCU_GBL_IFS_SLOT_MAX              0x0000FFFF
1039 #define WAVE1_PCU_GBL_IFS_SLOT_LSB              0
1040 #define WAVE1_PCU_GBL_IFS_SLOT_RESV0            0xFFFF0000
1041
1042 #define WAVE1_PHYCLK                            0x801C
1043 #define WAVE1_PHYCLK_USEC_MASK                  0x0000007F
1044 #define WAVE1_PHYCLK_USEC_LSB                   0
1045
1046 /* qca6174 PLL offset/mask */
1047 #define SOC_CORE_CLK_CTRL_OFFSET                0x00000114
1048 #define SOC_CORE_CLK_CTRL_DIV_LSB               0
1049 #define SOC_CORE_CLK_CTRL_DIV_MASK              0x00000007
1050
1051 #define EFUSE_OFFSET                            0x0000032c
1052 #define EFUSE_XTAL_SEL_LSB                      8
1053 #define EFUSE_XTAL_SEL_MASK                     0x00000700
1054
1055 #define BB_PLL_CONFIG_OFFSET                    0x000002f4
1056 #define BB_PLL_CONFIG_FRAC_LSB                  0
1057 #define BB_PLL_CONFIG_FRAC_MASK                 0x0003ffff
1058 #define BB_PLL_CONFIG_OUTDIV_LSB                18
1059 #define BB_PLL_CONFIG_OUTDIV_MASK               0x001c0000
1060
1061 #define WLAN_PLL_SETTLE_OFFSET                  0x0018
1062 #define WLAN_PLL_SETTLE_TIME_LSB                0
1063 #define WLAN_PLL_SETTLE_TIME_MASK               0x000007ff
1064
1065 #define WLAN_PLL_CONTROL_OFFSET                 0x0014
1066 #define WLAN_PLL_CONTROL_DIV_LSB                0
1067 #define WLAN_PLL_CONTROL_DIV_MASK               0x000003ff
1068 #define WLAN_PLL_CONTROL_REFDIV_LSB             10
1069 #define WLAN_PLL_CONTROL_REFDIV_MASK            0x00003c00
1070 #define WLAN_PLL_CONTROL_BYPASS_LSB             16
1071 #define WLAN_PLL_CONTROL_BYPASS_MASK            0x00010000
1072 #define WLAN_PLL_CONTROL_NOPWD_LSB              18
1073 #define WLAN_PLL_CONTROL_NOPWD_MASK             0x00040000
1074
1075 #define RTC_SYNC_STATUS_OFFSET                  0x0244
1076 #define RTC_SYNC_STATUS_PLL_CHANGING_LSB        5
1077 #define RTC_SYNC_STATUS_PLL_CHANGING_MASK       0x00000020
1078 /* qca6174 PLL offset/mask end */
1079
1080 #endif /* _HW_H_ */