2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/sched.h>
36 #include <linux/slab.h>
37 #include <linux/export.h>
38 #include <linux/pci.h>
39 #include <linux/errno.h>
41 #include <linux/mlx4/cmd.h>
42 #include <linux/mlx4/device.h>
43 #include <linux/semaphore.h>
44 #include <rdma/ib_smi.h>
51 #define CMD_POLL_TOKEN 0xffff
52 #define INBOX_MASK 0xffffffffffffff00ULL
54 #define CMD_CHAN_VER 1
55 #define CMD_CHAN_IF_REV 1
58 /* command completed successfully: */
60 /* Internal error (such as a bus error) occurred while processing command: */
61 CMD_STAT_INTERNAL_ERR
= 0x01,
62 /* Operation/command not supported or opcode modifier not supported: */
63 CMD_STAT_BAD_OP
= 0x02,
64 /* Parameter not supported or parameter out of range: */
65 CMD_STAT_BAD_PARAM
= 0x03,
66 /* System not enabled or bad system state: */
67 CMD_STAT_BAD_SYS_STATE
= 0x04,
68 /* Attempt to access reserved or unallocaterd resource: */
69 CMD_STAT_BAD_RESOURCE
= 0x05,
70 /* Requested resource is currently executing a command, or is otherwise busy: */
71 CMD_STAT_RESOURCE_BUSY
= 0x06,
72 /* Required capability exceeds device limits: */
73 CMD_STAT_EXCEED_LIM
= 0x08,
74 /* Resource is not in the appropriate state or ownership: */
75 CMD_STAT_BAD_RES_STATE
= 0x09,
76 /* Index out of range: */
77 CMD_STAT_BAD_INDEX
= 0x0a,
78 /* FW image corrupted: */
79 CMD_STAT_BAD_NVMEM
= 0x0b,
80 /* Error in ICM mapping (e.g. not enough auxiliary ICM pages to execute command): */
81 CMD_STAT_ICM_ERROR
= 0x0c,
82 /* Attempt to modify a QP/EE which is not in the presumed state: */
83 CMD_STAT_BAD_QP_STATE
= 0x10,
84 /* Bad segment parameters (Address/Size): */
85 CMD_STAT_BAD_SEG_PARAM
= 0x20,
86 /* Memory Region has Memory Windows bound to: */
87 CMD_STAT_REG_BOUND
= 0x21,
88 /* HCA local attached memory not present: */
89 CMD_STAT_LAM_NOT_PRE
= 0x22,
90 /* Bad management packet (silently discarded): */
91 CMD_STAT_BAD_PKT
= 0x30,
92 /* More outstanding CQEs in CQ than new CQ size: */
93 CMD_STAT_BAD_SIZE
= 0x40,
94 /* Multi Function device support required: */
95 CMD_STAT_MULTI_FUNC_REQ
= 0x50,
99 HCR_IN_PARAM_OFFSET
= 0x00,
100 HCR_IN_MODIFIER_OFFSET
= 0x08,
101 HCR_OUT_PARAM_OFFSET
= 0x0c,
102 HCR_TOKEN_OFFSET
= 0x14,
103 HCR_STATUS_OFFSET
= 0x18,
105 HCR_OPMOD_SHIFT
= 12,
112 GO_BIT_TIMEOUT_MSECS
= 10000
115 enum mlx4_vlan_transition
{
116 MLX4_VLAN_TRANSITION_VST_VST
= 0,
117 MLX4_VLAN_TRANSITION_VST_VGT
= 1,
118 MLX4_VLAN_TRANSITION_VGT_VST
= 2,
119 MLX4_VLAN_TRANSITION_VGT_VGT
= 3,
123 struct mlx4_cmd_context
{
124 struct completion done
;
132 static int mlx4_master_process_vhcr(struct mlx4_dev
*dev
, int slave
,
133 struct mlx4_vhcr_cmd
*in_vhcr
);
135 static int mlx4_status_to_errno(u8 status
)
137 static const int trans_table
[] = {
138 [CMD_STAT_INTERNAL_ERR
] = -EIO
,
139 [CMD_STAT_BAD_OP
] = -EPERM
,
140 [CMD_STAT_BAD_PARAM
] = -EINVAL
,
141 [CMD_STAT_BAD_SYS_STATE
] = -ENXIO
,
142 [CMD_STAT_BAD_RESOURCE
] = -EBADF
,
143 [CMD_STAT_RESOURCE_BUSY
] = -EBUSY
,
144 [CMD_STAT_EXCEED_LIM
] = -ENOMEM
,
145 [CMD_STAT_BAD_RES_STATE
] = -EBADF
,
146 [CMD_STAT_BAD_INDEX
] = -EBADF
,
147 [CMD_STAT_BAD_NVMEM
] = -EFAULT
,
148 [CMD_STAT_ICM_ERROR
] = -ENFILE
,
149 [CMD_STAT_BAD_QP_STATE
] = -EINVAL
,
150 [CMD_STAT_BAD_SEG_PARAM
] = -EFAULT
,
151 [CMD_STAT_REG_BOUND
] = -EBUSY
,
152 [CMD_STAT_LAM_NOT_PRE
] = -EAGAIN
,
153 [CMD_STAT_BAD_PKT
] = -EINVAL
,
154 [CMD_STAT_BAD_SIZE
] = -ENOMEM
,
155 [CMD_STAT_MULTI_FUNC_REQ
] = -EACCES
,
158 if (status
>= ARRAY_SIZE(trans_table
) ||
159 (status
!= CMD_STAT_OK
&& trans_table
[status
] == 0))
162 return trans_table
[status
];
165 static u8
mlx4_errno_to_status(int errno
)
169 return CMD_STAT_BAD_OP
;
171 return CMD_STAT_BAD_PARAM
;
173 return CMD_STAT_BAD_SYS_STATE
;
175 return CMD_STAT_RESOURCE_BUSY
;
177 return CMD_STAT_EXCEED_LIM
;
179 return CMD_STAT_ICM_ERROR
;
181 return CMD_STAT_INTERNAL_ERR
;
185 static int comm_pending(struct mlx4_dev
*dev
)
187 struct mlx4_priv
*priv
= mlx4_priv(dev
);
188 u32 status
= readl(&priv
->mfunc
.comm
->slave_read
);
190 return (swab32(status
) >> 31) != priv
->cmd
.comm_toggle
;
193 static void mlx4_comm_cmd_post(struct mlx4_dev
*dev
, u8 cmd
, u16 param
)
195 struct mlx4_priv
*priv
= mlx4_priv(dev
);
198 priv
->cmd
.comm_toggle
^= 1;
199 val
= param
| (cmd
<< 16) | (priv
->cmd
.comm_toggle
<< 31);
200 __raw_writel((__force u32
) cpu_to_be32(val
),
201 &priv
->mfunc
.comm
->slave_write
);
205 static int mlx4_comm_cmd_poll(struct mlx4_dev
*dev
, u8 cmd
, u16 param
,
206 unsigned long timeout
)
208 struct mlx4_priv
*priv
= mlx4_priv(dev
);
211 int ret_from_pending
= 0;
213 /* First, verify that the master reports correct status */
214 if (comm_pending(dev
)) {
215 mlx4_warn(dev
, "Communication channel is not idle - my toggle is %d (cmd:0x%x)\n",
216 priv
->cmd
.comm_toggle
, cmd
);
221 down(&priv
->cmd
.poll_sem
);
222 mlx4_comm_cmd_post(dev
, cmd
, param
);
224 end
= msecs_to_jiffies(timeout
) + jiffies
;
225 while (comm_pending(dev
) && time_before(jiffies
, end
))
227 ret_from_pending
= comm_pending(dev
);
228 if (ret_from_pending
) {
229 /* check if the slave is trying to boot in the middle of
230 * FLR process. The only non-zero result in the RESET command
231 * is MLX4_DELAY_RESET_SLAVE*/
232 if ((MLX4_COMM_CMD_RESET
== cmd
)) {
233 err
= MLX4_DELAY_RESET_SLAVE
;
235 mlx4_warn(dev
, "Communication channel timed out\n");
240 up(&priv
->cmd
.poll_sem
);
244 static int mlx4_comm_cmd_wait(struct mlx4_dev
*dev
, u8 op
,
245 u16 param
, unsigned long timeout
)
247 struct mlx4_cmd
*cmd
= &mlx4_priv(dev
)->cmd
;
248 struct mlx4_cmd_context
*context
;
252 down(&cmd
->event_sem
);
254 spin_lock(&cmd
->context_lock
);
255 BUG_ON(cmd
->free_head
< 0);
256 context
= &cmd
->context
[cmd
->free_head
];
257 context
->token
+= cmd
->token_mask
+ 1;
258 cmd
->free_head
= context
->next
;
259 spin_unlock(&cmd
->context_lock
);
261 init_completion(&context
->done
);
263 mlx4_comm_cmd_post(dev
, op
, param
);
265 if (!wait_for_completion_timeout(&context
->done
,
266 msecs_to_jiffies(timeout
))) {
267 mlx4_warn(dev
, "communication channel command 0x%x timed out\n",
273 err
= context
->result
;
274 if (err
&& context
->fw_status
!= CMD_STAT_MULTI_FUNC_REQ
) {
275 mlx4_err(dev
, "command 0x%x failed: fw status = 0x%x\n",
276 op
, context
->fw_status
);
281 /* wait for comm channel ready
282 * this is necessary for prevention the race
283 * when switching between event to polling mode
285 end
= msecs_to_jiffies(timeout
) + jiffies
;
286 while (comm_pending(dev
) && time_before(jiffies
, end
))
289 spin_lock(&cmd
->context_lock
);
290 context
->next
= cmd
->free_head
;
291 cmd
->free_head
= context
- cmd
->context
;
292 spin_unlock(&cmd
->context_lock
);
298 int mlx4_comm_cmd(struct mlx4_dev
*dev
, u8 cmd
, u16 param
,
299 unsigned long timeout
)
301 if (mlx4_priv(dev
)->cmd
.use_events
)
302 return mlx4_comm_cmd_wait(dev
, cmd
, param
, timeout
);
303 return mlx4_comm_cmd_poll(dev
, cmd
, param
, timeout
);
306 static int cmd_pending(struct mlx4_dev
*dev
)
310 if (pci_channel_offline(dev
->pdev
))
313 status
= readl(mlx4_priv(dev
)->cmd
.hcr
+ HCR_STATUS_OFFSET
);
315 return (status
& swab32(1 << HCR_GO_BIT
)) ||
316 (mlx4_priv(dev
)->cmd
.toggle
==
317 !!(status
& swab32(1 << HCR_T_BIT
)));
320 static int mlx4_cmd_post(struct mlx4_dev
*dev
, u64 in_param
, u64 out_param
,
321 u32 in_modifier
, u8 op_modifier
, u16 op
, u16 token
,
324 struct mlx4_cmd
*cmd
= &mlx4_priv(dev
)->cmd
;
325 u32 __iomem
*hcr
= cmd
->hcr
;
329 mutex_lock(&cmd
->hcr_mutex
);
331 if (pci_channel_offline(dev
->pdev
)) {
333 * Device is going through error recovery
334 * and cannot accept commands.
342 end
+= msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS
);
344 while (cmd_pending(dev
)) {
345 if (pci_channel_offline(dev
->pdev
)) {
347 * Device is going through error recovery
348 * and cannot accept commands.
354 if (time_after_eq(jiffies
, end
)) {
355 mlx4_err(dev
, "%s:cmd_pending failed\n", __func__
);
362 * We use writel (instead of something like memcpy_toio)
363 * because writes of less than 32 bits to the HCR don't work
364 * (and some architectures such as ia64 implement memcpy_toio
365 * in terms of writeb).
367 __raw_writel((__force u32
) cpu_to_be32(in_param
>> 32), hcr
+ 0);
368 __raw_writel((__force u32
) cpu_to_be32(in_param
& 0xfffffffful
), hcr
+ 1);
369 __raw_writel((__force u32
) cpu_to_be32(in_modifier
), hcr
+ 2);
370 __raw_writel((__force u32
) cpu_to_be32(out_param
>> 32), hcr
+ 3);
371 __raw_writel((__force u32
) cpu_to_be32(out_param
& 0xfffffffful
), hcr
+ 4);
372 __raw_writel((__force u32
) cpu_to_be32(token
<< 16), hcr
+ 5);
374 /* __raw_writel may not order writes. */
377 __raw_writel((__force u32
) cpu_to_be32((1 << HCR_GO_BIT
) |
378 (cmd
->toggle
<< HCR_T_BIT
) |
379 (event
? (1 << HCR_E_BIT
) : 0) |
380 (op_modifier
<< HCR_OPMOD_SHIFT
) |
384 * Make sure that our HCR writes don't get mixed in with
385 * writes from another CPU starting a FW command.
389 cmd
->toggle
= cmd
->toggle
^ 1;
394 mutex_unlock(&cmd
->hcr_mutex
);
398 static int mlx4_slave_cmd(struct mlx4_dev
*dev
, u64 in_param
, u64
*out_param
,
399 int out_is_imm
, u32 in_modifier
, u8 op_modifier
,
400 u16 op
, unsigned long timeout
)
402 struct mlx4_priv
*priv
= mlx4_priv(dev
);
403 struct mlx4_vhcr_cmd
*vhcr
= priv
->mfunc
.vhcr
;
406 mutex_lock(&priv
->cmd
.slave_cmd_mutex
);
408 vhcr
->in_param
= cpu_to_be64(in_param
);
409 vhcr
->out_param
= out_param
? cpu_to_be64(*out_param
) : 0;
410 vhcr
->in_modifier
= cpu_to_be32(in_modifier
);
411 vhcr
->opcode
= cpu_to_be16((((u16
) op_modifier
) << 12) | (op
& 0xfff));
412 vhcr
->token
= cpu_to_be16(CMD_POLL_TOKEN
);
414 vhcr
->flags
= !!(priv
->cmd
.use_events
) << 6;
416 if (mlx4_is_master(dev
)) {
417 ret
= mlx4_master_process_vhcr(dev
, dev
->caps
.function
, vhcr
);
422 be64_to_cpu(vhcr
->out_param
);
424 mlx4_err(dev
, "response expected while output mailbox is NULL for command 0x%x\n",
426 vhcr
->status
= CMD_STAT_BAD_PARAM
;
429 ret
= mlx4_status_to_errno(vhcr
->status
);
432 ret
= mlx4_comm_cmd(dev
, MLX4_COMM_CMD_VHCR_POST
, 0,
433 MLX4_COMM_TIME
+ timeout
);
438 be64_to_cpu(vhcr
->out_param
);
440 mlx4_err(dev
, "response expected while output mailbox is NULL for command 0x%x\n",
442 vhcr
->status
= CMD_STAT_BAD_PARAM
;
445 ret
= mlx4_status_to_errno(vhcr
->status
);
447 mlx4_err(dev
, "failed execution of VHCR_POST command opcode 0x%x\n",
451 mutex_unlock(&priv
->cmd
.slave_cmd_mutex
);
455 static int mlx4_cmd_poll(struct mlx4_dev
*dev
, u64 in_param
, u64
*out_param
,
456 int out_is_imm
, u32 in_modifier
, u8 op_modifier
,
457 u16 op
, unsigned long timeout
)
459 struct mlx4_priv
*priv
= mlx4_priv(dev
);
460 void __iomem
*hcr
= priv
->cmd
.hcr
;
465 down(&priv
->cmd
.poll_sem
);
467 if (pci_channel_offline(dev
->pdev
)) {
469 * Device is going through error recovery
470 * and cannot accept commands.
476 if (out_is_imm
&& !out_param
) {
477 mlx4_err(dev
, "response expected while output mailbox is NULL for command 0x%x\n",
483 err
= mlx4_cmd_post(dev
, in_param
, out_param
? *out_param
: 0,
484 in_modifier
, op_modifier
, op
, CMD_POLL_TOKEN
, 0);
488 end
= msecs_to_jiffies(timeout
) + jiffies
;
489 while (cmd_pending(dev
) && time_before(jiffies
, end
)) {
490 if (pci_channel_offline(dev
->pdev
)) {
492 * Device is going through error recovery
493 * and cannot accept commands.
502 if (cmd_pending(dev
)) {
503 mlx4_warn(dev
, "command 0x%x timed out (go bit not cleared)\n",
511 (u64
) be32_to_cpu((__force __be32
)
512 __raw_readl(hcr
+ HCR_OUT_PARAM_OFFSET
)) << 32 |
513 (u64
) be32_to_cpu((__force __be32
)
514 __raw_readl(hcr
+ HCR_OUT_PARAM_OFFSET
+ 4));
515 stat
= be32_to_cpu((__force __be32
)
516 __raw_readl(hcr
+ HCR_STATUS_OFFSET
)) >> 24;
517 err
= mlx4_status_to_errno(stat
);
519 mlx4_err(dev
, "command 0x%x failed: fw status = 0x%x\n",
523 up(&priv
->cmd
.poll_sem
);
527 void mlx4_cmd_event(struct mlx4_dev
*dev
, u16 token
, u8 status
, u64 out_param
)
529 struct mlx4_priv
*priv
= mlx4_priv(dev
);
530 struct mlx4_cmd_context
*context
=
531 &priv
->cmd
.context
[token
& priv
->cmd
.token_mask
];
533 /* previously timed out command completing at long last */
534 if (token
!= context
->token
)
537 context
->fw_status
= status
;
538 context
->result
= mlx4_status_to_errno(status
);
539 context
->out_param
= out_param
;
541 complete(&context
->done
);
544 static int mlx4_cmd_wait(struct mlx4_dev
*dev
, u64 in_param
, u64
*out_param
,
545 int out_is_imm
, u32 in_modifier
, u8 op_modifier
,
546 u16 op
, unsigned long timeout
)
548 struct mlx4_cmd
*cmd
= &mlx4_priv(dev
)->cmd
;
549 struct mlx4_cmd_context
*context
;
552 down(&cmd
->event_sem
);
554 spin_lock(&cmd
->context_lock
);
555 BUG_ON(cmd
->free_head
< 0);
556 context
= &cmd
->context
[cmd
->free_head
];
557 context
->token
+= cmd
->token_mask
+ 1;
558 cmd
->free_head
= context
->next
;
559 spin_unlock(&cmd
->context_lock
);
561 if (out_is_imm
&& !out_param
) {
562 mlx4_err(dev
, "response expected while output mailbox is NULL for command 0x%x\n",
568 init_completion(&context
->done
);
570 mlx4_cmd_post(dev
, in_param
, out_param
? *out_param
: 0,
571 in_modifier
, op_modifier
, op
, context
->token
, 1);
573 if (!wait_for_completion_timeout(&context
->done
,
574 msecs_to_jiffies(timeout
))) {
575 mlx4_warn(dev
, "command 0x%x timed out (go bit not cleared)\n",
581 err
= context
->result
;
583 /* Since we do not want to have this error message always
584 * displayed at driver start when there are ConnectX2 HCAs
585 * on the host, we deprecate the error message for this
586 * specific command/input_mod/opcode_mod/fw-status to be debug.
588 if (op
== MLX4_CMD_SET_PORT
&& in_modifier
== 1 &&
589 op_modifier
== 0 && context
->fw_status
== CMD_STAT_BAD_SIZE
)
590 mlx4_dbg(dev
, "command 0x%x failed: fw status = 0x%x\n",
591 op
, context
->fw_status
);
593 mlx4_err(dev
, "command 0x%x failed: fw status = 0x%x\n",
594 op
, context
->fw_status
);
599 *out_param
= context
->out_param
;
602 spin_lock(&cmd
->context_lock
);
603 context
->next
= cmd
->free_head
;
604 cmd
->free_head
= context
- cmd
->context
;
605 spin_unlock(&cmd
->context_lock
);
611 int __mlx4_cmd(struct mlx4_dev
*dev
, u64 in_param
, u64
*out_param
,
612 int out_is_imm
, u32 in_modifier
, u8 op_modifier
,
613 u16 op
, unsigned long timeout
, int native
)
615 if (pci_channel_offline(dev
->pdev
))
618 if (!mlx4_is_mfunc(dev
) || (native
&& mlx4_is_master(dev
))) {
619 if (mlx4_priv(dev
)->cmd
.use_events
)
620 return mlx4_cmd_wait(dev
, in_param
, out_param
,
621 out_is_imm
, in_modifier
,
622 op_modifier
, op
, timeout
);
624 return mlx4_cmd_poll(dev
, in_param
, out_param
,
625 out_is_imm
, in_modifier
,
626 op_modifier
, op
, timeout
);
628 return mlx4_slave_cmd(dev
, in_param
, out_param
, out_is_imm
,
629 in_modifier
, op_modifier
, op
, timeout
);
631 EXPORT_SYMBOL_GPL(__mlx4_cmd
);
634 static int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev
*dev
)
636 return mlx4_cmd(dev
, 0, 0, 0, MLX4_CMD_ARM_COMM_CHANNEL
,
637 MLX4_CMD_TIME_CLASS_B
, MLX4_CMD_NATIVE
);
640 static int mlx4_ACCESS_MEM(struct mlx4_dev
*dev
, u64 master_addr
,
641 int slave
, u64 slave_addr
,
642 int size
, int is_read
)
647 if ((slave_addr
& 0xfff) | (master_addr
& 0xfff) |
648 (slave
& ~0x7f) | (size
& 0xff)) {
649 mlx4_err(dev
, "Bad access mem params - slave_addr:0x%llx master_addr:0x%llx slave_id:%d size:%d\n",
650 slave_addr
, master_addr
, slave
, size
);
655 in_param
= (u64
) slave
| slave_addr
;
656 out_param
= (u64
) dev
->caps
.function
| master_addr
;
658 in_param
= (u64
) dev
->caps
.function
| master_addr
;
659 out_param
= (u64
) slave
| slave_addr
;
662 return mlx4_cmd_imm(dev
, in_param
, &out_param
, size
, 0,
664 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_NATIVE
);
667 static int query_pkey_block(struct mlx4_dev
*dev
, u8 port
, u16 index
, u16
*pkey
,
668 struct mlx4_cmd_mailbox
*inbox
,
669 struct mlx4_cmd_mailbox
*outbox
)
671 struct ib_smp
*in_mad
= (struct ib_smp
*)(inbox
->buf
);
672 struct ib_smp
*out_mad
= (struct ib_smp
*)(outbox
->buf
);
679 in_mad
->attr_mod
= cpu_to_be32(index
/ 32);
681 err
= mlx4_cmd_box(dev
, inbox
->dma
, outbox
->dma
, port
, 3,
682 MLX4_CMD_MAD_IFC
, MLX4_CMD_TIME_CLASS_C
,
687 for (i
= 0; i
< 32; ++i
)
688 pkey
[i
] = be16_to_cpu(((__be16
*) out_mad
->data
)[i
]);
693 static int get_full_pkey_table(struct mlx4_dev
*dev
, u8 port
, u16
*table
,
694 struct mlx4_cmd_mailbox
*inbox
,
695 struct mlx4_cmd_mailbox
*outbox
)
700 for (i
= 0; i
< dev
->caps
.pkey_table_len
[port
]; i
+= 32) {
701 err
= query_pkey_block(dev
, port
, i
, table
+ i
, inbox
, outbox
);
708 #define PORT_CAPABILITY_LOCATION_IN_SMP 20
709 #define PORT_STATE_OFFSET 32
711 static enum ib_port_state
vf_port_state(struct mlx4_dev
*dev
, int port
, int vf
)
713 if (mlx4_get_slave_port_state(dev
, vf
, port
) == SLAVE_PORT_UP
)
714 return IB_PORT_ACTIVE
;
719 static int mlx4_MAD_IFC_wrapper(struct mlx4_dev
*dev
, int slave
,
720 struct mlx4_vhcr
*vhcr
,
721 struct mlx4_cmd_mailbox
*inbox
,
722 struct mlx4_cmd_mailbox
*outbox
,
723 struct mlx4_cmd_info
*cmd
)
725 struct ib_smp
*smp
= inbox
->buf
;
733 struct mlx4_priv
*priv
= mlx4_priv(dev
);
734 struct ib_smp
*outsmp
= outbox
->buf
;
735 __be16
*outtab
= (__be16
*)(outsmp
->data
);
736 __be32 slave_cap_mask
;
737 __be64 slave_node_guid
;
739 port
= vhcr
->in_modifier
;
741 /* network-view bit is for driver use only, and should not be passed to FW */
742 opcode_modifier
= vhcr
->op_modifier
& ~0x8; /* clear netw view bit */
743 network_view
= !!(vhcr
->op_modifier
& 0x8);
745 if (smp
->base_version
== 1 &&
746 smp
->mgmt_class
== IB_MGMT_CLASS_SUBN_LID_ROUTED
&&
747 smp
->class_version
== 1) {
748 /* host view is paravirtualized */
749 if (!network_view
&& smp
->method
== IB_MGMT_METHOD_GET
) {
750 if (smp
->attr_id
== IB_SMP_ATTR_PKEY_TABLE
) {
751 index
= be32_to_cpu(smp
->attr_mod
);
752 if (port
< 1 || port
> dev
->caps
.num_ports
)
754 table
= kcalloc(dev
->caps
.pkey_table_len
[port
], sizeof *table
, GFP_KERNEL
);
757 /* need to get the full pkey table because the paravirtualized
758 * pkeys may be scattered among several pkey blocks.
760 err
= get_full_pkey_table(dev
, port
, table
, inbox
, outbox
);
762 for (vidx
= index
* 32; vidx
< (index
+ 1) * 32; ++vidx
) {
763 pidx
= priv
->virt2phys_pkey
[slave
][port
- 1][vidx
];
764 outtab
[vidx
% 32] = cpu_to_be16(table
[pidx
]);
770 if (smp
->attr_id
== IB_SMP_ATTR_PORT_INFO
) {
771 /*get the slave specific caps:*/
773 err
= mlx4_cmd_box(dev
, inbox
->dma
, outbox
->dma
,
774 vhcr
->in_modifier
, opcode_modifier
,
775 vhcr
->op
, MLX4_CMD_TIME_CLASS_C
, MLX4_CMD_NATIVE
);
776 /* modify the response for slaves */
777 if (!err
&& slave
!= mlx4_master_func_num(dev
)) {
778 u8
*state
= outsmp
->data
+ PORT_STATE_OFFSET
;
780 *state
= (*state
& 0xf0) | vf_port_state(dev
, port
, slave
);
781 slave_cap_mask
= priv
->mfunc
.master
.slave_state
[slave
].ib_cap_mask
[port
];
782 memcpy(outsmp
->data
+ PORT_CAPABILITY_LOCATION_IN_SMP
, &slave_cap_mask
, 4);
786 if (smp
->attr_id
== IB_SMP_ATTR_GUID_INFO
) {
787 /* compute slave's gid block */
788 smp
->attr_mod
= cpu_to_be32(slave
/ 8);
790 err
= mlx4_cmd_box(dev
, inbox
->dma
, outbox
->dma
,
791 vhcr
->in_modifier
, opcode_modifier
,
792 vhcr
->op
, MLX4_CMD_TIME_CLASS_C
, MLX4_CMD_NATIVE
);
794 /* if needed, move slave gid to index 0 */
797 outsmp
->data
+ (slave
% 8) * 8, 8);
798 /* delete all other gids */
799 memset(outsmp
->data
+ 8, 0, 56);
803 if (smp
->attr_id
== IB_SMP_ATTR_NODE_INFO
) {
804 err
= mlx4_cmd_box(dev
, inbox
->dma
, outbox
->dma
,
805 vhcr
->in_modifier
, opcode_modifier
,
806 vhcr
->op
, MLX4_CMD_TIME_CLASS_C
, MLX4_CMD_NATIVE
);
808 slave_node_guid
= mlx4_get_slave_node_guid(dev
, slave
);
809 memcpy(outsmp
->data
+ 12, &slave_node_guid
, 8);
816 /* Non-privileged VFs are only allowed "host" view LID-routed 'Get' MADs.
817 * These are the MADs used by ib verbs (such as ib_query_gids).
819 if (slave
!= mlx4_master_func_num(dev
) &&
820 !mlx4_vf_smi_enabled(dev
, slave
, port
)) {
821 if (!(smp
->mgmt_class
== IB_MGMT_CLASS_SUBN_LID_ROUTED
&&
822 smp
->method
== IB_MGMT_METHOD_GET
) || network_view
) {
823 mlx4_err(dev
, "Unprivileged slave %d is trying to execute a Subnet MGMT MAD, class 0x%x, method 0x%x, view=%s for attr 0x%x. Rejecting\n",
824 slave
, smp
->method
, smp
->mgmt_class
,
825 network_view
? "Network" : "Host",
826 be16_to_cpu(smp
->attr_id
));
831 return mlx4_cmd_box(dev
, inbox
->dma
, outbox
->dma
,
832 vhcr
->in_modifier
, opcode_modifier
,
833 vhcr
->op
, MLX4_CMD_TIME_CLASS_C
, MLX4_CMD_NATIVE
);
836 static int mlx4_CMD_EPERM_wrapper(struct mlx4_dev
*dev
, int slave
,
837 struct mlx4_vhcr
*vhcr
,
838 struct mlx4_cmd_mailbox
*inbox
,
839 struct mlx4_cmd_mailbox
*outbox
,
840 struct mlx4_cmd_info
*cmd
)
845 int mlx4_DMA_wrapper(struct mlx4_dev
*dev
, int slave
,
846 struct mlx4_vhcr
*vhcr
,
847 struct mlx4_cmd_mailbox
*inbox
,
848 struct mlx4_cmd_mailbox
*outbox
,
849 struct mlx4_cmd_info
*cmd
)
855 in_param
= cmd
->has_inbox
? (u64
) inbox
->dma
: vhcr
->in_param
;
856 out_param
= cmd
->has_outbox
? (u64
) outbox
->dma
: vhcr
->out_param
;
857 if (cmd
->encode_slave_id
) {
858 in_param
&= 0xffffffffffffff00ll
;
862 err
= __mlx4_cmd(dev
, in_param
, &out_param
, cmd
->out_is_imm
,
863 vhcr
->in_modifier
, vhcr
->op_modifier
, vhcr
->op
,
864 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_NATIVE
);
867 vhcr
->out_param
= out_param
;
872 static struct mlx4_cmd_info cmd_info
[] = {
874 .opcode
= MLX4_CMD_QUERY_FW
,
878 .encode_slave_id
= false,
880 .wrapper
= mlx4_QUERY_FW_wrapper
883 .opcode
= MLX4_CMD_QUERY_HCA
,
887 .encode_slave_id
= false,
892 .opcode
= MLX4_CMD_QUERY_DEV_CAP
,
896 .encode_slave_id
= false,
898 .wrapper
= mlx4_QUERY_DEV_CAP_wrapper
901 .opcode
= MLX4_CMD_QUERY_FUNC_CAP
,
905 .encode_slave_id
= false,
907 .wrapper
= mlx4_QUERY_FUNC_CAP_wrapper
910 .opcode
= MLX4_CMD_QUERY_ADAPTER
,
914 .encode_slave_id
= false,
919 .opcode
= MLX4_CMD_INIT_PORT
,
923 .encode_slave_id
= false,
925 .wrapper
= mlx4_INIT_PORT_wrapper
928 .opcode
= MLX4_CMD_CLOSE_PORT
,
932 .encode_slave_id
= false,
934 .wrapper
= mlx4_CLOSE_PORT_wrapper
937 .opcode
= MLX4_CMD_QUERY_PORT
,
941 .encode_slave_id
= false,
943 .wrapper
= mlx4_QUERY_PORT_wrapper
946 .opcode
= MLX4_CMD_SET_PORT
,
950 .encode_slave_id
= false,
952 .wrapper
= mlx4_SET_PORT_wrapper
955 .opcode
= MLX4_CMD_MAP_EQ
,
959 .encode_slave_id
= false,
961 .wrapper
= mlx4_MAP_EQ_wrapper
964 .opcode
= MLX4_CMD_SW2HW_EQ
,
968 .encode_slave_id
= true,
970 .wrapper
= mlx4_SW2HW_EQ_wrapper
973 .opcode
= MLX4_CMD_HW_HEALTH_CHECK
,
977 .encode_slave_id
= false,
982 .opcode
= MLX4_CMD_NOP
,
986 .encode_slave_id
= false,
991 .opcode
= MLX4_CMD_CONFIG_DEV
,
995 .encode_slave_id
= false,
997 .wrapper
= mlx4_CMD_EPERM_wrapper
1000 .opcode
= MLX4_CMD_ALLOC_RES
,
1002 .has_outbox
= false,
1004 .encode_slave_id
= false,
1006 .wrapper
= mlx4_ALLOC_RES_wrapper
1009 .opcode
= MLX4_CMD_FREE_RES
,
1011 .has_outbox
= false,
1012 .out_is_imm
= false,
1013 .encode_slave_id
= false,
1015 .wrapper
= mlx4_FREE_RES_wrapper
1018 .opcode
= MLX4_CMD_SW2HW_MPT
,
1020 .has_outbox
= false,
1021 .out_is_imm
= false,
1022 .encode_slave_id
= true,
1024 .wrapper
= mlx4_SW2HW_MPT_wrapper
1027 .opcode
= MLX4_CMD_QUERY_MPT
,
1030 .out_is_imm
= false,
1031 .encode_slave_id
= false,
1033 .wrapper
= mlx4_QUERY_MPT_wrapper
1036 .opcode
= MLX4_CMD_HW2SW_MPT
,
1038 .has_outbox
= false,
1039 .out_is_imm
= false,
1040 .encode_slave_id
= false,
1042 .wrapper
= mlx4_HW2SW_MPT_wrapper
1045 .opcode
= MLX4_CMD_READ_MTT
,
1048 .out_is_imm
= false,
1049 .encode_slave_id
= false,
1054 .opcode
= MLX4_CMD_WRITE_MTT
,
1056 .has_outbox
= false,
1057 .out_is_imm
= false,
1058 .encode_slave_id
= false,
1060 .wrapper
= mlx4_WRITE_MTT_wrapper
1063 .opcode
= MLX4_CMD_SYNC_TPT
,
1065 .has_outbox
= false,
1066 .out_is_imm
= false,
1067 .encode_slave_id
= false,
1072 .opcode
= MLX4_CMD_HW2SW_EQ
,
1075 .out_is_imm
= false,
1076 .encode_slave_id
= true,
1078 .wrapper
= mlx4_HW2SW_EQ_wrapper
1081 .opcode
= MLX4_CMD_QUERY_EQ
,
1084 .out_is_imm
= false,
1085 .encode_slave_id
= true,
1087 .wrapper
= mlx4_QUERY_EQ_wrapper
1090 .opcode
= MLX4_CMD_SW2HW_CQ
,
1092 .has_outbox
= false,
1093 .out_is_imm
= false,
1094 .encode_slave_id
= true,
1096 .wrapper
= mlx4_SW2HW_CQ_wrapper
1099 .opcode
= MLX4_CMD_HW2SW_CQ
,
1101 .has_outbox
= false,
1102 .out_is_imm
= false,
1103 .encode_slave_id
= false,
1105 .wrapper
= mlx4_HW2SW_CQ_wrapper
1108 .opcode
= MLX4_CMD_QUERY_CQ
,
1111 .out_is_imm
= false,
1112 .encode_slave_id
= false,
1114 .wrapper
= mlx4_QUERY_CQ_wrapper
1117 .opcode
= MLX4_CMD_MODIFY_CQ
,
1119 .has_outbox
= false,
1121 .encode_slave_id
= false,
1123 .wrapper
= mlx4_MODIFY_CQ_wrapper
1126 .opcode
= MLX4_CMD_SW2HW_SRQ
,
1128 .has_outbox
= false,
1129 .out_is_imm
= false,
1130 .encode_slave_id
= true,
1132 .wrapper
= mlx4_SW2HW_SRQ_wrapper
1135 .opcode
= MLX4_CMD_HW2SW_SRQ
,
1137 .has_outbox
= false,
1138 .out_is_imm
= false,
1139 .encode_slave_id
= false,
1141 .wrapper
= mlx4_HW2SW_SRQ_wrapper
1144 .opcode
= MLX4_CMD_QUERY_SRQ
,
1147 .out_is_imm
= false,
1148 .encode_slave_id
= false,
1150 .wrapper
= mlx4_QUERY_SRQ_wrapper
1153 .opcode
= MLX4_CMD_ARM_SRQ
,
1155 .has_outbox
= false,
1156 .out_is_imm
= false,
1157 .encode_slave_id
= false,
1159 .wrapper
= mlx4_ARM_SRQ_wrapper
1162 .opcode
= MLX4_CMD_RST2INIT_QP
,
1164 .has_outbox
= false,
1165 .out_is_imm
= false,
1166 .encode_slave_id
= true,
1168 .wrapper
= mlx4_RST2INIT_QP_wrapper
1171 .opcode
= MLX4_CMD_INIT2INIT_QP
,
1173 .has_outbox
= false,
1174 .out_is_imm
= false,
1175 .encode_slave_id
= false,
1177 .wrapper
= mlx4_INIT2INIT_QP_wrapper
1180 .opcode
= MLX4_CMD_INIT2RTR_QP
,
1182 .has_outbox
= false,
1183 .out_is_imm
= false,
1184 .encode_slave_id
= false,
1186 .wrapper
= mlx4_INIT2RTR_QP_wrapper
1189 .opcode
= MLX4_CMD_RTR2RTS_QP
,
1191 .has_outbox
= false,
1192 .out_is_imm
= false,
1193 .encode_slave_id
= false,
1195 .wrapper
= mlx4_RTR2RTS_QP_wrapper
1198 .opcode
= MLX4_CMD_RTS2RTS_QP
,
1200 .has_outbox
= false,
1201 .out_is_imm
= false,
1202 .encode_slave_id
= false,
1204 .wrapper
= mlx4_RTS2RTS_QP_wrapper
1207 .opcode
= MLX4_CMD_SQERR2RTS_QP
,
1209 .has_outbox
= false,
1210 .out_is_imm
= false,
1211 .encode_slave_id
= false,
1213 .wrapper
= mlx4_SQERR2RTS_QP_wrapper
1216 .opcode
= MLX4_CMD_2ERR_QP
,
1218 .has_outbox
= false,
1219 .out_is_imm
= false,
1220 .encode_slave_id
= false,
1222 .wrapper
= mlx4_GEN_QP_wrapper
1225 .opcode
= MLX4_CMD_RTS2SQD_QP
,
1227 .has_outbox
= false,
1228 .out_is_imm
= false,
1229 .encode_slave_id
= false,
1231 .wrapper
= mlx4_GEN_QP_wrapper
1234 .opcode
= MLX4_CMD_SQD2SQD_QP
,
1236 .has_outbox
= false,
1237 .out_is_imm
= false,
1238 .encode_slave_id
= false,
1240 .wrapper
= mlx4_SQD2SQD_QP_wrapper
1243 .opcode
= MLX4_CMD_SQD2RTS_QP
,
1245 .has_outbox
= false,
1246 .out_is_imm
= false,
1247 .encode_slave_id
= false,
1249 .wrapper
= mlx4_SQD2RTS_QP_wrapper
1252 .opcode
= MLX4_CMD_2RST_QP
,
1254 .has_outbox
= false,
1255 .out_is_imm
= false,
1256 .encode_slave_id
= false,
1258 .wrapper
= mlx4_2RST_QP_wrapper
1261 .opcode
= MLX4_CMD_QUERY_QP
,
1264 .out_is_imm
= false,
1265 .encode_slave_id
= false,
1267 .wrapper
= mlx4_GEN_QP_wrapper
1270 .opcode
= MLX4_CMD_SUSPEND_QP
,
1272 .has_outbox
= false,
1273 .out_is_imm
= false,
1274 .encode_slave_id
= false,
1276 .wrapper
= mlx4_GEN_QP_wrapper
1279 .opcode
= MLX4_CMD_UNSUSPEND_QP
,
1281 .has_outbox
= false,
1282 .out_is_imm
= false,
1283 .encode_slave_id
= false,
1285 .wrapper
= mlx4_GEN_QP_wrapper
1288 .opcode
= MLX4_CMD_UPDATE_QP
,
1290 .has_outbox
= false,
1291 .out_is_imm
= false,
1292 .encode_slave_id
= false,
1294 .wrapper
= mlx4_UPDATE_QP_wrapper
1297 .opcode
= MLX4_CMD_GET_OP_REQ
,
1299 .has_outbox
= false,
1300 .out_is_imm
= false,
1301 .encode_slave_id
= false,
1303 .wrapper
= mlx4_CMD_EPERM_wrapper
,
1306 .opcode
= MLX4_CMD_CONF_SPECIAL_QP
,
1308 .has_outbox
= false,
1309 .out_is_imm
= false,
1310 .encode_slave_id
= false,
1311 .verify
= NULL
, /* XXX verify: only demux can do this */
1315 .opcode
= MLX4_CMD_MAD_IFC
,
1318 .out_is_imm
= false,
1319 .encode_slave_id
= false,
1321 .wrapper
= mlx4_MAD_IFC_wrapper
1324 .opcode
= MLX4_CMD_MAD_DEMUX
,
1326 .has_outbox
= false,
1327 .out_is_imm
= false,
1328 .encode_slave_id
= false,
1330 .wrapper
= mlx4_CMD_EPERM_wrapper
1333 .opcode
= MLX4_CMD_QUERY_IF_STAT
,
1336 .out_is_imm
= false,
1337 .encode_slave_id
= false,
1339 .wrapper
= mlx4_QUERY_IF_STAT_wrapper
1342 .opcode
= MLX4_CMD_ACCESS_REG
,
1345 .out_is_imm
= false,
1346 .encode_slave_id
= false,
1350 /* Native multicast commands are not available for guests */
1352 .opcode
= MLX4_CMD_QP_ATTACH
,
1354 .has_outbox
= false,
1355 .out_is_imm
= false,
1356 .encode_slave_id
= false,
1358 .wrapper
= mlx4_QP_ATTACH_wrapper
1361 .opcode
= MLX4_CMD_PROMISC
,
1363 .has_outbox
= false,
1364 .out_is_imm
= false,
1365 .encode_slave_id
= false,
1367 .wrapper
= mlx4_PROMISC_wrapper
1369 /* Ethernet specific commands */
1371 .opcode
= MLX4_CMD_SET_VLAN_FLTR
,
1373 .has_outbox
= false,
1374 .out_is_imm
= false,
1375 .encode_slave_id
= false,
1377 .wrapper
= mlx4_SET_VLAN_FLTR_wrapper
1380 .opcode
= MLX4_CMD_SET_MCAST_FLTR
,
1382 .has_outbox
= false,
1383 .out_is_imm
= false,
1384 .encode_slave_id
= false,
1386 .wrapper
= mlx4_SET_MCAST_FLTR_wrapper
1389 .opcode
= MLX4_CMD_DUMP_ETH_STATS
,
1392 .out_is_imm
= false,
1393 .encode_slave_id
= false,
1395 .wrapper
= mlx4_DUMP_ETH_STATS_wrapper
1398 .opcode
= MLX4_CMD_INFORM_FLR_DONE
,
1400 .has_outbox
= false,
1401 .out_is_imm
= false,
1402 .encode_slave_id
= false,
1406 /* flow steering commands */
1408 .opcode
= MLX4_QP_FLOW_STEERING_ATTACH
,
1410 .has_outbox
= false,
1412 .encode_slave_id
= false,
1414 .wrapper
= mlx4_QP_FLOW_STEERING_ATTACH_wrapper
1417 .opcode
= MLX4_QP_FLOW_STEERING_DETACH
,
1419 .has_outbox
= false,
1420 .out_is_imm
= false,
1421 .encode_slave_id
= false,
1423 .wrapper
= mlx4_QP_FLOW_STEERING_DETACH_wrapper
1426 .opcode
= MLX4_FLOW_STEERING_IB_UC_QP_RANGE
,
1428 .has_outbox
= false,
1429 .out_is_imm
= false,
1430 .encode_slave_id
= false,
1432 .wrapper
= mlx4_CMD_EPERM_wrapper
1436 static int mlx4_master_process_vhcr(struct mlx4_dev
*dev
, int slave
,
1437 struct mlx4_vhcr_cmd
*in_vhcr
)
1439 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1440 struct mlx4_cmd_info
*cmd
= NULL
;
1441 struct mlx4_vhcr_cmd
*vhcr_cmd
= in_vhcr
? in_vhcr
: priv
->mfunc
.vhcr
;
1442 struct mlx4_vhcr
*vhcr
;
1443 struct mlx4_cmd_mailbox
*inbox
= NULL
;
1444 struct mlx4_cmd_mailbox
*outbox
= NULL
;
1451 /* Create sw representation of Virtual HCR */
1452 vhcr
= kzalloc(sizeof(struct mlx4_vhcr
), GFP_KERNEL
);
1456 /* DMA in the vHCR */
1458 ret
= mlx4_ACCESS_MEM(dev
, priv
->mfunc
.vhcr_dma
, slave
,
1459 priv
->mfunc
.master
.slave_state
[slave
].vhcr_dma
,
1460 ALIGN(sizeof(struct mlx4_vhcr_cmd
),
1461 MLX4_ACCESS_MEM_ALIGN
), 1);
1463 mlx4_err(dev
, "%s: Failed reading vhcr ret: 0x%x\n",
1470 /* Fill SW VHCR fields */
1471 vhcr
->in_param
= be64_to_cpu(vhcr_cmd
->in_param
);
1472 vhcr
->out_param
= be64_to_cpu(vhcr_cmd
->out_param
);
1473 vhcr
->in_modifier
= be32_to_cpu(vhcr_cmd
->in_modifier
);
1474 vhcr
->token
= be16_to_cpu(vhcr_cmd
->token
);
1475 vhcr
->op
= be16_to_cpu(vhcr_cmd
->opcode
) & 0xfff;
1476 vhcr
->op_modifier
= (u8
) (be16_to_cpu(vhcr_cmd
->opcode
) >> 12);
1477 vhcr
->e_bit
= vhcr_cmd
->flags
& (1 << 6);
1479 /* Lookup command */
1480 for (i
= 0; i
< ARRAY_SIZE(cmd_info
); ++i
) {
1481 if (vhcr
->op
== cmd_info
[i
].opcode
) {
1487 mlx4_err(dev
, "Unknown command:0x%x accepted from slave:%d\n",
1489 vhcr_cmd
->status
= CMD_STAT_BAD_PARAM
;
1494 if (cmd
->has_inbox
) {
1495 vhcr
->in_param
&= INBOX_MASK
;
1496 inbox
= mlx4_alloc_cmd_mailbox(dev
);
1497 if (IS_ERR(inbox
)) {
1498 vhcr_cmd
->status
= CMD_STAT_BAD_SIZE
;
1503 if (mlx4_ACCESS_MEM(dev
, inbox
->dma
, slave
,
1505 MLX4_MAILBOX_SIZE
, 1)) {
1506 mlx4_err(dev
, "%s: Failed reading inbox (cmd:0x%x)\n",
1507 __func__
, cmd
->opcode
);
1508 vhcr_cmd
->status
= CMD_STAT_INTERNAL_ERR
;
1513 /* Apply permission and bound checks if applicable */
1514 if (cmd
->verify
&& cmd
->verify(dev
, slave
, vhcr
, inbox
)) {
1515 mlx4_warn(dev
, "Command:0x%x from slave: %d failed protection checks for resource_id:%d\n",
1516 vhcr
->op
, slave
, vhcr
->in_modifier
);
1517 vhcr_cmd
->status
= CMD_STAT_BAD_OP
;
1521 /* Allocate outbox */
1522 if (cmd
->has_outbox
) {
1523 outbox
= mlx4_alloc_cmd_mailbox(dev
);
1524 if (IS_ERR(outbox
)) {
1525 vhcr_cmd
->status
= CMD_STAT_BAD_SIZE
;
1531 /* Execute the command! */
1533 err
= cmd
->wrapper(dev
, slave
, vhcr
, inbox
, outbox
,
1535 if (cmd
->out_is_imm
)
1536 vhcr_cmd
->out_param
= cpu_to_be64(vhcr
->out_param
);
1538 in_param
= cmd
->has_inbox
? (u64
) inbox
->dma
:
1540 out_param
= cmd
->has_outbox
? (u64
) outbox
->dma
:
1542 err
= __mlx4_cmd(dev
, in_param
, &out_param
,
1543 cmd
->out_is_imm
, vhcr
->in_modifier
,
1544 vhcr
->op_modifier
, vhcr
->op
,
1545 MLX4_CMD_TIME_CLASS_A
,
1548 if (cmd
->out_is_imm
) {
1549 vhcr
->out_param
= out_param
;
1550 vhcr_cmd
->out_param
= cpu_to_be64(vhcr
->out_param
);
1555 mlx4_warn(dev
, "vhcr command:0x%x slave:%d failed with error:%d, status %d\n",
1556 vhcr
->op
, slave
, vhcr
->errno
, err
);
1557 vhcr_cmd
->status
= mlx4_errno_to_status(err
);
1562 /* Write outbox if command completed successfully */
1563 if (cmd
->has_outbox
&& !vhcr_cmd
->status
) {
1564 ret
= mlx4_ACCESS_MEM(dev
, outbox
->dma
, slave
,
1566 MLX4_MAILBOX_SIZE
, MLX4_CMD_WRAPPED
);
1568 /* If we failed to write back the outbox after the
1569 *command was successfully executed, we must fail this
1570 * slave, as it is now in undefined state */
1571 mlx4_err(dev
, "%s:Failed writing outbox\n", __func__
);
1577 /* DMA back vhcr result */
1579 ret
= mlx4_ACCESS_MEM(dev
, priv
->mfunc
.vhcr_dma
, slave
,
1580 priv
->mfunc
.master
.slave_state
[slave
].vhcr_dma
,
1581 ALIGN(sizeof(struct mlx4_vhcr
),
1582 MLX4_ACCESS_MEM_ALIGN
),
1585 mlx4_err(dev
, "%s:Failed writing vhcr result\n",
1587 else if (vhcr
->e_bit
&&
1588 mlx4_GEN_EQE(dev
, slave
, &priv
->mfunc
.master
.cmd_eqe
))
1589 mlx4_warn(dev
, "Failed to generate command completion eqe for slave %d\n",
1595 mlx4_free_cmd_mailbox(dev
, inbox
);
1596 mlx4_free_cmd_mailbox(dev
, outbox
);
1600 static int mlx4_master_immediate_activate_vlan_qos(struct mlx4_priv
*priv
,
1601 int slave
, int port
)
1603 struct mlx4_vport_oper_state
*vp_oper
;
1604 struct mlx4_vport_state
*vp_admin
;
1605 struct mlx4_vf_immed_vlan_work
*work
;
1606 struct mlx4_dev
*dev
= &(priv
->dev
);
1608 int admin_vlan_ix
= NO_INDX
;
1610 vp_oper
= &priv
->mfunc
.master
.vf_oper
[slave
].vport
[port
];
1611 vp_admin
= &priv
->mfunc
.master
.vf_admin
[slave
].vport
[port
];
1613 if (vp_oper
->state
.default_vlan
== vp_admin
->default_vlan
&&
1614 vp_oper
->state
.default_qos
== vp_admin
->default_qos
&&
1615 vp_oper
->state
.link_state
== vp_admin
->link_state
)
1618 if (!(priv
->mfunc
.master
.slave_state
[slave
].active
&&
1619 dev
->caps
.flags2
& MLX4_DEV_CAP_FLAG2_UPDATE_QP
)) {
1620 /* even if the UPDATE_QP command isn't supported, we still want
1621 * to set this VF link according to the admin directive
1623 vp_oper
->state
.link_state
= vp_admin
->link_state
;
1627 mlx4_dbg(dev
, "updating immediately admin params slave %d port %d\n",
1629 mlx4_dbg(dev
, "vlan %d QoS %d link down %d\n",
1630 vp_admin
->default_vlan
, vp_admin
->default_qos
,
1631 vp_admin
->link_state
);
1633 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
1637 if (vp_oper
->state
.default_vlan
!= vp_admin
->default_vlan
) {
1638 if (MLX4_VGT
!= vp_admin
->default_vlan
) {
1639 err
= __mlx4_register_vlan(&priv
->dev
, port
,
1640 vp_admin
->default_vlan
,
1644 mlx4_warn(&priv
->dev
,
1645 "No vlan resources slave %d, port %d\n",
1650 admin_vlan_ix
= NO_INDX
;
1652 work
->flags
|= MLX4_VF_IMMED_VLAN_FLAG_VLAN
;
1653 mlx4_dbg(&priv
->dev
,
1654 "alloc vlan %d idx %d slave %d port %d\n",
1655 (int)(vp_admin
->default_vlan
),
1656 admin_vlan_ix
, slave
, port
);
1659 /* save original vlan ix and vlan id */
1660 work
->orig_vlan_id
= vp_oper
->state
.default_vlan
;
1661 work
->orig_vlan_ix
= vp_oper
->vlan_idx
;
1663 /* handle new qos */
1664 if (vp_oper
->state
.default_qos
!= vp_admin
->default_qos
)
1665 work
->flags
|= MLX4_VF_IMMED_VLAN_FLAG_QOS
;
1667 if (work
->flags
& MLX4_VF_IMMED_VLAN_FLAG_VLAN
)
1668 vp_oper
->vlan_idx
= admin_vlan_ix
;
1670 vp_oper
->state
.default_vlan
= vp_admin
->default_vlan
;
1671 vp_oper
->state
.default_qos
= vp_admin
->default_qos
;
1672 vp_oper
->state
.link_state
= vp_admin
->link_state
;
1674 if (vp_admin
->link_state
== IFLA_VF_LINK_STATE_DISABLE
)
1675 work
->flags
|= MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE
;
1677 /* iterate over QPs owned by this slave, using UPDATE_QP */
1679 work
->slave
= slave
;
1680 work
->qos
= vp_oper
->state
.default_qos
;
1681 work
->vlan_id
= vp_oper
->state
.default_vlan
;
1682 work
->vlan_ix
= vp_oper
->vlan_idx
;
1684 INIT_WORK(&work
->work
, mlx4_vf_immed_vlan_work_handler
);
1685 queue_work(priv
->mfunc
.master
.comm_wq
, &work
->work
);
1691 static int mlx4_master_activate_admin_state(struct mlx4_priv
*priv
, int slave
)
1694 struct mlx4_vport_state
*vp_admin
;
1695 struct mlx4_vport_oper_state
*vp_oper
;
1696 struct mlx4_active_ports actv_ports
= mlx4_get_active_ports(
1698 int min_port
= find_first_bit(actv_ports
.ports
,
1699 priv
->dev
.caps
.num_ports
) + 1;
1700 int max_port
= min_port
- 1 +
1701 bitmap_weight(actv_ports
.ports
, priv
->dev
.caps
.num_ports
);
1703 for (port
= min_port
; port
<= max_port
; port
++) {
1704 if (!test_bit(port
- 1, actv_ports
.ports
))
1706 priv
->mfunc
.master
.vf_oper
[slave
].smi_enabled
[port
] =
1707 priv
->mfunc
.master
.vf_admin
[slave
].enable_smi
[port
];
1708 vp_oper
= &priv
->mfunc
.master
.vf_oper
[slave
].vport
[port
];
1709 vp_admin
= &priv
->mfunc
.master
.vf_admin
[slave
].vport
[port
];
1710 vp_oper
->state
= *vp_admin
;
1711 if (MLX4_VGT
!= vp_admin
->default_vlan
) {
1712 err
= __mlx4_register_vlan(&priv
->dev
, port
,
1713 vp_admin
->default_vlan
, &(vp_oper
->vlan_idx
));
1715 vp_oper
->vlan_idx
= NO_INDX
;
1716 mlx4_warn(&priv
->dev
,
1717 "No vlan resources slave %d, port %d\n",
1721 mlx4_dbg(&priv
->dev
, "alloc vlan %d idx %d slave %d port %d\n",
1722 (int)(vp_oper
->state
.default_vlan
),
1723 vp_oper
->vlan_idx
, slave
, port
);
1725 if (vp_admin
->spoofchk
) {
1726 vp_oper
->mac_idx
= __mlx4_register_mac(&priv
->dev
,
1729 if (0 > vp_oper
->mac_idx
) {
1730 err
= vp_oper
->mac_idx
;
1731 vp_oper
->mac_idx
= NO_INDX
;
1732 mlx4_warn(&priv
->dev
,
1733 "No mac resources slave %d, port %d\n",
1737 mlx4_dbg(&priv
->dev
, "alloc mac %llx idx %d slave %d port %d\n",
1738 vp_oper
->state
.mac
, vp_oper
->mac_idx
, slave
, port
);
1744 static void mlx4_master_deactivate_admin_state(struct mlx4_priv
*priv
, int slave
)
1747 struct mlx4_vport_oper_state
*vp_oper
;
1748 struct mlx4_active_ports actv_ports
= mlx4_get_active_ports(
1750 int min_port
= find_first_bit(actv_ports
.ports
,
1751 priv
->dev
.caps
.num_ports
) + 1;
1752 int max_port
= min_port
- 1 +
1753 bitmap_weight(actv_ports
.ports
, priv
->dev
.caps
.num_ports
);
1756 for (port
= min_port
; port
<= max_port
; port
++) {
1757 if (!test_bit(port
- 1, actv_ports
.ports
))
1759 priv
->mfunc
.master
.vf_oper
[slave
].smi_enabled
[port
] =
1760 MLX4_VF_SMI_DISABLED
;
1761 vp_oper
= &priv
->mfunc
.master
.vf_oper
[slave
].vport
[port
];
1762 if (NO_INDX
!= vp_oper
->vlan_idx
) {
1763 __mlx4_unregister_vlan(&priv
->dev
,
1764 port
, vp_oper
->state
.default_vlan
);
1765 vp_oper
->vlan_idx
= NO_INDX
;
1767 if (NO_INDX
!= vp_oper
->mac_idx
) {
1768 __mlx4_unregister_mac(&priv
->dev
, port
, vp_oper
->state
.mac
);
1769 vp_oper
->mac_idx
= NO_INDX
;
1775 static void mlx4_master_do_cmd(struct mlx4_dev
*dev
, int slave
, u8 cmd
,
1776 u16 param
, u8 toggle
)
1778 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1779 struct mlx4_slave_state
*slave_state
= priv
->mfunc
.master
.slave_state
;
1781 u8 is_going_down
= 0;
1783 unsigned long flags
;
1785 slave_state
[slave
].comm_toggle
^= 1;
1786 reply
= (u32
) slave_state
[slave
].comm_toggle
<< 31;
1787 if (toggle
!= slave_state
[slave
].comm_toggle
) {
1788 mlx4_warn(dev
, "Incorrect toggle %d from slave %d. *** MASTER STATE COMPROMISED ***\n",
1792 if (cmd
== MLX4_COMM_CMD_RESET
) {
1793 mlx4_warn(dev
, "Received reset from slave:%d\n", slave
);
1794 slave_state
[slave
].active
= false;
1795 slave_state
[slave
].old_vlan_api
= false;
1796 mlx4_master_deactivate_admin_state(priv
, slave
);
1797 for (i
= 0; i
< MLX4_EVENT_TYPES_NUM
; ++i
) {
1798 slave_state
[slave
].event_eq
[i
].eqn
= -1;
1799 slave_state
[slave
].event_eq
[i
].token
= 0;
1801 /*check if we are in the middle of FLR process,
1802 if so return "retry" status to the slave*/
1803 if (MLX4_COMM_CMD_FLR
== slave_state
[slave
].last_cmd
)
1804 goto inform_slave_state
;
1806 mlx4_dispatch_event(dev
, MLX4_DEV_EVENT_SLAVE_SHUTDOWN
, slave
);
1808 /* write the version in the event field */
1809 reply
|= mlx4_comm_get_version();
1813 /*command from slave in the middle of FLR*/
1814 if (cmd
!= MLX4_COMM_CMD_RESET
&&
1815 MLX4_COMM_CMD_FLR
== slave_state
[slave
].last_cmd
) {
1816 mlx4_warn(dev
, "slave:%d is Trying to run cmd(0x%x) in the middle of FLR\n",
1822 case MLX4_COMM_CMD_VHCR0
:
1823 if (slave_state
[slave
].last_cmd
!= MLX4_COMM_CMD_RESET
)
1825 slave_state
[slave
].vhcr_dma
= ((u64
) param
) << 48;
1826 priv
->mfunc
.master
.slave_state
[slave
].cookie
= 0;
1827 mutex_init(&priv
->mfunc
.master
.gen_eqe_mutex
[slave
]);
1829 case MLX4_COMM_CMD_VHCR1
:
1830 if (slave_state
[slave
].last_cmd
!= MLX4_COMM_CMD_VHCR0
)
1832 slave_state
[slave
].vhcr_dma
|= ((u64
) param
) << 32;
1834 case MLX4_COMM_CMD_VHCR2
:
1835 if (slave_state
[slave
].last_cmd
!= MLX4_COMM_CMD_VHCR1
)
1837 slave_state
[slave
].vhcr_dma
|= ((u64
) param
) << 16;
1839 case MLX4_COMM_CMD_VHCR_EN
:
1840 if (slave_state
[slave
].last_cmd
!= MLX4_COMM_CMD_VHCR2
)
1842 slave_state
[slave
].vhcr_dma
|= param
;
1843 if (mlx4_master_activate_admin_state(priv
, slave
))
1845 slave_state
[slave
].active
= true;
1846 mlx4_dispatch_event(dev
, MLX4_DEV_EVENT_SLAVE_INIT
, slave
);
1848 case MLX4_COMM_CMD_VHCR_POST
:
1849 if ((slave_state
[slave
].last_cmd
!= MLX4_COMM_CMD_VHCR_EN
) &&
1850 (slave_state
[slave
].last_cmd
!= MLX4_COMM_CMD_VHCR_POST
))
1853 mutex_lock(&priv
->cmd
.slave_cmd_mutex
);
1854 if (mlx4_master_process_vhcr(dev
, slave
, NULL
)) {
1855 mlx4_err(dev
, "Failed processing vhcr for slave:%d, resetting slave\n",
1857 mutex_unlock(&priv
->cmd
.slave_cmd_mutex
);
1860 mutex_unlock(&priv
->cmd
.slave_cmd_mutex
);
1863 mlx4_warn(dev
, "Bad comm cmd:%d from slave:%d\n", cmd
, slave
);
1866 spin_lock_irqsave(&priv
->mfunc
.master
.slave_state_lock
, flags
);
1867 if (!slave_state
[slave
].is_slave_going_down
)
1868 slave_state
[slave
].last_cmd
= cmd
;
1871 spin_unlock_irqrestore(&priv
->mfunc
.master
.slave_state_lock
, flags
);
1872 if (is_going_down
) {
1873 mlx4_warn(dev
, "Slave is going down aborting command(%d) executing from slave:%d\n",
1877 __raw_writel((__force u32
) cpu_to_be32(reply
),
1878 &priv
->mfunc
.comm
[slave
].slave_read
);
1884 /* cleanup any slave resources */
1885 mlx4_delete_all_resources_for_slave(dev
, slave
);
1886 spin_lock_irqsave(&priv
->mfunc
.master
.slave_state_lock
, flags
);
1887 if (!slave_state
[slave
].is_slave_going_down
)
1888 slave_state
[slave
].last_cmd
= MLX4_COMM_CMD_RESET
;
1889 spin_unlock_irqrestore(&priv
->mfunc
.master
.slave_state_lock
, flags
);
1890 /*with slave in the middle of flr, no need to clean resources again.*/
1892 memset(&slave_state
[slave
].event_eq
, 0,
1893 sizeof(struct mlx4_slave_event_eq_info
));
1894 __raw_writel((__force u32
) cpu_to_be32(reply
),
1895 &priv
->mfunc
.comm
[slave
].slave_read
);
1899 /* master command processing */
1900 void mlx4_master_comm_channel(struct work_struct
*work
)
1902 struct mlx4_mfunc_master_ctx
*master
=
1904 struct mlx4_mfunc_master_ctx
,
1906 struct mlx4_mfunc
*mfunc
=
1907 container_of(master
, struct mlx4_mfunc
, master
);
1908 struct mlx4_priv
*priv
=
1909 container_of(mfunc
, struct mlx4_priv
, mfunc
);
1910 struct mlx4_dev
*dev
= &priv
->dev
;
1920 bit_vec
= master
->comm_arm_bit_vector
;
1921 for (i
= 0; i
< COMM_CHANNEL_BIT_ARRAY_SIZE
; i
++) {
1922 vec
= be32_to_cpu(bit_vec
[i
]);
1923 for (j
= 0; j
< 32; j
++) {
1924 if (!(vec
& (1 << j
)))
1927 slave
= (i
* 32) + j
;
1928 comm_cmd
= swab32(readl(
1929 &mfunc
->comm
[slave
].slave_write
));
1930 slt
= swab32(readl(&mfunc
->comm
[slave
].slave_read
))
1932 toggle
= comm_cmd
>> 31;
1933 if (toggle
!= slt
) {
1934 if (master
->slave_state
[slave
].comm_toggle
1936 pr_info("slave %d out of sync. read toggle %d, state toggle %d. Resynching.\n",
1938 master
->slave_state
[slave
].comm_toggle
);
1939 master
->slave_state
[slave
].comm_toggle
=
1942 mlx4_master_do_cmd(dev
, slave
,
1943 comm_cmd
>> 16 & 0xff,
1944 comm_cmd
& 0xffff, toggle
);
1950 if (reported
&& reported
!= served
)
1951 mlx4_warn(dev
, "Got command event with bitmask from %d slaves but %d were served\n",
1954 if (mlx4_ARM_COMM_CHANNEL(dev
))
1955 mlx4_warn(dev
, "Failed to arm comm channel events\n");
1958 static int sync_toggles(struct mlx4_dev
*dev
)
1960 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1965 wr_toggle
= swab32(readl(&priv
->mfunc
.comm
->slave_write
)) >> 31;
1966 end
= jiffies
+ msecs_to_jiffies(5000);
1968 while (time_before(jiffies
, end
)) {
1969 rd_toggle
= swab32(readl(&priv
->mfunc
.comm
->slave_read
)) >> 31;
1970 if (rd_toggle
== wr_toggle
) {
1971 priv
->cmd
.comm_toggle
= rd_toggle
;
1979 * we could reach here if for example the previous VM using this
1980 * function misbehaved and left the channel with unsynced state. We
1981 * should fix this here and give this VM a chance to use a properly
1984 mlx4_warn(dev
, "recovering from previously mis-behaved VM\n");
1985 __raw_writel((__force u32
) 0, &priv
->mfunc
.comm
->slave_read
);
1986 __raw_writel((__force u32
) 0, &priv
->mfunc
.comm
->slave_write
);
1987 priv
->cmd
.comm_toggle
= 0;
1992 int mlx4_multi_func_init(struct mlx4_dev
*dev
)
1994 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1995 struct mlx4_slave_state
*s_state
;
1996 int i
, j
, err
, port
;
1998 if (mlx4_is_master(dev
))
2000 ioremap(pci_resource_start(dev
->pdev
, priv
->fw
.comm_bar
) +
2001 priv
->fw
.comm_base
, MLX4_COMM_PAGESIZE
);
2004 ioremap(pci_resource_start(dev
->pdev
, 2) +
2005 MLX4_SLAVE_COMM_BASE
, MLX4_COMM_PAGESIZE
);
2006 if (!priv
->mfunc
.comm
) {
2007 mlx4_err(dev
, "Couldn't map communication vector\n");
2011 if (mlx4_is_master(dev
)) {
2012 priv
->mfunc
.master
.slave_state
=
2013 kzalloc(dev
->num_slaves
*
2014 sizeof(struct mlx4_slave_state
), GFP_KERNEL
);
2015 if (!priv
->mfunc
.master
.slave_state
)
2018 priv
->mfunc
.master
.vf_admin
=
2019 kzalloc(dev
->num_slaves
*
2020 sizeof(struct mlx4_vf_admin_state
), GFP_KERNEL
);
2021 if (!priv
->mfunc
.master
.vf_admin
)
2022 goto err_comm_admin
;
2024 priv
->mfunc
.master
.vf_oper
=
2025 kzalloc(dev
->num_slaves
*
2026 sizeof(struct mlx4_vf_oper_state
), GFP_KERNEL
);
2027 if (!priv
->mfunc
.master
.vf_oper
)
2030 for (i
= 0; i
< dev
->num_slaves
; ++i
) {
2031 s_state
= &priv
->mfunc
.master
.slave_state
[i
];
2032 s_state
->last_cmd
= MLX4_COMM_CMD_RESET
;
2033 for (j
= 0; j
< MLX4_EVENT_TYPES_NUM
; ++j
)
2034 s_state
->event_eq
[j
].eqn
= -1;
2035 __raw_writel((__force u32
) 0,
2036 &priv
->mfunc
.comm
[i
].slave_write
);
2037 __raw_writel((__force u32
) 0,
2038 &priv
->mfunc
.comm
[i
].slave_read
);
2040 for (port
= 1; port
<= MLX4_MAX_PORTS
; port
++) {
2041 s_state
->vlan_filter
[port
] =
2042 kzalloc(sizeof(struct mlx4_vlan_fltr
),
2044 if (!s_state
->vlan_filter
[port
]) {
2046 kfree(s_state
->vlan_filter
[port
]);
2049 INIT_LIST_HEAD(&s_state
->mcast_filters
[port
]);
2050 priv
->mfunc
.master
.vf_admin
[i
].vport
[port
].default_vlan
= MLX4_VGT
;
2051 priv
->mfunc
.master
.vf_oper
[i
].vport
[port
].state
.default_vlan
= MLX4_VGT
;
2052 priv
->mfunc
.master
.vf_oper
[i
].vport
[port
].vlan_idx
= NO_INDX
;
2053 priv
->mfunc
.master
.vf_oper
[i
].vport
[port
].mac_idx
= NO_INDX
;
2055 spin_lock_init(&s_state
->lock
);
2058 memset(&priv
->mfunc
.master
.cmd_eqe
, 0, dev
->caps
.eqe_size
);
2059 priv
->mfunc
.master
.cmd_eqe
.type
= MLX4_EVENT_TYPE_CMD
;
2060 INIT_WORK(&priv
->mfunc
.master
.comm_work
,
2061 mlx4_master_comm_channel
);
2062 INIT_WORK(&priv
->mfunc
.master
.slave_event_work
,
2063 mlx4_gen_slave_eqe
);
2064 INIT_WORK(&priv
->mfunc
.master
.slave_flr_event_work
,
2065 mlx4_master_handle_slave_flr
);
2066 spin_lock_init(&priv
->mfunc
.master
.slave_state_lock
);
2067 spin_lock_init(&priv
->mfunc
.master
.slave_eq
.event_lock
);
2068 priv
->mfunc
.master
.comm_wq
=
2069 create_singlethread_workqueue("mlx4_comm");
2070 if (!priv
->mfunc
.master
.comm_wq
)
2073 if (mlx4_init_resource_tracker(dev
))
2076 err
= mlx4_ARM_COMM_CHANNEL(dev
);
2078 mlx4_err(dev
, " Failed to arm comm channel eq: %x\n",
2084 err
= sync_toggles(dev
);
2086 mlx4_err(dev
, "Couldn't sync toggles\n");
2093 mlx4_free_resource_tracker(dev
, RES_TR_FREE_ALL
);
2095 flush_workqueue(priv
->mfunc
.master
.comm_wq
);
2096 destroy_workqueue(priv
->mfunc
.master
.comm_wq
);
2099 for (port
= 1; port
<= MLX4_MAX_PORTS
; port
++)
2100 kfree(priv
->mfunc
.master
.slave_state
[i
].vlan_filter
[port
]);
2102 kfree(priv
->mfunc
.master
.vf_oper
);
2104 kfree(priv
->mfunc
.master
.vf_admin
);
2106 kfree(priv
->mfunc
.master
.slave_state
);
2108 iounmap(priv
->mfunc
.comm
);
2110 dma_free_coherent(&(dev
->pdev
->dev
), PAGE_SIZE
,
2112 priv
->mfunc
.vhcr_dma
);
2113 priv
->mfunc
.vhcr
= NULL
;
2117 int mlx4_cmd_init(struct mlx4_dev
*dev
)
2119 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2121 mutex_init(&priv
->cmd
.hcr_mutex
);
2122 mutex_init(&priv
->cmd
.slave_cmd_mutex
);
2123 sema_init(&priv
->cmd
.poll_sem
, 1);
2124 priv
->cmd
.use_events
= 0;
2125 priv
->cmd
.toggle
= 1;
2127 priv
->cmd
.hcr
= NULL
;
2128 priv
->mfunc
.vhcr
= NULL
;
2130 if (!mlx4_is_slave(dev
)) {
2131 priv
->cmd
.hcr
= ioremap(pci_resource_start(dev
->pdev
, 0) +
2132 MLX4_HCR_BASE
, MLX4_HCR_SIZE
);
2133 if (!priv
->cmd
.hcr
) {
2134 mlx4_err(dev
, "Couldn't map command register\n");
2139 if (mlx4_is_mfunc(dev
)) {
2140 priv
->mfunc
.vhcr
= dma_alloc_coherent(&(dev
->pdev
->dev
), PAGE_SIZE
,
2141 &priv
->mfunc
.vhcr_dma
,
2143 if (!priv
->mfunc
.vhcr
)
2147 priv
->cmd
.pool
= pci_pool_create("mlx4_cmd", dev
->pdev
,
2149 MLX4_MAILBOX_SIZE
, 0);
2150 if (!priv
->cmd
.pool
)
2156 if (mlx4_is_mfunc(dev
))
2157 dma_free_coherent(&(dev
->pdev
->dev
), PAGE_SIZE
,
2158 priv
->mfunc
.vhcr
, priv
->mfunc
.vhcr_dma
);
2159 priv
->mfunc
.vhcr
= NULL
;
2162 if (!mlx4_is_slave(dev
))
2163 iounmap(priv
->cmd
.hcr
);
2167 void mlx4_multi_func_cleanup(struct mlx4_dev
*dev
)
2169 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2172 if (mlx4_is_master(dev
)) {
2173 flush_workqueue(priv
->mfunc
.master
.comm_wq
);
2174 destroy_workqueue(priv
->mfunc
.master
.comm_wq
);
2175 for (i
= 0; i
< dev
->num_slaves
; i
++) {
2176 for (port
= 1; port
<= MLX4_MAX_PORTS
; port
++)
2177 kfree(priv
->mfunc
.master
.slave_state
[i
].vlan_filter
[port
]);
2179 kfree(priv
->mfunc
.master
.slave_state
);
2180 kfree(priv
->mfunc
.master
.vf_admin
);
2181 kfree(priv
->mfunc
.master
.vf_oper
);
2184 iounmap(priv
->mfunc
.comm
);
2187 void mlx4_cmd_cleanup(struct mlx4_dev
*dev
)
2189 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2191 pci_pool_destroy(priv
->cmd
.pool
);
2193 if (!mlx4_is_slave(dev
))
2194 iounmap(priv
->cmd
.hcr
);
2195 if (mlx4_is_mfunc(dev
))
2196 dma_free_coherent(&(dev
->pdev
->dev
), PAGE_SIZE
,
2197 priv
->mfunc
.vhcr
, priv
->mfunc
.vhcr_dma
);
2198 priv
->mfunc
.vhcr
= NULL
;
2202 * Switch to using events to issue FW commands (can only be called
2203 * after event queue for command events has been initialized).
2205 int mlx4_cmd_use_events(struct mlx4_dev
*dev
)
2207 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2211 priv
->cmd
.context
= kmalloc(priv
->cmd
.max_cmds
*
2212 sizeof (struct mlx4_cmd_context
),
2214 if (!priv
->cmd
.context
)
2217 for (i
= 0; i
< priv
->cmd
.max_cmds
; ++i
) {
2218 priv
->cmd
.context
[i
].token
= i
;
2219 priv
->cmd
.context
[i
].next
= i
+ 1;
2222 priv
->cmd
.context
[priv
->cmd
.max_cmds
- 1].next
= -1;
2223 priv
->cmd
.free_head
= 0;
2225 sema_init(&priv
->cmd
.event_sem
, priv
->cmd
.max_cmds
);
2226 spin_lock_init(&priv
->cmd
.context_lock
);
2228 for (priv
->cmd
.token_mask
= 1;
2229 priv
->cmd
.token_mask
< priv
->cmd
.max_cmds
;
2230 priv
->cmd
.token_mask
<<= 1)
2232 --priv
->cmd
.token_mask
;
2234 down(&priv
->cmd
.poll_sem
);
2235 priv
->cmd
.use_events
= 1;
2241 * Switch back to polling (used when shutting down the device)
2243 void mlx4_cmd_use_polling(struct mlx4_dev
*dev
)
2245 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2248 priv
->cmd
.use_events
= 0;
2250 for (i
= 0; i
< priv
->cmd
.max_cmds
; ++i
)
2251 down(&priv
->cmd
.event_sem
);
2253 kfree(priv
->cmd
.context
);
2255 up(&priv
->cmd
.poll_sem
);
2258 struct mlx4_cmd_mailbox
*mlx4_alloc_cmd_mailbox(struct mlx4_dev
*dev
)
2260 struct mlx4_cmd_mailbox
*mailbox
;
2262 mailbox
= kmalloc(sizeof *mailbox
, GFP_KERNEL
);
2264 return ERR_PTR(-ENOMEM
);
2266 mailbox
->buf
= pci_pool_alloc(mlx4_priv(dev
)->cmd
.pool
, GFP_KERNEL
,
2268 if (!mailbox
->buf
) {
2270 return ERR_PTR(-ENOMEM
);
2273 memset(mailbox
->buf
, 0, MLX4_MAILBOX_SIZE
);
2277 EXPORT_SYMBOL_GPL(mlx4_alloc_cmd_mailbox
);
2279 void mlx4_free_cmd_mailbox(struct mlx4_dev
*dev
,
2280 struct mlx4_cmd_mailbox
*mailbox
)
2285 pci_pool_free(mlx4_priv(dev
)->cmd
.pool
, mailbox
->buf
, mailbox
->dma
);
2288 EXPORT_SYMBOL_GPL(mlx4_free_cmd_mailbox
);
2290 u32
mlx4_comm_get_version(void)
2292 return ((u32
) CMD_CHAN_IF_REV
<< 8) | (u32
) CMD_CHAN_VER
;
2295 static int mlx4_get_slave_indx(struct mlx4_dev
*dev
, int vf
)
2297 if ((vf
< 0) || (vf
>= dev
->num_vfs
)) {
2298 mlx4_err(dev
, "Bad vf number:%d (number of activated vf: %d)\n", vf
, dev
->num_vfs
);
2305 int mlx4_get_vf_indx(struct mlx4_dev
*dev
, int slave
)
2307 if (slave
< 1 || slave
> dev
->num_vfs
) {
2309 "Bad slave number:%d (number of activated slaves: %lu)\n",
2310 slave
, dev
->num_slaves
);
2316 struct mlx4_active_ports
mlx4_get_active_ports(struct mlx4_dev
*dev
, int slave
)
2318 struct mlx4_active_ports actv_ports
;
2321 bitmap_zero(actv_ports
.ports
, MLX4_MAX_PORTS
);
2324 bitmap_fill(actv_ports
.ports
, dev
->caps
.num_ports
);
2328 vf
= mlx4_get_vf_indx(dev
, slave
);
2332 bitmap_set(actv_ports
.ports
, dev
->dev_vfs
[vf
].min_port
- 1,
2333 min((int)dev
->dev_vfs
[mlx4_get_vf_indx(dev
, slave
)].n_ports
,
2334 dev
->caps
.num_ports
));
2338 EXPORT_SYMBOL_GPL(mlx4_get_active_ports
);
2340 int mlx4_slave_convert_port(struct mlx4_dev
*dev
, int slave
, int port
)
2343 struct mlx4_active_ports actv_ports
= mlx4_get_active_ports(dev
, slave
);
2344 unsigned m
= bitmap_weight(actv_ports
.ports
, dev
->caps
.num_ports
);
2346 if (port
<= 0 || port
> m
)
2349 n
= find_first_bit(actv_ports
.ports
, dev
->caps
.num_ports
);
2355 EXPORT_SYMBOL_GPL(mlx4_slave_convert_port
);
2357 int mlx4_phys_to_slave_port(struct mlx4_dev
*dev
, int slave
, int port
)
2359 struct mlx4_active_ports actv_ports
= mlx4_get_active_ports(dev
, slave
);
2360 if (test_bit(port
- 1, actv_ports
.ports
))
2362 find_first_bit(actv_ports
.ports
, dev
->caps
.num_ports
);
2366 EXPORT_SYMBOL_GPL(mlx4_phys_to_slave_port
);
2368 struct mlx4_slaves_pport
mlx4_phys_to_slaves_pport(struct mlx4_dev
*dev
,
2372 struct mlx4_slaves_pport slaves_pport
;
2374 bitmap_zero(slaves_pport
.slaves
, MLX4_MFUNC_MAX
);
2376 if (port
<= 0 || port
> dev
->caps
.num_ports
)
2377 return slaves_pport
;
2379 for (i
= 0; i
< dev
->num_vfs
+ 1; i
++) {
2380 struct mlx4_active_ports actv_ports
=
2381 mlx4_get_active_ports(dev
, i
);
2382 if (test_bit(port
- 1, actv_ports
.ports
))
2383 set_bit(i
, slaves_pport
.slaves
);
2386 return slaves_pport
;
2388 EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport
);
2390 struct mlx4_slaves_pport
mlx4_phys_to_slaves_pport_actv(
2391 struct mlx4_dev
*dev
,
2392 const struct mlx4_active_ports
*crit_ports
)
2395 struct mlx4_slaves_pport slaves_pport
;
2397 bitmap_zero(slaves_pport
.slaves
, MLX4_MFUNC_MAX
);
2399 for (i
= 0; i
< dev
->num_vfs
+ 1; i
++) {
2400 struct mlx4_active_ports actv_ports
=
2401 mlx4_get_active_ports(dev
, i
);
2402 if (bitmap_equal(crit_ports
->ports
, actv_ports
.ports
,
2403 dev
->caps
.num_ports
))
2404 set_bit(i
, slaves_pport
.slaves
);
2407 return slaves_pport
;
2409 EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport_actv
);
2411 static int mlx4_slaves_closest_port(struct mlx4_dev
*dev
, int slave
, int port
)
2413 struct mlx4_active_ports actv_ports
= mlx4_get_active_ports(dev
, slave
);
2414 int min_port
= find_first_bit(actv_ports
.ports
, dev
->caps
.num_ports
)
2416 int max_port
= min_port
+
2417 bitmap_weight(actv_ports
.ports
, dev
->caps
.num_ports
);
2419 if (port
< min_port
)
2421 else if (port
>= max_port
)
2422 port
= max_port
- 1;
2427 int mlx4_set_vf_mac(struct mlx4_dev
*dev
, int port
, int vf
, u64 mac
)
2429 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2430 struct mlx4_vport_state
*s_info
;
2433 if (!mlx4_is_master(dev
))
2434 return -EPROTONOSUPPORT
;
2436 slave
= mlx4_get_slave_indx(dev
, vf
);
2440 port
= mlx4_slaves_closest_port(dev
, slave
, port
);
2441 s_info
= &priv
->mfunc
.master
.vf_admin
[slave
].vport
[port
];
2443 mlx4_info(dev
, "default mac on vf %d port %d to %llX will take afect only after vf restart\n",
2444 vf
, port
, s_info
->mac
);
2447 EXPORT_SYMBOL_GPL(mlx4_set_vf_mac
);
2450 int mlx4_set_vf_vlan(struct mlx4_dev
*dev
, int port
, int vf
, u16 vlan
, u8 qos
)
2452 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2453 struct mlx4_vport_state
*vf_admin
;
2456 if ((!mlx4_is_master(dev
)) ||
2457 !(dev
->caps
.flags2
& MLX4_DEV_CAP_FLAG2_VLAN_CONTROL
))
2458 return -EPROTONOSUPPORT
;
2460 if ((vlan
> 4095) || (qos
> 7))
2463 slave
= mlx4_get_slave_indx(dev
, vf
);
2467 port
= mlx4_slaves_closest_port(dev
, slave
, port
);
2468 vf_admin
= &priv
->mfunc
.master
.vf_admin
[slave
].vport
[port
];
2470 if ((0 == vlan
) && (0 == qos
))
2471 vf_admin
->default_vlan
= MLX4_VGT
;
2473 vf_admin
->default_vlan
= vlan
;
2474 vf_admin
->default_qos
= qos
;
2476 if (mlx4_master_immediate_activate_vlan_qos(priv
, slave
, port
))
2478 "updating vf %d port %d config will take effect on next VF restart\n",
2482 EXPORT_SYMBOL_GPL(mlx4_set_vf_vlan
);
2484 /* mlx4_get_slave_default_vlan -
2485 * return true if VST ( default vlan)
2486 * if VST, will return vlan & qos (if not NULL)
2488 bool mlx4_get_slave_default_vlan(struct mlx4_dev
*dev
, int port
, int slave
,
2491 struct mlx4_vport_oper_state
*vp_oper
;
2492 struct mlx4_priv
*priv
;
2494 priv
= mlx4_priv(dev
);
2495 port
= mlx4_slaves_closest_port(dev
, slave
, port
);
2496 vp_oper
= &priv
->mfunc
.master
.vf_oper
[slave
].vport
[port
];
2498 if (MLX4_VGT
!= vp_oper
->state
.default_vlan
) {
2500 *vlan
= vp_oper
->state
.default_vlan
;
2502 *qos
= vp_oper
->state
.default_qos
;
2507 EXPORT_SYMBOL_GPL(mlx4_get_slave_default_vlan
);
2509 int mlx4_set_vf_spoofchk(struct mlx4_dev
*dev
, int port
, int vf
, bool setting
)
2511 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2512 struct mlx4_vport_state
*s_info
;
2515 if ((!mlx4_is_master(dev
)) ||
2516 !(dev
->caps
.flags2
& MLX4_DEV_CAP_FLAG2_FSM
))
2517 return -EPROTONOSUPPORT
;
2519 slave
= mlx4_get_slave_indx(dev
, vf
);
2523 port
= mlx4_slaves_closest_port(dev
, slave
, port
);
2524 s_info
= &priv
->mfunc
.master
.vf_admin
[slave
].vport
[port
];
2525 s_info
->spoofchk
= setting
;
2529 EXPORT_SYMBOL_GPL(mlx4_set_vf_spoofchk
);
2531 int mlx4_get_vf_config(struct mlx4_dev
*dev
, int port
, int vf
, struct ifla_vf_info
*ivf
)
2533 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2534 struct mlx4_vport_state
*s_info
;
2537 if (!mlx4_is_master(dev
))
2538 return -EPROTONOSUPPORT
;
2540 slave
= mlx4_get_slave_indx(dev
, vf
);
2544 s_info
= &priv
->mfunc
.master
.vf_admin
[slave
].vport
[port
];
2547 /* need to convert it to a func */
2548 ivf
->mac
[0] = ((s_info
->mac
>> (5*8)) & 0xff);
2549 ivf
->mac
[1] = ((s_info
->mac
>> (4*8)) & 0xff);
2550 ivf
->mac
[2] = ((s_info
->mac
>> (3*8)) & 0xff);
2551 ivf
->mac
[3] = ((s_info
->mac
>> (2*8)) & 0xff);
2552 ivf
->mac
[4] = ((s_info
->mac
>> (1*8)) & 0xff);
2553 ivf
->mac
[5] = ((s_info
->mac
) & 0xff);
2555 ivf
->vlan
= s_info
->default_vlan
;
2556 ivf
->qos
= s_info
->default_qos
;
2557 ivf
->max_tx_rate
= s_info
->tx_rate
;
2558 ivf
->min_tx_rate
= 0;
2559 ivf
->spoofchk
= s_info
->spoofchk
;
2560 ivf
->linkstate
= s_info
->link_state
;
2564 EXPORT_SYMBOL_GPL(mlx4_get_vf_config
);
2566 int mlx4_set_vf_link_state(struct mlx4_dev
*dev
, int port
, int vf
, int link_state
)
2568 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2569 struct mlx4_vport_state
*s_info
;
2573 slave
= mlx4_get_slave_indx(dev
, vf
);
2577 port
= mlx4_slaves_closest_port(dev
, slave
, port
);
2578 switch (link_state
) {
2579 case IFLA_VF_LINK_STATE_AUTO
:
2580 /* get current link state */
2581 if (!priv
->sense
.do_sense_port
[port
])
2582 link_stat_event
= MLX4_PORT_CHANGE_SUBTYPE_ACTIVE
;
2584 link_stat_event
= MLX4_PORT_CHANGE_SUBTYPE_DOWN
;
2587 case IFLA_VF_LINK_STATE_ENABLE
:
2588 link_stat_event
= MLX4_PORT_CHANGE_SUBTYPE_ACTIVE
;
2591 case IFLA_VF_LINK_STATE_DISABLE
:
2592 link_stat_event
= MLX4_PORT_CHANGE_SUBTYPE_DOWN
;
2596 mlx4_warn(dev
, "unknown value for link_state %02x on slave %d port %d\n",
2597 link_state
, slave
, port
);
2600 s_info
= &priv
->mfunc
.master
.vf_admin
[slave
].vport
[port
];
2601 s_info
->link_state
= link_state
;
2604 mlx4_gen_port_state_change_eqe(dev
, slave
, port
, link_stat_event
);
2606 if (mlx4_master_immediate_activate_vlan_qos(priv
, slave
, port
))
2608 "updating vf %d port %d no link state HW enforcment\n",
2612 EXPORT_SYMBOL_GPL(mlx4_set_vf_link_state
);
2614 int mlx4_vf_smi_enabled(struct mlx4_dev
*dev
, int slave
, int port
)
2616 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2618 if (slave
< 1 || slave
>= dev
->num_slaves
||
2619 port
< 1 || port
> MLX4_MAX_PORTS
)
2622 return priv
->mfunc
.master
.vf_oper
[slave
].smi_enabled
[port
] ==
2623 MLX4_VF_SMI_ENABLED
;
2625 EXPORT_SYMBOL_GPL(mlx4_vf_smi_enabled
);
2627 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev
*dev
, int slave
, int port
)
2629 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2631 if (slave
== mlx4_master_func_num(dev
))
2634 if (slave
< 1 || slave
>= dev
->num_slaves
||
2635 port
< 1 || port
> MLX4_MAX_PORTS
)
2638 return priv
->mfunc
.master
.vf_admin
[slave
].enable_smi
[port
] ==
2639 MLX4_VF_SMI_ENABLED
;
2641 EXPORT_SYMBOL_GPL(mlx4_vf_get_enable_smi_admin
);
2643 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev
*dev
, int slave
, int port
,
2646 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2648 if (slave
== mlx4_master_func_num(dev
))
2651 if (slave
< 1 || slave
>= dev
->num_slaves
||
2652 port
< 1 || port
> MLX4_MAX_PORTS
||
2653 enabled
< 0 || enabled
> 1)
2656 priv
->mfunc
.master
.vf_admin
[slave
].enable_smi
[port
] = enabled
;
2659 EXPORT_SYMBOL_GPL(mlx4_vf_set_enable_smi_admin
);