2 * Support functions for OMAP GPIO
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
22 #include <linux/device.h>
23 #include <linux/pm_runtime.h>
26 #include <linux/of_device.h>
27 #include <linux/gpio.h>
28 #include <linux/bitops.h>
29 #include <linux/platform_data/gpio-omap.h>
33 static LIST_HEAD(omap_gpio_list
);
51 struct list_head node
;
55 u32 enabled_non_wakeup_gpios
;
56 struct gpio_regs context
;
61 struct gpio_chip chip
;
74 int context_loss_count
;
76 bool workaround_enabled
;
78 void (*set_dataout
)(struct gpio_bank
*bank
, unsigned gpio
, int enable
);
79 int (*get_context_loss_count
)(struct device
*dev
);
81 struct omap_gpio_reg_offs
*regs
;
84 #define GPIO_MOD_CTRL_BIT BIT(0)
86 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
87 #define LINE_USED(line, offset) (line & (BIT(offset)))
89 static void omap_gpio_unmask_irq(struct irq_data
*d
);
91 static inline struct gpio_bank
*omap_irq_data_get_bank(struct irq_data
*d
)
93 struct gpio_chip
*chip
= irq_data_get_irq_chip_data(d
);
94 return container_of(chip
, struct gpio_bank
, chip
);
97 static void omap_set_gpio_direction(struct gpio_bank
*bank
, int gpio
,
100 void __iomem
*reg
= bank
->base
;
103 reg
+= bank
->regs
->direction
;
104 l
= readl_relaxed(reg
);
109 writel_relaxed(l
, reg
);
110 bank
->context
.oe
= l
;
114 /* set data out value using dedicate set/clear register */
115 static void omap_set_gpio_dataout_reg(struct gpio_bank
*bank
, unsigned offset
,
118 void __iomem
*reg
= bank
->base
;
122 reg
+= bank
->regs
->set_dataout
;
123 bank
->context
.dataout
|= l
;
125 reg
+= bank
->regs
->clr_dataout
;
126 bank
->context
.dataout
&= ~l
;
129 writel_relaxed(l
, reg
);
132 /* set data out value using mask register */
133 static void omap_set_gpio_dataout_mask(struct gpio_bank
*bank
, unsigned offset
,
136 void __iomem
*reg
= bank
->base
+ bank
->regs
->dataout
;
137 u32 gpio_bit
= BIT(offset
);
140 l
= readl_relaxed(reg
);
145 writel_relaxed(l
, reg
);
146 bank
->context
.dataout
= l
;
149 static int omap_get_gpio_datain(struct gpio_bank
*bank
, int offset
)
151 void __iomem
*reg
= bank
->base
+ bank
->regs
->datain
;
153 return (readl_relaxed(reg
) & (BIT(offset
))) != 0;
156 static int omap_get_gpio_dataout(struct gpio_bank
*bank
, int offset
)
158 void __iomem
*reg
= bank
->base
+ bank
->regs
->dataout
;
160 return (readl_relaxed(reg
) & (BIT(offset
))) != 0;
163 static inline void omap_gpio_rmw(void __iomem
*base
, u32 reg
, u32 mask
, bool set
)
165 int l
= readl_relaxed(base
+ reg
);
172 writel_relaxed(l
, base
+ reg
);
175 static inline void omap_gpio_dbck_enable(struct gpio_bank
*bank
)
177 if (bank
->dbck_enable_mask
&& !bank
->dbck_enabled
) {
178 clk_prepare_enable(bank
->dbck
);
179 bank
->dbck_enabled
= true;
181 writel_relaxed(bank
->dbck_enable_mask
,
182 bank
->base
+ bank
->regs
->debounce_en
);
186 static inline void omap_gpio_dbck_disable(struct gpio_bank
*bank
)
188 if (bank
->dbck_enable_mask
&& bank
->dbck_enabled
) {
190 * Disable debounce before cutting it's clock. If debounce is
191 * enabled but the clock is not, GPIO module seems to be unable
192 * to detect events and generate interrupts at least on OMAP3.
194 writel_relaxed(0, bank
->base
+ bank
->regs
->debounce_en
);
196 clk_disable_unprepare(bank
->dbck
);
197 bank
->dbck_enabled
= false;
202 * omap2_set_gpio_debounce - low level gpio debounce time
203 * @bank: the gpio bank we're acting upon
204 * @offset: the gpio number on this @bank
205 * @debounce: debounce time to use
207 * OMAP's debounce time is in 31us steps so we need
208 * to convert and round up to the closest unit.
210 static void omap2_set_gpio_debounce(struct gpio_bank
*bank
, unsigned offset
,
217 if (!bank
->dbck_flag
)
222 else if (debounce
> 7936)
225 debounce
= (debounce
/ 0x1f) - 1;
229 clk_prepare_enable(bank
->dbck
);
230 reg
= bank
->base
+ bank
->regs
->debounce
;
231 writel_relaxed(debounce
, reg
);
233 reg
= bank
->base
+ bank
->regs
->debounce_en
;
234 val
= readl_relaxed(reg
);
240 bank
->dbck_enable_mask
= val
;
242 writel_relaxed(val
, reg
);
243 clk_disable_unprepare(bank
->dbck
);
245 * Enable debounce clock per module.
246 * This call is mandatory because in omap_gpio_request() when
247 * *_runtime_get_sync() is called, _gpio_dbck_enable() within
248 * runtime callbck fails to turn on dbck because dbck_enable_mask
249 * used within _gpio_dbck_enable() is still not initialized at
250 * that point. Therefore we have to enable dbck here.
252 omap_gpio_dbck_enable(bank
);
253 if (bank
->dbck_enable_mask
) {
254 bank
->context
.debounce
= debounce
;
255 bank
->context
.debounce_en
= val
;
260 * omap_clear_gpio_debounce - clear debounce settings for a gpio
261 * @bank: the gpio bank we're acting upon
262 * @offset: the gpio number on this @bank
264 * If a gpio is using debounce, then clear the debounce enable bit and if
265 * this is the only gpio in this bank using debounce, then clear the debounce
266 * time too. The debounce clock will also be disabled when calling this function
267 * if this is the only gpio in the bank using debounce.
269 static void omap_clear_gpio_debounce(struct gpio_bank
*bank
, unsigned offset
)
271 u32 gpio_bit
= BIT(offset
);
273 if (!bank
->dbck_flag
)
276 if (!(bank
->dbck_enable_mask
& gpio_bit
))
279 bank
->dbck_enable_mask
&= ~gpio_bit
;
280 bank
->context
.debounce_en
&= ~gpio_bit
;
281 writel_relaxed(bank
->context
.debounce_en
,
282 bank
->base
+ bank
->regs
->debounce_en
);
284 if (!bank
->dbck_enable_mask
) {
285 bank
->context
.debounce
= 0;
286 writel_relaxed(bank
->context
.debounce
, bank
->base
+
287 bank
->regs
->debounce
);
288 clk_disable_unprepare(bank
->dbck
);
289 bank
->dbck_enabled
= false;
293 static inline void omap_set_gpio_trigger(struct gpio_bank
*bank
, int gpio
,
296 void __iomem
*base
= bank
->base
;
297 u32 gpio_bit
= BIT(gpio
);
299 omap_gpio_rmw(base
, bank
->regs
->leveldetect0
, gpio_bit
,
300 trigger
& IRQ_TYPE_LEVEL_LOW
);
301 omap_gpio_rmw(base
, bank
->regs
->leveldetect1
, gpio_bit
,
302 trigger
& IRQ_TYPE_LEVEL_HIGH
);
303 omap_gpio_rmw(base
, bank
->regs
->risingdetect
, gpio_bit
,
304 trigger
& IRQ_TYPE_EDGE_RISING
);
305 omap_gpio_rmw(base
, bank
->regs
->fallingdetect
, gpio_bit
,
306 trigger
& IRQ_TYPE_EDGE_FALLING
);
308 bank
->context
.leveldetect0
=
309 readl_relaxed(bank
->base
+ bank
->regs
->leveldetect0
);
310 bank
->context
.leveldetect1
=
311 readl_relaxed(bank
->base
+ bank
->regs
->leveldetect1
);
312 bank
->context
.risingdetect
=
313 readl_relaxed(bank
->base
+ bank
->regs
->risingdetect
);
314 bank
->context
.fallingdetect
=
315 readl_relaxed(bank
->base
+ bank
->regs
->fallingdetect
);
317 if (likely(!(bank
->non_wakeup_gpios
& gpio_bit
))) {
318 omap_gpio_rmw(base
, bank
->regs
->wkup_en
, gpio_bit
, trigger
!= 0);
319 bank
->context
.wake_en
=
320 readl_relaxed(bank
->base
+ bank
->regs
->wkup_en
);
323 /* This part needs to be executed always for OMAP{34xx, 44xx} */
324 if (!bank
->regs
->irqctrl
) {
325 /* On omap24xx proceed only when valid GPIO bit is set */
326 if (bank
->non_wakeup_gpios
) {
327 if (!(bank
->non_wakeup_gpios
& gpio_bit
))
332 * Log the edge gpio and manually trigger the IRQ
333 * after resume if the input level changes
334 * to avoid irq lost during PER RET/OFF mode
335 * Applies for omap2 non-wakeup gpio and all omap3 gpios
337 if (trigger
& IRQ_TYPE_EDGE_BOTH
)
338 bank
->enabled_non_wakeup_gpios
|= gpio_bit
;
340 bank
->enabled_non_wakeup_gpios
&= ~gpio_bit
;
345 readl_relaxed(bank
->base
+ bank
->regs
->leveldetect0
) |
346 readl_relaxed(bank
->base
+ bank
->regs
->leveldetect1
);
349 #ifdef CONFIG_ARCH_OMAP1
351 * This only applies to chips that can't do both rising and falling edge
352 * detection at once. For all other chips, this function is a noop.
354 static void omap_toggle_gpio_edge_triggering(struct gpio_bank
*bank
, int gpio
)
356 void __iomem
*reg
= bank
->base
;
359 if (!bank
->regs
->irqctrl
)
362 reg
+= bank
->regs
->irqctrl
;
364 l
= readl_relaxed(reg
);
370 writel_relaxed(l
, reg
);
373 static void omap_toggle_gpio_edge_triggering(struct gpio_bank
*bank
, int gpio
) {}
376 static int omap_set_gpio_triggering(struct gpio_bank
*bank
, int gpio
,
379 void __iomem
*reg
= bank
->base
;
380 void __iomem
*base
= bank
->base
;
383 if (bank
->regs
->leveldetect0
&& bank
->regs
->wkup_en
) {
384 omap_set_gpio_trigger(bank
, gpio
, trigger
);
385 } else if (bank
->regs
->irqctrl
) {
386 reg
+= bank
->regs
->irqctrl
;
388 l
= readl_relaxed(reg
);
389 if ((trigger
& IRQ_TYPE_SENSE_MASK
) == IRQ_TYPE_EDGE_BOTH
)
390 bank
->toggle_mask
|= BIT(gpio
);
391 if (trigger
& IRQ_TYPE_EDGE_RISING
)
393 else if (trigger
& IRQ_TYPE_EDGE_FALLING
)
398 writel_relaxed(l
, reg
);
399 } else if (bank
->regs
->edgectrl1
) {
401 reg
+= bank
->regs
->edgectrl2
;
403 reg
+= bank
->regs
->edgectrl1
;
406 l
= readl_relaxed(reg
);
407 l
&= ~(3 << (gpio
<< 1));
408 if (trigger
& IRQ_TYPE_EDGE_RISING
)
409 l
|= 2 << (gpio
<< 1);
410 if (trigger
& IRQ_TYPE_EDGE_FALLING
)
413 /* Enable wake-up during idle for dynamic tick */
414 omap_gpio_rmw(base
, bank
->regs
->wkup_en
, BIT(gpio
), trigger
);
415 bank
->context
.wake_en
=
416 readl_relaxed(bank
->base
+ bank
->regs
->wkup_en
);
417 writel_relaxed(l
, reg
);
422 static void omap_enable_gpio_module(struct gpio_bank
*bank
, unsigned offset
)
424 if (bank
->regs
->pinctrl
) {
425 void __iomem
*reg
= bank
->base
+ bank
->regs
->pinctrl
;
427 /* Claim the pin for MPU */
428 writel_relaxed(readl_relaxed(reg
) | (BIT(offset
)), reg
);
431 if (bank
->regs
->ctrl
&& !BANK_USED(bank
)) {
432 void __iomem
*reg
= bank
->base
+ bank
->regs
->ctrl
;
435 ctrl
= readl_relaxed(reg
);
436 /* Module is enabled, clocks are not gated */
437 ctrl
&= ~GPIO_MOD_CTRL_BIT
;
438 writel_relaxed(ctrl
, reg
);
439 bank
->context
.ctrl
= ctrl
;
443 static void omap_disable_gpio_module(struct gpio_bank
*bank
, unsigned offset
)
445 void __iomem
*base
= bank
->base
;
447 if (bank
->regs
->wkup_en
&&
448 !LINE_USED(bank
->mod_usage
, offset
) &&
449 !LINE_USED(bank
->irq_usage
, offset
)) {
450 /* Disable wake-up during idle for dynamic tick */
451 omap_gpio_rmw(base
, bank
->regs
->wkup_en
, BIT(offset
), 0);
452 bank
->context
.wake_en
=
453 readl_relaxed(bank
->base
+ bank
->regs
->wkup_en
);
456 if (bank
->regs
->ctrl
&& !BANK_USED(bank
)) {
457 void __iomem
*reg
= bank
->base
+ bank
->regs
->ctrl
;
460 ctrl
= readl_relaxed(reg
);
461 /* Module is disabled, clocks are gated */
462 ctrl
|= GPIO_MOD_CTRL_BIT
;
463 writel_relaxed(ctrl
, reg
);
464 bank
->context
.ctrl
= ctrl
;
468 static int omap_gpio_is_input(struct gpio_bank
*bank
, unsigned offset
)
470 void __iomem
*reg
= bank
->base
+ bank
->regs
->direction
;
472 return readl_relaxed(reg
) & BIT(offset
);
475 static void omap_gpio_init_irq(struct gpio_bank
*bank
, unsigned offset
)
477 if (!LINE_USED(bank
->mod_usage
, offset
)) {
478 omap_enable_gpio_module(bank
, offset
);
479 omap_set_gpio_direction(bank
, offset
, 1);
481 bank
->irq_usage
|= BIT(offset
);
484 static int omap_gpio_irq_type(struct irq_data
*d
, unsigned type
)
486 struct gpio_bank
*bank
= omap_irq_data_get_bank(d
);
489 unsigned offset
= d
->hwirq
;
491 if (type
& ~IRQ_TYPE_SENSE_MASK
)
494 if (!bank
->regs
->leveldetect0
&&
495 (type
& (IRQ_TYPE_LEVEL_LOW
|IRQ_TYPE_LEVEL_HIGH
)))
498 if (!BANK_USED(bank
))
499 pm_runtime_get_sync(bank
->dev
);
501 spin_lock_irqsave(&bank
->lock
, flags
);
502 retval
= omap_set_gpio_triggering(bank
, offset
, type
);
505 omap_gpio_init_irq(bank
, offset
);
506 if (!omap_gpio_is_input(bank
, offset
)) {
507 spin_unlock_irqrestore(&bank
->lock
, flags
);
511 spin_unlock_irqrestore(&bank
->lock
, flags
);
513 if (type
& (IRQ_TYPE_LEVEL_LOW
| IRQ_TYPE_LEVEL_HIGH
))
514 __irq_set_handler_locked(d
->irq
, handle_level_irq
);
515 else if (type
& (IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
))
516 __irq_set_handler_locked(d
->irq
, handle_edge_irq
);
521 if (!BANK_USED(bank
))
522 pm_runtime_put(bank
->dev
);
526 static void omap_clear_gpio_irqbank(struct gpio_bank
*bank
, int gpio_mask
)
528 void __iomem
*reg
= bank
->base
;
530 reg
+= bank
->regs
->irqstatus
;
531 writel_relaxed(gpio_mask
, reg
);
533 /* Workaround for clearing DSP GPIO interrupts to allow retention */
534 if (bank
->regs
->irqstatus2
) {
535 reg
= bank
->base
+ bank
->regs
->irqstatus2
;
536 writel_relaxed(gpio_mask
, reg
);
539 /* Flush posted write for the irq status to avoid spurious interrupts */
543 static inline void omap_clear_gpio_irqstatus(struct gpio_bank
*bank
,
546 omap_clear_gpio_irqbank(bank
, BIT(offset
));
549 static u32
omap_get_gpio_irqbank_mask(struct gpio_bank
*bank
)
551 void __iomem
*reg
= bank
->base
;
553 u32 mask
= (BIT(bank
->width
)) - 1;
555 reg
+= bank
->regs
->irqenable
;
556 l
= readl_relaxed(reg
);
557 if (bank
->regs
->irqenable_inv
)
563 static void omap_enable_gpio_irqbank(struct gpio_bank
*bank
, int gpio_mask
)
565 void __iomem
*reg
= bank
->base
;
568 if (bank
->regs
->set_irqenable
) {
569 reg
+= bank
->regs
->set_irqenable
;
571 bank
->context
.irqenable1
|= gpio_mask
;
573 reg
+= bank
->regs
->irqenable
;
574 l
= readl_relaxed(reg
);
575 if (bank
->regs
->irqenable_inv
)
579 bank
->context
.irqenable1
= l
;
582 writel_relaxed(l
, reg
);
585 static void omap_disable_gpio_irqbank(struct gpio_bank
*bank
, int gpio_mask
)
587 void __iomem
*reg
= bank
->base
;
590 if (bank
->regs
->clr_irqenable
) {
591 reg
+= bank
->regs
->clr_irqenable
;
593 bank
->context
.irqenable1
&= ~gpio_mask
;
595 reg
+= bank
->regs
->irqenable
;
596 l
= readl_relaxed(reg
);
597 if (bank
->regs
->irqenable_inv
)
601 bank
->context
.irqenable1
= l
;
604 writel_relaxed(l
, reg
);
607 static inline void omap_set_gpio_irqenable(struct gpio_bank
*bank
,
608 unsigned offset
, int enable
)
611 omap_enable_gpio_irqbank(bank
, BIT(offset
));
613 omap_disable_gpio_irqbank(bank
, BIT(offset
));
617 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
618 * 1510 does not seem to have a wake-up register. If JTAG is connected
619 * to the target, system will wake up always on GPIO events. While
620 * system is running all registered GPIO interrupts need to have wake-up
621 * enabled. When system is suspended, only selected GPIO interrupts need
622 * to have wake-up enabled.
624 static int omap_set_gpio_wakeup(struct gpio_bank
*bank
, unsigned offset
,
627 u32 gpio_bit
= BIT(offset
);
630 if (bank
->non_wakeup_gpios
& gpio_bit
) {
632 "Unable to modify wakeup on non-wakeup GPIO%d\n",
637 spin_lock_irqsave(&bank
->lock
, flags
);
639 bank
->context
.wake_en
|= gpio_bit
;
641 bank
->context
.wake_en
&= ~gpio_bit
;
643 writel_relaxed(bank
->context
.wake_en
, bank
->base
+ bank
->regs
->wkup_en
);
644 spin_unlock_irqrestore(&bank
->lock
, flags
);
649 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
650 static int omap_gpio_wake_enable(struct irq_data
*d
, unsigned int enable
)
652 struct gpio_bank
*bank
= omap_irq_data_get_bank(d
);
653 unsigned offset
= d
->hwirq
;
655 return omap_set_gpio_wakeup(bank
, offset
, enable
);
658 static int omap_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
660 struct gpio_bank
*bank
= container_of(chip
, struct gpio_bank
, chip
);
664 * If this is the first gpio_request for the bank,
665 * enable the bank module.
667 if (!BANK_USED(bank
))
668 pm_runtime_get_sync(bank
->dev
);
670 spin_lock_irqsave(&bank
->lock
, flags
);
671 omap_enable_gpio_module(bank
, offset
);
672 bank
->mod_usage
|= BIT(offset
);
673 spin_unlock_irqrestore(&bank
->lock
, flags
);
678 static void omap_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
680 struct gpio_bank
*bank
= container_of(chip
, struct gpio_bank
, chip
);
683 spin_lock_irqsave(&bank
->lock
, flags
);
684 bank
->mod_usage
&= ~(BIT(offset
));
685 if (!LINE_USED(bank
->irq_usage
, offset
)) {
686 omap_set_gpio_direction(bank
, offset
, 1);
687 omap_clear_gpio_debounce(bank
, offset
);
689 omap_disable_gpio_module(bank
, offset
);
690 spin_unlock_irqrestore(&bank
->lock
, flags
);
693 * If this is the last gpio to be freed in the bank,
694 * disable the bank module.
696 if (!BANK_USED(bank
))
697 pm_runtime_put(bank
->dev
);
701 * We need to unmask the GPIO bank interrupt as soon as possible to
702 * avoid missing GPIO interrupts for other lines in the bank.
703 * Then we need to mask-read-clear-unmask the triggered GPIO lines
704 * in the bank to avoid missing nested interrupts for a GPIO line.
705 * If we wait to unmask individual GPIO lines in the bank after the
706 * line's interrupt handler has been run, we may miss some nested
709 static void omap_gpio_irq_handler(unsigned int irq
, struct irq_desc
*desc
)
711 void __iomem
*isr_reg
= NULL
;
714 struct gpio_bank
*bank
;
716 struct irq_chip
*irqchip
= irq_desc_get_chip(desc
);
717 struct gpio_chip
*chip
= irq_get_handler_data(irq
);
719 chained_irq_enter(irqchip
, desc
);
721 bank
= container_of(chip
, struct gpio_bank
, chip
);
722 isr_reg
= bank
->base
+ bank
->regs
->irqstatus
;
723 pm_runtime_get_sync(bank
->dev
);
725 if (WARN_ON(!isr_reg
))
729 u32 isr_saved
, level_mask
= 0;
732 enabled
= omap_get_gpio_irqbank_mask(bank
);
733 isr_saved
= isr
= readl_relaxed(isr_reg
) & enabled
;
735 if (bank
->level_mask
)
736 level_mask
= bank
->level_mask
& enabled
;
738 /* clear edge sensitive interrupts before handler(s) are
739 called so that we don't miss any interrupt occurred while
741 omap_disable_gpio_irqbank(bank
, isr_saved
& ~level_mask
);
742 omap_clear_gpio_irqbank(bank
, isr_saved
& ~level_mask
);
743 omap_enable_gpio_irqbank(bank
, isr_saved
& ~level_mask
);
745 /* if there is only edge sensitive GPIO pin interrupts
746 configured, we could unmask GPIO bank interrupt immediately */
747 if (!level_mask
&& !unmasked
) {
749 chained_irq_exit(irqchip
, desc
);
760 * Some chips can't respond to both rising and falling
761 * at the same time. If this irq was requested with
762 * both flags, we need to flip the ICR data for the IRQ
763 * to respond to the IRQ for the opposite direction.
764 * This will be indicated in the bank toggle_mask.
766 if (bank
->toggle_mask
& (BIT(bit
)))
767 omap_toggle_gpio_edge_triggering(bank
, bit
);
769 generic_handle_irq(irq_find_mapping(bank
->chip
.irqdomain
,
773 /* if bank has any level sensitive GPIO pin interrupt
774 configured, we must unmask the bank interrupt only after
775 handler(s) are executed in order to avoid spurious bank
779 chained_irq_exit(irqchip
, desc
);
780 pm_runtime_put(bank
->dev
);
783 static unsigned int omap_gpio_irq_startup(struct irq_data
*d
)
785 struct gpio_bank
*bank
= omap_irq_data_get_bank(d
);
787 unsigned offset
= d
->hwirq
;
789 if (!BANK_USED(bank
))
790 pm_runtime_get_sync(bank
->dev
);
792 spin_lock_irqsave(&bank
->lock
, flags
);
794 if (!LINE_USED(bank
->mod_usage
, offset
))
795 omap_set_gpio_direction(bank
, offset
, 1);
796 else if (!omap_gpio_is_input(bank
, offset
))
798 omap_enable_gpio_module(bank
, offset
);
799 bank
->irq_usage
|= BIT(offset
);
801 spin_unlock_irqrestore(&bank
->lock
, flags
);
802 omap_gpio_unmask_irq(d
);
806 spin_unlock_irqrestore(&bank
->lock
, flags
);
807 if (!BANK_USED(bank
))
808 pm_runtime_put(bank
->dev
);
812 static void omap_gpio_irq_shutdown(struct irq_data
*d
)
814 struct gpio_bank
*bank
= omap_irq_data_get_bank(d
);
816 unsigned offset
= d
->hwirq
;
818 spin_lock_irqsave(&bank
->lock
, flags
);
819 bank
->irq_usage
&= ~(BIT(offset
));
820 omap_set_gpio_irqenable(bank
, offset
, 0);
821 omap_clear_gpio_irqstatus(bank
, offset
);
822 omap_set_gpio_triggering(bank
, offset
, IRQ_TYPE_NONE
);
823 if (!LINE_USED(bank
->mod_usage
, offset
))
824 omap_clear_gpio_debounce(bank
, offset
);
825 omap_disable_gpio_module(bank
, offset
);
826 spin_unlock_irqrestore(&bank
->lock
, flags
);
829 * If this is the last IRQ to be freed in the bank,
830 * disable the bank module.
832 if (!BANK_USED(bank
))
833 pm_runtime_put(bank
->dev
);
836 static void omap_gpio_ack_irq(struct irq_data
*d
)
838 struct gpio_bank
*bank
= omap_irq_data_get_bank(d
);
839 unsigned offset
= d
->hwirq
;
841 omap_clear_gpio_irqstatus(bank
, offset
);
844 static void omap_gpio_mask_irq(struct irq_data
*d
)
846 struct gpio_bank
*bank
= omap_irq_data_get_bank(d
);
847 unsigned offset
= d
->hwirq
;
850 spin_lock_irqsave(&bank
->lock
, flags
);
851 omap_set_gpio_irqenable(bank
, offset
, 0);
852 omap_set_gpio_triggering(bank
, offset
, IRQ_TYPE_NONE
);
853 spin_unlock_irqrestore(&bank
->lock
, flags
);
856 static void omap_gpio_unmask_irq(struct irq_data
*d
)
858 struct gpio_bank
*bank
= omap_irq_data_get_bank(d
);
859 unsigned offset
= d
->hwirq
;
860 u32 trigger
= irqd_get_trigger_type(d
);
863 spin_lock_irqsave(&bank
->lock
, flags
);
865 omap_set_gpio_triggering(bank
, offset
, trigger
);
867 /* For level-triggered GPIOs, the clearing must be done after
868 * the HW source is cleared, thus after the handler has run */
869 if (bank
->level_mask
& BIT(offset
)) {
870 omap_set_gpio_irqenable(bank
, offset
, 0);
871 omap_clear_gpio_irqstatus(bank
, offset
);
874 omap_set_gpio_irqenable(bank
, offset
, 1);
875 spin_unlock_irqrestore(&bank
->lock
, flags
);
878 /*---------------------------------------------------------------------*/
880 static int omap_mpuio_suspend_noirq(struct device
*dev
)
882 struct platform_device
*pdev
= to_platform_device(dev
);
883 struct gpio_bank
*bank
= platform_get_drvdata(pdev
);
884 void __iomem
*mask_reg
= bank
->base
+
885 OMAP_MPUIO_GPIO_MASKIT
/ bank
->stride
;
888 spin_lock_irqsave(&bank
->lock
, flags
);
889 writel_relaxed(0xffff & ~bank
->context
.wake_en
, mask_reg
);
890 spin_unlock_irqrestore(&bank
->lock
, flags
);
895 static int omap_mpuio_resume_noirq(struct device
*dev
)
897 struct platform_device
*pdev
= to_platform_device(dev
);
898 struct gpio_bank
*bank
= platform_get_drvdata(pdev
);
899 void __iomem
*mask_reg
= bank
->base
+
900 OMAP_MPUIO_GPIO_MASKIT
/ bank
->stride
;
903 spin_lock_irqsave(&bank
->lock
, flags
);
904 writel_relaxed(bank
->context
.wake_en
, mask_reg
);
905 spin_unlock_irqrestore(&bank
->lock
, flags
);
910 static const struct dev_pm_ops omap_mpuio_dev_pm_ops
= {
911 .suspend_noirq
= omap_mpuio_suspend_noirq
,
912 .resume_noirq
= omap_mpuio_resume_noirq
,
915 /* use platform_driver for this. */
916 static struct platform_driver omap_mpuio_driver
= {
919 .pm
= &omap_mpuio_dev_pm_ops
,
923 static struct platform_device omap_mpuio_device
= {
927 .driver
= &omap_mpuio_driver
.driver
,
929 /* could list the /proc/iomem resources */
932 static inline void omap_mpuio_init(struct gpio_bank
*bank
)
934 platform_set_drvdata(&omap_mpuio_device
, bank
);
936 if (platform_driver_register(&omap_mpuio_driver
) == 0)
937 (void) platform_device_register(&omap_mpuio_device
);
940 /*---------------------------------------------------------------------*/
942 static int omap_gpio_get_direction(struct gpio_chip
*chip
, unsigned offset
)
944 struct gpio_bank
*bank
;
949 bank
= container_of(chip
, struct gpio_bank
, chip
);
950 reg
= bank
->base
+ bank
->regs
->direction
;
951 spin_lock_irqsave(&bank
->lock
, flags
);
952 dir
= !!(readl_relaxed(reg
) & BIT(offset
));
953 spin_unlock_irqrestore(&bank
->lock
, flags
);
957 static int omap_gpio_input(struct gpio_chip
*chip
, unsigned offset
)
959 struct gpio_bank
*bank
;
962 bank
= container_of(chip
, struct gpio_bank
, chip
);
963 spin_lock_irqsave(&bank
->lock
, flags
);
964 omap_set_gpio_direction(bank
, offset
, 1);
965 spin_unlock_irqrestore(&bank
->lock
, flags
);
969 static int omap_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
971 struct gpio_bank
*bank
;
973 bank
= container_of(chip
, struct gpio_bank
, chip
);
975 if (omap_gpio_is_input(bank
, offset
))
976 return omap_get_gpio_datain(bank
, offset
);
978 return omap_get_gpio_dataout(bank
, offset
);
981 static int omap_gpio_output(struct gpio_chip
*chip
, unsigned offset
, int value
)
983 struct gpio_bank
*bank
;
986 bank
= container_of(chip
, struct gpio_bank
, chip
);
987 spin_lock_irqsave(&bank
->lock
, flags
);
988 bank
->set_dataout(bank
, offset
, value
);
989 omap_set_gpio_direction(bank
, offset
, 0);
990 spin_unlock_irqrestore(&bank
->lock
, flags
);
994 static int omap_gpio_debounce(struct gpio_chip
*chip
, unsigned offset
,
997 struct gpio_bank
*bank
;
1000 bank
= container_of(chip
, struct gpio_bank
, chip
);
1002 spin_lock_irqsave(&bank
->lock
, flags
);
1003 omap2_set_gpio_debounce(bank
, offset
, debounce
);
1004 spin_unlock_irqrestore(&bank
->lock
, flags
);
1009 static void omap_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
1011 struct gpio_bank
*bank
;
1012 unsigned long flags
;
1014 bank
= container_of(chip
, struct gpio_bank
, chip
);
1015 spin_lock_irqsave(&bank
->lock
, flags
);
1016 bank
->set_dataout(bank
, offset
, value
);
1017 spin_unlock_irqrestore(&bank
->lock
, flags
);
1020 /*---------------------------------------------------------------------*/
1022 static void __init
omap_gpio_show_rev(struct gpio_bank
*bank
)
1027 if (called
|| bank
->regs
->revision
== USHRT_MAX
)
1030 rev
= readw_relaxed(bank
->base
+ bank
->regs
->revision
);
1031 pr_info("OMAP GPIO hardware version %d.%d\n",
1032 (rev
>> 4) & 0x0f, rev
& 0x0f);
1037 static void omap_gpio_mod_init(struct gpio_bank
*bank
)
1039 void __iomem
*base
= bank
->base
;
1042 if (bank
->width
== 16)
1045 if (bank
->is_mpuio
) {
1046 writel_relaxed(l
, bank
->base
+ bank
->regs
->irqenable
);
1050 omap_gpio_rmw(base
, bank
->regs
->irqenable
, l
,
1051 bank
->regs
->irqenable_inv
);
1052 omap_gpio_rmw(base
, bank
->regs
->irqstatus
, l
,
1053 !bank
->regs
->irqenable_inv
);
1054 if (bank
->regs
->debounce_en
)
1055 writel_relaxed(0, base
+ bank
->regs
->debounce_en
);
1057 /* Save OE default value (0xffffffff) in the context */
1058 bank
->context
.oe
= readl_relaxed(bank
->base
+ bank
->regs
->direction
);
1059 /* Initialize interface clk ungated, module enabled */
1060 if (bank
->regs
->ctrl
)
1061 writel_relaxed(0, base
+ bank
->regs
->ctrl
);
1063 bank
->dbck
= clk_get(bank
->dev
, "dbclk");
1064 if (IS_ERR(bank
->dbck
))
1065 dev_err(bank
->dev
, "Could not get gpio dbck\n");
1068 static int omap_gpio_chip_init(struct gpio_bank
*bank
, struct irq_chip
*irqc
)
1075 * REVISIT eventually switch from OMAP-specific gpio structs
1076 * over to the generic ones
1078 bank
->chip
.request
= omap_gpio_request
;
1079 bank
->chip
.free
= omap_gpio_free
;
1080 bank
->chip
.get_direction
= omap_gpio_get_direction
;
1081 bank
->chip
.direction_input
= omap_gpio_input
;
1082 bank
->chip
.get
= omap_gpio_get
;
1083 bank
->chip
.direction_output
= omap_gpio_output
;
1084 bank
->chip
.set_debounce
= omap_gpio_debounce
;
1085 bank
->chip
.set
= omap_gpio_set
;
1086 if (bank
->is_mpuio
) {
1087 bank
->chip
.label
= "mpuio";
1088 if (bank
->regs
->wkup_en
)
1089 bank
->chip
.dev
= &omap_mpuio_device
.dev
;
1090 bank
->chip
.base
= OMAP_MPUIO(0);
1092 bank
->chip
.label
= "gpio";
1093 bank
->chip
.base
= gpio
;
1094 gpio
+= bank
->width
;
1096 bank
->chip
.ngpio
= bank
->width
;
1098 ret
= gpiochip_add(&bank
->chip
);
1100 dev_err(bank
->dev
, "Could not register gpio chip %d\n", ret
);
1104 #ifdef CONFIG_ARCH_OMAP1
1106 * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
1107 * irq_alloc_descs() since a base IRQ offset will no longer be needed.
1109 irq_base
= irq_alloc_descs(-1, 0, bank
->width
, 0);
1111 dev_err(bank
->dev
, "Couldn't allocate IRQ numbers\n");
1116 /* MPUIO is a bit different, reading IRQ status clears it */
1117 if (bank
->is_mpuio
) {
1118 irqc
->irq_ack
= dummy_irq_chip
.irq_ack
;
1119 irqc
->irq_mask
= irq_gc_mask_set_bit
;
1120 irqc
->irq_unmask
= irq_gc_mask_clr_bit
;
1121 if (!bank
->regs
->wkup_en
)
1122 irqc
->irq_set_wake
= NULL
;
1125 ret
= gpiochip_irqchip_add(&bank
->chip
, irqc
,
1126 irq_base
, omap_gpio_irq_handler
,
1130 dev_err(bank
->dev
, "Couldn't add irqchip to gpiochip %d\n", ret
);
1131 gpiochip_remove(&bank
->chip
);
1135 gpiochip_set_chained_irqchip(&bank
->chip
, irqc
,
1136 bank
->irq
, omap_gpio_irq_handler
);
1141 static const struct of_device_id omap_gpio_match
[];
1143 static int omap_gpio_probe(struct platform_device
*pdev
)
1145 struct device
*dev
= &pdev
->dev
;
1146 struct device_node
*node
= dev
->of_node
;
1147 const struct of_device_id
*match
;
1148 const struct omap_gpio_platform_data
*pdata
;
1149 struct resource
*res
;
1150 struct gpio_bank
*bank
;
1151 struct irq_chip
*irqc
;
1154 match
= of_match_device(of_match_ptr(omap_gpio_match
), dev
);
1156 pdata
= match
? match
->data
: dev_get_platdata(dev
);
1160 bank
= devm_kzalloc(dev
, sizeof(struct gpio_bank
), GFP_KERNEL
);
1162 dev_err(dev
, "Memory alloc failed\n");
1166 irqc
= devm_kzalloc(dev
, sizeof(*irqc
), GFP_KERNEL
);
1170 irqc
->irq_startup
= omap_gpio_irq_startup
,
1171 irqc
->irq_shutdown
= omap_gpio_irq_shutdown
,
1172 irqc
->irq_ack
= omap_gpio_ack_irq
,
1173 irqc
->irq_mask
= omap_gpio_mask_irq
,
1174 irqc
->irq_unmask
= omap_gpio_unmask_irq
,
1175 irqc
->irq_set_type
= omap_gpio_irq_type
,
1176 irqc
->irq_set_wake
= omap_gpio_wake_enable
,
1177 irqc
->name
= dev_name(&pdev
->dev
);
1179 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
1180 if (unlikely(!res
)) {
1181 dev_err(dev
, "Invalid IRQ resource\n");
1185 bank
->irq
= res
->start
;
1187 bank
->chip
.dev
= dev
;
1188 bank
->dbck_flag
= pdata
->dbck_flag
;
1189 bank
->stride
= pdata
->bank_stride
;
1190 bank
->width
= pdata
->bank_width
;
1191 bank
->is_mpuio
= pdata
->is_mpuio
;
1192 bank
->non_wakeup_gpios
= pdata
->non_wakeup_gpios
;
1193 bank
->regs
= pdata
->regs
;
1194 #ifdef CONFIG_OF_GPIO
1195 bank
->chip
.of_node
= of_node_get(node
);
1198 if (!of_property_read_bool(node
, "ti,gpio-always-on"))
1199 bank
->loses_context
= true;
1201 bank
->loses_context
= pdata
->loses_context
;
1203 if (bank
->loses_context
)
1204 bank
->get_context_loss_count
=
1205 pdata
->get_context_loss_count
;
1208 if (bank
->regs
->set_dataout
&& bank
->regs
->clr_dataout
)
1209 bank
->set_dataout
= omap_set_gpio_dataout_reg
;
1211 bank
->set_dataout
= omap_set_gpio_dataout_mask
;
1213 spin_lock_init(&bank
->lock
);
1215 /* Static mapping, never released */
1216 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1217 bank
->base
= devm_ioremap_resource(dev
, res
);
1218 if (IS_ERR(bank
->base
)) {
1219 irq_domain_remove(bank
->chip
.irqdomain
);
1220 return PTR_ERR(bank
->base
);
1223 platform_set_drvdata(pdev
, bank
);
1225 pm_runtime_enable(bank
->dev
);
1226 pm_runtime_irq_safe(bank
->dev
);
1227 pm_runtime_get_sync(bank
->dev
);
1230 omap_mpuio_init(bank
);
1232 omap_gpio_mod_init(bank
);
1234 ret
= omap_gpio_chip_init(bank
, irqc
);
1238 omap_gpio_show_rev(bank
);
1240 pm_runtime_put(bank
->dev
);
1242 list_add_tail(&bank
->node
, &omap_gpio_list
);
1247 static int omap_gpio_remove(struct platform_device
*pdev
)
1249 struct gpio_bank
*bank
= platform_get_drvdata(pdev
);
1251 list_del(&bank
->node
);
1252 gpiochip_remove(&bank
->chip
);
1253 pm_runtime_disable(bank
->dev
);
1258 #ifdef CONFIG_ARCH_OMAP2PLUS
1260 #if defined(CONFIG_PM)
1261 static void omap_gpio_restore_context(struct gpio_bank
*bank
);
1263 static int omap_gpio_runtime_suspend(struct device
*dev
)
1265 struct platform_device
*pdev
= to_platform_device(dev
);
1266 struct gpio_bank
*bank
= platform_get_drvdata(pdev
);
1268 unsigned long flags
;
1269 u32 wake_low
, wake_hi
;
1271 spin_lock_irqsave(&bank
->lock
, flags
);
1274 * Only edges can generate a wakeup event to the PRCM.
1276 * Therefore, ensure any wake-up capable GPIOs have
1277 * edge-detection enabled before going idle to ensure a wakeup
1278 * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1281 * The normal values will be restored upon ->runtime_resume()
1282 * by writing back the values saved in bank->context.
1284 wake_low
= bank
->context
.leveldetect0
& bank
->context
.wake_en
;
1286 writel_relaxed(wake_low
| bank
->context
.fallingdetect
,
1287 bank
->base
+ bank
->regs
->fallingdetect
);
1288 wake_hi
= bank
->context
.leveldetect1
& bank
->context
.wake_en
;
1290 writel_relaxed(wake_hi
| bank
->context
.risingdetect
,
1291 bank
->base
+ bank
->regs
->risingdetect
);
1293 if (!bank
->enabled_non_wakeup_gpios
)
1294 goto update_gpio_context_count
;
1296 if (bank
->power_mode
!= OFF_MODE
) {
1297 bank
->power_mode
= 0;
1298 goto update_gpio_context_count
;
1301 * If going to OFF, remove triggering for all
1302 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1303 * generated. See OMAP2420 Errata item 1.101.
1305 bank
->saved_datain
= readl_relaxed(bank
->base
+
1306 bank
->regs
->datain
);
1307 l1
= bank
->context
.fallingdetect
;
1308 l2
= bank
->context
.risingdetect
;
1310 l1
&= ~bank
->enabled_non_wakeup_gpios
;
1311 l2
&= ~bank
->enabled_non_wakeup_gpios
;
1313 writel_relaxed(l1
, bank
->base
+ bank
->regs
->fallingdetect
);
1314 writel_relaxed(l2
, bank
->base
+ bank
->regs
->risingdetect
);
1316 bank
->workaround_enabled
= true;
1318 update_gpio_context_count
:
1319 if (bank
->get_context_loss_count
)
1320 bank
->context_loss_count
=
1321 bank
->get_context_loss_count(bank
->dev
);
1323 omap_gpio_dbck_disable(bank
);
1324 spin_unlock_irqrestore(&bank
->lock
, flags
);
1329 static void omap_gpio_init_context(struct gpio_bank
*p
);
1331 static int omap_gpio_runtime_resume(struct device
*dev
)
1333 struct platform_device
*pdev
= to_platform_device(dev
);
1334 struct gpio_bank
*bank
= platform_get_drvdata(pdev
);
1335 u32 l
= 0, gen
, gen0
, gen1
;
1336 unsigned long flags
;
1339 spin_lock_irqsave(&bank
->lock
, flags
);
1342 * On the first resume during the probe, the context has not
1343 * been initialised and so initialise it now. Also initialise
1344 * the context loss count.
1346 if (bank
->loses_context
&& !bank
->context_valid
) {
1347 omap_gpio_init_context(bank
);
1349 if (bank
->get_context_loss_count
)
1350 bank
->context_loss_count
=
1351 bank
->get_context_loss_count(bank
->dev
);
1354 omap_gpio_dbck_enable(bank
);
1357 * In ->runtime_suspend(), level-triggered, wakeup-enabled
1358 * GPIOs were set to edge trigger also in order to be able to
1359 * generate a PRCM wakeup. Here we restore the
1360 * pre-runtime_suspend() values for edge triggering.
1362 writel_relaxed(bank
->context
.fallingdetect
,
1363 bank
->base
+ bank
->regs
->fallingdetect
);
1364 writel_relaxed(bank
->context
.risingdetect
,
1365 bank
->base
+ bank
->regs
->risingdetect
);
1367 if (bank
->loses_context
) {
1368 if (!bank
->get_context_loss_count
) {
1369 omap_gpio_restore_context(bank
);
1371 c
= bank
->get_context_loss_count(bank
->dev
);
1372 if (c
!= bank
->context_loss_count
) {
1373 omap_gpio_restore_context(bank
);
1375 spin_unlock_irqrestore(&bank
->lock
, flags
);
1381 if (!bank
->workaround_enabled
) {
1382 spin_unlock_irqrestore(&bank
->lock
, flags
);
1386 l
= readl_relaxed(bank
->base
+ bank
->regs
->datain
);
1389 * Check if any of the non-wakeup interrupt GPIOs have changed
1390 * state. If so, generate an IRQ by software. This is
1391 * horribly racy, but it's the best we can do to work around
1394 l
^= bank
->saved_datain
;
1395 l
&= bank
->enabled_non_wakeup_gpios
;
1398 * No need to generate IRQs for the rising edge for gpio IRQs
1399 * configured with falling edge only; and vice versa.
1401 gen0
= l
& bank
->context
.fallingdetect
;
1402 gen0
&= bank
->saved_datain
;
1404 gen1
= l
& bank
->context
.risingdetect
;
1405 gen1
&= ~(bank
->saved_datain
);
1407 /* FIXME: Consider GPIO IRQs with level detections properly! */
1408 gen
= l
& (~(bank
->context
.fallingdetect
) &
1409 ~(bank
->context
.risingdetect
));
1410 /* Consider all GPIO IRQs needed to be updated */
1416 old0
= readl_relaxed(bank
->base
+ bank
->regs
->leveldetect0
);
1417 old1
= readl_relaxed(bank
->base
+ bank
->regs
->leveldetect1
);
1419 if (!bank
->regs
->irqstatus_raw0
) {
1420 writel_relaxed(old0
| gen
, bank
->base
+
1421 bank
->regs
->leveldetect0
);
1422 writel_relaxed(old1
| gen
, bank
->base
+
1423 bank
->regs
->leveldetect1
);
1426 if (bank
->regs
->irqstatus_raw0
) {
1427 writel_relaxed(old0
| l
, bank
->base
+
1428 bank
->regs
->leveldetect0
);
1429 writel_relaxed(old1
| l
, bank
->base
+
1430 bank
->regs
->leveldetect1
);
1432 writel_relaxed(old0
, bank
->base
+ bank
->regs
->leveldetect0
);
1433 writel_relaxed(old1
, bank
->base
+ bank
->regs
->leveldetect1
);
1436 bank
->workaround_enabled
= false;
1437 spin_unlock_irqrestore(&bank
->lock
, flags
);
1441 #endif /* CONFIG_PM */
1443 #if IS_BUILTIN(CONFIG_GPIO_OMAP)
1444 void omap2_gpio_prepare_for_idle(int pwr_mode
)
1446 struct gpio_bank
*bank
;
1448 list_for_each_entry(bank
, &omap_gpio_list
, node
) {
1449 if (!BANK_USED(bank
) || !bank
->loses_context
)
1452 bank
->power_mode
= pwr_mode
;
1454 pm_runtime_put_sync_suspend(bank
->dev
);
1458 void omap2_gpio_resume_after_idle(void)
1460 struct gpio_bank
*bank
;
1462 list_for_each_entry(bank
, &omap_gpio_list
, node
) {
1463 if (!BANK_USED(bank
) || !bank
->loses_context
)
1466 pm_runtime_get_sync(bank
->dev
);
1471 #if defined(CONFIG_PM)
1472 static void omap_gpio_init_context(struct gpio_bank
*p
)
1474 struct omap_gpio_reg_offs
*regs
= p
->regs
;
1475 void __iomem
*base
= p
->base
;
1477 p
->context
.ctrl
= readl_relaxed(base
+ regs
->ctrl
);
1478 p
->context
.oe
= readl_relaxed(base
+ regs
->direction
);
1479 p
->context
.wake_en
= readl_relaxed(base
+ regs
->wkup_en
);
1480 p
->context
.leveldetect0
= readl_relaxed(base
+ regs
->leveldetect0
);
1481 p
->context
.leveldetect1
= readl_relaxed(base
+ regs
->leveldetect1
);
1482 p
->context
.risingdetect
= readl_relaxed(base
+ regs
->risingdetect
);
1483 p
->context
.fallingdetect
= readl_relaxed(base
+ regs
->fallingdetect
);
1484 p
->context
.irqenable1
= readl_relaxed(base
+ regs
->irqenable
);
1485 p
->context
.irqenable2
= readl_relaxed(base
+ regs
->irqenable2
);
1487 if (regs
->set_dataout
&& p
->regs
->clr_dataout
)
1488 p
->context
.dataout
= readl_relaxed(base
+ regs
->set_dataout
);
1490 p
->context
.dataout
= readl_relaxed(base
+ regs
->dataout
);
1492 p
->context_valid
= true;
1495 static void omap_gpio_restore_context(struct gpio_bank
*bank
)
1497 writel_relaxed(bank
->context
.wake_en
,
1498 bank
->base
+ bank
->regs
->wkup_en
);
1499 writel_relaxed(bank
->context
.ctrl
, bank
->base
+ bank
->regs
->ctrl
);
1500 writel_relaxed(bank
->context
.leveldetect0
,
1501 bank
->base
+ bank
->regs
->leveldetect0
);
1502 writel_relaxed(bank
->context
.leveldetect1
,
1503 bank
->base
+ bank
->regs
->leveldetect1
);
1504 writel_relaxed(bank
->context
.risingdetect
,
1505 bank
->base
+ bank
->regs
->risingdetect
);
1506 writel_relaxed(bank
->context
.fallingdetect
,
1507 bank
->base
+ bank
->regs
->fallingdetect
);
1508 if (bank
->regs
->set_dataout
&& bank
->regs
->clr_dataout
)
1509 writel_relaxed(bank
->context
.dataout
,
1510 bank
->base
+ bank
->regs
->set_dataout
);
1512 writel_relaxed(bank
->context
.dataout
,
1513 bank
->base
+ bank
->regs
->dataout
);
1514 writel_relaxed(bank
->context
.oe
, bank
->base
+ bank
->regs
->direction
);
1516 if (bank
->dbck_enable_mask
) {
1517 writel_relaxed(bank
->context
.debounce
, bank
->base
+
1518 bank
->regs
->debounce
);
1519 writel_relaxed(bank
->context
.debounce_en
,
1520 bank
->base
+ bank
->regs
->debounce_en
);
1523 writel_relaxed(bank
->context
.irqenable1
,
1524 bank
->base
+ bank
->regs
->irqenable
);
1525 writel_relaxed(bank
->context
.irqenable2
,
1526 bank
->base
+ bank
->regs
->irqenable2
);
1528 #endif /* CONFIG_PM */
1530 #define omap_gpio_runtime_suspend NULL
1531 #define omap_gpio_runtime_resume NULL
1532 static inline void omap_gpio_init_context(struct gpio_bank
*p
) {}
1535 static const struct dev_pm_ops gpio_pm_ops
= {
1536 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend
, omap_gpio_runtime_resume
,
1540 #if defined(CONFIG_OF)
1541 static struct omap_gpio_reg_offs omap2_gpio_regs
= {
1542 .revision
= OMAP24XX_GPIO_REVISION
,
1543 .direction
= OMAP24XX_GPIO_OE
,
1544 .datain
= OMAP24XX_GPIO_DATAIN
,
1545 .dataout
= OMAP24XX_GPIO_DATAOUT
,
1546 .set_dataout
= OMAP24XX_GPIO_SETDATAOUT
,
1547 .clr_dataout
= OMAP24XX_GPIO_CLEARDATAOUT
,
1548 .irqstatus
= OMAP24XX_GPIO_IRQSTATUS1
,
1549 .irqstatus2
= OMAP24XX_GPIO_IRQSTATUS2
,
1550 .irqenable
= OMAP24XX_GPIO_IRQENABLE1
,
1551 .irqenable2
= OMAP24XX_GPIO_IRQENABLE2
,
1552 .set_irqenable
= OMAP24XX_GPIO_SETIRQENABLE1
,
1553 .clr_irqenable
= OMAP24XX_GPIO_CLEARIRQENABLE1
,
1554 .debounce
= OMAP24XX_GPIO_DEBOUNCE_VAL
,
1555 .debounce_en
= OMAP24XX_GPIO_DEBOUNCE_EN
,
1556 .ctrl
= OMAP24XX_GPIO_CTRL
,
1557 .wkup_en
= OMAP24XX_GPIO_WAKE_EN
,
1558 .leveldetect0
= OMAP24XX_GPIO_LEVELDETECT0
,
1559 .leveldetect1
= OMAP24XX_GPIO_LEVELDETECT1
,
1560 .risingdetect
= OMAP24XX_GPIO_RISINGDETECT
,
1561 .fallingdetect
= OMAP24XX_GPIO_FALLINGDETECT
,
1564 static struct omap_gpio_reg_offs omap4_gpio_regs
= {
1565 .revision
= OMAP4_GPIO_REVISION
,
1566 .direction
= OMAP4_GPIO_OE
,
1567 .datain
= OMAP4_GPIO_DATAIN
,
1568 .dataout
= OMAP4_GPIO_DATAOUT
,
1569 .set_dataout
= OMAP4_GPIO_SETDATAOUT
,
1570 .clr_dataout
= OMAP4_GPIO_CLEARDATAOUT
,
1571 .irqstatus
= OMAP4_GPIO_IRQSTATUS0
,
1572 .irqstatus2
= OMAP4_GPIO_IRQSTATUS1
,
1573 .irqenable
= OMAP4_GPIO_IRQSTATUSSET0
,
1574 .irqenable2
= OMAP4_GPIO_IRQSTATUSSET1
,
1575 .set_irqenable
= OMAP4_GPIO_IRQSTATUSSET0
,
1576 .clr_irqenable
= OMAP4_GPIO_IRQSTATUSCLR0
,
1577 .debounce
= OMAP4_GPIO_DEBOUNCINGTIME
,
1578 .debounce_en
= OMAP4_GPIO_DEBOUNCENABLE
,
1579 .ctrl
= OMAP4_GPIO_CTRL
,
1580 .wkup_en
= OMAP4_GPIO_IRQWAKEN0
,
1581 .leveldetect0
= OMAP4_GPIO_LEVELDETECT0
,
1582 .leveldetect1
= OMAP4_GPIO_LEVELDETECT1
,
1583 .risingdetect
= OMAP4_GPIO_RISINGDETECT
,
1584 .fallingdetect
= OMAP4_GPIO_FALLINGDETECT
,
1587 static const struct omap_gpio_platform_data omap2_pdata
= {
1588 .regs
= &omap2_gpio_regs
,
1593 static const struct omap_gpio_platform_data omap3_pdata
= {
1594 .regs
= &omap2_gpio_regs
,
1599 static const struct omap_gpio_platform_data omap4_pdata
= {
1600 .regs
= &omap4_gpio_regs
,
1605 static const struct of_device_id omap_gpio_match
[] = {
1607 .compatible
= "ti,omap4-gpio",
1608 .data
= &omap4_pdata
,
1611 .compatible
= "ti,omap3-gpio",
1612 .data
= &omap3_pdata
,
1615 .compatible
= "ti,omap2-gpio",
1616 .data
= &omap2_pdata
,
1620 MODULE_DEVICE_TABLE(of
, omap_gpio_match
);
1623 static struct platform_driver omap_gpio_driver
= {
1624 .probe
= omap_gpio_probe
,
1625 .remove
= omap_gpio_remove
,
1627 .name
= "omap_gpio",
1629 .of_match_table
= of_match_ptr(omap_gpio_match
),
1634 * gpio driver register needs to be done before
1635 * machine_init functions access gpio APIs.
1636 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1638 static int __init
omap_gpio_drv_reg(void)
1640 return platform_driver_register(&omap_gpio_driver
);
1642 postcore_initcall(omap_gpio_drv_reg
);
1644 static void __exit
omap_gpio_exit(void)
1646 platform_driver_unregister(&omap_gpio_driver
);
1648 module_exit(omap_gpio_exit
);
1650 MODULE_DESCRIPTION("omap gpio driver");
1651 MODULE_ALIAS("platform:gpio-omap");
1652 MODULE_LICENSE("GPL v2");