2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
7 Based on the original rt2800pci.c and rt2800usb.c.
8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
14 <http://rt2x00.serialmonkey.com>
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
34 Abstract: rt2800 generic device routines.
37 #include <linux/crc-ccitt.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/slab.h>
43 #include "rt2800lib.h"
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
60 #define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62 #define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64 #define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66 #define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev
*rt2x00dev
)
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev
) ||
74 !rt2x00_rt(rt2x00dev
, RT2872
))
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev
, RF3020
) ||
79 rt2x00_rf(rt2x00dev
, RF3021
) ||
80 rt2x00_rf(rt2x00dev
, RF3022
))
83 rt2x00_warn(rt2x00dev
, "Unknown RF chipset on rt305x\n");
87 static void rt2800_bbp_write(struct rt2x00_dev
*rt2x00dev
,
88 const unsigned int word
, const u8 value
)
92 mutex_lock(&rt2x00dev
->csr_mutex
);
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
98 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
100 rt2x00_set_field32(®
, BBP_CSR_CFG_VALUE
, value
);
101 rt2x00_set_field32(®
, BBP_CSR_CFG_REGNUM
, word
);
102 rt2x00_set_field32(®
, BBP_CSR_CFG_BUSY
, 1);
103 rt2x00_set_field32(®
, BBP_CSR_CFG_READ_CONTROL
, 0);
104 rt2x00_set_field32(®
, BBP_CSR_CFG_BBP_RW_MODE
, 1);
106 rt2800_register_write_lock(rt2x00dev
, BBP_CSR_CFG
, reg
);
109 mutex_unlock(&rt2x00dev
->csr_mutex
);
112 static void rt2800_bbp_read(struct rt2x00_dev
*rt2x00dev
,
113 const unsigned int word
, u8
*value
)
117 mutex_lock(&rt2x00dev
->csr_mutex
);
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
127 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
129 rt2x00_set_field32(®
, BBP_CSR_CFG_REGNUM
, word
);
130 rt2x00_set_field32(®
, BBP_CSR_CFG_BUSY
, 1);
131 rt2x00_set_field32(®
, BBP_CSR_CFG_READ_CONTROL
, 1);
132 rt2x00_set_field32(®
, BBP_CSR_CFG_BBP_RW_MODE
, 1);
134 rt2800_register_write_lock(rt2x00dev
, BBP_CSR_CFG
, reg
);
136 WAIT_FOR_BBP(rt2x00dev
, ®
);
139 *value
= rt2x00_get_field32(reg
, BBP_CSR_CFG_VALUE
);
141 mutex_unlock(&rt2x00dev
->csr_mutex
);
144 static void rt2800_rfcsr_write(struct rt2x00_dev
*rt2x00dev
,
145 const unsigned int word
, const u8 value
)
149 mutex_lock(&rt2x00dev
->csr_mutex
);
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
155 if (WAIT_FOR_RFCSR(rt2x00dev
, ®
)) {
157 rt2x00_set_field32(®
, RF_CSR_CFG_DATA
, value
);
158 rt2x00_set_field32(®
, RF_CSR_CFG_REGNUM
, word
);
159 rt2x00_set_field32(®
, RF_CSR_CFG_WRITE
, 1);
160 rt2x00_set_field32(®
, RF_CSR_CFG_BUSY
, 1);
162 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG
, reg
);
165 mutex_unlock(&rt2x00dev
->csr_mutex
);
168 static void rt2800_rfcsr_read(struct rt2x00_dev
*rt2x00dev
,
169 const unsigned int word
, u8
*value
)
173 mutex_lock(&rt2x00dev
->csr_mutex
);
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
183 if (WAIT_FOR_RFCSR(rt2x00dev
, ®
)) {
185 rt2x00_set_field32(®
, RF_CSR_CFG_REGNUM
, word
);
186 rt2x00_set_field32(®
, RF_CSR_CFG_WRITE
, 0);
187 rt2x00_set_field32(®
, RF_CSR_CFG_BUSY
, 1);
189 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG
, reg
);
191 WAIT_FOR_RFCSR(rt2x00dev
, ®
);
194 *value
= rt2x00_get_field32(reg
, RF_CSR_CFG_DATA
);
196 mutex_unlock(&rt2x00dev
->csr_mutex
);
199 static void rt2800_rf_write(struct rt2x00_dev
*rt2x00dev
,
200 const unsigned int word
, const u32 value
)
204 mutex_lock(&rt2x00dev
->csr_mutex
);
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
210 if (WAIT_FOR_RF(rt2x00dev
, ®
)) {
212 rt2x00_set_field32(®
, RF_CSR_CFG0_REG_VALUE_BW
, value
);
213 rt2x00_set_field32(®
, RF_CSR_CFG0_STANDBYMODE
, 0);
214 rt2x00_set_field32(®
, RF_CSR_CFG0_SEL
, 0);
215 rt2x00_set_field32(®
, RF_CSR_CFG0_BUSY
, 1);
217 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG0
, reg
);
218 rt2x00_rf_write(rt2x00dev
, word
, value
);
221 mutex_unlock(&rt2x00dev
->csr_mutex
);
224 static const unsigned int rt2800_eeprom_map
[EEPROM_WORD_COUNT
] = {
225 [EEPROM_CHIP_ID
] = 0x0000,
226 [EEPROM_VERSION
] = 0x0001,
227 [EEPROM_MAC_ADDR_0
] = 0x0002,
228 [EEPROM_MAC_ADDR_1
] = 0x0003,
229 [EEPROM_MAC_ADDR_2
] = 0x0004,
230 [EEPROM_NIC_CONF0
] = 0x001a,
231 [EEPROM_NIC_CONF1
] = 0x001b,
232 [EEPROM_FREQ
] = 0x001d,
233 [EEPROM_LED_AG_CONF
] = 0x001e,
234 [EEPROM_LED_ACT_CONF
] = 0x001f,
235 [EEPROM_LED_POLARITY
] = 0x0020,
236 [EEPROM_NIC_CONF2
] = 0x0021,
237 [EEPROM_LNA
] = 0x0022,
238 [EEPROM_RSSI_BG
] = 0x0023,
239 [EEPROM_RSSI_BG2
] = 0x0024,
240 [EEPROM_TXMIXER_GAIN_BG
] = 0x0024, /* overlaps with RSSI_BG2 */
241 [EEPROM_RSSI_A
] = 0x0025,
242 [EEPROM_RSSI_A2
] = 0x0026,
243 [EEPROM_TXMIXER_GAIN_A
] = 0x0026, /* overlaps with RSSI_A2 */
244 [EEPROM_EIRP_MAX_TX_POWER
] = 0x0027,
245 [EEPROM_TXPOWER_DELTA
] = 0x0028,
246 [EEPROM_TXPOWER_BG1
] = 0x0029,
247 [EEPROM_TXPOWER_BG2
] = 0x0030,
248 [EEPROM_TSSI_BOUND_BG1
] = 0x0037,
249 [EEPROM_TSSI_BOUND_BG2
] = 0x0038,
250 [EEPROM_TSSI_BOUND_BG3
] = 0x0039,
251 [EEPROM_TSSI_BOUND_BG4
] = 0x003a,
252 [EEPROM_TSSI_BOUND_BG5
] = 0x003b,
253 [EEPROM_TXPOWER_A1
] = 0x003c,
254 [EEPROM_TXPOWER_A2
] = 0x0053,
255 [EEPROM_TSSI_BOUND_A1
] = 0x006a,
256 [EEPROM_TSSI_BOUND_A2
] = 0x006b,
257 [EEPROM_TSSI_BOUND_A3
] = 0x006c,
258 [EEPROM_TSSI_BOUND_A4
] = 0x006d,
259 [EEPROM_TSSI_BOUND_A5
] = 0x006e,
260 [EEPROM_TXPOWER_BYRATE
] = 0x006f,
261 [EEPROM_BBP_START
] = 0x0078,
264 static const unsigned int rt2800_eeprom_map_ext
[EEPROM_WORD_COUNT
] = {
265 [EEPROM_CHIP_ID
] = 0x0000,
266 [EEPROM_VERSION
] = 0x0001,
267 [EEPROM_MAC_ADDR_0
] = 0x0002,
268 [EEPROM_MAC_ADDR_1
] = 0x0003,
269 [EEPROM_MAC_ADDR_2
] = 0x0004,
270 [EEPROM_NIC_CONF0
] = 0x001a,
271 [EEPROM_NIC_CONF1
] = 0x001b,
272 [EEPROM_NIC_CONF2
] = 0x001c,
273 [EEPROM_EIRP_MAX_TX_POWER
] = 0x0020,
274 [EEPROM_FREQ
] = 0x0022,
275 [EEPROM_LED_AG_CONF
] = 0x0023,
276 [EEPROM_LED_ACT_CONF
] = 0x0024,
277 [EEPROM_LED_POLARITY
] = 0x0025,
278 [EEPROM_LNA
] = 0x0026,
279 [EEPROM_EXT_LNA2
] = 0x0027,
280 [EEPROM_RSSI_BG
] = 0x0028,
281 [EEPROM_TXPOWER_DELTA
] = 0x0028, /* Overlaps with RSSI_BG */
282 [EEPROM_RSSI_BG2
] = 0x0029,
283 [EEPROM_TXMIXER_GAIN_BG
] = 0x0029, /* Overlaps with RSSI_BG2 */
284 [EEPROM_RSSI_A
] = 0x002a,
285 [EEPROM_RSSI_A2
] = 0x002b,
286 [EEPROM_TXMIXER_GAIN_A
] = 0x002b, /* Overlaps with RSSI_A2 */
287 [EEPROM_TXPOWER_BG1
] = 0x0030,
288 [EEPROM_TXPOWER_BG2
] = 0x0037,
289 [EEPROM_EXT_TXPOWER_BG3
] = 0x003e,
290 [EEPROM_TSSI_BOUND_BG1
] = 0x0045,
291 [EEPROM_TSSI_BOUND_BG2
] = 0x0046,
292 [EEPROM_TSSI_BOUND_BG3
] = 0x0047,
293 [EEPROM_TSSI_BOUND_BG4
] = 0x0048,
294 [EEPROM_TSSI_BOUND_BG5
] = 0x0049,
295 [EEPROM_TXPOWER_A1
] = 0x004b,
296 [EEPROM_TXPOWER_A2
] = 0x0065,
297 [EEPROM_EXT_TXPOWER_A3
] = 0x007f,
298 [EEPROM_TSSI_BOUND_A1
] = 0x009a,
299 [EEPROM_TSSI_BOUND_A2
] = 0x009b,
300 [EEPROM_TSSI_BOUND_A3
] = 0x009c,
301 [EEPROM_TSSI_BOUND_A4
] = 0x009d,
302 [EEPROM_TSSI_BOUND_A5
] = 0x009e,
303 [EEPROM_TXPOWER_BYRATE
] = 0x00a0,
306 static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev
*rt2x00dev
,
307 const enum rt2800_eeprom_word word
)
309 const unsigned int *map
;
312 if (WARN_ONCE(word
>= EEPROM_WORD_COUNT
,
313 "%s: invalid EEPROM word %d\n",
314 wiphy_name(rt2x00dev
->hw
->wiphy
), word
))
317 if (rt2x00_rt(rt2x00dev
, RT3593
))
318 map
= rt2800_eeprom_map_ext
;
320 map
= rt2800_eeprom_map
;
324 /* Index 0 is valid only for EEPROM_CHIP_ID.
325 * Otherwise it means that the offset of the
326 * given word is not initialized in the map,
327 * or that the field is not usable on the
330 WARN_ONCE(word
!= EEPROM_CHIP_ID
&& index
== 0,
331 "%s: invalid access of EEPROM word %d\n",
332 wiphy_name(rt2x00dev
->hw
->wiphy
), word
);
337 static void *rt2800_eeprom_addr(struct rt2x00_dev
*rt2x00dev
,
338 const enum rt2800_eeprom_word word
)
342 index
= rt2800_eeprom_word_index(rt2x00dev
, word
);
343 return rt2x00_eeprom_addr(rt2x00dev
, index
);
346 static void rt2800_eeprom_read(struct rt2x00_dev
*rt2x00dev
,
347 const enum rt2800_eeprom_word word
, u16
*data
)
351 index
= rt2800_eeprom_word_index(rt2x00dev
, word
);
352 rt2x00_eeprom_read(rt2x00dev
, index
, data
);
355 static void rt2800_eeprom_write(struct rt2x00_dev
*rt2x00dev
,
356 const enum rt2800_eeprom_word word
, u16 data
)
360 index
= rt2800_eeprom_word_index(rt2x00dev
, word
);
361 rt2x00_eeprom_write(rt2x00dev
, index
, data
);
364 static void rt2800_eeprom_read_from_array(struct rt2x00_dev
*rt2x00dev
,
365 const enum rt2800_eeprom_word array
,
371 index
= rt2800_eeprom_word_index(rt2x00dev
, array
);
372 rt2x00_eeprom_read(rt2x00dev
, index
+ offset
, data
);
375 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev
*rt2x00dev
)
380 rt2800_register_read(rt2x00dev
, WLAN_FUN_CTRL
, ®
);
381 if (rt2x00_get_field32(reg
, WLAN_EN
))
384 rt2x00_set_field32(®
, WLAN_GPIO_OUT_OE_BIT_ALL
, 0xff);
385 rt2x00_set_field32(®
, FRC_WL_ANT_SET
, 1);
386 rt2x00_set_field32(®
, WLAN_CLK_EN
, 0);
387 rt2x00_set_field32(®
, WLAN_EN
, 1);
388 rt2800_register_write(rt2x00dev
, WLAN_FUN_CTRL
, reg
);
390 udelay(REGISTER_BUSY_DELAY
);
395 * Check PLL_LD & XTAL_RDY.
397 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
398 rt2800_register_read(rt2x00dev
, CMB_CTRL
, ®
);
399 if (rt2x00_get_field32(reg
, PLL_LD
) &&
400 rt2x00_get_field32(reg
, XTAL_RDY
))
402 udelay(REGISTER_BUSY_DELAY
);
405 if (i
>= REGISTER_BUSY_COUNT
) {
410 rt2800_register_write(rt2x00dev
, 0x58, 0x018);
411 udelay(REGISTER_BUSY_DELAY
);
412 rt2800_register_write(rt2x00dev
, 0x58, 0x418);
413 udelay(REGISTER_BUSY_DELAY
);
414 rt2800_register_write(rt2x00dev
, 0x58, 0x618);
415 udelay(REGISTER_BUSY_DELAY
);
421 rt2800_register_read(rt2x00dev
, WLAN_FUN_CTRL
, ®
);
422 rt2x00_set_field32(®
, PCIE_APP0_CLK_REQ
, 0);
423 rt2x00_set_field32(®
, WLAN_CLK_EN
, 1);
424 rt2x00_set_field32(®
, WLAN_RESET
, 1);
425 rt2800_register_write(rt2x00dev
, WLAN_FUN_CTRL
, reg
);
427 rt2x00_set_field32(®
, WLAN_RESET
, 0);
428 rt2800_register_write(rt2x00dev
, WLAN_FUN_CTRL
, reg
);
430 rt2800_register_write(rt2x00dev
, INT_SOURCE_CSR
, 0x7fffffff);
431 } while (count
!= 0);
436 void rt2800_mcu_request(struct rt2x00_dev
*rt2x00dev
,
437 const u8 command
, const u8 token
,
438 const u8 arg0
, const u8 arg1
)
443 * SOC devices don't support MCU requests.
445 if (rt2x00_is_soc(rt2x00dev
))
448 mutex_lock(&rt2x00dev
->csr_mutex
);
451 * Wait until the MCU becomes available, afterwards we
452 * can safely write the new data into the register.
454 if (WAIT_FOR_MCU(rt2x00dev
, ®
)) {
455 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_OWNER
, 1);
456 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_CMD_TOKEN
, token
);
457 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG0
, arg0
);
458 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG1
, arg1
);
459 rt2800_register_write_lock(rt2x00dev
, H2M_MAILBOX_CSR
, reg
);
462 rt2x00_set_field32(®
, HOST_CMD_CSR_HOST_COMMAND
, command
);
463 rt2800_register_write_lock(rt2x00dev
, HOST_CMD_CSR
, reg
);
466 mutex_unlock(&rt2x00dev
->csr_mutex
);
468 EXPORT_SYMBOL_GPL(rt2800_mcu_request
);
470 int rt2800_wait_csr_ready(struct rt2x00_dev
*rt2x00dev
)
475 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
476 rt2800_register_read(rt2x00dev
, MAC_CSR0
, ®
);
477 if (reg
&& reg
!= ~0)
482 rt2x00_err(rt2x00dev
, "Unstable hardware\n");
485 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready
);
487 int rt2800_wait_wpdma_ready(struct rt2x00_dev
*rt2x00dev
)
493 * Some devices are really slow to respond here. Wait a whole second
496 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
497 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
498 if (!rt2x00_get_field32(reg
, WPDMA_GLO_CFG_TX_DMA_BUSY
) &&
499 !rt2x00_get_field32(reg
, WPDMA_GLO_CFG_RX_DMA_BUSY
))
505 rt2x00_err(rt2x00dev
, "WPDMA TX/RX busy [0x%08x]\n", reg
);
508 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready
);
510 void rt2800_disable_wpdma(struct rt2x00_dev
*rt2x00dev
)
514 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
515 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
516 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_DMA_BUSY
, 0);
517 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
518 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_DMA_BUSY
, 0);
519 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 1);
520 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
522 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma
);
524 static bool rt2800_check_firmware_crc(const u8
*data
, const size_t len
)
530 * The last 2 bytes in the firmware array are the crc checksum itself,
531 * this means that we should never pass those 2 bytes to the crc
534 fw_crc
= (data
[len
- 2] << 8 | data
[len
- 1]);
537 * Use the crc ccitt algorithm.
538 * This will return the same value as the legacy driver which
539 * used bit ordering reversion on the both the firmware bytes
540 * before input input as well as on the final output.
541 * Obviously using crc ccitt directly is much more efficient.
543 crc
= crc_ccitt(~0, data
, len
- 2);
546 * There is a small difference between the crc-itu-t + bitrev and
547 * the crc-ccitt crc calculation. In the latter method the 2 bytes
548 * will be swapped, use swab16 to convert the crc to the correct
553 return fw_crc
== crc
;
556 int rt2800_check_firmware(struct rt2x00_dev
*rt2x00dev
,
557 const u8
*data
, const size_t len
)
564 * PCI(e) & SOC devices require firmware with a length
565 * of 8kb. USB devices require firmware files with a length
566 * of 4kb. Certain USB chipsets however require different firmware,
567 * which Ralink only provides attached to the original firmware
568 * file. Thus for USB devices, firmware files have a length
569 * which is a multiple of 4kb. The firmware for rt3290 chip also
570 * have a length which is a multiple of 4kb.
572 if (rt2x00_is_usb(rt2x00dev
) || rt2x00_rt(rt2x00dev
, RT3290
))
579 * Validate the firmware length
581 if (len
!= fw_len
&& (!multiple
|| (len
% fw_len
) != 0))
582 return FW_BAD_LENGTH
;
585 * Check if the chipset requires one of the upper parts
588 if (rt2x00_is_usb(rt2x00dev
) &&
589 !rt2x00_rt(rt2x00dev
, RT2860
) &&
590 !rt2x00_rt(rt2x00dev
, RT2872
) &&
591 !rt2x00_rt(rt2x00dev
, RT3070
) &&
592 ((len
/ fw_len
) == 1))
593 return FW_BAD_VERSION
;
596 * 8kb firmware files must be checked as if it were
597 * 2 separate firmware files.
599 while (offset
< len
) {
600 if (!rt2800_check_firmware_crc(data
+ offset
, fw_len
))
608 EXPORT_SYMBOL_GPL(rt2800_check_firmware
);
610 int rt2800_load_firmware(struct rt2x00_dev
*rt2x00dev
,
611 const u8
*data
, const size_t len
)
617 if (rt2x00_rt(rt2x00dev
, RT3290
)) {
618 retval
= rt2800_enable_wlan_rt3290(rt2x00dev
);
624 * If driver doesn't wake up firmware here,
625 * rt2800_load_firmware will hang forever when interface is up again.
627 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, 0x00000000);
630 * Wait for stable hardware.
632 if (rt2800_wait_csr_ready(rt2x00dev
))
635 if (rt2x00_is_pci(rt2x00dev
)) {
636 if (rt2x00_rt(rt2x00dev
, RT3290
) ||
637 rt2x00_rt(rt2x00dev
, RT3572
) ||
638 rt2x00_rt(rt2x00dev
, RT5390
) ||
639 rt2x00_rt(rt2x00dev
, RT5392
)) {
640 rt2800_register_read(rt2x00dev
, AUX_CTRL
, ®
);
641 rt2x00_set_field32(®
, AUX_CTRL_FORCE_PCIE_CLK
, 1);
642 rt2x00_set_field32(®
, AUX_CTRL_WAKE_PCIE_EN
, 1);
643 rt2800_register_write(rt2x00dev
, AUX_CTRL
, reg
);
645 rt2800_register_write(rt2x00dev
, PWR_PIN_CFG
, 0x00000002);
648 rt2800_disable_wpdma(rt2x00dev
);
651 * Write firmware to the device.
653 rt2800_drv_write_firmware(rt2x00dev
, data
, len
);
656 * Wait for device to stabilize.
658 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
659 rt2800_register_read(rt2x00dev
, PBF_SYS_CTRL
, ®
);
660 if (rt2x00_get_field32(reg
, PBF_SYS_CTRL_READY
))
665 if (i
== REGISTER_BUSY_COUNT
) {
666 rt2x00_err(rt2x00dev
, "PBF system register not ready\n");
671 * Disable DMA, will be reenabled later when enabling
674 rt2800_disable_wpdma(rt2x00dev
);
677 * Initialize firmware.
679 rt2800_register_write(rt2x00dev
, H2M_BBP_AGENT
, 0);
680 rt2800_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
681 if (rt2x00_is_usb(rt2x00dev
)) {
682 rt2800_register_write(rt2x00dev
, H2M_INT_SRC
, 0);
683 rt2800_mcu_request(rt2x00dev
, MCU_BOOT_SIGNAL
, 0, 0, 0);
689 EXPORT_SYMBOL_GPL(rt2800_load_firmware
);
691 void rt2800_write_tx_data(struct queue_entry
*entry
,
692 struct txentry_desc
*txdesc
)
694 __le32
*txwi
= rt2800_drv_get_txwi(entry
);
699 * Initialize TX Info descriptor
701 rt2x00_desc_read(txwi
, 0, &word
);
702 rt2x00_set_field32(&word
, TXWI_W0_FRAG
,
703 test_bit(ENTRY_TXD_MORE_FRAG
, &txdesc
->flags
));
704 rt2x00_set_field32(&word
, TXWI_W0_MIMO_PS
,
705 test_bit(ENTRY_TXD_HT_MIMO_PS
, &txdesc
->flags
));
706 rt2x00_set_field32(&word
, TXWI_W0_CF_ACK
, 0);
707 rt2x00_set_field32(&word
, TXWI_W0_TS
,
708 test_bit(ENTRY_TXD_REQ_TIMESTAMP
, &txdesc
->flags
));
709 rt2x00_set_field32(&word
, TXWI_W0_AMPDU
,
710 test_bit(ENTRY_TXD_HT_AMPDU
, &txdesc
->flags
));
711 rt2x00_set_field32(&word
, TXWI_W0_MPDU_DENSITY
,
712 txdesc
->u
.ht
.mpdu_density
);
713 rt2x00_set_field32(&word
, TXWI_W0_TX_OP
, txdesc
->u
.ht
.txop
);
714 rt2x00_set_field32(&word
, TXWI_W0_MCS
, txdesc
->u
.ht
.mcs
);
715 rt2x00_set_field32(&word
, TXWI_W0_BW
,
716 test_bit(ENTRY_TXD_HT_BW_40
, &txdesc
->flags
));
717 rt2x00_set_field32(&word
, TXWI_W0_SHORT_GI
,
718 test_bit(ENTRY_TXD_HT_SHORT_GI
, &txdesc
->flags
));
719 rt2x00_set_field32(&word
, TXWI_W0_STBC
, txdesc
->u
.ht
.stbc
);
720 rt2x00_set_field32(&word
, TXWI_W0_PHYMODE
, txdesc
->rate_mode
);
721 rt2x00_desc_write(txwi
, 0, word
);
723 rt2x00_desc_read(txwi
, 1, &word
);
724 rt2x00_set_field32(&word
, TXWI_W1_ACK
,
725 test_bit(ENTRY_TXD_ACK
, &txdesc
->flags
));
726 rt2x00_set_field32(&word
, TXWI_W1_NSEQ
,
727 test_bit(ENTRY_TXD_GENERATE_SEQ
, &txdesc
->flags
));
728 rt2x00_set_field32(&word
, TXWI_W1_BW_WIN_SIZE
, txdesc
->u
.ht
.ba_size
);
729 rt2x00_set_field32(&word
, TXWI_W1_WIRELESS_CLI_ID
,
730 test_bit(ENTRY_TXD_ENCRYPT
, &txdesc
->flags
) ?
731 txdesc
->key_idx
: txdesc
->u
.ht
.wcid
);
732 rt2x00_set_field32(&word
, TXWI_W1_MPDU_TOTAL_BYTE_COUNT
,
734 rt2x00_set_field32(&word
, TXWI_W1_PACKETID_QUEUE
, entry
->queue
->qid
);
735 rt2x00_set_field32(&word
, TXWI_W1_PACKETID_ENTRY
, (entry
->entry_idx
% 3) + 1);
736 rt2x00_desc_write(txwi
, 1, word
);
739 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
740 * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
741 * When TXD_W3_WIV is set to 1 it will use the IV data
742 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
743 * crypto entry in the registers should be used to encrypt the frame.
745 * Nulify all remaining words as well, we don't know how to program them.
747 for (i
= 2; i
< entry
->queue
->winfo_size
/ sizeof(__le32
); i
++)
748 _rt2x00_desc_write(txwi
, i
, 0);
750 EXPORT_SYMBOL_GPL(rt2800_write_tx_data
);
752 static int rt2800_agc_to_rssi(struct rt2x00_dev
*rt2x00dev
, u32 rxwi_w2
)
754 s8 rssi0
= rt2x00_get_field32(rxwi_w2
, RXWI_W2_RSSI0
);
755 s8 rssi1
= rt2x00_get_field32(rxwi_w2
, RXWI_W2_RSSI1
);
756 s8 rssi2
= rt2x00_get_field32(rxwi_w2
, RXWI_W2_RSSI2
);
762 if (rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
) {
763 rt2800_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG
, &eeprom
);
764 offset0
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG_OFFSET0
);
765 offset1
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG_OFFSET1
);
766 rt2800_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &eeprom
);
767 offset2
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG2_OFFSET2
);
769 rt2800_eeprom_read(rt2x00dev
, EEPROM_RSSI_A
, &eeprom
);
770 offset0
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A_OFFSET0
);
771 offset1
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A_OFFSET1
);
772 rt2800_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &eeprom
);
773 offset2
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A2_OFFSET2
);
777 * Convert the value from the descriptor into the RSSI value
778 * If the value in the descriptor is 0, it is considered invalid
779 * and the default (extremely low) rssi value is assumed
781 rssi0
= (rssi0
) ? (-12 - offset0
- rt2x00dev
->lna_gain
- rssi0
) : -128;
782 rssi1
= (rssi1
) ? (-12 - offset1
- rt2x00dev
->lna_gain
- rssi1
) : -128;
783 rssi2
= (rssi2
) ? (-12 - offset2
- rt2x00dev
->lna_gain
- rssi2
) : -128;
786 * mac80211 only accepts a single RSSI value. Calculating the
787 * average doesn't deliver a fair answer either since -60:-60 would
788 * be considered equally good as -50:-70 while the second is the one
789 * which gives less energy...
791 rssi0
= max(rssi0
, rssi1
);
792 return (int)max(rssi0
, rssi2
);
795 void rt2800_process_rxwi(struct queue_entry
*entry
,
796 struct rxdone_entry_desc
*rxdesc
)
798 __le32
*rxwi
= (__le32
*) entry
->skb
->data
;
801 rt2x00_desc_read(rxwi
, 0, &word
);
803 rxdesc
->cipher
= rt2x00_get_field32(word
, RXWI_W0_UDF
);
804 rxdesc
->size
= rt2x00_get_field32(word
, RXWI_W0_MPDU_TOTAL_BYTE_COUNT
);
806 rt2x00_desc_read(rxwi
, 1, &word
);
808 if (rt2x00_get_field32(word
, RXWI_W1_SHORT_GI
))
809 rxdesc
->flags
|= RX_FLAG_SHORT_GI
;
811 if (rt2x00_get_field32(word
, RXWI_W1_BW
))
812 rxdesc
->flags
|= RX_FLAG_40MHZ
;
815 * Detect RX rate, always use MCS as signal type.
817 rxdesc
->dev_flags
|= RXDONE_SIGNAL_MCS
;
818 rxdesc
->signal
= rt2x00_get_field32(word
, RXWI_W1_MCS
);
819 rxdesc
->rate_mode
= rt2x00_get_field32(word
, RXWI_W1_PHYMODE
);
822 * Mask of 0x8 bit to remove the short preamble flag.
824 if (rxdesc
->rate_mode
== RATE_MODE_CCK
)
825 rxdesc
->signal
&= ~0x8;
827 rt2x00_desc_read(rxwi
, 2, &word
);
830 * Convert descriptor AGC value to RSSI value.
832 rxdesc
->rssi
= rt2800_agc_to_rssi(entry
->queue
->rt2x00dev
, word
);
834 * Remove RXWI descriptor from start of the buffer.
836 skb_pull(entry
->skb
, entry
->queue
->winfo_size
);
838 EXPORT_SYMBOL_GPL(rt2800_process_rxwi
);
840 void rt2800_txdone_entry(struct queue_entry
*entry
, u32 status
, __le32
*txwi
)
842 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
843 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
844 struct txdone_entry_desc txdesc
;
850 * Obtain the status about this packet.
853 rt2x00_desc_read(txwi
, 0, &word
);
855 mcs
= rt2x00_get_field32(word
, TXWI_W0_MCS
);
856 ampdu
= rt2x00_get_field32(word
, TXWI_W0_AMPDU
);
858 real_mcs
= rt2x00_get_field32(status
, TX_STA_FIFO_MCS
);
859 aggr
= rt2x00_get_field32(status
, TX_STA_FIFO_TX_AGGRE
);
862 * If a frame was meant to be sent as a single non-aggregated MPDU
863 * but ended up in an aggregate the used tx rate doesn't correlate
864 * with the one specified in the TXWI as the whole aggregate is sent
865 * with the same rate.
867 * For example: two frames are sent to rt2x00, the first one sets
868 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
869 * and requests MCS15. If the hw aggregates both frames into one
870 * AMDPU the tx status for both frames will contain MCS7 although
871 * the frame was sent successfully.
873 * Hence, replace the requested rate with the real tx rate to not
874 * confuse the rate control algortihm by providing clearly wrong
877 if (unlikely(aggr
== 1 && ampdu
== 0 && real_mcs
!= mcs
)) {
878 skbdesc
->tx_rate_idx
= real_mcs
;
882 if (aggr
== 1 || ampdu
== 1)
883 __set_bit(TXDONE_AMPDU
, &txdesc
.flags
);
886 * Ralink has a retry mechanism using a global fallback
887 * table. We setup this fallback table to try the immediate
888 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
889 * always contains the MCS used for the last transmission, be
890 * it successful or not.
892 if (rt2x00_get_field32(status
, TX_STA_FIFO_TX_SUCCESS
)) {
894 * Transmission succeeded. The number of retries is
897 __set_bit(TXDONE_SUCCESS
, &txdesc
.flags
);
898 txdesc
.retry
= ((mcs
> real_mcs
) ? mcs
- real_mcs
: 0);
901 * Transmission failed. The number of retries is
902 * always 7 in this case (for a total number of 8
905 __set_bit(TXDONE_FAILURE
, &txdesc
.flags
);
906 txdesc
.retry
= rt2x00dev
->long_retry
;
910 * the frame was retried at least once
911 * -> hw used fallback rates
914 __set_bit(TXDONE_FALLBACK
, &txdesc
.flags
);
916 rt2x00lib_txdone(entry
, &txdesc
);
918 EXPORT_SYMBOL_GPL(rt2800_txdone_entry
);
920 void rt2800_write_beacon(struct queue_entry
*entry
, struct txentry_desc
*txdesc
)
922 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
923 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
924 unsigned int beacon_base
;
925 unsigned int padding_len
;
927 const int txwi_desc_size
= entry
->queue
->winfo_size
;
930 * Disable beaconing while we are reloading the beacon data,
931 * otherwise we might be sending out invalid data.
933 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
935 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
936 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
939 * Add space for the TXWI in front of the skb.
941 memset(skb_push(entry
->skb
, txwi_desc_size
), 0, txwi_desc_size
);
944 * Register descriptor details in skb frame descriptor.
946 skbdesc
->flags
|= SKBDESC_DESC_IN_SKB
;
947 skbdesc
->desc
= entry
->skb
->data
;
948 skbdesc
->desc_len
= txwi_desc_size
;
951 * Add the TXWI for the beacon to the skb.
953 rt2800_write_tx_data(entry
, txdesc
);
956 * Dump beacon to userspace through debugfs.
958 rt2x00debug_dump_frame(rt2x00dev
, DUMP_FRAME_BEACON
, entry
->skb
);
961 * Write entire beacon with TXWI and padding to register.
963 padding_len
= roundup(entry
->skb
->len
, 4) - entry
->skb
->len
;
964 if (padding_len
&& skb_pad(entry
->skb
, padding_len
)) {
965 rt2x00_err(rt2x00dev
, "Failure padding beacon, aborting\n");
966 /* skb freed by skb_pad() on failure */
968 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, orig_reg
);
972 beacon_base
= HW_BEACON_OFFSET(entry
->entry_idx
);
973 rt2800_register_multiwrite(rt2x00dev
, beacon_base
, entry
->skb
->data
,
974 entry
->skb
->len
+ padding_len
);
977 * Enable beaconing again.
979 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 1);
980 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
983 * Clean up beacon skb.
985 dev_kfree_skb_any(entry
->skb
);
988 EXPORT_SYMBOL_GPL(rt2800_write_beacon
);
990 static inline void rt2800_clear_beacon_register(struct rt2x00_dev
*rt2x00dev
,
991 unsigned int beacon_base
)
994 const int txwi_desc_size
= rt2x00dev
->bcn
->winfo_size
;
997 * For the Beacon base registers we only need to clear
998 * the whole TXWI which (when set to 0) will invalidate
1001 for (i
= 0; i
< txwi_desc_size
; i
+= sizeof(__le32
))
1002 rt2800_register_write(rt2x00dev
, beacon_base
+ i
, 0);
1005 void rt2800_clear_beacon(struct queue_entry
*entry
)
1007 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
1011 * Disable beaconing while we are reloading the beacon data,
1012 * otherwise we might be sending out invalid data.
1014 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
1015 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
1016 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
1021 rt2800_clear_beacon_register(rt2x00dev
,
1022 HW_BEACON_OFFSET(entry
->entry_idx
));
1025 * Enabled beaconing again.
1027 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 1);
1028 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
1030 EXPORT_SYMBOL_GPL(rt2800_clear_beacon
);
1032 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1033 const struct rt2x00debug rt2800_rt2x00debug
= {
1034 .owner
= THIS_MODULE
,
1036 .read
= rt2800_register_read
,
1037 .write
= rt2800_register_write
,
1038 .flags
= RT2X00DEBUGFS_OFFSET
,
1039 .word_base
= CSR_REG_BASE
,
1040 .word_size
= sizeof(u32
),
1041 .word_count
= CSR_REG_SIZE
/ sizeof(u32
),
1044 /* NOTE: The local EEPROM access functions can't
1045 * be used here, use the generic versions instead.
1047 .read
= rt2x00_eeprom_read
,
1048 .write
= rt2x00_eeprom_write
,
1049 .word_base
= EEPROM_BASE
,
1050 .word_size
= sizeof(u16
),
1051 .word_count
= EEPROM_SIZE
/ sizeof(u16
),
1054 .read
= rt2800_bbp_read
,
1055 .write
= rt2800_bbp_write
,
1056 .word_base
= BBP_BASE
,
1057 .word_size
= sizeof(u8
),
1058 .word_count
= BBP_SIZE
/ sizeof(u8
),
1061 .read
= rt2x00_rf_read
,
1062 .write
= rt2800_rf_write
,
1063 .word_base
= RF_BASE
,
1064 .word_size
= sizeof(u32
),
1065 .word_count
= RF_SIZE
/ sizeof(u32
),
1068 .read
= rt2800_rfcsr_read
,
1069 .write
= rt2800_rfcsr_write
,
1070 .word_base
= RFCSR_BASE
,
1071 .word_size
= sizeof(u8
),
1072 .word_count
= RFCSR_SIZE
/ sizeof(u8
),
1075 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug
);
1076 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1078 int rt2800_rfkill_poll(struct rt2x00_dev
*rt2x00dev
)
1082 if (rt2x00_rt(rt2x00dev
, RT3290
)) {
1083 rt2800_register_read(rt2x00dev
, WLAN_FUN_CTRL
, ®
);
1084 return rt2x00_get_field32(reg
, WLAN_GPIO_IN_BIT0
);
1086 rt2800_register_read(rt2x00dev
, GPIO_CTRL
, ®
);
1087 return rt2x00_get_field32(reg
, GPIO_CTRL_VAL2
);
1090 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll
);
1092 #ifdef CONFIG_RT2X00_LIB_LEDS
1093 static void rt2800_brightness_set(struct led_classdev
*led_cdev
,
1094 enum led_brightness brightness
)
1096 struct rt2x00_led
*led
=
1097 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
1098 unsigned int enabled
= brightness
!= LED_OFF
;
1099 unsigned int bg_mode
=
1100 (enabled
&& led
->rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
);
1101 unsigned int polarity
=
1102 rt2x00_get_field16(led
->rt2x00dev
->led_mcu_reg
,
1103 EEPROM_FREQ_LED_POLARITY
);
1104 unsigned int ledmode
=
1105 rt2x00_get_field16(led
->rt2x00dev
->led_mcu_reg
,
1106 EEPROM_FREQ_LED_MODE
);
1109 /* Check for SoC (SOC devices don't support MCU requests) */
1110 if (rt2x00_is_soc(led
->rt2x00dev
)) {
1111 rt2800_register_read(led
->rt2x00dev
, LED_CFG
, ®
);
1113 /* Set LED Polarity */
1114 rt2x00_set_field32(®
, LED_CFG_LED_POLAR
, polarity
);
1117 if (led
->type
== LED_TYPE_RADIO
) {
1118 rt2x00_set_field32(®
, LED_CFG_G_LED_MODE
,
1120 } else if (led
->type
== LED_TYPE_ASSOC
) {
1121 rt2x00_set_field32(®
, LED_CFG_Y_LED_MODE
,
1123 } else if (led
->type
== LED_TYPE_QUALITY
) {
1124 rt2x00_set_field32(®
, LED_CFG_R_LED_MODE
,
1128 rt2800_register_write(led
->rt2x00dev
, LED_CFG
, reg
);
1131 if (led
->type
== LED_TYPE_RADIO
) {
1132 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff, ledmode
,
1133 enabled
? 0x20 : 0);
1134 } else if (led
->type
== LED_TYPE_ASSOC
) {
1135 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff, ledmode
,
1136 enabled
? (bg_mode
? 0x60 : 0xa0) : 0x20);
1137 } else if (led
->type
== LED_TYPE_QUALITY
) {
1139 * The brightness is divided into 6 levels (0 - 5),
1140 * The specs tell us the following levels:
1141 * 0, 1 ,3, 7, 15, 31
1142 * to determine the level in a simple way we can simply
1143 * work with bitshifting:
1146 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED_STRENGTH
, 0xff,
1147 (1 << brightness
/ (LED_FULL
/ 6)) - 1,
1153 static void rt2800_init_led(struct rt2x00_dev
*rt2x00dev
,
1154 struct rt2x00_led
*led
, enum led_type type
)
1156 led
->rt2x00dev
= rt2x00dev
;
1158 led
->led_dev
.brightness_set
= rt2800_brightness_set
;
1159 led
->flags
= LED_INITIALIZED
;
1161 #endif /* CONFIG_RT2X00_LIB_LEDS */
1164 * Configuration handlers.
1166 static void rt2800_config_wcid(struct rt2x00_dev
*rt2x00dev
,
1170 struct mac_wcid_entry wcid_entry
;
1173 offset
= MAC_WCID_ENTRY(wcid
);
1175 memset(&wcid_entry
, 0xff, sizeof(wcid_entry
));
1177 memcpy(wcid_entry
.mac
, address
, ETH_ALEN
);
1179 rt2800_register_multiwrite(rt2x00dev
, offset
,
1180 &wcid_entry
, sizeof(wcid_entry
));
1183 static void rt2800_delete_wcid_attr(struct rt2x00_dev
*rt2x00dev
, int wcid
)
1186 offset
= MAC_WCID_ATTR_ENTRY(wcid
);
1187 rt2800_register_write(rt2x00dev
, offset
, 0);
1190 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev
*rt2x00dev
,
1191 int wcid
, u32 bssidx
)
1193 u32 offset
= MAC_WCID_ATTR_ENTRY(wcid
);
1197 * The BSS Idx numbers is split in a main value of 3 bits,
1198 * and a extended field for adding one additional bit to the value.
1200 rt2800_register_read(rt2x00dev
, offset
, ®
);
1201 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_BSS_IDX
, (bssidx
& 0x7));
1202 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT
,
1203 (bssidx
& 0x8) >> 3);
1204 rt2800_register_write(rt2x00dev
, offset
, reg
);
1207 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev
*rt2x00dev
,
1208 struct rt2x00lib_crypto
*crypto
,
1209 struct ieee80211_key_conf
*key
)
1211 struct mac_iveiv_entry iveiv_entry
;
1215 offset
= MAC_WCID_ATTR_ENTRY(key
->hw_key_idx
);
1217 if (crypto
->cmd
== SET_KEY
) {
1218 rt2800_register_read(rt2x00dev
, offset
, ®
);
1219 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_KEYTAB
,
1220 !!(key
->flags
& IEEE80211_KEY_FLAG_PAIRWISE
));
1222 * Both the cipher as the BSS Idx numbers are split in a main
1223 * value of 3 bits, and a extended field for adding one additional
1226 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER
,
1227 (crypto
->cipher
& 0x7));
1228 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER_EXT
,
1229 (crypto
->cipher
& 0x8) >> 3);
1230 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_RX_WIUDF
, crypto
->cipher
);
1231 rt2800_register_write(rt2x00dev
, offset
, reg
);
1233 /* Delete the cipher without touching the bssidx */
1234 rt2800_register_read(rt2x00dev
, offset
, ®
);
1235 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_KEYTAB
, 0);
1236 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER
, 0);
1237 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER_EXT
, 0);
1238 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_RX_WIUDF
, 0);
1239 rt2800_register_write(rt2x00dev
, offset
, reg
);
1242 offset
= MAC_IVEIV_ENTRY(key
->hw_key_idx
);
1244 memset(&iveiv_entry
, 0, sizeof(iveiv_entry
));
1245 if ((crypto
->cipher
== CIPHER_TKIP
) ||
1246 (crypto
->cipher
== CIPHER_TKIP_NO_MIC
) ||
1247 (crypto
->cipher
== CIPHER_AES
))
1248 iveiv_entry
.iv
[3] |= 0x20;
1249 iveiv_entry
.iv
[3] |= key
->keyidx
<< 6;
1250 rt2800_register_multiwrite(rt2x00dev
, offset
,
1251 &iveiv_entry
, sizeof(iveiv_entry
));
1254 int rt2800_config_shared_key(struct rt2x00_dev
*rt2x00dev
,
1255 struct rt2x00lib_crypto
*crypto
,
1256 struct ieee80211_key_conf
*key
)
1258 struct hw_key_entry key_entry
;
1259 struct rt2x00_field32 field
;
1263 if (crypto
->cmd
== SET_KEY
) {
1264 key
->hw_key_idx
= (4 * crypto
->bssidx
) + key
->keyidx
;
1266 memcpy(key_entry
.key
, crypto
->key
,
1267 sizeof(key_entry
.key
));
1268 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
1269 sizeof(key_entry
.tx_mic
));
1270 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
1271 sizeof(key_entry
.rx_mic
));
1273 offset
= SHARED_KEY_ENTRY(key
->hw_key_idx
);
1274 rt2800_register_multiwrite(rt2x00dev
, offset
,
1275 &key_entry
, sizeof(key_entry
));
1279 * The cipher types are stored over multiple registers
1280 * starting with SHARED_KEY_MODE_BASE each word will have
1281 * 32 bits and contains the cipher types for 2 bssidx each.
1282 * Using the correct defines correctly will cause overhead,
1283 * so just calculate the correct offset.
1285 field
.bit_offset
= 4 * (key
->hw_key_idx
% 8);
1286 field
.bit_mask
= 0x7 << field
.bit_offset
;
1288 offset
= SHARED_KEY_MODE_ENTRY(key
->hw_key_idx
/ 8);
1290 rt2800_register_read(rt2x00dev
, offset
, ®
);
1291 rt2x00_set_field32(®
, field
,
1292 (crypto
->cmd
== SET_KEY
) * crypto
->cipher
);
1293 rt2800_register_write(rt2x00dev
, offset
, reg
);
1296 * Update WCID information
1298 rt2800_config_wcid(rt2x00dev
, crypto
->address
, key
->hw_key_idx
);
1299 rt2800_config_wcid_attr_bssidx(rt2x00dev
, key
->hw_key_idx
,
1301 rt2800_config_wcid_attr_cipher(rt2x00dev
, crypto
, key
);
1305 EXPORT_SYMBOL_GPL(rt2800_config_shared_key
);
1307 static inline int rt2800_find_wcid(struct rt2x00_dev
*rt2x00dev
)
1309 struct mac_wcid_entry wcid_entry
;
1314 * Search for the first free WCID entry and return the corresponding
1317 * Make sure the WCID starts _after_ the last possible shared key
1320 * Since parts of the pairwise key table might be shared with
1321 * the beacon frame buffers 6 & 7 we should only write into the
1322 * first 222 entries.
1324 for (idx
= 33; idx
<= 222; idx
++) {
1325 offset
= MAC_WCID_ENTRY(idx
);
1326 rt2800_register_multiread(rt2x00dev
, offset
, &wcid_entry
,
1327 sizeof(wcid_entry
));
1328 if (is_broadcast_ether_addr(wcid_entry
.mac
))
1333 * Use -1 to indicate that we don't have any more space in the WCID
1339 int rt2800_config_pairwise_key(struct rt2x00_dev
*rt2x00dev
,
1340 struct rt2x00lib_crypto
*crypto
,
1341 struct ieee80211_key_conf
*key
)
1343 struct hw_key_entry key_entry
;
1346 if (crypto
->cmd
== SET_KEY
) {
1348 * Allow key configuration only for STAs that are
1351 if (crypto
->wcid
< 0)
1353 key
->hw_key_idx
= crypto
->wcid
;
1355 memcpy(key_entry
.key
, crypto
->key
,
1356 sizeof(key_entry
.key
));
1357 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
1358 sizeof(key_entry
.tx_mic
));
1359 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
1360 sizeof(key_entry
.rx_mic
));
1362 offset
= PAIRWISE_KEY_ENTRY(key
->hw_key_idx
);
1363 rt2800_register_multiwrite(rt2x00dev
, offset
,
1364 &key_entry
, sizeof(key_entry
));
1368 * Update WCID information
1370 rt2800_config_wcid_attr_cipher(rt2x00dev
, crypto
, key
);
1374 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key
);
1376 int rt2800_sta_add(struct rt2x00_dev
*rt2x00dev
, struct ieee80211_vif
*vif
,
1377 struct ieee80211_sta
*sta
)
1380 struct rt2x00_sta
*sta_priv
= sta_to_rt2x00_sta(sta
);
1383 * Find next free WCID.
1385 wcid
= rt2800_find_wcid(rt2x00dev
);
1388 * Store selected wcid even if it is invalid so that we can
1389 * later decide if the STA is uploaded into the hw.
1391 sta_priv
->wcid
= wcid
;
1394 * No space left in the device, however, we can still communicate
1395 * with the STA -> No error.
1401 * Clean up WCID attributes and write STA address to the device.
1403 rt2800_delete_wcid_attr(rt2x00dev
, wcid
);
1404 rt2800_config_wcid(rt2x00dev
, sta
->addr
, wcid
);
1405 rt2800_config_wcid_attr_bssidx(rt2x00dev
, wcid
,
1406 rt2x00lib_get_bssidx(rt2x00dev
, vif
));
1409 EXPORT_SYMBOL_GPL(rt2800_sta_add
);
1411 int rt2800_sta_remove(struct rt2x00_dev
*rt2x00dev
, int wcid
)
1414 * Remove WCID entry, no need to clean the attributes as they will
1415 * get renewed when the WCID is reused.
1417 rt2800_config_wcid(rt2x00dev
, NULL
, wcid
);
1421 EXPORT_SYMBOL_GPL(rt2800_sta_remove
);
1423 void rt2800_config_filter(struct rt2x00_dev
*rt2x00dev
,
1424 const unsigned int filter_flags
)
1429 * Start configuration steps.
1430 * Note that the version error will always be dropped
1431 * and broadcast frames will always be accepted since
1432 * there is no filter for it at this time.
1434 rt2800_register_read(rt2x00dev
, RX_FILTER_CFG
, ®
);
1435 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CRC_ERROR
,
1436 !(filter_flags
& FIF_FCSFAIL
));
1437 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_PHY_ERROR
,
1438 !(filter_flags
& FIF_PLCPFAIL
));
1439 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_NOT_TO_ME
,
1440 !(filter_flags
& FIF_PROMISC_IN_BSS
));
1441 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_NOT_MY_BSSD
, 0);
1442 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_VER_ERROR
, 1);
1443 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_MULTICAST
,
1444 !(filter_flags
& FIF_ALLMULTI
));
1445 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BROADCAST
, 0);
1446 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_DUPLICATE
, 1);
1447 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CF_END_ACK
,
1448 !(filter_flags
& FIF_CONTROL
));
1449 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CF_END
,
1450 !(filter_flags
& FIF_CONTROL
));
1451 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_ACK
,
1452 !(filter_flags
& FIF_CONTROL
));
1453 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CTS
,
1454 !(filter_flags
& FIF_CONTROL
));
1455 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_RTS
,
1456 !(filter_flags
& FIF_CONTROL
));
1457 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_PSPOLL
,
1458 !(filter_flags
& FIF_PSPOLL
));
1459 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BA
, 0);
1460 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BAR
,
1461 !(filter_flags
& FIF_CONTROL
));
1462 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CNTL
,
1463 !(filter_flags
& FIF_CONTROL
));
1464 rt2800_register_write(rt2x00dev
, RX_FILTER_CFG
, reg
);
1466 EXPORT_SYMBOL_GPL(rt2800_config_filter
);
1468 void rt2800_config_intf(struct rt2x00_dev
*rt2x00dev
, struct rt2x00_intf
*intf
,
1469 struct rt2x00intf_conf
*conf
, const unsigned int flags
)
1472 bool update_bssid
= false;
1474 if (flags
& CONFIG_UPDATE_TYPE
) {
1476 * Enable synchronisation.
1478 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
1479 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_SYNC
, conf
->sync
);
1480 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
1482 if (conf
->sync
== TSF_SYNC_AP_NONE
) {
1484 * Tune beacon queue transmit parameters for AP mode
1486 rt2800_register_read(rt2x00dev
, TBTT_SYNC_CFG
, ®
);
1487 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_CWMIN
, 0);
1488 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_AIFSN
, 1);
1489 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_EXP_WIN
, 32);
1490 rt2x00_set_field32(®
, TBTT_SYNC_CFG_TBTT_ADJUST
, 0);
1491 rt2800_register_write(rt2x00dev
, TBTT_SYNC_CFG
, reg
);
1493 rt2800_register_read(rt2x00dev
, TBTT_SYNC_CFG
, ®
);
1494 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_CWMIN
, 4);
1495 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_AIFSN
, 2);
1496 rt2x00_set_field32(®
, TBTT_SYNC_CFG_BCN_EXP_WIN
, 32);
1497 rt2x00_set_field32(®
, TBTT_SYNC_CFG_TBTT_ADJUST
, 16);
1498 rt2800_register_write(rt2x00dev
, TBTT_SYNC_CFG
, reg
);
1502 if (flags
& CONFIG_UPDATE_MAC
) {
1503 if (flags
& CONFIG_UPDATE_TYPE
&&
1504 conf
->sync
== TSF_SYNC_AP_NONE
) {
1506 * The BSSID register has to be set to our own mac
1507 * address in AP mode.
1509 memcpy(conf
->bssid
, conf
->mac
, sizeof(conf
->mac
));
1510 update_bssid
= true;
1513 if (!is_zero_ether_addr((const u8
*)conf
->mac
)) {
1514 reg
= le32_to_cpu(conf
->mac
[1]);
1515 rt2x00_set_field32(®
, MAC_ADDR_DW1_UNICAST_TO_ME_MASK
, 0xff);
1516 conf
->mac
[1] = cpu_to_le32(reg
);
1519 rt2800_register_multiwrite(rt2x00dev
, MAC_ADDR_DW0
,
1520 conf
->mac
, sizeof(conf
->mac
));
1523 if ((flags
& CONFIG_UPDATE_BSSID
) || update_bssid
) {
1524 if (!is_zero_ether_addr((const u8
*)conf
->bssid
)) {
1525 reg
= le32_to_cpu(conf
->bssid
[1]);
1526 rt2x00_set_field32(®
, MAC_BSSID_DW1_BSS_ID_MASK
, 3);
1527 rt2x00_set_field32(®
, MAC_BSSID_DW1_BSS_BCN_NUM
, 7);
1528 conf
->bssid
[1] = cpu_to_le32(reg
);
1531 rt2800_register_multiwrite(rt2x00dev
, MAC_BSSID_DW0
,
1532 conf
->bssid
, sizeof(conf
->bssid
));
1535 EXPORT_SYMBOL_GPL(rt2800_config_intf
);
1537 static void rt2800_config_ht_opmode(struct rt2x00_dev
*rt2x00dev
,
1538 struct rt2x00lib_erp
*erp
)
1540 bool any_sta_nongf
= !!(erp
->ht_opmode
&
1541 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT
);
1542 u8 protection
= erp
->ht_opmode
& IEEE80211_HT_OP_MODE_PROTECTION
;
1543 u8 mm20_mode
, mm40_mode
, gf20_mode
, gf40_mode
;
1544 u16 mm20_rate
, mm40_rate
, gf20_rate
, gf40_rate
;
1547 /* default protection rate for HT20: OFDM 24M */
1548 mm20_rate
= gf20_rate
= 0x4004;
1550 /* default protection rate for HT40: duplicate OFDM 24M */
1551 mm40_rate
= gf40_rate
= 0x4084;
1553 switch (protection
) {
1554 case IEEE80211_HT_OP_MODE_PROTECTION_NONE
:
1556 * All STAs in this BSS are HT20/40 but there might be
1557 * STAs not supporting greenfield mode.
1558 * => Disable protection for HT transmissions.
1560 mm20_mode
= mm40_mode
= gf20_mode
= gf40_mode
= 0;
1563 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ
:
1565 * All STAs in this BSS are HT20 or HT20/40 but there
1566 * might be STAs not supporting greenfield mode.
1567 * => Protect all HT40 transmissions.
1569 mm20_mode
= gf20_mode
= 0;
1570 mm40_mode
= gf40_mode
= 2;
1573 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER
:
1575 * Nonmember protection:
1576 * According to 802.11n we _should_ protect all
1577 * HT transmissions (but we don't have to).
1579 * But if cts_protection is enabled we _shall_ protect
1580 * all HT transmissions using a CCK rate.
1582 * And if any station is non GF we _shall_ protect
1585 * We decide to protect everything
1586 * -> fall through to mixed mode.
1588 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED
:
1590 * Legacy STAs are present
1591 * => Protect all HT transmissions.
1593 mm20_mode
= mm40_mode
= gf20_mode
= gf40_mode
= 2;
1596 * If erp protection is needed we have to protect HT
1597 * transmissions with CCK 11M long preamble.
1599 if (erp
->cts_protection
) {
1600 /* don't duplicate RTS/CTS in CCK mode */
1601 mm20_rate
= mm40_rate
= 0x0003;
1602 gf20_rate
= gf40_rate
= 0x0003;
1607 /* check for STAs not supporting greenfield mode */
1609 gf20_mode
= gf40_mode
= 2;
1611 /* Update HT protection config */
1612 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
1613 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_RATE
, mm20_rate
);
1614 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_CTRL
, mm20_mode
);
1615 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
1617 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
1618 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_RATE
, mm40_rate
);
1619 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_CTRL
, mm40_mode
);
1620 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
1622 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
1623 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_RATE
, gf20_rate
);
1624 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_CTRL
, gf20_mode
);
1625 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
1627 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
1628 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_RATE
, gf40_rate
);
1629 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_CTRL
, gf40_mode
);
1630 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
1633 void rt2800_config_erp(struct rt2x00_dev
*rt2x00dev
, struct rt2x00lib_erp
*erp
,
1638 if (changed
& BSS_CHANGED_ERP_PREAMBLE
) {
1639 rt2800_register_read(rt2x00dev
, AUTO_RSP_CFG
, ®
);
1640 rt2x00_set_field32(®
, AUTO_RSP_CFG_BAC_ACK_POLICY
,
1641 !!erp
->short_preamble
);
1642 rt2x00_set_field32(®
, AUTO_RSP_CFG_AR_PREAMBLE
,
1643 !!erp
->short_preamble
);
1644 rt2800_register_write(rt2x00dev
, AUTO_RSP_CFG
, reg
);
1647 if (changed
& BSS_CHANGED_ERP_CTS_PROT
) {
1648 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
1649 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_CTRL
,
1650 erp
->cts_protection
? 2 : 0);
1651 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
1654 if (changed
& BSS_CHANGED_BASIC_RATES
) {
1655 rt2800_register_write(rt2x00dev
, LEGACY_BASIC_RATE
,
1657 rt2800_register_write(rt2x00dev
, HT_BASIC_RATE
, 0x00008003);
1660 if (changed
& BSS_CHANGED_ERP_SLOT
) {
1661 rt2800_register_read(rt2x00dev
, BKOFF_SLOT_CFG
, ®
);
1662 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_SLOT_TIME
,
1664 rt2800_register_write(rt2x00dev
, BKOFF_SLOT_CFG
, reg
);
1666 rt2800_register_read(rt2x00dev
, XIFS_TIME_CFG
, ®
);
1667 rt2x00_set_field32(®
, XIFS_TIME_CFG_EIFS
, erp
->eifs
);
1668 rt2800_register_write(rt2x00dev
, XIFS_TIME_CFG
, reg
);
1671 if (changed
& BSS_CHANGED_BEACON_INT
) {
1672 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
1673 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_INTERVAL
,
1674 erp
->beacon_int
* 16);
1675 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
1678 if (changed
& BSS_CHANGED_HT
)
1679 rt2800_config_ht_opmode(rt2x00dev
, erp
);
1681 EXPORT_SYMBOL_GPL(rt2800_config_erp
);
1683 static void rt2800_config_3572bt_ant(struct rt2x00_dev
*rt2x00dev
)
1687 u8 led_ctrl
, led_g_mode
, led_r_mode
;
1689 rt2800_register_read(rt2x00dev
, GPIO_SWITCH
, ®
);
1690 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
) {
1691 rt2x00_set_field32(®
, GPIO_SWITCH_0
, 1);
1692 rt2x00_set_field32(®
, GPIO_SWITCH_1
, 1);
1694 rt2x00_set_field32(®
, GPIO_SWITCH_0
, 0);
1695 rt2x00_set_field32(®
, GPIO_SWITCH_1
, 0);
1697 rt2800_register_write(rt2x00dev
, GPIO_SWITCH
, reg
);
1699 rt2800_register_read(rt2x00dev
, LED_CFG
, ®
);
1700 led_g_mode
= rt2x00_get_field32(reg
, LED_CFG_LED_POLAR
) ? 3 : 0;
1701 led_r_mode
= rt2x00_get_field32(reg
, LED_CFG_LED_POLAR
) ? 0 : 3;
1702 if (led_g_mode
!= rt2x00_get_field32(reg
, LED_CFG_G_LED_MODE
) ||
1703 led_r_mode
!= rt2x00_get_field32(reg
, LED_CFG_R_LED_MODE
)) {
1704 rt2800_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &eeprom
);
1705 led_ctrl
= rt2x00_get_field16(eeprom
, EEPROM_FREQ_LED_MODE
);
1706 if (led_ctrl
== 0 || led_ctrl
> 0x40) {
1707 rt2x00_set_field32(®
, LED_CFG_G_LED_MODE
, led_g_mode
);
1708 rt2x00_set_field32(®
, LED_CFG_R_LED_MODE
, led_r_mode
);
1709 rt2800_register_write(rt2x00dev
, LED_CFG
, reg
);
1711 rt2800_mcu_request(rt2x00dev
, MCU_BAND_SELECT
, 0xff,
1712 (led_g_mode
<< 2) | led_r_mode
, 1);
1717 static void rt2800_set_ant_diversity(struct rt2x00_dev
*rt2x00dev
,
1721 u8 eesk_pin
= (ant
== ANTENNA_A
) ? 1 : 0;
1722 u8 gpio_bit3
= (ant
== ANTENNA_A
) ? 0 : 1;
1724 if (rt2x00_is_pci(rt2x00dev
)) {
1725 rt2800_register_read(rt2x00dev
, E2PROM_CSR
, ®
);
1726 rt2x00_set_field32(®
, E2PROM_CSR_DATA_CLOCK
, eesk_pin
);
1727 rt2800_register_write(rt2x00dev
, E2PROM_CSR
, reg
);
1728 } else if (rt2x00_is_usb(rt2x00dev
))
1729 rt2800_mcu_request(rt2x00dev
, MCU_ANT_SELECT
, 0xff,
1732 rt2800_register_read(rt2x00dev
, GPIO_CTRL
, ®
);
1733 rt2x00_set_field32(®
, GPIO_CTRL_DIR3
, 0);
1734 rt2x00_set_field32(®
, GPIO_CTRL_VAL3
, gpio_bit3
);
1735 rt2800_register_write(rt2x00dev
, GPIO_CTRL
, reg
);
1738 void rt2800_config_ant(struct rt2x00_dev
*rt2x00dev
, struct antenna_setup
*ant
)
1744 rt2800_bbp_read(rt2x00dev
, 1, &r1
);
1745 rt2800_bbp_read(rt2x00dev
, 3, &r3
);
1747 if (rt2x00_rt(rt2x00dev
, RT3572
) &&
1748 test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
))
1749 rt2800_config_3572bt_ant(rt2x00dev
);
1752 * Configure the TX antenna.
1754 switch (ant
->tx_chain_num
) {
1756 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 0);
1759 if (rt2x00_rt(rt2x00dev
, RT3572
) &&
1760 test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
))
1761 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 1);
1763 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 2);
1766 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 0);
1771 * Configure the RX antenna.
1773 switch (ant
->rx_chain_num
) {
1775 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
1776 rt2x00_rt(rt2x00dev
, RT3090
) ||
1777 rt2x00_rt(rt2x00dev
, RT3352
) ||
1778 rt2x00_rt(rt2x00dev
, RT3390
)) {
1779 rt2800_eeprom_read(rt2x00dev
,
1780 EEPROM_NIC_CONF1
, &eeprom
);
1781 if (rt2x00_get_field16(eeprom
,
1782 EEPROM_NIC_CONF1_ANT_DIVERSITY
))
1783 rt2800_set_ant_diversity(rt2x00dev
,
1784 rt2x00dev
->default_ant
.rx
);
1786 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 0);
1789 if (rt2x00_rt(rt2x00dev
, RT3572
) &&
1790 test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
)) {
1791 rt2x00_set_field8(&r3
, BBP3_RX_ADC
, 1);
1792 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
,
1793 rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
);
1794 rt2800_set_ant_diversity(rt2x00dev
, ANTENNA_B
);
1796 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 1);
1800 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 2);
1804 rt2800_bbp_write(rt2x00dev
, 3, r3
);
1805 rt2800_bbp_write(rt2x00dev
, 1, r1
);
1807 EXPORT_SYMBOL_GPL(rt2800_config_ant
);
1809 static void rt2800_config_lna_gain(struct rt2x00_dev
*rt2x00dev
,
1810 struct rt2x00lib_conf
*libconf
)
1815 if (libconf
->rf
.channel
<= 14) {
1816 rt2800_eeprom_read(rt2x00dev
, EEPROM_LNA
, &eeprom
);
1817 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_LNA_BG
);
1818 } else if (libconf
->rf
.channel
<= 64) {
1819 rt2800_eeprom_read(rt2x00dev
, EEPROM_LNA
, &eeprom
);
1820 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_LNA_A0
);
1821 } else if (libconf
->rf
.channel
<= 128) {
1822 rt2800_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &eeprom
);
1823 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG2_LNA_A1
);
1825 rt2800_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &eeprom
);
1826 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A2_LNA_A2
);
1829 rt2x00dev
->lna_gain
= lna_gain
;
1832 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev
*rt2x00dev
,
1833 struct ieee80211_conf
*conf
,
1834 struct rf_channel
*rf
,
1835 struct channel_info
*info
)
1837 rt2x00_set_field32(&rf
->rf4
, RF4_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
1839 if (rt2x00dev
->default_ant
.tx_chain_num
== 1)
1840 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_TX1
, 1);
1842 if (rt2x00dev
->default_ant
.rx_chain_num
== 1) {
1843 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX1
, 1);
1844 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX2
, 1);
1845 } else if (rt2x00dev
->default_ant
.rx_chain_num
== 2)
1846 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX2
, 1);
1848 if (rf
->channel
> 14) {
1850 * When TX power is below 0, we should increase it by 7 to
1851 * make it a positive value (Minimum value is -7).
1852 * However this means that values between 0 and 7 have
1853 * double meaning, and we should set a 7DBm boost flag.
1855 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_A_7DBM_BOOST
,
1856 (info
->default_power1
>= 0));
1858 if (info
->default_power1
< 0)
1859 info
->default_power1
+= 7;
1861 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_A
, info
->default_power1
);
1863 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_A_7DBM_BOOST
,
1864 (info
->default_power2
>= 0));
1866 if (info
->default_power2
< 0)
1867 info
->default_power2
+= 7;
1869 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_A
, info
->default_power2
);
1871 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_G
, info
->default_power1
);
1872 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_G
, info
->default_power2
);
1875 rt2x00_set_field32(&rf
->rf4
, RF4_HT40
, conf_is_ht40(conf
));
1877 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
1878 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
1879 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
1880 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
1884 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
1885 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
1886 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
| 0x00000004);
1887 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
1891 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
1892 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
1893 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
1894 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
1897 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev
*rt2x00dev
,
1898 struct ieee80211_conf
*conf
,
1899 struct rf_channel
*rf
,
1900 struct channel_info
*info
)
1902 struct rt2800_drv_data
*drv_data
= rt2x00dev
->drv_data
;
1903 u8 rfcsr
, calib_tx
, calib_rx
;
1905 rt2800_rfcsr_write(rt2x00dev
, 2, rf
->rf1
);
1907 rt2800_rfcsr_read(rt2x00dev
, 3, &rfcsr
);
1908 rt2x00_set_field8(&rfcsr
, RFCSR3_K
, rf
->rf3
);
1909 rt2800_rfcsr_write(rt2x00dev
, 3, rfcsr
);
1911 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
1912 rt2x00_set_field8(&rfcsr
, RFCSR6_R1
, rf
->rf2
);
1913 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
1915 rt2800_rfcsr_read(rt2x00dev
, 12, &rfcsr
);
1916 rt2x00_set_field8(&rfcsr
, RFCSR12_TX_POWER
, info
->default_power1
);
1917 rt2800_rfcsr_write(rt2x00dev
, 12, rfcsr
);
1919 rt2800_rfcsr_read(rt2x00dev
, 13, &rfcsr
);
1920 rt2x00_set_field8(&rfcsr
, RFCSR13_TX_POWER
, info
->default_power2
);
1921 rt2800_rfcsr_write(rt2x00dev
, 13, rfcsr
);
1923 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
1924 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 0);
1925 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
,
1926 rt2x00dev
->default_ant
.rx_chain_num
<= 1);
1927 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
,
1928 rt2x00dev
->default_ant
.rx_chain_num
<= 2);
1929 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 0);
1930 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
,
1931 rt2x00dev
->default_ant
.tx_chain_num
<= 1);
1932 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
,
1933 rt2x00dev
->default_ant
.tx_chain_num
<= 2);
1934 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
1936 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
1937 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 1);
1938 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
1940 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 0);
1941 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
1943 rt2800_rfcsr_read(rt2x00dev
, 23, &rfcsr
);
1944 rt2x00_set_field8(&rfcsr
, RFCSR23_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
1945 rt2800_rfcsr_write(rt2x00dev
, 23, rfcsr
);
1947 if (rt2x00_rt(rt2x00dev
, RT3390
)) {
1948 calib_tx
= conf_is_ht40(conf
) ? 0x68 : 0x4f;
1949 calib_rx
= conf_is_ht40(conf
) ? 0x6f : 0x4f;
1951 if (conf_is_ht40(conf
)) {
1952 calib_tx
= drv_data
->calibration_bw40
;
1953 calib_rx
= drv_data
->calibration_bw40
;
1955 calib_tx
= drv_data
->calibration_bw20
;
1956 calib_rx
= drv_data
->calibration_bw20
;
1960 rt2800_rfcsr_read(rt2x00dev
, 24, &rfcsr
);
1961 rt2x00_set_field8(&rfcsr
, RFCSR24_TX_CALIB
, calib_tx
);
1962 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr
);
1964 rt2800_rfcsr_read(rt2x00dev
, 31, &rfcsr
);
1965 rt2x00_set_field8(&rfcsr
, RFCSR31_RX_CALIB
, calib_rx
);
1966 rt2800_rfcsr_write(rt2x00dev
, 31, rfcsr
);
1968 rt2800_rfcsr_read(rt2x00dev
, 7, &rfcsr
);
1969 rt2x00_set_field8(&rfcsr
, RFCSR7_RF_TUNING
, 1);
1970 rt2800_rfcsr_write(rt2x00dev
, 7, rfcsr
);
1972 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
1973 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 1);
1974 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
1976 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 0);
1977 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
1980 static void rt2800_config_channel_rf3052(struct rt2x00_dev
*rt2x00dev
,
1981 struct ieee80211_conf
*conf
,
1982 struct rf_channel
*rf
,
1983 struct channel_info
*info
)
1985 struct rt2800_drv_data
*drv_data
= rt2x00dev
->drv_data
;
1989 if (rf
->channel
<= 14) {
1990 rt2800_bbp_write(rt2x00dev
, 25, drv_data
->bbp25
);
1991 rt2800_bbp_write(rt2x00dev
, 26, drv_data
->bbp26
);
1993 rt2800_bbp_write(rt2x00dev
, 25, 0x09);
1994 rt2800_bbp_write(rt2x00dev
, 26, 0xff);
1997 rt2800_rfcsr_write(rt2x00dev
, 2, rf
->rf1
);
1998 rt2800_rfcsr_write(rt2x00dev
, 3, rf
->rf3
);
2000 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
2001 rt2x00_set_field8(&rfcsr
, RFCSR6_R1
, rf
->rf2
);
2002 if (rf
->channel
<= 14)
2003 rt2x00_set_field8(&rfcsr
, RFCSR6_TXDIV
, 2);
2005 rt2x00_set_field8(&rfcsr
, RFCSR6_TXDIV
, 1);
2006 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
2008 rt2800_rfcsr_read(rt2x00dev
, 5, &rfcsr
);
2009 if (rf
->channel
<= 14)
2010 rt2x00_set_field8(&rfcsr
, RFCSR5_R1
, 1);
2012 rt2x00_set_field8(&rfcsr
, RFCSR5_R1
, 2);
2013 rt2800_rfcsr_write(rt2x00dev
, 5, rfcsr
);
2015 rt2800_rfcsr_read(rt2x00dev
, 12, &rfcsr
);
2016 if (rf
->channel
<= 14) {
2017 rt2x00_set_field8(&rfcsr
, RFCSR12_DR0
, 3);
2018 rt2x00_set_field8(&rfcsr
, RFCSR12_TX_POWER
,
2019 info
->default_power1
);
2021 rt2x00_set_field8(&rfcsr
, RFCSR12_DR0
, 7);
2022 rt2x00_set_field8(&rfcsr
, RFCSR12_TX_POWER
,
2023 (info
->default_power1
& 0x3) |
2024 ((info
->default_power1
& 0xC) << 1));
2026 rt2800_rfcsr_write(rt2x00dev
, 12, rfcsr
);
2028 rt2800_rfcsr_read(rt2x00dev
, 13, &rfcsr
);
2029 if (rf
->channel
<= 14) {
2030 rt2x00_set_field8(&rfcsr
, RFCSR13_DR0
, 3);
2031 rt2x00_set_field8(&rfcsr
, RFCSR13_TX_POWER
,
2032 info
->default_power2
);
2034 rt2x00_set_field8(&rfcsr
, RFCSR13_DR0
, 7);
2035 rt2x00_set_field8(&rfcsr
, RFCSR13_TX_POWER
,
2036 (info
->default_power2
& 0x3) |
2037 ((info
->default_power2
& 0xC) << 1));
2039 rt2800_rfcsr_write(rt2x00dev
, 13, rfcsr
);
2041 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
2042 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 0);
2043 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 0);
2044 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 0);
2045 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 0);
2046 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
, 0);
2047 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
, 0);
2048 if (test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
)) {
2049 if (rf
->channel
<= 14) {
2050 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 1);
2051 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 1);
2053 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
, 1);
2054 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
, 1);
2056 switch (rt2x00dev
->default_ant
.tx_chain_num
) {
2058 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 1);
2060 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
, 1);
2064 switch (rt2x00dev
->default_ant
.rx_chain_num
) {
2066 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 1);
2068 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
, 1);
2072 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
2074 rt2800_rfcsr_read(rt2x00dev
, 23, &rfcsr
);
2075 rt2x00_set_field8(&rfcsr
, RFCSR23_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
2076 rt2800_rfcsr_write(rt2x00dev
, 23, rfcsr
);
2078 if (conf_is_ht40(conf
)) {
2079 rt2800_rfcsr_write(rt2x00dev
, 24, drv_data
->calibration_bw40
);
2080 rt2800_rfcsr_write(rt2x00dev
, 31, drv_data
->calibration_bw40
);
2082 rt2800_rfcsr_write(rt2x00dev
, 24, drv_data
->calibration_bw20
);
2083 rt2800_rfcsr_write(rt2x00dev
, 31, drv_data
->calibration_bw20
);
2086 if (rf
->channel
<= 14) {
2087 rt2800_rfcsr_write(rt2x00dev
, 7, 0xd8);
2088 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc3);
2089 rt2800_rfcsr_write(rt2x00dev
, 10, 0xf1);
2090 rt2800_rfcsr_write(rt2x00dev
, 11, 0xb9);
2091 rt2800_rfcsr_write(rt2x00dev
, 15, 0x53);
2093 rt2x00_set_field8(&rfcsr
, RFCSR16_TXMIXER_GAIN
,
2094 drv_data
->txmixer_gain_24g
);
2095 rt2800_rfcsr_write(rt2x00dev
, 16, rfcsr
);
2096 rt2800_rfcsr_write(rt2x00dev
, 17, 0x23);
2097 rt2800_rfcsr_write(rt2x00dev
, 19, 0x93);
2098 rt2800_rfcsr_write(rt2x00dev
, 20, 0xb3);
2099 rt2800_rfcsr_write(rt2x00dev
, 25, 0x15);
2100 rt2800_rfcsr_write(rt2x00dev
, 26, 0x85);
2101 rt2800_rfcsr_write(rt2x00dev
, 27, 0x00);
2102 rt2800_rfcsr_write(rt2x00dev
, 29, 0x9b);
2104 rt2800_rfcsr_read(rt2x00dev
, 7, &rfcsr
);
2105 rt2x00_set_field8(&rfcsr
, RFCSR7_BIT2
, 1);
2106 rt2x00_set_field8(&rfcsr
, RFCSR7_BIT3
, 0);
2107 rt2x00_set_field8(&rfcsr
, RFCSR7_BIT4
, 1);
2108 rt2x00_set_field8(&rfcsr
, RFCSR7_BITS67
, 0);
2109 rt2800_rfcsr_write(rt2x00dev
, 7, rfcsr
);
2110 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc0);
2111 rt2800_rfcsr_write(rt2x00dev
, 10, 0xf1);
2112 rt2800_rfcsr_write(rt2x00dev
, 11, 0x00);
2113 rt2800_rfcsr_write(rt2x00dev
, 15, 0x43);
2115 rt2x00_set_field8(&rfcsr
, RFCSR16_TXMIXER_GAIN
,
2116 drv_data
->txmixer_gain_5g
);
2117 rt2800_rfcsr_write(rt2x00dev
, 16, rfcsr
);
2118 rt2800_rfcsr_write(rt2x00dev
, 17, 0x23);
2119 if (rf
->channel
<= 64) {
2120 rt2800_rfcsr_write(rt2x00dev
, 19, 0xb7);
2121 rt2800_rfcsr_write(rt2x00dev
, 20, 0xf6);
2122 rt2800_rfcsr_write(rt2x00dev
, 25, 0x3d);
2123 } else if (rf
->channel
<= 128) {
2124 rt2800_rfcsr_write(rt2x00dev
, 19, 0x74);
2125 rt2800_rfcsr_write(rt2x00dev
, 20, 0xf4);
2126 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
2128 rt2800_rfcsr_write(rt2x00dev
, 19, 0x72);
2129 rt2800_rfcsr_write(rt2x00dev
, 20, 0xf3);
2130 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
2132 rt2800_rfcsr_write(rt2x00dev
, 26, 0x87);
2133 rt2800_rfcsr_write(rt2x00dev
, 27, 0x01);
2134 rt2800_rfcsr_write(rt2x00dev
, 29, 0x9f);
2137 rt2800_register_read(rt2x00dev
, GPIO_CTRL
, ®
);
2138 rt2x00_set_field32(®
, GPIO_CTRL_DIR7
, 0);
2139 if (rf
->channel
<= 14)
2140 rt2x00_set_field32(®
, GPIO_CTRL_VAL7
, 1);
2142 rt2x00_set_field32(®
, GPIO_CTRL_VAL7
, 0);
2143 rt2800_register_write(rt2x00dev
, GPIO_CTRL
, reg
);
2145 rt2800_rfcsr_read(rt2x00dev
, 7, &rfcsr
);
2146 rt2x00_set_field8(&rfcsr
, RFCSR7_RF_TUNING
, 1);
2147 rt2800_rfcsr_write(rt2x00dev
, 7, rfcsr
);
2150 #define POWER_BOUND 0x27
2151 #define POWER_BOUND_5G 0x2b
2152 #define FREQ_OFFSET_BOUND 0x5f
2154 static void rt2800_adjust_freq_offset(struct rt2x00_dev
*rt2x00dev
)
2158 rt2800_rfcsr_read(rt2x00dev
, 17, &rfcsr
);
2159 if (rt2x00dev
->freq_offset
> FREQ_OFFSET_BOUND
)
2160 rt2x00_set_field8(&rfcsr
, RFCSR17_CODE
, FREQ_OFFSET_BOUND
);
2162 rt2x00_set_field8(&rfcsr
, RFCSR17_CODE
, rt2x00dev
->freq_offset
);
2163 rt2800_rfcsr_write(rt2x00dev
, 17, rfcsr
);
2166 static void rt2800_config_channel_rf3290(struct rt2x00_dev
*rt2x00dev
,
2167 struct ieee80211_conf
*conf
,
2168 struct rf_channel
*rf
,
2169 struct channel_info
*info
)
2173 rt2800_rfcsr_write(rt2x00dev
, 8, rf
->rf1
);
2174 rt2800_rfcsr_write(rt2x00dev
, 9, rf
->rf3
);
2175 rt2800_rfcsr_read(rt2x00dev
, 11, &rfcsr
);
2176 rt2x00_set_field8(&rfcsr
, RFCSR11_R
, rf
->rf2
);
2177 rt2800_rfcsr_write(rt2x00dev
, 11, rfcsr
);
2179 rt2800_rfcsr_read(rt2x00dev
, 49, &rfcsr
);
2180 if (info
->default_power1
> POWER_BOUND
)
2181 rt2x00_set_field8(&rfcsr
, RFCSR49_TX
, POWER_BOUND
);
2183 rt2x00_set_field8(&rfcsr
, RFCSR49_TX
, info
->default_power1
);
2184 rt2800_rfcsr_write(rt2x00dev
, 49, rfcsr
);
2186 rt2800_adjust_freq_offset(rt2x00dev
);
2188 if (rf
->channel
<= 14) {
2189 if (rf
->channel
== 6)
2190 rt2800_bbp_write(rt2x00dev
, 68, 0x0c);
2192 rt2800_bbp_write(rt2x00dev
, 68, 0x0b);
2194 if (rf
->channel
>= 1 && rf
->channel
<= 6)
2195 rt2800_bbp_write(rt2x00dev
, 59, 0x0f);
2196 else if (rf
->channel
>= 7 && rf
->channel
<= 11)
2197 rt2800_bbp_write(rt2x00dev
, 59, 0x0e);
2198 else if (rf
->channel
>= 12 && rf
->channel
<= 14)
2199 rt2800_bbp_write(rt2x00dev
, 59, 0x0d);
2203 static void rt2800_config_channel_rf3322(struct rt2x00_dev
*rt2x00dev
,
2204 struct ieee80211_conf
*conf
,
2205 struct rf_channel
*rf
,
2206 struct channel_info
*info
)
2210 rt2800_rfcsr_write(rt2x00dev
, 8, rf
->rf1
);
2211 rt2800_rfcsr_write(rt2x00dev
, 9, rf
->rf3
);
2213 rt2800_rfcsr_write(rt2x00dev
, 11, 0x42);
2214 rt2800_rfcsr_write(rt2x00dev
, 12, 0x1c);
2215 rt2800_rfcsr_write(rt2x00dev
, 13, 0x00);
2217 if (info
->default_power1
> POWER_BOUND
)
2218 rt2800_rfcsr_write(rt2x00dev
, 47, POWER_BOUND
);
2220 rt2800_rfcsr_write(rt2x00dev
, 47, info
->default_power1
);
2222 if (info
->default_power2
> POWER_BOUND
)
2223 rt2800_rfcsr_write(rt2x00dev
, 48, POWER_BOUND
);
2225 rt2800_rfcsr_write(rt2x00dev
, 48, info
->default_power2
);
2227 rt2800_adjust_freq_offset(rt2x00dev
);
2229 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
2230 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 1);
2231 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 1);
2233 if ( rt2x00dev
->default_ant
.tx_chain_num
== 2 )
2234 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 1);
2236 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 0);
2238 if ( rt2x00dev
->default_ant
.rx_chain_num
== 2 )
2239 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 1);
2241 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 0);
2243 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
, 0);
2244 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
, 0);
2246 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
2248 rt2800_rfcsr_write(rt2x00dev
, 31, 80);
2251 static void rt2800_config_channel_rf53xx(struct rt2x00_dev
*rt2x00dev
,
2252 struct ieee80211_conf
*conf
,
2253 struct rf_channel
*rf
,
2254 struct channel_info
*info
)
2258 rt2800_rfcsr_write(rt2x00dev
, 8, rf
->rf1
);
2259 rt2800_rfcsr_write(rt2x00dev
, 9, rf
->rf3
);
2260 rt2800_rfcsr_read(rt2x00dev
, 11, &rfcsr
);
2261 rt2x00_set_field8(&rfcsr
, RFCSR11_R
, rf
->rf2
);
2262 rt2800_rfcsr_write(rt2x00dev
, 11, rfcsr
);
2264 rt2800_rfcsr_read(rt2x00dev
, 49, &rfcsr
);
2265 if (info
->default_power1
> POWER_BOUND
)
2266 rt2x00_set_field8(&rfcsr
, RFCSR49_TX
, POWER_BOUND
);
2268 rt2x00_set_field8(&rfcsr
, RFCSR49_TX
, info
->default_power1
);
2269 rt2800_rfcsr_write(rt2x00dev
, 49, rfcsr
);
2271 if (rt2x00_rt(rt2x00dev
, RT5392
)) {
2272 rt2800_rfcsr_read(rt2x00dev
, 50, &rfcsr
);
2273 if (info
->default_power1
> POWER_BOUND
)
2274 rt2x00_set_field8(&rfcsr
, RFCSR50_TX
, POWER_BOUND
);
2276 rt2x00_set_field8(&rfcsr
, RFCSR50_TX
,
2277 info
->default_power2
);
2278 rt2800_rfcsr_write(rt2x00dev
, 50, rfcsr
);
2281 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
2282 if (rt2x00_rt(rt2x00dev
, RT5392
)) {
2283 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 1);
2284 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 1);
2286 rt2x00_set_field8(&rfcsr
, RFCSR1_RF_BLOCK_EN
, 1);
2287 rt2x00_set_field8(&rfcsr
, RFCSR1_PLL_PD
, 1);
2288 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 1);
2289 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 1);
2290 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
2292 rt2800_adjust_freq_offset(rt2x00dev
);
2294 if (rf
->channel
<= 14) {
2295 int idx
= rf
->channel
-1;
2297 if (test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
)) {
2298 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
)) {
2299 /* r55/r59 value array of channel 1~14 */
2300 static const char r55_bt_rev
[] = {0x83, 0x83,
2301 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2302 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2303 static const char r59_bt_rev
[] = {0x0e, 0x0e,
2304 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2305 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2307 rt2800_rfcsr_write(rt2x00dev
, 55,
2309 rt2800_rfcsr_write(rt2x00dev
, 59,
2312 static const char r59_bt
[] = {0x8b, 0x8b, 0x8b,
2313 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2314 0x88, 0x88, 0x86, 0x85, 0x84};
2316 rt2800_rfcsr_write(rt2x00dev
, 59, r59_bt
[idx
]);
2319 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
)) {
2320 static const char r55_nonbt_rev
[] = {0x23, 0x23,
2321 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2322 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2323 static const char r59_nonbt_rev
[] = {0x07, 0x07,
2324 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2325 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2327 rt2800_rfcsr_write(rt2x00dev
, 55,
2328 r55_nonbt_rev
[idx
]);
2329 rt2800_rfcsr_write(rt2x00dev
, 59,
2330 r59_nonbt_rev
[idx
]);
2331 } else if (rt2x00_rt(rt2x00dev
, RT5390
) ||
2332 rt2x00_rt(rt2x00dev
, RT5392
)) {
2333 static const char r59_non_bt
[] = {0x8f, 0x8f,
2334 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2335 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2337 rt2800_rfcsr_write(rt2x00dev
, 59,
2344 static void rt2800_config_channel_rf55xx(struct rt2x00_dev
*rt2x00dev
,
2345 struct ieee80211_conf
*conf
,
2346 struct rf_channel
*rf
,
2347 struct channel_info
*info
)
2354 const bool is_11b
= false;
2355 const bool is_type_ep
= false;
2357 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
2358 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
,
2359 (rf
->channel
> 14 || conf_is_ht40(conf
)) ? 5 : 0);
2360 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
2362 /* Order of values on rf_channel entry: N, K, mod, R */
2363 rt2800_rfcsr_write(rt2x00dev
, 8, rf
->rf1
& 0xff);
2365 rt2800_rfcsr_read(rt2x00dev
, 9, &rfcsr
);
2366 rt2x00_set_field8(&rfcsr
, RFCSR9_K
, rf
->rf2
& 0xf);
2367 rt2x00_set_field8(&rfcsr
, RFCSR9_N
, (rf
->rf1
& 0x100) >> 8);
2368 rt2x00_set_field8(&rfcsr
, RFCSR9_MOD
, ((rf
->rf3
- 8) & 0x4) >> 2);
2369 rt2800_rfcsr_write(rt2x00dev
, 9, rfcsr
);
2371 rt2800_rfcsr_read(rt2x00dev
, 11, &rfcsr
);
2372 rt2x00_set_field8(&rfcsr
, RFCSR11_R
, rf
->rf4
- 1);
2373 rt2x00_set_field8(&rfcsr
, RFCSR11_MOD
, (rf
->rf3
- 8) & 0x3);
2374 rt2800_rfcsr_write(rt2x00dev
, 11, rfcsr
);
2376 if (rf
->channel
<= 14) {
2377 rt2800_rfcsr_write(rt2x00dev
, 10, 0x90);
2378 /* FIXME: RF11 owerwrite ? */
2379 rt2800_rfcsr_write(rt2x00dev
, 11, 0x4A);
2380 rt2800_rfcsr_write(rt2x00dev
, 12, 0x52);
2381 rt2800_rfcsr_write(rt2x00dev
, 13, 0x42);
2382 rt2800_rfcsr_write(rt2x00dev
, 22, 0x40);
2383 rt2800_rfcsr_write(rt2x00dev
, 24, 0x4A);
2384 rt2800_rfcsr_write(rt2x00dev
, 25, 0x80);
2385 rt2800_rfcsr_write(rt2x00dev
, 27, 0x42);
2386 rt2800_rfcsr_write(rt2x00dev
, 36, 0x80);
2387 rt2800_rfcsr_write(rt2x00dev
, 37, 0x08);
2388 rt2800_rfcsr_write(rt2x00dev
, 38, 0x89);
2389 rt2800_rfcsr_write(rt2x00dev
, 39, 0x1B);
2390 rt2800_rfcsr_write(rt2x00dev
, 40, 0x0D);
2391 rt2800_rfcsr_write(rt2x00dev
, 41, 0x9B);
2392 rt2800_rfcsr_write(rt2x00dev
, 42, 0xD5);
2393 rt2800_rfcsr_write(rt2x00dev
, 43, 0x72);
2394 rt2800_rfcsr_write(rt2x00dev
, 44, 0x0E);
2395 rt2800_rfcsr_write(rt2x00dev
, 45, 0xA2);
2396 rt2800_rfcsr_write(rt2x00dev
, 46, 0x6B);
2397 rt2800_rfcsr_write(rt2x00dev
, 48, 0x10);
2398 rt2800_rfcsr_write(rt2x00dev
, 51, 0x3E);
2399 rt2800_rfcsr_write(rt2x00dev
, 52, 0x48);
2400 rt2800_rfcsr_write(rt2x00dev
, 54, 0x38);
2401 rt2800_rfcsr_write(rt2x00dev
, 56, 0xA1);
2402 rt2800_rfcsr_write(rt2x00dev
, 57, 0x00);
2403 rt2800_rfcsr_write(rt2x00dev
, 58, 0x39);
2404 rt2800_rfcsr_write(rt2x00dev
, 60, 0x45);
2405 rt2800_rfcsr_write(rt2x00dev
, 61, 0x91);
2406 rt2800_rfcsr_write(rt2x00dev
, 62, 0x39);
2408 /* TODO RF27 <- tssi */
2410 rfcsr
= rf
->channel
<= 10 ? 0x07 : 0x06;
2411 rt2800_rfcsr_write(rt2x00dev
, 23, rfcsr
);
2412 rt2800_rfcsr_write(rt2x00dev
, 59, rfcsr
);
2416 rt2800_rfcsr_write(rt2x00dev
, 31, 0xF8);
2417 rt2800_rfcsr_write(rt2x00dev
, 32, 0xC0);
2419 rt2800_rfcsr_write(rt2x00dev
, 55, 0x06);
2421 rt2800_rfcsr_write(rt2x00dev
, 55, 0x47);
2425 rt2800_rfcsr_write(rt2x00dev
, 55, 0x03);
2427 rt2800_rfcsr_write(rt2x00dev
, 55, 0x43);
2430 power_bound
= POWER_BOUND
;
2433 rt2800_rfcsr_write(rt2x00dev
, 10, 0x97);
2434 /* FIMXE: RF11 overwrite */
2435 rt2800_rfcsr_write(rt2x00dev
, 11, 0x40);
2436 rt2800_rfcsr_write(rt2x00dev
, 25, 0xBF);
2437 rt2800_rfcsr_write(rt2x00dev
, 27, 0x42);
2438 rt2800_rfcsr_write(rt2x00dev
, 36, 0x00);
2439 rt2800_rfcsr_write(rt2x00dev
, 37, 0x04);
2440 rt2800_rfcsr_write(rt2x00dev
, 38, 0x85);
2441 rt2800_rfcsr_write(rt2x00dev
, 40, 0x42);
2442 rt2800_rfcsr_write(rt2x00dev
, 41, 0xBB);
2443 rt2800_rfcsr_write(rt2x00dev
, 42, 0xD7);
2444 rt2800_rfcsr_write(rt2x00dev
, 45, 0x41);
2445 rt2800_rfcsr_write(rt2x00dev
, 48, 0x00);
2446 rt2800_rfcsr_write(rt2x00dev
, 57, 0x77);
2447 rt2800_rfcsr_write(rt2x00dev
, 60, 0x05);
2448 rt2800_rfcsr_write(rt2x00dev
, 61, 0x01);
2450 /* TODO RF27 <- tssi */
2452 if (rf
->channel
>= 36 && rf
->channel
<= 64) {
2454 rt2800_rfcsr_write(rt2x00dev
, 12, 0x2E);
2455 rt2800_rfcsr_write(rt2x00dev
, 13, 0x22);
2456 rt2800_rfcsr_write(rt2x00dev
, 22, 0x60);
2457 rt2800_rfcsr_write(rt2x00dev
, 23, 0x7F);
2458 if (rf
->channel
<= 50)
2459 rt2800_rfcsr_write(rt2x00dev
, 24, 0x09);
2460 else if (rf
->channel
>= 52)
2461 rt2800_rfcsr_write(rt2x00dev
, 24, 0x07);
2462 rt2800_rfcsr_write(rt2x00dev
, 39, 0x1C);
2463 rt2800_rfcsr_write(rt2x00dev
, 43, 0x5B);
2464 rt2800_rfcsr_write(rt2x00dev
, 44, 0X40);
2465 rt2800_rfcsr_write(rt2x00dev
, 46, 0X00);
2466 rt2800_rfcsr_write(rt2x00dev
, 51, 0xFE);
2467 rt2800_rfcsr_write(rt2x00dev
, 52, 0x0C);
2468 rt2800_rfcsr_write(rt2x00dev
, 54, 0xF8);
2469 if (rf
->channel
<= 50) {
2470 rt2800_rfcsr_write(rt2x00dev
, 55, 0x06),
2471 rt2800_rfcsr_write(rt2x00dev
, 56, 0xD3);
2472 } else if (rf
->channel
>= 52) {
2473 rt2800_rfcsr_write(rt2x00dev
, 55, 0x04);
2474 rt2800_rfcsr_write(rt2x00dev
, 56, 0xBB);
2477 rt2800_rfcsr_write(rt2x00dev
, 58, 0x15);
2478 rt2800_rfcsr_write(rt2x00dev
, 59, 0x7F);
2479 rt2800_rfcsr_write(rt2x00dev
, 62, 0x15);
2481 } else if (rf
->channel
>= 100 && rf
->channel
<= 165) {
2483 rt2800_rfcsr_write(rt2x00dev
, 12, 0x0E);
2484 rt2800_rfcsr_write(rt2x00dev
, 13, 0x42);
2485 rt2800_rfcsr_write(rt2x00dev
, 22, 0x40);
2486 if (rf
->channel
<= 153) {
2487 rt2800_rfcsr_write(rt2x00dev
, 23, 0x3C);
2488 rt2800_rfcsr_write(rt2x00dev
, 24, 0x06);
2489 } else if (rf
->channel
>= 155) {
2490 rt2800_rfcsr_write(rt2x00dev
, 23, 0x38);
2491 rt2800_rfcsr_write(rt2x00dev
, 24, 0x05);
2493 if (rf
->channel
<= 138) {
2494 rt2800_rfcsr_write(rt2x00dev
, 39, 0x1A);
2495 rt2800_rfcsr_write(rt2x00dev
, 43, 0x3B);
2496 rt2800_rfcsr_write(rt2x00dev
, 44, 0x20);
2497 rt2800_rfcsr_write(rt2x00dev
, 46, 0x18);
2498 } else if (rf
->channel
>= 140) {
2499 rt2800_rfcsr_write(rt2x00dev
, 39, 0x18);
2500 rt2800_rfcsr_write(rt2x00dev
, 43, 0x1B);
2501 rt2800_rfcsr_write(rt2x00dev
, 44, 0x10);
2502 rt2800_rfcsr_write(rt2x00dev
, 46, 0X08);
2504 if (rf
->channel
<= 124)
2505 rt2800_rfcsr_write(rt2x00dev
, 51, 0xFC);
2506 else if (rf
->channel
>= 126)
2507 rt2800_rfcsr_write(rt2x00dev
, 51, 0xEC);
2508 if (rf
->channel
<= 138)
2509 rt2800_rfcsr_write(rt2x00dev
, 52, 0x06);
2510 else if (rf
->channel
>= 140)
2511 rt2800_rfcsr_write(rt2x00dev
, 52, 0x06);
2512 rt2800_rfcsr_write(rt2x00dev
, 54, 0xEB);
2513 if (rf
->channel
<= 138)
2514 rt2800_rfcsr_write(rt2x00dev
, 55, 0x01);
2515 else if (rf
->channel
>= 140)
2516 rt2800_rfcsr_write(rt2x00dev
, 55, 0x00);
2517 if (rf
->channel
<= 128)
2518 rt2800_rfcsr_write(rt2x00dev
, 56, 0xBB);
2519 else if (rf
->channel
>= 130)
2520 rt2800_rfcsr_write(rt2x00dev
, 56, 0xAB);
2521 if (rf
->channel
<= 116)
2522 rt2800_rfcsr_write(rt2x00dev
, 58, 0x1D);
2523 else if (rf
->channel
>= 118)
2524 rt2800_rfcsr_write(rt2x00dev
, 58, 0x15);
2525 if (rf
->channel
<= 138)
2526 rt2800_rfcsr_write(rt2x00dev
, 59, 0x3F);
2527 else if (rf
->channel
>= 140)
2528 rt2800_rfcsr_write(rt2x00dev
, 59, 0x7C);
2529 if (rf
->channel
<= 116)
2530 rt2800_rfcsr_write(rt2x00dev
, 62, 0x1D);
2531 else if (rf
->channel
>= 118)
2532 rt2800_rfcsr_write(rt2x00dev
, 62, 0x15);
2535 power_bound
= POWER_BOUND_5G
;
2539 rt2800_rfcsr_read(rt2x00dev
, 49, &rfcsr
);
2540 if (info
->default_power1
> power_bound
)
2541 rt2x00_set_field8(&rfcsr
, RFCSR49_TX
, power_bound
);
2543 rt2x00_set_field8(&rfcsr
, RFCSR49_TX
, info
->default_power1
);
2545 rt2x00_set_field8(&rfcsr
, RFCSR49_EP
, ep_reg
);
2546 rt2800_rfcsr_write(rt2x00dev
, 49, rfcsr
);
2548 rt2800_rfcsr_read(rt2x00dev
, 50, &rfcsr
);
2549 if (info
->default_power2
> power_bound
)
2550 rt2x00_set_field8(&rfcsr
, RFCSR50_TX
, power_bound
);
2552 rt2x00_set_field8(&rfcsr
, RFCSR50_TX
, info
->default_power2
);
2554 rt2x00_set_field8(&rfcsr
, RFCSR50_EP
, ep_reg
);
2555 rt2800_rfcsr_write(rt2x00dev
, 50, rfcsr
);
2557 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
2558 rt2x00_set_field8(&rfcsr
, RFCSR1_RF_BLOCK_EN
, 1);
2559 rt2x00_set_field8(&rfcsr
, RFCSR1_PLL_PD
, 1);
2561 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
,
2562 rt2x00dev
->default_ant
.tx_chain_num
>= 1);
2563 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
,
2564 rt2x00dev
->default_ant
.tx_chain_num
== 2);
2565 rt2x00_set_field8(&rfcsr
, RFCSR1_TX2_PD
, 0);
2567 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
,
2568 rt2x00dev
->default_ant
.rx_chain_num
>= 1);
2569 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
,
2570 rt2x00dev
->default_ant
.rx_chain_num
== 2);
2571 rt2x00_set_field8(&rfcsr
, RFCSR1_RX2_PD
, 0);
2573 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
2574 rt2800_rfcsr_write(rt2x00dev
, 6, 0xe4);
2576 if (conf_is_ht40(conf
))
2577 rt2800_rfcsr_write(rt2x00dev
, 30, 0x16);
2579 rt2800_rfcsr_write(rt2x00dev
, 30, 0x10);
2582 rt2800_rfcsr_write(rt2x00dev
, 31, 0x80);
2583 rt2800_rfcsr_write(rt2x00dev
, 32, 0x80);
2586 /* TODO proper frequency adjustment */
2587 rt2800_adjust_freq_offset(rt2x00dev
);
2589 /* TODO merge with others */
2590 rt2800_rfcsr_read(rt2x00dev
, 3, &rfcsr
);
2591 rt2x00_set_field8(&rfcsr
, RFCSR3_VCOCAL_EN
, 1);
2592 rt2800_rfcsr_write(rt2x00dev
, 3, rfcsr
);
2595 rt2800_bbp_write(rt2x00dev
, 62, 0x37 - rt2x00dev
->lna_gain
);
2596 rt2800_bbp_write(rt2x00dev
, 63, 0x37 - rt2x00dev
->lna_gain
);
2597 rt2800_bbp_write(rt2x00dev
, 64, 0x37 - rt2x00dev
->lna_gain
);
2599 rt2800_bbp_write(rt2x00dev
, 79, (rf
->channel
<= 14) ? 0x1C : 0x18);
2600 rt2800_bbp_write(rt2x00dev
, 80, (rf
->channel
<= 14) ? 0x0E : 0x08);
2601 rt2800_bbp_write(rt2x00dev
, 81, (rf
->channel
<= 14) ? 0x3A : 0x38);
2602 rt2800_bbp_write(rt2x00dev
, 82, (rf
->channel
<= 14) ? 0x62 : 0x92);
2604 /* GLRT band configuration */
2605 rt2800_bbp_write(rt2x00dev
, 195, 128);
2606 rt2800_bbp_write(rt2x00dev
, 196, (rf
->channel
<= 14) ? 0xE0 : 0xF0);
2607 rt2800_bbp_write(rt2x00dev
, 195, 129);
2608 rt2800_bbp_write(rt2x00dev
, 196, (rf
->channel
<= 14) ? 0x1F : 0x1E);
2609 rt2800_bbp_write(rt2x00dev
, 195, 130);
2610 rt2800_bbp_write(rt2x00dev
, 196, (rf
->channel
<= 14) ? 0x38 : 0x28);
2611 rt2800_bbp_write(rt2x00dev
, 195, 131);
2612 rt2800_bbp_write(rt2x00dev
, 196, (rf
->channel
<= 14) ? 0x32 : 0x20);
2613 rt2800_bbp_write(rt2x00dev
, 195, 133);
2614 rt2800_bbp_write(rt2x00dev
, 196, (rf
->channel
<= 14) ? 0x28 : 0x7F);
2615 rt2800_bbp_write(rt2x00dev
, 195, 124);
2616 rt2800_bbp_write(rt2x00dev
, 196, (rf
->channel
<= 14) ? 0x19 : 0x7F);
2619 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev
*rt2x00dev
,
2620 const unsigned int word
,
2625 for (chain
= 0; chain
< rt2x00dev
->default_ant
.rx_chain_num
; chain
++) {
2626 rt2800_bbp_read(rt2x00dev
, 27, ®
);
2627 rt2x00_set_field8(®
, BBP27_RX_CHAIN_SEL
, chain
);
2628 rt2800_bbp_write(rt2x00dev
, 27, reg
);
2630 rt2800_bbp_write(rt2x00dev
, word
, value
);
2634 static void rt2800_iq_calibrate(struct rt2x00_dev
*rt2x00dev
, int channel
)
2639 rt2800_bbp_write(rt2x00dev
, 158, 0x2c);
2641 cal
= rt2x00_eeprom_byte(rt2x00dev
, EEPROM_IQ_GAIN_CAL_TX0_2G
);
2642 else if (channel
>= 36 && channel
<= 64)
2643 cal
= rt2x00_eeprom_byte(rt2x00dev
,
2644 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G
);
2645 else if (channel
>= 100 && channel
<= 138)
2646 cal
= rt2x00_eeprom_byte(rt2x00dev
,
2647 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G
);
2648 else if (channel
>= 140 && channel
<= 165)
2649 cal
= rt2x00_eeprom_byte(rt2x00dev
,
2650 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G
);
2653 rt2800_bbp_write(rt2x00dev
, 159, cal
);
2656 rt2800_bbp_write(rt2x00dev
, 158, 0x2d);
2658 cal
= rt2x00_eeprom_byte(rt2x00dev
, EEPROM_IQ_PHASE_CAL_TX0_2G
);
2659 else if (channel
>= 36 && channel
<= 64)
2660 cal
= rt2x00_eeprom_byte(rt2x00dev
,
2661 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G
);
2662 else if (channel
>= 100 && channel
<= 138)
2663 cal
= rt2x00_eeprom_byte(rt2x00dev
,
2664 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G
);
2665 else if (channel
>= 140 && channel
<= 165)
2666 cal
= rt2x00_eeprom_byte(rt2x00dev
,
2667 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G
);
2670 rt2800_bbp_write(rt2x00dev
, 159, cal
);
2673 rt2800_bbp_write(rt2x00dev
, 158, 0x4a);
2675 cal
= rt2x00_eeprom_byte(rt2x00dev
, EEPROM_IQ_GAIN_CAL_TX1_2G
);
2676 else if (channel
>= 36 && channel
<= 64)
2677 cal
= rt2x00_eeprom_byte(rt2x00dev
,
2678 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G
);
2679 else if (channel
>= 100 && channel
<= 138)
2680 cal
= rt2x00_eeprom_byte(rt2x00dev
,
2681 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G
);
2682 else if (channel
>= 140 && channel
<= 165)
2683 cal
= rt2x00_eeprom_byte(rt2x00dev
,
2684 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G
);
2687 rt2800_bbp_write(rt2x00dev
, 159, cal
);
2690 rt2800_bbp_write(rt2x00dev
, 158, 0x4b);
2692 cal
= rt2x00_eeprom_byte(rt2x00dev
, EEPROM_IQ_PHASE_CAL_TX1_2G
);
2693 else if (channel
>= 36 && channel
<= 64)
2694 cal
= rt2x00_eeprom_byte(rt2x00dev
,
2695 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G
);
2696 else if (channel
>= 100 && channel
<= 138)
2697 cal
= rt2x00_eeprom_byte(rt2x00dev
,
2698 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G
);
2699 else if (channel
>= 140 && channel
<= 165)
2700 cal
= rt2x00_eeprom_byte(rt2x00dev
,
2701 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G
);
2704 rt2800_bbp_write(rt2x00dev
, 159, cal
);
2706 /* FIXME: possible RX0, RX1 callibration ? */
2708 /* RF IQ compensation control */
2709 rt2800_bbp_write(rt2x00dev
, 158, 0x04);
2710 cal
= rt2x00_eeprom_byte(rt2x00dev
, EEPROM_RF_IQ_COMPENSATION_CONTROL
);
2711 rt2800_bbp_write(rt2x00dev
, 159, cal
!= 0xff ? cal
: 0);
2713 /* RF IQ imbalance compensation control */
2714 rt2800_bbp_write(rt2x00dev
, 158, 0x03);
2715 cal
= rt2x00_eeprom_byte(rt2x00dev
,
2716 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL
);
2717 rt2800_bbp_write(rt2x00dev
, 159, cal
!= 0xff ? cal
: 0);
2720 static void rt2800_config_channel(struct rt2x00_dev
*rt2x00dev
,
2721 struct ieee80211_conf
*conf
,
2722 struct rf_channel
*rf
,
2723 struct channel_info
*info
)
2726 unsigned int tx_pin
;
2729 if (rf
->channel
<= 14) {
2730 info
->default_power1
= TXPOWER_G_TO_DEV(info
->default_power1
);
2731 info
->default_power2
= TXPOWER_G_TO_DEV(info
->default_power2
);
2733 info
->default_power1
= TXPOWER_A_TO_DEV(info
->default_power1
);
2734 info
->default_power2
= TXPOWER_A_TO_DEV(info
->default_power2
);
2737 switch (rt2x00dev
->chip
.rf
) {
2743 rt2800_config_channel_rf3xxx(rt2x00dev
, conf
, rf
, info
);
2746 rt2800_config_channel_rf3052(rt2x00dev
, conf
, rf
, info
);
2749 rt2800_config_channel_rf3290(rt2x00dev
, conf
, rf
, info
);
2752 rt2800_config_channel_rf3322(rt2x00dev
, conf
, rf
, info
);
2759 rt2800_config_channel_rf53xx(rt2x00dev
, conf
, rf
, info
);
2762 rt2800_config_channel_rf55xx(rt2x00dev
, conf
, rf
, info
);
2765 rt2800_config_channel_rf2xxx(rt2x00dev
, conf
, rf
, info
);
2768 if (rt2x00_rf(rt2x00dev
, RF3290
) ||
2769 rt2x00_rf(rt2x00dev
, RF3322
) ||
2770 rt2x00_rf(rt2x00dev
, RF5360
) ||
2771 rt2x00_rf(rt2x00dev
, RF5370
) ||
2772 rt2x00_rf(rt2x00dev
, RF5372
) ||
2773 rt2x00_rf(rt2x00dev
, RF5390
) ||
2774 rt2x00_rf(rt2x00dev
, RF5392
)) {
2775 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
2776 rt2x00_set_field8(&rfcsr
, RFCSR30_TX_H20M
, 0);
2777 rt2x00_set_field8(&rfcsr
, RFCSR30_RX_H20M
, 0);
2778 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
2780 rt2800_rfcsr_read(rt2x00dev
, 3, &rfcsr
);
2781 rt2x00_set_field8(&rfcsr
, RFCSR3_VCOCAL_EN
, 1);
2782 rt2800_rfcsr_write(rt2x00dev
, 3, rfcsr
);
2786 * Change BBP settings
2788 if (rt2x00_rt(rt2x00dev
, RT3352
)) {
2789 rt2800_bbp_write(rt2x00dev
, 27, 0x0);
2790 rt2800_bbp_write(rt2x00dev
, 66, 0x26 + rt2x00dev
->lna_gain
);
2791 rt2800_bbp_write(rt2x00dev
, 27, 0x20);
2792 rt2800_bbp_write(rt2x00dev
, 66, 0x26 + rt2x00dev
->lna_gain
);
2794 rt2800_bbp_write(rt2x00dev
, 62, 0x37 - rt2x00dev
->lna_gain
);
2795 rt2800_bbp_write(rt2x00dev
, 63, 0x37 - rt2x00dev
->lna_gain
);
2796 rt2800_bbp_write(rt2x00dev
, 64, 0x37 - rt2x00dev
->lna_gain
);
2797 rt2800_bbp_write(rt2x00dev
, 86, 0);
2800 if (rf
->channel
<= 14) {
2801 if (!rt2x00_rt(rt2x00dev
, RT5390
) &&
2802 !rt2x00_rt(rt2x00dev
, RT5392
)) {
2803 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG
,
2804 &rt2x00dev
->cap_flags
)) {
2805 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
2806 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
2808 rt2800_bbp_write(rt2x00dev
, 82, 0x84);
2809 rt2800_bbp_write(rt2x00dev
, 75, 0x50);
2813 if (rt2x00_rt(rt2x00dev
, RT3572
))
2814 rt2800_bbp_write(rt2x00dev
, 82, 0x94);
2816 rt2800_bbp_write(rt2x00dev
, 82, 0xf2);
2818 if (test_bit(CAPABILITY_EXTERNAL_LNA_A
, &rt2x00dev
->cap_flags
))
2819 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
2821 rt2800_bbp_write(rt2x00dev
, 75, 0x50);
2824 rt2800_register_read(rt2x00dev
, TX_BAND_CFG
, ®
);
2825 rt2x00_set_field32(®
, TX_BAND_CFG_HT40_MINUS
, conf_is_ht40_minus(conf
));
2826 rt2x00_set_field32(®
, TX_BAND_CFG_A
, rf
->channel
> 14);
2827 rt2x00_set_field32(®
, TX_BAND_CFG_BG
, rf
->channel
<= 14);
2828 rt2800_register_write(rt2x00dev
, TX_BAND_CFG
, reg
);
2830 if (rt2x00_rt(rt2x00dev
, RT3572
))
2831 rt2800_rfcsr_write(rt2x00dev
, 8, 0);
2835 switch (rt2x00dev
->default_ant
.tx_chain_num
) {
2837 /* Turn on tertiary PAs */
2838 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A2_EN
,
2840 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G2_EN
,
2844 /* Turn on secondary PAs */
2845 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A1_EN
,
2847 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G1_EN
,
2851 /* Turn on primary PAs */
2852 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A0_EN
,
2854 if (test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
))
2855 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G0_EN
, 1);
2857 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G0_EN
,
2862 switch (rt2x00dev
->default_ant
.rx_chain_num
) {
2864 /* Turn on tertiary LNAs */
2865 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_A2_EN
, 1);
2866 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_G2_EN
, 1);
2869 /* Turn on secondary LNAs */
2870 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_A1_EN
, 1);
2871 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_G1_EN
, 1);
2874 /* Turn on primary LNAs */
2875 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_A0_EN
, 1);
2876 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_G0_EN
, 1);
2880 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_RFTR_EN
, 1);
2881 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_TRSW_EN
, 1);
2883 rt2800_register_write(rt2x00dev
, TX_PIN_CFG
, tx_pin
);
2885 if (rt2x00_rt(rt2x00dev
, RT3572
))
2886 rt2800_rfcsr_write(rt2x00dev
, 8, 0x80);
2888 if (rt2x00_rt(rt2x00dev
, RT5592
)) {
2889 rt2800_bbp_write(rt2x00dev
, 195, 141);
2890 rt2800_bbp_write(rt2x00dev
, 196, conf_is_ht40(conf
) ? 0x10 : 0x1a);
2893 reg
= (rf
->channel
<= 14 ? 0x1c : 0x24) + 2 * rt2x00dev
->lna_gain
;
2894 rt2800_bbp_write_with_rx_chain(rt2x00dev
, 66, reg
);
2896 rt2800_iq_calibrate(rt2x00dev
, rf
->channel
);
2899 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
2900 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 2 * conf_is_ht40(conf
));
2901 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
2903 rt2800_bbp_read(rt2x00dev
, 3, &bbp
);
2904 rt2x00_set_field8(&bbp
, BBP3_HT40_MINUS
, conf_is_ht40_minus(conf
));
2905 rt2800_bbp_write(rt2x00dev
, 3, bbp
);
2907 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
)) {
2908 if (conf_is_ht40(conf
)) {
2909 rt2800_bbp_write(rt2x00dev
, 69, 0x1a);
2910 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
2911 rt2800_bbp_write(rt2x00dev
, 73, 0x16);
2913 rt2800_bbp_write(rt2x00dev
, 69, 0x16);
2914 rt2800_bbp_write(rt2x00dev
, 70, 0x08);
2915 rt2800_bbp_write(rt2x00dev
, 73, 0x11);
2922 * Clear channel statistic counters
2924 rt2800_register_read(rt2x00dev
, CH_IDLE_STA
, ®
);
2925 rt2800_register_read(rt2x00dev
, CH_BUSY_STA
, ®
);
2926 rt2800_register_read(rt2x00dev
, CH_BUSY_STA_SEC
, ®
);
2931 if (rt2x00_rt(rt2x00dev
, RT3352
)) {
2932 rt2800_bbp_read(rt2x00dev
, 49, &bbp
);
2933 rt2x00_set_field8(&bbp
, BBP49_UPDATE_FLAG
, 0);
2934 rt2800_bbp_write(rt2x00dev
, 49, bbp
);
2938 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev
*rt2x00dev
)
2947 * Read TSSI boundaries for temperature compensation from
2950 * Array idx 0 1 2 3 4 5 6 7 8
2951 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
2952 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
2954 if (rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
) {
2955 rt2800_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG1
, &eeprom
);
2956 tssi_bounds
[0] = rt2x00_get_field16(eeprom
,
2957 EEPROM_TSSI_BOUND_BG1_MINUS4
);
2958 tssi_bounds
[1] = rt2x00_get_field16(eeprom
,
2959 EEPROM_TSSI_BOUND_BG1_MINUS3
);
2961 rt2800_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG2
, &eeprom
);
2962 tssi_bounds
[2] = rt2x00_get_field16(eeprom
,
2963 EEPROM_TSSI_BOUND_BG2_MINUS2
);
2964 tssi_bounds
[3] = rt2x00_get_field16(eeprom
,
2965 EEPROM_TSSI_BOUND_BG2_MINUS1
);
2967 rt2800_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG3
, &eeprom
);
2968 tssi_bounds
[4] = rt2x00_get_field16(eeprom
,
2969 EEPROM_TSSI_BOUND_BG3_REF
);
2970 tssi_bounds
[5] = rt2x00_get_field16(eeprom
,
2971 EEPROM_TSSI_BOUND_BG3_PLUS1
);
2973 rt2800_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG4
, &eeprom
);
2974 tssi_bounds
[6] = rt2x00_get_field16(eeprom
,
2975 EEPROM_TSSI_BOUND_BG4_PLUS2
);
2976 tssi_bounds
[7] = rt2x00_get_field16(eeprom
,
2977 EEPROM_TSSI_BOUND_BG4_PLUS3
);
2979 rt2800_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_BG5
, &eeprom
);
2980 tssi_bounds
[8] = rt2x00_get_field16(eeprom
,
2981 EEPROM_TSSI_BOUND_BG5_PLUS4
);
2983 step
= rt2x00_get_field16(eeprom
,
2984 EEPROM_TSSI_BOUND_BG5_AGC_STEP
);
2986 rt2800_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A1
, &eeprom
);
2987 tssi_bounds
[0] = rt2x00_get_field16(eeprom
,
2988 EEPROM_TSSI_BOUND_A1_MINUS4
);
2989 tssi_bounds
[1] = rt2x00_get_field16(eeprom
,
2990 EEPROM_TSSI_BOUND_A1_MINUS3
);
2992 rt2800_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A2
, &eeprom
);
2993 tssi_bounds
[2] = rt2x00_get_field16(eeprom
,
2994 EEPROM_TSSI_BOUND_A2_MINUS2
);
2995 tssi_bounds
[3] = rt2x00_get_field16(eeprom
,
2996 EEPROM_TSSI_BOUND_A2_MINUS1
);
2998 rt2800_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A3
, &eeprom
);
2999 tssi_bounds
[4] = rt2x00_get_field16(eeprom
,
3000 EEPROM_TSSI_BOUND_A3_REF
);
3001 tssi_bounds
[5] = rt2x00_get_field16(eeprom
,
3002 EEPROM_TSSI_BOUND_A3_PLUS1
);
3004 rt2800_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A4
, &eeprom
);
3005 tssi_bounds
[6] = rt2x00_get_field16(eeprom
,
3006 EEPROM_TSSI_BOUND_A4_PLUS2
);
3007 tssi_bounds
[7] = rt2x00_get_field16(eeprom
,
3008 EEPROM_TSSI_BOUND_A4_PLUS3
);
3010 rt2800_eeprom_read(rt2x00dev
, EEPROM_TSSI_BOUND_A5
, &eeprom
);
3011 tssi_bounds
[8] = rt2x00_get_field16(eeprom
,
3012 EEPROM_TSSI_BOUND_A5_PLUS4
);
3014 step
= rt2x00_get_field16(eeprom
,
3015 EEPROM_TSSI_BOUND_A5_AGC_STEP
);
3019 * Check if temperature compensation is supported.
3021 if (tssi_bounds
[4] == 0xff || step
== 0xff)
3025 * Read current TSSI (BBP 49).
3027 rt2800_bbp_read(rt2x00dev
, 49, ¤t_tssi
);
3030 * Compare TSSI value (BBP49) with the compensation boundaries
3031 * from the EEPROM and increase or decrease tx power.
3033 for (i
= 0; i
<= 3; i
++) {
3034 if (current_tssi
> tssi_bounds
[i
])
3039 for (i
= 8; i
>= 5; i
--) {
3040 if (current_tssi
< tssi_bounds
[i
])
3045 return (i
- 4) * step
;
3048 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev
*rt2x00dev
,
3049 enum ieee80211_band band
)
3056 rt2800_eeprom_read(rt2x00dev
, EEPROM_TXPOWER_DELTA
, &eeprom
);
3059 * HT40 compensation not required.
3061 if (eeprom
== 0xffff ||
3062 !test_bit(CONFIG_CHANNEL_HT40
, &rt2x00dev
->flags
))
3065 if (band
== IEEE80211_BAND_2GHZ
) {
3066 comp_en
= rt2x00_get_field16(eeprom
,
3067 EEPROM_TXPOWER_DELTA_ENABLE_2G
);
3069 comp_type
= rt2x00_get_field16(eeprom
,
3070 EEPROM_TXPOWER_DELTA_TYPE_2G
);
3071 comp_value
= rt2x00_get_field16(eeprom
,
3072 EEPROM_TXPOWER_DELTA_VALUE_2G
);
3074 comp_value
= -comp_value
;
3077 comp_en
= rt2x00_get_field16(eeprom
,
3078 EEPROM_TXPOWER_DELTA_ENABLE_5G
);
3080 comp_type
= rt2x00_get_field16(eeprom
,
3081 EEPROM_TXPOWER_DELTA_TYPE_5G
);
3082 comp_value
= rt2x00_get_field16(eeprom
,
3083 EEPROM_TXPOWER_DELTA_VALUE_5G
);
3085 comp_value
= -comp_value
;
3092 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev
*rt2x00dev
,
3093 int power_level
, int max_power
)
3097 if (test_bit(CAPABILITY_POWER_LIMIT
, &rt2x00dev
->cap_flags
))
3101 * XXX: We don't know the maximum transmit power of our hardware since
3102 * the EEPROM doesn't expose it. We only know that we are calibrated
3105 * Hence, we assume the regulatory limit that cfg80211 calulated for
3106 * the current channel is our maximum and if we are requested to lower
3107 * the value we just reduce our tx power accordingly.
3109 delta
= power_level
- max_power
;
3110 return min(delta
, 0);
3113 static u8
rt2800_compensate_txpower(struct rt2x00_dev
*rt2x00dev
, int is_rate_b
,
3114 enum ieee80211_band band
, int power_level
,
3115 u8 txpower
, int delta
)
3120 u8 eirp_txpower_criterion
;
3123 if (test_bit(CAPABILITY_POWER_LIMIT
, &rt2x00dev
->cap_flags
)) {
3125 * Check if eirp txpower exceed txpower_limit.
3126 * We use OFDM 6M as criterion and its eirp txpower
3127 * is stored at EEPROM_EIRP_MAX_TX_POWER.
3128 * .11b data rate need add additional 4dbm
3129 * when calculating eirp txpower.
3131 rt2800_eeprom_read_from_array(rt2x00dev
, EEPROM_TXPOWER_BYRATE
,
3133 criterion
= rt2x00_get_field16(eeprom
,
3134 EEPROM_TXPOWER_BYRATE_RATE0
);
3136 rt2800_eeprom_read(rt2x00dev
, EEPROM_EIRP_MAX_TX_POWER
,
3139 if (band
== IEEE80211_BAND_2GHZ
)
3140 eirp_txpower_criterion
= rt2x00_get_field16(eeprom
,
3141 EEPROM_EIRP_MAX_TX_POWER_2GHZ
);
3143 eirp_txpower_criterion
= rt2x00_get_field16(eeprom
,
3144 EEPROM_EIRP_MAX_TX_POWER_5GHZ
);
3146 eirp_txpower
= eirp_txpower_criterion
+ (txpower
- criterion
) +
3147 (is_rate_b
? 4 : 0) + delta
;
3149 reg_limit
= (eirp_txpower
> power_level
) ?
3150 (eirp_txpower
- power_level
) : 0;
3154 txpower
= max(0, txpower
+ delta
- reg_limit
);
3155 return min_t(u8
, txpower
, 0xc);
3159 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
3160 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
3161 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
3162 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
3163 * Reference per rate transmit power values are located in the EEPROM at
3164 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
3165 * current conditions (i.e. band, bandwidth, temperature, user settings).
3167 static void rt2800_config_txpower(struct rt2x00_dev
*rt2x00dev
,
3168 struct ieee80211_channel
*chan
,
3174 int i
, is_rate_b
, delta
, power_ctrl
;
3175 enum ieee80211_band band
= chan
->band
;
3178 * Calculate HT40 compensation. For 40MHz we need to add or subtract
3179 * value read from EEPROM (different for 2GHz and for 5GHz).
3181 delta
= rt2800_get_txpower_bw_comp(rt2x00dev
, band
);
3184 * Calculate temperature compensation. Depends on measurement of current
3185 * TSSI (Transmitter Signal Strength Indication) we know TX power (due
3186 * to temperature or maybe other factors) is smaller or bigger than
3187 * expected. We adjust it, based on TSSI reference and boundaries values
3188 * provided in EEPROM.
3190 delta
+= rt2800_get_gain_calibration_delta(rt2x00dev
);
3193 * Decrease power according to user settings, on devices with unknown
3194 * maximum tx power. For other devices we take user power_level into
3195 * consideration on rt2800_compensate_txpower().
3197 delta
+= rt2800_get_txpower_reg_delta(rt2x00dev
, power_level
,
3201 * BBP_R1 controls TX power for all rates, it allow to set the following
3202 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
3204 * TODO: we do not use +6 dBm option to do not increase power beyond
3205 * regulatory limit, however this could be utilized for devices with
3206 * CAPABILITY_POWER_LIMIT.
3208 * TODO: add different temperature compensation code for RT3290 & RT5390
3209 * to allow to use BBP_R1 for those chips.
3211 if (!rt2x00_rt(rt2x00dev
, RT3290
) &&
3212 !rt2x00_rt(rt2x00dev
, RT5390
)) {
3213 rt2800_bbp_read(rt2x00dev
, 1, &r1
);
3217 } else if (delta
<= -6) {
3223 rt2x00_set_field8(&r1
, BBP1_TX_POWER_CTRL
, power_ctrl
);
3224 rt2800_bbp_write(rt2x00dev
, 1, r1
);
3227 offset
= TX_PWR_CFG_0
;
3229 for (i
= 0; i
< EEPROM_TXPOWER_BYRATE_SIZE
; i
+= 2) {
3230 /* just to be safe */
3231 if (offset
> TX_PWR_CFG_4
)
3234 rt2800_register_read(rt2x00dev
, offset
, ®
);
3236 /* read the next four txpower values */
3237 rt2800_eeprom_read_from_array(rt2x00dev
, EEPROM_TXPOWER_BYRATE
,
3240 is_rate_b
= i
? 0 : 1;
3242 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
3243 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
3244 * TX_PWR_CFG_4: unknown
3246 txpower
= rt2x00_get_field16(eeprom
,
3247 EEPROM_TXPOWER_BYRATE_RATE0
);
3248 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
3249 power_level
, txpower
, delta
);
3250 rt2x00_set_field32(®
, TX_PWR_CFG_RATE0
, txpower
);
3253 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
3254 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
3255 * TX_PWR_CFG_4: unknown
3257 txpower
= rt2x00_get_field16(eeprom
,
3258 EEPROM_TXPOWER_BYRATE_RATE1
);
3259 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
3260 power_level
, txpower
, delta
);
3261 rt2x00_set_field32(®
, TX_PWR_CFG_RATE1
, txpower
);
3264 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
3265 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
3266 * TX_PWR_CFG_4: unknown
3268 txpower
= rt2x00_get_field16(eeprom
,
3269 EEPROM_TXPOWER_BYRATE_RATE2
);
3270 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
3271 power_level
, txpower
, delta
);
3272 rt2x00_set_field32(®
, TX_PWR_CFG_RATE2
, txpower
);
3275 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
3276 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
3277 * TX_PWR_CFG_4: unknown
3279 txpower
= rt2x00_get_field16(eeprom
,
3280 EEPROM_TXPOWER_BYRATE_RATE3
);
3281 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
3282 power_level
, txpower
, delta
);
3283 rt2x00_set_field32(®
, TX_PWR_CFG_RATE3
, txpower
);
3285 /* read the next four txpower values */
3286 rt2800_eeprom_read_from_array(rt2x00dev
, EEPROM_TXPOWER_BYRATE
,
3291 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
3292 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
3293 * TX_PWR_CFG_4: unknown
3295 txpower
= rt2x00_get_field16(eeprom
,
3296 EEPROM_TXPOWER_BYRATE_RATE0
);
3297 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
3298 power_level
, txpower
, delta
);
3299 rt2x00_set_field32(®
, TX_PWR_CFG_RATE4
, txpower
);
3302 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
3303 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
3304 * TX_PWR_CFG_4: unknown
3306 txpower
= rt2x00_get_field16(eeprom
,
3307 EEPROM_TXPOWER_BYRATE_RATE1
);
3308 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
3309 power_level
, txpower
, delta
);
3310 rt2x00_set_field32(®
, TX_PWR_CFG_RATE5
, txpower
);
3313 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
3314 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
3315 * TX_PWR_CFG_4: unknown
3317 txpower
= rt2x00_get_field16(eeprom
,
3318 EEPROM_TXPOWER_BYRATE_RATE2
);
3319 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
3320 power_level
, txpower
, delta
);
3321 rt2x00_set_field32(®
, TX_PWR_CFG_RATE6
, txpower
);
3324 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
3325 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
3326 * TX_PWR_CFG_4: unknown
3328 txpower
= rt2x00_get_field16(eeprom
,
3329 EEPROM_TXPOWER_BYRATE_RATE3
);
3330 txpower
= rt2800_compensate_txpower(rt2x00dev
, is_rate_b
, band
,
3331 power_level
, txpower
, delta
);
3332 rt2x00_set_field32(®
, TX_PWR_CFG_RATE7
, txpower
);
3334 rt2800_register_write(rt2x00dev
, offset
, reg
);
3336 /* next TX_PWR_CFG register */
3341 void rt2800_gain_calibration(struct rt2x00_dev
*rt2x00dev
)
3343 rt2800_config_txpower(rt2x00dev
, rt2x00dev
->hw
->conf
.chandef
.chan
,
3344 rt2x00dev
->tx_power
);
3346 EXPORT_SYMBOL_GPL(rt2800_gain_calibration
);
3348 void rt2800_vco_calibration(struct rt2x00_dev
*rt2x00dev
)
3354 * A voltage-controlled oscillator(VCO) is an electronic oscillator
3355 * designed to be controlled in oscillation frequency by a voltage
3356 * input. Maybe the temperature will affect the frequency of
3357 * oscillation to be shifted. The VCO calibration will be called
3358 * periodically to adjust the frequency to be precision.
3361 rt2800_register_read(rt2x00dev
, TX_PIN_CFG
, &tx_pin
);
3362 tx_pin
&= TX_PIN_CFG_PA_PE_DISABLE
;
3363 rt2800_register_write(rt2x00dev
, TX_PIN_CFG
, tx_pin
);
3365 switch (rt2x00dev
->chip
.rf
) {
3372 rt2800_rfcsr_read(rt2x00dev
, 7, &rfcsr
);
3373 rt2x00_set_field8(&rfcsr
, RFCSR7_RF_TUNING
, 1);
3374 rt2800_rfcsr_write(rt2x00dev
, 7, rfcsr
);
3382 rt2800_rfcsr_read(rt2x00dev
, 3, &rfcsr
);
3383 rt2x00_set_field8(&rfcsr
, RFCSR3_VCOCAL_EN
, 1);
3384 rt2800_rfcsr_write(rt2x00dev
, 3, rfcsr
);
3392 rt2800_register_read(rt2x00dev
, TX_PIN_CFG
, &tx_pin
);
3393 if (rt2x00dev
->rf_channel
<= 14) {
3394 switch (rt2x00dev
->default_ant
.tx_chain_num
) {
3396 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G2_EN
, 1);
3399 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G1_EN
, 1);
3403 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G0_EN
, 1);
3407 switch (rt2x00dev
->default_ant
.tx_chain_num
) {
3409 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A2_EN
, 1);
3412 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A1_EN
, 1);
3416 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A0_EN
, 1);
3420 rt2800_register_write(rt2x00dev
, TX_PIN_CFG
, tx_pin
);
3423 EXPORT_SYMBOL_GPL(rt2800_vco_calibration
);
3425 static void rt2800_config_retry_limit(struct rt2x00_dev
*rt2x00dev
,
3426 struct rt2x00lib_conf
*libconf
)
3430 rt2800_register_read(rt2x00dev
, TX_RTY_CFG
, ®
);
3431 rt2x00_set_field32(®
, TX_RTY_CFG_SHORT_RTY_LIMIT
,
3432 libconf
->conf
->short_frame_max_tx_count
);
3433 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_LIMIT
,
3434 libconf
->conf
->long_frame_max_tx_count
);
3435 rt2800_register_write(rt2x00dev
, TX_RTY_CFG
, reg
);
3438 static void rt2800_config_ps(struct rt2x00_dev
*rt2x00dev
,
3439 struct rt2x00lib_conf
*libconf
)
3441 enum dev_state state
=
3442 (libconf
->conf
->flags
& IEEE80211_CONF_PS
) ?
3443 STATE_SLEEP
: STATE_AWAKE
;
3446 if (state
== STATE_SLEEP
) {
3447 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, 0);
3449 rt2800_register_read(rt2x00dev
, AUTOWAKEUP_CFG
, ®
);
3450 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTO_LEAD_TIME
, 5);
3451 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE
,
3452 libconf
->conf
->listen_interval
- 1);
3453 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTOWAKE
, 1);
3454 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, reg
);
3456 rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, state
);
3458 rt2800_register_read(rt2x00dev
, AUTOWAKEUP_CFG
, ®
);
3459 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTO_LEAD_TIME
, 0);
3460 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE
, 0);
3461 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTOWAKE
, 0);
3462 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, reg
);
3464 rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, state
);
3468 void rt2800_config(struct rt2x00_dev
*rt2x00dev
,
3469 struct rt2x00lib_conf
*libconf
,
3470 const unsigned int flags
)
3472 /* Always recalculate LNA gain before changing configuration */
3473 rt2800_config_lna_gain(rt2x00dev
, libconf
);
3475 if (flags
& IEEE80211_CONF_CHANGE_CHANNEL
) {
3476 rt2800_config_channel(rt2x00dev
, libconf
->conf
,
3477 &libconf
->rf
, &libconf
->channel
);
3478 rt2800_config_txpower(rt2x00dev
, libconf
->conf
->chandef
.chan
,
3479 libconf
->conf
->power_level
);
3481 if (flags
& IEEE80211_CONF_CHANGE_POWER
)
3482 rt2800_config_txpower(rt2x00dev
, libconf
->conf
->chandef
.chan
,
3483 libconf
->conf
->power_level
);
3484 if (flags
& IEEE80211_CONF_CHANGE_RETRY_LIMITS
)
3485 rt2800_config_retry_limit(rt2x00dev
, libconf
);
3486 if (flags
& IEEE80211_CONF_CHANGE_PS
)
3487 rt2800_config_ps(rt2x00dev
, libconf
);
3489 EXPORT_SYMBOL_GPL(rt2800_config
);
3494 void rt2800_link_stats(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
)
3499 * Update FCS error count from register.
3501 rt2800_register_read(rt2x00dev
, RX_STA_CNT0
, ®
);
3502 qual
->rx_failed
= rt2x00_get_field32(reg
, RX_STA_CNT0_CRC_ERR
);
3504 EXPORT_SYMBOL_GPL(rt2800_link_stats
);
3506 static u8
rt2800_get_default_vgc(struct rt2x00_dev
*rt2x00dev
)
3510 if (rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
) {
3511 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
3512 rt2x00_rt(rt2x00dev
, RT3071
) ||
3513 rt2x00_rt(rt2x00dev
, RT3090
) ||
3514 rt2x00_rt(rt2x00dev
, RT3290
) ||
3515 rt2x00_rt(rt2x00dev
, RT3390
) ||
3516 rt2x00_rt(rt2x00dev
, RT3572
) ||
3517 rt2x00_rt(rt2x00dev
, RT5390
) ||
3518 rt2x00_rt(rt2x00dev
, RT5392
) ||
3519 rt2x00_rt(rt2x00dev
, RT5592
))
3520 vgc
= 0x1c + (2 * rt2x00dev
->lna_gain
);
3522 vgc
= 0x2e + rt2x00dev
->lna_gain
;
3523 } else { /* 5GHZ band */
3524 if (rt2x00_rt(rt2x00dev
, RT3572
))
3525 vgc
= 0x22 + (rt2x00dev
->lna_gain
* 5) / 3;
3526 else if (rt2x00_rt(rt2x00dev
, RT5592
))
3527 vgc
= 0x24 + (2 * rt2x00dev
->lna_gain
);
3529 if (!test_bit(CONFIG_CHANNEL_HT40
, &rt2x00dev
->flags
))
3530 vgc
= 0x32 + (rt2x00dev
->lna_gain
* 5) / 3;
3532 vgc
= 0x3a + (rt2x00dev
->lna_gain
* 5) / 3;
3539 static inline void rt2800_set_vgc(struct rt2x00_dev
*rt2x00dev
,
3540 struct link_qual
*qual
, u8 vgc_level
)
3542 if (qual
->vgc_level
!= vgc_level
) {
3543 if (rt2x00_rt(rt2x00dev
, RT5592
)) {
3544 rt2800_bbp_write(rt2x00dev
, 83, qual
->rssi
> -65 ? 0x4a : 0x7a);
3545 rt2800_bbp_write_with_rx_chain(rt2x00dev
, 66, vgc_level
);
3547 rt2800_bbp_write(rt2x00dev
, 66, vgc_level
);
3548 qual
->vgc_level
= vgc_level
;
3549 qual
->vgc_level_reg
= vgc_level
;
3553 void rt2800_reset_tuner(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
)
3555 rt2800_set_vgc(rt2x00dev
, qual
, rt2800_get_default_vgc(rt2x00dev
));
3557 EXPORT_SYMBOL_GPL(rt2800_reset_tuner
);
3559 void rt2800_link_tuner(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
,
3564 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
))
3567 * When RSSI is better then -80 increase VGC level with 0x10, except
3571 vgc
= rt2800_get_default_vgc(rt2x00dev
);
3573 if (rt2x00_rt(rt2x00dev
, RT5592
) && qual
->rssi
> -65)
3575 else if (qual
->rssi
> -80)
3578 rt2800_set_vgc(rt2x00dev
, qual
, vgc
);
3580 EXPORT_SYMBOL_GPL(rt2800_link_tuner
);
3583 * Initialization functions.
3585 static int rt2800_init_registers(struct rt2x00_dev
*rt2x00dev
)
3592 rt2800_disable_wpdma(rt2x00dev
);
3594 ret
= rt2800_drv_init_registers(rt2x00dev
);
3598 rt2800_register_read(rt2x00dev
, BCN_OFFSET0
, ®
);
3599 rt2x00_set_field32(®
, BCN_OFFSET0_BCN0
, 0xe0); /* 0x3800 */
3600 rt2x00_set_field32(®
, BCN_OFFSET0_BCN1
, 0xe8); /* 0x3a00 */
3601 rt2x00_set_field32(®
, BCN_OFFSET0_BCN2
, 0xf0); /* 0x3c00 */
3602 rt2x00_set_field32(®
, BCN_OFFSET0_BCN3
, 0xf8); /* 0x3e00 */
3603 rt2800_register_write(rt2x00dev
, BCN_OFFSET0
, reg
);
3605 rt2800_register_read(rt2x00dev
, BCN_OFFSET1
, ®
);
3606 rt2x00_set_field32(®
, BCN_OFFSET1_BCN4
, 0xc8); /* 0x3200 */
3607 rt2x00_set_field32(®
, BCN_OFFSET1_BCN5
, 0xd0); /* 0x3400 */
3608 rt2x00_set_field32(®
, BCN_OFFSET1_BCN6
, 0x77); /* 0x1dc0 */
3609 rt2x00_set_field32(®
, BCN_OFFSET1_BCN7
, 0x6f); /* 0x1bc0 */
3610 rt2800_register_write(rt2x00dev
, BCN_OFFSET1
, reg
);
3612 rt2800_register_write(rt2x00dev
, LEGACY_BASIC_RATE
, 0x0000013f);
3613 rt2800_register_write(rt2x00dev
, HT_BASIC_RATE
, 0x00008003);
3615 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, 0x00000000);
3617 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
3618 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_INTERVAL
, 1600);
3619 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_TICKING
, 0);
3620 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_SYNC
, 0);
3621 rt2x00_set_field32(®
, BCN_TIME_CFG_TBTT_ENABLE
, 0);
3622 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
3623 rt2x00_set_field32(®
, BCN_TIME_CFG_TX_TIME_COMPENSATE
, 0);
3624 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
3626 rt2800_config_filter(rt2x00dev
, FIF_ALLMULTI
);
3628 rt2800_register_read(rt2x00dev
, BKOFF_SLOT_CFG
, ®
);
3629 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_SLOT_TIME
, 9);
3630 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_CC_DELAY_TIME
, 2);
3631 rt2800_register_write(rt2x00dev
, BKOFF_SLOT_CFG
, reg
);
3633 if (rt2x00_rt(rt2x00dev
, RT3290
)) {
3634 rt2800_register_read(rt2x00dev
, WLAN_FUN_CTRL
, ®
);
3635 if (rt2x00_get_field32(reg
, WLAN_EN
) == 1) {
3636 rt2x00_set_field32(®
, PCIE_APP0_CLK_REQ
, 1);
3637 rt2800_register_write(rt2x00dev
, WLAN_FUN_CTRL
, reg
);
3640 rt2800_register_read(rt2x00dev
, CMB_CTRL
, ®
);
3641 if (!(rt2x00_get_field32(reg
, LDO0_EN
) == 1)) {
3642 rt2x00_set_field32(®
, LDO0_EN
, 1);
3643 rt2x00_set_field32(®
, LDO_BGSEL
, 3);
3644 rt2800_register_write(rt2x00dev
, CMB_CTRL
, reg
);
3647 rt2800_register_read(rt2x00dev
, OSC_CTRL
, ®
);
3648 rt2x00_set_field32(®
, OSC_ROSC_EN
, 1);
3649 rt2x00_set_field32(®
, OSC_CAL_REQ
, 1);
3650 rt2x00_set_field32(®
, OSC_REF_CYCLE
, 0x27);
3651 rt2800_register_write(rt2x00dev
, OSC_CTRL
, reg
);
3653 rt2800_register_read(rt2x00dev
, COEX_CFG0
, ®
);
3654 rt2x00_set_field32(®
, COEX_CFG_ANT
, 0x5e);
3655 rt2800_register_write(rt2x00dev
, COEX_CFG0
, reg
);
3657 rt2800_register_read(rt2x00dev
, COEX_CFG2
, ®
);
3658 rt2x00_set_field32(®
, BT_COEX_CFG1
, 0x00);
3659 rt2x00_set_field32(®
, BT_COEX_CFG0
, 0x17);
3660 rt2x00_set_field32(®
, WL_COEX_CFG1
, 0x93);
3661 rt2x00_set_field32(®
, WL_COEX_CFG0
, 0x7f);
3662 rt2800_register_write(rt2x00dev
, COEX_CFG2
, reg
);
3664 rt2800_register_read(rt2x00dev
, PLL_CTRL
, ®
);
3665 rt2x00_set_field32(®
, PLL_CONTROL
, 1);
3666 rt2800_register_write(rt2x00dev
, PLL_CTRL
, reg
);
3669 if (rt2x00_rt(rt2x00dev
, RT3071
) ||
3670 rt2x00_rt(rt2x00dev
, RT3090
) ||
3671 rt2x00_rt(rt2x00dev
, RT3290
) ||
3672 rt2x00_rt(rt2x00dev
, RT3390
)) {
3674 if (rt2x00_rt(rt2x00dev
, RT3290
))
3675 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
,
3678 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
,
3681 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
3682 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
3683 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
) ||
3684 rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
)) {
3685 rt2800_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
,
3687 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_DAC_TEST
))
3688 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
,
3691 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
,
3694 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
3696 } else if (rt2x00_rt(rt2x00dev
, RT3070
)) {
3697 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
3699 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
)) {
3700 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
3701 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x0000002c);
3703 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
3704 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
3706 } else if (rt2800_is_305x_soc(rt2x00dev
)) {
3707 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
3708 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
3709 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000030);
3710 } else if (rt2x00_rt(rt2x00dev
, RT3352
)) {
3711 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000402);
3712 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
3713 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
3714 } else if (rt2x00_rt(rt2x00dev
, RT3572
)) {
3715 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
3716 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
3717 } else if (rt2x00_rt(rt2x00dev
, RT3593
)) {
3718 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000402);
3719 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
3720 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3593
, REV_RT3593E
)) {
3721 rt2800_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
,
3723 if (rt2x00_get_field16(eeprom
,
3724 EEPROM_NIC_CONF1_DAC_TEST
))
3725 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
,
3728 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
,
3731 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
,
3734 } else if (rt2x00_rt(rt2x00dev
, RT5390
) ||
3735 rt2x00_rt(rt2x00dev
, RT5392
) ||
3736 rt2x00_rt(rt2x00dev
, RT5592
)) {
3737 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000404);
3738 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
3739 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
3741 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000000);
3742 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
3745 rt2800_register_read(rt2x00dev
, TX_LINK_CFG
, ®
);
3746 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFB_LIFETIME
, 32);
3747 rt2x00_set_field32(®
, TX_LINK_CFG_MFB_ENABLE
, 0);
3748 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_UMFS_ENABLE
, 0);
3749 rt2x00_set_field32(®
, TX_LINK_CFG_TX_MRQ_EN
, 0);
3750 rt2x00_set_field32(®
, TX_LINK_CFG_TX_RDG_EN
, 0);
3751 rt2x00_set_field32(®
, TX_LINK_CFG_TX_CF_ACK_EN
, 1);
3752 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFB
, 0);
3753 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFS
, 0);
3754 rt2800_register_write(rt2x00dev
, TX_LINK_CFG
, reg
);
3756 rt2800_register_read(rt2x00dev
, TX_TIMEOUT_CFG
, ®
);
3757 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_MPDU_LIFETIME
, 9);
3758 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT
, 32);
3759 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_TX_OP_TIMEOUT
, 10);
3760 rt2800_register_write(rt2x00dev
, TX_TIMEOUT_CFG
, reg
);
3762 rt2800_register_read(rt2x00dev
, MAX_LEN_CFG
, ®
);
3763 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_MPDU
, AGGREGATION_SIZE
);
3764 if (rt2x00_rt_rev_gte(rt2x00dev
, RT2872
, REV_RT2872E
) ||
3765 rt2x00_rt(rt2x00dev
, RT2883
) ||
3766 rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070E
))
3767 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_PSDU
, 2);
3769 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_PSDU
, 1);
3770 rt2x00_set_field32(®
, MAX_LEN_CFG_MIN_PSDU
, 0);
3771 rt2x00_set_field32(®
, MAX_LEN_CFG_MIN_MPDU
, 0);
3772 rt2800_register_write(rt2x00dev
, MAX_LEN_CFG
, reg
);
3774 rt2800_register_read(rt2x00dev
, LED_CFG
, ®
);
3775 rt2x00_set_field32(®
, LED_CFG_ON_PERIOD
, 70);
3776 rt2x00_set_field32(®
, LED_CFG_OFF_PERIOD
, 30);
3777 rt2x00_set_field32(®
, LED_CFG_SLOW_BLINK_PERIOD
, 3);
3778 rt2x00_set_field32(®
, LED_CFG_R_LED_MODE
, 3);
3779 rt2x00_set_field32(®
, LED_CFG_G_LED_MODE
, 3);
3780 rt2x00_set_field32(®
, LED_CFG_Y_LED_MODE
, 3);
3781 rt2x00_set_field32(®
, LED_CFG_LED_POLAR
, 1);
3782 rt2800_register_write(rt2x00dev
, LED_CFG
, reg
);
3784 rt2800_register_write(rt2x00dev
, PBF_MAX_PCNT
, 0x1f3fbf9f);
3786 rt2800_register_read(rt2x00dev
, TX_RTY_CFG
, ®
);
3787 rt2x00_set_field32(®
, TX_RTY_CFG_SHORT_RTY_LIMIT
, 15);
3788 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_LIMIT
, 31);
3789 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_THRE
, 2000);
3790 rt2x00_set_field32(®
, TX_RTY_CFG_NON_AGG_RTY_MODE
, 0);
3791 rt2x00_set_field32(®
, TX_RTY_CFG_AGG_RTY_MODE
, 0);
3792 rt2x00_set_field32(®
, TX_RTY_CFG_TX_AUTO_FB_ENABLE
, 1);
3793 rt2800_register_write(rt2x00dev
, TX_RTY_CFG
, reg
);
3795 rt2800_register_read(rt2x00dev
, AUTO_RSP_CFG
, ®
);
3796 rt2x00_set_field32(®
, AUTO_RSP_CFG_AUTORESPONDER
, 1);
3797 rt2x00_set_field32(®
, AUTO_RSP_CFG_BAC_ACK_POLICY
, 1);
3798 rt2x00_set_field32(®
, AUTO_RSP_CFG_CTS_40_MMODE
, 0);
3799 rt2x00_set_field32(®
, AUTO_RSP_CFG_CTS_40_MREF
, 0);
3800 rt2x00_set_field32(®
, AUTO_RSP_CFG_AR_PREAMBLE
, 1);
3801 rt2x00_set_field32(®
, AUTO_RSP_CFG_DUAL_CTS_EN
, 0);
3802 rt2x00_set_field32(®
, AUTO_RSP_CFG_ACK_CTS_PSM_BIT
, 0);
3803 rt2800_register_write(rt2x00dev
, AUTO_RSP_CFG
, reg
);
3805 rt2800_register_read(rt2x00dev
, CCK_PROT_CFG
, ®
);
3806 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_RATE
, 3);
3807 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_CTRL
, 0);
3808 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_NAV_SHORT
, 1);
3809 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
3810 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
3811 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
3812 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
3813 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
3814 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
3815 rt2x00_set_field32(®
, CCK_PROT_CFG_RTS_TH_EN
, 1);
3816 rt2800_register_write(rt2x00dev
, CCK_PROT_CFG
, reg
);
3818 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
3819 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_RATE
, 3);
3820 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_CTRL
, 0);
3821 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_NAV_SHORT
, 1);
3822 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
3823 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
3824 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
3825 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
3826 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
3827 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
3828 rt2x00_set_field32(®
, OFDM_PROT_CFG_RTS_TH_EN
, 1);
3829 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
3831 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
3832 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_RATE
, 0x4004);
3833 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_CTRL
, 0);
3834 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_NAV_SHORT
, 1);
3835 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
3836 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
3837 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
3838 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
3839 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
3840 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
3841 rt2x00_set_field32(®
, MM20_PROT_CFG_RTS_TH_EN
, 0);
3842 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
3844 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
3845 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_RATE
, 0x4084);
3846 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_CTRL
, 0);
3847 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_NAV_SHORT
, 1);
3848 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
3849 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
3850 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
3851 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_MM40
, 1);
3852 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
3853 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_GF40
, 1);
3854 rt2x00_set_field32(®
, MM40_PROT_CFG_RTS_TH_EN
, 0);
3855 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
3857 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
3858 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_RATE
, 0x4004);
3859 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_CTRL
, 0);
3860 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_NAV_SHORT
, 1);
3861 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
3862 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
3863 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
3864 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
3865 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
3866 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
3867 rt2x00_set_field32(®
, GF20_PROT_CFG_RTS_TH_EN
, 0);
3868 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
3870 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
3871 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_RATE
, 0x4084);
3872 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_CTRL
, 0);
3873 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_NAV_SHORT
, 1);
3874 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
3875 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
3876 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
3877 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_MM40
, 1);
3878 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
3879 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_GF40
, 1);
3880 rt2x00_set_field32(®
, GF40_PROT_CFG_RTS_TH_EN
, 0);
3881 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
3883 if (rt2x00_is_usb(rt2x00dev
)) {
3884 rt2800_register_write(rt2x00dev
, PBF_CFG
, 0xf40006);
3886 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
3887 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
3888 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_DMA_BUSY
, 0);
3889 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
3890 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_DMA_BUSY
, 0);
3891 rt2x00_set_field32(®
, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE
, 3);
3892 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 0);
3893 rt2x00_set_field32(®
, WPDMA_GLO_CFG_BIG_ENDIAN
, 0);
3894 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_HDR_SCATTER
, 0);
3895 rt2x00_set_field32(®
, WPDMA_GLO_CFG_HDR_SEG_LEN
, 0);
3896 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
3900 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
3901 * although it is reserved.
3903 rt2800_register_read(rt2x00dev
, TXOP_CTRL_CFG
, ®
);
3904 rt2x00_set_field32(®
, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN
, 1);
3905 rt2x00_set_field32(®
, TXOP_CTRL_CFG_AC_TRUN_EN
, 1);
3906 rt2x00_set_field32(®
, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN
, 1);
3907 rt2x00_set_field32(®
, TXOP_CTRL_CFG_USER_MODE_TRUN_EN
, 1);
3908 rt2x00_set_field32(®
, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN
, 1);
3909 rt2x00_set_field32(®
, TXOP_CTRL_CFG_RESERVED_TRUN_EN
, 1);
3910 rt2x00_set_field32(®
, TXOP_CTRL_CFG_LSIG_TXOP_EN
, 0);
3911 rt2x00_set_field32(®
, TXOP_CTRL_CFG_EXT_CCA_EN
, 0);
3912 rt2x00_set_field32(®
, TXOP_CTRL_CFG_EXT_CCA_DLY
, 88);
3913 rt2x00_set_field32(®
, TXOP_CTRL_CFG_EXT_CWMIN
, 0);
3914 rt2800_register_write(rt2x00dev
, TXOP_CTRL_CFG
, reg
);
3916 reg
= rt2x00_rt(rt2x00dev
, RT5592
) ? 0x00000082 : 0x00000002;
3917 rt2800_register_write(rt2x00dev
, TXOP_HLDR_ET
, reg
);
3919 rt2800_register_read(rt2x00dev
, TX_RTS_CFG
, ®
);
3920 rt2x00_set_field32(®
, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT
, 32);
3921 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_THRES
,
3922 IEEE80211_MAX_RTS_THRESHOLD
);
3923 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_FBK_EN
, 0);
3924 rt2800_register_write(rt2x00dev
, TX_RTS_CFG
, reg
);
3926 rt2800_register_write(rt2x00dev
, EXP_ACK_TIME
, 0x002400ca);
3929 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
3930 * time should be set to 16. However, the original Ralink driver uses
3931 * 16 for both and indeed using a value of 10 for CCK SIFS results in
3932 * connection problems with 11g + CTS protection. Hence, use the same
3933 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
3935 rt2800_register_read(rt2x00dev
, XIFS_TIME_CFG
, ®
);
3936 rt2x00_set_field32(®
, XIFS_TIME_CFG_CCKM_SIFS_TIME
, 16);
3937 rt2x00_set_field32(®
, XIFS_TIME_CFG_OFDM_SIFS_TIME
, 16);
3938 rt2x00_set_field32(®
, XIFS_TIME_CFG_OFDM_XIFS_TIME
, 4);
3939 rt2x00_set_field32(®
, XIFS_TIME_CFG_EIFS
, 314);
3940 rt2x00_set_field32(®
, XIFS_TIME_CFG_BB_RXEND_ENABLE
, 1);
3941 rt2800_register_write(rt2x00dev
, XIFS_TIME_CFG
, reg
);
3943 rt2800_register_write(rt2x00dev
, PWR_PIN_CFG
, 0x00000003);
3946 * ASIC will keep garbage value after boot, clear encryption keys.
3948 for (i
= 0; i
< 4; i
++)
3949 rt2800_register_write(rt2x00dev
,
3950 SHARED_KEY_MODE_ENTRY(i
), 0);
3952 for (i
= 0; i
< 256; i
++) {
3953 rt2800_config_wcid(rt2x00dev
, NULL
, i
);
3954 rt2800_delete_wcid_attr(rt2x00dev
, i
);
3955 rt2800_register_write(rt2x00dev
, MAC_IVEIV_ENTRY(i
), 0);
3961 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE0
);
3962 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE1
);
3963 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE2
);
3964 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE3
);
3965 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE4
);
3966 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE5
);
3967 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE6
);
3968 rt2800_clear_beacon_register(rt2x00dev
, HW_BEACON_BASE7
);
3970 if (rt2x00_is_usb(rt2x00dev
)) {
3971 rt2800_register_read(rt2x00dev
, US_CYC_CNT
, ®
);
3972 rt2x00_set_field32(®
, US_CYC_CNT_CLOCK_CYCLE
, 30);
3973 rt2800_register_write(rt2x00dev
, US_CYC_CNT
, reg
);
3974 } else if (rt2x00_is_pcie(rt2x00dev
)) {
3975 rt2800_register_read(rt2x00dev
, US_CYC_CNT
, ®
);
3976 rt2x00_set_field32(®
, US_CYC_CNT_CLOCK_CYCLE
, 125);
3977 rt2800_register_write(rt2x00dev
, US_CYC_CNT
, reg
);
3980 rt2800_register_read(rt2x00dev
, HT_FBK_CFG0
, ®
);
3981 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS0FBK
, 0);
3982 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS1FBK
, 0);
3983 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS2FBK
, 1);
3984 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS3FBK
, 2);
3985 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS4FBK
, 3);
3986 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS5FBK
, 4);
3987 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS6FBK
, 5);
3988 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS7FBK
, 6);
3989 rt2800_register_write(rt2x00dev
, HT_FBK_CFG0
, reg
);
3991 rt2800_register_read(rt2x00dev
, HT_FBK_CFG1
, ®
);
3992 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS8FBK
, 8);
3993 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS9FBK
, 8);
3994 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS10FBK
, 9);
3995 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS11FBK
, 10);
3996 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS12FBK
, 11);
3997 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS13FBK
, 12);
3998 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS14FBK
, 13);
3999 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS15FBK
, 14);
4000 rt2800_register_write(rt2x00dev
, HT_FBK_CFG1
, reg
);
4002 rt2800_register_read(rt2x00dev
, LG_FBK_CFG0
, ®
);
4003 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS0FBK
, 8);
4004 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS1FBK
, 8);
4005 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS2FBK
, 9);
4006 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS3FBK
, 10);
4007 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS4FBK
, 11);
4008 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS5FBK
, 12);
4009 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS6FBK
, 13);
4010 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS7FBK
, 14);
4011 rt2800_register_write(rt2x00dev
, LG_FBK_CFG0
, reg
);
4013 rt2800_register_read(rt2x00dev
, LG_FBK_CFG1
, ®
);
4014 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS0FBK
, 0);
4015 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS1FBK
, 0);
4016 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS2FBK
, 1);
4017 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS3FBK
, 2);
4018 rt2800_register_write(rt2x00dev
, LG_FBK_CFG1
, reg
);
4021 * Do not force the BA window size, we use the TXWI to set it
4023 rt2800_register_read(rt2x00dev
, AMPDU_BA_WINSIZE
, ®
);
4024 rt2x00_set_field32(®
, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE
, 0);
4025 rt2x00_set_field32(®
, AMPDU_BA_WINSIZE_FORCE_WINSIZE
, 0);
4026 rt2800_register_write(rt2x00dev
, AMPDU_BA_WINSIZE
, reg
);
4029 * We must clear the error counters.
4030 * These registers are cleared on read,
4031 * so we may pass a useless variable to store the value.
4033 rt2800_register_read(rt2x00dev
, RX_STA_CNT0
, ®
);
4034 rt2800_register_read(rt2x00dev
, RX_STA_CNT1
, ®
);
4035 rt2800_register_read(rt2x00dev
, RX_STA_CNT2
, ®
);
4036 rt2800_register_read(rt2x00dev
, TX_STA_CNT0
, ®
);
4037 rt2800_register_read(rt2x00dev
, TX_STA_CNT1
, ®
);
4038 rt2800_register_read(rt2x00dev
, TX_STA_CNT2
, ®
);
4041 * Setup leadtime for pre tbtt interrupt to 6ms
4043 rt2800_register_read(rt2x00dev
, INT_TIMER_CFG
, ®
);
4044 rt2x00_set_field32(®
, INT_TIMER_CFG_PRE_TBTT_TIMER
, 6 << 4);
4045 rt2800_register_write(rt2x00dev
, INT_TIMER_CFG
, reg
);
4048 * Set up channel statistics timer
4050 rt2800_register_read(rt2x00dev
, CH_TIME_CFG
, ®
);
4051 rt2x00_set_field32(®
, CH_TIME_CFG_EIFS_BUSY
, 1);
4052 rt2x00_set_field32(®
, CH_TIME_CFG_NAV_BUSY
, 1);
4053 rt2x00_set_field32(®
, CH_TIME_CFG_RX_BUSY
, 1);
4054 rt2x00_set_field32(®
, CH_TIME_CFG_TX_BUSY
, 1);
4055 rt2x00_set_field32(®
, CH_TIME_CFG_TMR_EN
, 1);
4056 rt2800_register_write(rt2x00dev
, CH_TIME_CFG
, reg
);
4061 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev
*rt2x00dev
)
4066 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
4067 rt2800_register_read(rt2x00dev
, MAC_STATUS_CFG
, ®
);
4068 if (!rt2x00_get_field32(reg
, MAC_STATUS_CFG_BBP_RF_BUSY
))
4071 udelay(REGISTER_BUSY_DELAY
);
4074 rt2x00_err(rt2x00dev
, "BBP/RF register access failed, aborting\n");
4078 static int rt2800_wait_bbp_ready(struct rt2x00_dev
*rt2x00dev
)
4084 * BBP was enabled after firmware was loaded,
4085 * but we need to reactivate it now.
4087 rt2800_register_write(rt2x00dev
, H2M_BBP_AGENT
, 0);
4088 rt2800_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
4091 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
4092 rt2800_bbp_read(rt2x00dev
, 0, &value
);
4093 if ((value
!= 0xff) && (value
!= 0x00))
4095 udelay(REGISTER_BUSY_DELAY
);
4098 rt2x00_err(rt2x00dev
, "BBP register access failed, aborting\n");
4102 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev
*rt2x00dev
)
4106 rt2800_bbp_read(rt2x00dev
, 4, &value
);
4107 rt2x00_set_field8(&value
, BBP4_MAC_IF_CTRL
, 1);
4108 rt2800_bbp_write(rt2x00dev
, 4, value
);
4111 static void rt2800_init_freq_calibration(struct rt2x00_dev
*rt2x00dev
)
4113 rt2800_bbp_write(rt2x00dev
, 142, 1);
4114 rt2800_bbp_write(rt2x00dev
, 143, 57);
4117 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev
*rt2x00dev
)
4119 const u8 glrt_table
[] = {
4120 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
4121 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
4122 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
4123 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
4124 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
4125 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
4126 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
4127 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
4128 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */
4132 for (i
= 0; i
< ARRAY_SIZE(glrt_table
); i
++) {
4133 rt2800_bbp_write(rt2x00dev
, 195, 128 + i
);
4134 rt2800_bbp_write(rt2x00dev
, 196, glrt_table
[i
]);
4138 static void rt2800_init_bbp_early(struct rt2x00_dev
*rt2x00dev
)
4140 rt2800_bbp_write(rt2x00dev
, 65, 0x2C);
4141 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
4142 rt2800_bbp_write(rt2x00dev
, 68, 0x0B);
4143 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
4144 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
4145 rt2800_bbp_write(rt2x00dev
, 73, 0x10);
4146 rt2800_bbp_write(rt2x00dev
, 81, 0x37);
4147 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
4148 rt2800_bbp_write(rt2x00dev
, 83, 0x6A);
4149 rt2800_bbp_write(rt2x00dev
, 84, 0x99);
4150 rt2800_bbp_write(rt2x00dev
, 86, 0x00);
4151 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
4152 rt2800_bbp_write(rt2x00dev
, 92, 0x00);
4153 rt2800_bbp_write(rt2x00dev
, 103, 0x00);
4154 rt2800_bbp_write(rt2x00dev
, 105, 0x05);
4155 rt2800_bbp_write(rt2x00dev
, 106, 0x35);
4158 static void rt2800_disable_unused_dac_adc(struct rt2x00_dev
*rt2x00dev
)
4163 rt2800_bbp_read(rt2x00dev
, 138, &value
);
4164 rt2800_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &eeprom
);
4165 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
) == 1)
4167 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
) == 1)
4169 rt2800_bbp_write(rt2x00dev
, 138, value
);
4172 static void rt2800_init_bbp_305x_soc(struct rt2x00_dev
*rt2x00dev
)
4174 rt2800_bbp_write(rt2x00dev
, 31, 0x08);
4176 rt2800_bbp_write(rt2x00dev
, 65, 0x2c);
4177 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
4179 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
4180 rt2800_bbp_write(rt2x00dev
, 73, 0x10);
4182 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
4184 rt2800_bbp_write(rt2x00dev
, 78, 0x0e);
4185 rt2800_bbp_write(rt2x00dev
, 80, 0x08);
4187 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
4189 rt2800_bbp_write(rt2x00dev
, 83, 0x6a);
4191 rt2800_bbp_write(rt2x00dev
, 84, 0x99);
4193 rt2800_bbp_write(rt2x00dev
, 86, 0x00);
4195 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
4197 rt2800_bbp_write(rt2x00dev
, 92, 0x00);
4199 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
4201 rt2800_bbp_write(rt2x00dev
, 105, 0x01);
4203 rt2800_bbp_write(rt2x00dev
, 106, 0x35);
4206 static void rt2800_init_bbp_28xx(struct rt2x00_dev
*rt2x00dev
)
4208 rt2800_bbp_write(rt2x00dev
, 65, 0x2c);
4209 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
4211 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
)) {
4212 rt2800_bbp_write(rt2x00dev
, 69, 0x16);
4213 rt2800_bbp_write(rt2x00dev
, 73, 0x12);
4215 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
4216 rt2800_bbp_write(rt2x00dev
, 73, 0x10);
4219 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
4221 rt2800_bbp_write(rt2x00dev
, 81, 0x37);
4223 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
4225 rt2800_bbp_write(rt2x00dev
, 83, 0x6a);
4227 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860D
))
4228 rt2800_bbp_write(rt2x00dev
, 84, 0x19);
4230 rt2800_bbp_write(rt2x00dev
, 84, 0x99);
4232 rt2800_bbp_write(rt2x00dev
, 86, 0x00);
4234 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
4236 rt2800_bbp_write(rt2x00dev
, 92, 0x00);
4238 rt2800_bbp_write(rt2x00dev
, 103, 0x00);
4240 rt2800_bbp_write(rt2x00dev
, 105, 0x05);
4242 rt2800_bbp_write(rt2x00dev
, 106, 0x35);
4245 static void rt2800_init_bbp_30xx(struct rt2x00_dev
*rt2x00dev
)
4247 rt2800_bbp_write(rt2x00dev
, 65, 0x2c);
4248 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
4250 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
4251 rt2800_bbp_write(rt2x00dev
, 73, 0x10);
4253 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
4255 rt2800_bbp_write(rt2x00dev
, 79, 0x13);
4256 rt2800_bbp_write(rt2x00dev
, 80, 0x05);
4257 rt2800_bbp_write(rt2x00dev
, 81, 0x33);
4259 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
4261 rt2800_bbp_write(rt2x00dev
, 83, 0x6a);
4263 rt2800_bbp_write(rt2x00dev
, 84, 0x99);
4265 rt2800_bbp_write(rt2x00dev
, 86, 0x00);
4267 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
4269 rt2800_bbp_write(rt2x00dev
, 92, 0x00);
4271 if (rt2x00_rt_rev_gte(rt2x00dev
, RT3070
, REV_RT3070F
) ||
4272 rt2x00_rt_rev_gte(rt2x00dev
, RT3071
, REV_RT3071E
) ||
4273 rt2x00_rt_rev_gte(rt2x00dev
, RT3090
, REV_RT3090E
))
4274 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
4276 rt2800_bbp_write(rt2x00dev
, 103, 0x00);
4278 rt2800_bbp_write(rt2x00dev
, 105, 0x05);
4280 rt2800_bbp_write(rt2x00dev
, 106, 0x35);
4282 if (rt2x00_rt(rt2x00dev
, RT3071
) ||
4283 rt2x00_rt(rt2x00dev
, RT3090
))
4284 rt2800_disable_unused_dac_adc(rt2x00dev
);
4287 static void rt2800_init_bbp_3290(struct rt2x00_dev
*rt2x00dev
)
4291 rt2800_bbp4_mac_if_ctrl(rt2x00dev
);
4293 rt2800_bbp_write(rt2x00dev
, 31, 0x08);
4295 rt2800_bbp_write(rt2x00dev
, 65, 0x2c);
4296 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
4298 rt2800_bbp_write(rt2x00dev
, 68, 0x0b);
4300 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
4301 rt2800_bbp_write(rt2x00dev
, 73, 0x13);
4302 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
4303 rt2800_bbp_write(rt2x00dev
, 76, 0x28);
4305 rt2800_bbp_write(rt2x00dev
, 77, 0x58);
4307 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
4309 rt2800_bbp_write(rt2x00dev
, 74, 0x0b);
4310 rt2800_bbp_write(rt2x00dev
, 79, 0x18);
4311 rt2800_bbp_write(rt2x00dev
, 80, 0x09);
4312 rt2800_bbp_write(rt2x00dev
, 81, 0x33);
4314 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
4316 rt2800_bbp_write(rt2x00dev
, 83, 0x7a);
4318 rt2800_bbp_write(rt2x00dev
, 84, 0x9a);
4320 rt2800_bbp_write(rt2x00dev
, 86, 0x38);
4322 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
4324 rt2800_bbp_write(rt2x00dev
, 92, 0x02);
4326 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
4328 rt2800_bbp_write(rt2x00dev
, 104, 0x92);
4330 rt2800_bbp_write(rt2x00dev
, 105, 0x1c);
4332 rt2800_bbp_write(rt2x00dev
, 106, 0x03);
4334 rt2800_bbp_write(rt2x00dev
, 128, 0x12);
4336 rt2800_bbp_write(rt2x00dev
, 67, 0x24);
4337 rt2800_bbp_write(rt2x00dev
, 143, 0x04);
4338 rt2800_bbp_write(rt2x00dev
, 142, 0x99);
4339 rt2800_bbp_write(rt2x00dev
, 150, 0x30);
4340 rt2800_bbp_write(rt2x00dev
, 151, 0x2e);
4341 rt2800_bbp_write(rt2x00dev
, 152, 0x20);
4342 rt2800_bbp_write(rt2x00dev
, 153, 0x34);
4343 rt2800_bbp_write(rt2x00dev
, 154, 0x40);
4344 rt2800_bbp_write(rt2x00dev
, 155, 0x3b);
4345 rt2800_bbp_write(rt2x00dev
, 253, 0x04);
4347 rt2800_bbp_read(rt2x00dev
, 47, &value
);
4348 rt2x00_set_field8(&value
, BBP47_TSSI_ADC6
, 1);
4349 rt2800_bbp_write(rt2x00dev
, 47, value
);
4351 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
4352 rt2800_bbp_read(rt2x00dev
, 3, &value
);
4353 rt2x00_set_field8(&value
, BBP3_ADC_MODE_SWITCH
, 1);
4354 rt2x00_set_field8(&value
, BBP3_ADC_INIT_MODE
, 1);
4355 rt2800_bbp_write(rt2x00dev
, 3, value
);
4358 static void rt2800_init_bbp_3352(struct rt2x00_dev
*rt2x00dev
)
4360 rt2800_bbp_write(rt2x00dev
, 3, 0x00);
4361 rt2800_bbp_write(rt2x00dev
, 4, 0x50);
4363 rt2800_bbp_write(rt2x00dev
, 31, 0x08);
4365 rt2800_bbp_write(rt2x00dev
, 47, 0x48);
4367 rt2800_bbp_write(rt2x00dev
, 65, 0x2c);
4368 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
4370 rt2800_bbp_write(rt2x00dev
, 68, 0x0b);
4372 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
4373 rt2800_bbp_write(rt2x00dev
, 73, 0x13);
4374 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
4375 rt2800_bbp_write(rt2x00dev
, 76, 0x28);
4377 rt2800_bbp_write(rt2x00dev
, 77, 0x59);
4379 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
4381 rt2800_bbp_write(rt2x00dev
, 78, 0x0e);
4382 rt2800_bbp_write(rt2x00dev
, 80, 0x08);
4383 rt2800_bbp_write(rt2x00dev
, 81, 0x37);
4385 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
4387 rt2800_bbp_write(rt2x00dev
, 83, 0x6a);
4389 rt2800_bbp_write(rt2x00dev
, 84, 0x99);
4391 rt2800_bbp_write(rt2x00dev
, 86, 0x38);
4393 rt2800_bbp_write(rt2x00dev
, 88, 0x90);
4395 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
4397 rt2800_bbp_write(rt2x00dev
, 92, 0x02);
4399 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
4401 rt2800_bbp_write(rt2x00dev
, 104, 0x92);
4403 rt2800_bbp_write(rt2x00dev
, 105, 0x34);
4405 rt2800_bbp_write(rt2x00dev
, 106, 0x05);
4407 rt2800_bbp_write(rt2x00dev
, 120, 0x50);
4409 rt2800_bbp_write(rt2x00dev
, 137, 0x0f);
4411 rt2800_bbp_write(rt2x00dev
, 163, 0xbd);
4412 /* Set ITxBF timeout to 0x9c40=1000msec */
4413 rt2800_bbp_write(rt2x00dev
, 179, 0x02);
4414 rt2800_bbp_write(rt2x00dev
, 180, 0x00);
4415 rt2800_bbp_write(rt2x00dev
, 182, 0x40);
4416 rt2800_bbp_write(rt2x00dev
, 180, 0x01);
4417 rt2800_bbp_write(rt2x00dev
, 182, 0x9c);
4418 rt2800_bbp_write(rt2x00dev
, 179, 0x00);
4419 /* Reprogram the inband interface to put right values in RXWI */
4420 rt2800_bbp_write(rt2x00dev
, 142, 0x04);
4421 rt2800_bbp_write(rt2x00dev
, 143, 0x3b);
4422 rt2800_bbp_write(rt2x00dev
, 142, 0x06);
4423 rt2800_bbp_write(rt2x00dev
, 143, 0xa0);
4424 rt2800_bbp_write(rt2x00dev
, 142, 0x07);
4425 rt2800_bbp_write(rt2x00dev
, 143, 0xa1);
4426 rt2800_bbp_write(rt2x00dev
, 142, 0x08);
4427 rt2800_bbp_write(rt2x00dev
, 143, 0xa2);
4429 rt2800_bbp_write(rt2x00dev
, 148, 0xc8);
4432 static void rt2800_init_bbp_3390(struct rt2x00_dev
*rt2x00dev
)
4434 rt2800_bbp_write(rt2x00dev
, 65, 0x2c);
4435 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
4437 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
4438 rt2800_bbp_write(rt2x00dev
, 73, 0x10);
4440 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
4442 rt2800_bbp_write(rt2x00dev
, 79, 0x13);
4443 rt2800_bbp_write(rt2x00dev
, 80, 0x05);
4444 rt2800_bbp_write(rt2x00dev
, 81, 0x33);
4446 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
4448 rt2800_bbp_write(rt2x00dev
, 83, 0x6a);
4450 rt2800_bbp_write(rt2x00dev
, 84, 0x99);
4452 rt2800_bbp_write(rt2x00dev
, 86, 0x00);
4454 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
4456 rt2800_bbp_write(rt2x00dev
, 92, 0x00);
4458 if (rt2x00_rt_rev_gte(rt2x00dev
, RT3390
, REV_RT3390E
))
4459 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
4461 rt2800_bbp_write(rt2x00dev
, 103, 0x00);
4463 rt2800_bbp_write(rt2x00dev
, 105, 0x05);
4465 rt2800_bbp_write(rt2x00dev
, 106, 0x35);
4467 rt2800_disable_unused_dac_adc(rt2x00dev
);
4470 static void rt2800_init_bbp_3572(struct rt2x00_dev
*rt2x00dev
)
4472 rt2800_bbp_write(rt2x00dev
, 31, 0x08);
4474 rt2800_bbp_write(rt2x00dev
, 65, 0x2c);
4475 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
4477 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
4478 rt2800_bbp_write(rt2x00dev
, 73, 0x10);
4480 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
4482 rt2800_bbp_write(rt2x00dev
, 79, 0x13);
4483 rt2800_bbp_write(rt2x00dev
, 80, 0x05);
4484 rt2800_bbp_write(rt2x00dev
, 81, 0x33);
4486 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
4488 rt2800_bbp_write(rt2x00dev
, 83, 0x6a);
4490 rt2800_bbp_write(rt2x00dev
, 84, 0x99);
4492 rt2800_bbp_write(rt2x00dev
, 86, 0x00);
4494 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
4496 rt2800_bbp_write(rt2x00dev
, 92, 0x00);
4498 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
4500 rt2800_bbp_write(rt2x00dev
, 105, 0x05);
4502 rt2800_bbp_write(rt2x00dev
, 106, 0x35);
4504 rt2800_disable_unused_dac_adc(rt2x00dev
);
4507 static void rt2800_init_bbp_3593(struct rt2x00_dev
*rt2x00dev
)
4509 rt2800_init_bbp_early(rt2x00dev
);
4511 rt2800_bbp_write(rt2x00dev
, 79, 0x13);
4512 rt2800_bbp_write(rt2x00dev
, 80, 0x05);
4513 rt2800_bbp_write(rt2x00dev
, 81, 0x33);
4514 rt2800_bbp_write(rt2x00dev
, 137, 0x0f);
4516 rt2800_bbp_write(rt2x00dev
, 84, 0x19);
4518 /* Enable DC filter */
4519 if (rt2x00_rt_rev_gte(rt2x00dev
, RT3593
, REV_RT3593E
))
4520 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
4523 static void rt2800_init_bbp_53xx(struct rt2x00_dev
*rt2x00dev
)
4529 rt2800_bbp4_mac_if_ctrl(rt2x00dev
);
4531 rt2800_bbp_write(rt2x00dev
, 31, 0x08);
4533 rt2800_bbp_write(rt2x00dev
, 65, 0x2c);
4534 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
4536 rt2800_bbp_write(rt2x00dev
, 68, 0x0b);
4538 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
4539 rt2800_bbp_write(rt2x00dev
, 73, 0x13);
4540 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
4541 rt2800_bbp_write(rt2x00dev
, 76, 0x28);
4543 rt2800_bbp_write(rt2x00dev
, 77, 0x59);
4545 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
4547 rt2800_bbp_write(rt2x00dev
, 79, 0x13);
4548 rt2800_bbp_write(rt2x00dev
, 80, 0x05);
4549 rt2800_bbp_write(rt2x00dev
, 81, 0x33);
4551 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
4553 rt2800_bbp_write(rt2x00dev
, 83, 0x7a);
4555 rt2800_bbp_write(rt2x00dev
, 84, 0x9a);
4557 rt2800_bbp_write(rt2x00dev
, 86, 0x38);
4559 if (rt2x00_rt(rt2x00dev
, RT5392
))
4560 rt2800_bbp_write(rt2x00dev
, 88, 0x90);
4562 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
4564 rt2800_bbp_write(rt2x00dev
, 92, 0x02);
4566 if (rt2x00_rt(rt2x00dev
, RT5392
)) {
4567 rt2800_bbp_write(rt2x00dev
, 95, 0x9a);
4568 rt2800_bbp_write(rt2x00dev
, 98, 0x12);
4571 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
4573 rt2800_bbp_write(rt2x00dev
, 104, 0x92);
4575 rt2800_bbp_write(rt2x00dev
, 105, 0x3c);
4577 if (rt2x00_rt(rt2x00dev
, RT5390
))
4578 rt2800_bbp_write(rt2x00dev
, 106, 0x03);
4579 else if (rt2x00_rt(rt2x00dev
, RT5392
))
4580 rt2800_bbp_write(rt2x00dev
, 106, 0x12);
4584 rt2800_bbp_write(rt2x00dev
, 128, 0x12);
4586 if (rt2x00_rt(rt2x00dev
, RT5392
)) {
4587 rt2800_bbp_write(rt2x00dev
, 134, 0xd0);
4588 rt2800_bbp_write(rt2x00dev
, 135, 0xf6);
4591 rt2800_disable_unused_dac_adc(rt2x00dev
);
4593 rt2800_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &eeprom
);
4594 div_mode
= rt2x00_get_field16(eeprom
,
4595 EEPROM_NIC_CONF1_ANT_DIVERSITY
);
4596 ant
= (div_mode
== 3) ? 1 : 0;
4598 /* check if this is a Bluetooth combo card */
4599 if (test_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
)) {
4602 rt2800_register_read(rt2x00dev
, GPIO_CTRL
, ®
);
4603 rt2x00_set_field32(®
, GPIO_CTRL_DIR3
, 0);
4604 rt2x00_set_field32(®
, GPIO_CTRL_DIR6
, 0);
4605 rt2x00_set_field32(®
, GPIO_CTRL_VAL3
, 0);
4606 rt2x00_set_field32(®
, GPIO_CTRL_VAL6
, 0);
4608 rt2x00_set_field32(®
, GPIO_CTRL_VAL3
, 1);
4610 rt2x00_set_field32(®
, GPIO_CTRL_VAL6
, 1);
4611 rt2800_register_write(rt2x00dev
, GPIO_CTRL
, reg
);
4614 /* This chip has hardware antenna diversity*/
4615 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390R
)) {
4616 rt2800_bbp_write(rt2x00dev
, 150, 0); /* Disable Antenna Software OFDM */
4617 rt2800_bbp_write(rt2x00dev
, 151, 0); /* Disable Antenna Software CCK */
4618 rt2800_bbp_write(rt2x00dev
, 154, 0); /* Clear previously selected antenna */
4621 rt2800_bbp_read(rt2x00dev
, 152, &value
);
4623 rt2x00_set_field8(&value
, BBP152_RX_DEFAULT_ANT
, 1);
4625 rt2x00_set_field8(&value
, BBP152_RX_DEFAULT_ANT
, 0);
4626 rt2800_bbp_write(rt2x00dev
, 152, value
);
4628 rt2800_init_freq_calibration(rt2x00dev
);
4631 static void rt2800_init_bbp_5592(struct rt2x00_dev
*rt2x00dev
)
4637 rt2800_init_bbp_early(rt2x00dev
);
4639 rt2800_bbp_read(rt2x00dev
, 105, &value
);
4640 rt2x00_set_field8(&value
, BBP105_MLD
,
4641 rt2x00dev
->default_ant
.rx_chain_num
== 2);
4642 rt2800_bbp_write(rt2x00dev
, 105, value
);
4644 rt2800_bbp4_mac_if_ctrl(rt2x00dev
);
4646 rt2800_bbp_write(rt2x00dev
, 20, 0x06);
4647 rt2800_bbp_write(rt2x00dev
, 31, 0x08);
4648 rt2800_bbp_write(rt2x00dev
, 65, 0x2C);
4649 rt2800_bbp_write(rt2x00dev
, 68, 0xDD);
4650 rt2800_bbp_write(rt2x00dev
, 69, 0x1A);
4651 rt2800_bbp_write(rt2x00dev
, 70, 0x05);
4652 rt2800_bbp_write(rt2x00dev
, 73, 0x13);
4653 rt2800_bbp_write(rt2x00dev
, 74, 0x0F);
4654 rt2800_bbp_write(rt2x00dev
, 75, 0x4F);
4655 rt2800_bbp_write(rt2x00dev
, 76, 0x28);
4656 rt2800_bbp_write(rt2x00dev
, 77, 0x59);
4657 rt2800_bbp_write(rt2x00dev
, 84, 0x9A);
4658 rt2800_bbp_write(rt2x00dev
, 86, 0x38);
4659 rt2800_bbp_write(rt2x00dev
, 88, 0x90);
4660 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
4661 rt2800_bbp_write(rt2x00dev
, 92, 0x02);
4662 rt2800_bbp_write(rt2x00dev
, 95, 0x9a);
4663 rt2800_bbp_write(rt2x00dev
, 98, 0x12);
4664 rt2800_bbp_write(rt2x00dev
, 103, 0xC0);
4665 rt2800_bbp_write(rt2x00dev
, 104, 0x92);
4666 /* FIXME BBP105 owerwrite */
4667 rt2800_bbp_write(rt2x00dev
, 105, 0x3C);
4668 rt2800_bbp_write(rt2x00dev
, 106, 0x35);
4669 rt2800_bbp_write(rt2x00dev
, 128, 0x12);
4670 rt2800_bbp_write(rt2x00dev
, 134, 0xD0);
4671 rt2800_bbp_write(rt2x00dev
, 135, 0xF6);
4672 rt2800_bbp_write(rt2x00dev
, 137, 0x0F);
4674 /* Initialize GLRT (Generalized Likehood Radio Test) */
4675 rt2800_init_bbp_5592_glrt(rt2x00dev
);
4677 rt2800_bbp4_mac_if_ctrl(rt2x00dev
);
4679 rt2800_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &eeprom
);
4680 div_mode
= rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_ANT_DIVERSITY
);
4681 ant
= (div_mode
== 3) ? 1 : 0;
4682 rt2800_bbp_read(rt2x00dev
, 152, &value
);
4685 rt2x00_set_field8(&value
, BBP152_RX_DEFAULT_ANT
, 1);
4687 /* Auxiliary antenna */
4688 rt2x00_set_field8(&value
, BBP152_RX_DEFAULT_ANT
, 0);
4690 rt2800_bbp_write(rt2x00dev
, 152, value
);
4692 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5592
, REV_RT5592C
)) {
4693 rt2800_bbp_read(rt2x00dev
, 254, &value
);
4694 rt2x00_set_field8(&value
, BBP254_BIT7
, 1);
4695 rt2800_bbp_write(rt2x00dev
, 254, value
);
4698 rt2800_init_freq_calibration(rt2x00dev
);
4700 rt2800_bbp_write(rt2x00dev
, 84, 0x19);
4701 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5592
, REV_RT5592C
))
4702 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
4705 static void rt2800_init_bbp(struct rt2x00_dev
*rt2x00dev
)
4712 if (rt2800_is_305x_soc(rt2x00dev
))
4713 rt2800_init_bbp_305x_soc(rt2x00dev
);
4715 switch (rt2x00dev
->chip
.rt
) {
4719 rt2800_init_bbp_28xx(rt2x00dev
);
4724 rt2800_init_bbp_30xx(rt2x00dev
);
4727 rt2800_init_bbp_3290(rt2x00dev
);
4730 rt2800_init_bbp_3352(rt2x00dev
);
4733 rt2800_init_bbp_3390(rt2x00dev
);
4736 rt2800_init_bbp_3572(rt2x00dev
);
4739 rt2800_init_bbp_3593(rt2x00dev
);
4743 rt2800_init_bbp_53xx(rt2x00dev
);
4746 rt2800_init_bbp_5592(rt2x00dev
);
4750 for (i
= 0; i
< EEPROM_BBP_SIZE
; i
++) {
4751 rt2800_eeprom_read_from_array(rt2x00dev
, EEPROM_BBP_START
, i
,
4754 if (eeprom
!= 0xffff && eeprom
!= 0x0000) {
4755 reg_id
= rt2x00_get_field16(eeprom
, EEPROM_BBP_REG_ID
);
4756 value
= rt2x00_get_field16(eeprom
, EEPROM_BBP_VALUE
);
4757 rt2800_bbp_write(rt2x00dev
, reg_id
, value
);
4762 static void rt2800_led_open_drain_enable(struct rt2x00_dev
*rt2x00dev
)
4766 rt2800_register_read(rt2x00dev
, OPT_14_CSR
, ®
);
4767 rt2x00_set_field32(®
, OPT_14_CSR_BIT0
, 1);
4768 rt2800_register_write(rt2x00dev
, OPT_14_CSR
, reg
);
4771 static u8
rt2800_init_rx_filter(struct rt2x00_dev
*rt2x00dev
, bool bw40
,
4780 u8 rfcsr24
= (bw40
) ? 0x27 : 0x07;
4782 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
4784 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
4785 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 2 * bw40
);
4786 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
4788 rt2800_rfcsr_read(rt2x00dev
, 31, &rfcsr
);
4789 rt2x00_set_field8(&rfcsr
, RFCSR31_RX_H20M
, bw40
);
4790 rt2800_rfcsr_write(rt2x00dev
, 31, rfcsr
);
4792 rt2800_rfcsr_read(rt2x00dev
, 22, &rfcsr
);
4793 rt2x00_set_field8(&rfcsr
, RFCSR22_BASEBAND_LOOPBACK
, 1);
4794 rt2800_rfcsr_write(rt2x00dev
, 22, rfcsr
);
4797 * Set power & frequency of passband test tone
4799 rt2800_bbp_write(rt2x00dev
, 24, 0);
4801 for (i
= 0; i
< 100; i
++) {
4802 rt2800_bbp_write(rt2x00dev
, 25, 0x90);
4805 rt2800_bbp_read(rt2x00dev
, 55, &passband
);
4811 * Set power & frequency of stopband test tone
4813 rt2800_bbp_write(rt2x00dev
, 24, 0x06);
4815 for (i
= 0; i
< 100; i
++) {
4816 rt2800_bbp_write(rt2x00dev
, 25, 0x90);
4819 rt2800_bbp_read(rt2x00dev
, 55, &stopband
);
4821 if ((passband
- stopband
) <= filter_target
) {
4823 overtuned
+= ((passband
- stopband
) == filter_target
);
4827 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
4830 rfcsr24
-= !!overtuned
;
4832 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
4836 static void rt2800_rf_init_calibration(struct rt2x00_dev
*rt2x00dev
,
4837 const unsigned int rf_reg
)
4841 rt2800_rfcsr_read(rt2x00dev
, rf_reg
, &rfcsr
);
4842 rt2x00_set_field8(&rfcsr
, FIELD8(0x80), 1);
4843 rt2800_rfcsr_write(rt2x00dev
, rf_reg
, rfcsr
);
4845 rt2x00_set_field8(&rfcsr
, FIELD8(0x80), 0);
4846 rt2800_rfcsr_write(rt2x00dev
, rf_reg
, rfcsr
);
4849 static void rt2800_rx_filter_calibration(struct rt2x00_dev
*rt2x00dev
)
4851 struct rt2800_drv_data
*drv_data
= rt2x00dev
->drv_data
;
4857 * TODO: sync filter_tgt values with vendor driver
4859 if (rt2x00_rt(rt2x00dev
, RT3070
)) {
4860 filter_tgt_bw20
= 0x16;
4861 filter_tgt_bw40
= 0x19;
4863 filter_tgt_bw20
= 0x13;
4864 filter_tgt_bw40
= 0x15;
4867 drv_data
->calibration_bw20
=
4868 rt2800_init_rx_filter(rt2x00dev
, false, filter_tgt_bw20
);
4869 drv_data
->calibration_bw40
=
4870 rt2800_init_rx_filter(rt2x00dev
, true, filter_tgt_bw40
);
4873 * Save BBP 25 & 26 values for later use in channel switching (for 3052)
4875 rt2800_bbp_read(rt2x00dev
, 25, &drv_data
->bbp25
);
4876 rt2800_bbp_read(rt2x00dev
, 26, &drv_data
->bbp26
);
4879 * Set back to initial state
4881 rt2800_bbp_write(rt2x00dev
, 24, 0);
4883 rt2800_rfcsr_read(rt2x00dev
, 22, &rfcsr
);
4884 rt2x00_set_field8(&rfcsr
, RFCSR22_BASEBAND_LOOPBACK
, 0);
4885 rt2800_rfcsr_write(rt2x00dev
, 22, rfcsr
);
4888 * Set BBP back to BW20
4890 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
4891 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 0);
4892 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
4895 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev
*rt2x00dev
)
4897 struct rt2800_drv_data
*drv_data
= rt2x00dev
->drv_data
;
4898 u8 min_gain
, rfcsr
, bbp
;
4901 rt2800_rfcsr_read(rt2x00dev
, 17, &rfcsr
);
4903 rt2x00_set_field8(&rfcsr
, RFCSR17_TX_LO1_EN
, 0);
4904 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
4905 rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
4906 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
) ||
4907 rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
)) {
4908 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG
, &rt2x00dev
->cap_flags
))
4909 rt2x00_set_field8(&rfcsr
, RFCSR17_R
, 1);
4912 min_gain
= rt2x00_rt(rt2x00dev
, RT3070
) ? 1 : 2;
4913 if (drv_data
->txmixer_gain_24g
>= min_gain
) {
4914 rt2x00_set_field8(&rfcsr
, RFCSR17_TXMIXER_GAIN
,
4915 drv_data
->txmixer_gain_24g
);
4918 rt2800_rfcsr_write(rt2x00dev
, 17, rfcsr
);
4920 if (rt2x00_rt(rt2x00dev
, RT3090
)) {
4921 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
4922 rt2800_bbp_read(rt2x00dev
, 138, &bbp
);
4923 rt2800_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &eeprom
);
4924 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
) == 1)
4925 rt2x00_set_field8(&bbp
, BBP138_RX_ADC1
, 0);
4926 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
) == 1)
4927 rt2x00_set_field8(&bbp
, BBP138_TX_DAC1
, 1);
4928 rt2800_bbp_write(rt2x00dev
, 138, bbp
);
4931 if (rt2x00_rt(rt2x00dev
, RT3070
)) {
4932 rt2800_rfcsr_read(rt2x00dev
, 27, &rfcsr
);
4933 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
))
4934 rt2x00_set_field8(&rfcsr
, RFCSR27_R1
, 3);
4936 rt2x00_set_field8(&rfcsr
, RFCSR27_R1
, 0);
4937 rt2x00_set_field8(&rfcsr
, RFCSR27_R2
, 0);
4938 rt2x00_set_field8(&rfcsr
, RFCSR27_R3
, 0);
4939 rt2x00_set_field8(&rfcsr
, RFCSR27_R4
, 0);
4940 rt2800_rfcsr_write(rt2x00dev
, 27, rfcsr
);
4941 } else if (rt2x00_rt(rt2x00dev
, RT3071
) ||
4942 rt2x00_rt(rt2x00dev
, RT3090
) ||
4943 rt2x00_rt(rt2x00dev
, RT3390
)) {
4944 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
4945 rt2x00_set_field8(&rfcsr
, RFCSR1_RF_BLOCK_EN
, 1);
4946 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 0);
4947 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 0);
4948 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 1);
4949 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 1);
4950 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
4952 rt2800_rfcsr_read(rt2x00dev
, 15, &rfcsr
);
4953 rt2x00_set_field8(&rfcsr
, RFCSR15_TX_LO2_EN
, 0);
4954 rt2800_rfcsr_write(rt2x00dev
, 15, rfcsr
);
4956 rt2800_rfcsr_read(rt2x00dev
, 20, &rfcsr
);
4957 rt2x00_set_field8(&rfcsr
, RFCSR20_RX_LO1_EN
, 0);
4958 rt2800_rfcsr_write(rt2x00dev
, 20, rfcsr
);
4960 rt2800_rfcsr_read(rt2x00dev
, 21, &rfcsr
);
4961 rt2x00_set_field8(&rfcsr
, RFCSR21_RX_LO2_EN
, 0);
4962 rt2800_rfcsr_write(rt2x00dev
, 21, rfcsr
);
4966 static void rt2800_normal_mode_setup_3593(struct rt2x00_dev
*rt2x00dev
)
4968 struct rt2800_drv_data
*drv_data
= rt2x00dev
->drv_data
;
4972 rt2800_rfcsr_read(rt2x00dev
, 50, &rfcsr
);
4973 rt2x00_set_field8(&rfcsr
, RFCSR50_TX_LO2_EN
, 0);
4974 rt2800_rfcsr_write(rt2x00dev
, 50, rfcsr
);
4976 rt2800_rfcsr_read(rt2x00dev
, 51, &rfcsr
);
4977 tx_gain
= rt2x00_get_field8(drv_data
->txmixer_gain_24g
,
4978 RFCSR17_TXMIXER_GAIN
);
4979 rt2x00_set_field8(&rfcsr
, RFCSR51_BITS24
, tx_gain
);
4980 rt2800_rfcsr_write(rt2x00dev
, 51, rfcsr
);
4982 rt2800_rfcsr_read(rt2x00dev
, 38, &rfcsr
);
4983 rt2x00_set_field8(&rfcsr
, RFCSR38_RX_LO1_EN
, 0);
4984 rt2800_rfcsr_write(rt2x00dev
, 38, rfcsr
);
4986 rt2800_rfcsr_read(rt2x00dev
, 39, &rfcsr
);
4987 rt2x00_set_field8(&rfcsr
, RFCSR39_RX_LO2_EN
, 0);
4988 rt2800_rfcsr_write(rt2x00dev
, 39, rfcsr
);
4990 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
4991 rt2x00_set_field8(&rfcsr
, RFCSR1_RF_BLOCK_EN
, 1);
4992 rt2x00_set_field8(&rfcsr
, RFCSR1_PLL_PD
, 1);
4993 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
4995 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
4996 rt2x00_set_field8(&rfcsr
, RFCSR30_RX_VCM
, 2);
4997 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
4999 /* TODO: enable stream mode */
5002 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev
*rt2x00dev
)
5007 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
5008 rt2800_bbp_read(rt2x00dev
, 138, ®
);
5009 rt2800_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &eeprom
);
5010 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
) == 1)
5011 rt2x00_set_field8(®
, BBP138_RX_ADC1
, 0);
5012 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
) == 1)
5013 rt2x00_set_field8(®
, BBP138_TX_DAC1
, 1);
5014 rt2800_bbp_write(rt2x00dev
, 138, reg
);
5016 rt2800_rfcsr_read(rt2x00dev
, 38, ®
);
5017 rt2x00_set_field8(®
, RFCSR38_RX_LO1_EN
, 0);
5018 rt2800_rfcsr_write(rt2x00dev
, 38, reg
);
5020 rt2800_rfcsr_read(rt2x00dev
, 39, ®
);
5021 rt2x00_set_field8(®
, RFCSR39_RX_LO2_EN
, 0);
5022 rt2800_rfcsr_write(rt2x00dev
, 39, reg
);
5024 rt2800_bbp4_mac_if_ctrl(rt2x00dev
);
5026 rt2800_rfcsr_read(rt2x00dev
, 30, ®
);
5027 rt2x00_set_field8(®
, RFCSR30_RX_VCM
, 2);
5028 rt2800_rfcsr_write(rt2x00dev
, 30, reg
);
5031 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev
*rt2x00dev
)
5033 rt2800_rf_init_calibration(rt2x00dev
, 30);
5035 rt2800_rfcsr_write(rt2x00dev
, 0, 0x50);
5036 rt2800_rfcsr_write(rt2x00dev
, 1, 0x01);
5037 rt2800_rfcsr_write(rt2x00dev
, 2, 0xf7);
5038 rt2800_rfcsr_write(rt2x00dev
, 3, 0x75);
5039 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
5040 rt2800_rfcsr_write(rt2x00dev
, 5, 0x03);
5041 rt2800_rfcsr_write(rt2x00dev
, 6, 0x02);
5042 rt2800_rfcsr_write(rt2x00dev
, 7, 0x50);
5043 rt2800_rfcsr_write(rt2x00dev
, 8, 0x39);
5044 rt2800_rfcsr_write(rt2x00dev
, 9, 0x0f);
5045 rt2800_rfcsr_write(rt2x00dev
, 10, 0x60);
5046 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
5047 rt2800_rfcsr_write(rt2x00dev
, 12, 0x75);
5048 rt2800_rfcsr_write(rt2x00dev
, 13, 0x75);
5049 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
5050 rt2800_rfcsr_write(rt2x00dev
, 15, 0x58);
5051 rt2800_rfcsr_write(rt2x00dev
, 16, 0xb3);
5052 rt2800_rfcsr_write(rt2x00dev
, 17, 0x92);
5053 rt2800_rfcsr_write(rt2x00dev
, 18, 0x2c);
5054 rt2800_rfcsr_write(rt2x00dev
, 19, 0x02);
5055 rt2800_rfcsr_write(rt2x00dev
, 20, 0xba);
5056 rt2800_rfcsr_write(rt2x00dev
, 21, 0xdb);
5057 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
5058 rt2800_rfcsr_write(rt2x00dev
, 23, 0x31);
5059 rt2800_rfcsr_write(rt2x00dev
, 24, 0x08);
5060 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
5061 rt2800_rfcsr_write(rt2x00dev
, 26, 0x25);
5062 rt2800_rfcsr_write(rt2x00dev
, 27, 0x23);
5063 rt2800_rfcsr_write(rt2x00dev
, 28, 0x13);
5064 rt2800_rfcsr_write(rt2x00dev
, 29, 0x83);
5065 rt2800_rfcsr_write(rt2x00dev
, 30, 0x00);
5066 rt2800_rfcsr_write(rt2x00dev
, 31, 0x00);
5069 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev
*rt2x00dev
)
5075 /* XXX vendor driver do this only for 3070 */
5076 rt2800_rf_init_calibration(rt2x00dev
, 30);
5078 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
5079 rt2800_rfcsr_write(rt2x00dev
, 5, 0x03);
5080 rt2800_rfcsr_write(rt2x00dev
, 6, 0x02);
5081 rt2800_rfcsr_write(rt2x00dev
, 7, 0x60);
5082 rt2800_rfcsr_write(rt2x00dev
, 9, 0x0f);
5083 rt2800_rfcsr_write(rt2x00dev
, 10, 0x41);
5084 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
5085 rt2800_rfcsr_write(rt2x00dev
, 12, 0x7b);
5086 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
5087 rt2800_rfcsr_write(rt2x00dev
, 15, 0x58);
5088 rt2800_rfcsr_write(rt2x00dev
, 16, 0xb3);
5089 rt2800_rfcsr_write(rt2x00dev
, 17, 0x92);
5090 rt2800_rfcsr_write(rt2x00dev
, 18, 0x2c);
5091 rt2800_rfcsr_write(rt2x00dev
, 19, 0x02);
5092 rt2800_rfcsr_write(rt2x00dev
, 20, 0xba);
5093 rt2800_rfcsr_write(rt2x00dev
, 21, 0xdb);
5094 rt2800_rfcsr_write(rt2x00dev
, 24, 0x16);
5095 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
5096 rt2800_rfcsr_write(rt2x00dev
, 29, 0x1f);
5098 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
)) {
5099 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
5100 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
5101 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
5102 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
5103 } else if (rt2x00_rt(rt2x00dev
, RT3071
) ||
5104 rt2x00_rt(rt2x00dev
, RT3090
)) {
5105 rt2800_rfcsr_write(rt2x00dev
, 31, 0x14);
5107 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
5108 rt2x00_set_field8(&rfcsr
, RFCSR6_R2
, 1);
5109 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
5111 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
5112 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
5113 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
5114 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
)) {
5115 rt2800_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
,
5117 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_DAC_TEST
))
5118 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
5120 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 0);
5122 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
5124 rt2800_register_read(rt2x00dev
, GPIO_SWITCH
, ®
);
5125 rt2x00_set_field32(®
, GPIO_SWITCH_5
, 0);
5126 rt2800_register_write(rt2x00dev
, GPIO_SWITCH
, reg
);
5129 rt2800_rx_filter_calibration(rt2x00dev
);
5131 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
) ||
5132 rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
5133 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
))
5134 rt2800_rfcsr_write(rt2x00dev
, 27, 0x03);
5136 rt2800_led_open_drain_enable(rt2x00dev
);
5137 rt2800_normal_mode_setup_3xxx(rt2x00dev
);
5140 static void rt2800_init_rfcsr_3290(struct rt2x00_dev
*rt2x00dev
)
5144 rt2800_rf_init_calibration(rt2x00dev
, 2);
5146 rt2800_rfcsr_write(rt2x00dev
, 1, 0x0f);
5147 rt2800_rfcsr_write(rt2x00dev
, 2, 0x80);
5148 rt2800_rfcsr_write(rt2x00dev
, 3, 0x08);
5149 rt2800_rfcsr_write(rt2x00dev
, 4, 0x00);
5150 rt2800_rfcsr_write(rt2x00dev
, 6, 0xa0);
5151 rt2800_rfcsr_write(rt2x00dev
, 8, 0xf3);
5152 rt2800_rfcsr_write(rt2x00dev
, 9, 0x02);
5153 rt2800_rfcsr_write(rt2x00dev
, 10, 0x53);
5154 rt2800_rfcsr_write(rt2x00dev
, 11, 0x4a);
5155 rt2800_rfcsr_write(rt2x00dev
, 12, 0x46);
5156 rt2800_rfcsr_write(rt2x00dev
, 13, 0x9f);
5157 rt2800_rfcsr_write(rt2x00dev
, 18, 0x02);
5158 rt2800_rfcsr_write(rt2x00dev
, 22, 0x20);
5159 rt2800_rfcsr_write(rt2x00dev
, 25, 0x83);
5160 rt2800_rfcsr_write(rt2x00dev
, 26, 0x82);
5161 rt2800_rfcsr_write(rt2x00dev
, 27, 0x09);
5162 rt2800_rfcsr_write(rt2x00dev
, 29, 0x10);
5163 rt2800_rfcsr_write(rt2x00dev
, 30, 0x10);
5164 rt2800_rfcsr_write(rt2x00dev
, 31, 0x80);
5165 rt2800_rfcsr_write(rt2x00dev
, 32, 0x80);
5166 rt2800_rfcsr_write(rt2x00dev
, 33, 0x00);
5167 rt2800_rfcsr_write(rt2x00dev
, 34, 0x05);
5168 rt2800_rfcsr_write(rt2x00dev
, 35, 0x12);
5169 rt2800_rfcsr_write(rt2x00dev
, 36, 0x00);
5170 rt2800_rfcsr_write(rt2x00dev
, 38, 0x85);
5171 rt2800_rfcsr_write(rt2x00dev
, 39, 0x1b);
5172 rt2800_rfcsr_write(rt2x00dev
, 40, 0x0b);
5173 rt2800_rfcsr_write(rt2x00dev
, 41, 0xbb);
5174 rt2800_rfcsr_write(rt2x00dev
, 42, 0xd5);
5175 rt2800_rfcsr_write(rt2x00dev
, 43, 0x7b);
5176 rt2800_rfcsr_write(rt2x00dev
, 44, 0x0e);
5177 rt2800_rfcsr_write(rt2x00dev
, 45, 0xa2);
5178 rt2800_rfcsr_write(rt2x00dev
, 46, 0x73);
5179 rt2800_rfcsr_write(rt2x00dev
, 47, 0x00);
5180 rt2800_rfcsr_write(rt2x00dev
, 48, 0x10);
5181 rt2800_rfcsr_write(rt2x00dev
, 49, 0x98);
5182 rt2800_rfcsr_write(rt2x00dev
, 52, 0x38);
5183 rt2800_rfcsr_write(rt2x00dev
, 53, 0x00);
5184 rt2800_rfcsr_write(rt2x00dev
, 54, 0x78);
5185 rt2800_rfcsr_write(rt2x00dev
, 55, 0x43);
5186 rt2800_rfcsr_write(rt2x00dev
, 56, 0x02);
5187 rt2800_rfcsr_write(rt2x00dev
, 57, 0x80);
5188 rt2800_rfcsr_write(rt2x00dev
, 58, 0x7f);
5189 rt2800_rfcsr_write(rt2x00dev
, 59, 0x09);
5190 rt2800_rfcsr_write(rt2x00dev
, 60, 0x45);
5191 rt2800_rfcsr_write(rt2x00dev
, 61, 0xc1);
5193 rt2800_rfcsr_read(rt2x00dev
, 29, &rfcsr
);
5194 rt2x00_set_field8(&rfcsr
, RFCSR29_RSSI_GAIN
, 3);
5195 rt2800_rfcsr_write(rt2x00dev
, 29, rfcsr
);
5197 rt2800_led_open_drain_enable(rt2x00dev
);
5198 rt2800_normal_mode_setup_3xxx(rt2x00dev
);
5201 static void rt2800_init_rfcsr_3352(struct rt2x00_dev
*rt2x00dev
)
5203 rt2800_rf_init_calibration(rt2x00dev
, 30);
5205 rt2800_rfcsr_write(rt2x00dev
, 0, 0xf0);
5206 rt2800_rfcsr_write(rt2x00dev
, 1, 0x23);
5207 rt2800_rfcsr_write(rt2x00dev
, 2, 0x50);
5208 rt2800_rfcsr_write(rt2x00dev
, 3, 0x18);
5209 rt2800_rfcsr_write(rt2x00dev
, 4, 0x00);
5210 rt2800_rfcsr_write(rt2x00dev
, 5, 0x00);
5211 rt2800_rfcsr_write(rt2x00dev
, 6, 0x33);
5212 rt2800_rfcsr_write(rt2x00dev
, 7, 0x00);
5213 rt2800_rfcsr_write(rt2x00dev
, 8, 0xf1);
5214 rt2800_rfcsr_write(rt2x00dev
, 9, 0x02);
5215 rt2800_rfcsr_write(rt2x00dev
, 10, 0xd2);
5216 rt2800_rfcsr_write(rt2x00dev
, 11, 0x42);
5217 rt2800_rfcsr_write(rt2x00dev
, 12, 0x1c);
5218 rt2800_rfcsr_write(rt2x00dev
, 13, 0x00);
5219 rt2800_rfcsr_write(rt2x00dev
, 14, 0x5a);
5220 rt2800_rfcsr_write(rt2x00dev
, 15, 0x00);
5221 rt2800_rfcsr_write(rt2x00dev
, 16, 0x01);
5222 rt2800_rfcsr_write(rt2x00dev
, 18, 0x45);
5223 rt2800_rfcsr_write(rt2x00dev
, 19, 0x02);
5224 rt2800_rfcsr_write(rt2x00dev
, 20, 0x00);
5225 rt2800_rfcsr_write(rt2x00dev
, 21, 0x00);
5226 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
5227 rt2800_rfcsr_write(rt2x00dev
, 23, 0x00);
5228 rt2800_rfcsr_write(rt2x00dev
, 24, 0x00);
5229 rt2800_rfcsr_write(rt2x00dev
, 25, 0x80);
5230 rt2800_rfcsr_write(rt2x00dev
, 26, 0x00);
5231 rt2800_rfcsr_write(rt2x00dev
, 27, 0x03);
5232 rt2800_rfcsr_write(rt2x00dev
, 28, 0x03);
5233 rt2800_rfcsr_write(rt2x00dev
, 29, 0x00);
5234 rt2800_rfcsr_write(rt2x00dev
, 30, 0x10);
5235 rt2800_rfcsr_write(rt2x00dev
, 31, 0x80);
5236 rt2800_rfcsr_write(rt2x00dev
, 32, 0x80);
5237 rt2800_rfcsr_write(rt2x00dev
, 33, 0x00);
5238 rt2800_rfcsr_write(rt2x00dev
, 34, 0x01);
5239 rt2800_rfcsr_write(rt2x00dev
, 35, 0x03);
5240 rt2800_rfcsr_write(rt2x00dev
, 36, 0xbd);
5241 rt2800_rfcsr_write(rt2x00dev
, 37, 0x3c);
5242 rt2800_rfcsr_write(rt2x00dev
, 38, 0x5f);
5243 rt2800_rfcsr_write(rt2x00dev
, 39, 0xc5);
5244 rt2800_rfcsr_write(rt2x00dev
, 40, 0x33);
5245 rt2800_rfcsr_write(rt2x00dev
, 41, 0x5b);
5246 rt2800_rfcsr_write(rt2x00dev
, 42, 0x5b);
5247 rt2800_rfcsr_write(rt2x00dev
, 43, 0xdb);
5248 rt2800_rfcsr_write(rt2x00dev
, 44, 0xdb);
5249 rt2800_rfcsr_write(rt2x00dev
, 45, 0xdb);
5250 rt2800_rfcsr_write(rt2x00dev
, 46, 0xdd);
5251 rt2800_rfcsr_write(rt2x00dev
, 47, 0x0d);
5252 rt2800_rfcsr_write(rt2x00dev
, 48, 0x14);
5253 rt2800_rfcsr_write(rt2x00dev
, 49, 0x00);
5254 rt2800_rfcsr_write(rt2x00dev
, 50, 0x2d);
5255 rt2800_rfcsr_write(rt2x00dev
, 51, 0x7f);
5256 rt2800_rfcsr_write(rt2x00dev
, 52, 0x00);
5257 rt2800_rfcsr_write(rt2x00dev
, 53, 0x52);
5258 rt2800_rfcsr_write(rt2x00dev
, 54, 0x1b);
5259 rt2800_rfcsr_write(rt2x00dev
, 55, 0x7f);
5260 rt2800_rfcsr_write(rt2x00dev
, 56, 0x00);
5261 rt2800_rfcsr_write(rt2x00dev
, 57, 0x52);
5262 rt2800_rfcsr_write(rt2x00dev
, 58, 0x1b);
5263 rt2800_rfcsr_write(rt2x00dev
, 59, 0x00);
5264 rt2800_rfcsr_write(rt2x00dev
, 60, 0x00);
5265 rt2800_rfcsr_write(rt2x00dev
, 61, 0x00);
5266 rt2800_rfcsr_write(rt2x00dev
, 62, 0x00);
5267 rt2800_rfcsr_write(rt2x00dev
, 63, 0x00);
5269 rt2800_rx_filter_calibration(rt2x00dev
);
5270 rt2800_led_open_drain_enable(rt2x00dev
);
5271 rt2800_normal_mode_setup_3xxx(rt2x00dev
);
5274 static void rt2800_init_rfcsr_3390(struct rt2x00_dev
*rt2x00dev
)
5278 rt2800_rf_init_calibration(rt2x00dev
, 30);
5280 rt2800_rfcsr_write(rt2x00dev
, 0, 0xa0);
5281 rt2800_rfcsr_write(rt2x00dev
, 1, 0xe1);
5282 rt2800_rfcsr_write(rt2x00dev
, 2, 0xf1);
5283 rt2800_rfcsr_write(rt2x00dev
, 3, 0x62);
5284 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
5285 rt2800_rfcsr_write(rt2x00dev
, 5, 0x8b);
5286 rt2800_rfcsr_write(rt2x00dev
, 6, 0x42);
5287 rt2800_rfcsr_write(rt2x00dev
, 7, 0x34);
5288 rt2800_rfcsr_write(rt2x00dev
, 8, 0x00);
5289 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc0);
5290 rt2800_rfcsr_write(rt2x00dev
, 10, 0x61);
5291 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
5292 rt2800_rfcsr_write(rt2x00dev
, 12, 0x3b);
5293 rt2800_rfcsr_write(rt2x00dev
, 13, 0xe0);
5294 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
5295 rt2800_rfcsr_write(rt2x00dev
, 15, 0x53);
5296 rt2800_rfcsr_write(rt2x00dev
, 16, 0xe0);
5297 rt2800_rfcsr_write(rt2x00dev
, 17, 0x94);
5298 rt2800_rfcsr_write(rt2x00dev
, 18, 0x5c);
5299 rt2800_rfcsr_write(rt2x00dev
, 19, 0x4a);
5300 rt2800_rfcsr_write(rt2x00dev
, 20, 0xb2);
5301 rt2800_rfcsr_write(rt2x00dev
, 21, 0xf6);
5302 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
5303 rt2800_rfcsr_write(rt2x00dev
, 23, 0x14);
5304 rt2800_rfcsr_write(rt2x00dev
, 24, 0x08);
5305 rt2800_rfcsr_write(rt2x00dev
, 25, 0x3d);
5306 rt2800_rfcsr_write(rt2x00dev
, 26, 0x85);
5307 rt2800_rfcsr_write(rt2x00dev
, 27, 0x00);
5308 rt2800_rfcsr_write(rt2x00dev
, 28, 0x41);
5309 rt2800_rfcsr_write(rt2x00dev
, 29, 0x8f);
5310 rt2800_rfcsr_write(rt2x00dev
, 30, 0x20);
5311 rt2800_rfcsr_write(rt2x00dev
, 31, 0x0f);
5313 rt2800_register_read(rt2x00dev
, GPIO_SWITCH
, ®
);
5314 rt2x00_set_field32(®
, GPIO_SWITCH_5
, 0);
5315 rt2800_register_write(rt2x00dev
, GPIO_SWITCH
, reg
);
5317 rt2800_rx_filter_calibration(rt2x00dev
);
5319 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
))
5320 rt2800_rfcsr_write(rt2x00dev
, 27, 0x03);
5322 rt2800_led_open_drain_enable(rt2x00dev
);
5323 rt2800_normal_mode_setup_3xxx(rt2x00dev
);
5326 static void rt2800_init_rfcsr_3572(struct rt2x00_dev
*rt2x00dev
)
5331 rt2800_rf_init_calibration(rt2x00dev
, 30);
5333 rt2800_rfcsr_write(rt2x00dev
, 0, 0x70);
5334 rt2800_rfcsr_write(rt2x00dev
, 1, 0x81);
5335 rt2800_rfcsr_write(rt2x00dev
, 2, 0xf1);
5336 rt2800_rfcsr_write(rt2x00dev
, 3, 0x02);
5337 rt2800_rfcsr_write(rt2x00dev
, 4, 0x4c);
5338 rt2800_rfcsr_write(rt2x00dev
, 5, 0x05);
5339 rt2800_rfcsr_write(rt2x00dev
, 6, 0x4a);
5340 rt2800_rfcsr_write(rt2x00dev
, 7, 0xd8);
5341 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc3);
5342 rt2800_rfcsr_write(rt2x00dev
, 10, 0xf1);
5343 rt2800_rfcsr_write(rt2x00dev
, 11, 0xb9);
5344 rt2800_rfcsr_write(rt2x00dev
, 12, 0x70);
5345 rt2800_rfcsr_write(rt2x00dev
, 13, 0x65);
5346 rt2800_rfcsr_write(rt2x00dev
, 14, 0xa0);
5347 rt2800_rfcsr_write(rt2x00dev
, 15, 0x53);
5348 rt2800_rfcsr_write(rt2x00dev
, 16, 0x4c);
5349 rt2800_rfcsr_write(rt2x00dev
, 17, 0x23);
5350 rt2800_rfcsr_write(rt2x00dev
, 18, 0xac);
5351 rt2800_rfcsr_write(rt2x00dev
, 19, 0x93);
5352 rt2800_rfcsr_write(rt2x00dev
, 20, 0xb3);
5353 rt2800_rfcsr_write(rt2x00dev
, 21, 0xd0);
5354 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
5355 rt2800_rfcsr_write(rt2x00dev
, 23, 0x3c);
5356 rt2800_rfcsr_write(rt2x00dev
, 24, 0x16);
5357 rt2800_rfcsr_write(rt2x00dev
, 25, 0x15);
5358 rt2800_rfcsr_write(rt2x00dev
, 26, 0x85);
5359 rt2800_rfcsr_write(rt2x00dev
, 27, 0x00);
5360 rt2800_rfcsr_write(rt2x00dev
, 28, 0x00);
5361 rt2800_rfcsr_write(rt2x00dev
, 29, 0x9b);
5362 rt2800_rfcsr_write(rt2x00dev
, 30, 0x09);
5363 rt2800_rfcsr_write(rt2x00dev
, 31, 0x10);
5365 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
5366 rt2x00_set_field8(&rfcsr
, RFCSR6_R2
, 1);
5367 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
5369 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
5370 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
5371 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
5372 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
5374 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
5375 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 0);
5376 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
5377 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
5379 rt2800_rx_filter_calibration(rt2x00dev
);
5380 rt2800_led_open_drain_enable(rt2x00dev
);
5381 rt2800_normal_mode_setup_3xxx(rt2x00dev
);
5384 static void rt2800_init_rfcsr_3593(struct rt2x00_dev
*rt2x00dev
)
5386 struct rt2800_drv_data
*drv_data
= rt2x00dev
->drv_data
;
5390 /* Disable GPIO #4 and #7 function for LAN PE control */
5391 rt2800_register_read(rt2x00dev
, GPIO_SWITCH
, ®
);
5392 rt2x00_set_field32(®
, GPIO_SWITCH_4
, 0);
5393 rt2x00_set_field32(®
, GPIO_SWITCH_7
, 0);
5394 rt2800_register_write(rt2x00dev
, GPIO_SWITCH
, reg
);
5396 /* Initialize default register values */
5397 rt2800_rfcsr_write(rt2x00dev
, 1, 0x03);
5398 rt2800_rfcsr_write(rt2x00dev
, 3, 0x80);
5399 rt2800_rfcsr_write(rt2x00dev
, 5, 0x00);
5400 rt2800_rfcsr_write(rt2x00dev
, 6, 0x40);
5401 rt2800_rfcsr_write(rt2x00dev
, 8, 0xf1);
5402 rt2800_rfcsr_write(rt2x00dev
, 9, 0x02);
5403 rt2800_rfcsr_write(rt2x00dev
, 10, 0xd3);
5404 rt2800_rfcsr_write(rt2x00dev
, 11, 0x40);
5405 rt2800_rfcsr_write(rt2x00dev
, 12, 0x4e);
5406 rt2800_rfcsr_write(rt2x00dev
, 13, 0x12);
5407 rt2800_rfcsr_write(rt2x00dev
, 18, 0x40);
5408 rt2800_rfcsr_write(rt2x00dev
, 22, 0x20);
5409 rt2800_rfcsr_write(rt2x00dev
, 30, 0x10);
5410 rt2800_rfcsr_write(rt2x00dev
, 31, 0x80);
5411 rt2800_rfcsr_write(rt2x00dev
, 32, 0x78);
5412 rt2800_rfcsr_write(rt2x00dev
, 33, 0x3b);
5413 rt2800_rfcsr_write(rt2x00dev
, 34, 0x3c);
5414 rt2800_rfcsr_write(rt2x00dev
, 35, 0xe0);
5415 rt2800_rfcsr_write(rt2x00dev
, 38, 0x86);
5416 rt2800_rfcsr_write(rt2x00dev
, 39, 0x23);
5417 rt2800_rfcsr_write(rt2x00dev
, 44, 0xd3);
5418 rt2800_rfcsr_write(rt2x00dev
, 45, 0xbb);
5419 rt2800_rfcsr_write(rt2x00dev
, 46, 0x60);
5420 rt2800_rfcsr_write(rt2x00dev
, 49, 0x8e);
5421 rt2800_rfcsr_write(rt2x00dev
, 50, 0x86);
5422 rt2800_rfcsr_write(rt2x00dev
, 51, 0x75);
5423 rt2800_rfcsr_write(rt2x00dev
, 52, 0x45);
5424 rt2800_rfcsr_write(rt2x00dev
, 53, 0x18);
5425 rt2800_rfcsr_write(rt2x00dev
, 54, 0x18);
5426 rt2800_rfcsr_write(rt2x00dev
, 55, 0x18);
5427 rt2800_rfcsr_write(rt2x00dev
, 56, 0xdb);
5428 rt2800_rfcsr_write(rt2x00dev
, 57, 0x6e);
5430 /* Initiate calibration */
5431 /* TODO: use rt2800_rf_init_calibration ? */
5432 rt2800_rfcsr_read(rt2x00dev
, 2, &rfcsr
);
5433 rt2x00_set_field8(&rfcsr
, RFCSR2_RESCAL_EN
, 1);
5434 rt2800_rfcsr_write(rt2x00dev
, 2, rfcsr
);
5436 rt2800_adjust_freq_offset(rt2x00dev
);
5438 rt2800_rfcsr_read(rt2x00dev
, 18, &rfcsr
);
5439 rt2x00_set_field8(&rfcsr
, RFCSR18_XO_TUNE_BYPASS
, 1);
5440 rt2800_rfcsr_write(rt2x00dev
, 18, rfcsr
);
5442 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
5443 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
5444 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
5445 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
5446 usleep_range(1000, 1500);
5447 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
5448 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 0);
5449 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
5451 /* Set initial values for RX filter calibration */
5452 drv_data
->calibration_bw20
= 0x1f;
5453 drv_data
->calibration_bw40
= 0x2f;
5455 /* Save BBP 25 & 26 values for later use in channel switching */
5456 rt2800_bbp_read(rt2x00dev
, 25, &drv_data
->bbp25
);
5457 rt2800_bbp_read(rt2x00dev
, 26, &drv_data
->bbp26
);
5459 rt2800_led_open_drain_enable(rt2x00dev
);
5460 rt2800_normal_mode_setup_3593(rt2x00dev
);
5462 /* TODO: post BBP initialization */
5464 /* TODO: enable stream mode support */
5467 static void rt2800_init_rfcsr_5390(struct rt2x00_dev
*rt2x00dev
)
5469 rt2800_rf_init_calibration(rt2x00dev
, 2);
5471 rt2800_rfcsr_write(rt2x00dev
, 1, 0x0f);
5472 rt2800_rfcsr_write(rt2x00dev
, 2, 0x80);
5473 rt2800_rfcsr_write(rt2x00dev
, 3, 0x88);
5474 rt2800_rfcsr_write(rt2x00dev
, 5, 0x10);
5475 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
5476 rt2800_rfcsr_write(rt2x00dev
, 6, 0xe0);
5478 rt2800_rfcsr_write(rt2x00dev
, 6, 0xa0);
5479 rt2800_rfcsr_write(rt2x00dev
, 7, 0x00);
5480 rt2800_rfcsr_write(rt2x00dev
, 10, 0x53);
5481 rt2800_rfcsr_write(rt2x00dev
, 11, 0x4a);
5482 rt2800_rfcsr_write(rt2x00dev
, 12, 0xc6);
5483 rt2800_rfcsr_write(rt2x00dev
, 13, 0x9f);
5484 rt2800_rfcsr_write(rt2x00dev
, 14, 0x00);
5485 rt2800_rfcsr_write(rt2x00dev
, 15, 0x00);
5486 rt2800_rfcsr_write(rt2x00dev
, 16, 0x00);
5487 rt2800_rfcsr_write(rt2x00dev
, 18, 0x03);
5488 rt2800_rfcsr_write(rt2x00dev
, 19, 0x00);
5490 rt2800_rfcsr_write(rt2x00dev
, 20, 0x00);
5491 rt2800_rfcsr_write(rt2x00dev
, 21, 0x00);
5492 rt2800_rfcsr_write(rt2x00dev
, 22, 0x20);
5493 rt2800_rfcsr_write(rt2x00dev
, 23, 0x00);
5494 rt2800_rfcsr_write(rt2x00dev
, 24, 0x00);
5495 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
5496 rt2800_rfcsr_write(rt2x00dev
, 25, 0x80);
5498 rt2800_rfcsr_write(rt2x00dev
, 25, 0xc0);
5499 rt2800_rfcsr_write(rt2x00dev
, 26, 0x00);
5500 rt2800_rfcsr_write(rt2x00dev
, 27, 0x09);
5501 rt2800_rfcsr_write(rt2x00dev
, 28, 0x00);
5502 rt2800_rfcsr_write(rt2x00dev
, 29, 0x10);
5504 rt2800_rfcsr_write(rt2x00dev
, 30, 0x00);
5505 rt2800_rfcsr_write(rt2x00dev
, 31, 0x80);
5506 rt2800_rfcsr_write(rt2x00dev
, 32, 0x80);
5507 rt2800_rfcsr_write(rt2x00dev
, 33, 0x00);
5508 rt2800_rfcsr_write(rt2x00dev
, 34, 0x07);
5509 rt2800_rfcsr_write(rt2x00dev
, 35, 0x12);
5510 rt2800_rfcsr_write(rt2x00dev
, 36, 0x00);
5511 rt2800_rfcsr_write(rt2x00dev
, 37, 0x08);
5512 rt2800_rfcsr_write(rt2x00dev
, 38, 0x85);
5513 rt2800_rfcsr_write(rt2x00dev
, 39, 0x1b);
5515 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
5516 rt2800_rfcsr_write(rt2x00dev
, 40, 0x0b);
5518 rt2800_rfcsr_write(rt2x00dev
, 40, 0x4b);
5519 rt2800_rfcsr_write(rt2x00dev
, 41, 0xbb);
5520 rt2800_rfcsr_write(rt2x00dev
, 42, 0xd2);
5521 rt2800_rfcsr_write(rt2x00dev
, 43, 0x9a);
5522 rt2800_rfcsr_write(rt2x00dev
, 44, 0x0e);
5523 rt2800_rfcsr_write(rt2x00dev
, 45, 0xa2);
5524 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
5525 rt2800_rfcsr_write(rt2x00dev
, 46, 0x73);
5527 rt2800_rfcsr_write(rt2x00dev
, 46, 0x7b);
5528 rt2800_rfcsr_write(rt2x00dev
, 47, 0x00);
5529 rt2800_rfcsr_write(rt2x00dev
, 48, 0x10);
5530 rt2800_rfcsr_write(rt2x00dev
, 49, 0x94);
5532 rt2800_rfcsr_write(rt2x00dev
, 52, 0x38);
5533 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
5534 rt2800_rfcsr_write(rt2x00dev
, 53, 0x00);
5536 rt2800_rfcsr_write(rt2x00dev
, 53, 0x84);
5537 rt2800_rfcsr_write(rt2x00dev
, 54, 0x78);
5538 rt2800_rfcsr_write(rt2x00dev
, 55, 0x44);
5539 rt2800_rfcsr_write(rt2x00dev
, 56, 0x22);
5540 rt2800_rfcsr_write(rt2x00dev
, 57, 0x80);
5541 rt2800_rfcsr_write(rt2x00dev
, 58, 0x7f);
5542 rt2800_rfcsr_write(rt2x00dev
, 59, 0x63);
5544 rt2800_rfcsr_write(rt2x00dev
, 60, 0x45);
5545 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390F
))
5546 rt2800_rfcsr_write(rt2x00dev
, 61, 0xd1);
5548 rt2800_rfcsr_write(rt2x00dev
, 61, 0xdd);
5549 rt2800_rfcsr_write(rt2x00dev
, 62, 0x00);
5550 rt2800_rfcsr_write(rt2x00dev
, 63, 0x00);
5552 rt2800_normal_mode_setup_5xxx(rt2x00dev
);
5554 rt2800_led_open_drain_enable(rt2x00dev
);
5557 static void rt2800_init_rfcsr_5392(struct rt2x00_dev
*rt2x00dev
)
5559 rt2800_rf_init_calibration(rt2x00dev
, 2);
5561 rt2800_rfcsr_write(rt2x00dev
, 1, 0x17);
5562 rt2800_rfcsr_write(rt2x00dev
, 2, 0x80);
5563 rt2800_rfcsr_write(rt2x00dev
, 3, 0x88);
5564 rt2800_rfcsr_write(rt2x00dev
, 5, 0x10);
5565 rt2800_rfcsr_write(rt2x00dev
, 6, 0xe0);
5566 rt2800_rfcsr_write(rt2x00dev
, 7, 0x00);
5567 rt2800_rfcsr_write(rt2x00dev
, 10, 0x53);
5568 rt2800_rfcsr_write(rt2x00dev
, 11, 0x4a);
5569 rt2800_rfcsr_write(rt2x00dev
, 12, 0x46);
5570 rt2800_rfcsr_write(rt2x00dev
, 13, 0x9f);
5571 rt2800_rfcsr_write(rt2x00dev
, 14, 0x00);
5572 rt2800_rfcsr_write(rt2x00dev
, 15, 0x00);
5573 rt2800_rfcsr_write(rt2x00dev
, 16, 0x00);
5574 rt2800_rfcsr_write(rt2x00dev
, 18, 0x03);
5575 rt2800_rfcsr_write(rt2x00dev
, 19, 0x4d);
5576 rt2800_rfcsr_write(rt2x00dev
, 20, 0x00);
5577 rt2800_rfcsr_write(rt2x00dev
, 21, 0x8d);
5578 rt2800_rfcsr_write(rt2x00dev
, 22, 0x20);
5579 rt2800_rfcsr_write(rt2x00dev
, 23, 0x0b);
5580 rt2800_rfcsr_write(rt2x00dev
, 24, 0x44);
5581 rt2800_rfcsr_write(rt2x00dev
, 25, 0x80);
5582 rt2800_rfcsr_write(rt2x00dev
, 26, 0x82);
5583 rt2800_rfcsr_write(rt2x00dev
, 27, 0x09);
5584 rt2800_rfcsr_write(rt2x00dev
, 28, 0x00);
5585 rt2800_rfcsr_write(rt2x00dev
, 29, 0x10);
5586 rt2800_rfcsr_write(rt2x00dev
, 30, 0x10);
5587 rt2800_rfcsr_write(rt2x00dev
, 31, 0x80);
5588 rt2800_rfcsr_write(rt2x00dev
, 32, 0x20);
5589 rt2800_rfcsr_write(rt2x00dev
, 33, 0xC0);
5590 rt2800_rfcsr_write(rt2x00dev
, 34, 0x07);
5591 rt2800_rfcsr_write(rt2x00dev
, 35, 0x12);
5592 rt2800_rfcsr_write(rt2x00dev
, 36, 0x00);
5593 rt2800_rfcsr_write(rt2x00dev
, 37, 0x08);
5594 rt2800_rfcsr_write(rt2x00dev
, 38, 0x89);
5595 rt2800_rfcsr_write(rt2x00dev
, 39, 0x1b);
5596 rt2800_rfcsr_write(rt2x00dev
, 40, 0x0f);
5597 rt2800_rfcsr_write(rt2x00dev
, 41, 0xbb);
5598 rt2800_rfcsr_write(rt2x00dev
, 42, 0xd5);
5599 rt2800_rfcsr_write(rt2x00dev
, 43, 0x9b);
5600 rt2800_rfcsr_write(rt2x00dev
, 44, 0x0e);
5601 rt2800_rfcsr_write(rt2x00dev
, 45, 0xa2);
5602 rt2800_rfcsr_write(rt2x00dev
, 46, 0x73);
5603 rt2800_rfcsr_write(rt2x00dev
, 47, 0x0c);
5604 rt2800_rfcsr_write(rt2x00dev
, 48, 0x10);
5605 rt2800_rfcsr_write(rt2x00dev
, 49, 0x94);
5606 rt2800_rfcsr_write(rt2x00dev
, 50, 0x94);
5607 rt2800_rfcsr_write(rt2x00dev
, 51, 0x3a);
5608 rt2800_rfcsr_write(rt2x00dev
, 52, 0x48);
5609 rt2800_rfcsr_write(rt2x00dev
, 53, 0x44);
5610 rt2800_rfcsr_write(rt2x00dev
, 54, 0x38);
5611 rt2800_rfcsr_write(rt2x00dev
, 55, 0x43);
5612 rt2800_rfcsr_write(rt2x00dev
, 56, 0xa1);
5613 rt2800_rfcsr_write(rt2x00dev
, 57, 0x00);
5614 rt2800_rfcsr_write(rt2x00dev
, 58, 0x39);
5615 rt2800_rfcsr_write(rt2x00dev
, 59, 0x07);
5616 rt2800_rfcsr_write(rt2x00dev
, 60, 0x45);
5617 rt2800_rfcsr_write(rt2x00dev
, 61, 0x91);
5618 rt2800_rfcsr_write(rt2x00dev
, 62, 0x39);
5619 rt2800_rfcsr_write(rt2x00dev
, 63, 0x07);
5621 rt2800_normal_mode_setup_5xxx(rt2x00dev
);
5623 rt2800_led_open_drain_enable(rt2x00dev
);
5626 static void rt2800_init_rfcsr_5592(struct rt2x00_dev
*rt2x00dev
)
5628 rt2800_rf_init_calibration(rt2x00dev
, 30);
5630 rt2800_rfcsr_write(rt2x00dev
, 1, 0x3F);
5631 rt2800_rfcsr_write(rt2x00dev
, 3, 0x08);
5632 rt2800_rfcsr_write(rt2x00dev
, 3, 0x08);
5633 rt2800_rfcsr_write(rt2x00dev
, 5, 0x10);
5634 rt2800_rfcsr_write(rt2x00dev
, 6, 0xE4);
5635 rt2800_rfcsr_write(rt2x00dev
, 7, 0x00);
5636 rt2800_rfcsr_write(rt2x00dev
, 14, 0x00);
5637 rt2800_rfcsr_write(rt2x00dev
, 15, 0x00);
5638 rt2800_rfcsr_write(rt2x00dev
, 16, 0x00);
5639 rt2800_rfcsr_write(rt2x00dev
, 18, 0x03);
5640 rt2800_rfcsr_write(rt2x00dev
, 19, 0x4D);
5641 rt2800_rfcsr_write(rt2x00dev
, 20, 0x10);
5642 rt2800_rfcsr_write(rt2x00dev
, 21, 0x8D);
5643 rt2800_rfcsr_write(rt2x00dev
, 26, 0x82);
5644 rt2800_rfcsr_write(rt2x00dev
, 28, 0x00);
5645 rt2800_rfcsr_write(rt2x00dev
, 29, 0x10);
5646 rt2800_rfcsr_write(rt2x00dev
, 33, 0xC0);
5647 rt2800_rfcsr_write(rt2x00dev
, 34, 0x07);
5648 rt2800_rfcsr_write(rt2x00dev
, 35, 0x12);
5649 rt2800_rfcsr_write(rt2x00dev
, 47, 0x0C);
5650 rt2800_rfcsr_write(rt2x00dev
, 53, 0x22);
5651 rt2800_rfcsr_write(rt2x00dev
, 63, 0x07);
5653 rt2800_rfcsr_write(rt2x00dev
, 2, 0x80);
5656 rt2800_adjust_freq_offset(rt2x00dev
);
5658 /* Enable DC filter */
5659 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5592
, REV_RT5592C
))
5660 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
5662 rt2800_normal_mode_setup_5xxx(rt2x00dev
);
5664 if (rt2x00_rt_rev_lt(rt2x00dev
, RT5592
, REV_RT5592C
))
5665 rt2800_rfcsr_write(rt2x00dev
, 27, 0x03);
5667 rt2800_led_open_drain_enable(rt2x00dev
);
5670 static void rt2800_init_rfcsr(struct rt2x00_dev
*rt2x00dev
)
5672 if (rt2800_is_305x_soc(rt2x00dev
)) {
5673 rt2800_init_rfcsr_305x_soc(rt2x00dev
);
5677 switch (rt2x00dev
->chip
.rt
) {
5681 rt2800_init_rfcsr_30xx(rt2x00dev
);
5684 rt2800_init_rfcsr_3290(rt2x00dev
);
5687 rt2800_init_rfcsr_3352(rt2x00dev
);
5690 rt2800_init_rfcsr_3390(rt2x00dev
);
5693 rt2800_init_rfcsr_3572(rt2x00dev
);
5696 rt2800_init_rfcsr_3593(rt2x00dev
);
5699 rt2800_init_rfcsr_5390(rt2x00dev
);
5702 rt2800_init_rfcsr_5392(rt2x00dev
);
5705 rt2800_init_rfcsr_5592(rt2x00dev
);
5710 int rt2800_enable_radio(struct rt2x00_dev
*rt2x00dev
)
5716 * Initialize all registers.
5718 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev
) ||
5719 rt2800_init_registers(rt2x00dev
)))
5723 * Send signal to firmware during boot time.
5725 rt2800_register_write(rt2x00dev
, H2M_BBP_AGENT
, 0);
5726 rt2800_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
5727 if (rt2x00_is_usb(rt2x00dev
)) {
5728 rt2800_register_write(rt2x00dev
, H2M_INT_SRC
, 0);
5729 rt2800_mcu_request(rt2x00dev
, MCU_BOOT_SIGNAL
, 0, 0, 0);
5733 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev
) ||
5734 rt2800_wait_bbp_ready(rt2x00dev
)))
5737 rt2800_init_bbp(rt2x00dev
);
5738 rt2800_init_rfcsr(rt2x00dev
);
5740 if (rt2x00_is_usb(rt2x00dev
) &&
5741 (rt2x00_rt(rt2x00dev
, RT3070
) ||
5742 rt2x00_rt(rt2x00dev
, RT3071
) ||
5743 rt2x00_rt(rt2x00dev
, RT3572
))) {
5745 rt2800_mcu_request(rt2x00dev
, MCU_CURRENT
, 0, 0, 0);
5752 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
5753 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_TX
, 1);
5754 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 0);
5755 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
5759 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
5760 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 1);
5761 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 1);
5762 rt2x00_set_field32(®
, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE
, 2);
5763 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 1);
5764 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
5766 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
5767 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_TX
, 1);
5768 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 1);
5769 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
5772 * Initialize LED control
5774 rt2800_eeprom_read(rt2x00dev
, EEPROM_LED_AG_CONF
, &word
);
5775 rt2800_mcu_request(rt2x00dev
, MCU_LED_AG_CONF
, 0xff,
5776 word
& 0xff, (word
>> 8) & 0xff);
5778 rt2800_eeprom_read(rt2x00dev
, EEPROM_LED_ACT_CONF
, &word
);
5779 rt2800_mcu_request(rt2x00dev
, MCU_LED_ACT_CONF
, 0xff,
5780 word
& 0xff, (word
>> 8) & 0xff);
5782 rt2800_eeprom_read(rt2x00dev
, EEPROM_LED_POLARITY
, &word
);
5783 rt2800_mcu_request(rt2x00dev
, MCU_LED_LED_POLARITY
, 0xff,
5784 word
& 0xff, (word
>> 8) & 0xff);
5788 EXPORT_SYMBOL_GPL(rt2800_enable_radio
);
5790 void rt2800_disable_radio(struct rt2x00_dev
*rt2x00dev
)
5794 rt2800_disable_wpdma(rt2x00dev
);
5796 /* Wait for DMA, ignore error */
5797 rt2800_wait_wpdma_ready(rt2x00dev
);
5799 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
5800 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_TX
, 0);
5801 rt2x00_set_field32(®
, MAC_SYS_CTRL_ENABLE_RX
, 0);
5802 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
5804 EXPORT_SYMBOL_GPL(rt2800_disable_radio
);
5806 int rt2800_efuse_detect(struct rt2x00_dev
*rt2x00dev
)
5811 if (rt2x00_rt(rt2x00dev
, RT3290
))
5812 efuse_ctrl_reg
= EFUSE_CTRL_3290
;
5814 efuse_ctrl_reg
= EFUSE_CTRL
;
5816 rt2800_register_read(rt2x00dev
, efuse_ctrl_reg
, ®
);
5817 return rt2x00_get_field32(reg
, EFUSE_CTRL_PRESENT
);
5819 EXPORT_SYMBOL_GPL(rt2800_efuse_detect
);
5821 static void rt2800_efuse_read(struct rt2x00_dev
*rt2x00dev
, unsigned int i
)
5825 u16 efuse_data0_reg
;
5826 u16 efuse_data1_reg
;
5827 u16 efuse_data2_reg
;
5828 u16 efuse_data3_reg
;
5830 if (rt2x00_rt(rt2x00dev
, RT3290
)) {
5831 efuse_ctrl_reg
= EFUSE_CTRL_3290
;
5832 efuse_data0_reg
= EFUSE_DATA0_3290
;
5833 efuse_data1_reg
= EFUSE_DATA1_3290
;
5834 efuse_data2_reg
= EFUSE_DATA2_3290
;
5835 efuse_data3_reg
= EFUSE_DATA3_3290
;
5837 efuse_ctrl_reg
= EFUSE_CTRL
;
5838 efuse_data0_reg
= EFUSE_DATA0
;
5839 efuse_data1_reg
= EFUSE_DATA1
;
5840 efuse_data2_reg
= EFUSE_DATA2
;
5841 efuse_data3_reg
= EFUSE_DATA3
;
5843 mutex_lock(&rt2x00dev
->csr_mutex
);
5845 rt2800_register_read_lock(rt2x00dev
, efuse_ctrl_reg
, ®
);
5846 rt2x00_set_field32(®
, EFUSE_CTRL_ADDRESS_IN
, i
);
5847 rt2x00_set_field32(®
, EFUSE_CTRL_MODE
, 0);
5848 rt2x00_set_field32(®
, EFUSE_CTRL_KICK
, 1);
5849 rt2800_register_write_lock(rt2x00dev
, efuse_ctrl_reg
, reg
);
5851 /* Wait until the EEPROM has been loaded */
5852 rt2800_regbusy_read(rt2x00dev
, efuse_ctrl_reg
, EFUSE_CTRL_KICK
, ®
);
5853 /* Apparently the data is read from end to start */
5854 rt2800_register_read_lock(rt2x00dev
, efuse_data3_reg
, ®
);
5855 /* The returned value is in CPU order, but eeprom is le */
5856 *(u32
*)&rt2x00dev
->eeprom
[i
] = cpu_to_le32(reg
);
5857 rt2800_register_read_lock(rt2x00dev
, efuse_data2_reg
, ®
);
5858 *(u32
*)&rt2x00dev
->eeprom
[i
+ 2] = cpu_to_le32(reg
);
5859 rt2800_register_read_lock(rt2x00dev
, efuse_data1_reg
, ®
);
5860 *(u32
*)&rt2x00dev
->eeprom
[i
+ 4] = cpu_to_le32(reg
);
5861 rt2800_register_read_lock(rt2x00dev
, efuse_data0_reg
, ®
);
5862 *(u32
*)&rt2x00dev
->eeprom
[i
+ 6] = cpu_to_le32(reg
);
5864 mutex_unlock(&rt2x00dev
->csr_mutex
);
5867 int rt2800_read_eeprom_efuse(struct rt2x00_dev
*rt2x00dev
)
5871 for (i
= 0; i
< EEPROM_SIZE
/ sizeof(u16
); i
+= 8)
5872 rt2800_efuse_read(rt2x00dev
, i
);
5876 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse
);
5878 static int rt2800_validate_eeprom(struct rt2x00_dev
*rt2x00dev
)
5880 struct rt2800_drv_data
*drv_data
= rt2x00dev
->drv_data
;
5883 u8 default_lna_gain
;
5889 retval
= rt2800_read_eeprom(rt2x00dev
);
5894 * Start validation of the data that has been read.
5896 mac
= rt2800_eeprom_addr(rt2x00dev
, EEPROM_MAC_ADDR_0
);
5897 if (!is_valid_ether_addr(mac
)) {
5898 eth_random_addr(mac
);
5899 rt2x00_eeprom_dbg(rt2x00dev
, "MAC: %pM\n", mac
);
5902 rt2800_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &word
);
5903 if (word
== 0xffff) {
5904 rt2x00_set_field16(&word
, EEPROM_NIC_CONF0_RXPATH
, 2);
5905 rt2x00_set_field16(&word
, EEPROM_NIC_CONF0_TXPATH
, 1);
5906 rt2x00_set_field16(&word
, EEPROM_NIC_CONF0_RF_TYPE
, RF2820
);
5907 rt2800_eeprom_write(rt2x00dev
, EEPROM_NIC_CONF0
, word
);
5908 rt2x00_eeprom_dbg(rt2x00dev
, "Antenna: 0x%04x\n", word
);
5909 } else if (rt2x00_rt(rt2x00dev
, RT2860
) ||
5910 rt2x00_rt(rt2x00dev
, RT2872
)) {
5912 * There is a max of 2 RX streams for RT28x0 series
5914 if (rt2x00_get_field16(word
, EEPROM_NIC_CONF0_RXPATH
) > 2)
5915 rt2x00_set_field16(&word
, EEPROM_NIC_CONF0_RXPATH
, 2);
5916 rt2800_eeprom_write(rt2x00dev
, EEPROM_NIC_CONF0
, word
);
5919 rt2800_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &word
);
5920 if (word
== 0xffff) {
5921 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_HW_RADIO
, 0);
5922 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC
, 0);
5923 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G
, 0);
5924 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G
, 0);
5925 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_CARDBUS_ACCEL
, 0);
5926 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BW40M_SB_2G
, 0);
5927 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BW40M_SB_5G
, 0);
5928 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_WPS_PBC
, 0);
5929 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BW40M_2G
, 0);
5930 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BW40M_5G
, 0);
5931 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA
, 0);
5932 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_ANT_DIVERSITY
, 0);
5933 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_INTERNAL_TX_ALC
, 0);
5934 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_BT_COEXIST
, 0);
5935 rt2x00_set_field16(&word
, EEPROM_NIC_CONF1_DAC_TEST
, 0);
5936 rt2800_eeprom_write(rt2x00dev
, EEPROM_NIC_CONF1
, word
);
5937 rt2x00_eeprom_dbg(rt2x00dev
, "NIC: 0x%04x\n", word
);
5940 rt2800_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &word
);
5941 if ((word
& 0x00ff) == 0x00ff) {
5942 rt2x00_set_field16(&word
, EEPROM_FREQ_OFFSET
, 0);
5943 rt2800_eeprom_write(rt2x00dev
, EEPROM_FREQ
, word
);
5944 rt2x00_eeprom_dbg(rt2x00dev
, "Freq: 0x%04x\n", word
);
5946 if ((word
& 0xff00) == 0xff00) {
5947 rt2x00_set_field16(&word
, EEPROM_FREQ_LED_MODE
,
5948 LED_MODE_TXRX_ACTIVITY
);
5949 rt2x00_set_field16(&word
, EEPROM_FREQ_LED_POLARITY
, 0);
5950 rt2800_eeprom_write(rt2x00dev
, EEPROM_FREQ
, word
);
5951 rt2800_eeprom_write(rt2x00dev
, EEPROM_LED_AG_CONF
, 0x5555);
5952 rt2800_eeprom_write(rt2x00dev
, EEPROM_LED_ACT_CONF
, 0x2221);
5953 rt2800_eeprom_write(rt2x00dev
, EEPROM_LED_POLARITY
, 0xa9f8);
5954 rt2x00_eeprom_dbg(rt2x00dev
, "Led Mode: 0x%04x\n", word
);
5958 * During the LNA validation we are going to use
5959 * lna0 as correct value. Note that EEPROM_LNA
5960 * is never validated.
5962 rt2800_eeprom_read(rt2x00dev
, EEPROM_LNA
, &word
);
5963 default_lna_gain
= rt2x00_get_field16(word
, EEPROM_LNA_A0
);
5965 rt2800_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG
, &word
);
5966 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG_OFFSET0
)) > 10)
5967 rt2x00_set_field16(&word
, EEPROM_RSSI_BG_OFFSET0
, 0);
5968 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG_OFFSET1
)) > 10)
5969 rt2x00_set_field16(&word
, EEPROM_RSSI_BG_OFFSET1
, 0);
5970 rt2800_eeprom_write(rt2x00dev
, EEPROM_RSSI_BG
, word
);
5972 rt2800_eeprom_read(rt2x00dev
, EEPROM_TXMIXER_GAIN_BG
, &word
);
5973 if ((word
& 0x00ff) != 0x00ff) {
5974 drv_data
->txmixer_gain_24g
=
5975 rt2x00_get_field16(word
, EEPROM_TXMIXER_GAIN_BG_VAL
);
5977 drv_data
->txmixer_gain_24g
= 0;
5980 rt2800_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &word
);
5981 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG2_OFFSET2
)) > 10)
5982 rt2x00_set_field16(&word
, EEPROM_RSSI_BG2_OFFSET2
, 0);
5983 if (rt2x00_get_field16(word
, EEPROM_RSSI_BG2_LNA_A1
) == 0x00 ||
5984 rt2x00_get_field16(word
, EEPROM_RSSI_BG2_LNA_A1
) == 0xff)
5985 rt2x00_set_field16(&word
, EEPROM_RSSI_BG2_LNA_A1
,
5987 rt2800_eeprom_write(rt2x00dev
, EEPROM_RSSI_BG2
, word
);
5989 rt2800_eeprom_read(rt2x00dev
, EEPROM_TXMIXER_GAIN_A
, &word
);
5990 if ((word
& 0x00ff) != 0x00ff) {
5991 drv_data
->txmixer_gain_5g
=
5992 rt2x00_get_field16(word
, EEPROM_TXMIXER_GAIN_A_VAL
);
5994 drv_data
->txmixer_gain_5g
= 0;
5997 rt2800_eeprom_read(rt2x00dev
, EEPROM_RSSI_A
, &word
);
5998 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A_OFFSET0
)) > 10)
5999 rt2x00_set_field16(&word
, EEPROM_RSSI_A_OFFSET0
, 0);
6000 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A_OFFSET1
)) > 10)
6001 rt2x00_set_field16(&word
, EEPROM_RSSI_A_OFFSET1
, 0);
6002 rt2800_eeprom_write(rt2x00dev
, EEPROM_RSSI_A
, word
);
6004 rt2800_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &word
);
6005 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A2_OFFSET2
)) > 10)
6006 rt2x00_set_field16(&word
, EEPROM_RSSI_A2_OFFSET2
, 0);
6007 if (rt2x00_get_field16(word
, EEPROM_RSSI_A2_LNA_A2
) == 0x00 ||
6008 rt2x00_get_field16(word
, EEPROM_RSSI_A2_LNA_A2
) == 0xff)
6009 rt2x00_set_field16(&word
, EEPROM_RSSI_A2_LNA_A2
,
6011 rt2800_eeprom_write(rt2x00dev
, EEPROM_RSSI_A2
, word
);
6016 static int rt2800_init_eeprom(struct rt2x00_dev
*rt2x00dev
)
6023 * Read EEPROM word for configuration.
6025 rt2800_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &eeprom
);
6028 * Identify RF chipset by EEPROM value
6029 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
6030 * RT53xx: defined in "EEPROM_CHIP_ID" field
6032 if (rt2x00_rt(rt2x00dev
, RT3290
) ||
6033 rt2x00_rt(rt2x00dev
, RT5390
) ||
6034 rt2x00_rt(rt2x00dev
, RT5392
))
6035 rt2800_eeprom_read(rt2x00dev
, EEPROM_CHIP_ID
, &rf
);
6037 rf
= rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RF_TYPE
);
6060 rt2x00_err(rt2x00dev
, "Invalid RF chipset 0x%04x detected\n",
6065 rt2x00_set_rf(rt2x00dev
, rf
);
6068 * Identify default antenna configuration.
6070 rt2x00dev
->default_ant
.tx_chain_num
=
6071 rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
);
6072 rt2x00dev
->default_ant
.rx_chain_num
=
6073 rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
);
6075 rt2800_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF1
, &eeprom
);
6077 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
6078 rt2x00_rt(rt2x00dev
, RT3090
) ||
6079 rt2x00_rt(rt2x00dev
, RT3352
) ||
6080 rt2x00_rt(rt2x00dev
, RT3390
)) {
6081 value
= rt2x00_get_field16(eeprom
,
6082 EEPROM_NIC_CONF1_ANT_DIVERSITY
);
6087 rt2x00dev
->default_ant
.tx
= ANTENNA_A
;
6088 rt2x00dev
->default_ant
.rx
= ANTENNA_A
;
6091 rt2x00dev
->default_ant
.tx
= ANTENNA_A
;
6092 rt2x00dev
->default_ant
.rx
= ANTENNA_B
;
6096 rt2x00dev
->default_ant
.tx
= ANTENNA_A
;
6097 rt2x00dev
->default_ant
.rx
= ANTENNA_A
;
6100 if (rt2x00_rt_rev_gte(rt2x00dev
, RT5390
, REV_RT5390R
)) {
6101 rt2x00dev
->default_ant
.tx
= ANTENNA_HW_DIVERSITY
; /* Unused */
6102 rt2x00dev
->default_ant
.rx
= ANTENNA_HW_DIVERSITY
; /* Unused */
6106 * Determine external LNA informations.
6108 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G
))
6109 __set_bit(CAPABILITY_EXTERNAL_LNA_A
, &rt2x00dev
->cap_flags
);
6110 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G
))
6111 __set_bit(CAPABILITY_EXTERNAL_LNA_BG
, &rt2x00dev
->cap_flags
);
6114 * Detect if this device has an hardware controlled radio.
6116 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_HW_RADIO
))
6117 __set_bit(CAPABILITY_HW_BUTTON
, &rt2x00dev
->cap_flags
);
6120 * Detect if this device has Bluetooth co-existence.
6122 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF1_BT_COEXIST
))
6123 __set_bit(CAPABILITY_BT_COEXIST
, &rt2x00dev
->cap_flags
);
6126 * Read frequency offset and RF programming sequence.
6128 rt2800_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &eeprom
);
6129 rt2x00dev
->freq_offset
= rt2x00_get_field16(eeprom
, EEPROM_FREQ_OFFSET
);
6132 * Store led settings, for correct led behaviour.
6134 #ifdef CONFIG_RT2X00_LIB_LEDS
6135 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_radio
, LED_TYPE_RADIO
);
6136 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_assoc
, LED_TYPE_ASSOC
);
6137 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_qual
, LED_TYPE_QUALITY
);
6139 rt2x00dev
->led_mcu_reg
= eeprom
;
6140 #endif /* CONFIG_RT2X00_LIB_LEDS */
6143 * Check if support EIRP tx power limit feature.
6145 rt2800_eeprom_read(rt2x00dev
, EEPROM_EIRP_MAX_TX_POWER
, &eeprom
);
6147 if (rt2x00_get_field16(eeprom
, EEPROM_EIRP_MAX_TX_POWER_2GHZ
) <
6148 EIRP_MAX_TX_POWER_LIMIT
)
6149 __set_bit(CAPABILITY_POWER_LIMIT
, &rt2x00dev
->cap_flags
);
6155 * RF value list for rt28xx
6156 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
6158 static const struct rf_channel rf_vals
[] = {
6159 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
6160 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
6161 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
6162 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
6163 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
6164 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
6165 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
6166 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
6167 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
6168 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
6169 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
6170 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
6171 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
6172 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
6174 /* 802.11 UNI / HyperLan 2 */
6175 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
6176 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
6177 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
6178 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
6179 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
6180 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
6181 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
6182 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
6183 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
6184 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
6185 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
6186 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
6188 /* 802.11 HyperLan 2 */
6189 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
6190 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
6191 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
6192 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
6193 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
6194 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
6195 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
6196 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
6197 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
6198 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
6199 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
6200 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
6201 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
6202 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
6203 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
6204 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
6207 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
6208 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
6209 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
6210 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
6211 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
6212 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
6213 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
6214 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
6215 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
6216 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
6217 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
6220 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
6221 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
6222 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
6223 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
6224 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
6225 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
6226 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
6230 * RF value list for rt3xxx
6231 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
6233 static const struct rf_channel rf_vals_3x
[] = {
6249 /* 802.11 UNI / HyperLan 2 */
6263 /* 802.11 HyperLan 2 */
6295 static const struct rf_channel rf_vals_5592_xtal20
[] = {
6296 /* Channel, N, K, mod, R */
6306 {10, 491, 4, 10, 3},
6307 {11, 492, 4, 10, 3},
6308 {12, 493, 4, 10, 3},
6309 {13, 494, 4, 10, 3},
6310 {14, 496, 8, 10, 3},
6311 {36, 172, 8, 12, 1},
6312 {38, 173, 0, 12, 1},
6313 {40, 173, 4, 12, 1},
6314 {42, 173, 8, 12, 1},
6315 {44, 174, 0, 12, 1},
6316 {46, 174, 4, 12, 1},
6317 {48, 174, 8, 12, 1},
6318 {50, 175, 0, 12, 1},
6319 {52, 175, 4, 12, 1},
6320 {54, 175, 8, 12, 1},
6321 {56, 176, 0, 12, 1},
6322 {58, 176, 4, 12, 1},
6323 {60, 176, 8, 12, 1},
6324 {62, 177, 0, 12, 1},
6325 {64, 177, 4, 12, 1},
6326 {100, 183, 4, 12, 1},
6327 {102, 183, 8, 12, 1},
6328 {104, 184, 0, 12, 1},
6329 {106, 184, 4, 12, 1},
6330 {108, 184, 8, 12, 1},
6331 {110, 185, 0, 12, 1},
6332 {112, 185, 4, 12, 1},
6333 {114, 185, 8, 12, 1},
6334 {116, 186, 0, 12, 1},
6335 {118, 186, 4, 12, 1},
6336 {120, 186, 8, 12, 1},
6337 {122, 187, 0, 12, 1},
6338 {124, 187, 4, 12, 1},
6339 {126, 187, 8, 12, 1},
6340 {128, 188, 0, 12, 1},
6341 {130, 188, 4, 12, 1},
6342 {132, 188, 8, 12, 1},
6343 {134, 189, 0, 12, 1},
6344 {136, 189, 4, 12, 1},
6345 {138, 189, 8, 12, 1},
6346 {140, 190, 0, 12, 1},
6347 {149, 191, 6, 12, 1},
6348 {151, 191, 10, 12, 1},
6349 {153, 192, 2, 12, 1},
6350 {155, 192, 6, 12, 1},
6351 {157, 192, 10, 12, 1},
6352 {159, 193, 2, 12, 1},
6353 {161, 193, 6, 12, 1},
6354 {165, 194, 2, 12, 1},
6355 {184, 164, 0, 12, 1},
6356 {188, 164, 4, 12, 1},
6357 {192, 165, 8, 12, 1},
6358 {196, 166, 0, 12, 1},
6361 static const struct rf_channel rf_vals_5592_xtal40
[] = {
6362 /* Channel, N, K, mod, R */
6372 {10, 245, 7, 10, 3},
6373 {11, 246, 2, 10, 3},
6374 {12, 246, 7, 10, 3},
6375 {13, 247, 2, 10, 3},
6376 {14, 248, 4, 10, 3},
6380 {42, 86, 10, 12, 1},
6386 {54, 87, 10, 12, 1},
6392 {100, 91, 8, 12, 1},
6393 {102, 91, 10, 12, 1},
6394 {104, 92, 0, 12, 1},
6395 {106, 92, 2, 12, 1},
6396 {108, 92, 4, 12, 1},
6397 {110, 92, 6, 12, 1},
6398 {112, 92, 8, 12, 1},
6399 {114, 92, 10, 12, 1},
6400 {116, 93, 0, 12, 1},
6401 {118, 93, 2, 12, 1},
6402 {120, 93, 4, 12, 1},
6403 {122, 93, 6, 12, 1},
6404 {124, 93, 8, 12, 1},
6405 {126, 93, 10, 12, 1},
6406 {128, 94, 0, 12, 1},
6407 {130, 94, 2, 12, 1},
6408 {132, 94, 4, 12, 1},
6409 {134, 94, 6, 12, 1},
6410 {136, 94, 8, 12, 1},
6411 {138, 94, 10, 12, 1},
6412 {140, 95, 0, 12, 1},
6413 {149, 95, 9, 12, 1},
6414 {151, 95, 11, 12, 1},
6415 {153, 96, 1, 12, 1},
6416 {155, 96, 3, 12, 1},
6417 {157, 96, 5, 12, 1},
6418 {159, 96, 7, 12, 1},
6419 {161, 96, 9, 12, 1},
6420 {165, 97, 1, 12, 1},
6421 {184, 82, 0, 12, 1},
6422 {188, 82, 4, 12, 1},
6423 {192, 82, 8, 12, 1},
6424 {196, 83, 0, 12, 1},
6427 static int rt2800_probe_hw_mode(struct rt2x00_dev
*rt2x00dev
)
6429 struct hw_mode_spec
*spec
= &rt2x00dev
->spec
;
6430 struct channel_info
*info
;
6431 char *default_power1
;
6432 char *default_power2
;
6438 * Disable powersaving as default on PCI devices.
6440 if (rt2x00_is_pci(rt2x00dev
) || rt2x00_is_soc(rt2x00dev
))
6441 rt2x00dev
->hw
->wiphy
->flags
&= ~WIPHY_FLAG_PS_ON_BY_DEFAULT
;
6444 * Initialize all hw fields.
6446 rt2x00dev
->hw
->flags
=
6447 IEEE80211_HW_SIGNAL_DBM
|
6448 IEEE80211_HW_SUPPORTS_PS
|
6449 IEEE80211_HW_PS_NULLFUNC_STACK
|
6450 IEEE80211_HW_AMPDU_AGGREGATION
|
6451 IEEE80211_HW_REPORTS_TX_ACK_STATUS
;
6454 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
6455 * unless we are capable of sending the buffered frames out after the
6456 * DTIM transmission using rt2x00lib_beacondone. This will send out
6457 * multicast and broadcast traffic immediately instead of buffering it
6458 * infinitly and thus dropping it after some time.
6460 if (!rt2x00_is_usb(rt2x00dev
))
6461 rt2x00dev
->hw
->flags
|=
6462 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
;
6464 SET_IEEE80211_DEV(rt2x00dev
->hw
, rt2x00dev
->dev
);
6465 SET_IEEE80211_PERM_ADDR(rt2x00dev
->hw
,
6466 rt2800_eeprom_addr(rt2x00dev
,
6467 EEPROM_MAC_ADDR_0
));
6470 * As rt2800 has a global fallback table we cannot specify
6471 * more then one tx rate per frame but since the hw will
6472 * try several rates (based on the fallback table) we should
6473 * initialize max_report_rates to the maximum number of rates
6474 * we are going to try. Otherwise mac80211 will truncate our
6475 * reported tx rates and the rc algortihm will end up with
6478 rt2x00dev
->hw
->max_rates
= 1;
6479 rt2x00dev
->hw
->max_report_rates
= 7;
6480 rt2x00dev
->hw
->max_rate_tries
= 1;
6482 rt2800_eeprom_read(rt2x00dev
, EEPROM_NIC_CONF0
, &eeprom
);
6485 * Initialize hw_mode information.
6487 spec
->supported_bands
= SUPPORT_BAND_2GHZ
;
6488 spec
->supported_rates
= SUPPORT_RATE_CCK
| SUPPORT_RATE_OFDM
;
6490 if (rt2x00_rf(rt2x00dev
, RF2820
) ||
6491 rt2x00_rf(rt2x00dev
, RF2720
)) {
6492 spec
->num_channels
= 14;
6493 spec
->channels
= rf_vals
;
6494 } else if (rt2x00_rf(rt2x00dev
, RF2850
) ||
6495 rt2x00_rf(rt2x00dev
, RF2750
)) {
6496 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
6497 spec
->num_channels
= ARRAY_SIZE(rf_vals
);
6498 spec
->channels
= rf_vals
;
6499 } else if (rt2x00_rf(rt2x00dev
, RF3020
) ||
6500 rt2x00_rf(rt2x00dev
, RF2020
) ||
6501 rt2x00_rf(rt2x00dev
, RF3021
) ||
6502 rt2x00_rf(rt2x00dev
, RF3022
) ||
6503 rt2x00_rf(rt2x00dev
, RF3290
) ||
6504 rt2x00_rf(rt2x00dev
, RF3320
) ||
6505 rt2x00_rf(rt2x00dev
, RF3322
) ||
6506 rt2x00_rf(rt2x00dev
, RF5360
) ||
6507 rt2x00_rf(rt2x00dev
, RF5370
) ||
6508 rt2x00_rf(rt2x00dev
, RF5372
) ||
6509 rt2x00_rf(rt2x00dev
, RF5390
) ||
6510 rt2x00_rf(rt2x00dev
, RF5392
)) {
6511 spec
->num_channels
= 14;
6512 spec
->channels
= rf_vals_3x
;
6513 } else if (rt2x00_rf(rt2x00dev
, RF3052
)) {
6514 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
6515 spec
->num_channels
= ARRAY_SIZE(rf_vals_3x
);
6516 spec
->channels
= rf_vals_3x
;
6517 } else if (rt2x00_rf(rt2x00dev
, RF5592
)) {
6518 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
6520 rt2800_register_read(rt2x00dev
, MAC_DEBUG_INDEX
, ®
);
6521 if (rt2x00_get_field32(reg
, MAC_DEBUG_INDEX_XTAL
)) {
6522 spec
->num_channels
= ARRAY_SIZE(rf_vals_5592_xtal40
);
6523 spec
->channels
= rf_vals_5592_xtal40
;
6525 spec
->num_channels
= ARRAY_SIZE(rf_vals_5592_xtal20
);
6526 spec
->channels
= rf_vals_5592_xtal20
;
6530 if (WARN_ON_ONCE(!spec
->channels
))
6534 * Initialize HT information.
6536 if (!rt2x00_rf(rt2x00dev
, RF2020
))
6537 spec
->ht
.ht_supported
= true;
6539 spec
->ht
.ht_supported
= false;
6542 IEEE80211_HT_CAP_SUP_WIDTH_20_40
|
6543 IEEE80211_HT_CAP_GRN_FLD
|
6544 IEEE80211_HT_CAP_SGI_20
|
6545 IEEE80211_HT_CAP_SGI_40
;
6547 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
) >= 2)
6548 spec
->ht
.cap
|= IEEE80211_HT_CAP_TX_STBC
;
6551 rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
) <<
6552 IEEE80211_HT_CAP_RX_STBC_SHIFT
;
6554 spec
->ht
.ampdu_factor
= 3;
6555 spec
->ht
.ampdu_density
= 4;
6556 spec
->ht
.mcs
.tx_params
=
6557 IEEE80211_HT_MCS_TX_DEFINED
|
6558 IEEE80211_HT_MCS_TX_RX_DIFF
|
6559 ((rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_TXPATH
) - 1) <<
6560 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT
);
6562 switch (rt2x00_get_field16(eeprom
, EEPROM_NIC_CONF0_RXPATH
)) {
6564 spec
->ht
.mcs
.rx_mask
[2] = 0xff;
6566 spec
->ht
.mcs
.rx_mask
[1] = 0xff;
6568 spec
->ht
.mcs
.rx_mask
[0] = 0xff;
6569 spec
->ht
.mcs
.rx_mask
[4] = 0x1; /* MCS32 */
6574 * Create channel information array
6576 info
= kcalloc(spec
->num_channels
, sizeof(*info
), GFP_KERNEL
);
6580 spec
->channels_info
= info
;
6582 default_power1
= rt2800_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_BG1
);
6583 default_power2
= rt2800_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_BG2
);
6585 for (i
= 0; i
< 14; i
++) {
6586 info
[i
].default_power1
= default_power1
[i
];
6587 info
[i
].default_power2
= default_power2
[i
];
6590 if (spec
->num_channels
> 14) {
6591 default_power1
= rt2800_eeprom_addr(rt2x00dev
,
6593 default_power2
= rt2800_eeprom_addr(rt2x00dev
,
6596 for (i
= 14; i
< spec
->num_channels
; i
++) {
6597 info
[i
].default_power1
= default_power1
[i
- 14];
6598 info
[i
].default_power2
= default_power2
[i
- 14];
6602 switch (rt2x00dev
->chip
.rf
) {
6615 __set_bit(CAPABILITY_VCO_RECALIBRATION
, &rt2x00dev
->cap_flags
);
6622 static int rt2800_probe_rt(struct rt2x00_dev
*rt2x00dev
)
6628 if (rt2x00_rt(rt2x00dev
, RT3290
))
6629 rt2800_register_read(rt2x00dev
, MAC_CSR0_3290
, ®
);
6631 rt2800_register_read(rt2x00dev
, MAC_CSR0
, ®
);
6633 rt
= rt2x00_get_field32(reg
, MAC_CSR0_CHIPSET
);
6634 rev
= rt2x00_get_field32(reg
, MAC_CSR0_REVISION
);
6652 rt2x00_err(rt2x00dev
, "Invalid RT chipset 0x%04x, rev %04x detected\n",
6657 rt2x00_set_rt(rt2x00dev
, rt
, rev
);
6662 int rt2800_probe_hw(struct rt2x00_dev
*rt2x00dev
)
6667 retval
= rt2800_probe_rt(rt2x00dev
);
6672 * Allocate eeprom data.
6674 retval
= rt2800_validate_eeprom(rt2x00dev
);
6678 retval
= rt2800_init_eeprom(rt2x00dev
);
6683 * Enable rfkill polling by setting GPIO direction of the
6684 * rfkill switch GPIO pin correctly.
6686 rt2800_register_read(rt2x00dev
, GPIO_CTRL
, ®
);
6687 rt2x00_set_field32(®
, GPIO_CTRL_DIR2
, 1);
6688 rt2800_register_write(rt2x00dev
, GPIO_CTRL
, reg
);
6691 * Initialize hw specifications.
6693 retval
= rt2800_probe_hw_mode(rt2x00dev
);
6698 * Set device capabilities.
6700 __set_bit(CAPABILITY_CONTROL_FILTERS
, &rt2x00dev
->cap_flags
);
6701 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL
, &rt2x00dev
->cap_flags
);
6702 if (!rt2x00_is_usb(rt2x00dev
))
6703 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT
, &rt2x00dev
->cap_flags
);
6706 * Set device requirements.
6708 if (!rt2x00_is_soc(rt2x00dev
))
6709 __set_bit(REQUIRE_FIRMWARE
, &rt2x00dev
->cap_flags
);
6710 __set_bit(REQUIRE_L2PAD
, &rt2x00dev
->cap_flags
);
6711 __set_bit(REQUIRE_TXSTATUS_FIFO
, &rt2x00dev
->cap_flags
);
6712 if (!rt2800_hwcrypt_disabled(rt2x00dev
))
6713 __set_bit(CAPABILITY_HW_CRYPTO
, &rt2x00dev
->cap_flags
);
6714 __set_bit(CAPABILITY_LINK_TUNING
, &rt2x00dev
->cap_flags
);
6715 __set_bit(REQUIRE_HT_TX_DESC
, &rt2x00dev
->cap_flags
);
6716 if (rt2x00_is_usb(rt2x00dev
))
6717 __set_bit(REQUIRE_PS_AUTOWAKE
, &rt2x00dev
->cap_flags
);
6719 __set_bit(REQUIRE_DMA
, &rt2x00dev
->cap_flags
);
6720 __set_bit(REQUIRE_TASKLET_CONTEXT
, &rt2x00dev
->cap_flags
);
6724 * Set the rssi offset.
6726 rt2x00dev
->rssi_offset
= DEFAULT_RSSI_OFFSET
;
6730 EXPORT_SYMBOL_GPL(rt2800_probe_hw
);
6733 * IEEE80211 stack callback functions.
6735 void rt2800_get_tkip_seq(struct ieee80211_hw
*hw
, u8 hw_key_idx
, u32
*iv32
,
6738 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
6739 struct mac_iveiv_entry iveiv_entry
;
6742 offset
= MAC_IVEIV_ENTRY(hw_key_idx
);
6743 rt2800_register_multiread(rt2x00dev
, offset
,
6744 &iveiv_entry
, sizeof(iveiv_entry
));
6746 memcpy(iv16
, &iveiv_entry
.iv
[0], sizeof(*iv16
));
6747 memcpy(iv32
, &iveiv_entry
.iv
[4], sizeof(*iv32
));
6749 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq
);
6751 int rt2800_set_rts_threshold(struct ieee80211_hw
*hw
, u32 value
)
6753 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
6755 bool enabled
= (value
< IEEE80211_MAX_RTS_THRESHOLD
);
6757 rt2800_register_read(rt2x00dev
, TX_RTS_CFG
, ®
);
6758 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_THRES
, value
);
6759 rt2800_register_write(rt2x00dev
, TX_RTS_CFG
, reg
);
6761 rt2800_register_read(rt2x00dev
, CCK_PROT_CFG
, ®
);
6762 rt2x00_set_field32(®
, CCK_PROT_CFG_RTS_TH_EN
, enabled
);
6763 rt2800_register_write(rt2x00dev
, CCK_PROT_CFG
, reg
);
6765 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
6766 rt2x00_set_field32(®
, OFDM_PROT_CFG_RTS_TH_EN
, enabled
);
6767 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
6769 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
6770 rt2x00_set_field32(®
, MM20_PROT_CFG_RTS_TH_EN
, enabled
);
6771 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
6773 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
6774 rt2x00_set_field32(®
, MM40_PROT_CFG_RTS_TH_EN
, enabled
);
6775 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
6777 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
6778 rt2x00_set_field32(®
, GF20_PROT_CFG_RTS_TH_EN
, enabled
);
6779 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
6781 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
6782 rt2x00_set_field32(®
, GF40_PROT_CFG_RTS_TH_EN
, enabled
);
6783 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
6787 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold
);
6789 int rt2800_conf_tx(struct ieee80211_hw
*hw
,
6790 struct ieee80211_vif
*vif
, u16 queue_idx
,
6791 const struct ieee80211_tx_queue_params
*params
)
6793 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
6794 struct data_queue
*queue
;
6795 struct rt2x00_field32 field
;
6801 * First pass the configuration through rt2x00lib, that will
6802 * update the queue settings and validate the input. After that
6803 * we are free to update the registers based on the value
6804 * in the queue parameter.
6806 retval
= rt2x00mac_conf_tx(hw
, vif
, queue_idx
, params
);
6811 * We only need to perform additional register initialization
6817 queue
= rt2x00queue_get_tx_queue(rt2x00dev
, queue_idx
);
6819 /* Update WMM TXOP register */
6820 offset
= WMM_TXOP0_CFG
+ (sizeof(u32
) * (!!(queue_idx
& 2)));
6821 field
.bit_offset
= (queue_idx
& 1) * 16;
6822 field
.bit_mask
= 0xffff << field
.bit_offset
;
6824 rt2800_register_read(rt2x00dev
, offset
, ®
);
6825 rt2x00_set_field32(®
, field
, queue
->txop
);
6826 rt2800_register_write(rt2x00dev
, offset
, reg
);
6828 /* Update WMM registers */
6829 field
.bit_offset
= queue_idx
* 4;
6830 field
.bit_mask
= 0xf << field
.bit_offset
;
6832 rt2800_register_read(rt2x00dev
, WMM_AIFSN_CFG
, ®
);
6833 rt2x00_set_field32(®
, field
, queue
->aifs
);
6834 rt2800_register_write(rt2x00dev
, WMM_AIFSN_CFG
, reg
);
6836 rt2800_register_read(rt2x00dev
, WMM_CWMIN_CFG
, ®
);
6837 rt2x00_set_field32(®
, field
, queue
->cw_min
);
6838 rt2800_register_write(rt2x00dev
, WMM_CWMIN_CFG
, reg
);
6840 rt2800_register_read(rt2x00dev
, WMM_CWMAX_CFG
, ®
);
6841 rt2x00_set_field32(®
, field
, queue
->cw_max
);
6842 rt2800_register_write(rt2x00dev
, WMM_CWMAX_CFG
, reg
);
6844 /* Update EDCA registers */
6845 offset
= EDCA_AC0_CFG
+ (sizeof(u32
) * queue_idx
);
6847 rt2800_register_read(rt2x00dev
, offset
, ®
);
6848 rt2x00_set_field32(®
, EDCA_AC0_CFG_TX_OP
, queue
->txop
);
6849 rt2x00_set_field32(®
, EDCA_AC0_CFG_AIFSN
, queue
->aifs
);
6850 rt2x00_set_field32(®
, EDCA_AC0_CFG_CWMIN
, queue
->cw_min
);
6851 rt2x00_set_field32(®
, EDCA_AC0_CFG_CWMAX
, queue
->cw_max
);
6852 rt2800_register_write(rt2x00dev
, offset
, reg
);
6856 EXPORT_SYMBOL_GPL(rt2800_conf_tx
);
6858 u64
rt2800_get_tsf(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
)
6860 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
6864 rt2800_register_read(rt2x00dev
, TSF_TIMER_DW1
, ®
);
6865 tsf
= (u64
) rt2x00_get_field32(reg
, TSF_TIMER_DW1_HIGH_WORD
) << 32;
6866 rt2800_register_read(rt2x00dev
, TSF_TIMER_DW0
, ®
);
6867 tsf
|= rt2x00_get_field32(reg
, TSF_TIMER_DW0_LOW_WORD
);
6871 EXPORT_SYMBOL_GPL(rt2800_get_tsf
);
6873 int rt2800_ampdu_action(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
,
6874 enum ieee80211_ampdu_mlme_action action
,
6875 struct ieee80211_sta
*sta
, u16 tid
, u16
*ssn
,
6878 struct rt2x00_sta
*sta_priv
= (struct rt2x00_sta
*)sta
->drv_priv
;
6882 * Don't allow aggregation for stations the hardware isn't aware
6883 * of because tx status reports for frames to an unknown station
6884 * always contain wcid=255 and thus we can't distinguish between
6885 * multiple stations which leads to unwanted situations when the
6886 * hw reorders frames due to aggregation.
6888 if (sta_priv
->wcid
< 0)
6892 case IEEE80211_AMPDU_RX_START
:
6893 case IEEE80211_AMPDU_RX_STOP
:
6895 * The hw itself takes care of setting up BlockAck mechanisms.
6896 * So, we only have to allow mac80211 to nagotiate a BlockAck
6897 * agreement. Once that is done, the hw will BlockAck incoming
6898 * AMPDUs without further setup.
6901 case IEEE80211_AMPDU_TX_START
:
6902 ieee80211_start_tx_ba_cb_irqsafe(vif
, sta
->addr
, tid
);
6904 case IEEE80211_AMPDU_TX_STOP_CONT
:
6905 case IEEE80211_AMPDU_TX_STOP_FLUSH
:
6906 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT
:
6907 ieee80211_stop_tx_ba_cb_irqsafe(vif
, sta
->addr
, tid
);
6909 case IEEE80211_AMPDU_TX_OPERATIONAL
:
6912 rt2x00_warn((struct rt2x00_dev
*)hw
->priv
,
6913 "Unknown AMPDU action\n");
6918 EXPORT_SYMBOL_GPL(rt2800_ampdu_action
);
6920 int rt2800_get_survey(struct ieee80211_hw
*hw
, int idx
,
6921 struct survey_info
*survey
)
6923 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
6924 struct ieee80211_conf
*conf
= &hw
->conf
;
6925 u32 idle
, busy
, busy_ext
;
6930 survey
->channel
= conf
->chandef
.chan
;
6932 rt2800_register_read(rt2x00dev
, CH_IDLE_STA
, &idle
);
6933 rt2800_register_read(rt2x00dev
, CH_BUSY_STA
, &busy
);
6934 rt2800_register_read(rt2x00dev
, CH_BUSY_STA_SEC
, &busy_ext
);
6937 survey
->filled
= SURVEY_INFO_CHANNEL_TIME
|
6938 SURVEY_INFO_CHANNEL_TIME_BUSY
|
6939 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY
;
6941 survey
->channel_time
= (idle
+ busy
) / 1000;
6942 survey
->channel_time_busy
= busy
/ 1000;
6943 survey
->channel_time_ext_busy
= busy_ext
/ 1000;
6946 if (!(hw
->conf
.flags
& IEEE80211_CONF_OFFCHANNEL
))
6947 survey
->filled
|= SURVEY_INFO_IN_USE
;
6952 EXPORT_SYMBOL_GPL(rt2800_get_survey
);
6954 MODULE_AUTHOR(DRV_PROJECT
", Bartlomiej Zolnierkiewicz");
6955 MODULE_VERSION(DRV_VERSION
);
6956 MODULE_DESCRIPTION("Ralink RT2800 library");
6957 MODULE_LICENSE("GPL");