| blob | 47aceaea5d665aa9b12f7e47170ba3750228c250 |
1 /*
2 Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
4 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
5 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
6 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
7 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
8 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
9 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
10 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
11 <http://rt2x00.serialmonkey.com>
13 This program is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2 of the License, or
16 (at your option) any later version.
18 This program is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with this program; if not, write to the
25 Free Software Foundation, Inc.,
26 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 */
29 /*
30 Module: rt2800
31 Abstract: Data structures and registers for the rt2800 modules.
32 Supported chipsets: RT2800E, RT2800ED & RT2800U.
33 */
35 #ifndef RT2800_H
36 #define RT2800_H
38 /*
39 * RF chip defines.
40 *
41 * RF2820 2.4G 2T3R
42 * RF2850 2.4G/5G 2T3R
43 * RF2720 2.4G 1T2R
44 * RF2750 2.4G/5G 1T2R
45 * RF3020 2.4G 1T1R
46 * RF2020 2.4G B/G
47 * RF3021 2.4G 1T2R
48 * RF3022 2.4G 2T2R
49 * RF3052 2.4G/5G 2T2R
50 * RF2853 2.4G/5G 3T3R
51 * RF3320 2.4G 1T1R(RT3350/RT3370/RT3390)
52 * RF3322 2.4G 2T2R(RT3352/RT3371/RT3372/RT3391/RT3392)
53 * RF3053 2.4G/5G 3T3R(RT3883/RT3563/RT3573/RT3593/RT3662)
54 * RF5592 2.4G/5G 2T2R
55 * RF5360 2.4G 1T1R
56 * RF5370 2.4G 1T1R
57 * RF5390 2.4G 1T1R
58 */
59 #define RF2820 0x0001
60 #define RF2850 0x0002
61 #define RF2720 0x0003
62 #define RF2750 0x0004
63 #define RF3020 0x0005
64 #define RF2020 0x0006
65 #define RF3021 0x0007
66 #define RF3022 0x0008
67 #define RF3052 0x0009
68 #define RF2853 0x000a
69 #define RF3320 0x000b
70 #define RF3322 0x000c
71 #define RF3053 0x000d
72 #define RF5592 0x000f
73 #define RF3290 0x3290
74 #define RF5360 0x5360
75 #define RF5370 0x5370
76 #define RF5372 0x5372
77 #define RF5390 0x5390
78 #define RF5392 0x5392
80 /*
81 * Chipset revisions.
82 */
83 #define REV_RT2860C 0x0100
84 #define REV_RT2860D 0x0101
85 #define REV_RT2872E 0x0200
86 #define REV_RT3070E 0x0200
87 #define REV_RT3070F 0x0201
88 #define REV_RT3071E 0x0211
89 #define REV_RT3090E 0x0211
90 #define REV_RT3390E 0x0211
91 #define REV_RT3593E 0x0211
92 #define REV_RT5390F 0x0502
93 #define REV_RT5390R 0x1502
94 #define REV_RT5592C 0x0221
96 #define DEFAULT_RSSI_OFFSET 120
98 /*
99 * Register layout information.
100 */
101 #define CSR_REG_BASE 0x1000
102 #define CSR_REG_SIZE 0x0800
103 #define EEPROM_BASE 0x0000
104 #define EEPROM_SIZE 0x0200
105 #define BBP_BASE 0x0000
106 #define BBP_SIZE 0x00ff
107 #define RF_BASE 0x0004
108 #define RF_SIZE 0x0010
109 #define RFCSR_BASE 0x0000
110 #define RFCSR_SIZE 0x0040
112 /*
113 * Number of TX queues.
114 */
115 #define NUM_TX_QUEUES 4
117 /*
118 * Registers.
119 */
122 /*
123 * MAC_CSR0_3290: MAC_CSR0 for RT3290 to identity MAC version number.
124 */
125 #define MAC_CSR0_3290 0x0000
127 /*
128 * E2PROM_CSR: PCI EEPROM control register.
129 * RELOAD: Write 1 to reload eeprom content.
130 * TYPE: 0: 93c46, 1:93c66.
131 * LOAD_STATUS: 1:loading, 0:done.
132 */
133 #define E2PROM_CSR 0x0004
134 #define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001)
135 #define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002)
136 #define E2PROM_CSR_DATA_IN FIELD32(0x00000004)
137 #define E2PROM_CSR_DATA_OUT FIELD32(0x00000008)
138 #define E2PROM_CSR_TYPE FIELD32(0x00000030)
139 #define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
140 #define E2PROM_CSR_RELOAD FIELD32(0x00000080)
142 /*
143 * CMB_CTRL_CFG
144 */
145 #define CMB_CTRL 0x0020
146 #define AUX_OPT_BIT0 FIELD32(0x00000001)
147 #define AUX_OPT_BIT1 FIELD32(0x00000002)
148 #define AUX_OPT_BIT2 FIELD32(0x00000004)
149 #define AUX_OPT_BIT3 FIELD32(0x00000008)
150 #define AUX_OPT_BIT4 FIELD32(0x00000010)
151 #define AUX_OPT_BIT5 FIELD32(0x00000020)
152 #define AUX_OPT_BIT6 FIELD32(0x00000040)
153 #define AUX_OPT_BIT7 FIELD32(0x00000080)
154 #define AUX_OPT_BIT8 FIELD32(0x00000100)
155 #define AUX_OPT_BIT9 FIELD32(0x00000200)
156 #define AUX_OPT_BIT10 FIELD32(0x00000400)
157 #define AUX_OPT_BIT11 FIELD32(0x00000800)
158 #define AUX_OPT_BIT12 FIELD32(0x00001000)
159 #define AUX_OPT_BIT13 FIELD32(0x00002000)
160 #define AUX_OPT_BIT14 FIELD32(0x00004000)
161 #define AUX_OPT_BIT15 FIELD32(0x00008000)
162 #define LDO25_LEVEL FIELD32(0x00030000)
163 #define LDO25_LARGEA FIELD32(0x00040000)
164 #define LDO25_FRC_ON FIELD32(0x00080000)
165 #define CMB_RSV FIELD32(0x00300000)
166 #define XTAL_RDY FIELD32(0x00400000)
167 #define PLL_LD FIELD32(0x00800000)
168 #define LDO_CORE_LEVEL FIELD32(0x0F000000)
169 #define LDO_BGSEL FIELD32(0x30000000)
170 #define LDO3_EN FIELD32(0x40000000)
171 #define LDO0_EN FIELD32(0x80000000)
173 /*
174 * EFUSE_CSR_3290: RT3290 EEPROM
175 */
176 #define EFUSE_CTRL_3290 0x0024
178 /*
179 * EFUSE_DATA3 of 3290
180 */
181 #define EFUSE_DATA3_3290 0x0028
183 /*
184 * EFUSE_DATA2 of 3290
185 */
186 #define EFUSE_DATA2_3290 0x002c
188 /*
189 * EFUSE_DATA1 of 3290
190 */
191 #define EFUSE_DATA1_3290 0x0030
193 /*
194 * EFUSE_DATA0 of 3290
195 */
196 #define EFUSE_DATA0_3290 0x0034
198 /*
199 * OSC_CTRL_CFG
200 * Ring oscillator configuration
201 */
202 #define OSC_CTRL 0x0038
203 #define OSC_REF_CYCLE FIELD32(0x00001fff)
204 #define OSC_RSV FIELD32(0x0000e000)
205 #define OSC_CAL_CNT FIELD32(0x0fff0000)
206 #define OSC_CAL_ACK FIELD32(0x10000000)
207 #define OSC_CLK_32K_VLD FIELD32(0x20000000)
208 #define OSC_CAL_REQ FIELD32(0x40000000)
209 #define OSC_ROSC_EN FIELD32(0x80000000)
211 /*
212 * COEX_CFG_0
213 */
214 #define COEX_CFG0 0x0040
215 #define COEX_CFG_ANT FIELD32(0xff000000)
216 /*
217 * COEX_CFG_1
218 */
219 #define COEX_CFG1 0x0044
221 /*
222 * COEX_CFG_2
223 */
224 #define COEX_CFG2 0x0048
225 #define BT_COEX_CFG1 FIELD32(0xff000000)
226 #define BT_COEX_CFG0 FIELD32(0x00ff0000)
227 #define WL_COEX_CFG1 FIELD32(0x0000ff00)
228 #define WL_COEX_CFG0 FIELD32(0x000000ff)
229 /*
230 * PLL_CTRL_CFG
231 * PLL configuration register
232 */
233 #define PLL_CTRL 0x0050
234 #define PLL_RESERVED_INPUT1 FIELD32(0x000000ff)
235 #define PLL_RESERVED_INPUT2 FIELD32(0x0000ff00)
236 #define PLL_CONTROL FIELD32(0x00070000)
237 #define PLL_LPF_R1 FIELD32(0x00080000)
238 #define PLL_LPF_C1_CTRL FIELD32(0x00300000)
239 #define PLL_LPF_C2_CTRL FIELD32(0x00c00000)
240 #define PLL_CP_CURRENT_CTRL FIELD32(0x03000000)
241 #define PLL_PFD_DELAY_CTRL FIELD32(0x0c000000)
242 #define PLL_LOCK_CTRL FIELD32(0x70000000)
243 #define PLL_VBGBK_EN FIELD32(0x80000000)
246 /*
247 * WLAN_CTRL_CFG
248 * RT3290 wlan configuration
249 */
250 #define WLAN_FUN_CTRL 0x0080
251 #define WLAN_EN FIELD32(0x00000001)
252 #define WLAN_CLK_EN FIELD32(0x00000002)
253 #define WLAN_RSV1 FIELD32(0x00000004)
254 #define WLAN_RESET FIELD32(0x00000008)
255 #define PCIE_APP0_CLK_REQ FIELD32(0x00000010)
256 #define FRC_WL_ANT_SET FIELD32(0x00000020)
257 #define INV_TR_SW0 FIELD32(0x00000040)
258 #define WLAN_GPIO_IN_BIT0 FIELD32(0x00000100)
259 #define WLAN_GPIO_IN_BIT1 FIELD32(0x00000200)
260 #define WLAN_GPIO_IN_BIT2 FIELD32(0x00000400)
261 #define WLAN_GPIO_IN_BIT3 FIELD32(0x00000800)
262 #define WLAN_GPIO_IN_BIT4 FIELD32(0x00001000)
263 #define WLAN_GPIO_IN_BIT5 FIELD32(0x00002000)
264 #define WLAN_GPIO_IN_BIT6 FIELD32(0x00004000)
265 #define WLAN_GPIO_IN_BIT7 FIELD32(0x00008000)
266 #define WLAN_GPIO_IN_BIT_ALL FIELD32(0x0000ff00)
267 #define WLAN_GPIO_OUT_BIT0 FIELD32(0x00010000)
268 #define WLAN_GPIO_OUT_BIT1 FIELD32(0x00020000)
269 #define WLAN_GPIO_OUT_BIT2 FIELD32(0x00040000)
270 #define WLAN_GPIO_OUT_BIT3 FIELD32(0x00050000)
271 #define WLAN_GPIO_OUT_BIT4 FIELD32(0x00100000)
272 #define WLAN_GPIO_OUT_BIT5 FIELD32(0x00200000)
273 #define WLAN_GPIO_OUT_BIT6 FIELD32(0x00400000)
274 #define WLAN_GPIO_OUT_BIT7 FIELD32(0x00800000)
275 #define WLAN_GPIO_OUT_BIT_ALL FIELD32(0x00ff0000)
276 #define WLAN_GPIO_OUT_OE_BIT0 FIELD32(0x01000000)
277 #define WLAN_GPIO_OUT_OE_BIT1 FIELD32(0x02000000)
278 #define WLAN_GPIO_OUT_OE_BIT2 FIELD32(0x04000000)
279 #define WLAN_GPIO_OUT_OE_BIT3 FIELD32(0x08000000)
280 #define WLAN_GPIO_OUT_OE_BIT4 FIELD32(0x10000000)
281 #define WLAN_GPIO_OUT_OE_BIT5 FIELD32(0x20000000)
282 #define WLAN_GPIO_OUT_OE_BIT6 FIELD32(0x40000000)
283 #define WLAN_GPIO_OUT_OE_BIT7 FIELD32(0x80000000)
284 #define WLAN_GPIO_OUT_OE_BIT_ALL FIELD32(0xff000000)
286 /*
287 * AUX_CTRL: Aux/PCI-E related configuration
288 */
289 #define AUX_CTRL 0x10c
290 #define AUX_CTRL_WAKE_PCIE_EN FIELD32(0x00000002)
291 #define AUX_CTRL_FORCE_PCIE_CLK FIELD32(0x00000400)
293 /*
294 * OPT_14: Unknown register used by rt3xxx devices.
295 */
296 #define OPT_14_CSR 0x0114
297 #define OPT_14_CSR_BIT0 FIELD32(0x00000001)
299 /*
300 * INT_SOURCE_CSR: Interrupt source register.
301 * Write one to clear corresponding bit.
302 * TX_FIFO_STATUS: FIFO Statistics is full, sw should read TX_STA_FIFO
303 */
304 #define INT_SOURCE_CSR 0x0200
305 #define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
306 #define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
307 #define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
308 #define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
309 #define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
310 #define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
311 #define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
312 #define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
313 #define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
314 #define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
315 #define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
316 #define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
317 #define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
318 #define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
319 #define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
320 #define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
321 #define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
322 #define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
324 /*
325 * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
326 */
327 #define INT_MASK_CSR 0x0204
328 #define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
329 #define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
330 #define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
331 #define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
332 #define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
333 #define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
334 #define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
335 #define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
336 #define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
337 #define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
338 #define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
339 #define INT_MASK_CSR_TBTT FIELD32(0x00000800)
340 #define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
341 #define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
342 #define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
343 #define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
344 #define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
345 #define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
347 /*
348 * WPDMA_GLO_CFG
349 */
350 #define WPDMA_GLO_CFG 0x0208
351 #define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
352 #define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
353 #define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
354 #define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
355 #define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
356 #define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
357 #define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
358 #define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
359 #define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
361 /*
362 * WPDMA_RST_IDX
363 */
364 #define WPDMA_RST_IDX 0x020c
365 #define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
366 #define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
367 #define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
368 #define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
369 #define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
370 #define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
371 #define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
373 /*
374 * DELAY_INT_CFG
375 */
376 #define DELAY_INT_CFG 0x0210
377 #define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
378 #define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
379 #define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
380 #define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
381 #define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
382 #define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
384 /*
385 * WMM_AIFSN_CFG: Aifsn for each EDCA AC
386 * AIFSN0: AC_VO
387 * AIFSN1: AC_VI
388 * AIFSN2: AC_BE
389 * AIFSN3: AC_BK
390 */
391 #define WMM_AIFSN_CFG 0x0214
392 #define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
393 #define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
394 #define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
395 #define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
397 /*
398 * WMM_CWMIN_CSR: CWmin for each EDCA AC
399 * CWMIN0: AC_VO
400 * CWMIN1: AC_VI
401 * CWMIN2: AC_BE
402 * CWMIN3: AC_BK
403 */
404 #define WMM_CWMIN_CFG 0x0218
405 #define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
406 #define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
407 #define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
408 #define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
410 /*
411 * WMM_CWMAX_CSR: CWmax for each EDCA AC
412 * CWMAX0: AC_VO
413 * CWMAX1: AC_VI
414 * CWMAX2: AC_BE
415 * CWMAX3: AC_BK
416 */
417 #define WMM_CWMAX_CFG 0x021c
418 #define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
419 #define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
420 #define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
421 #define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
423 /*
424 * AC_TXOP0: AC_VO/AC_VI TXOP register
425 * AC0TXOP: AC_VO in unit of 32us
426 * AC1TXOP: AC_VI in unit of 32us
427 */
428 #define WMM_TXOP0_CFG 0x0220
429 #define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
430 #define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
432 /*
433 * AC_TXOP1: AC_BE/AC_BK TXOP register
434 * AC2TXOP: AC_BE in unit of 32us
435 * AC3TXOP: AC_BK in unit of 32us
436 */
437 #define WMM_TXOP1_CFG 0x0224
438 #define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
439 #define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
441 /*
442 * GPIO_CTRL:
443 * GPIO_CTRL_VALx: GPIO value
444 * GPIO_CTRL_DIRx: GPIO direction: 0 = output; 1 = input
445 */
446 #define GPIO_CTRL 0x0228
447 #define GPIO_CTRL_VAL0 FIELD32(0x00000001)
448 #define GPIO_CTRL_VAL1 FIELD32(0x00000002)
449 #define GPIO_CTRL_VAL2 FIELD32(0x00000004)
450 #define GPIO_CTRL_VAL3 FIELD32(0x00000008)
451 #define GPIO_CTRL_VAL4 FIELD32(0x00000010)
452 #define GPIO_CTRL_VAL5 FIELD32(0x00000020)
453 #define GPIO_CTRL_VAL6 FIELD32(0x00000040)
454 #define GPIO_CTRL_VAL7 FIELD32(0x00000080)
455 #define GPIO_CTRL_DIR0 FIELD32(0x00000100)
456 #define GPIO_CTRL_DIR1 FIELD32(0x00000200)
457 #define GPIO_CTRL_DIR2 FIELD32(0x00000400)
458 #define GPIO_CTRL_DIR3 FIELD32(0x00000800)
459 #define GPIO_CTRL_DIR4 FIELD32(0x00001000)
460 #define GPIO_CTRL_DIR5 FIELD32(0x00002000)
461 #define GPIO_CTRL_DIR6 FIELD32(0x00004000)
462 #define GPIO_CTRL_DIR7 FIELD32(0x00008000)
463 #define GPIO_CTRL_VAL8 FIELD32(0x00010000)
464 #define GPIO_CTRL_VAL9 FIELD32(0x00020000)
465 #define GPIO_CTRL_VAL10 FIELD32(0x00040000)
466 #define GPIO_CTRL_DIR8 FIELD32(0x01000000)
467 #define GPIO_CTRL_DIR9 FIELD32(0x02000000)
468 #define GPIO_CTRL_DIR10 FIELD32(0x04000000)
470 /*
471 * MCU_CMD_CFG
472 */
473 #define MCU_CMD_CFG 0x022c
475 /*
476 * AC_VO register offsets
477 */
478 #define TX_BASE_PTR0 0x0230
479 #define TX_MAX_CNT0 0x0234
480 #define TX_CTX_IDX0 0x0238
481 #define TX_DTX_IDX0 0x023c
483 /*
484 * AC_VI register offsets
485 */
486 #define TX_BASE_PTR1 0x0240
487 #define TX_MAX_CNT1 0x0244
488 #define TX_CTX_IDX1 0x0248
489 #define TX_DTX_IDX1 0x024c
491 /*
492 * AC_BE register offsets
493 */
494 #define TX_BASE_PTR2 0x0250
495 #define TX_MAX_CNT2 0x0254
496 #define TX_CTX_IDX2 0x0258
497 #define TX_DTX_IDX2 0x025c
499 /*
500 * AC_BK register offsets
501 */
502 #define TX_BASE_PTR3 0x0260
503 #define TX_MAX_CNT3 0x0264
504 #define TX_CTX_IDX3 0x0268
505 #define TX_DTX_IDX3 0x026c
507 /*
508 * HCCA register offsets
509 */
510 #define TX_BASE_PTR4 0x0270
511 #define TX_MAX_CNT4 0x0274
512 #define TX_CTX_IDX4 0x0278
513 #define TX_DTX_IDX4 0x027c
515 /*
516 * MGMT register offsets
517 */
518 #define TX_BASE_PTR5 0x0280
519 #define TX_MAX_CNT5 0x0284
520 #define TX_CTX_IDX5 0x0288
521 #define TX_DTX_IDX5 0x028c
523 /*
524 * RX register offsets
525 */
526 #define RX_BASE_PTR 0x0290
527 #define RX_MAX_CNT 0x0294
528 #define RX_CRX_IDX 0x0298
529 #define RX_DRX_IDX 0x029c
531 /*
532 * USB_DMA_CFG
533 * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns.
534 * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes.
535 * PHY_CLEAR: phy watch dog enable.
536 * TX_CLEAR: Clear USB DMA TX path.
537 * TXOP_HALT: Halt TXOP count down when TX buffer is full.
538 * RX_BULK_AGG_EN: Enable Rx Bulk Aggregation.
539 * RX_BULK_EN: Enable USB DMA Rx.
540 * TX_BULK_EN: Enable USB DMA Tx.
541 * EP_OUT_VALID: OUT endpoint data valid.
542 * RX_BUSY: USB DMA RX FSM busy.
543 * TX_BUSY: USB DMA TX FSM busy.
544 */
545 #define USB_DMA_CFG 0x02a0
546 #define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT FIELD32(0x000000ff)
547 #define USB_DMA_CFG_RX_BULK_AGG_LIMIT FIELD32(0x0000ff00)
548 #define USB_DMA_CFG_PHY_CLEAR FIELD32(0x00010000)
549 #define USB_DMA_CFG_TX_CLEAR FIELD32(0x00080000)
550 #define USB_DMA_CFG_TXOP_HALT FIELD32(0x00100000)
551 #define USB_DMA_CFG_RX_BULK_AGG_EN FIELD32(0x00200000)
552 #define USB_DMA_CFG_RX_BULK_EN FIELD32(0x00400000)
553 #define USB_DMA_CFG_TX_BULK_EN FIELD32(0x00800000)
554 #define USB_DMA_CFG_EP_OUT_VALID FIELD32(0x3f000000)
555 #define USB_DMA_CFG_RX_BUSY FIELD32(0x40000000)
556 #define USB_DMA_CFG_TX_BUSY FIELD32(0x80000000)
558 /*
559 * US_CYC_CNT
560 * BT_MODE_EN: Bluetooth mode enable
561 * CLOCK CYCLE: Clock cycle count in 1us.
562 * PCI:0x21, PCIE:0x7d, USB:0x1e
563 */
564 #define US_CYC_CNT 0x02a4
565 #define US_CYC_CNT_BT_MODE_EN FIELD32(0x00000100)
566 #define US_CYC_CNT_CLOCK_CYCLE FIELD32(0x000000ff)
568 /*
569 * PBF_SYS_CTRL
570 * HOST_RAM_WRITE: enable Host program ram write selection
571 */
572 #define PBF_SYS_CTRL 0x0400
573 #define PBF_SYS_CTRL_READY FIELD32(0x00000080)
574 #define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
576 /*
577 * HOST-MCU shared memory
578 */
579 #define HOST_CMD_CSR 0x0404
580 #define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
582 /*
583 * PBF registers
584 * Most are for debug. Driver doesn't touch PBF register.
585 */
586 #define PBF_CFG 0x0408
587 #define PBF_MAX_PCNT 0x040c
588 #define PBF_CTRL 0x0410
589 #define PBF_INT_STA 0x0414
590 #define PBF_INT_ENA 0x0418
592 /*
593 * BCN_OFFSET0:
594 */
595 #define BCN_OFFSET0 0x042c
596 #define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
597 #define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
598 #define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
599 #define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
601 /*
602 * BCN_OFFSET1:
603 */
604 #define BCN_OFFSET1 0x0430
605 #define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
606 #define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
607 #define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
608 #define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
610 /*
611 * TXRXQ_PCNT: PBF register
612 * PCNT_TX0Q: Page count for TX hardware queue 0
613 * PCNT_TX1Q: Page count for TX hardware queue 1
614 * PCNT_TX2Q: Page count for TX hardware queue 2
615 * PCNT_RX0Q: Page count for RX hardware queue
616 */
617 #define TXRXQ_PCNT 0x0438
618 #define TXRXQ_PCNT_TX0Q FIELD32(0x000000ff)
619 #define TXRXQ_PCNT_TX1Q FIELD32(0x0000ff00)
620 #define TXRXQ_PCNT_TX2Q FIELD32(0x00ff0000)
621 #define TXRXQ_PCNT_RX0Q FIELD32(0xff000000)
623 /*
624 * PBF register
625 * Debug. Driver doesn't touch PBF register.
626 */
627 #define PBF_DBG 0x043c
629 /*
630 * RF registers
631 */
632 #define RF_CSR_CFG 0x0500
633 #define RF_CSR_CFG_DATA FIELD32(0x000000ff)
634 #define RF_CSR_CFG_REGNUM FIELD32(0x00003f00)
635 #define RF_CSR_CFG_WRITE FIELD32(0x00010000)
636 #define RF_CSR_CFG_BUSY FIELD32(0x00020000)
638 /*
639 * EFUSE_CSR: RT30x0 EEPROM
640 */
641 #define EFUSE_CTRL 0x0580
642 #define EFUSE_CTRL_ADDRESS_IN FIELD32(0x03fe0000)
643 #define EFUSE_CTRL_MODE FIELD32(0x000000c0)
644 #define EFUSE_CTRL_KICK FIELD32(0x40000000)
645 #define EFUSE_CTRL_PRESENT FIELD32(0x80000000)
647 /*
648 * EFUSE_DATA0
649 */
650 #define EFUSE_DATA0 0x0590
652 /*
653 * EFUSE_DATA1
654 */
655 #define EFUSE_DATA1 0x0594
657 /*
658 * EFUSE_DATA2
659 */
660 #define EFUSE_DATA2 0x0598
662 /*
663 * EFUSE_DATA3
664 */
665 #define EFUSE_DATA3 0x059c
667 /*
668 * LDO_CFG0
669 */
670 #define LDO_CFG0 0x05d4
671 #define LDO_CFG0_DELAY3 FIELD32(0x000000ff)
672 #define LDO_CFG0_DELAY2 FIELD32(0x0000ff00)
673 #define LDO_CFG0_DELAY1 FIELD32(0x00ff0000)
674 #define LDO_CFG0_BGSEL FIELD32(0x03000000)
675 #define LDO_CFG0_LDO_CORE_VLEVEL FIELD32(0x1c000000)
676 #define LD0_CFG0_LDO25_LEVEL FIELD32(0x60000000)
677 #define LDO_CFG0_LDO25_LARGEA FIELD32(0x80000000)
679 /*
680 * GPIO_SWITCH
681 */
682 #define GPIO_SWITCH 0x05dc
683 #define GPIO_SWITCH_0 FIELD32(0x00000001)
684 #define GPIO_SWITCH_1 FIELD32(0x00000002)
685 #define GPIO_SWITCH_2 FIELD32(0x00000004)
686 #define GPIO_SWITCH_3 FIELD32(0x00000008)
687 #define GPIO_SWITCH_4 FIELD32(0x00000010)
688 #define GPIO_SWITCH_5 FIELD32(0x00000020)
689 #define GPIO_SWITCH_6 FIELD32(0x00000040)
690 #define GPIO_SWITCH_7 FIELD32(0x00000080)
692 /*
693 * FIXME: where the DEBUG_INDEX name come from?
694 */
695 #define MAC_DEBUG_INDEX 0x05e8
696 #define MAC_DEBUG_INDEX_XTAL FIELD32(0x80000000)
698 /*
699 * MAC Control/Status Registers(CSR).
700 * Some values are set in TU, whereas 1 TU == 1024 us.
701 */
703 /*
704 * MAC_CSR0: ASIC revision number.
705 * ASIC_REV: 0
706 * ASIC_VER: 2860 or 2870
707 */
708 #define MAC_CSR0 0x1000
709 #define MAC_CSR0_REVISION FIELD32(0x0000ffff)
710 #define MAC_CSR0_CHIPSET FIELD32(0xffff0000)
712 /*
713 * MAC_SYS_CTRL:
714 */
715 #define MAC_SYS_CTRL 0x1004
716 #define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
717 #define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
718 #define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
719 #define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
720 #define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
721 #define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
722 #define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
723 #define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
725 /*
726 * MAC_ADDR_DW0: STA MAC register 0
727 */
728 #define MAC_ADDR_DW0 0x1008
729 #define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
730 #define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
731 #define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
732 #define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
734 /*
735 * MAC_ADDR_DW1: STA MAC register 1
736 * UNICAST_TO_ME_MASK:
737 * Used to mask off bits from byte 5 of the MAC address
738 * to determine the UNICAST_TO_ME bit for RX frames.
739 * The full mask is complemented by BSS_ID_MASK:
740 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
741 */
742 #define MAC_ADDR_DW1 0x100c
743 #define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
744 #define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
745 #define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
747 /*
748 * MAC_BSSID_DW0: BSSID register 0
749 */
750 #define MAC_BSSID_DW0 0x1010
751 #define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
752 #define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
753 #define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
754 #define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
756 /*
757 * MAC_BSSID_DW1: BSSID register 1
758 * BSS_ID_MASK:
759 * 0: 1-BSSID mode (BSS index = 0)
760 * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
761 * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
762 * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
763 * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
764 * BSSID. This will make sure that those bits will be ignored
765 * when determining the MY_BSS of RX frames.
766 */
767 #define MAC_BSSID_DW1 0x1014
768 #define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
769 #define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
770 #define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
771 #define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
773 /*
774 * MAX_LEN_CFG: Maximum frame length register.
775 * MAX_MPDU: rt2860b max 16k bytes
776 * MAX_PSDU: Maximum PSDU length
777 * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
778 */
779 #define MAX_LEN_CFG 0x1018
780 #define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
781 #define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
782 #define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
783 #define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
785 /*
786 * BBP_CSR_CFG: BBP serial control register
787 * VALUE: Register value to program into BBP
788 * REG_NUM: Selected BBP register
789 * READ_CONTROL: 0 write BBP, 1 read BBP
790 * BUSY: ASIC is busy executing BBP commands
791 * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
792 * BBP_RW_MODE: 0 serial, 1 parallel
793 */
794 #define BBP_CSR_CFG 0x101c
795 #define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
796 #define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
797 #define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
798 #define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
799 #define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
800 #define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
802 /*
803 * RF_CSR_CFG0: RF control register
804 * REGID_AND_VALUE: Register value to program into RF
805 * BITWIDTH: Selected RF register
806 * STANDBYMODE: 0 high when standby, 1 low when standby
807 * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
808 * BUSY: ASIC is busy executing RF commands
809 */
810 #define RF_CSR_CFG0 0x1020
811 #define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
812 #define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
813 #define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
814 #define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
815 #define RF_CSR_CFG0_SEL FIELD32(0x40000000)
816 #define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
818 /*
819 * RF_CSR_CFG1: RF control register
820 * REGID_AND_VALUE: Register value to program into RF
821 * RFGAP: Gap between BB_CONTROL_RF and RF_LE
822 * 0: 3 system clock cycle (37.5usec)
823 * 1: 5 system clock cycle (62.5usec)
824 */
825 #define RF_CSR_CFG1 0x1024
826 #define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
827 #define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
829 /*
830 * RF_CSR_CFG2: RF control register
831 * VALUE: Register value to program into RF
832 */
833 #define RF_CSR_CFG2 0x1028
834 #define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
836 /*
837 * LED_CFG: LED control
838 * ON_PERIOD: LED active time (ms) during TX (only used for LED mode 1)
839 * OFF_PERIOD: LED inactive time (ms) during TX (only used for LED mode 1)
840 * SLOW_BLINK_PERIOD: LED blink interval in seconds (only used for LED mode 2)
841 * color LED's:
842 * 0: off
843 * 1: blinking upon TX2
844 * 2: periodic slow blinking
845 * 3: always on
846 * LED polarity:
847 * 0: active low
848 * 1: active high
849 */
850 #define LED_CFG 0x102c
851 #define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
852 #define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
853 #define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
854 #define LED_CFG_R_LED_MODE FIELD32(0x03000000)
855 #define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
856 #define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
857 #define LED_CFG_LED_POLAR FIELD32(0x40000000)
859 /*
860 * AMPDU_BA_WINSIZE: Force BlockAck window size
861 * FORCE_WINSIZE_ENABLE:
862 * 0: Disable forcing of BlockAck window size
863 * 1: Enable forcing of BlockAck window size, overwrites values BlockAck
864 * window size values in the TXWI
865 * FORCE_WINSIZE: BlockAck window size
866 */
867 #define AMPDU_BA_WINSIZE 0x1040
868 #define AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE FIELD32(0x00000020)
869 #define AMPDU_BA_WINSIZE_FORCE_WINSIZE FIELD32(0x0000001f)
871 /*
872 * XIFS_TIME_CFG: MAC timing
873 * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
874 * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
875 * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
876 * when MAC doesn't reference BBP signal BBRXEND
877 * EIFS: unit 1us
878 * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
879 *
880 */
881 #define XIFS_TIME_CFG 0x1100
882 #define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
883 #define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
884 #define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
885 #define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
886 #define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
888 /*
889 * BKOFF_SLOT_CFG:
890 */
891 #define BKOFF_SLOT_CFG 0x1104
892 #define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
893 #define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
895 /*
896 * NAV_TIME_CFG:
897 */
898 #define NAV_TIME_CFG 0x1108
899 #define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
900 #define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
901 #define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
902 #define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
904 /*
905 * CH_TIME_CFG: count as channel busy
906 * EIFS_BUSY: Count EIFS as channel busy
907 * NAV_BUSY: Count NAS as channel busy
908 * RX_BUSY: Count RX as channel busy
909 * TX_BUSY: Count TX as channel busy
910 * TMR_EN: Enable channel statistics timer
911 */
912 #define CH_TIME_CFG 0x110c
913 #define CH_TIME_CFG_EIFS_BUSY FIELD32(0x00000010)
914 #define CH_TIME_CFG_NAV_BUSY FIELD32(0x00000008)
915 #define CH_TIME_CFG_RX_BUSY FIELD32(0x00000004)
916 #define CH_TIME_CFG_TX_BUSY FIELD32(0x00000002)
917 #define CH_TIME_CFG_TMR_EN FIELD32(0x00000001)
919 /*
920 * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
921 */
922 #define PBF_LIFE_TIMER 0x1110
924 /*
925 * BCN_TIME_CFG:
926 * BEACON_INTERVAL: in unit of 1/16 TU
927 * TSF_TICKING: Enable TSF auto counting
928 * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
929 * BEACON_GEN: Enable beacon generator
930 */
931 #define BCN_TIME_CFG 0x1114
932 #define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
933 #define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
934 #define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
935 #define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
936 #define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
937 #define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
939 /*
940 * TBTT_SYNC_CFG:
941 * BCN_AIFSN: Beacon AIFSN after TBTT interrupt in slots
942 * BCN_CWMIN: Beacon CWMin after TBTT interrupt in slots
943 */
944 #define TBTT_SYNC_CFG 0x1118
945 #define TBTT_SYNC_CFG_TBTT_ADJUST FIELD32(0x000000ff)
946 #define TBTT_SYNC_CFG_BCN_EXP_WIN FIELD32(0x0000ff00)
947 #define TBTT_SYNC_CFG_BCN_AIFSN FIELD32(0x000f0000)
948 #define TBTT_SYNC_CFG_BCN_CWMIN FIELD32(0x00f00000)
950 /*
951 * TSF_TIMER_DW0: Local lsb TSF timer, read-only
952 */
953 #define TSF_TIMER_DW0 0x111c
954 #define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
956 /*
957 * TSF_TIMER_DW1: Local msb TSF timer, read-only
958 */
959 #define TSF_TIMER_DW1 0x1120
960 #define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
962 /*
963 * TBTT_TIMER: TImer remains till next TBTT, read-only
964 */
965 #define TBTT_TIMER 0x1124
967 /*
968 * INT_TIMER_CFG: timer configuration
969 * PRE_TBTT_TIMER: leadtime to tbtt for pretbtt interrupt in units of 1/16 TU
970 * GP_TIMER: period of general purpose timer in units of 1/16 TU
971 */
972 #define INT_TIMER_CFG 0x1128
973 #define INT_TIMER_CFG_PRE_TBTT_TIMER FIELD32(0x0000ffff)
974 #define INT_TIMER_CFG_GP_TIMER FIELD32(0xffff0000)
976 /*
977 * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
978 */
979 #define INT_TIMER_EN 0x112c
980 #define INT_TIMER_EN_PRE_TBTT_TIMER FIELD32(0x00000001)
981 #define INT_TIMER_EN_GP_TIMER FIELD32(0x00000002)
983 /*
984 * CH_IDLE_STA: channel idle time (in us)
985 */
986 #define CH_IDLE_STA 0x1130
988 /*
989 * CH_BUSY_STA: channel busy time on primary channel (in us)
990 */
991 #define CH_BUSY_STA 0x1134
993 /*
994 * CH_BUSY_STA_SEC: channel busy time on secondary channel in HT40 mode (in us)
995 */
996 #define CH_BUSY_STA_SEC 0x1138
998 /*
999 * MAC_STATUS_CFG:
1000 * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
1001 * if 1 or higher one of the 2 registers is busy.
1002 */
1003 #define MAC_STATUS_CFG 0x1200
1004 #define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
1006 /*
1007 * PWR_PIN_CFG:
1008 */
1009 #define PWR_PIN_CFG 0x1204
1011 /*
1012 * AUTOWAKEUP_CFG: Manual power control / status register
1013 * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
1014 * AUTOWAKE: 0:sleep, 1:awake
1015 */
1016 #define AUTOWAKEUP_CFG 0x1208
1017 #define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
1018 #define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
1019 #define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
1021 /*
1022 * EDCA_AC0_CFG:
1023 */
1024 #define EDCA_AC0_CFG 0x1300
1025 #define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
1026 #define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
1027 #define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
1028 #define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
1030 /*
1031 * EDCA_AC1_CFG:
1032 */
1033 #define EDCA_AC1_CFG 0x1304
1034 #define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
1035 #define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
1036 #define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
1037 #define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
1039 /*
1040 * EDCA_AC2_CFG:
1041 */
1042 #define EDCA_AC2_CFG 0x1308
1043 #define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
1044 #define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
1045 #define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
1046 #define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
1048 /*
1049 * EDCA_AC3_CFG:
1050 */
1051 #define EDCA_AC3_CFG 0x130c
1052 #define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
1053 #define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
1054 #define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
1055 #define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
1057 /*
1058 * EDCA_TID_AC_MAP:
1059 */
1060 #define EDCA_TID_AC_MAP 0x1310
1062 /*
1063 * TX_PWR_CFG:
1064 */
1065 #define TX_PWR_CFG_RATE0 FIELD32(0x0000000f)
1066 #define TX_PWR_CFG_RATE1 FIELD32(0x000000f0)
1067 #define TX_PWR_CFG_RATE2 FIELD32(0x00000f00)
1068 #define TX_PWR_CFG_RATE3 FIELD32(0x0000f000)
1069 #define TX_PWR_CFG_RATE4 FIELD32(0x000f0000)
1070 #define TX_PWR_CFG_RATE5 FIELD32(0x00f00000)
1071 #define TX_PWR_CFG_RATE6 FIELD32(0x0f000000)
1072 #define TX_PWR_CFG_RATE7 FIELD32(0xf0000000)
1074 /*
1075 * TX_PWR_CFG_0:
1076 */
1077 #define TX_PWR_CFG_0 0x1314
1078 #define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
1079 #define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
1080 #define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
1081 #define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
1082 #define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
1083 #define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
1084 #define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
1085 #define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
1087 /*
1088 * TX_PWR_CFG_1:
1089 */
1090 #define TX_PWR_CFG_1 0x1318
1091 #define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
1092 #define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
1093 #define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
1094 #define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
1095 #define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
1096 #define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
1097 #define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
1098 #define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
1100 /*
1101 * TX_PWR_CFG_2:
1102 */
1103 #define TX_PWR_CFG_2 0x131c
1104 #define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
1105 #define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
1106 #define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
1107 #define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
1108 #define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
1109 #define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
1110 #define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
1111 #define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
1113 /*
1114 * TX_PWR_CFG_3:
1115 */
1116 #define TX_PWR_CFG_3 0x1320
1117 #define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
1118 #define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
1119 #define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
1120 #define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
1121 #define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
1122 #define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
1123 #define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
1124 #define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
1126 /*
1127 * TX_PWR_CFG_4:
1128 */
1129 #define TX_PWR_CFG_4 0x1324
1130 #define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
1131 #define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
1132 #define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
1133 #define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
1135 /*
1136 * TX_PIN_CFG:
1137 */
1138 #define TX_PIN_CFG 0x1328
1139 #define TX_PIN_CFG_PA_PE_DISABLE 0xfcfffff0
1140 #define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
1141 #define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
1142 #define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
1143 #define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
1144 #define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
1145 #define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
1146 #define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
1147 #define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
1148 #define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
1149 #define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
1150 #define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
1151 #define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
1152 #define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
1153 #define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
1154 #define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
1155 #define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
1156 #define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
1157 #define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
1158 #define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
1159 #define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
1160 #define TX_PIN_CFG_PA_PE_A2_EN FIELD32(0x01000000)
1161 #define TX_PIN_CFG_PA_PE_G2_EN FIELD32(0x02000000)
1162 #define TX_PIN_CFG_PA_PE_A2_POL FIELD32(0x04000000)
1163 #define TX_PIN_CFG_PA_PE_G2_POL FIELD32(0x08000000)
1164 #define TX_PIN_CFG_LNA_PE_A2_EN FIELD32(0x10000000)
1165 #define TX_PIN_CFG_LNA_PE_G2_EN FIELD32(0x20000000)
1166 #define TX_PIN_CFG_LNA_PE_A2_POL FIELD32(0x40000000)
1167 #define TX_PIN_CFG_LNA_PE_G2_POL FIELD32(0x80000000)
1169 /*
1170 * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
1171 */
1172 #define TX_BAND_CFG 0x132c
1173 #define TX_BAND_CFG_HT40_MINUS FIELD32(0x00000001)
1174 #define TX_BAND_CFG_A FIELD32(0x00000002)
1175 #define TX_BAND_CFG_BG FIELD32(0x00000004)
1177 /*
1178 * TX_SW_CFG0:
1179 */
1180 #define TX_SW_CFG0 0x1330
1182 /*
1183 * TX_SW_CFG1:
1184 */
1185 #define TX_SW_CFG1 0x1334
1187 /*
1188 * TX_SW_CFG2:
1189 */
1190 #define TX_SW_CFG2 0x1338
1192 /*
1193 * TXOP_THRES_CFG:
1194 */
1195 #define TXOP_THRES_CFG 0x133c
1197 /*
1198 * TXOP_CTRL_CFG:
1199 * TIMEOUT_TRUN_EN: Enable/Disable TXOP timeout truncation
1200 * AC_TRUN_EN: Enable/Disable truncation for AC change
1201 * TXRATEGRP_TRUN_EN: Enable/Disable truncation for TX rate group change
1202 * USER_MODE_TRUN_EN: Enable/Disable truncation for user TXOP mode
1203 * MIMO_PS_TRUN_EN: Enable/Disable truncation for MIMO PS RTS/CTS
1204 * RESERVED_TRUN_EN: Reserved
1205 * LSIG_TXOP_EN: Enable/Disable L-SIG TXOP protection
1206 * EXT_CCA_EN: Enable/Disable extension channel CCA reference (Defer 40Mhz
1207 * transmissions if extension CCA is clear).
1208 * EXT_CCA_DLY: Extension CCA signal delay time (unit: us)
1209 * EXT_CWMIN: CwMin for extension channel backoff
1210 * 0: Disabled
1211 *
1212 */
1213 #define TXOP_CTRL_CFG 0x1340
1214 #define TXOP_CTRL_CFG_TIMEOUT_TRUN_EN FIELD32(0x00000001)
1215 #define TXOP_CTRL_CFG_AC_TRUN_EN FIELD32(0x00000002)
1216 #define TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN FIELD32(0x00000004)
1217 #define TXOP_CTRL_CFG_USER_MODE_TRUN_EN FIELD32(0x00000008)
1218 #define TXOP_CTRL_CFG_MIMO_PS_TRUN_EN FIELD32(0x00000010)
1219 #define TXOP_CTRL_CFG_RESERVED_TRUN_EN FIELD32(0x00000020)
1220 #define TXOP_CTRL_CFG_LSIG_TXOP_EN FIELD32(0x00000040)
1221 #define TXOP_CTRL_CFG_EXT_CCA_EN FIELD32(0x00000080)
1222 #define TXOP_CTRL_CFG_EXT_CCA_DLY FIELD32(0x0000ff00)
1223 #define TXOP_CTRL_CFG_EXT_CWMIN FIELD32(0x000f0000)
1225 /*
1226 * TX_RTS_CFG:
1227 * RTS_THRES: unit:byte
1228 * RTS_FBK_EN: enable rts rate fallback
1229 */
1230 #define TX_RTS_CFG 0x1344
1231 #define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
1232 #define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
1233 #define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
1235 /*
1236 * TX_TIMEOUT_CFG:
1237 * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
1238 * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
1239 * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
1240 * it is recommended that:
1241 * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
1242 */
1243 #define TX_TIMEOUT_CFG 0x1348
1244 #define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
1245 #define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
1246 #define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
1248 /*
1249 * TX_RTY_CFG:
1250 * SHORT_RTY_LIMIT: short retry limit
1251 * LONG_RTY_LIMIT: long retry limit
1252 * LONG_RTY_THRE: Long retry threshoold
1253 * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
1254 * 0:expired by retry limit, 1: expired by mpdu life timer
1255 * AGG_RTY_MODE: Aggregate MPDU retry mode
1256 * 0:expired by retry limit, 1: expired by mpdu life timer
1257 * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
1258 */
1259 #define TX_RTY_CFG 0x134c
1260 #define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
1261 #define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
1262 #define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
1263 #define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
1264 #define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
1265 #define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
1267 /*
1268 * TX_LINK_CFG:
1269 * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
1270 * MFB_ENABLE: TX apply remote MFB 1:enable
1271 * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
1272 * 0: not apply remote remote unsolicit (MFS=7)
1273 * TX_MRQ_EN: MCS request TX enable
1274 * TX_RDG_EN: RDG TX enable
1275 * TX_CF_ACK_EN: Piggyback CF-ACK enable
1276 * REMOTE_MFB: remote MCS feedback
1277 * REMOTE_MFS: remote MCS feedback sequence number
1278 */
1279 #define TX_LINK_CFG 0x1350
1280 #define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
1281 #define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
1282 #define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
1283 #define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
1284 #define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
1285 #define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
1286 #define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
1287 #define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
1289 /*
1290 * HT_FBK_CFG0:
1291 */
1292 #define HT_FBK_CFG0 0x1354
1293 #define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
1294 #define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
1295 #define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
1296 #define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
1297 #define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
1298 #define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
1299 #define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
1300 #define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
1302 /*
1303 * HT_FBK_CFG1:
1304 */
1305 #define HT_FBK_CFG1 0x1358
1306 #define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
1307 #define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
1308 #define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
1309 #define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
1310 #define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
1311 #define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
1312 #define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
1313 #define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
1315 /*
1316 * LG_FBK_CFG0:
1317 */
1318 #define LG_FBK_CFG0 0x135c
1319 #define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
1320 #define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
1321 #define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
1322 #define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
1323 #define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
1324 #define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
1325 #define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
1326 #define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
1328 /*
1329 * LG_FBK_CFG1:
1330 */
1331 #define LG_FBK_CFG1 0x1360
1332 #define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
1333 #define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
1334 #define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
1335 #define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
1337 /*
1338 * CCK_PROT_CFG: CCK Protection
1339 * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
1340 * PROTECT_CTRL: Protection control frame type for CCK TX
1341 * 0:none, 1:RTS/CTS, 2:CTS-to-self
1342 * PROTECT_NAV_SHORT: TXOP protection type for CCK TX with short NAV
1343 * PROTECT_NAV_LONG: TXOP protection type for CCK TX with long NAV
1344 * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
1345 * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
1346 * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
1347 * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
1348 * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
1349 * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
1350 * RTS_TH_EN: RTS threshold enable on CCK TX
1351 */
1352 #define CCK_PROT_CFG 0x1364
1353 #define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1354 #define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1355 #define CCK_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1356 #define CCK_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1357 #define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1358 #define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1359 #define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1360 #define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1361 #define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1362 #define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1363 #define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1365 /*
1366 * OFDM_PROT_CFG: OFDM Protection
1367 */
1368 #define OFDM_PROT_CFG 0x1368
1369 #define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1370 #define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1371 #define OFDM_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1372 #define OFDM_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1373 #define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1374 #define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1375 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1376 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1377 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1378 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1379 #define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1381 /*
1382 * MM20_PROT_CFG: MM20 Protection
1383 */
1384 #define MM20_PROT_CFG 0x136c
1385 #define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1386 #define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1387 #define MM20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1388 #define MM20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1389 #define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1390 #define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1391 #define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1392 #define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1393 #define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1394 #define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1395 #define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1397 /*
1398 * MM40_PROT_CFG: MM40 Protection
1399 */
1400 #define MM40_PROT_CFG 0x1370
1401 #define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1402 #define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1403 #define MM40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1404 #define MM40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1405 #define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1406 #define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1407 #define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1408 #define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1409 #define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1410 #define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1411 #define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1413 /*
1414 * GF20_PROT_CFG: GF20 Protection
1415 */
1416 #define GF20_PROT_CFG 0x1374
1417 #define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1418 #define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1419 #define GF20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1420 #define GF20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1421 #define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1422 #define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1423 #define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1424 #define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1425 #define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1426 #define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1427 #define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1429 /*
1430 * GF40_PROT_CFG: GF40 Protection
1431 */
1432 #define GF40_PROT_CFG 0x1378
1433 #define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1434 #define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1435 #define GF40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1436 #define GF40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1437 #define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1438 #define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1439 #define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1440 #define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1441 #define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1442 #define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1443 #define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1445 /*
1446 * EXP_CTS_TIME:
1447 */
1448 #define EXP_CTS_TIME 0x137c
1450 /*
1451 * EXP_ACK_TIME:
1452 */
1453 #define EXP_ACK_TIME 0x1380
1455 /*
1456 * RX_FILTER_CFG: RX configuration register.
1457 */
1458 #define RX_FILTER_CFG 0x1400
1459 #define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
1460 #define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
1461 #define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
1462 #define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
1463 #define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
1464 #define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
1465 #define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
1466 #define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
1467 #define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
1468 #define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
1469 #define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
1470 #define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
1471 #define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
1472 #define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
1473 #define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
1474 #define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
1475 #define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
1477 /*
1478 * AUTO_RSP_CFG:
1479 * AUTORESPONDER: 0: disable, 1: enable
1480 * BAC_ACK_POLICY: 0:long, 1:short preamble
1481 * CTS_40_MMODE: Response CTS 40MHz duplicate mode
1482 * CTS_40_MREF: Response CTS 40MHz duplicate mode
1483 * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
1484 * DUAL_CTS_EN: Power bit value in control frame
1485 * ACK_CTS_PSM_BIT:Power bit value in control frame
1486 */
1487 #define AUTO_RSP_CFG 0x1404
1488 #define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
1489 #define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
1490 #define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
1491 #define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
1492 #define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
1493 #define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
1494 #define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
1496 /*
1497 * LEGACY_BASIC_RATE:
1498 */
1499 #define LEGACY_BASIC_RATE 0x1408
1501 /*
1502 * HT_BASIC_RATE:
1503 */
1504 #define HT_BASIC_RATE 0x140c
1506 /*
1507 * HT_CTRL_CFG:
1508 */
1509 #define HT_CTRL_CFG 0x1410
1511 /*
1512 * SIFS_COST_CFG:
1513 */
1514 #define SIFS_COST_CFG 0x1414
1516 /*
1517 * RX_PARSER_CFG:
1518 * Set NAV for all received frames
1519 */
1520 #define RX_PARSER_CFG 0x1418
1522 /*
1523 * TX_SEC_CNT0:
1524 */
1525 #define TX_SEC_CNT0 0x1500
1527 /*
1528 * RX_SEC_CNT0:
1529 */
1530 #define RX_SEC_CNT0 0x1504
1532 /*
1533 * CCMP_FC_MUTE:
1534 */
1535 #define CCMP_FC_MUTE 0x1508
1537 /*
1538 * TXOP_HLDR_ADDR0:
1539 */
1540 #define TXOP_HLDR_ADDR0 0x1600
1542 /*
1543 * TXOP_HLDR_ADDR1:
1544 */
1545 #define TXOP_HLDR_ADDR1 0x1604
1547 /*
1548 * TXOP_HLDR_ET:
1549 */
1550 #define TXOP_HLDR_ET 0x1608
1552 /*
1553 * QOS_CFPOLL_RA_DW0:
1554 */
1555 #define QOS_CFPOLL_RA_DW0 0x160c
1557 /*
1558 * QOS_CFPOLL_RA_DW1:
1559 */
1560 #define QOS_CFPOLL_RA_DW1 0x1610
1562 /*
1563 * QOS_CFPOLL_QC:
1564 */
1565 #define QOS_CFPOLL_QC 0x1614
1567 /*
1568 * RX_STA_CNT0: RX PLCP error count & RX CRC error count
1569 */
1570 #define RX_STA_CNT0 0x1700
1571 #define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
1572 #define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
1574 /*
1575 * RX_STA_CNT1: RX False CCA count & RX LONG frame count
1576 */
1577 #define RX_STA_CNT1 0x1704
1578 #define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
1579 #define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
1581 /*
1582 * RX_STA_CNT2:
1583 */
1584 #define RX_STA_CNT2 0x1708
1585 #define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
1586 #define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
1588 /*
1589 * TX_STA_CNT0: TX Beacon count
1590 */
1591 #define TX_STA_CNT0 0x170c
1592 #define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
1593 #define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
1595 /*
1596 * TX_STA_CNT1: TX tx count
1597 */
1598 #define TX_STA_CNT1 0x1710
1599 #define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
1600 #define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
1602 /*
1603 * TX_STA_CNT2: TX tx count
1604 */
1605 #define TX_STA_CNT2 0x1714
1606 #define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
1607 #define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
1609 /*
1610 * TX_STA_FIFO: TX Result for specific PID status fifo register.
1611 *
1612 * This register is implemented as FIFO with 16 entries in the HW. Each
1613 * register read fetches the next tx result. If the FIFO is full because
1614 * it wasn't read fast enough after the according interrupt (TX_FIFO_STATUS)
1615 * triggered, the hw seems to simply drop further tx results.
1616 *
1617 * VALID: 1: this tx result is valid
1618 * 0: no valid tx result -> driver should stop reading
1619 * PID_TYPE: The PID latched from the PID field in the TXWI, can be used
1620 * to match a frame with its tx result (even though the PID is
1621 * only 4 bits wide).
1622 * PID_QUEUE: Part of PID_TYPE, this is the queue index number (0-3)
1623 * PID_ENTRY: Part of PID_TYPE, this is the queue entry index number (1-3)
1624 * This identification number is calculated by ((idx % 3) + 1).
1625 * TX_SUCCESS: Indicates tx success (1) or failure (0)
1626 * TX_AGGRE: Indicates if the frame was part of an aggregate (1) or not (0)
1627 * TX_ACK_REQUIRED: Indicates if the frame needed to get ack'ed (1) or not (0)
1628 * WCID: The wireless client ID.
1629 * MCS: The tx rate used during the last transmission of this frame, be it
1630 * successful or not.
1631 * PHYMODE: The phymode used for the transmission.
1632 */
1633 #define TX_STA_FIFO 0x1718
1634 #define TX_STA_FIFO_VALID FIELD32(0x00000001)
1635 #define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
1636 #define TX_STA_FIFO_PID_QUEUE FIELD32(0x00000006)
1637 #define TX_STA_FIFO_PID_ENTRY FIELD32(0x00000018)
1638 #define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
1639 #define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
1640 #define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
1641 #define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
1642 #define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
1643 #define TX_STA_FIFO_MCS FIELD32(0x007f0000)
1644 #define TX_STA_FIFO_PHYMODE FIELD32(0xc0000000)
1646 /*
1647 * TX_AGG_CNT: Debug counter
1648 */
1649 #define TX_AGG_CNT 0x171c
1650 #define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
1651 #define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
1653 /*
1654 * TX_AGG_CNT0:
1655 */
1656 #define TX_AGG_CNT0 0x1720
1657 #define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
1658 #define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
1660 /*
1661 * TX_AGG_CNT1:
1662 */
1663 #define TX_AGG_CNT1 0x1724
1664 #define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
1665 #define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
1667 /*
1668 * TX_AGG_CNT2:
1669 */
1670 #define TX_AGG_CNT2 0x1728
1671 #define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
1672 #define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
1674 /*
1675 * TX_AGG_CNT3:
1676 */
1677 #define TX_AGG_CNT3 0x172c
1678 #define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
1679 #define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
1681 /*
1682 * TX_AGG_CNT4:
1683 */
1684 #define TX_AGG_CNT4 0x1730
1685 #define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
1686 #define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
1688 /*
1689 * TX_AGG_CNT5:
1690 */
1691 #define TX_AGG_CNT5 0x1734
1692 #define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
1693 #define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
1695 /*
1696 * TX_AGG_CNT6:
1697 */
1698 #define TX_AGG_CNT6 0x1738
1699 #define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
1700 #define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
1702 /*
1703 * TX_AGG_CNT7:
1704 */
1705 #define TX_AGG_CNT7 0x173c
1706 #define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
1707 #define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
1709 /*
1710 * MPDU_DENSITY_CNT:
1711 * TX_ZERO_DEL: TX zero length delimiter count
1712 * RX_ZERO_DEL: RX zero length delimiter count
1713 */
1714 #define MPDU_DENSITY_CNT 0x1740
1715 #define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
1716 #define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
1718 /*
1719 * Security key table memory.
1720 *
1721 * The pairwise key table shares some memory with the beacon frame
1722 * buffers 6 and 7. That basically means that when beacon 6 & 7
1723 * are used we should only use the reduced pairwise key table which
1724 * has a maximum of 222 entries.
1725 *
1726 * ---------------------------------------------
1727 * |0x4000 | Pairwise Key | Reduced Pairwise |
1728 * | | Table | Key Table |
1729 * | | Size: 256 * 32 | Size: 222 * 32 |
1730 * |0x5BC0 | |-------------------
1731 * | | | Beacon 6 |
1732 * |0x5DC0 | |-------------------
1733 * | | | Beacon 7 |
1734 * |0x5FC0 | |-------------------
1735 * |0x5FFF | |
1736 * --------------------------
1737 *
1738 * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
1739 * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
1740 * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
1741 * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
1742 * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
1743 * SHARED_KEY_MODE_BASE: 4-byte * 16-entry
1744 */
1745 #define MAC_WCID_BASE 0x1800
1746 #define PAIRWISE_KEY_TABLE_BASE 0x4000
1747 #define MAC_IVEIV_TABLE_BASE 0x6000
1748 #define MAC_WCID_ATTRIBUTE_BASE 0x6800
1749 #define SHARED_KEY_TABLE_BASE 0x6c00
1750 #define SHARED_KEY_MODE_BASE 0x7000
1752 #define MAC_WCID_ENTRY(__idx) \
1753 (MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)))
1754 #define PAIRWISE_KEY_ENTRY(__idx) \
1755 (PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)))
1756 #define MAC_IVEIV_ENTRY(__idx) \
1757 (MAC_IVEIV_TABLE_BASE + ((__idx) * sizeof(struct mac_iveiv_entry)))
1758 #define MAC_WCID_ATTR_ENTRY(__idx) \
1759 (MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)))
1760 #define SHARED_KEY_ENTRY(__idx) \
1761 (SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)))
1762 #define SHARED_KEY_MODE_ENTRY(__idx) \
1763 (SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)))
1780 /*
1781 * MAC_WCID_ATTRIBUTE:
1782 */
1783 #define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
1784 #define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
1785 #define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
1786 #define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
1787 #define MAC_WCID_ATTRIBUTE_CIPHER_EXT FIELD32(0x00000400)
1788 #define MAC_WCID_ATTRIBUTE_BSS_IDX_EXT FIELD32(0x00000800)
1789 #define MAC_WCID_ATTRIBUTE_WAPI_MCBC FIELD32(0x00008000)
1790 #define MAC_WCID_ATTRIBUTE_WAPI_KEY_IDX FIELD32(0xff000000)
1792 /*
1793 * SHARED_KEY_MODE:
1794 */
1795 #define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
1796 #define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
1797 #define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
1798 #define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
1799 #define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
1800 #define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
1801 #define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
1802 #define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
1804 /*
1805 * HOST-MCU communication
1806 */
1808 /*
1809 * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
1810 * CMD_TOKEN: Command id, 0xff disable status reporting.
1811 */
1812 #define H2M_MAILBOX_CSR 0x7010
1813 #define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
1814 #define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
1815 #define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
1816 #define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
1818 /*
1819 * H2M_MAILBOX_CID:
1820 * Free slots contain 0xff. MCU will store command's token to lowest free slot.
1821 * If all slots are occupied status will be dropped.
1822 */
1823 #define H2M_MAILBOX_CID 0x7014
1824 #define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff)
1825 #define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00)
1826 #define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000)
1827 #define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000)
1829 /*
1830 * H2M_MAILBOX_STATUS:
1831 * Command status will be saved to same slot as command id.
1832 */
1833 #define H2M_MAILBOX_STATUS 0x701c
1835 /*
1836 * H2M_INT_SRC:
1837 */
1838 #define H2M_INT_SRC 0x7024
1840 /*
1841 * H2M_BBP_AGENT:
1842 */
1843 #define H2M_BBP_AGENT 0x7028
1845 /*
1846 * MCU_LEDCS: LED control for MCU Mailbox.
1847 */
1848 #define MCU_LEDCS_LED_MODE FIELD8(0x1f)
1849 #define MCU_LEDCS_POLARITY FIELD8(0x01)
1851 /*
1852 * HW_CS_CTS_BASE:
1853 * Carrier-sense CTS frame base address.
1854 * It's where mac stores carrier-sense frame for carrier-sense function.
1855 */
1856 #define HW_CS_CTS_BASE 0x7700
1858 /*
1859 * HW_DFS_CTS_BASE:
1860 * DFS CTS frame base address. It's where mac stores CTS frame for DFS.
1861 */
1862 #define HW_DFS_CTS_BASE 0x7780
1864 /*
1865 * TXRX control registers - base address 0x3000
1866 */
1868 /*
1869 * TXRX_CSR1:
1870 * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
1871 */
1872 #define TXRX_CSR1 0x77d0
1874 /*
1875 * HW_DEBUG_SETTING_BASE:
1876 * since NULL frame won't be that long (256 byte)
1877 * We steal 16 tail bytes to save debugging settings
1878 */
1879 #define HW_DEBUG_SETTING_BASE 0x77f0
1880 #define HW_DEBUG_SETTING_BASE2 0x7770
1882 /*
1883 * HW_BEACON_BASE
1884 * In order to support maximum 8 MBSS and its maximum length
1885 * is 512 bytes for each beacon
1886 * Three section discontinue memory segments will be used.
1887 * 1. The original region for BCN 0~3
1888 * 2. Extract memory from FCE table for BCN 4~5
1889 * 3. Extract memory from Pair-wise key table for BCN 6~7
1890 * It occupied those memory of wcid 238~253 for BCN 6
1891 * and wcid 222~237 for BCN 7 (see Security key table memory
1892 * for more info).
1893 *
1894 * IMPORTANT NOTE: Not sure why legacy driver does this,
1895 * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
1896 */
1897 #define HW_BEACON_BASE0 0x7800
1898 #define HW_BEACON_BASE1 0x7a00
1899 #define HW_BEACON_BASE2 0x7c00
1900 #define HW_BEACON_BASE3 0x7e00
1901 #define HW_BEACON_BASE4 0x7200
1902 #define HW_BEACON_BASE5 0x7400
1903 #define HW_BEACON_BASE6 0x5dc0
1904 #define HW_BEACON_BASE7 0x5bc0
1906 #define HW_BEACON_OFFSET(__index) \
1907 (((__index) < 4) ? (HW_BEACON_BASE0 + (__index * 0x0200)) : \
1908 (((__index) < 6) ? (HW_BEACON_BASE4 + ((__index - 4) * 0x0200)) : \
1909 (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))))
1911 /*
1912 * BBP registers.
1913 * The wordsize of the BBP is 8 bits.
1914 */
1916 /*
1917 * BBP 1: TX Antenna & Power Control
1918 * POWER_CTRL:
1919 * 0 - normal,
1920 * 1 - drop tx power by 6dBm,
1921 * 2 - drop tx power by 12dBm,
1922 * 3 - increase tx power by 6dBm
1923 */
1924 #define BBP1_TX_POWER_CTRL FIELD8(0x07)
1925 #define BBP1_TX_ANTENNA FIELD8(0x18)
1927 /*
1928 * BBP 3: RX Antenna
1929 */
1930 #define BBP3_RX_ADC FIELD8(0x03)
1931 #define BBP3_RX_ANTENNA FIELD8(0x18)
1932 #define BBP3_HT40_MINUS FIELD8(0x20)
1933 #define BBP3_ADC_MODE_SWITCH FIELD8(0x40)
1934 #define BBP3_ADC_INIT_MODE FIELD8(0x80)
1936 /*
1937 * BBP 4: Bandwidth
1938 */
1939 #define BBP4_TX_BF FIELD8(0x01)
1940 #define BBP4_BANDWIDTH FIELD8(0x18)
1941 #define BBP4_MAC_IF_CTRL FIELD8(0x40)
1943 /* BBP27 */
1944 #define BBP27_RX_CHAIN_SEL FIELD8(0x60)
1946 /*
1947 * BBP 47: Bandwidth
1948 */
1949 #define BBP47_TSSI_REPORT_SEL FIELD8(0x03)
1950 #define BBP47_TSSI_UPDATE_REQ FIELD8(0x04)
1951 #define BBP47_TSSI_TSSI_MODE FIELD8(0x18)
1952 #define BBP47_TSSI_ADC6 FIELD8(0x80)
1954 /*
1955 * BBP 49
1956 */
1957 #define BBP49_UPDATE_FLAG FIELD8(0x01)
1959 /*
1960 * BBP 105:
1961 * - bit0: detect SIG on primary channel only (on 40MHz bandwidth)
1962 * - bit1: FEQ (Feed Forward Compensation) for independend streams
1963 * - bit2: MLD (Maximum Likehood Detection) for 2 streams (reserved on single
1964 * stream)
1965 * - bit4: channel estimation updates based on remodulation of
1966 * L-SIG and HT-SIG symbols
1967 */
1968 #define BBP105_DETECT_SIG_ON_PRIMARY FIELD8(0x01)
1969 #define BBP105_FEQ FIELD8(0x02)
1970 #define BBP105_MLD FIELD8(0x04)
1971 #define BBP105_SIG_REMODULATION FIELD8(0x08)
1973 /*
1974 * BBP 109
1975 */
1976 #define BBP109_TX0_POWER FIELD8(0x0f)
1977 #define BBP109_TX1_POWER FIELD8(0xf0)
1979 /*
1980 * BBP 138: Unknown
1981 */
1982 #define BBP138_RX_ADC1 FIELD8(0x02)
1983 #define BBP138_RX_ADC2 FIELD8(0x04)
1984 #define BBP138_TX_DAC1 FIELD8(0x20)
1985 #define BBP138_TX_DAC2 FIELD8(0x40)
1987 /*
1988 * BBP 152: Rx Ant
1989 */
1990 #define BBP152_RX_DEFAULT_ANT FIELD8(0x80)
1992 /*
1993 * BBP 254: unknown
1994 */
1995 #define BBP254_BIT7 FIELD8(0x80)
1997 /*
1998 * RFCSR registers
1999 * The wordsize of the RFCSR is 8 bits.
2000 */
2002 /*
2003 * RFCSR 1:
2004 */
2005 #define RFCSR1_RF_BLOCK_EN FIELD8(0x01)
2006 #define RFCSR1_PLL_PD FIELD8(0x02)
2007 #define RFCSR1_RX0_PD FIELD8(0x04)
2008 #define RFCSR1_TX0_PD FIELD8(0x08)
2009 #define RFCSR1_RX1_PD FIELD8(0x10)
2010 #define RFCSR1_TX1_PD FIELD8(0x20)
2011 #define RFCSR1_RX2_PD FIELD8(0x40)
2012 #define RFCSR1_TX2_PD FIELD8(0x80)
2014 /*
2015 * RFCSR 2:
2016 */
2017 #define RFCSR2_RESCAL_EN FIELD8(0x80)
2019 /*
2020 * RFCSR 3:
2021 */
2022 #define RFCSR3_K FIELD8(0x0f)
2023 /* Bits [7-4] for RF3320 (RT3370/RT3390), on other chipsets reserved */
2024 #define RFCSR3_PA1_BIAS_CCK FIELD8(0x70)
2025 #define RFCSR3_PA2_CASCODE_BIAS_CCKK FIELD8(0x80)
2026 /* Bits for RF3290/RF5360/RF5370/RF5372/RF5390/RF5392 */
2027 #define RFCSR3_VCOCAL_EN FIELD8(0x80)
2029 /*
2030 * FRCSR 5:
2031 */
2032 #define RFCSR5_R1 FIELD8(0x0c)
2034 /*
2035 * RFCSR 6:
2036 */
2037 #define RFCSR6_R1 FIELD8(0x03)
2038 #define RFCSR6_R2 FIELD8(0x40)
2039 #define RFCSR6_TXDIV FIELD8(0x0c)
2041 /*
2042 * RFCSR 7:
2043 */
2044 #define RFCSR7_RF_TUNING FIELD8(0x01)
2045 #define RFCSR7_BIT1 FIELD8(0x02)
2046 #define RFCSR7_BIT2 FIELD8(0x04)
2047 #define RFCSR7_BIT3 FIELD8(0x08)
2048 #define RFCSR7_BIT4 FIELD8(0x10)
2049 #define RFCSR7_BIT5 FIELD8(0x20)
2050 #define RFCSR7_BITS67 FIELD8(0xc0)
2052 /*
2053 * RFCSR 9:
2054 */
2055 #define RFCSR9_K FIELD8(0x0f)
2056 #define RFCSR9_N FIELD8(0x10)
2057 #define RFCSR9_UNKNOWN FIELD8(0x60)
2058 #define RFCSR9_MOD FIELD8(0x80)
2060 /*
2061 * RFCSR 11:
2062 */
2063 #define RFCSR11_R FIELD8(0x03)
2064 #define RFCSR11_MOD FIELD8(0xc0)
2066 /*
2067 * RFCSR 12:
2068 */
2069 #define RFCSR12_TX_POWER FIELD8(0x1f)
2070 #define RFCSR12_DR0 FIELD8(0xe0)
2072 /*
2073 * RFCSR 13:
2074 */
2075 #define RFCSR13_TX_POWER FIELD8(0x1f)
2076 #define RFCSR13_DR0 FIELD8(0xe0)
2078 /*
2079 * RFCSR 15:
2080 */
2081 #define RFCSR15_TX_LO2_EN FIELD8(0x08)
2083 /*
2084 * RFCSR 16:
2085 */
2086 #define RFCSR16_TXMIXER_GAIN FIELD8(0x07)
2088 /*
2089 * RFCSR 17:
2090 */
2091 #define RFCSR17_TXMIXER_GAIN FIELD8(0x07)
2092 #define RFCSR17_TX_LO1_EN FIELD8(0x08)
2093 #define RFCSR17_R FIELD8(0x20)
2094 #define RFCSR17_CODE FIELD8(0x7f)
2096 /* RFCSR 18 */
2097 #define RFCSR18_XO_TUNE_BYPASS FIELD8(0x40)
2100 /*
2101 * RFCSR 20:
2102 */
2103 #define RFCSR20_RX_LO1_EN FIELD8(0x08)
2105 /*
2106 * RFCSR 21:
2107 */
2108 #define RFCSR21_RX_LO2_EN FIELD8(0x08)
2110 /*
2111 * RFCSR 22:
2112 */
2113 #define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
2115 /*
2116 * RFCSR 23:
2117 */
2118 #define RFCSR23_FREQ_OFFSET FIELD8(0x7f)
2120 /*
2121 * RFCSR 24:
2122 */
2123 #define RFCSR24_TX_AGC_FC FIELD8(0x1f)
2124 #define RFCSR24_TX_H20M FIELD8(0x20)
2125 #define RFCSR24_TX_CALIB FIELD8(0x7f)
2127 /*
2128 * RFCSR 27:
2129 */
2130 #define RFCSR27_R1 FIELD8(0x03)
2131 #define RFCSR27_R2 FIELD8(0x04)
2132 #define RFCSR27_R3 FIELD8(0x30)
2133 #define RFCSR27_R4 FIELD8(0x40)
2135 /*
2136 * RFCSR 29:
2137 */
2138 #define RFCSR29_ADC6_TEST FIELD8(0x01)
2139 #define RFCSR29_ADC6_INT_TEST FIELD8(0x02)
2140 #define RFCSR29_RSSI_RESET FIELD8(0x04)
2141 #define RFCSR29_RSSI_ON FIELD8(0x08)
2142 #define RFCSR29_RSSI_RIP_CTRL FIELD8(0x30)
2143 #define RFCSR29_RSSI_GAIN FIELD8(0xc0)
2145 /*
2146 * RFCSR 30:
2147 */
2148 #define RFCSR30_TX_H20M FIELD8(0x02)
2149 #define RFCSR30_RX_H20M FIELD8(0x04)
2150 #define RFCSR30_RX_VCM FIELD8(0x18)
2151 #define RFCSR30_RF_CALIBRATION FIELD8(0x80)
2153 /*
2154 * RFCSR 31:
2155 */
2156 #define RFCSR31_RX_AGC_FC FIELD8(0x1f)
2157 #define RFCSR31_RX_H20M FIELD8(0x20)
2158 #define RFCSR31_RX_CALIB FIELD8(0x7f)
2160 /*
2161 * RFCSR 38:
2162 */
2163 #define RFCSR38_RX_LO1_EN FIELD8(0x20)
2165 /*
2166 * RFCSR 39:
2167 */
2168 #define RFCSR39_RX_LO2_EN FIELD8(0x80)
2170 /*
2171 * RFCSR 49:
2172 */
2173 #define RFCSR49_TX FIELD8(0x3f)
2174 #define RFCSR49_EP FIELD8(0xc0)
2176 /*
2177 * RFCSR 50:
2178 */
2179 #define RFCSR50_TX FIELD8(0x3f)
2180 #define RFCSR50_EP FIELD8(0xc0)
2181 /* bits for RT3593*/
2182 #define RFCSR50_TX_LO2_EN FIELD8(0x10)
2184 /* RFCSR 51 */
2185 /* bits for RT3593*/
2186 #define RFCSR51_BITS24 FIELD8(0x1c)
2188 /*
2189 * RF registers
2190 */
2192 /*
2193 * RF 2
2194 */
2195 #define RF2_ANTENNA_RX2 FIELD32(0x00000040)
2196 #define RF2_ANTENNA_TX1 FIELD32(0x00004000)
2197 #define RF2_ANTENNA_RX1 FIELD32(0x00020000)
2199 /*
2200 * RF 3
2201 */
2202 #define RF3_TXPOWER_G FIELD32(0x00003e00)
2203 #define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
2204 #define RF3_TXPOWER_A FIELD32(0x00003c00)
2206 /*
2207 * RF 4
2208 */
2209 #define RF4_TXPOWER_G FIELD32(0x000007c0)
2210 #define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
2211 #define RF4_TXPOWER_A FIELD32(0x00000780)
2212 #define RF4_FREQ_OFFSET FIELD32(0x001f8000)
2213 #define RF4_HT40 FIELD32(0x00200000)
2215 /*
2216 * EEPROM content.
2217 * The wordsize of the EEPROM is 16 bits.
2218 */
2222 EEPROM_VERSION,
2223 EEPROM_MAC_ADDR_0,
2224 EEPROM_MAC_ADDR_1,
2225 EEPROM_MAC_ADDR_2,
2226 EEPROM_NIC_CONF0,
2227 EEPROM_NIC_CONF1,
2228 EEPROM_FREQ,
2229 EEPROM_LED_AG_CONF,
2230 EEPROM_LED_ACT_CONF,
2231 EEPROM_LED_POLARITY,
2232 EEPROM_NIC_CONF2,
2233 EEPROM_LNA,
2234 EEPROM_RSSI_BG,
2235 EEPROM_RSSI_BG2,
2236 EEPROM_TXMIXER_GAIN_BG,
2237 EEPROM_RSSI_A,
2238 EEPROM_RSSI_A2,
2239 EEPROM_TXMIXER_GAIN_A,
2240 EEPROM_EIRP_MAX_TX_POWER,
2241 EEPROM_TXPOWER_DELTA,
2242 EEPROM_TXPOWER_BG1,
2243 EEPROM_TXPOWER_BG2,
2244 EEPROM_TSSI_BOUND_BG1,
2245 EEPROM_TSSI_BOUND_BG2,
2246 EEPROM_TSSI_BOUND_BG3,
2247 EEPROM_TSSI_BOUND_BG4,
2248 EEPROM_TSSI_BOUND_BG5,
2249 EEPROM_TXPOWER_A1,
2250 EEPROM_TXPOWER_A2,
2251 EEPROM_TSSI_BOUND_A1,
2252 EEPROM_TSSI_BOUND_A2,
2253 EEPROM_TSSI_BOUND_A3,
2254 EEPROM_TSSI_BOUND_A4,
2255 EEPROM_TSSI_BOUND_A5,
2256 EEPROM_TXPOWER_BYRATE,
2257 EEPROM_BBP_START,
2259 /* IDs for extended EEPROM format used by three-chain devices */
2260 EEPROM_EXT_LNA2,
2261 EEPROM_EXT_TXPOWER_BG3,
2262 EEPROM_EXT_TXPOWER_A3,
2264 /* New values must be added before this */
2265 EEPROM_WORD_COUNT
2266 };
2268 /*
2269 * EEPROM Version
2270 */
2271 #define EEPROM_VERSION_FAE FIELD16(0x00ff)
2272 #define EEPROM_VERSION_VERSION FIELD16(0xff00)
2274 /*
2275 * HW MAC address.
2276 */
2277 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
2278 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
2279 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
2280 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
2281 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
2282 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
2284 /*
2285 * EEPROM NIC Configuration 0
2286 * RXPATH: 1: 1R, 2: 2R, 3: 3R
2287 * TXPATH: 1: 1T, 2: 2T, 3: 3T
2288 * RF_TYPE: RFIC type
2289 */
2290 #define EEPROM_NIC_CONF0_RXPATH FIELD16(0x000f)
2291 #define EEPROM_NIC_CONF0_TXPATH FIELD16(0x00f0)
2292 #define EEPROM_NIC_CONF0_RF_TYPE FIELD16(0x0f00)
2294 /*
2295 * EEPROM NIC Configuration 1
2296 * HW_RADIO: 0: disable, 1: enable
2297 * EXTERNAL_TX_ALC: 0: disable, 1: enable
2298 * EXTERNAL_LNA_2G: 0: disable, 1: enable
2299 * EXTERNAL_LNA_5G: 0: disable, 1: enable
2300 * CARDBUS_ACCEL: 0: enable, 1: disable
2301 * BW40M_SB_2G: 0: disable, 1: enable
2302 * BW40M_SB_5G: 0: disable, 1: enable
2303 * WPS_PBC: 0: disable, 1: enable
2304 * BW40M_2G: 0: enable, 1: disable
2305 * BW40M_5G: 0: enable, 1: disable
2306 * BROADBAND_EXT_LNA: 0: disable, 1: enable
2307 * ANT_DIVERSITY: 00: Disable, 01: Diversity,
2308 * 10: Main antenna, 11: Aux antenna
2309 * INTERNAL_TX_ALC: 0: disable, 1: enable
2310 * BT_COEXIST: 0: disable, 1: enable
2311 * DAC_TEST: 0: disable, 1: enable
2312 */
2313 #define EEPROM_NIC_CONF1_HW_RADIO FIELD16(0x0001)
2314 #define EEPROM_NIC_CONF1_EXTERNAL_TX_ALC FIELD16(0x0002)
2315 #define EEPROM_NIC_CONF1_EXTERNAL_LNA_2G FIELD16(0x0004)
2316 #define EEPROM_NIC_CONF1_EXTERNAL_LNA_5G FIELD16(0x0008)
2317 #define EEPROM_NIC_CONF1_CARDBUS_ACCEL FIELD16(0x0010)
2318 #define EEPROM_NIC_CONF1_BW40M_SB_2G FIELD16(0x0020)
2319 #define EEPROM_NIC_CONF1_BW40M_SB_5G FIELD16(0x0040)
2320 #define EEPROM_NIC_CONF1_WPS_PBC FIELD16(0x0080)
2321 #define EEPROM_NIC_CONF1_BW40M_2G FIELD16(0x0100)
2322 #define EEPROM_NIC_CONF1_BW40M_5G FIELD16(0x0200)
2323 #define EEPROM_NIC_CONF1_BROADBAND_EXT_LNA FIELD16(0x400)
2324 #define EEPROM_NIC_CONF1_ANT_DIVERSITY FIELD16(0x1800)
2325 #define EEPROM_NIC_CONF1_INTERNAL_TX_ALC FIELD16(0x2000)
2326 #define EEPROM_NIC_CONF1_BT_COEXIST FIELD16(0x4000)
2327 #define EEPROM_NIC_CONF1_DAC_TEST FIELD16(0x8000)
2329 /*
2330 * EEPROM frequency
2331 */
2332 #define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
2333 #define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
2334 #define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
2336 /*
2337 * EEPROM LED
2338 * POLARITY_RDY_G: Polarity RDY_G setting.
2339 * POLARITY_RDY_A: Polarity RDY_A setting.
2340 * POLARITY_ACT: Polarity ACT setting.
2341 * POLARITY_GPIO_0: Polarity GPIO0 setting.
2342 * POLARITY_GPIO_1: Polarity GPIO1 setting.
2343 * POLARITY_GPIO_2: Polarity GPIO2 setting.
2344 * POLARITY_GPIO_3: Polarity GPIO3 setting.
2345 * POLARITY_GPIO_4: Polarity GPIO4 setting.
2346 * LED_MODE: Led mode.
2347 */
2348 #define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
2349 #define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
2350 #define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
2351 #define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
2352 #define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
2353 #define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
2354 #define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
2355 #define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
2356 #define EEPROM_LED_LED_MODE FIELD16(0x1f00)
2358 /*
2359 * EEPROM NIC Configuration 2
2360 * RX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream
2361 * TX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream
2362 * CRYSTAL: 00: Reserved, 01: One crystal, 10: Two crystal, 11: Reserved
2363 */
2364 #define EEPROM_NIC_CONF2_RX_STREAM FIELD16(0x000f)
2365 #define EEPROM_NIC_CONF2_TX_STREAM FIELD16(0x00f0)
2366 #define EEPROM_NIC_CONF2_CRYSTAL FIELD16(0x0600)
2368 /*
2369 * EEPROM LNA
2370 */
2371 #define EEPROM_LNA_BG FIELD16(0x00ff)
2372 #define EEPROM_LNA_A0 FIELD16(0xff00)
2374 /*
2375 * EEPROM RSSI BG offset
2376 */
2377 #define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
2378 #define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
2380 /*
2381 * EEPROM RSSI BG2 offset
2382 */
2383 #define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
2384 #define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
2386 /*
2387 * EEPROM TXMIXER GAIN BG offset (note overlaps with EEPROM RSSI BG2).
2388 */
2389 #define EEPROM_TXMIXER_GAIN_BG_VAL FIELD16(0x0007)
2391 /*
2392 * EEPROM RSSI A offset
2393 */
2394 #define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
2395 #define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
2397 /*
2398 * EEPROM RSSI A2 offset
2399 */
2400 #define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
2401 #define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
2403 /*
2404 * EEPROM TXMIXER GAIN A offset (note overlaps with EEPROM RSSI A2).
2405 */
2406 #define EEPROM_TXMIXER_GAIN_A_VAL FIELD16(0x0007)
2408 /*
2409 * EEPROM EIRP Maximum TX power values(unit: dbm)
2410 */
2411 #define EEPROM_EIRP_MAX_TX_POWER_2GHZ FIELD16(0x00ff)
2412 #define EEPROM_EIRP_MAX_TX_POWER_5GHZ FIELD16(0xff00)
2414 /*
2415 * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
2416 * This is delta in 40MHZ.
2417 * VALUE: Tx Power dalta value, MAX=4(unit: dbm)
2418 * TYPE: 1: Plus the delta value, 0: minus the delta value
2419 * ENABLE: enable tx power compensation for 40BW
2420 */
2421 #define EEPROM_TXPOWER_DELTA_VALUE_2G FIELD16(0x003f)
2422 #define EEPROM_TXPOWER_DELTA_TYPE_2G FIELD16(0x0040)
2423 #define EEPROM_TXPOWER_DELTA_ENABLE_2G FIELD16(0x0080)
2424 #define EEPROM_TXPOWER_DELTA_VALUE_5G FIELD16(0x3f00)
2425 #define EEPROM_TXPOWER_DELTA_TYPE_5G FIELD16(0x4000)
2426 #define EEPROM_TXPOWER_DELTA_ENABLE_5G FIELD16(0x8000)
2428 /*
2429 * EEPROM TXPOWER 802.11BG
2430 */
2431 #define EEPROM_TXPOWER_BG_SIZE 7
2432 #define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
2433 #define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
2435 /*
2436 * EEPROM temperature compensation boundaries 802.11BG
2437 * MINUS4: If the actual TSSI is below this boundary, tx power needs to be
2438 * reduced by (agc_step * -4)
2439 * MINUS3: If the actual TSSI is below this boundary, tx power needs to be
2440 * reduced by (agc_step * -3)
2441 */
2442 #define EEPROM_TSSI_BOUND_BG1_MINUS4 FIELD16(0x00ff)
2443 #define EEPROM_TSSI_BOUND_BG1_MINUS3 FIELD16(0xff00)
2445 /*
2446 * EEPROM temperature compensation boundaries 802.11BG
2447 * MINUS2: If the actual TSSI is below this boundary, tx power needs to be
2448 * reduced by (agc_step * -2)
2449 * MINUS1: If the actual TSSI is below this boundary, tx power needs to be
2450 * reduced by (agc_step * -1)
2451 */
2452 #define EEPROM_TSSI_BOUND_BG2_MINUS2 FIELD16(0x00ff)
2453 #define EEPROM_TSSI_BOUND_BG2_MINUS1 FIELD16(0xff00)
2455 /*
2456 * EEPROM temperature compensation boundaries 802.11BG
2457 * REF: Reference TSSI value, no tx power changes needed
2458 * PLUS1: If the actual TSSI is above this boundary, tx power needs to be
2459 * increased by (agc_step * 1)
2460 */
2461 #define EEPROM_TSSI_BOUND_BG3_REF FIELD16(0x00ff)
2462 #define EEPROM_TSSI_BOUND_BG3_PLUS1 FIELD16(0xff00)
2464 /*
2465 * EEPROM temperature compensation boundaries 802.11BG
2466 * PLUS2: If the actual TSSI is above this boundary, tx power needs to be
2467 * increased by (agc_step * 2)
2468 * PLUS3: If the actual TSSI is above this boundary, tx power needs to be
2469 * increased by (agc_step * 3)
2470 */
2471 #define EEPROM_TSSI_BOUND_BG4_PLUS2 FIELD16(0x00ff)
2472 #define EEPROM_TSSI_BOUND_BG4_PLUS3 FIELD16(0xff00)
2474 /*
2475 * EEPROM temperature compensation boundaries 802.11BG
2476 * PLUS4: If the actual TSSI is above this boundary, tx power needs to be
2477 * increased by (agc_step * 4)
2478 * AGC_STEP: Temperature compensation step.
2479 */
2480 #define EEPROM_TSSI_BOUND_BG5_PLUS4 FIELD16(0x00ff)
2481 #define EEPROM_TSSI_BOUND_BG5_AGC_STEP FIELD16(0xff00)
2483 /*
2484 * EEPROM TXPOWER 802.11A
2485 */
2486 #define EEPROM_TXPOWER_A_SIZE 6
2487 #define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
2488 #define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
2490 /*
2491 * EEPROM temperature compensation boundaries 802.11A
2492 * MINUS4: If the actual TSSI is below this boundary, tx power needs to be
2493 * reduced by (agc_step * -4)
2494 * MINUS3: If the actual TSSI is below this boundary, tx power needs to be
2495 * reduced by (agc_step * -3)
2496 */
2497 #define EEPROM_TSSI_BOUND_A1_MINUS4 FIELD16(0x00ff)
2498 #define EEPROM_TSSI_BOUND_A1_MINUS3 FIELD16(0xff00)
2500 /*
2501 * EEPROM temperature compensation boundaries 802.11A
2502 * MINUS2: If the actual TSSI is below this boundary, tx power needs to be
2503 * reduced by (agc_step * -2)
2504 * MINUS1: If the actual TSSI is below this boundary, tx power needs to be
2505 * reduced by (agc_step * -1)
2506 */
2507 #define EEPROM_TSSI_BOUND_A2_MINUS2 FIELD16(0x00ff)
2508 #define EEPROM_TSSI_BOUND_A2_MINUS1 FIELD16(0xff00)
2510 /*
2511 * EEPROM temperature compensation boundaries 802.11A
2512 * REF: Reference TSSI value, no tx power changes needed
2513 * PLUS1: If the actual TSSI is above this boundary, tx power needs to be
2514 * increased by (agc_step * 1)
2515 */
2516 #define EEPROM_TSSI_BOUND_A3_REF FIELD16(0x00ff)
2517 #define EEPROM_TSSI_BOUND_A3_PLUS1 FIELD16(0xff00)
2519 /*
2520 * EEPROM temperature compensation boundaries 802.11A
2521 * PLUS2: If the actual TSSI is above this boundary, tx power needs to be
2522 * increased by (agc_step * 2)
2523 * PLUS3: If the actual TSSI is above this boundary, tx power needs to be
2524 * increased by (agc_step * 3)
2525 */
2526 #define EEPROM_TSSI_BOUND_A4_PLUS2 FIELD16(0x00ff)
2527 #define EEPROM_TSSI_BOUND_A4_PLUS3 FIELD16(0xff00)
2529 /*
2530 * EEPROM temperature compensation boundaries 802.11A
2531 * PLUS4: If the actual TSSI is above this boundary, tx power needs to be
2532 * increased by (agc_step * 4)
2533 * AGC_STEP: Temperature compensation step.
2534 */
2535 #define EEPROM_TSSI_BOUND_A5_PLUS4 FIELD16(0x00ff)
2536 #define EEPROM_TSSI_BOUND_A5_AGC_STEP FIELD16(0xff00)
2538 /*
2539 * EEPROM TXPOWER by rate: tx power per tx rate for HT20 mode
2540 */
2541 #define EEPROM_TXPOWER_BYRATE_SIZE 9
2543 #define EEPROM_TXPOWER_BYRATE_RATE0 FIELD16(0x000f)
2544 #define EEPROM_TXPOWER_BYRATE_RATE1 FIELD16(0x00f0)
2545 #define EEPROM_TXPOWER_BYRATE_RATE2 FIELD16(0x0f00)
2546 #define EEPROM_TXPOWER_BYRATE_RATE3 FIELD16(0xf000)
2548 /*
2549 * EEPROM BBP.
2550 */
2551 #define EEPROM_BBP_SIZE 16
2552 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
2553 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
2555 /*
2556 * EEPROM IQ Calibration, unlike other entries those are byte addresses.
2557 */
2559 #define EEPROM_IQ_GAIN_CAL_TX0_2G 0x130
2560 #define EEPROM_IQ_PHASE_CAL_TX0_2G 0x131
2561 #define EEPROM_IQ_GROUPDELAY_CAL_TX0_2G 0x132
2562 #define EEPROM_IQ_GAIN_CAL_TX1_2G 0x133
2563 #define EEPROM_IQ_PHASE_CAL_TX1_2G 0x134
2564 #define EEPROM_IQ_GROUPDELAY_CAL_TX1_2G 0x135
2565 #define EEPROM_IQ_GAIN_CAL_RX0_2G 0x136
2566 #define EEPROM_IQ_PHASE_CAL_RX0_2G 0x137
2567 #define EEPROM_IQ_GROUPDELAY_CAL_RX0_2G 0x138
2568 #define EEPROM_IQ_GAIN_CAL_RX1_2G 0x139
2569 #define EEPROM_IQ_PHASE_CAL_RX1_2G 0x13A
2570 #define EEPROM_IQ_GROUPDELAY_CAL_RX1_2G 0x13B
2571 #define EEPROM_RF_IQ_COMPENSATION_CONTROL 0x13C
2572 #define EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL 0x13D
2573 #define EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G 0x144
2574 #define EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G 0x145
2575 #define EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G 0X146
2576 #define EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G 0x147
2577 #define EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G 0x148
2578 #define EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G 0x149
2579 #define EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G 0x14A
2580 #define EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G 0x14B
2581 #define EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G 0X14C
2582 #define EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G 0x14D
2583 #define EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G 0x14E
2584 #define EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G 0x14F
2585 #define EEPROM_IQ_GROUPDELAY_CAL_TX0_CH36_TO_CH64_5G 0x150
2586 #define EEPROM_IQ_GROUPDELAY_CAL_TX1_CH36_TO_CH64_5G 0x151
2587 #define EEPROM_IQ_GROUPDELAY_CAL_TX0_CH100_TO_CH138_5G 0x152
2588 #define EEPROM_IQ_GROUPDELAY_CAL_TX1_CH100_TO_CH138_5G 0x153
2589 #define EEPROM_IQ_GROUPDELAY_CAL_TX0_CH140_TO_CH165_5G 0x154
2590 #define EEPROM_IQ_GROUPDELAY_CAL_TX1_CH140_TO_CH165_5G 0x155
2591 #define EEPROM_IQ_GAIN_CAL_RX0_CH36_TO_CH64_5G 0x156
2592 #define EEPROM_IQ_PHASE_CAL_RX0_CH36_TO_CH64_5G 0x157
2593 #define EEPROM_IQ_GAIN_CAL_RX0_CH100_TO_CH138_5G 0X158
2594 #define EEPROM_IQ_PHASE_CAL_RX0_CH100_TO_CH138_5G 0x159
2595 #define EEPROM_IQ_GAIN_CAL_RX0_CH140_TO_CH165_5G 0x15A
2596 #define EEPROM_IQ_PHASE_CAL_RX0_CH140_TO_CH165_5G 0x15B
2597 #define EEPROM_IQ_GAIN_CAL_RX1_CH36_TO_CH64_5G 0x15C
2598 #define EEPROM_IQ_PHASE_CAL_RX1_CH36_TO_CH64_5G 0x15D
2599 #define EEPROM_IQ_GAIN_CAL_RX1_CH100_TO_CH138_5G 0X15E
2600 #define EEPROM_IQ_PHASE_CAL_RX1_CH100_TO_CH138_5G 0x15F
2601 #define EEPROM_IQ_GAIN_CAL_RX1_CH140_TO_CH165_5G 0x160
2602 #define EEPROM_IQ_PHASE_CAL_RX1_CH140_TO_CH165_5G 0x161
2603 #define EEPROM_IQ_GROUPDELAY_CAL_RX0_CH36_TO_CH64_5G 0x162
2604 #define EEPROM_IQ_GROUPDELAY_CAL_RX1_CH36_TO_CH64_5G 0x163
2605 #define EEPROM_IQ_GROUPDELAY_CAL_RX0_CH100_TO_CH138_5G 0x164
2606 #define EEPROM_IQ_GROUPDELAY_CAL_RX1_CH100_TO_CH138_5G 0x165
2607 #define EEPROM_IQ_GROUPDELAY_CAL_RX0_CH140_TO_CH165_5G 0x166
2608 #define EEPROM_IQ_GROUPDELAY_CAL_RX1_CH140_TO_CH165_5G 0x167
2610 /*
2611 * MCU mailbox commands.
2612 * MCU_SLEEP - go to power-save mode.
2613 * arg1: 1: save as much power as possible, 0: save less power.
2614 * status: 1: success, 2: already asleep,
2615 * 3: maybe MAC is busy so can't finish this task.
2616 * MCU_RADIO_OFF
2617 * arg0: 0: do power-saving, NOT turn off radio.
2618 */
2619 #define MCU_SLEEP 0x30
2620 #define MCU_WAKEUP 0x31
2621 #define MCU_RADIO_OFF 0x35
2622 #define MCU_CURRENT 0x36
2623 #define MCU_LED 0x50
2624 #define MCU_LED_STRENGTH 0x51
2625 #define MCU_LED_AG_CONF 0x52
2626 #define MCU_LED_ACT_CONF 0x53
2627 #define MCU_LED_LED_POLARITY 0x54
2628 #define MCU_RADAR 0x60
2629 #define MCU_BOOT_SIGNAL 0x72
2630 #define MCU_ANT_SELECT 0X73
2631 #define MCU_BBP_SIGNAL 0x80
2632 #define MCU_POWER_SAVE 0x83
2633 #define MCU_BAND_SELECT 0x91
2635 /*
2636 * MCU mailbox tokens
2637 */
2638 #define TOKEN_SLEEP 1
2639 #define TOKEN_RADIO_OFF 2
2640 #define TOKEN_WAKEUP 3
2643 /*
2644 * DMA descriptor defines.
2645 */
2647 #define TXWI_DESC_SIZE_4WORDS (4 * sizeof(__le32))
2648 #define TXWI_DESC_SIZE_5WORDS (5 * sizeof(__le32))
2650 #define RXWI_DESC_SIZE_4WORDS (4 * sizeof(__le32))
2651 #define RXWI_DESC_SIZE_6WORDS (6 * sizeof(__le32))
2653 /*
2654 * TX WI structure
2655 */
2657 /*
2658 * Word0
2659 * FRAG: 1 To inform TKIP engine this is a fragment.
2660 * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
2661 * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
2662 * BW: Channel bandwidth 0:20MHz, 1:40 MHz (for legacy rates this will
2663 * duplicate the frame to both channels).
2664 * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
2665 * AMPDU: 1: this frame is eligible for AMPDU aggregation, the hw will
2666 * aggregate consecutive frames with the same RA and QoS TID. If
2667 * a frame A with the same RA and QoS TID but AMPDU=0 is queued
2668 * directly after a frame B with AMPDU=1, frame A might still
2669 * get aggregated into the AMPDU started by frame B. So, setting
2670 * AMPDU to 0 does _not_ necessarily mean the frame is sent as
2671 * MPDU, it can still end up in an AMPDU if the previous frame
2672 * was tagged as AMPDU.
2673 */
2674 #define TXWI_W0_FRAG FIELD32(0x00000001)
2675 #define TXWI_W0_MIMO_PS FIELD32(0x00000002)
2676 #define TXWI_W0_CF_ACK FIELD32(0x00000004)
2677 #define TXWI_W0_TS FIELD32(0x00000008)
2678 #define TXWI_W0_AMPDU FIELD32(0x00000010)
2679 #define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
2680 #define TXWI_W0_TX_OP FIELD32(0x00000300)
2681 #define TXWI_W0_MCS FIELD32(0x007f0000)
2682 #define TXWI_W0_BW FIELD32(0x00800000)
2683 #define TXWI_W0_SHORT_GI FIELD32(0x01000000)
2684 #define TXWI_W0_STBC FIELD32(0x06000000)
2685 #define TXWI_W0_IFS FIELD32(0x08000000)
2686 #define TXWI_W0_PHYMODE FIELD32(0xc0000000)
2688 /*
2689 * Word1
2690 * ACK: 0: No Ack needed, 1: Ack needed
2691 * NSEQ: 0: Don't assign hw sequence number, 1: Assign hw sequence number
2692 * BW_WIN_SIZE: BA windows size of the recipient
2693 * WIRELESS_CLI_ID: Client ID for WCID table access
2694 * MPDU_TOTAL_BYTE_COUNT: Length of 802.11 frame
2695 * PACKETID: Will be latched into the TX_STA_FIFO register once the according
2696 * frame was processed. If multiple frames are aggregated together
2697 * (AMPDU==1) the reported tx status will always contain the packet
2698 * id of the first frame. 0: Don't report tx status for this frame.
2699 * PACKETID_QUEUE: Part of PACKETID, This is the queue index (0-3)
2700 * PACKETID_ENTRY: Part of PACKETID, THis is the queue entry index (1-3)
2701 * This identification number is calculated by ((idx % 3) + 1).
2702 * The (+1) is required to prevent PACKETID to become 0.
2703 */
2704 #define TXWI_W1_ACK FIELD32(0x00000001)
2705 #define TXWI_W1_NSEQ FIELD32(0x00000002)
2706 #define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
2707 #define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
2708 #define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
2709 #define TXWI_W1_PACKETID FIELD32(0xf0000000)
2710 #define TXWI_W1_PACKETID_QUEUE FIELD32(0x30000000)
2711 #define TXWI_W1_PACKETID_ENTRY FIELD32(0xc0000000)
2713 /*
2714 * Word2
2715 */
2716 #define TXWI_W2_IV FIELD32(0xffffffff)
2718 /*
2719 * Word3
2720 */
2721 #define TXWI_W3_EIV FIELD32(0xffffffff)
2723 /*
2724 * RX WI structure
2725 */
2727 /*
2728 * Word0
2729 */
2730 #define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
2731 #define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
2732 #define RXWI_W0_BSSID FIELD32(0x00001c00)
2733 #define RXWI_W0_UDF FIELD32(0x0000e000)
2734 #define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
2735 #define RXWI_W0_TID FIELD32(0xf0000000)
2737 /*
2738 * Word1
2739 */
2740 #define RXWI_W1_FRAG FIELD32(0x0000000f)
2741 #define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
2742 #define RXWI_W1_MCS FIELD32(0x007f0000)
2743 #define RXWI_W1_BW FIELD32(0x00800000)
2744 #define RXWI_W1_SHORT_GI FIELD32(0x01000000)
2745 #define RXWI_W1_STBC FIELD32(0x06000000)
2746 #define RXWI_W1_PHYMODE FIELD32(0xc0000000)
2748 /*
2749 * Word2
2750 */
2751 #define RXWI_W2_RSSI0 FIELD32(0x000000ff)
2752 #define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
2753 #define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
2755 /*
2756 * Word3
2757 */
2758 #define RXWI_W3_SNR0 FIELD32(0x000000ff)
2759 #define RXWI_W3_SNR1 FIELD32(0x0000ff00)
2761 /*
2762 * Macros for converting txpower from EEPROM to mac80211 value
2763 * and from mac80211 value to register value.
2764 */
2765 #define MIN_G_TXPOWER 0
2766 #define MIN_A_TXPOWER -7
2767 #define MAX_G_TXPOWER 31
2768 #define MAX_A_TXPOWER 15
2769 #define DEFAULT_TXPOWER 5
2771 #define TXPOWER_G_FROM_DEV(__txpower) \
2772 ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
2774 #define TXPOWER_G_TO_DEV(__txpower) \
2775 clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
2777 #define TXPOWER_A_FROM_DEV(__txpower) \
2778 ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
2780 #define TXPOWER_A_TO_DEV(__txpower) \
2781 clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
2783 /*
2784 * Board's maximun TX power limitation
2785 */
2786 #define EIRP_MAX_TX_POWER_LIMIT 0x50
2788 /*
2789 * Number of TBTT intervals after which we have to adjust
2790 * the hw beacon timer.
2791 */
2792 #define BCN_TBTT_OFFSET 64
2794 /*
2795 * RT2800 driver data structure
2796 */
2798 u8 calibration_bw20;
2799 u8 calibration_bw40;
2800 u8 bbp25;
2801 u8 bbp26;
2802 u8 txmixer_gain_24g;
2803 u8 txmixer_gain_5g;
2805 };