drivers/memory/fsl_ifc.c

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc
   3  *
   4  * Freescale Integrated Flash Controller
   5  *
   6  * Author: Dipen Dudhat <Dipen.Dudhat@freescale.com>
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/compiler.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/types.h>
  27 #include <linux/slab.h>
  28 #include <linux/io.h>
  29 #include <linux/of.h>
  30 #include <linux/of_device.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/fsl_ifc.h>
  33 #include <asm/prom.h>
  34
  35 struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
  36 EXPORT_SYMBOL(fsl_ifc_ctrl_dev);
  37
  38 /*
  39  * convert_ifc_address - convert the base address
  40  * @addr_base:  base address of the memory bank
  41  */
  42 unsigned int convert_ifc_address(phys_addr_t addr_base)
  43 {
  44         return addr_base & CSPR_BA;
  45 }
  46 EXPORT_SYMBOL(convert_ifc_address);
  47
  48 /*
  49  * fsl_ifc_find - find IFC bank
  50  * @addr_base:  base address of the memory bank
  51  *
  52  * This function walks IFC banks comparing "Base address" field of the CSPR
  53  * registers with the supplied addr_base argument. When bases match this
  54  * function returns bank number (starting with 0), otherwise it returns
  55  * appropriate errno value.
  56  */
  57 int fsl_ifc_find(phys_addr_t addr_base)
  58 {
  59         int i = 0;
  60
  61         if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->regs)
  62                 return -ENODEV;
  63
  64         for (i = 0; i < ARRAY_SIZE(fsl_ifc_ctrl_dev->regs->cspr_cs); i++) {
  65                 u32 cspr = in_be32(&fsl_ifc_ctrl_dev->regs->cspr_cs[i].cspr);
  66                 if (cspr & CSPR_V && (cspr & CSPR_BA) ==
  67                                 convert_ifc_address(addr_base))
  68                         return i;
  69         }
  70
  71         return -ENOENT;
  72 }
  73 EXPORT_SYMBOL(fsl_ifc_find);
  74
  75 static int fsl_ifc_ctrl_init(struct fsl_ifc_ctrl *ctrl)
  76 {
  77         struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
  78
  79         /*
  80          * Clear all the common status and event registers
  81          */
  82         if (in_be32(&ifc->cm_evter_stat) & IFC_CM_EVTER_STAT_CSER)
  83                 out_be32(&ifc->cm_evter_stat, IFC_CM_EVTER_STAT_CSER);
  84
  85         /* enable all error and events */
  86         out_be32(&ifc->cm_evter_en, IFC_CM_EVTER_EN_CSEREN);
  87
  88         /* enable all error and event interrupts */
  89         out_be32(&ifc->cm_evter_intr_en, IFC_CM_EVTER_INTR_EN_CSERIREN);
  90         out_be32(&ifc->cm_erattr0, 0x0);
  91         out_be32(&ifc->cm_erattr1, 0x0);
  92
  93         return 0;
  94 }
  95
  96 static int fsl_ifc_ctrl_remove(struct platform_device *dev)
  97 {
  98         struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(&dev->dev);
  99
 100         free_irq(ctrl->nand_irq, ctrl);
 101         free_irq(ctrl->irq, ctrl);
 102
 103         irq_dispose_mapping(ctrl->nand_irq);
 104         irq_dispose_mapping(ctrl->irq);
 105
 106         iounmap(ctrl->regs);
 107
 108         dev_set_drvdata(&dev->dev, NULL);
 109         kfree(ctrl);
 110
 111         return 0;
 112 }
 113
 114 /*
 115  * NAND events are split between an operational interrupt which only
 116  * receives OPC, and an error interrupt that receives everything else,
 117  * including non-NAND errors.  Whichever interrupt gets to it first
 118  * records the status and wakes the wait queue.
 119  */
 120 static DEFINE_SPINLOCK(nand_irq_lock);
 121
 122 static u32 check_nand_stat(struct fsl_ifc_ctrl *ctrl)
 123 {
 124         struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
 125         unsigned long flags;
 126         u32 stat;
 127
 128         spin_lock_irqsave(&nand_irq_lock, flags);
 129
 130         stat = in_be32(&ifc->ifc_nand.nand_evter_stat);
 131         if (stat) {
 132                 out_be32(&ifc->ifc_nand.nand_evter_stat, stat);
 133                 ctrl->nand_stat = stat;
 134                 wake_up(&ctrl->nand_wait);
 135         }
 136
 137         spin_unlock_irqrestore(&nand_irq_lock, flags);
 138
 139         return stat;
 140 }
 141
 142 static irqreturn_t fsl_ifc_nand_irq(int irqno, void *data)
 143 {
 144         struct fsl_ifc_ctrl *ctrl = data;
 145
 146         if (check_nand_stat(ctrl))
 147                 return IRQ_HANDLED;
 148
 149         return IRQ_NONE;
 150 }
 151
 152 /*
 153  * NOTE: This interrupt is used to report ifc events of various kinds,
 154  * such as transaction errors on the chipselects.
 155  */
 156 static irqreturn_t fsl_ifc_ctrl_irq(int irqno, void *data)
 157 {
 158         struct fsl_ifc_ctrl *ctrl = data;
 159         struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
 160         u32 err_axiid, err_srcid, status, cs_err, err_addr;
 161         irqreturn_t ret = IRQ_NONE;
 162
 163         /* read for chip select error */
 164         cs_err = in_be32(&ifc->cm_evter_stat);
 165         if (cs_err) {
 166                 dev_err(ctrl->dev, "transaction sent to IFC is not mapped to"
 167                                 "any memory bank 0x%08X\n", cs_err);
 168                 /* clear the chip select error */
 169                 out_be32(&ifc->cm_evter_stat, IFC_CM_EVTER_STAT_CSER);
 170
 171                 /* read error attribute registers print the error information */
 172                 status = in_be32(&ifc->cm_erattr0);
 173                 err_addr = in_be32(&ifc->cm_erattr1);
 174
 175                 if (status & IFC_CM_ERATTR0_ERTYP_READ)
 176                         dev_err(ctrl->dev, "Read transaction error"
 177                                 "CM_ERATTR0 0x%08X\n", status);
 178                 else
 179                         dev_err(ctrl->dev, "Write transaction error"
 180                                 "CM_ERATTR0 0x%08X\n", status);
 181
 182                 err_axiid = (status & IFC_CM_ERATTR0_ERAID) >>
 183                                         IFC_CM_ERATTR0_ERAID_SHIFT;
 184                 dev_err(ctrl->dev, "AXI ID of the error"
 185                                         "transaction 0x%08X\n", err_axiid);
 186
 187                 err_srcid = (status & IFC_CM_ERATTR0_ESRCID) >>
 188                                         IFC_CM_ERATTR0_ESRCID_SHIFT;
 189                 dev_err(ctrl->dev, "SRC ID of the error"
 190                                         "transaction 0x%08X\n", err_srcid);
 191
 192                 dev_err(ctrl->dev, "Transaction Address corresponding to error"
 193                                         "ERADDR 0x%08X\n", err_addr);
 194
 195                 ret = IRQ_HANDLED;
 196         }
 197
 198         if (check_nand_stat(ctrl))
 199                 ret = IRQ_HANDLED;
 200
 201         return ret;
 202 }
 203
 204 /*
 205  * fsl_ifc_ctrl_probe
 206  *
 207  * called by device layer when it finds a device matching
 208  * one our driver can handled. This code allocates all of
 209  * the resources needed for the controller only.  The
 210  * resources for the NAND banks themselves are allocated
 211  * in the chip probe function.
 212 */
 213 static int fsl_ifc_ctrl_probe(struct platform_device *dev)
 214 {
 215         int ret = 0;
 216
 217
 218         dev_info(&dev->dev, "Freescale Integrated Flash Controller\n");
 219
 220         fsl_ifc_ctrl_dev = kzalloc(sizeof(*fsl_ifc_ctrl_dev), GFP_KERNEL);
 221         if (!fsl_ifc_ctrl_dev)
 222                 return -ENOMEM;
 223
 224         dev_set_drvdata(&dev->dev, fsl_ifc_ctrl_dev);
 225
 226         /* IOMAP the entire IFC region */
 227         fsl_ifc_ctrl_dev->regs = of_iomap(dev->dev.of_node, 0);
 228         if (!fsl_ifc_ctrl_dev->regs) {
 229                 dev_err(&dev->dev, "failed to get memory region\n");
 230                 ret = -ENODEV;
 231                 goto err;
 232         }
 233
 234         /* get the Controller level irq */
 235         fsl_ifc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0);
 236         if (fsl_ifc_ctrl_dev->irq == NO_IRQ) {
 237                 dev_err(&dev->dev, "failed to get irq resource "
 238                                                         "for IFC\n");
 239                 ret = -ENODEV;
 240                 goto err;
 241         }
 242
 243         /* get the nand machine irq */
 244         fsl_ifc_ctrl_dev->nand_irq =
 245                         irq_of_parse_and_map(dev->dev.of_node, 1);
 246
 247         fsl_ifc_ctrl_dev->dev = &dev->dev;
 248
 249         ret = fsl_ifc_ctrl_init(fsl_ifc_ctrl_dev);
 250         if (ret < 0)
 251                 goto err;
 252
 253         init_waitqueue_head(&fsl_ifc_ctrl_dev->nand_wait);
 254
 255         ret = request_irq(fsl_ifc_ctrl_dev->irq, fsl_ifc_ctrl_irq, IRQF_SHARED,
 256                           "fsl-ifc", fsl_ifc_ctrl_dev);
 257         if (ret != 0) {
 258                 dev_err(&dev->dev, "failed to install irq (%d)\n",
 259                         fsl_ifc_ctrl_dev->irq);
 260                 goto err_irq;
 261         }
 262
 263         if (fsl_ifc_ctrl_dev->nand_irq) {
 264                 ret = request_irq(fsl_ifc_ctrl_dev->nand_irq, fsl_ifc_nand_irq,
 265                                 0, "fsl-ifc-nand", fsl_ifc_ctrl_dev);
 266                 if (ret != 0) {
 267                         dev_err(&dev->dev, "failed to install irq (%d)\n",
 268                                 fsl_ifc_ctrl_dev->nand_irq);
 269                         goto err_nandirq;
 270                 }
 271         }
 272
 273         return 0;
 274
 275 err_nandirq:
 276         free_irq(fsl_ifc_ctrl_dev->nand_irq, fsl_ifc_ctrl_dev);
 277         irq_dispose_mapping(fsl_ifc_ctrl_dev->nand_irq);
 278 err_irq:
 279         free_irq(fsl_ifc_ctrl_dev->irq, fsl_ifc_ctrl_dev);
 280         irq_dispose_mapping(fsl_ifc_ctrl_dev->irq);
 281 err:
 282         return ret;
 283 }
 284
 285 static const struct of_device_id fsl_ifc_match[] = {
 286         {
 287                 .compatible = "fsl,ifc",
 288         },
 289         {},
 290 };
 291
 292 static struct platform_driver fsl_ifc_ctrl_driver = {
 293         .driver = {
 294                 .name   = "fsl-ifc",
 295                 .of_match_table = fsl_ifc_match,
 296         },
 297         .probe       = fsl_ifc_ctrl_probe,
 298         .remove      = fsl_ifc_ctrl_remove,
 299 };
 300
 301 static int __init fsl_ifc_init(void)
 302 {
 303         return platform_driver_register(&fsl_ifc_ctrl_driver);
 304 }
 305 subsys_initcall(fsl_ifc_init);
 306
 307 MODULE_LICENSE("GPL");
 308 MODULE_AUTHOR("Freescale Semiconductor");
 309 MODULE_DESCRIPTION("Freescale Integrated Flash Controller driver");