2 * Copyright (C) 2013 NVIDIA Corporation
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include <linux/debugfs.h>
11 #include <linux/gpio.h>
13 #include <linux/platform_device.h>
14 #include <linux/reset.h>
16 #include <soc/tegra/pmc.h>
18 #include <drm/drm_atomic_helper.h>
19 #include <drm/drm_dp_helper.h>
20 #include <drm/drm_panel.h>
27 struct host1x_client client
;
28 struct tegra_output output
;
33 struct reset_control
*rst
;
34 struct clk
*clk_parent
;
39 struct tegra_dpaux
*dpaux
;
44 struct drm_info_list
*debugfs_files
;
45 struct drm_minor
*minor
;
46 struct dentry
*debugfs
;
49 struct tegra_sor_config
{
62 static inline struct tegra_sor
*
63 host1x_client_to_sor(struct host1x_client
*client
)
65 return container_of(client
, struct tegra_sor
, client
);
68 static inline struct tegra_sor
*to_sor(struct tegra_output
*output
)
70 return container_of(output
, struct tegra_sor
, output
);
73 static inline u32
tegra_sor_readl(struct tegra_sor
*sor
, unsigned long offset
)
75 return readl(sor
->regs
+ (offset
<< 2));
78 static inline void tegra_sor_writel(struct tegra_sor
*sor
, u32 value
,
81 writel(value
, sor
->regs
+ (offset
<< 2));
84 static int tegra_sor_dp_train_fast(struct tegra_sor
*sor
,
85 struct drm_dp_link
*link
)
92 /* setup lane parameters */
93 value
= SOR_LANE_DRIVE_CURRENT_LANE3(0x40) |
94 SOR_LANE_DRIVE_CURRENT_LANE2(0x40) |
95 SOR_LANE_DRIVE_CURRENT_LANE1(0x40) |
96 SOR_LANE_DRIVE_CURRENT_LANE0(0x40);
97 tegra_sor_writel(sor
, value
, SOR_LANE_DRIVE_CURRENT0
);
99 value
= SOR_LANE_PREEMPHASIS_LANE3(0x0f) |
100 SOR_LANE_PREEMPHASIS_LANE2(0x0f) |
101 SOR_LANE_PREEMPHASIS_LANE1(0x0f) |
102 SOR_LANE_PREEMPHASIS_LANE0(0x0f);
103 tegra_sor_writel(sor
, value
, SOR_LANE_PREEMPHASIS0
);
105 value
= SOR_LANE_POSTCURSOR_LANE3(0x00) |
106 SOR_LANE_POSTCURSOR_LANE2(0x00) |
107 SOR_LANE_POSTCURSOR_LANE1(0x00) |
108 SOR_LANE_POSTCURSOR_LANE0(0x00);
109 tegra_sor_writel(sor
, value
, SOR_LANE_POSTCURSOR0
);
111 /* disable LVDS mode */
112 tegra_sor_writel(sor
, 0, SOR_LVDS
);
114 value
= tegra_sor_readl(sor
, SOR_DP_PADCTL0
);
115 value
|= SOR_DP_PADCTL_TX_PU_ENABLE
;
116 value
&= ~SOR_DP_PADCTL_TX_PU_MASK
;
117 value
|= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */
118 tegra_sor_writel(sor
, value
, SOR_DP_PADCTL0
);
120 value
= tegra_sor_readl(sor
, SOR_DP_PADCTL0
);
121 value
|= SOR_DP_PADCTL_CM_TXD_3
| SOR_DP_PADCTL_CM_TXD_2
|
122 SOR_DP_PADCTL_CM_TXD_1
| SOR_DP_PADCTL_CM_TXD_0
;
123 tegra_sor_writel(sor
, value
, SOR_DP_PADCTL0
);
125 usleep_range(10, 100);
127 value
= tegra_sor_readl(sor
, SOR_DP_PADCTL0
);
128 value
&= ~(SOR_DP_PADCTL_CM_TXD_3
| SOR_DP_PADCTL_CM_TXD_2
|
129 SOR_DP_PADCTL_CM_TXD_1
| SOR_DP_PADCTL_CM_TXD_0
);
130 tegra_sor_writel(sor
, value
, SOR_DP_PADCTL0
);
132 err
= tegra_dpaux_prepare(sor
->dpaux
, DP_SET_ANSI_8B10B
);
136 for (i
= 0, value
= 0; i
< link
->num_lanes
; i
++) {
137 unsigned long lane
= SOR_DP_TPG_CHANNEL_CODING
|
138 SOR_DP_TPG_SCRAMBLER_NONE
|
139 SOR_DP_TPG_PATTERN_TRAIN1
;
140 value
= (value
<< 8) | lane
;
143 tegra_sor_writel(sor
, value
, SOR_DP_TPG
);
145 pattern
= DP_TRAINING_PATTERN_1
;
147 err
= tegra_dpaux_train(sor
->dpaux
, link
, pattern
);
151 value
= tegra_sor_readl(sor
, SOR_DP_SPARE0
);
152 value
|= SOR_DP_SPARE_SEQ_ENABLE
;
153 value
&= ~SOR_DP_SPARE_PANEL_INTERNAL
;
154 value
|= SOR_DP_SPARE_MACRO_SOR_CLK
;
155 tegra_sor_writel(sor
, value
, SOR_DP_SPARE0
);
157 for (i
= 0, value
= 0; i
< link
->num_lanes
; i
++) {
158 unsigned long lane
= SOR_DP_TPG_CHANNEL_CODING
|
159 SOR_DP_TPG_SCRAMBLER_NONE
|
160 SOR_DP_TPG_PATTERN_TRAIN2
;
161 value
= (value
<< 8) | lane
;
164 tegra_sor_writel(sor
, value
, SOR_DP_TPG
);
166 pattern
= DP_LINK_SCRAMBLING_DISABLE
| DP_TRAINING_PATTERN_2
;
168 err
= tegra_dpaux_train(sor
->dpaux
, link
, pattern
);
172 for (i
= 0, value
= 0; i
< link
->num_lanes
; i
++) {
173 unsigned long lane
= SOR_DP_TPG_CHANNEL_CODING
|
174 SOR_DP_TPG_SCRAMBLER_GALIOS
|
175 SOR_DP_TPG_PATTERN_NONE
;
176 value
= (value
<< 8) | lane
;
179 tegra_sor_writel(sor
, value
, SOR_DP_TPG
);
181 pattern
= DP_TRAINING_PATTERN_DISABLE
;
183 err
= tegra_dpaux_train(sor
->dpaux
, link
, pattern
);
190 static void tegra_sor_super_update(struct tegra_sor
*sor
)
192 tegra_sor_writel(sor
, 0, SOR_SUPER_STATE0
);
193 tegra_sor_writel(sor
, 1, SOR_SUPER_STATE0
);
194 tegra_sor_writel(sor
, 0, SOR_SUPER_STATE0
);
197 static void tegra_sor_update(struct tegra_sor
*sor
)
199 tegra_sor_writel(sor
, 0, SOR_STATE0
);
200 tegra_sor_writel(sor
, 1, SOR_STATE0
);
201 tegra_sor_writel(sor
, 0, SOR_STATE0
);
204 static int tegra_sor_setup_pwm(struct tegra_sor
*sor
, unsigned long timeout
)
208 value
= tegra_sor_readl(sor
, SOR_PWM_DIV
);
209 value
&= ~SOR_PWM_DIV_MASK
;
210 value
|= 0x400; /* period */
211 tegra_sor_writel(sor
, value
, SOR_PWM_DIV
);
213 value
= tegra_sor_readl(sor
, SOR_PWM_CTL
);
214 value
&= ~SOR_PWM_CTL_DUTY_CYCLE_MASK
;
215 value
|= 0x400; /* duty cycle */
216 value
&= ~SOR_PWM_CTL_CLK_SEL
; /* clock source: PCLK */
217 value
|= SOR_PWM_CTL_TRIGGER
;
218 tegra_sor_writel(sor
, value
, SOR_PWM_CTL
);
220 timeout
= jiffies
+ msecs_to_jiffies(timeout
);
222 while (time_before(jiffies
, timeout
)) {
223 value
= tegra_sor_readl(sor
, SOR_PWM_CTL
);
224 if ((value
& SOR_PWM_CTL_TRIGGER
) == 0)
227 usleep_range(25, 100);
233 static int tegra_sor_attach(struct tegra_sor
*sor
)
235 unsigned long value
, timeout
;
237 /* wake up in normal mode */
238 value
= tegra_sor_readl(sor
, SOR_SUPER_STATE1
);
239 value
|= SOR_SUPER_STATE_HEAD_MODE_AWAKE
;
240 value
|= SOR_SUPER_STATE_MODE_NORMAL
;
241 tegra_sor_writel(sor
, value
, SOR_SUPER_STATE1
);
242 tegra_sor_super_update(sor
);
245 value
= tegra_sor_readl(sor
, SOR_SUPER_STATE1
);
246 value
|= SOR_SUPER_STATE_ATTACHED
;
247 tegra_sor_writel(sor
, value
, SOR_SUPER_STATE1
);
248 tegra_sor_super_update(sor
);
250 timeout
= jiffies
+ msecs_to_jiffies(250);
252 while (time_before(jiffies
, timeout
)) {
253 value
= tegra_sor_readl(sor
, SOR_TEST
);
254 if ((value
& SOR_TEST_ATTACHED
) != 0)
257 usleep_range(25, 100);
263 static int tegra_sor_wakeup(struct tegra_sor
*sor
)
265 unsigned long value
, timeout
;
267 timeout
= jiffies
+ msecs_to_jiffies(250);
269 /* wait for head to wake up */
270 while (time_before(jiffies
, timeout
)) {
271 value
= tegra_sor_readl(sor
, SOR_TEST
);
272 value
&= SOR_TEST_HEAD_MODE_MASK
;
274 if (value
== SOR_TEST_HEAD_MODE_AWAKE
)
277 usleep_range(25, 100);
283 static int tegra_sor_power_up(struct tegra_sor
*sor
, unsigned long timeout
)
287 value
= tegra_sor_readl(sor
, SOR_PWR
);
288 value
|= SOR_PWR_TRIGGER
| SOR_PWR_NORMAL_STATE_PU
;
289 tegra_sor_writel(sor
, value
, SOR_PWR
);
291 timeout
= jiffies
+ msecs_to_jiffies(timeout
);
293 while (time_before(jiffies
, timeout
)) {
294 value
= tegra_sor_readl(sor
, SOR_PWR
);
295 if ((value
& SOR_PWR_TRIGGER
) == 0)
298 usleep_range(25, 100);
304 struct tegra_sor_params
{
305 /* number of link clocks per line */
306 unsigned int num_clocks
;
307 /* ratio between input and output */
309 /* precision factor */
312 unsigned int active_polarity
;
313 unsigned int active_count
;
314 unsigned int active_frac
;
315 unsigned int tu_size
;
319 static int tegra_sor_compute_params(struct tegra_sor
*sor
,
320 struct tegra_sor_params
*params
,
321 unsigned int tu_size
)
323 u64 active_sym
, active_count
, frac
, approx
;
324 u32 active_polarity
, active_frac
= 0;
325 const u64 f
= params
->precision
;
328 active_sym
= params
->ratio
* tu_size
;
329 active_count
= div_u64(active_sym
, f
) * f
;
330 frac
= active_sym
- active_count
;
333 if (frac
>= (f
/ 2)) {
341 frac
= div_u64(f
* f
, frac
); /* 1/fraction */
342 if (frac
<= (15 * f
)) {
343 active_frac
= div_u64(frac
, f
);
349 active_frac
= active_polarity
? 1 : 15;
353 if (active_frac
== 1)
356 if (active_polarity
== 1) {
358 approx
= active_count
+ (active_frac
* (f
- 1)) * f
;
359 approx
= div_u64(approx
, active_frac
* f
);
361 approx
= active_count
+ f
;
365 approx
= active_count
+ div_u64(f
, active_frac
);
367 approx
= active_count
;
370 error
= div_s64(active_sym
- approx
, tu_size
);
371 error
*= params
->num_clocks
;
373 if (error
<= 0 && abs64(error
) < params
->error
) {
374 params
->active_count
= div_u64(active_count
, f
);
375 params
->active_polarity
= active_polarity
;
376 params
->active_frac
= active_frac
;
377 params
->error
= abs64(error
);
378 params
->tu_size
= tu_size
;
387 static int tegra_sor_calc_config(struct tegra_sor
*sor
,
388 struct drm_display_mode
*mode
,
389 struct tegra_sor_config
*config
,
390 struct drm_dp_link
*link
)
392 const u64 f
= 100000, link_rate
= link
->rate
* 1000;
393 const u64 pclk
= mode
->clock
* 1000;
394 u64 input
, output
, watermark
, num
;
395 struct tegra_sor_params params
;
396 u32 num_syms_per_line
;
399 if (!link_rate
|| !link
->num_lanes
|| !pclk
|| !config
->bits_per_pixel
)
402 output
= link_rate
* 8 * link
->num_lanes
;
403 input
= pclk
* config
->bits_per_pixel
;
408 memset(¶ms
, 0, sizeof(params
));
409 params
.ratio
= div64_u64(input
* f
, output
);
410 params
.num_clocks
= div_u64(link_rate
* mode
->hdisplay
, pclk
);
411 params
.precision
= f
;
412 params
.error
= 64 * f
;
415 for (i
= params
.tu_size
; i
>= 32; i
--)
416 if (tegra_sor_compute_params(sor
, ¶ms
, i
))
419 if (params
.active_frac
== 0) {
420 config
->active_polarity
= 0;
421 config
->active_count
= params
.active_count
;
423 if (!params
.active_polarity
)
424 config
->active_count
--;
426 config
->tu_size
= params
.tu_size
;
427 config
->active_frac
= 1;
429 config
->active_polarity
= params
.active_polarity
;
430 config
->active_count
= params
.active_count
;
431 config
->active_frac
= params
.active_frac
;
432 config
->tu_size
= params
.tu_size
;
436 "polarity: %d active count: %d tu size: %d active frac: %d\n",
437 config
->active_polarity
, config
->active_count
,
438 config
->tu_size
, config
->active_frac
);
440 watermark
= params
.ratio
* config
->tu_size
* (f
- params
.ratio
);
441 watermark
= div_u64(watermark
, f
);
443 watermark
= div_u64(watermark
+ params
.error
, f
);
444 config
->watermark
= watermark
+ (config
->bits_per_pixel
/ 8) + 2;
445 num_syms_per_line
= (mode
->hdisplay
* config
->bits_per_pixel
) *
446 (link
->num_lanes
* 8);
448 if (config
->watermark
> 30) {
449 config
->watermark
= 30;
451 "unable to compute TU size, forcing watermark to %u\n",
453 } else if (config
->watermark
> num_syms_per_line
) {
454 config
->watermark
= num_syms_per_line
;
455 dev_err(sor
->dev
, "watermark too high, forcing to %u\n",
459 /* compute the number of symbols per horizontal blanking interval */
460 num
= ((mode
->htotal
- mode
->hdisplay
) - 7) * link_rate
;
461 config
->hblank_symbols
= div_u64(num
, pclk
);
463 if (link
->capabilities
& DP_LINK_CAP_ENHANCED_FRAMING
)
464 config
->hblank_symbols
-= 3;
466 config
->hblank_symbols
-= 12 / link
->num_lanes
;
468 /* compute the number of symbols per vertical blanking interval */
469 num
= (mode
->hdisplay
- 25) * link_rate
;
470 config
->vblank_symbols
= div_u64(num
, pclk
);
471 config
->vblank_symbols
-= 36 / link
->num_lanes
+ 4;
473 dev_dbg(sor
->dev
, "blank symbols: H:%u V:%u\n", config
->hblank_symbols
,
474 config
->vblank_symbols
);
479 static int tegra_sor_detach(struct tegra_sor
*sor
)
481 unsigned long value
, timeout
;
483 /* switch to safe mode */
484 value
= tegra_sor_readl(sor
, SOR_SUPER_STATE1
);
485 value
&= ~SOR_SUPER_STATE_MODE_NORMAL
;
486 tegra_sor_writel(sor
, value
, SOR_SUPER_STATE1
);
487 tegra_sor_super_update(sor
);
489 timeout
= jiffies
+ msecs_to_jiffies(250);
491 while (time_before(jiffies
, timeout
)) {
492 value
= tegra_sor_readl(sor
, SOR_PWR
);
493 if (value
& SOR_PWR_MODE_SAFE
)
497 if ((value
& SOR_PWR_MODE_SAFE
) == 0)
501 value
= tegra_sor_readl(sor
, SOR_SUPER_STATE1
);
502 value
&= ~SOR_SUPER_STATE_HEAD_MODE_MASK
;
503 tegra_sor_writel(sor
, value
, SOR_SUPER_STATE1
);
504 tegra_sor_super_update(sor
);
507 value
= tegra_sor_readl(sor
, SOR_SUPER_STATE1
);
508 value
&= ~SOR_SUPER_STATE_ATTACHED
;
509 tegra_sor_writel(sor
, value
, SOR_SUPER_STATE1
);
510 tegra_sor_super_update(sor
);
512 timeout
= jiffies
+ msecs_to_jiffies(250);
514 while (time_before(jiffies
, timeout
)) {
515 value
= tegra_sor_readl(sor
, SOR_TEST
);
516 if ((value
& SOR_TEST_ATTACHED
) == 0)
519 usleep_range(25, 100);
522 if ((value
& SOR_TEST_ATTACHED
) != 0)
528 static int tegra_sor_power_down(struct tegra_sor
*sor
)
530 unsigned long value
, timeout
;
533 value
= tegra_sor_readl(sor
, SOR_PWR
);
534 value
&= ~SOR_PWR_NORMAL_STATE_PU
;
535 value
|= SOR_PWR_TRIGGER
;
536 tegra_sor_writel(sor
, value
, SOR_PWR
);
538 timeout
= jiffies
+ msecs_to_jiffies(250);
540 while (time_before(jiffies
, timeout
)) {
541 value
= tegra_sor_readl(sor
, SOR_PWR
);
542 if ((value
& SOR_PWR_TRIGGER
) == 0)
545 usleep_range(25, 100);
548 if ((value
& SOR_PWR_TRIGGER
) != 0)
551 err
= clk_set_parent(sor
->clk
, sor
->clk_safe
);
553 dev_err(sor
->dev
, "failed to set safe parent clock: %d\n", err
);
555 value
= tegra_sor_readl(sor
, SOR_DP_PADCTL0
);
556 value
&= ~(SOR_DP_PADCTL_PD_TXD_3
| SOR_DP_PADCTL_PD_TXD_0
|
557 SOR_DP_PADCTL_PD_TXD_1
| SOR_DP_PADCTL_PD_TXD_2
);
558 tegra_sor_writel(sor
, value
, SOR_DP_PADCTL0
);
560 /* stop lane sequencer */
561 value
= SOR_LANE_SEQ_CTL_TRIGGER
| SOR_LANE_SEQ_CTL_SEQUENCE_UP
|
562 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN
;
563 tegra_sor_writel(sor
, value
, SOR_LANE_SEQ_CTL
);
565 timeout
= jiffies
+ msecs_to_jiffies(250);
567 while (time_before(jiffies
, timeout
)) {
568 value
= tegra_sor_readl(sor
, SOR_LANE_SEQ_CTL
);
569 if ((value
& SOR_LANE_SEQ_CTL_TRIGGER
) == 0)
572 usleep_range(25, 100);
575 if ((value
& SOR_LANE_SEQ_CTL_TRIGGER
) != 0)
578 value
= tegra_sor_readl(sor
, SOR_PLL2
);
579 value
|= SOR_PLL2_PORT_POWERDOWN
;
580 tegra_sor_writel(sor
, value
, SOR_PLL2
);
582 usleep_range(20, 100);
584 value
= tegra_sor_readl(sor
, SOR_PLL0
);
585 value
|= SOR_PLL0_VCOPD
| SOR_PLL0_PWR
;
586 tegra_sor_writel(sor
, value
, SOR_PLL0
);
588 value
= tegra_sor_readl(sor
, SOR_PLL2
);
589 value
|= SOR_PLL2_SEQ_PLLCAPPD
;
590 value
|= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE
;
591 tegra_sor_writel(sor
, value
, SOR_PLL2
);
593 usleep_range(20, 100);
598 static int tegra_sor_crc_open(struct inode
*inode
, struct file
*file
)
600 file
->private_data
= inode
->i_private
;
605 static int tegra_sor_crc_release(struct inode
*inode
, struct file
*file
)
610 static int tegra_sor_crc_wait(struct tegra_sor
*sor
, unsigned long timeout
)
614 timeout
= jiffies
+ msecs_to_jiffies(timeout
);
616 while (time_before(jiffies
, timeout
)) {
617 value
= tegra_sor_readl(sor
, SOR_CRCA
);
618 if (value
& SOR_CRCA_VALID
)
621 usleep_range(100, 200);
627 static ssize_t
tegra_sor_crc_read(struct file
*file
, char __user
*buffer
,
628 size_t size
, loff_t
*ppos
)
630 struct tegra_sor
*sor
= file
->private_data
;
635 mutex_lock(&sor
->lock
);
642 value
= tegra_sor_readl(sor
, SOR_STATE1
);
643 value
&= ~SOR_STATE_ASY_CRC_MODE_MASK
;
644 tegra_sor_writel(sor
, value
, SOR_STATE1
);
646 value
= tegra_sor_readl(sor
, SOR_CRC_CNTRL
);
647 value
|= SOR_CRC_CNTRL_ENABLE
;
648 tegra_sor_writel(sor
, value
, SOR_CRC_CNTRL
);
650 value
= tegra_sor_readl(sor
, SOR_TEST
);
651 value
&= ~SOR_TEST_CRC_POST_SERIALIZE
;
652 tegra_sor_writel(sor
, value
, SOR_TEST
);
654 err
= tegra_sor_crc_wait(sor
, 100);
658 tegra_sor_writel(sor
, SOR_CRCA_RESET
, SOR_CRCA
);
659 value
= tegra_sor_readl(sor
, SOR_CRCB
);
661 num
= scnprintf(buf
, sizeof(buf
), "%08x\n", value
);
663 err
= simple_read_from_buffer(buffer
, size
, ppos
, buf
, num
);
666 mutex_unlock(&sor
->lock
);
670 static const struct file_operations tegra_sor_crc_fops
= {
671 .owner
= THIS_MODULE
,
672 .open
= tegra_sor_crc_open
,
673 .read
= tegra_sor_crc_read
,
674 .release
= tegra_sor_crc_release
,
677 static int tegra_sor_show_regs(struct seq_file
*s
, void *data
)
679 struct drm_info_node
*node
= s
->private;
680 struct tegra_sor
*sor
= node
->info_ent
->data
;
682 #define DUMP_REG(name) \
683 seq_printf(s, "%-38s %#05x %08x\n", #name, name, \
684 tegra_sor_readl(sor, name))
687 DUMP_REG(SOR_SUPER_STATE0
);
688 DUMP_REG(SOR_SUPER_STATE1
);
689 DUMP_REG(SOR_STATE0
);
690 DUMP_REG(SOR_STATE1
);
691 DUMP_REG(SOR_HEAD_STATE0(0));
692 DUMP_REG(SOR_HEAD_STATE0(1));
693 DUMP_REG(SOR_HEAD_STATE1(0));
694 DUMP_REG(SOR_HEAD_STATE1(1));
695 DUMP_REG(SOR_HEAD_STATE2(0));
696 DUMP_REG(SOR_HEAD_STATE2(1));
697 DUMP_REG(SOR_HEAD_STATE3(0));
698 DUMP_REG(SOR_HEAD_STATE3(1));
699 DUMP_REG(SOR_HEAD_STATE4(0));
700 DUMP_REG(SOR_HEAD_STATE4(1));
701 DUMP_REG(SOR_HEAD_STATE5(0));
702 DUMP_REG(SOR_HEAD_STATE5(1));
703 DUMP_REG(SOR_CRC_CNTRL
);
704 DUMP_REG(SOR_DP_DEBUG_MVID
);
705 DUMP_REG(SOR_CLK_CNTRL
);
718 DUMP_REG(SOR_SEQ_CTL
);
719 DUMP_REG(SOR_LANE_SEQ_CTL
);
720 DUMP_REG(SOR_SEQ_INST(0));
721 DUMP_REG(SOR_SEQ_INST(1));
722 DUMP_REG(SOR_SEQ_INST(2));
723 DUMP_REG(SOR_SEQ_INST(3));
724 DUMP_REG(SOR_SEQ_INST(4));
725 DUMP_REG(SOR_SEQ_INST(5));
726 DUMP_REG(SOR_SEQ_INST(6));
727 DUMP_REG(SOR_SEQ_INST(7));
728 DUMP_REG(SOR_SEQ_INST(8));
729 DUMP_REG(SOR_SEQ_INST(9));
730 DUMP_REG(SOR_SEQ_INST(10));
731 DUMP_REG(SOR_SEQ_INST(11));
732 DUMP_REG(SOR_SEQ_INST(12));
733 DUMP_REG(SOR_SEQ_INST(13));
734 DUMP_REG(SOR_SEQ_INST(14));
735 DUMP_REG(SOR_SEQ_INST(15));
736 DUMP_REG(SOR_PWM_DIV
);
737 DUMP_REG(SOR_PWM_CTL
);
738 DUMP_REG(SOR_VCRC_A0
);
739 DUMP_REG(SOR_VCRC_A1
);
740 DUMP_REG(SOR_VCRC_B0
);
741 DUMP_REG(SOR_VCRC_B1
);
742 DUMP_REG(SOR_CCRC_A0
);
743 DUMP_REG(SOR_CCRC_A1
);
744 DUMP_REG(SOR_CCRC_B0
);
745 DUMP_REG(SOR_CCRC_B1
);
746 DUMP_REG(SOR_EDATA_A0
);
747 DUMP_REG(SOR_EDATA_A1
);
748 DUMP_REG(SOR_EDATA_B0
);
749 DUMP_REG(SOR_EDATA_B1
);
750 DUMP_REG(SOR_COUNT_A0
);
751 DUMP_REG(SOR_COUNT_A1
);
752 DUMP_REG(SOR_COUNT_B0
);
753 DUMP_REG(SOR_COUNT_B1
);
754 DUMP_REG(SOR_DEBUG_A0
);
755 DUMP_REG(SOR_DEBUG_A1
);
756 DUMP_REG(SOR_DEBUG_B0
);
757 DUMP_REG(SOR_DEBUG_B1
);
759 DUMP_REG(SOR_MSCHECK
);
760 DUMP_REG(SOR_XBAR_CTRL
);
761 DUMP_REG(SOR_XBAR_POL
);
762 DUMP_REG(SOR_DP_LINKCTL0
);
763 DUMP_REG(SOR_DP_LINKCTL1
);
764 DUMP_REG(SOR_LANE_DRIVE_CURRENT0
);
765 DUMP_REG(SOR_LANE_DRIVE_CURRENT1
);
766 DUMP_REG(SOR_LANE4_DRIVE_CURRENT0
);
767 DUMP_REG(SOR_LANE4_DRIVE_CURRENT1
);
768 DUMP_REG(SOR_LANE_PREEMPHASIS0
);
769 DUMP_REG(SOR_LANE_PREEMPHASIS1
);
770 DUMP_REG(SOR_LANE4_PREEMPHASIS0
);
771 DUMP_REG(SOR_LANE4_PREEMPHASIS1
);
772 DUMP_REG(SOR_LANE_POSTCURSOR0
);
773 DUMP_REG(SOR_LANE_POSTCURSOR1
);
774 DUMP_REG(SOR_DP_CONFIG0
);
775 DUMP_REG(SOR_DP_CONFIG1
);
776 DUMP_REG(SOR_DP_MN0
);
777 DUMP_REG(SOR_DP_MN1
);
778 DUMP_REG(SOR_DP_PADCTL0
);
779 DUMP_REG(SOR_DP_PADCTL1
);
780 DUMP_REG(SOR_DP_DEBUG0
);
781 DUMP_REG(SOR_DP_DEBUG1
);
782 DUMP_REG(SOR_DP_SPARE0
);
783 DUMP_REG(SOR_DP_SPARE1
);
784 DUMP_REG(SOR_DP_AUDIO_CTRL
);
785 DUMP_REG(SOR_DP_AUDIO_HBLANK_SYMBOLS
);
786 DUMP_REG(SOR_DP_AUDIO_VBLANK_SYMBOLS
);
787 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_HEADER
);
788 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK0
);
789 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK1
);
790 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK2
);
791 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK3
);
792 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK4
);
793 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK5
);
794 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK6
);
795 DUMP_REG(SOR_DP_TPG
);
796 DUMP_REG(SOR_DP_TPG_CONFIG
);
797 DUMP_REG(SOR_DP_LQ_CSTM0
);
798 DUMP_REG(SOR_DP_LQ_CSTM1
);
799 DUMP_REG(SOR_DP_LQ_CSTM2
);
806 static const struct drm_info_list debugfs_files
[] = {
807 { "regs", tegra_sor_show_regs
, 0, NULL
},
810 static int tegra_sor_debugfs_init(struct tegra_sor
*sor
,
811 struct drm_minor
*minor
)
813 struct dentry
*entry
;
817 sor
->debugfs
= debugfs_create_dir("sor", minor
->debugfs_root
);
821 sor
->debugfs_files
= kmemdup(debugfs_files
, sizeof(debugfs_files
),
823 if (!sor
->debugfs_files
) {
828 for (i
= 0; i
< ARRAY_SIZE(debugfs_files
); i
++)
829 sor
->debugfs_files
[i
].data
= sor
;
831 err
= drm_debugfs_create_files(sor
->debugfs_files
,
832 ARRAY_SIZE(debugfs_files
),
833 sor
->debugfs
, minor
);
837 entry
= debugfs_create_file("crc", 0644, sor
->debugfs
, sor
,
838 &tegra_sor_crc_fops
);
847 kfree(sor
->debugfs_files
);
848 sor
->debugfs_files
= NULL
;
850 debugfs_remove_recursive(sor
->debugfs
);
855 static void tegra_sor_debugfs_exit(struct tegra_sor
*sor
)
857 drm_debugfs_remove_files(sor
->debugfs_files
, ARRAY_SIZE(debugfs_files
),
861 kfree(sor
->debugfs_files
);
864 debugfs_remove_recursive(sor
->debugfs
);
865 sor
->debugfs_files
= NULL
;
868 static void tegra_sor_connector_dpms(struct drm_connector
*connector
, int mode
)
872 static enum drm_connector_status
873 tegra_sor_connector_detect(struct drm_connector
*connector
, bool force
)
875 struct tegra_output
*output
= connector_to_output(connector
);
876 struct tegra_sor
*sor
= to_sor(output
);
879 return tegra_dpaux_detect(sor
->dpaux
);
881 return connector_status_unknown
;
884 static const struct drm_connector_funcs tegra_sor_connector_funcs
= {
885 .dpms
= tegra_sor_connector_dpms
,
886 .reset
= drm_atomic_helper_connector_reset
,
887 .detect
= tegra_sor_connector_detect
,
888 .fill_modes
= drm_helper_probe_single_connector_modes
,
889 .destroy
= tegra_output_connector_destroy
,
890 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
891 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
894 static int tegra_sor_connector_get_modes(struct drm_connector
*connector
)
896 struct tegra_output
*output
= connector_to_output(connector
);
897 struct tegra_sor
*sor
= to_sor(output
);
901 tegra_dpaux_enable(sor
->dpaux
);
903 err
= tegra_output_connector_get_modes(connector
);
906 tegra_dpaux_disable(sor
->dpaux
);
911 static enum drm_mode_status
912 tegra_sor_connector_mode_valid(struct drm_connector
*connector
,
913 struct drm_display_mode
*mode
)
918 static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs
= {
919 .get_modes
= tegra_sor_connector_get_modes
,
920 .mode_valid
= tegra_sor_connector_mode_valid
,
921 .best_encoder
= tegra_output_connector_best_encoder
,
924 static const struct drm_encoder_funcs tegra_sor_encoder_funcs
= {
925 .destroy
= tegra_output_encoder_destroy
,
928 static void tegra_sor_encoder_dpms(struct drm_encoder
*encoder
, int mode
)
932 static void tegra_sor_encoder_prepare(struct drm_encoder
*encoder
)
936 static void tegra_sor_encoder_commit(struct drm_encoder
*encoder
)
940 static void tegra_sor_encoder_mode_set(struct drm_encoder
*encoder
,
941 struct drm_display_mode
*mode
,
942 struct drm_display_mode
*adjusted
)
944 struct tegra_output
*output
= encoder_to_output(encoder
);
945 struct tegra_dc
*dc
= to_tegra_dc(encoder
->crtc
);
946 unsigned int vbe
, vse
, hbe
, hse
, vbs
, hbs
, i
;
947 struct tegra_sor
*sor
= to_sor(output
);
948 struct tegra_sor_config config
;
949 struct drm_dp_link link
;
950 struct drm_dp_aux
*aux
;
954 mutex_lock(&sor
->lock
);
959 err
= clk_prepare_enable(sor
->clk
);
963 reset_control_deassert(sor
->rst
);
966 drm_panel_prepare(output
->panel
);
968 /* FIXME: properly convert to struct drm_dp_aux */
969 aux
= (struct drm_dp_aux
*)sor
->dpaux
;
972 err
= tegra_dpaux_enable(sor
->dpaux
);
974 dev_err(sor
->dev
, "failed to enable DP: %d\n", err
);
976 err
= drm_dp_link_probe(aux
, &link
);
978 dev_err(sor
->dev
, "failed to probe eDP link: %d\n",
984 err
= clk_set_parent(sor
->clk
, sor
->clk_safe
);
986 dev_err(sor
->dev
, "failed to set safe parent clock: %d\n", err
);
988 memset(&config
, 0, sizeof(config
));
989 config
.bits_per_pixel
= output
->connector
.display_info
.bpc
* 3;
991 err
= tegra_sor_calc_config(sor
, mode
, &config
, &link
);
993 dev_err(sor
->dev
, "failed to compute link configuration: %d\n",
996 value
= tegra_sor_readl(sor
, SOR_CLK_CNTRL
);
997 value
&= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK
;
998 value
|= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK
;
999 tegra_sor_writel(sor
, value
, SOR_CLK_CNTRL
);
1001 value
= tegra_sor_readl(sor
, SOR_PLL2
);
1002 value
&= ~SOR_PLL2_BANDGAP_POWERDOWN
;
1003 tegra_sor_writel(sor
, value
, SOR_PLL2
);
1004 usleep_range(20, 100);
1006 value
= tegra_sor_readl(sor
, SOR_PLL3
);
1007 value
|= SOR_PLL3_PLL_VDD_MODE_3V3
;
1008 tegra_sor_writel(sor
, value
, SOR_PLL3
);
1010 value
= SOR_PLL0_ICHPMP(0xf) | SOR_PLL0_VCOCAP_RST
|
1011 SOR_PLL0_PLLREG_LEVEL_V45
| SOR_PLL0_RESISTOR_EXT
;
1012 tegra_sor_writel(sor
, value
, SOR_PLL0
);
1014 value
= tegra_sor_readl(sor
, SOR_PLL2
);
1015 value
|= SOR_PLL2_SEQ_PLLCAPPD
;
1016 value
&= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE
;
1017 value
|= SOR_PLL2_LVDS_ENABLE
;
1018 tegra_sor_writel(sor
, value
, SOR_PLL2
);
1020 value
= SOR_PLL1_TERM_COMPOUT
| SOR_PLL1_TMDS_TERM
;
1021 tegra_sor_writel(sor
, value
, SOR_PLL1
);
1024 value
= tegra_sor_readl(sor
, SOR_PLL2
);
1025 if ((value
& SOR_PLL2_SEQ_PLLCAPPD_ENFORCE
) == 0)
1028 usleep_range(250, 1000);
1031 value
= tegra_sor_readl(sor
, SOR_PLL2
);
1032 value
&= ~SOR_PLL2_POWERDOWN_OVERRIDE
;
1033 value
&= ~SOR_PLL2_PORT_POWERDOWN
;
1034 tegra_sor_writel(sor
, value
, SOR_PLL2
);
1040 /* set safe link bandwidth (1.62 Gbps) */
1041 value
= tegra_sor_readl(sor
, SOR_CLK_CNTRL
);
1042 value
&= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK
;
1043 value
|= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62
;
1044 tegra_sor_writel(sor
, value
, SOR_CLK_CNTRL
);
1047 value
= tegra_sor_readl(sor
, SOR_PLL2
);
1048 value
|= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE
| SOR_PLL2_PORT_POWERDOWN
|
1049 SOR_PLL2_BANDGAP_POWERDOWN
;
1050 tegra_sor_writel(sor
, value
, SOR_PLL2
);
1052 value
= tegra_sor_readl(sor
, SOR_PLL0
);
1053 value
|= SOR_PLL0_VCOPD
| SOR_PLL0_PWR
;
1054 tegra_sor_writel(sor
, value
, SOR_PLL0
);
1056 value
= tegra_sor_readl(sor
, SOR_DP_PADCTL0
);
1057 value
&= ~SOR_DP_PADCTL_PAD_CAL_PD
;
1058 tegra_sor_writel(sor
, value
, SOR_DP_PADCTL0
);
1061 err
= tegra_io_rail_power_on(TEGRA_IO_RAIL_LVDS
);
1063 dev_err(sor
->dev
, "failed to power on I/O rail: %d\n", err
);
1067 usleep_range(5, 100);
1070 value
= tegra_sor_readl(sor
, SOR_PLL2
);
1071 value
&= ~SOR_PLL2_BANDGAP_POWERDOWN
;
1072 tegra_sor_writel(sor
, value
, SOR_PLL2
);
1074 usleep_range(20, 100);
1077 value
= tegra_sor_readl(sor
, SOR_PLL0
);
1078 value
&= ~SOR_PLL0_VCOPD
;
1079 value
&= ~SOR_PLL0_PWR
;
1080 tegra_sor_writel(sor
, value
, SOR_PLL0
);
1082 value
= tegra_sor_readl(sor
, SOR_PLL2
);
1083 value
&= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE
;
1084 tegra_sor_writel(sor
, value
, SOR_PLL2
);
1086 usleep_range(200, 1000);
1089 value
= tegra_sor_readl(sor
, SOR_PLL2
);
1090 value
&= ~SOR_PLL2_PORT_POWERDOWN
;
1091 tegra_sor_writel(sor
, value
, SOR_PLL2
);
1093 /* switch to DP clock */
1094 err
= clk_set_parent(sor
->clk
, sor
->clk_dp
);
1096 dev_err(sor
->dev
, "failed to set DP parent clock: %d\n", err
);
1098 /* power DP lanes */
1099 value
= tegra_sor_readl(sor
, SOR_DP_PADCTL0
);
1101 if (link
.num_lanes
<= 2)
1102 value
&= ~(SOR_DP_PADCTL_PD_TXD_3
| SOR_DP_PADCTL_PD_TXD_2
);
1104 value
|= SOR_DP_PADCTL_PD_TXD_3
| SOR_DP_PADCTL_PD_TXD_2
;
1106 if (link
.num_lanes
<= 1)
1107 value
&= ~SOR_DP_PADCTL_PD_TXD_1
;
1109 value
|= SOR_DP_PADCTL_PD_TXD_1
;
1111 if (link
.num_lanes
== 0)
1112 value
&= ~SOR_DP_PADCTL_PD_TXD_0
;
1114 value
|= SOR_DP_PADCTL_PD_TXD_0
;
1116 tegra_sor_writel(sor
, value
, SOR_DP_PADCTL0
);
1118 value
= tegra_sor_readl(sor
, SOR_DP_LINKCTL0
);
1119 value
&= ~SOR_DP_LINKCTL_LANE_COUNT_MASK
;
1120 value
|= SOR_DP_LINKCTL_LANE_COUNT(link
.num_lanes
);
1121 tegra_sor_writel(sor
, value
, SOR_DP_LINKCTL0
);
1123 /* start lane sequencer */
1124 value
= SOR_LANE_SEQ_CTL_TRIGGER
| SOR_LANE_SEQ_CTL_SEQUENCE_DOWN
|
1125 SOR_LANE_SEQ_CTL_POWER_STATE_UP
;
1126 tegra_sor_writel(sor
, value
, SOR_LANE_SEQ_CTL
);
1129 value
= tegra_sor_readl(sor
, SOR_LANE_SEQ_CTL
);
1130 if ((value
& SOR_LANE_SEQ_CTL_TRIGGER
) == 0)
1133 usleep_range(250, 1000);
1136 /* set link bandwidth */
1137 value
= tegra_sor_readl(sor
, SOR_CLK_CNTRL
);
1138 value
&= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK
;
1139 value
|= drm_dp_link_rate_to_bw_code(link
.rate
) << 2;
1140 tegra_sor_writel(sor
, value
, SOR_CLK_CNTRL
);
1143 value
= tegra_sor_readl(sor
, SOR_DP_LINKCTL0
);
1144 value
|= SOR_DP_LINKCTL_ENABLE
;
1146 value
&= ~SOR_DP_LINKCTL_TU_SIZE_MASK
;
1147 value
|= SOR_DP_LINKCTL_TU_SIZE(config
.tu_size
);
1149 value
|= SOR_DP_LINKCTL_ENHANCED_FRAME
;
1150 tegra_sor_writel(sor
, value
, SOR_DP_LINKCTL0
);
1152 for (i
= 0, value
= 0; i
< 4; i
++) {
1153 unsigned long lane
= SOR_DP_TPG_CHANNEL_CODING
|
1154 SOR_DP_TPG_SCRAMBLER_GALIOS
|
1155 SOR_DP_TPG_PATTERN_NONE
;
1156 value
= (value
<< 8) | lane
;
1159 tegra_sor_writel(sor
, value
, SOR_DP_TPG
);
1161 value
= tegra_sor_readl(sor
, SOR_DP_CONFIG0
);
1162 value
&= ~SOR_DP_CONFIG_WATERMARK_MASK
;
1163 value
|= SOR_DP_CONFIG_WATERMARK(config
.watermark
);
1165 value
&= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK
;
1166 value
|= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config
.active_count
);
1168 value
&= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK
;
1169 value
|= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config
.active_frac
);
1171 if (config
.active_polarity
)
1172 value
|= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY
;
1174 value
&= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY
;
1176 value
|= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE
;
1177 value
|= SOR_DP_CONFIG_DISPARITY_NEGATIVE
;
1178 tegra_sor_writel(sor
, value
, SOR_DP_CONFIG0
);
1180 value
= tegra_sor_readl(sor
, SOR_DP_AUDIO_HBLANK_SYMBOLS
);
1181 value
&= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK
;
1182 value
|= config
.hblank_symbols
& 0xffff;
1183 tegra_sor_writel(sor
, value
, SOR_DP_AUDIO_HBLANK_SYMBOLS
);
1185 value
= tegra_sor_readl(sor
, SOR_DP_AUDIO_VBLANK_SYMBOLS
);
1186 value
&= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK
;
1187 value
|= config
.vblank_symbols
& 0xffff;
1188 tegra_sor_writel(sor
, value
, SOR_DP_AUDIO_VBLANK_SYMBOLS
);
1190 /* enable pad calibration logic */
1191 value
= tegra_sor_readl(sor
, SOR_DP_PADCTL0
);
1192 value
|= SOR_DP_PADCTL_PAD_CAL_PD
;
1193 tegra_sor_writel(sor
, value
, SOR_DP_PADCTL0
);
1198 err
= drm_dp_link_probe(aux
, &link
);
1200 dev_err(sor
->dev
, "failed to probe eDP link: %d\n",
1205 err
= drm_dp_link_power_up(aux
, &link
);
1207 dev_err(sor
->dev
, "failed to power up eDP link: %d\n",
1212 err
= drm_dp_link_configure(aux
, &link
);
1214 dev_err(sor
->dev
, "failed to configure eDP link: %d\n",
1219 rate
= drm_dp_link_rate_to_bw_code(link
.rate
);
1220 lanes
= link
.num_lanes
;
1222 value
= tegra_sor_readl(sor
, SOR_CLK_CNTRL
);
1223 value
&= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK
;
1224 value
|= SOR_CLK_CNTRL_DP_LINK_SPEED(rate
);
1225 tegra_sor_writel(sor
, value
, SOR_CLK_CNTRL
);
1227 value
= tegra_sor_readl(sor
, SOR_DP_LINKCTL0
);
1228 value
&= ~SOR_DP_LINKCTL_LANE_COUNT_MASK
;
1229 value
|= SOR_DP_LINKCTL_LANE_COUNT(lanes
);
1231 if (link
.capabilities
& DP_LINK_CAP_ENHANCED_FRAMING
)
1232 value
|= SOR_DP_LINKCTL_ENHANCED_FRAME
;
1234 tegra_sor_writel(sor
, value
, SOR_DP_LINKCTL0
);
1236 /* disable training pattern generator */
1238 for (i
= 0; i
< link
.num_lanes
; i
++) {
1239 unsigned long lane
= SOR_DP_TPG_CHANNEL_CODING
|
1240 SOR_DP_TPG_SCRAMBLER_GALIOS
|
1241 SOR_DP_TPG_PATTERN_NONE
;
1242 value
= (value
<< 8) | lane
;
1245 tegra_sor_writel(sor
, value
, SOR_DP_TPG
);
1247 err
= tegra_sor_dp_train_fast(sor
, &link
);
1249 dev_err(sor
->dev
, "DP fast link training failed: %d\n",
1254 dev_dbg(sor
->dev
, "fast link training succeeded\n");
1257 err
= tegra_sor_power_up(sor
, 250);
1259 dev_err(sor
->dev
, "failed to power up SOR: %d\n", err
);
1264 * configure panel (24bpp, vsync-, hsync-, DP-A protocol, complete
1265 * raster, associate with display controller)
1267 value
= SOR_STATE_ASY_PROTOCOL_DP_A
|
1268 SOR_STATE_ASY_CRC_MODE_COMPLETE
|
1269 SOR_STATE_ASY_OWNER(dc
->pipe
+ 1);
1271 if (mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1272 value
&= ~SOR_STATE_ASY_HSYNCPOL
;
1274 if (mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
1275 value
|= SOR_STATE_ASY_HSYNCPOL
;
1277 if (mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1278 value
&= ~SOR_STATE_ASY_VSYNCPOL
;
1280 if (mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
1281 value
|= SOR_STATE_ASY_VSYNCPOL
;
1283 switch (config
.bits_per_pixel
) {
1285 value
|= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444
;
1289 value
|= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444
;
1297 tegra_sor_writel(sor
, value
, SOR_STATE1
);
1300 * TODO: The video timing programming below doesn't seem to match the
1301 * register definitions.
1304 value
= ((mode
->vtotal
& 0x7fff) << 16) | (mode
->htotal
& 0x7fff);
1305 tegra_sor_writel(sor
, value
, SOR_HEAD_STATE1(0));
1307 vse
= mode
->vsync_end
- mode
->vsync_start
- 1;
1308 hse
= mode
->hsync_end
- mode
->hsync_start
- 1;
1310 value
= ((vse
& 0x7fff) << 16) | (hse
& 0x7fff);
1311 tegra_sor_writel(sor
, value
, SOR_HEAD_STATE2(0));
1313 vbe
= vse
+ (mode
->vsync_start
- mode
->vdisplay
);
1314 hbe
= hse
+ (mode
->hsync_start
- mode
->hdisplay
);
1316 value
= ((vbe
& 0x7fff) << 16) | (hbe
& 0x7fff);
1317 tegra_sor_writel(sor
, value
, SOR_HEAD_STATE3(0));
1319 vbs
= vbe
+ mode
->vdisplay
;
1320 hbs
= hbe
+ mode
->hdisplay
;
1322 value
= ((vbs
& 0x7fff) << 16) | (hbs
& 0x7fff);
1323 tegra_sor_writel(sor
, value
, SOR_HEAD_STATE4(0));
1325 /* CSTM (LVDS, link A/B, upper) */
1326 value
= SOR_CSTM_LVDS
| SOR_CSTM_LINK_ACT_A
| SOR_CSTM_LINK_ACT_B
|
1328 tegra_sor_writel(sor
, value
, SOR_CSTM
);
1331 err
= tegra_sor_setup_pwm(sor
, 250);
1333 dev_err(sor
->dev
, "failed to setup PWM: %d\n", err
);
1337 tegra_sor_update(sor
);
1339 value
= tegra_dc_readl(dc
, DC_DISP_DISP_WIN_OPTIONS
);
1340 value
|= SOR_ENABLE
;
1341 tegra_dc_writel(dc
, value
, DC_DISP_DISP_WIN_OPTIONS
);
1343 tegra_dc_commit(dc
);
1345 err
= tegra_sor_attach(sor
);
1347 dev_err(sor
->dev
, "failed to attach SOR: %d\n", err
);
1351 err
= tegra_sor_wakeup(sor
);
1353 dev_err(sor
->dev
, "failed to enable DC: %d\n", err
);
1358 drm_panel_enable(output
->panel
);
1360 sor
->enabled
= true;
1363 mutex_unlock(&sor
->lock
);
1366 static void tegra_sor_encoder_disable(struct drm_encoder
*encoder
)
1368 struct tegra_output
*output
= encoder_to_output(encoder
);
1369 struct tegra_dc
*dc
= to_tegra_dc(encoder
->crtc
);
1370 struct tegra_sor
*sor
= to_sor(output
);
1374 mutex_lock(&sor
->lock
);
1380 drm_panel_disable(output
->panel
);
1382 err
= tegra_sor_detach(sor
);
1384 dev_err(sor
->dev
, "failed to detach SOR: %d\n", err
);
1388 tegra_sor_writel(sor
, 0, SOR_STATE1
);
1389 tegra_sor_update(sor
);
1392 * The following accesses registers of the display controller, so make
1393 * sure it's only executed when the output is attached to one.
1396 value
= tegra_dc_readl(dc
, DC_DISP_DISP_WIN_OPTIONS
);
1397 value
&= ~SOR_ENABLE
;
1398 tegra_dc_writel(dc
, value
, DC_DISP_DISP_WIN_OPTIONS
);
1400 tegra_dc_commit(dc
);
1403 err
= tegra_sor_power_down(sor
);
1405 dev_err(sor
->dev
, "failed to power down SOR: %d\n", err
);
1410 err
= tegra_dpaux_disable(sor
->dpaux
);
1412 dev_err(sor
->dev
, "failed to disable DP: %d\n", err
);
1417 err
= tegra_io_rail_power_off(TEGRA_IO_RAIL_LVDS
);
1419 dev_err(sor
->dev
, "failed to power off I/O rail: %d\n", err
);
1424 drm_panel_unprepare(output
->panel
);
1426 clk_disable_unprepare(sor
->clk
);
1427 reset_control_assert(sor
->rst
);
1429 sor
->enabled
= false;
1432 mutex_unlock(&sor
->lock
);
1436 tegra_sor_encoder_atomic_check(struct drm_encoder
*encoder
,
1437 struct drm_crtc_state
*crtc_state
,
1438 struct drm_connector_state
*conn_state
)
1440 struct tegra_output
*output
= encoder_to_output(encoder
);
1441 struct tegra_dc
*dc
= to_tegra_dc(conn_state
->crtc
);
1442 unsigned long pclk
= crtc_state
->mode
.clock
* 1000;
1443 struct tegra_sor
*sor
= to_sor(output
);
1446 err
= tegra_dc_state_setup_clock(dc
, crtc_state
, sor
->clk_parent
,
1449 dev_err(output
->dev
, "failed to setup CRTC state: %d\n", err
);
1456 static const struct drm_encoder_helper_funcs tegra_sor_encoder_helper_funcs
= {
1457 .dpms
= tegra_sor_encoder_dpms
,
1458 .prepare
= tegra_sor_encoder_prepare
,
1459 .commit
= tegra_sor_encoder_commit
,
1460 .mode_set
= tegra_sor_encoder_mode_set
,
1461 .disable
= tegra_sor_encoder_disable
,
1462 .atomic_check
= tegra_sor_encoder_atomic_check
,
1465 static int tegra_sor_init(struct host1x_client
*client
)
1467 struct drm_device
*drm
= dev_get_drvdata(client
->parent
);
1468 struct tegra_sor
*sor
= host1x_client_to_sor(client
);
1474 sor
->output
.dev
= sor
->dev
;
1476 drm_connector_init(drm
, &sor
->output
.connector
,
1477 &tegra_sor_connector_funcs
,
1478 DRM_MODE_CONNECTOR_eDP
);
1479 drm_connector_helper_add(&sor
->output
.connector
,
1480 &tegra_sor_connector_helper_funcs
);
1481 sor
->output
.connector
.dpms
= DRM_MODE_DPMS_OFF
;
1483 drm_encoder_init(drm
, &sor
->output
.encoder
, &tegra_sor_encoder_funcs
,
1484 DRM_MODE_ENCODER_TMDS
);
1485 drm_encoder_helper_add(&sor
->output
.encoder
,
1486 &tegra_sor_encoder_helper_funcs
);
1488 drm_mode_connector_attach_encoder(&sor
->output
.connector
,
1489 &sor
->output
.encoder
);
1490 drm_connector_register(&sor
->output
.connector
);
1492 err
= tegra_output_init(drm
, &sor
->output
);
1494 dev_err(client
->dev
, "failed to initialize output: %d\n", err
);
1498 sor
->output
.encoder
.possible_crtcs
= 0x3;
1500 if (IS_ENABLED(CONFIG_DEBUG_FS
)) {
1501 err
= tegra_sor_debugfs_init(sor
, drm
->primary
);
1503 dev_err(sor
->dev
, "debugfs setup failed: %d\n", err
);
1507 err
= tegra_dpaux_attach(sor
->dpaux
, &sor
->output
);
1509 dev_err(sor
->dev
, "failed to attach DP: %d\n", err
);
1515 * XXX: Remove this reset once proper hand-over from firmware to
1516 * kernel is possible.
1518 err
= reset_control_assert(sor
->rst
);
1520 dev_err(sor
->dev
, "failed to assert SOR reset: %d\n", err
);
1524 err
= clk_prepare_enable(sor
->clk
);
1526 dev_err(sor
->dev
, "failed to enable clock: %d\n", err
);
1530 usleep_range(1000, 3000);
1532 err
= reset_control_deassert(sor
->rst
);
1534 dev_err(sor
->dev
, "failed to deassert SOR reset: %d\n", err
);
1538 err
= clk_prepare_enable(sor
->clk_safe
);
1542 err
= clk_prepare_enable(sor
->clk_dp
);
1549 static int tegra_sor_exit(struct host1x_client
*client
)
1551 struct tegra_sor
*sor
= host1x_client_to_sor(client
);
1554 tegra_output_exit(&sor
->output
);
1557 err
= tegra_dpaux_detach(sor
->dpaux
);
1559 dev_err(sor
->dev
, "failed to detach DP: %d\n", err
);
1564 clk_disable_unprepare(sor
->clk_safe
);
1565 clk_disable_unprepare(sor
->clk_dp
);
1566 clk_disable_unprepare(sor
->clk
);
1568 if (IS_ENABLED(CONFIG_DEBUG_FS
))
1569 tegra_sor_debugfs_exit(sor
);
1574 static const struct host1x_client_ops sor_client_ops
= {
1575 .init
= tegra_sor_init
,
1576 .exit
= tegra_sor_exit
,
1579 static int tegra_sor_probe(struct platform_device
*pdev
)
1581 struct device_node
*np
;
1582 struct tegra_sor
*sor
;
1583 struct resource
*regs
;
1586 sor
= devm_kzalloc(&pdev
->dev
, sizeof(*sor
), GFP_KERNEL
);
1590 sor
->output
.dev
= sor
->dev
= &pdev
->dev
;
1592 np
= of_parse_phandle(pdev
->dev
.of_node
, "nvidia,dpaux", 0);
1594 sor
->dpaux
= tegra_dpaux_find_by_of_node(np
);
1598 return -EPROBE_DEFER
;
1601 err
= tegra_output_probe(&sor
->output
);
1605 regs
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1606 sor
->regs
= devm_ioremap_resource(&pdev
->dev
, regs
);
1607 if (IS_ERR(sor
->regs
))
1608 return PTR_ERR(sor
->regs
);
1610 sor
->rst
= devm_reset_control_get(&pdev
->dev
, "sor");
1611 if (IS_ERR(sor
->rst
))
1612 return PTR_ERR(sor
->rst
);
1614 sor
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
1615 if (IS_ERR(sor
->clk
))
1616 return PTR_ERR(sor
->clk
);
1618 sor
->clk_parent
= devm_clk_get(&pdev
->dev
, "parent");
1619 if (IS_ERR(sor
->clk_parent
))
1620 return PTR_ERR(sor
->clk_parent
);
1622 sor
->clk_safe
= devm_clk_get(&pdev
->dev
, "safe");
1623 if (IS_ERR(sor
->clk_safe
))
1624 return PTR_ERR(sor
->clk_safe
);
1626 sor
->clk_dp
= devm_clk_get(&pdev
->dev
, "dp");
1627 if (IS_ERR(sor
->clk_dp
))
1628 return PTR_ERR(sor
->clk_dp
);
1630 INIT_LIST_HEAD(&sor
->client
.list
);
1631 sor
->client
.ops
= &sor_client_ops
;
1632 sor
->client
.dev
= &pdev
->dev
;
1634 mutex_init(&sor
->lock
);
1636 err
= host1x_client_register(&sor
->client
);
1638 dev_err(&pdev
->dev
, "failed to register host1x client: %d\n",
1643 platform_set_drvdata(pdev
, sor
);
1648 static int tegra_sor_remove(struct platform_device
*pdev
)
1650 struct tegra_sor
*sor
= platform_get_drvdata(pdev
);
1653 err
= host1x_client_unregister(&sor
->client
);
1655 dev_err(&pdev
->dev
, "failed to unregister host1x client: %d\n",
1660 tegra_output_remove(&sor
->output
);
1665 static const struct of_device_id tegra_sor_of_match
[] = {
1666 { .compatible
= "nvidia,tegra124-sor", },
1669 MODULE_DEVICE_TABLE(of
, tegra_sor_of_match
);
1671 struct platform_driver tegra_sor_driver
= {
1673 .name
= "tegra-sor",
1674 .of_match_table
= tegra_sor_of_match
,
1676 .probe
= tegra_sor_probe
,
1677 .remove
= tegra_sor_remove
,