drivers/net/dsa/mv88e6131.c

   1 /*
   2  * net/dsa/mv88e6131.c - Marvell 88e6095/6095f/6131 switch chip support
   3  * Copyright (c) 2008-2009 Marvell Semiconductor
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  */
  10
  11 #include <linux/delay.h>
  12 #include <linux/jiffies.h>
  13 #include <linux/list.h>
  14 #include <linux/module.h>
  15 #include <linux/netdevice.h>
  16 #include <linux/phy.h>
  17 #include <net/dsa.h>
  18 #include "mv88e6xxx.h"
  19
  20 /* Switch product IDs */
  21 #define ID_6085         0x04a0
  22 #define ID_6095         0x0950
  23 #define ID_6131         0x1060
  24 #define ID_6131_B2      0x1066
  25
  26 static char *mv88e6131_probe(struct device *host_dev, int sw_addr)
  27 {
  28         struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
  29         int ret;
  30
  31         if (bus == NULL)
  32                 return NULL;
  33
  34         ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), 0x03);
  35         if (ret >= 0) {
  36                 int ret_masked = ret & 0xfff0;
  37
  38                 if (ret_masked == ID_6085)
  39                         return "Marvell 88E6085";
  40                 if (ret_masked == ID_6095)
  41                         return "Marvell 88E6095/88E6095F";
  42                 if (ret == ID_6131_B2)
  43                         return "Marvell 88E6131 (B2)";
  44                 if (ret_masked == ID_6131)
  45                         return "Marvell 88E6131";
  46         }
  47
  48         return NULL;
  49 }
  50
  51 static int mv88e6131_switch_reset(struct dsa_switch *ds)
  52 {
  53         int i;
  54         int ret;
  55         unsigned long timeout;
  56
  57         /* Set all ports to the disabled state. */
  58         for (i = 0; i < 11; i++) {
  59                 ret = REG_READ(REG_PORT(i), 0x04);
  60                 REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
  61         }
  62
  63         /* Wait for transmit queues to drain. */
  64         usleep_range(2000, 4000);
  65
  66         /* Reset the switch. */
  67         REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
  68
  69         /* Wait up to one second for reset to complete. */
  70         timeout = jiffies + 1 * HZ;
  71         while (time_before(jiffies, timeout)) {
  72                 ret = REG_READ(REG_GLOBAL, 0x00);
  73                 if ((ret & 0xc800) == 0xc800)
  74                         break;
  75
  76                 usleep_range(1000, 2000);
  77         }
  78         if (time_after(jiffies, timeout))
  79                 return -ETIMEDOUT;
  80
  81         return 0;
  82 }
  83
  84 static int mv88e6131_setup_global(struct dsa_switch *ds)
  85 {
  86         int ret;
  87         int i;
  88
  89         /* Enable the PHY polling unit, don't discard packets with
  90          * excessive collisions, use a weighted fair queueing scheme
  91          * to arbitrate between packet queues, set the maximum frame
  92          * size to 1632, and mask all interrupt sources.
  93          */
  94         REG_WRITE(REG_GLOBAL, 0x04, 0x4400);
  95
  96         /* Set the default address aging time to 5 minutes, and
  97          * enable address learn messages to be sent to all message
  98          * ports.
  99          */
 100         REG_WRITE(REG_GLOBAL, 0x0a, 0x0148);
 101
 102         /* Configure the priority mapping registers. */
 103         ret = mv88e6xxx_config_prio(ds);
 104         if (ret < 0)
 105                 return ret;
 106
 107         /* Set the VLAN ethertype to 0x8100. */
 108         REG_WRITE(REG_GLOBAL, 0x19, 0x8100);
 109
 110         /* Disable ARP mirroring, and configure the upstream port as
 111          * the port to which ingress and egress monitor frames are to
 112          * be sent.
 113          */
 114         REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1100) | 0x00f0);
 115
 116         /* Disable cascade port functionality unless this device
 117          * is used in a cascade configuration, and set the switch's
 118          * DSA device number.
 119          */
 120         if (ds->dst->pd->nr_chips > 1)
 121                 REG_WRITE(REG_GLOBAL, 0x1c, 0xf000 | (ds->index & 0x1f));
 122         else
 123                 REG_WRITE(REG_GLOBAL, 0x1c, 0xe000 | (ds->index & 0x1f));
 124
 125         /* Send all frames with destination addresses matching
 126          * 01:80:c2:00:00:0x to the CPU port.
 127          */
 128         REG_WRITE(REG_GLOBAL2, 0x03, 0xffff);
 129
 130         /* Ignore removed tag data on doubly tagged packets, disable
 131          * flow control messages, force flow control priority to the
 132          * highest, and send all special multicast frames to the CPU
 133          * port at the highest priority.
 134          */
 135         REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff);
 136
 137         /* Program the DSA routing table. */
 138         for (i = 0; i < 32; i++) {
 139                 int nexthop;
 140
 141                 nexthop = 0x1f;
 142                 if (i != ds->index && i < ds->dst->pd->nr_chips)
 143                         nexthop = ds->pd->rtable[i] & 0x1f;
 144
 145                 REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop);
 146         }
 147
 148         /* Clear all trunk masks. */
 149         for (i = 0; i < 8; i++)
 150                 REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0x7ff);
 151
 152         /* Clear all trunk mappings. */
 153         for (i = 0; i < 16; i++)
 154                 REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11));
 155
 156         /* Force the priority of IGMP/MLD snoop frames and ARP frames
 157          * to the highest setting.
 158          */
 159         REG_WRITE(REG_GLOBAL2, 0x0f, 0x00ff);
 160
 161         return 0;
 162 }
 163
 164 static int mv88e6131_setup_port(struct dsa_switch *ds, int p)
 165 {
 166         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 167         int addr = REG_PORT(p);
 168         u16 val;
 169
 170         /* MAC Forcing register: don't force link, speed, duplex
 171          * or flow control state to any particular values on physical
 172          * ports, but force the CPU port and all DSA ports to 1000 Mb/s
 173          * (100 Mb/s on 6085) full duplex.
 174          */
 175         if (dsa_is_cpu_port(ds, p) || ds->dsa_port_mask & (1 << p))
 176                 if (ps->id == ID_6085)
 177                         REG_WRITE(addr, 0x01, 0x003d); /* 100 Mb/s */
 178                 else
 179                         REG_WRITE(addr, 0x01, 0x003e); /* 1000 Mb/s */
 180         else
 181                 REG_WRITE(addr, 0x01, 0x0003);
 182
 183         /* Port Control: disable Core Tag, disable Drop-on-Lock,
 184          * transmit frames unmodified, disable Header mode,
 185          * enable IGMP/MLD snoop, disable DoubleTag, disable VLAN
 186          * tunneling, determine priority by looking at 802.1p and
 187          * IP priority fields (IP prio has precedence), and set STP
 188          * state to Forwarding.
 189          *
 190          * If this is the upstream port for this switch, enable
 191          * forwarding of unknown unicasts, and enable DSA tagging
 192          * mode.
 193          *
 194          * If this is the link to another switch, use DSA tagging
 195          * mode, but do not enable forwarding of unknown unicasts.
 196          */
 197         val = 0x0433;
 198         if (p == dsa_upstream_port(ds)) {
 199                 val |= 0x0104;
 200                 /* On 6085, unknown multicast forward is controlled
 201                  * here rather than in Port Control 2 register.
 202                  */
 203                 if (ps->id == ID_6085)
 204                         val |= 0x0008;
 205         }
 206         if (ds->dsa_port_mask & (1 << p))
 207                 val |= 0x0100;
 208         REG_WRITE(addr, 0x04, val);
 209
 210         /* Port Control 1: disable trunking.  Also, if this is the
 211          * CPU port, enable learn messages to be sent to this port.
 212          */
 213         REG_WRITE(addr, 0x05, dsa_is_cpu_port(ds, p) ? 0x8000 : 0x0000);
 214
 215         /* Port based VLAN map: give each port its own address
 216          * database, allow the CPU port to talk to each of the 'real'
 217          * ports, and allow each of the 'real' ports to only talk to
 218          * the upstream port.
 219          */
 220         val = (p & 0xf) << 12;
 221         if (dsa_is_cpu_port(ds, p))
 222                 val |= ds->phys_port_mask;
 223         else
 224                 val |= 1 << dsa_upstream_port(ds);
 225         REG_WRITE(addr, 0x06, val);
 226
 227         /* Default VLAN ID and priority: don't set a default VLAN
 228          * ID, and set the default packet priority to zero.
 229          */
 230         REG_WRITE(addr, 0x07, 0x0000);
 231
 232         /* Port Control 2: don't force a good FCS, don't use
 233          * VLAN-based, source address-based or destination
 234          * address-based priority overrides, don't let the switch
 235          * add or strip 802.1q tags, don't discard tagged or
 236          * untagged frames on this port, do a destination address
 237          * lookup on received packets as usual, don't send a copy
 238          * of all transmitted/received frames on this port to the
 239          * CPU, and configure the upstream port number.
 240          *
 241          * If this is the upstream port for this switch, enable
 242          * forwarding of unknown multicast addresses.
 243          */
 244         if (ps->id == ID_6085)
 245                 /* on 6085, bits 3:0 are reserved, bit 6 control ARP
 246                  * mirroring, and multicast forward is handled in
 247                  * Port Control register.
 248                  */
 249                 REG_WRITE(addr, 0x08, 0x0080);
 250         else {
 251                 val = 0x0080 | dsa_upstream_port(ds);
 252                 if (p == dsa_upstream_port(ds))
 253                         val |= 0x0040;
 254                 REG_WRITE(addr, 0x08, val);
 255         }
 256
 257         /* Rate Control: disable ingress rate limiting. */
 258         REG_WRITE(addr, 0x09, 0x0000);
 259
 260         /* Rate Control 2: disable egress rate limiting. */
 261         REG_WRITE(addr, 0x0a, 0x0000);
 262
 263         /* Port Association Vector: when learning source addresses
 264          * of packets, add the address to the address database using
 265          * a port bitmap that has only the bit for this port set and
 266          * the other bits clear.
 267          */
 268         REG_WRITE(addr, 0x0b, 1 << p);
 269
 270         /* Tag Remap: use an identity 802.1p prio -> switch prio
 271          * mapping.
 272          */
 273         REG_WRITE(addr, 0x18, 0x3210);
 274
 275         /* Tag Remap 2: use an identity 802.1p prio -> switch prio
 276          * mapping.
 277          */
 278         REG_WRITE(addr, 0x19, 0x7654);
 279
 280         return 0;
 281 }
 282
 283 static int mv88e6131_setup(struct dsa_switch *ds)
 284 {
 285         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 286         int i;
 287         int ret;
 288
 289         mutex_init(&ps->smi_mutex);
 290         mv88e6xxx_ppu_state_init(ds);
 291         mutex_init(&ps->stats_mutex);
 292
 293         ps->id = REG_READ(REG_PORT(0), 0x03) & 0xfff0;
 294
 295         ret = mv88e6131_switch_reset(ds);
 296         if (ret < 0)
 297                 return ret;
 298
 299         /* @@@ initialise vtu and atu */
 300
 301         ret = mv88e6131_setup_global(ds);
 302         if (ret < 0)
 303                 return ret;
 304
 305         for (i = 0; i < 11; i++) {
 306                 ret = mv88e6131_setup_port(ds, i);
 307                 if (ret < 0)
 308                         return ret;
 309         }
 310
 311         return 0;
 312 }
 313
 314 static int mv88e6131_port_to_phy_addr(int port)
 315 {
 316         if (port >= 0 && port <= 11)
 317                 return port;
 318         return -1;
 319 }
 320
 321 static int
 322 mv88e6131_phy_read(struct dsa_switch *ds, int port, int regnum)
 323 {
 324         int addr = mv88e6131_port_to_phy_addr(port);
 325         return mv88e6xxx_phy_read_ppu(ds, addr, regnum);
 326 }
 327
 328 static int
 329 mv88e6131_phy_write(struct dsa_switch *ds,
 330                               int port, int regnum, u16 val)
 331 {
 332         int addr = mv88e6131_port_to_phy_addr(port);
 333         return mv88e6xxx_phy_write_ppu(ds, addr, regnum, val);
 334 }
 335
 336 static struct mv88e6xxx_hw_stat mv88e6131_hw_stats[] = {
 337         { "in_good_octets", 8, 0x00, },
 338         { "in_bad_octets", 4, 0x02, },
 339         { "in_unicast", 4, 0x04, },
 340         { "in_broadcasts", 4, 0x06, },
 341         { "in_multicasts", 4, 0x07, },
 342         { "in_pause", 4, 0x16, },
 343         { "in_undersize", 4, 0x18, },
 344         { "in_fragments", 4, 0x19, },
 345         { "in_oversize", 4, 0x1a, },
 346         { "in_jabber", 4, 0x1b, },
 347         { "in_rx_error", 4, 0x1c, },
 348         { "in_fcs_error", 4, 0x1d, },
 349         { "out_octets", 8, 0x0e, },
 350         { "out_unicast", 4, 0x10, },
 351         { "out_broadcasts", 4, 0x13, },
 352         { "out_multicasts", 4, 0x12, },
 353         { "out_pause", 4, 0x15, },
 354         { "excessive", 4, 0x11, },
 355         { "collisions", 4, 0x1e, },
 356         { "deferred", 4, 0x05, },
 357         { "single", 4, 0x14, },
 358         { "multiple", 4, 0x17, },
 359         { "out_fcs_error", 4, 0x03, },
 360         { "late", 4, 0x1f, },
 361         { "hist_64bytes", 4, 0x08, },
 362         { "hist_65_127bytes", 4, 0x09, },
 363         { "hist_128_255bytes", 4, 0x0a, },
 364         { "hist_256_511bytes", 4, 0x0b, },
 365         { "hist_512_1023bytes", 4, 0x0c, },
 366         { "hist_1024_max_bytes", 4, 0x0d, },
 367 };
 368
 369 static void
 370 mv88e6131_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
 371 {
 372         mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6131_hw_stats),
 373                               mv88e6131_hw_stats, port, data);
 374 }
 375
 376 static void
 377 mv88e6131_get_ethtool_stats(struct dsa_switch *ds,
 378                                   int port, uint64_t *data)
 379 {
 380         mv88e6xxx_get_ethtool_stats(ds, ARRAY_SIZE(mv88e6131_hw_stats),
 381                                     mv88e6131_hw_stats, port, data);
 382 }
 383
 384 static int mv88e6131_get_sset_count(struct dsa_switch *ds)
 385 {
 386         return ARRAY_SIZE(mv88e6131_hw_stats);
 387 }
 388
 389 struct dsa_switch_driver mv88e6131_switch_driver = {
 390         .tag_protocol           = DSA_TAG_PROTO_DSA,
 391         .priv_size              = sizeof(struct mv88e6xxx_priv_state),
 392         .probe                  = mv88e6131_probe,
 393         .setup                  = mv88e6131_setup,
 394         .set_addr               = mv88e6xxx_set_addr_direct,
 395         .phy_read               = mv88e6131_phy_read,
 396         .phy_write              = mv88e6131_phy_write,
 397         .poll_link              = mv88e6xxx_poll_link,
 398         .get_strings            = mv88e6131_get_strings,
 399         .get_ethtool_stats      = mv88e6131_get_ethtool_stats,
 400         .get_sset_count         = mv88e6131_get_sset_count,
 401 };
 402
 403 MODULE_ALIAS("platform:mv88e6085");
 404 MODULE_ALIAS("platform:mv88e6095");
 405 MODULE_ALIAS("platform:mv88e6095f");
 406 MODULE_ALIAS("platform:mv88e6131");