drivers/net/dsa/mv88e6xxx.c

   1 /*
   2  * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
   3  * Copyright (c) 2008 Marvell Semiconductor
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  */
  10
  11 #include <linux/delay.h>
  12 #include <linux/etherdevice.h>
  13 #include <linux/if_bridge.h>
  14 #include <linux/jiffies.h>
  15 #include <linux/list.h>
  16 #include <linux/module.h>
  17 #include <linux/netdevice.h>
  18 #include <linux/phy.h>
  19 #include <net/dsa.h>
  20 #include "mv88e6xxx.h"
  21
  22 /* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
  23  * use all 32 SMI bus addresses on its SMI bus, and all switch registers
  24  * will be directly accessible on some {device address,register address}
  25  * pair.  If the ADDR[4:0] pins are not strapped to zero, the switch
  26  * will only respond to SMI transactions to that specific address, and
  27  * an indirect addressing mechanism needs to be used to access its
  28  * registers.
  29  */
  30 static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
  31 {
  32         int ret;
  33         int i;
  34
  35         for (i = 0; i < 16; i++) {
  36                 ret = mdiobus_read(bus, sw_addr, 0);
  37                 if (ret < 0)
  38                         return ret;
  39
  40                 if ((ret & 0x8000) == 0)
  41                         return 0;
  42         }
  43
  44         return -ETIMEDOUT;
  45 }
  46
  47 int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg)
  48 {
  49         int ret;
  50
  51         if (sw_addr == 0)
  52                 return mdiobus_read(bus, addr, reg);
  53
  54         /* Wait for the bus to become free. */
  55         ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
  56         if (ret < 0)
  57                 return ret;
  58
  59         /* Transmit the read command. */
  60         ret = mdiobus_write(bus, sw_addr, 0, 0x9800 | (addr << 5) | reg);
  61         if (ret < 0)
  62                 return ret;
  63
  64         /* Wait for the read command to complete. */
  65         ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
  66         if (ret < 0)
  67                 return ret;
  68
  69         /* Read the data. */
  70         ret = mdiobus_read(bus, sw_addr, 1);
  71         if (ret < 0)
  72                 return ret;
  73
  74         return ret & 0xffff;
  75 }
  76
  77 /* Must be called with SMI mutex held */
  78 static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
  79 {
  80         struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
  81         int ret;
  82
  83         if (bus == NULL)
  84                 return -EINVAL;
  85
  86         ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg);
  87         if (ret < 0)
  88                 return ret;
  89
  90         dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
  91                 addr, reg, ret);
  92
  93         return ret;
  94 }
  95
  96 int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
  97 {
  98         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
  99         int ret;
 100
 101         mutex_lock(&ps->smi_mutex);
 102         ret = _mv88e6xxx_reg_read(ds, addr, reg);
 103         mutex_unlock(&ps->smi_mutex);
 104
 105         return ret;
 106 }
 107
 108 int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
 109                           int reg, u16 val)
 110 {
 111         int ret;
 112
 113         if (sw_addr == 0)
 114                 return mdiobus_write(bus, addr, reg, val);
 115
 116         /* Wait for the bus to become free. */
 117         ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
 118         if (ret < 0)
 119                 return ret;
 120
 121         /* Transmit the data to write. */
 122         ret = mdiobus_write(bus, sw_addr, 1, val);
 123         if (ret < 0)
 124                 return ret;
 125
 126         /* Transmit the write command. */
 127         ret = mdiobus_write(bus, sw_addr, 0, 0x9400 | (addr << 5) | reg);
 128         if (ret < 0)
 129                 return ret;
 130
 131         /* Wait for the write command to complete. */
 132         ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
 133         if (ret < 0)
 134                 return ret;
 135
 136         return 0;
 137 }
 138
 139 /* Must be called with SMI mutex held */
 140 static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg,
 141                                 u16 val)
 142 {
 143         struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
 144
 145         if (bus == NULL)
 146                 return -EINVAL;
 147
 148         dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
 149                 addr, reg, val);
 150
 151         return __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val);
 152 }
 153
 154 int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
 155 {
 156         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 157         int ret;
 158
 159         mutex_lock(&ps->smi_mutex);
 160         ret = _mv88e6xxx_reg_write(ds, addr, reg, val);
 161         mutex_unlock(&ps->smi_mutex);
 162
 163         return ret;
 164 }
 165
 166 int mv88e6xxx_config_prio(struct dsa_switch *ds)
 167 {
 168         /* Configure the IP ToS mapping registers. */
 169         REG_WRITE(REG_GLOBAL, 0x10, 0x0000);
 170         REG_WRITE(REG_GLOBAL, 0x11, 0x0000);
 171         REG_WRITE(REG_GLOBAL, 0x12, 0x5555);
 172         REG_WRITE(REG_GLOBAL, 0x13, 0x5555);
 173         REG_WRITE(REG_GLOBAL, 0x14, 0xaaaa);
 174         REG_WRITE(REG_GLOBAL, 0x15, 0xaaaa);
 175         REG_WRITE(REG_GLOBAL, 0x16, 0xffff);
 176         REG_WRITE(REG_GLOBAL, 0x17, 0xffff);
 177
 178         /* Configure the IEEE 802.1p priority mapping register. */
 179         REG_WRITE(REG_GLOBAL, 0x18, 0xfa41);
 180
 181         return 0;
 182 }
 183
 184 int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
 185 {
 186         REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]);
 187         REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]);
 188         REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]);
 189
 190         return 0;
 191 }
 192
 193 int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
 194 {
 195         int i;
 196         int ret;
 197
 198         for (i = 0; i < 6; i++) {
 199                 int j;
 200
 201                 /* Write the MAC address byte. */
 202                 REG_WRITE(REG_GLOBAL2, 0x0d, 0x8000 | (i << 8) | addr[i]);
 203
 204                 /* Wait for the write to complete. */
 205                 for (j = 0; j < 16; j++) {
 206                         ret = REG_READ(REG_GLOBAL2, 0x0d);
 207                         if ((ret & 0x8000) == 0)
 208                                 break;
 209                 }
 210                 if (j == 16)
 211                         return -ETIMEDOUT;
 212         }
 213
 214         return 0;
 215 }
 216
 217 int mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
 218 {
 219         if (addr >= 0)
 220                 return mv88e6xxx_reg_read(ds, addr, regnum);
 221         return 0xffff;
 222 }
 223
 224 int mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum, u16 val)
 225 {
 226         if (addr >= 0)
 227                 return mv88e6xxx_reg_write(ds, addr, regnum, val);
 228         return 0;
 229 }
 230
 231 #ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
 232 static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
 233 {
 234         int ret;
 235         unsigned long timeout;
 236
 237         ret = REG_READ(REG_GLOBAL, 0x04);
 238         REG_WRITE(REG_GLOBAL, 0x04, ret & ~0x4000);
 239
 240         timeout = jiffies + 1 * HZ;
 241         while (time_before(jiffies, timeout)) {
 242                 ret = REG_READ(REG_GLOBAL, 0x00);
 243                 usleep_range(1000, 2000);
 244                 if ((ret & 0xc000) != 0xc000)
 245                         return 0;
 246         }
 247
 248         return -ETIMEDOUT;
 249 }
 250
 251 static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
 252 {
 253         int ret;
 254         unsigned long timeout;
 255
 256         ret = REG_READ(REG_GLOBAL, 0x04);
 257         REG_WRITE(REG_GLOBAL, 0x04, ret | 0x4000);
 258
 259         timeout = jiffies + 1 * HZ;
 260         while (time_before(jiffies, timeout)) {
 261                 ret = REG_READ(REG_GLOBAL, 0x00);
 262                 usleep_range(1000, 2000);
 263                 if ((ret & 0xc000) == 0xc000)
 264                         return 0;
 265         }
 266
 267         return -ETIMEDOUT;
 268 }
 269
 270 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
 271 {
 272         struct mv88e6xxx_priv_state *ps;
 273
 274         ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
 275         if (mutex_trylock(&ps->ppu_mutex)) {
 276                 struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1;
 277
 278                 if (mv88e6xxx_ppu_enable(ds) == 0)
 279                         ps->ppu_disabled = 0;
 280                 mutex_unlock(&ps->ppu_mutex);
 281         }
 282 }
 283
 284 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
 285 {
 286         struct mv88e6xxx_priv_state *ps = (void *)_ps;
 287
 288         schedule_work(&ps->ppu_work);
 289 }
 290
 291 static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds)
 292 {
 293         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 294         int ret;
 295
 296         mutex_lock(&ps->ppu_mutex);
 297
 298         /* If the PHY polling unit is enabled, disable it so that
 299          * we can access the PHY registers.  If it was already
 300          * disabled, cancel the timer that is going to re-enable
 301          * it.
 302          */
 303         if (!ps->ppu_disabled) {
 304                 ret = mv88e6xxx_ppu_disable(ds);
 305                 if (ret < 0) {
 306                         mutex_unlock(&ps->ppu_mutex);
 307                         return ret;
 308                 }
 309                 ps->ppu_disabled = 1;
 310         } else {
 311                 del_timer(&ps->ppu_timer);
 312                 ret = 0;
 313         }
 314
 315         return ret;
 316 }
 317
 318 static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds)
 319 {
 320         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 321
 322         /* Schedule a timer to re-enable the PHY polling unit. */
 323         mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
 324         mutex_unlock(&ps->ppu_mutex);
 325 }
 326
 327 void mv88e6xxx_ppu_state_init(struct dsa_switch *ds)
 328 {
 329         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 330
 331         mutex_init(&ps->ppu_mutex);
 332         INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
 333         init_timer(&ps->ppu_timer);
 334         ps->ppu_timer.data = (unsigned long)ps;
 335         ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
 336 }
 337
 338 int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
 339 {
 340         int ret;
 341
 342         ret = mv88e6xxx_ppu_access_get(ds);
 343         if (ret >= 0) {
 344                 ret = mv88e6xxx_reg_read(ds, addr, regnum);
 345                 mv88e6xxx_ppu_access_put(ds);
 346         }
 347
 348         return ret;
 349 }
 350
 351 int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
 352                             int regnum, u16 val)
 353 {
 354         int ret;
 355
 356         ret = mv88e6xxx_ppu_access_get(ds);
 357         if (ret >= 0) {
 358                 ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
 359                 mv88e6xxx_ppu_access_put(ds);
 360         }
 361
 362         return ret;
 363 }
 364 #endif
 365
 366 void mv88e6xxx_poll_link(struct dsa_switch *ds)
 367 {
 368         int i;
 369
 370         for (i = 0; i < DSA_MAX_PORTS; i++) {
 371                 struct net_device *dev;
 372                 int uninitialized_var(port_status);
 373                 int link;
 374                 int speed;
 375                 int duplex;
 376                 int fc;
 377
 378                 dev = ds->ports[i];
 379                 if (dev == NULL)
 380                         continue;
 381
 382                 link = 0;
 383                 if (dev->flags & IFF_UP) {
 384                         port_status = mv88e6xxx_reg_read(ds, REG_PORT(i), 0x00);
 385                         if (port_status < 0)
 386                                 continue;
 387
 388                         link = !!(port_status & 0x0800);
 389                 }
 390
 391                 if (!link) {
 392                         if (netif_carrier_ok(dev)) {
 393                                 netdev_info(dev, "link down\n");
 394                                 netif_carrier_off(dev);
 395                         }
 396                         continue;
 397                 }
 398
 399                 switch (port_status & 0x0300) {
 400                 case 0x0000:
 401                         speed = 10;
 402                         break;
 403                 case 0x0100:
 404                         speed = 100;
 405                         break;
 406                 case 0x0200:
 407                         speed = 1000;
 408                         break;
 409                 default:
 410                         speed = -1;
 411                         break;
 412                 }
 413                 duplex = (port_status & 0x0400) ? 1 : 0;
 414                 fc = (port_status & 0x8000) ? 1 : 0;
 415
 416                 if (!netif_carrier_ok(dev)) {
 417                         netdev_info(dev,
 418                                     "link up, %d Mb/s, %s duplex, flow control %sabled\n",
 419                                     speed,
 420                                     duplex ? "full" : "half",
 421                                     fc ? "en" : "dis");
 422                         netif_carrier_on(dev);
 423                 }
 424         }
 425 }
 426
 427 static int mv88e6xxx_stats_wait(struct dsa_switch *ds)
 428 {
 429         int ret;
 430         int i;
 431
 432         for (i = 0; i < 10; i++) {
 433                 ret = REG_READ(REG_GLOBAL, 0x1d);
 434                 if ((ret & 0x8000) == 0)
 435                         return 0;
 436         }
 437
 438         return -ETIMEDOUT;
 439 }
 440
 441 static int mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
 442 {
 443         int ret;
 444
 445         /* Snapshot the hardware statistics counters for this port. */
 446         REG_WRITE(REG_GLOBAL, 0x1d, 0xdc00 | port);
 447
 448         /* Wait for the snapshotting to complete. */
 449         ret = mv88e6xxx_stats_wait(ds);
 450         if (ret < 0)
 451                 return ret;
 452
 453         return 0;
 454 }
 455
 456 static void mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val)
 457 {
 458         u32 _val;
 459         int ret;
 460
 461         *val = 0;
 462
 463         ret = mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x1d, 0xcc00 | stat);
 464         if (ret < 0)
 465                 return;
 466
 467         ret = mv88e6xxx_stats_wait(ds);
 468         if (ret < 0)
 469                 return;
 470
 471         ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, 0x1e);
 472         if (ret < 0)
 473                 return;
 474
 475         _val = ret << 16;
 476
 477         ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, 0x1f);
 478         if (ret < 0)
 479                 return;
 480
 481         *val = _val | ret;
 482 }
 483
 484 void mv88e6xxx_get_strings(struct dsa_switch *ds,
 485                            int nr_stats, struct mv88e6xxx_hw_stat *stats,
 486                            int port, uint8_t *data)
 487 {
 488         int i;
 489
 490         for (i = 0; i < nr_stats; i++) {
 491                 memcpy(data + i * ETH_GSTRING_LEN,
 492                        stats[i].string, ETH_GSTRING_LEN);
 493         }
 494 }
 495
 496 void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
 497                                  int nr_stats, struct mv88e6xxx_hw_stat *stats,
 498                                  int port, uint64_t *data)
 499 {
 500         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 501         int ret;
 502         int i;
 503
 504         mutex_lock(&ps->stats_mutex);
 505
 506         ret = mv88e6xxx_stats_snapshot(ds, port);
 507         if (ret < 0) {
 508                 mutex_unlock(&ps->stats_mutex);
 509                 return;
 510         }
 511
 512         /* Read each of the counters. */
 513         for (i = 0; i < nr_stats; i++) {
 514                 struct mv88e6xxx_hw_stat *s = stats + i;
 515                 u32 low;
 516                 u32 high = 0;
 517
 518                 if (s->reg >= 0x100) {
 519                         int ret;
 520
 521                         ret = mv88e6xxx_reg_read(ds, REG_PORT(port),
 522                                                  s->reg - 0x100);
 523                         if (ret < 0)
 524                                 goto error;
 525                         low = ret;
 526                         if (s->sizeof_stat == 4) {
 527                                 ret = mv88e6xxx_reg_read(ds, REG_PORT(port),
 528                                                          s->reg - 0x100 + 1);
 529                                 if (ret < 0)
 530                                         goto error;
 531                                 high = ret;
 532                         }
 533                         data[i] = (((u64)high) << 16) | low;
 534                         continue;
 535                 }
 536                 mv88e6xxx_stats_read(ds, s->reg, &low);
 537                 if (s->sizeof_stat == 8)
 538                         mv88e6xxx_stats_read(ds, s->reg + 1, &high);
 539
 540                 data[i] = (((u64)high) << 32) | low;
 541         }
 542 error:
 543         mutex_unlock(&ps->stats_mutex);
 544 }
 545
 546 int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
 547 {
 548         return 32 * sizeof(u16);
 549 }
 550
 551 void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
 552                         struct ethtool_regs *regs, void *_p)
 553 {
 554         u16 *p = _p;
 555         int i;
 556
 557         regs->version = 0;
 558
 559         memset(p, 0xff, 32 * sizeof(u16));
 560
 561         for (i = 0; i < 32; i++) {
 562                 int ret;
 563
 564                 ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i);
 565                 if (ret >= 0)
 566                         p[i] = ret;
 567         }
 568 }
 569
 570 #ifdef CONFIG_NET_DSA_HWMON
 571
 572 int  mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
 573 {
 574         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 575         int ret;
 576         int val;
 577
 578         *temp = 0;
 579
 580         mutex_lock(&ps->phy_mutex);
 581
 582         ret = mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6);
 583         if (ret < 0)
 584                 goto error;
 585
 586         /* Enable temperature sensor */
 587         ret = mv88e6xxx_phy_read(ds, 0x0, 0x1a);
 588         if (ret < 0)
 589                 goto error;
 590
 591         ret = mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5));
 592         if (ret < 0)
 593                 goto error;
 594
 595         /* Wait for temperature to stabilize */
 596         usleep_range(10000, 12000);
 597
 598         val = mv88e6xxx_phy_read(ds, 0x0, 0x1a);
 599         if (val < 0) {
 600                 ret = val;
 601                 goto error;
 602         }
 603
 604         /* Disable temperature sensor */
 605         ret = mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5));
 606         if (ret < 0)
 607                 goto error;
 608
 609         *temp = ((val & 0x1f) - 5) * 5;
 610
 611 error:
 612         mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0);
 613         mutex_unlock(&ps->phy_mutex);
 614         return ret;
 615 }
 616 #endif /* CONFIG_NET_DSA_HWMON */
 617
 618 static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
 619 {
 620         unsigned long timeout = jiffies + HZ / 10;
 621
 622         while (time_before(jiffies, timeout)) {
 623                 int ret;
 624
 625                 ret = REG_READ(reg, offset);
 626                 if (!(ret & mask))
 627                         return 0;
 628
 629                 usleep_range(1000, 2000);
 630         }
 631         return -ETIMEDOUT;
 632 }
 633
 634 int mv88e6xxx_phy_wait(struct dsa_switch *ds)
 635 {
 636         return mv88e6xxx_wait(ds, REG_GLOBAL2, 0x18, 0x8000);
 637 }
 638
 639 int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
 640 {
 641         return mv88e6xxx_wait(ds, REG_GLOBAL2, 0x14, 0x0800);
 642 }
 643
 644 int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
 645 {
 646         return mv88e6xxx_wait(ds, REG_GLOBAL2, 0x14, 0x8000);
 647 }
 648
 649 /* Must be called with SMI lock held */
 650 static int _mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
 651 {
 652         unsigned long timeout = jiffies + HZ / 10;
 653
 654         while (time_before(jiffies, timeout)) {
 655                 int ret;
 656
 657                 ret = _mv88e6xxx_reg_read(ds, reg, offset);
 658                 if (ret < 0)
 659                         return ret;
 660                 if (!(ret & mask))
 661                         return 0;
 662
 663                 usleep_range(1000, 2000);
 664         }
 665         return -ETIMEDOUT;
 666 }
 667
 668 /* Must be called with SMI lock held */
 669 static int _mv88e6xxx_atu_wait(struct dsa_switch *ds)
 670 {
 671         return _mv88e6xxx_wait(ds, REG_GLOBAL, 0x0b, ATU_BUSY);
 672 }
 673
 674 int mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr, int regnum)
 675 {
 676         int ret;
 677
 678         REG_WRITE(REG_GLOBAL2, 0x18, 0x9800 | (addr << 5) | regnum);
 679
 680         ret = mv88e6xxx_phy_wait(ds);
 681         if (ret < 0)
 682                 return ret;
 683
 684         return REG_READ(REG_GLOBAL2, 0x19);
 685 }
 686
 687 int mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr, int regnum,
 688                                  u16 val)
 689 {
 690         REG_WRITE(REG_GLOBAL2, 0x19, val);
 691         REG_WRITE(REG_GLOBAL2, 0x18, 0x9400 | (addr << 5) | regnum);
 692
 693         return mv88e6xxx_phy_wait(ds);
 694 }
 695
 696 int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
 697 {
 698         int reg;
 699
 700         reg = mv88e6xxx_phy_read_indirect(ds, port, 16);
 701         if (reg < 0)
 702                 return -EOPNOTSUPP;
 703
 704         e->eee_enabled = !!(reg & 0x0200);
 705         e->tx_lpi_enabled = !!(reg & 0x0100);
 706
 707         reg = REG_READ(REG_PORT(port), 0);
 708         e->eee_active = !!(reg & 0x0040);
 709
 710         return 0;
 711 }
 712
 713 static int mv88e6xxx_eee_enable_set(struct dsa_switch *ds, int port,
 714                                     bool eee_enabled, bool tx_lpi_enabled)
 715 {
 716         int reg, nreg;
 717
 718         reg = mv88e6xxx_phy_read_indirect(ds, port, 16);
 719         if (reg < 0)
 720                 return reg;
 721
 722         nreg = reg & ~0x0300;
 723         if (eee_enabled)
 724                 nreg |= 0x0200;
 725         if (tx_lpi_enabled)
 726                 nreg |= 0x0100;
 727
 728         if (nreg != reg)
 729                 return mv88e6xxx_phy_write_indirect(ds, port, 16, nreg);
 730
 731         return 0;
 732 }
 733
 734 int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
 735                       struct phy_device *phydev, struct ethtool_eee *e)
 736 {
 737         int ret;
 738
 739         ret = mv88e6xxx_eee_enable_set(ds, port, e->eee_enabled,
 740                                        e->tx_lpi_enabled);
 741         if (ret)
 742                 return -EOPNOTSUPP;
 743
 744         return 0;
 745 }
 746
 747 static int _mv88e6xxx_atu_cmd(struct dsa_switch *ds, int fid, u16 cmd)
 748 {
 749         int ret;
 750
 751         ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x01, fid);
 752         if (ret < 0)
 753                 return ret;
 754
 755         ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x0b, cmd);
 756         if (ret < 0)
 757                 return ret;
 758
 759         return _mv88e6xxx_atu_wait(ds);
 760 }
 761
 762 static int _mv88e6xxx_flush_fid(struct dsa_switch *ds, int fid)
 763 {
 764         int ret;
 765
 766         ret = _mv88e6xxx_atu_wait(ds);
 767         if (ret < 0)
 768                 return ret;
 769
 770         return _mv88e6xxx_atu_cmd(ds, fid, ATU_CMD_FLUSH_NONSTATIC_FID);
 771 }
 772
 773 static int mv88e6xxx_set_port_state(struct dsa_switch *ds, int port, u8 state)
 774 {
 775         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 776         int reg, ret;
 777         u8 oldstate;
 778
 779         mutex_lock(&ps->smi_mutex);
 780
 781         reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), 0x04);
 782         if (reg < 0)
 783                 goto abort;
 784
 785         oldstate = reg & PSTATE_MASK;
 786         if (oldstate != state) {
 787                 /* Flush forwarding database if we're moving a port
 788                  * from Learning or Forwarding state to Disabled or
 789                  * Blocking or Listening state.
 790                  */
 791                 if (oldstate >= PSTATE_LEARNING && state <= PSTATE_BLOCKING) {
 792                         ret = _mv88e6xxx_flush_fid(ds, ps->fid[port]);
 793                         if (ret)
 794                                 goto abort;
 795                 }
 796                 reg = (reg & ~PSTATE_MASK) | state;
 797                 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), 0x04, reg);
 798         }
 799
 800 abort:
 801         mutex_unlock(&ps->smi_mutex);
 802         return ret;
 803 }
 804
 805 /* Must be called with smi lock held */
 806 static int _mv88e6xxx_update_port_config(struct dsa_switch *ds, int port)
 807 {
 808         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 809         u8 fid = ps->fid[port];
 810         u16 reg = fid << 12;
 811
 812         if (dsa_is_cpu_port(ds, port))
 813                 reg |= ds->phys_port_mask;
 814         else
 815                 reg |= (ps->bridge_mask[fid] |
 816                        (1 << dsa_upstream_port(ds))) & ~(1 << port);
 817
 818         return _mv88e6xxx_reg_write(ds, REG_PORT(port), 0x06, reg);
 819 }
 820
 821 /* Must be called with smi lock held */
 822 static int _mv88e6xxx_update_bridge_config(struct dsa_switch *ds, int fid)
 823 {
 824         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 825         int port;
 826         u32 mask;
 827         int ret;
 828
 829         mask = ds->phys_port_mask;
 830         while (mask) {
 831                 port = __ffs(mask);
 832                 mask &= ~(1 << port);
 833                 if (ps->fid[port] != fid)
 834                         continue;
 835
 836                 ret = _mv88e6xxx_update_port_config(ds, port);
 837                 if (ret)
 838                         return ret;
 839         }
 840
 841         return _mv88e6xxx_flush_fid(ds, fid);
 842 }
 843
 844 /* Bridge handling functions */
 845
 846 int mv88e6xxx_join_bridge(struct dsa_switch *ds, int port, u32 br_port_mask)
 847 {
 848         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 849         int ret = 0;
 850         u32 nmask;
 851         int fid;
 852
 853         /* If the bridge group is not empty, join that group.
 854          * Otherwise create a new group.
 855          */
 856         fid = ps->fid[port];
 857         nmask = br_port_mask & ~(1 << port);
 858         if (nmask)
 859                 fid = ps->fid[__ffs(nmask)];
 860
 861         nmask = ps->bridge_mask[fid] | (1 << port);
 862         if (nmask != br_port_mask) {
 863                 netdev_err(ds->ports[port],
 864                            "join: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n",
 865                            fid, br_port_mask, nmask);
 866                 return -EINVAL;
 867         }
 868
 869         mutex_lock(&ps->smi_mutex);
 870
 871         ps->bridge_mask[fid] = br_port_mask;
 872
 873         if (fid != ps->fid[port]) {
 874                 ps->fid_mask |= 1 << ps->fid[port];
 875                 ps->fid[port] = fid;
 876                 ret = _mv88e6xxx_update_bridge_config(ds, fid);
 877         }
 878
 879         mutex_unlock(&ps->smi_mutex);
 880
 881         return ret;
 882 }
 883
 884 int mv88e6xxx_leave_bridge(struct dsa_switch *ds, int port, u32 br_port_mask)
 885 {
 886         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 887         u8 fid, newfid;
 888         int ret;
 889
 890         fid = ps->fid[port];
 891
 892         if (ps->bridge_mask[fid] != br_port_mask) {
 893                 netdev_err(ds->ports[port],
 894                            "leave: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n",
 895                            fid, br_port_mask, ps->bridge_mask[fid]);
 896                 return -EINVAL;
 897         }
 898
 899         /* If the port was the last port of a bridge, we are done.
 900          * Otherwise assign a new fid to the port, and fix up
 901          * the bridge configuration.
 902          */
 903         if (br_port_mask == (1 << port))
 904                 return 0;
 905
 906         mutex_lock(&ps->smi_mutex);
 907
 908         newfid = __ffs(ps->fid_mask);
 909         ps->fid[port] = newfid;
 910         ps->fid_mask &= (1 << newfid);
 911         ps->bridge_mask[fid] &= ~(1 << port);
 912         ps->bridge_mask[newfid] = 1 << port;
 913
 914         ret = _mv88e6xxx_update_bridge_config(ds, fid);
 915         if (!ret)
 916                 ret = _mv88e6xxx_update_bridge_config(ds, newfid);
 917
 918         mutex_unlock(&ps->smi_mutex);
 919
 920         return ret;
 921 }
 922
 923 int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state)
 924 {
 925         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 926         int stp_state;
 927
 928         switch (state) {
 929         case BR_STATE_DISABLED:
 930                 stp_state = PSTATE_DISABLED;
 931                 break;
 932         case BR_STATE_BLOCKING:
 933         case BR_STATE_LISTENING:
 934                 stp_state = PSTATE_BLOCKING;
 935                 break;
 936         case BR_STATE_LEARNING:
 937                 stp_state = PSTATE_LEARNING;
 938                 break;
 939         case BR_STATE_FORWARDING:
 940         default:
 941                 stp_state = PSTATE_FORWARDING;
 942                 break;
 943         }
 944
 945         netdev_dbg(ds->ports[port], "port state %d [%d]\n", state, stp_state);
 946
 947         /* mv88e6xxx_port_stp_update may be called with softirqs disabled,
 948          * so we can not update the port state directly but need to schedule it.
 949          */
 950         ps->port_state[port] = stp_state;
 951         set_bit(port, &ps->port_state_update_mask);
 952         schedule_work(&ps->bridge_work);
 953
 954         return 0;
 955 }
 956
 957 static int __mv88e6xxx_write_addr(struct dsa_switch *ds,
 958                                   const unsigned char *addr)
 959 {
 960         int i, ret;
 961
 962         for (i = 0; i < 3; i++) {
 963                 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x0d + i,
 964                                         (addr[i * 2] << 8) | addr[i * 2 + 1]);
 965                 if (ret < 0)
 966                         return ret;
 967         }
 968
 969         return 0;
 970 }
 971
 972 static int __mv88e6xxx_read_addr(struct dsa_switch *ds, unsigned char *addr)
 973 {
 974         int i, ret;
 975
 976         for (i = 0; i < 3; i++) {
 977                 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, 0x0d + i);
 978                 if (ret < 0)
 979                         return ret;
 980                 addr[i * 2] = ret >> 8;
 981                 addr[i * 2 + 1] = ret & 0xff;
 982         }
 983
 984         return 0;
 985 }
 986
 987 static int __mv88e6xxx_port_fdb_cmd(struct dsa_switch *ds, int port,
 988                                     const unsigned char *addr, int state)
 989 {
 990         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 991         u8 fid = ps->fid[port];
 992         int ret;
 993
 994         ret = _mv88e6xxx_atu_wait(ds);
 995         if (ret < 0)
 996                 return ret;
 997
 998         ret = __mv88e6xxx_write_addr(ds, addr);
 999         if (ret < 0)
1000                 return ret;
1001
1002         ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x0c,
1003                                    (0x10 << port) | state);
1004         if (ret)
1005                 return ret;
1006
1007         ret = _mv88e6xxx_atu_cmd(ds, fid, ATU_CMD_LOAD_FID);
1008
1009         return ret;
1010 }
1011
1012 int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1013                            const unsigned char *addr, u16 vid)
1014 {
1015         int state = is_multicast_ether_addr(addr) ?
1016                                         FDB_STATE_MC_STATIC : FDB_STATE_STATIC;
1017         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1018         int ret;
1019
1020         mutex_lock(&ps->smi_mutex);
1021         ret = __mv88e6xxx_port_fdb_cmd(ds, port, addr, state);
1022         mutex_unlock(&ps->smi_mutex);
1023
1024         return ret;
1025 }
1026
1027 int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1028                            const unsigned char *addr, u16 vid)
1029 {
1030         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1031         int ret;
1032
1033         mutex_lock(&ps->smi_mutex);
1034         ret = __mv88e6xxx_port_fdb_cmd(ds, port, addr, FDB_STATE_UNUSED);
1035         mutex_unlock(&ps->smi_mutex);
1036
1037         return ret;
1038 }
1039
1040 static int __mv88e6xxx_port_getnext(struct dsa_switch *ds, int port,
1041                                     unsigned char *addr, bool *is_static)
1042 {
1043         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1044         u8 fid = ps->fid[port];
1045         int ret, state;
1046
1047         ret = _mv88e6xxx_atu_wait(ds);
1048         if (ret < 0)
1049                 return ret;
1050
1051         ret = __mv88e6xxx_write_addr(ds, addr);
1052         if (ret < 0)
1053                 return ret;
1054
1055         do {
1056                 ret = _mv88e6xxx_atu_cmd(ds, fid, ATU_CMD_GETNEXT_FID);
1057                 if (ret < 0)
1058                         return ret;
1059
1060                 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, 0x0c);
1061                 if (ret < 0)
1062                         return ret;
1063                 state = ret & FDB_STATE_MASK;
1064                 if (state == FDB_STATE_UNUSED)
1065                         return -ENOENT;
1066         } while (!(((ret >> 4) & 0xff) & (1 << port)));
1067
1068         ret = __mv88e6xxx_read_addr(ds, addr);
1069         if (ret < 0)
1070                 return ret;
1071
1072         *is_static = state == (is_multicast_ether_addr(addr) ?
1073                                FDB_STATE_MC_STATIC : FDB_STATE_STATIC);
1074
1075         return 0;
1076 }
1077
1078 /* get next entry for port */
1079 int mv88e6xxx_port_fdb_getnext(struct dsa_switch *ds, int port,
1080                                unsigned char *addr, bool *is_static)
1081 {
1082         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1083         int ret;
1084
1085         mutex_lock(&ps->smi_mutex);
1086         ret = __mv88e6xxx_port_getnext(ds, port, addr, is_static);
1087         mutex_unlock(&ps->smi_mutex);
1088
1089         return ret;
1090 }
1091
1092 static void mv88e6xxx_bridge_work(struct work_struct *work)
1093 {
1094         struct mv88e6xxx_priv_state *ps;
1095         struct dsa_switch *ds;
1096         int port;
1097
1098         ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work);
1099         ds = ((struct dsa_switch *)ps) - 1;
1100
1101         while (ps->port_state_update_mask) {
1102                 port = __ffs(ps->port_state_update_mask);
1103                 clear_bit(port, &ps->port_state_update_mask);
1104                 mv88e6xxx_set_port_state(ds, port, ps->port_state[port]);
1105         }
1106 }
1107
1108 int mv88e6xxx_setup_port_common(struct dsa_switch *ds, int port)
1109 {
1110         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1111         int ret, fid;
1112
1113         mutex_lock(&ps->smi_mutex);
1114
1115         /* Port Control 1: disable trunking, disable sending
1116          * learning messages to this port.
1117          */
1118         ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), 0x05, 0x0000);
1119         if (ret)
1120                 goto abort;
1121
1122         /* Port based VLAN map: give each port its own address
1123          * database, allow the CPU port to talk to each of the 'real'
1124          * ports, and allow each of the 'real' ports to only talk to
1125          * the upstream port.
1126          */
1127         fid = __ffs(ps->fid_mask);
1128         ps->fid[port] = fid;
1129         ps->fid_mask &= ~(1 << fid);
1130
1131         if (!dsa_is_cpu_port(ds, port))
1132                 ps->bridge_mask[fid] = 1 << port;
1133
1134         ret = _mv88e6xxx_update_port_config(ds, port);
1135         if (ret)
1136                 goto abort;
1137
1138         /* Default VLAN ID and priority: don't set a default VLAN
1139          * ID, and set the default packet priority to zero.
1140          */
1141         ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), 0x07, 0x0000);
1142 abort:
1143         mutex_unlock(&ps->smi_mutex);
1144         return ret;
1145 }
1146
1147 int mv88e6xxx_setup_common(struct dsa_switch *ds)
1148 {
1149         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1150
1151         mutex_init(&ps->smi_mutex);
1152         mutex_init(&ps->stats_mutex);
1153         mutex_init(&ps->phy_mutex);
1154
1155         ps->id = REG_READ(REG_PORT(0), 0x03) & 0xfff0;
1156
1157         ps->fid_mask = (1 << DSA_MAX_PORTS) - 1;
1158
1159         INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work);
1160
1161         return 0;
1162 }
1163
1164 static int __init mv88e6xxx_init(void)
1165 {
1166 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
1167         register_switch_driver(&mv88e6131_switch_driver);
1168 #endif
1169 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
1170         register_switch_driver(&mv88e6123_61_65_switch_driver);
1171 #endif
1172 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
1173         register_switch_driver(&mv88e6352_switch_driver);
1174 #endif
1175 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
1176         register_switch_driver(&mv88e6171_switch_driver);
1177 #endif
1178         return 0;
1179 }
1180 module_init(mv88e6xxx_init);
1181
1182 static void __exit mv88e6xxx_cleanup(void)
1183 {
1184 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
1185         unregister_switch_driver(&mv88e6171_switch_driver);
1186 #endif
1187 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
1188         unregister_switch_driver(&mv88e6123_61_65_switch_driver);
1189 #endif
1190 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
1191         unregister_switch_driver(&mv88e6131_switch_driver);
1192 #endif
1193 }
1194 module_exit(mv88e6xxx_cleanup);
1195
1196 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
1197 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
1198 MODULE_LICENSE("GPL");