?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
btrfs: add comments to barriers before waitqueue_active
[linux-2.6/btrfs-unstable.git] / drivers / irqchip / irq-renesas-intc-irqpin.c
blob9525335723f68f7e4c408d81a6538dc8e72a2b5f
1 /*
2 * Renesas INTC External IRQ Pin Driver
3 *
4 * Copyright (C) 2013 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/clk.h>
21 #include <linux/init.h>
22 #include <linux/of.h>
23 #include <linux/platform_device.h>
24 #include <linux/spinlock.h>
25 #include <linux/interrupt.h>
26 #include <linux/ioport.h>
27 #include <linux/io.h>
28 #include <linux/irq.h>
29 #include <linux/irqdomain.h>
30 #include <linux/err.h>
31 #include <linux/slab.h>
32 #include <linux/module.h>
33 #include <linux/of_device.h>
34 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
35 #include <linux/pm_runtime.h>
36
37 #define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */
38
39 #define INTC_IRQPIN_REG_SENSE 0 /* ICRn */
40 #define INTC_IRQPIN_REG_PRIO 1 /* INTPRInn */
41 #define INTC_IRQPIN_REG_SOURCE 2 /* INTREQnn */
42 #define INTC_IRQPIN_REG_MASK 3 /* INTMSKnn */
43 #define INTC_IRQPIN_REG_CLEAR 4 /* INTMSKCLRnn */
44 #define INTC_IRQPIN_REG_NR_MANDATORY 5
45 #define INTC_IRQPIN_REG_IRLM 5 /* ICR0 with IRLM bit (optional) */
46 #define INTC_IRQPIN_REG_NR 6
47
48 /* INTC external IRQ PIN hardware register access:
49 *
50 * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)
51 * PRIO is read-write 32-bit with 4-bits per IRQ (**)
52 * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)
53 * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
54 * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
55 *
56 * (*) May be accessed by more than one driver instance - lock needed
57 * (**) Read-modify-write access by one driver instance - lock needed
58 * (***) Accessed by one driver instance only - no locking needed
59 */
60
61 struct intc_irqpin_iomem {
62 void __iomem *iomem;
63 unsigned long (*read)(void __iomem *iomem);
64 void (*write)(void __iomem *iomem, unsigned long data);
65 int width;
66 };
67
68 struct intc_irqpin_irq {
69 int hw_irq;
70 int requested_irq;
71 int domain_irq;
72 struct intc_irqpin_priv *p;
73 };
74
75 struct intc_irqpin_priv {
76 struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
77 struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
78 struct renesas_intc_irqpin_config config;
79 unsigned int number_of_irqs;
80 struct platform_device *pdev;
81 struct irq_chip irq_chip;
82 struct irq_domain *irq_domain;
83 struct clk *clk;
84 bool shared_irqs;
85 u8 shared_irq_mask;
86 };
87
88 struct intc_irqpin_irlm_config {
89 unsigned int irlm_bit;
90 };
91
92 static unsigned long intc_irqpin_read32(void __iomem *iomem)
93 {
94 return ioread32(iomem);
95 }
96
97 static unsigned long intc_irqpin_read8(void __iomem *iomem)
98 {
99 return ioread8(iomem);
100 }
101
102 static void intc_irqpin_write32(void __iomem *iomem, unsigned long data)
103 {
104 iowrite32(data, iomem);
105 }
106
107 static void intc_irqpin_write8(void __iomem *iomem, unsigned long data)
108 {
109 iowrite8(data, iomem);
110 }
111
112 static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p,
113 int reg)
114 {
115 struct intc_irqpin_iomem *i = &p->iomem[reg];
116
117 return i->read(i->iomem);
118 }
119
120 static inline void intc_irqpin_write(struct intc_irqpin_priv *p,
121 int reg, unsigned long data)
122 {
123 struct intc_irqpin_iomem *i = &p->iomem[reg];
124
125 i->write(i->iomem, data);
126 }
127
128 static inline unsigned long intc_irqpin_hwirq_mask(struct intc_irqpin_priv *p,
129 int reg, int hw_irq)
130 {
131 return BIT((p->iomem[reg].width - 1) - hw_irq);
132 }
133
134 static inline void intc_irqpin_irq_write_hwirq(struct intc_irqpin_priv *p,
135 int reg, int hw_irq)
136 {
137 intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq));
138 }
139
140 static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */
141
142 static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p,
143 int reg, int shift,
144 int width, int value)
145 {
146 unsigned long flags;
147 unsigned long tmp;
148
149 raw_spin_lock_irqsave(&intc_irqpin_lock, flags);
150
151 tmp = intc_irqpin_read(p, reg);
152 tmp &= ~(((1 << width) - 1) << shift);
153 tmp |= value << shift;
154 intc_irqpin_write(p, reg, tmp);
155
156 raw_spin_unlock_irqrestore(&intc_irqpin_lock, flags);
157 }
158
159 static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
160 int irq, int do_mask)
161 {
162 /* The PRIO register is assumed to be 32-bit with fixed 4-bit fields. */
163 int bitfield_width = 4;
164 int shift = 32 - (irq + 1) * bitfield_width;
165
166 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO,
167 shift, bitfield_width,
168 do_mask ? 0 : (1 << bitfield_width) - 1);
169 }
170
171 static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
172 {
173 /* The SENSE register is assumed to be 32-bit. */
174 int bitfield_width = p->config.sense_bitfield_width;
175 int shift = 32 - (irq + 1) * bitfield_width;
176
177 dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);
178
179 if (value >= (1 << bitfield_width))
180 return -EINVAL;
181
182 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_SENSE, shift,
183 bitfield_width, value);
184 return 0;
185 }
186
187 static void intc_irqpin_dbg(struct intc_irqpin_irq *i, char *str)
188 {
189 dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
190 str, i->requested_irq, i->hw_irq, i->domain_irq);
191 }
192
193 static void intc_irqpin_irq_enable(struct irq_data *d)
194 {
195 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
196 int hw_irq = irqd_to_hwirq(d);
197
198 intc_irqpin_dbg(&p->irq[hw_irq], "enable");
199 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
200 }
201
202 static void intc_irqpin_irq_disable(struct irq_data *d)
203 {
204 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
205 int hw_irq = irqd_to_hwirq(d);
206
207 intc_irqpin_dbg(&p->irq[hw_irq], "disable");
208 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
209 }
210
211 static void intc_irqpin_shared_irq_enable(struct irq_data *d)
212 {
213 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
214 int hw_irq = irqd_to_hwirq(d);
215
216 intc_irqpin_dbg(&p->irq[hw_irq], "shared enable");
217 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
218
219 p->shared_irq_mask &= ~BIT(hw_irq);
220 }
221
222 static void intc_irqpin_shared_irq_disable(struct irq_data *d)
223 {
224 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
225 int hw_irq = irqd_to_hwirq(d);
226
227 intc_irqpin_dbg(&p->irq[hw_irq], "shared disable");
228 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
229
230 p->shared_irq_mask |= BIT(hw_irq);
231 }
232
233 static void intc_irqpin_irq_enable_force(struct irq_data *d)
234 {
235 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
236 int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
237
238 intc_irqpin_irq_enable(d);
239
240 /* enable interrupt through parent interrupt controller,
241 * assumes non-shared interrupt with 1:1 mapping
242 * needed for busted IRQs on some SoCs like sh73a0
243 */
244 irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq));
245 }
246
247 static void intc_irqpin_irq_disable_force(struct irq_data *d)
248 {
249 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
250 int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
251
252 /* disable interrupt through parent interrupt controller,
253 * assumes non-shared interrupt with 1:1 mapping
254 * needed for busted IRQs on some SoCs like sh73a0
255 */
256 irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq));
257 intc_irqpin_irq_disable(d);
258 }
259
260 #define INTC_IRQ_SENSE_VALID 0x10
261 #define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID)
262
263 static unsigned char intc_irqpin_sense[IRQ_TYPE_SENSE_MASK + 1] = {
264 [IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x00),
265 [IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x01),
266 [IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x02),
267 [IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x03),
268 [IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x04),
269 };
270
271 static int intc_irqpin_irq_set_type(struct irq_data *d, unsigned int type)
272 {
273 unsigned char value = intc_irqpin_sense[type & IRQ_TYPE_SENSE_MASK];
274 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
275
276 if (!(value & INTC_IRQ_SENSE_VALID))
277 return -EINVAL;
278
279 return intc_irqpin_set_sense(p, irqd_to_hwirq(d),
280 value ^ INTC_IRQ_SENSE_VALID);
281 }
282
283 static int intc_irqpin_irq_set_wake(struct irq_data *d, unsigned int on)
284 {
285 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
286 int hw_irq = irqd_to_hwirq(d);
287
288 irq_set_irq_wake(p->irq[hw_irq].requested_irq, on);
289
290 if (!p->clk)
291 return 0;
292
293 if (on)
294 clk_enable(p->clk);
295 else
296 clk_disable(p->clk);
297
298 return 0;
299 }
300
301 static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id)
302 {
303 struct intc_irqpin_irq *i = dev_id;
304 struct intc_irqpin_priv *p = i->p;
305 unsigned long bit;
306
307 intc_irqpin_dbg(i, "demux1");
308 bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq);
309
310 if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) {
311 intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit);
312 intc_irqpin_dbg(i, "demux2");
313 generic_handle_irq(i->domain_irq);
314 return IRQ_HANDLED;
315 }
316 return IRQ_NONE;
317 }
318
319 static irqreturn_t intc_irqpin_shared_irq_handler(int irq, void *dev_id)
320 {
321 struct intc_irqpin_priv *p = dev_id;
322 unsigned int reg_source = intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE);
323 irqreturn_t status = IRQ_NONE;
324 int k;
325
326 for (k = 0; k < 8; k++) {
327 if (reg_source & BIT(7 - k)) {
328 if (BIT(k) & p->shared_irq_mask)
329 continue;
330
331 status |= intc_irqpin_irq_handler(irq, &p->irq[k]);
332 }
333 }
334
335 return status;
336 }
337
338 /*
339 * This lock class tells lockdep that INTC External IRQ Pin irqs are in a
340 * different category than their parents, so it won't report false recursion.
341 */
342 static struct lock_class_key intc_irqpin_irq_lock_class;
343
344 static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq,
345 irq_hw_number_t hw)
346 {
347 struct intc_irqpin_priv *p = h->host_data;
348
349 p->irq[hw].domain_irq = virq;
350 p->irq[hw].hw_irq = hw;
351
352 intc_irqpin_dbg(&p->irq[hw], "map");
353 irq_set_chip_data(virq, h->host_data);
354 irq_set_lockdep_class(virq, &intc_irqpin_irq_lock_class);
355 irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
356 return 0;
357 }
358
359 static const struct irq_domain_ops intc_irqpin_irq_domain_ops = {
360 .map = intc_irqpin_irq_domain_map,
361 .xlate = irq_domain_xlate_twocell,
362 };
363
364 static const struct intc_irqpin_irlm_config intc_irqpin_irlm_r8a7779 = {
365 .irlm_bit = 23, /* ICR0.IRLM0 */
366 };
367
368 static const struct of_device_id intc_irqpin_dt_ids[] = {
369 { .compatible = "renesas,intc-irqpin", },
370 { .compatible = "renesas,intc-irqpin-r8a7779",
371 .data = &intc_irqpin_irlm_r8a7779 },
372 {},
373 };
374 MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids);
375
376 static int intc_irqpin_probe(struct platform_device *pdev)
377 {
378 struct device *dev = &pdev->dev;
379 struct renesas_intc_irqpin_config *pdata = dev->platform_data;
380 const struct of_device_id *of_id;
381 struct intc_irqpin_priv *p;
382 struct intc_irqpin_iomem *i;
383 struct resource *io[INTC_IRQPIN_REG_NR];
384 struct resource *irq;
385 struct irq_chip *irq_chip;
386 void (*enable_fn)(struct irq_data *d);
387 void (*disable_fn)(struct irq_data *d);
388 const char *name = dev_name(dev);
389 int ref_irq;
390 int ret;
391 int k;
392
393 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
394 if (!p) {
395 dev_err(dev, "failed to allocate driver data\n");
396 return -ENOMEM;
397 }
398
399 /* deal with driver instance configuration */
400 if (pdata) {
401 memcpy(&p->config, pdata, sizeof(*pdata));
402 } else {
403 of_property_read_u32(dev->of_node, "sense-bitfield-width",
404 &p->config.sense_bitfield_width);
405 p->config.control_parent = of_property_read_bool(dev->of_node,
406 "control-parent");
407 }
408 if (!p->config.sense_bitfield_width)
409 p->config.sense_bitfield_width = 4; /* default to 4 bits */
410
411 p->pdev = pdev;
412 platform_set_drvdata(pdev, p);
413
414 p->clk = devm_clk_get(dev, NULL);
415 if (IS_ERR(p->clk)) {
416 dev_warn(dev, "unable to get clock\n");
417 p->clk = NULL;
418 }
419
420 pm_runtime_enable(dev);
421 pm_runtime_get_sync(dev);
422
423 /* get hold of register banks */
424 memset(io, 0, sizeof(io));
425 for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
426 io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k);
427 if (!io[k] && k < INTC_IRQPIN_REG_NR_MANDATORY) {
428 dev_err(dev, "not enough IOMEM resources\n");
429 ret = -EINVAL;
430 goto err0;
431 }
432 }
433
434 /* allow any number of IRQs between 1 and INTC_IRQPIN_MAX */
435 for (k = 0; k < INTC_IRQPIN_MAX; k++) {
436 irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
437 if (!irq)
438 break;
439
440 p->irq[k].p = p;
441 p->irq[k].requested_irq = irq->start;
442 }
443
444 p->number_of_irqs = k;
445 if (p->number_of_irqs < 1) {
446 dev_err(dev, "not enough IRQ resources\n");
447 ret = -EINVAL;
448 goto err0;
449 }
450
451 /* ioremap IOMEM and setup read/write callbacks */
452 for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
453 i = &p->iomem[k];
454
455 /* handle optional registers */
456 if (!io[k])
457 continue;
458
459 switch (resource_size(io[k])) {
460 case 1:
461 i->width = 8;
462 i->read = intc_irqpin_read8;
463 i->write = intc_irqpin_write8;
464 break;
465 case 4:
466 i->width = 32;
467 i->read = intc_irqpin_read32;
468 i->write = intc_irqpin_write32;
469 break;
470 default:
471 dev_err(dev, "IOMEM size mismatch\n");
472 ret = -EINVAL;
473 goto err0;
474 }
475
476 i->iomem = devm_ioremap_nocache(dev, io[k]->start,
477 resource_size(io[k]));
478 if (!i->iomem) {
479 dev_err(dev, "failed to remap IOMEM\n");
480 ret = -ENXIO;
481 goto err0;
482 }
483 }
484
485 /* configure "individual IRQ mode" where needed */
486 of_id = of_match_device(intc_irqpin_dt_ids, dev);
487 if (of_id && of_id->data) {
488 const struct intc_irqpin_irlm_config *irlm_config = of_id->data;
489
490 if (io[INTC_IRQPIN_REG_IRLM])
491 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_IRLM,
492 irlm_config->irlm_bit,
493 1, 1);
494 else
495 dev_warn(dev, "unable to select IRLM mode\n");
496 }
497
498 /* mask all interrupts using priority */
499 for (k = 0; k < p->number_of_irqs; k++)
500 intc_irqpin_mask_unmask_prio(p, k, 1);
501
502 /* clear all pending interrupts */
503 intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, 0x0);
504
505 /* scan for shared interrupt lines */
506 ref_irq = p->irq[0].requested_irq;
507 p->shared_irqs = true;
508 for (k = 1; k < p->number_of_irqs; k++) {
509 if (ref_irq != p->irq[k].requested_irq) {
510 p->shared_irqs = false;
511 break;
512 }
513 }
514
515 /* use more severe masking method if requested */
516 if (p->config.control_parent) {
517 enable_fn = intc_irqpin_irq_enable_force;
518 disable_fn = intc_irqpin_irq_disable_force;
519 } else if (!p->shared_irqs) {
520 enable_fn = intc_irqpin_irq_enable;
521 disable_fn = intc_irqpin_irq_disable;
522 } else {
523 enable_fn = intc_irqpin_shared_irq_enable;
524 disable_fn = intc_irqpin_shared_irq_disable;
525 }
526
527 irq_chip = &p->irq_chip;
528 irq_chip->name = name;
529 irq_chip->irq_mask = disable_fn;
530 irq_chip->irq_unmask = enable_fn;
531 irq_chip->irq_set_type = intc_irqpin_irq_set_type;
532 irq_chip->irq_set_wake = intc_irqpin_irq_set_wake;
533 irq_chip->flags = IRQCHIP_MASK_ON_SUSPEND;
534
535 p->irq_domain = irq_domain_add_simple(dev->of_node,
536 p->number_of_irqs,
537 p->config.irq_base,
538 &intc_irqpin_irq_domain_ops, p);
539 if (!p->irq_domain) {
540 ret = -ENXIO;
541 dev_err(dev, "cannot initialize irq domain\n");
542 goto err0;
543 }
544
545 if (p->shared_irqs) {
546 /* request one shared interrupt */
547 if (devm_request_irq(dev, p->irq[0].requested_irq,
548 intc_irqpin_shared_irq_handler,
549 IRQF_SHARED, name, p)) {
550 dev_err(dev, "failed to request low IRQ\n");
551 ret = -ENOENT;
552 goto err1;
553 }
554 } else {
555 /* request interrupts one by one */
556 for (k = 0; k < p->number_of_irqs; k++) {
557 if (devm_request_irq(dev, p->irq[k].requested_irq,
558 intc_irqpin_irq_handler, 0, name,
559 &p->irq[k])) {
560 dev_err(dev, "failed to request low IRQ\n");
561 ret = -ENOENT;
562 goto err1;
563 }
564 }
565 }
566
567 /* unmask all interrupts on prio level */
568 for (k = 0; k < p->number_of_irqs; k++)
569 intc_irqpin_mask_unmask_prio(p, k, 0);
570
571 dev_info(dev, "driving %d irqs\n", p->number_of_irqs);
572
573 /* warn in case of mismatch if irq base is specified */
574 if (p->config.irq_base) {
575 if (p->config.irq_base != p->irq[0].domain_irq)
576 dev_warn(dev, "irq base mismatch (%d/%d)\n",
577 p->config.irq_base, p->irq[0].domain_irq);
578 }
579
580 return 0;
581
582 err1:
583 irq_domain_remove(p->irq_domain);
584 err0:
585 pm_runtime_put(dev);
586 pm_runtime_disable(dev);
587 return ret;
588 }
589
590 static int intc_irqpin_remove(struct platform_device *pdev)
591 {
592 struct intc_irqpin_priv *p = platform_get_drvdata(pdev);
593
594 irq_domain_remove(p->irq_domain);
595 pm_runtime_put(&pdev->dev);
596 pm_runtime_disable(&pdev->dev);
597 return 0;
598 }
599
600 static struct platform_driver intc_irqpin_device_driver = {
601 .probe = intc_irqpin_probe,
602 .remove = intc_irqpin_remove,
603 .driver = {
604 .name = "renesas_intc_irqpin",
605 .of_match_table = intc_irqpin_dt_ids,
606 }
607 };
608
609 static int __init intc_irqpin_init(void)
610 {
611 return platform_driver_register(&intc_irqpin_device_driver);
612 }
613 postcore_initcall(intc_irqpin_init);
614
615 static void __exit intc_irqpin_exit(void)
616 {
617 platform_driver_unregister(&intc_irqpin_device_driver);
618 }
619 module_exit(intc_irqpin_exit);
620
621 MODULE_AUTHOR("Magnus Damm");
622 MODULE_DESCRIPTION("Renesas INTC External IRQ Pin Driver");
623 MODULE_LICENSE("GPL v2");
(deprecated) Btrfs devel tree