2 * T4240RDB Device Tree Source
4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
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35 /include/ "t4240si-pre.dtsi"
38 model = "fsl,T4240RDB";
39 compatible = "fsl,T4240RDB";
42 interrupt-parent = <&mpic>;
45 sgmii_phy21 = &sgmiiphy21;
46 sgmii_phy22 = &sgmiiphy22;
47 sgmii_phy23 = &sgmiiphy23;
48 sgmii_phy24 = &sgmiiphy24;
49 sgmii_phy41 = &sgmiiphy41;
50 sgmii_phy42 = &sgmiiphy42;
51 sgmii_phy43 = &sgmiiphy43;
52 sgmii_phy44 = &sgmiiphy44;
55 ifc: localbus@ffe124000 {
56 reg = <0xf 0xfe124000 0 0x2000>;
57 ranges = <0 0 0xf 0xe8000000 0x08000000
58 2 0 0xf 0xff800000 0x00010000
59 3 0 0xf 0xffdf0000 0x00008000>;
64 compatible = "cfi-flash";
65 reg = <0x0 0x0 0x8000000>;
74 compatible = "fsl,ifc-nand";
75 reg = <0x2 0x0 0x10000>;
80 device_type = "memory";
88 bman_fbpr: bman-fbpr {
90 alignment = <0 0x1000000>;
94 alignment = <0 0x400000>;
96 qman_pfdr: qman-pfdr {
98 alignment = <0 0x2000000>;
102 dcsr: dcsr@f00000000 {
103 ranges = <0x00000000 0xf 0x00000000 0x01072000>;
106 bportals: bman-portals@ff4000000 {
107 ranges = <0x0 0xf 0xf4000000 0x2000000>;
110 qportals: qman-portals@ff6000000 {
111 ranges = <0x0 0xf 0xf6000000 0x2000000>;
115 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
116 reg = <0xf 0xfe000000 0 0x00001000>;
119 #address-cells = <1>;
121 compatible = "sst,sst25wf040", "jedec,spi-nor";
123 spi-max-frequency = <40000000>; /* input clock */
129 compatible = "at24,24c256";
133 compatible = "at24,24c256";
137 compatible = "at24,24c256";
141 compatible = "dallas,ds1374";
143 interrupts = <0x1 0x1 0 0>;
148 voltage-ranges = <1800 1800 3300 3300>;
153 phy-handle = <&sgmiiphy21>;
154 phy-connection-type = "sgmii";
158 phy-handle = <&sgmiiphy22>;
159 phy-connection-type = "sgmii";
163 phy-handle = <&sgmiiphy23>;
164 phy-connection-type = "sgmii";
168 phy-handle = <&sgmiiphy24>;
169 phy-connection-type = "sgmii";
181 phy-handle = <&xfiphy1>;
182 phy-connection-type = "xgmii";
186 phy-handle = <&xfiphy2>;
187 phy-connection-type = "xgmii";
193 phy-handle = <&sgmiiphy41>;
194 phy-connection-type = "sgmii";
198 phy-handle = <&sgmiiphy42>;
199 phy-connection-type = "sgmii";
203 phy-handle = <&sgmiiphy43>;
204 phy-connection-type = "sgmii";
208 phy-handle = <&sgmiiphy44>;
209 phy-connection-type = "sgmii";
221 phy-handle = <&xfiphy3>;
222 phy-connection-type = "xgmii";
226 phy-handle = <&xfiphy4>;
227 phy-connection-type = "xgmii";
231 sgmiiphy21: ethernet-phy@0 {
235 sgmiiphy22: ethernet-phy@1 {
239 sgmiiphy23: ethernet-phy@2 {
243 sgmiiphy24: ethernet-phy@3 {
247 sgmiiphy41: ethernet-phy@4 {
251 sgmiiphy42: ethernet-phy@5 {
255 sgmiiphy43: ethernet-phy@6 {
259 sgmiiphy44: ethernet-phy@7 {
265 xfiphy1: ethernet-phy@10 {
266 compatible = "ethernet-phy-ieee802.3-c45";
270 xfiphy2: ethernet-phy@11 {
271 compatible = "ethernet-phy-ieee802.3-c45";
275 xfiphy3: ethernet-phy@13 {
276 compatible = "ethernet-phy-ieee802.3-c45";
280 xfiphy4: ethernet-phy@12 {
281 compatible = "ethernet-phy-ieee802.3-c45";
288 pci0: pcie@ffe240000 {
289 reg = <0xf 0xfe240000 0 0x10000>;
290 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
291 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
293 ranges = <0x02000000 0 0xe0000000
294 0x02000000 0 0xe0000000
297 0x01000000 0 0x00000000
298 0x01000000 0 0x00000000
303 pci1: pcie@ffe250000 {
304 reg = <0xf 0xfe250000 0 0x10000>;
305 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
306 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
308 ranges = <0x02000000 0 0xe0000000
309 0x02000000 0 0xe0000000
312 0x01000000 0 0x00000000
313 0x01000000 0 0x00000000
318 pci2: pcie@ffe260000 {
319 reg = <0xf 0xfe260000 0 0x1000>;
320 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
321 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
323 ranges = <0x02000000 0 0xe0000000
324 0x02000000 0 0xe0000000
327 0x01000000 0 0x00000000
328 0x01000000 0 0x00000000
333 pci3: pcie@ffe270000 {
334 reg = <0xf 0xfe270000 0 0x10000>;
335 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
336 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
338 ranges = <0x02000000 0 0xe0000000
339 0x02000000 0 0xe0000000
342 0x01000000 0 0x00000000
343 0x01000000 0 0x00000000
348 rio: rapidio@ffe0c0000 {
349 reg = <0xf 0xfe0c0000 0 0x11000>;
352 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
355 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
360 /include/ "t4240si-post.dtsi"