2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/console.h>
30 #include <drm/drm_crtc_helper.h>
31 #include <drm/radeon_drm.h>
32 #include "radeon_reg.h"
34 #include "radeon_asic.h"
38 * Clear GPU surface registers.
40 void radeon_surface_init(struct radeon_device
*rdev
)
42 /* FIXME: check this out */
43 if (rdev
->family
< CHIP_R600
) {
46 for (i
= 0; i
< 8; i
++) {
47 WREG32(RADEON_SURFACE0_INFO
+
48 i
* (RADEON_SURFACE1_INFO
- RADEON_SURFACE0_INFO
),
52 WREG32(RADEON_SURFACE_CNTL
, 0);
57 * GPU scratch registers helpers function.
59 void radeon_scratch_init(struct radeon_device
*rdev
)
63 /* FIXME: check this out */
64 if (rdev
->family
< CHIP_R300
) {
65 rdev
->scratch
.num_reg
= 5;
67 rdev
->scratch
.num_reg
= 7;
69 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
70 rdev
->scratch
.free
[i
] = true;
71 rdev
->scratch
.reg
[i
] = RADEON_SCRATCH_REG0
+ (i
* 4);
75 int radeon_scratch_get(struct radeon_device
*rdev
, uint32_t *reg
)
79 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
80 if (rdev
->scratch
.free
[i
]) {
81 rdev
->scratch
.free
[i
] = false;
82 *reg
= rdev
->scratch
.reg
[i
];
89 void radeon_scratch_free(struct radeon_device
*rdev
, uint32_t reg
)
93 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
94 if (rdev
->scratch
.reg
[i
] == reg
) {
95 rdev
->scratch
.free
[i
] = true;
102 * MC common functions
104 int radeon_mc_setup(struct radeon_device
*rdev
)
108 /* Some chips have an "issue" with the memory controller, the
109 * location must be aligned to the size. We just align it down,
110 * too bad if we walk over the top of system memory, we don't
111 * use DMA without a remapped anyway.
112 * Affected chips are rv280, all r3xx, and all r4xx, but not IGP
114 /* FGLRX seems to setup like this, VRAM a 0, then GART.
117 * Note: from R6xx the address space is 40bits but here we only
118 * use 32bits (still have to see a card which would exhaust 4G
121 if (rdev
->mc
.vram_location
!= 0xFFFFFFFFUL
) {
122 /* vram location was already setup try to put gtt after
124 tmp
= rdev
->mc
.vram_location
+ rdev
->mc
.mc_vram_size
;
125 tmp
= (tmp
+ rdev
->mc
.gtt_size
- 1) & ~(rdev
->mc
.gtt_size
- 1);
126 if ((0xFFFFFFFFUL
- tmp
) >= rdev
->mc
.gtt_size
) {
127 rdev
->mc
.gtt_location
= tmp
;
129 if (rdev
->mc
.gtt_size
>= rdev
->mc
.vram_location
) {
130 printk(KERN_ERR
"[drm] GTT too big to fit "
131 "before or after vram location.\n");
134 rdev
->mc
.gtt_location
= 0;
136 } else if (rdev
->mc
.gtt_location
!= 0xFFFFFFFFUL
) {
137 /* gtt location was already setup try to put vram before
139 if (rdev
->mc
.mc_vram_size
< rdev
->mc
.gtt_location
) {
140 rdev
->mc
.vram_location
= 0;
142 tmp
= rdev
->mc
.gtt_location
+ rdev
->mc
.gtt_size
;
143 tmp
+= (rdev
->mc
.mc_vram_size
- 1);
144 tmp
&= ~(rdev
->mc
.mc_vram_size
- 1);
145 if ((0xFFFFFFFFUL
- tmp
) >= rdev
->mc
.mc_vram_size
) {
146 rdev
->mc
.vram_location
= tmp
;
148 printk(KERN_ERR
"[drm] vram too big to fit "
149 "before or after GTT location.\n");
154 rdev
->mc
.vram_location
= 0;
155 tmp
= rdev
->mc
.mc_vram_size
;
156 tmp
= (tmp
+ rdev
->mc
.gtt_size
- 1) & ~(rdev
->mc
.gtt_size
- 1);
157 rdev
->mc
.gtt_location
= tmp
;
159 rdev
->mc
.vram_start
= rdev
->mc
.vram_location
;
160 rdev
->mc
.vram_end
= rdev
->mc
.vram_location
+ rdev
->mc
.mc_vram_size
- 1;
161 rdev
->mc
.gtt_start
= rdev
->mc
.gtt_location
;
162 rdev
->mc
.gtt_end
= rdev
->mc
.gtt_location
+ rdev
->mc
.gtt_size
- 1;
163 DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev
->mc
.mc_vram_size
>> 20));
164 DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
165 (unsigned)rdev
->mc
.vram_location
,
166 (unsigned)(rdev
->mc
.vram_location
+ rdev
->mc
.mc_vram_size
- 1));
167 DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev
->mc
.gtt_size
>> 20));
168 DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
169 (unsigned)rdev
->mc
.gtt_location
,
170 (unsigned)(rdev
->mc
.gtt_location
+ rdev
->mc
.gtt_size
- 1));
176 * GPU helpers function.
178 bool radeon_card_posted(struct radeon_device
*rdev
)
182 /* first check CRTCs */
183 if (ASIC_IS_AVIVO(rdev
)) {
184 reg
= RREG32(AVIVO_D1CRTC_CONTROL
) |
185 RREG32(AVIVO_D2CRTC_CONTROL
);
186 if (reg
& AVIVO_CRTC_EN
) {
190 reg
= RREG32(RADEON_CRTC_GEN_CNTL
) |
191 RREG32(RADEON_CRTC2_GEN_CNTL
);
192 if (reg
& RADEON_CRTC_EN
) {
197 /* then check MEM_SIZE, in case the crtcs are off */
198 if (rdev
->family
>= CHIP_R600
)
199 reg
= RREG32(R600_CONFIG_MEMSIZE
);
201 reg
= RREG32(RADEON_CONFIG_MEMSIZE
);
210 int radeon_dummy_page_init(struct radeon_device
*rdev
)
212 rdev
->dummy_page
.page
= alloc_page(GFP_DMA32
| GFP_KERNEL
| __GFP_ZERO
);
213 if (rdev
->dummy_page
.page
== NULL
)
215 rdev
->dummy_page
.addr
= pci_map_page(rdev
->pdev
, rdev
->dummy_page
.page
,
216 0, PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
217 if (!rdev
->dummy_page
.addr
) {
218 __free_page(rdev
->dummy_page
.page
);
219 rdev
->dummy_page
.page
= NULL
;
225 void radeon_dummy_page_fini(struct radeon_device
*rdev
)
227 if (rdev
->dummy_page
.page
== NULL
)
229 pci_unmap_page(rdev
->pdev
, rdev
->dummy_page
.addr
,
230 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
231 __free_page(rdev
->dummy_page
.page
);
232 rdev
->dummy_page
.page
= NULL
;
237 * Registers accessors functions.
239 uint32_t radeon_invalid_rreg(struct radeon_device
*rdev
, uint32_t reg
)
241 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg
);
246 void radeon_invalid_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
)
248 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
253 void radeon_register_accessor_init(struct radeon_device
*rdev
)
255 rdev
->mc_rreg
= &radeon_invalid_rreg
;
256 rdev
->mc_wreg
= &radeon_invalid_wreg
;
257 rdev
->pll_rreg
= &radeon_invalid_rreg
;
258 rdev
->pll_wreg
= &radeon_invalid_wreg
;
259 rdev
->pciep_rreg
= &radeon_invalid_rreg
;
260 rdev
->pciep_wreg
= &radeon_invalid_wreg
;
262 /* Don't change order as we are overridding accessor. */
263 if (rdev
->family
< CHIP_RV515
) {
264 rdev
->pcie_reg_mask
= 0xff;
266 rdev
->pcie_reg_mask
= 0x7ff;
268 /* FIXME: not sure here */
269 if (rdev
->family
<= CHIP_R580
) {
270 rdev
->pll_rreg
= &r100_pll_rreg
;
271 rdev
->pll_wreg
= &r100_pll_wreg
;
273 if (rdev
->family
>= CHIP_R420
) {
274 rdev
->mc_rreg
= &r420_mc_rreg
;
275 rdev
->mc_wreg
= &r420_mc_wreg
;
277 if (rdev
->family
>= CHIP_RV515
) {
278 rdev
->mc_rreg
= &rv515_mc_rreg
;
279 rdev
->mc_wreg
= &rv515_mc_wreg
;
281 if (rdev
->family
== CHIP_RS400
|| rdev
->family
== CHIP_RS480
) {
282 rdev
->mc_rreg
= &rs400_mc_rreg
;
283 rdev
->mc_wreg
= &rs400_mc_wreg
;
285 if (rdev
->family
== CHIP_RS690
|| rdev
->family
== CHIP_RS740
) {
286 rdev
->mc_rreg
= &rs690_mc_rreg
;
287 rdev
->mc_wreg
= &rs690_mc_wreg
;
289 if (rdev
->family
== CHIP_RS600
) {
290 rdev
->mc_rreg
= &rs600_mc_rreg
;
291 rdev
->mc_wreg
= &rs600_mc_wreg
;
293 if (rdev
->family
>= CHIP_R600
) {
294 rdev
->pciep_rreg
= &r600_pciep_rreg
;
295 rdev
->pciep_wreg
= &r600_pciep_wreg
;
303 int radeon_asic_init(struct radeon_device
*rdev
)
305 radeon_register_accessor_init(rdev
);
306 switch (rdev
->family
) {
316 rdev
->asic
= &r100_asic
;
322 rdev
->asic
= &r300_asic
;
327 rdev
->asic
= &r420_asic
;
331 rdev
->asic
= &rs400_asic
;
334 rdev
->asic
= &rs600_asic
;
338 rdev
->asic
= &rs690_asic
;
341 rdev
->asic
= &rv515_asic
;
348 rdev
->asic
= &r520_asic
;
358 rdev
->asic
= &r600_asic
;
364 rdev
->asic
= &rv770_asic
;
367 /* FIXME: not supported yet */
375 * Wrapper around modesetting bits.
377 int radeon_clocks_init(struct radeon_device
*rdev
)
381 radeon_get_clock_info(rdev
->ddev
);
382 r
= radeon_static_clocks_init(rdev
->ddev
);
386 DRM_INFO("Clocks initialized !\n");
390 void radeon_clocks_fini(struct radeon_device
*rdev
)
394 /* ATOM accessor methods */
395 static uint32_t cail_pll_read(struct card_info
*info
, uint32_t reg
)
397 struct radeon_device
*rdev
= info
->dev
->dev_private
;
400 r
= rdev
->pll_rreg(rdev
, reg
);
404 static void cail_pll_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
406 struct radeon_device
*rdev
= info
->dev
->dev_private
;
408 rdev
->pll_wreg(rdev
, reg
, val
);
411 static uint32_t cail_mc_read(struct card_info
*info
, uint32_t reg
)
413 struct radeon_device
*rdev
= info
->dev
->dev_private
;
416 r
= rdev
->mc_rreg(rdev
, reg
);
420 static void cail_mc_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
422 struct radeon_device
*rdev
= info
->dev
->dev_private
;
424 rdev
->mc_wreg(rdev
, reg
, val
);
427 static void cail_reg_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
429 struct radeon_device
*rdev
= info
->dev
->dev_private
;
434 static uint32_t cail_reg_read(struct card_info
*info
, uint32_t reg
)
436 struct radeon_device
*rdev
= info
->dev
->dev_private
;
443 static struct card_info atom_card_info
= {
445 .reg_read
= cail_reg_read
,
446 .reg_write
= cail_reg_write
,
447 .mc_read
= cail_mc_read
,
448 .mc_write
= cail_mc_write
,
449 .pll_read
= cail_pll_read
,
450 .pll_write
= cail_pll_write
,
453 int radeon_atombios_init(struct radeon_device
*rdev
)
455 atom_card_info
.dev
= rdev
->ddev
;
456 rdev
->mode_info
.atom_context
= atom_parse(&atom_card_info
, rdev
->bios
);
457 radeon_atom_initialize_bios_scratch_regs(rdev
->ddev
);
461 void radeon_atombios_fini(struct radeon_device
*rdev
)
463 kfree(rdev
->mode_info
.atom_context
);
466 int radeon_combios_init(struct radeon_device
*rdev
)
468 radeon_combios_initialize_bios_scratch_regs(rdev
->ddev
);
472 void radeon_combios_fini(struct radeon_device
*rdev
)
480 int radeon_device_init(struct radeon_device
*rdev
,
481 struct drm_device
*ddev
,
482 struct pci_dev
*pdev
,
488 DRM_INFO("radeon: Initializing kernel modesetting.\n");
489 rdev
->shutdown
= false;
490 rdev
->dev
= &pdev
->dev
;
494 rdev
->family
= flags
& RADEON_FAMILY_MASK
;
495 rdev
->is_atom_bios
= false;
496 rdev
->usec_timeout
= RADEON_MAX_USEC_TIMEOUT
;
497 rdev
->mc
.gtt_size
= radeon_gart_size
* 1024 * 1024;
498 rdev
->gpu_lockup
= false;
499 /* mutex initialization are all done here so we
500 * can recall function without having locking issues */
501 mutex_init(&rdev
->cs_mutex
);
502 mutex_init(&rdev
->ib_pool
.mutex
);
503 mutex_init(&rdev
->cp
.mutex
);
504 rwlock_init(&rdev
->fence_drv
.lock
);
505 INIT_LIST_HEAD(&rdev
->gem
.objects
);
507 if (radeon_agpmode
== -1) {
508 rdev
->flags
&= ~RADEON_IS_AGP
;
509 if (rdev
->family
>= CHIP_RV515
||
510 rdev
->family
== CHIP_RV380
||
511 rdev
->family
== CHIP_RV410
||
512 rdev
->family
== CHIP_R423
) {
513 DRM_INFO("Forcing AGP to PCIE mode\n");
514 rdev
->flags
|= RADEON_IS_PCIE
;
516 DRM_INFO("Forcing AGP to PCI mode\n");
517 rdev
->flags
|= RADEON_IS_PCI
;
521 /* Set asic functions */
522 r
= radeon_asic_init(rdev
);
527 /* set DMA mask + need_dma32 flags.
528 * PCIE - can handle 40-bits.
529 * IGP - can handle 40-bits (in theory)
530 * AGP - generally dma32 is safest
533 rdev
->need_dma32
= false;
534 if (rdev
->flags
& RADEON_IS_AGP
)
535 rdev
->need_dma32
= true;
536 if (rdev
->flags
& RADEON_IS_PCI
)
537 rdev
->need_dma32
= true;
539 dma_bits
= rdev
->need_dma32
? 32 : 40;
540 r
= pci_set_dma_mask(rdev
->pdev
, DMA_BIT_MASK(dma_bits
));
542 printk(KERN_WARNING
"radeon: No suitable DMA available.\n");
545 /* Registers mapping */
546 /* TODO: block userspace mapping of io register */
547 rdev
->rmmio_base
= drm_get_resource_start(rdev
->ddev
, 2);
548 rdev
->rmmio_size
= drm_get_resource_len(rdev
->ddev
, 2);
549 rdev
->rmmio
= ioremap(rdev
->rmmio_base
, rdev
->rmmio_size
);
550 if (rdev
->rmmio
== NULL
) {
553 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev
->rmmio_base
);
554 DRM_INFO("register mmio size: %u\n", (unsigned)rdev
->rmmio_size
);
556 rdev
->new_init_path
= false;
557 r
= radeon_init(rdev
);
561 if (!rdev
->new_init_path
) {
562 /* Setup errata flags */
564 /* Initialize scratch registers */
565 radeon_scratch_init(rdev
);
566 /* Initialize surface registers */
567 radeon_surface_init(rdev
);
569 /* TODO: disable VGA need to use VGA request */
571 if (!radeon_get_bios(rdev
)) {
572 if (ASIC_IS_AVIVO(rdev
))
575 if (rdev
->is_atom_bios
) {
576 r
= radeon_atombios_init(rdev
);
581 r
= radeon_combios_init(rdev
);
586 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
587 if (radeon_gpu_reset(rdev
)) {
588 /* FIXME: what do we want to do here ? */
590 /* check if cards are posted or not */
591 if (!radeon_card_posted(rdev
) && rdev
->bios
) {
592 DRM_INFO("GPU not posted. posting now...\n");
593 if (rdev
->is_atom_bios
) {
594 atom_asic_init(rdev
->mode_info
.atom_context
);
596 radeon_combios_asic_init(rdev
->ddev
);
599 /* Initialize clocks */
600 r
= radeon_clocks_init(rdev
);
604 /* Get vram informations */
605 radeon_vram_info(rdev
);
607 /* Initialize memory controller (also test AGP) */
608 r
= radeon_mc_init(rdev
);
613 r
= radeon_fence_driver_init(rdev
);
617 r
= radeon_irq_kms_init(rdev
);
622 r
= radeon_object_init(rdev
);
626 /* Initialize GART (initialize after TTM so we can allocate
627 * memory through TTM but finalize after TTM) */
628 r
= radeon_gart_enable(rdev
);
630 r
= radeon_gem_init(rdev
);
635 r
= radeon_cp_init(rdev
, 1024 * 1024);
638 r
= radeon_wb_init(rdev
);
640 DRM_ERROR("radeon: failled initializing WB (%d).\n", r
);
645 r
= radeon_ib_pool_init(rdev
);
647 DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r
);
652 r
= radeon_ib_test(rdev
);
654 DRM_ERROR("radeon: failled testing IB (%d).\n", r
);
659 DRM_INFO("radeon: kernel modesetting successfully initialized.\n");
660 if (radeon_testing
) {
661 radeon_test_moves(rdev
);
663 if (radeon_benchmarking
) {
664 radeon_benchmark(rdev
);
669 void radeon_device_fini(struct radeon_device
*rdev
)
671 DRM_INFO("radeon: finishing device.\n");
672 rdev
->shutdown
= true;
673 /* Order matter so becarefull if you rearrange anythings */
674 if (!rdev
->new_init_path
) {
675 radeon_ib_pool_fini(rdev
);
676 radeon_cp_fini(rdev
);
677 radeon_wb_fini(rdev
);
678 radeon_gem_fini(rdev
);
679 radeon_mc_fini(rdev
);
681 radeon_agp_fini(rdev
);
683 radeon_irq_kms_fini(rdev
);
684 radeon_fence_driver_fini(rdev
);
685 radeon_clocks_fini(rdev
);
686 radeon_object_fini(rdev
);
687 if (rdev
->is_atom_bios
) {
688 radeon_atombios_fini(rdev
);
690 radeon_combios_fini(rdev
);
697 iounmap(rdev
->rmmio
);
705 int radeon_suspend_kms(struct drm_device
*dev
, pm_message_t state
)
707 struct radeon_device
*rdev
= dev
->dev_private
;
708 struct drm_crtc
*crtc
;
710 if (dev
== NULL
|| rdev
== NULL
) {
713 if (state
.event
== PM_EVENT_PRETHAW
) {
716 /* unpin the front buffers */
717 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
718 struct radeon_framebuffer
*rfb
= to_radeon_framebuffer(crtc
->fb
);
719 struct radeon_object
*robj
;
721 if (rfb
== NULL
|| rfb
->obj
== NULL
) {
724 robj
= rfb
->obj
->driver_private
;
725 if (robj
!= rdev
->fbdev_robj
) {
726 radeon_object_unpin(robj
);
729 /* evict vram memory */
730 radeon_object_evict_vram(rdev
);
731 /* wait for gpu to finish processing current batch */
732 radeon_fence_wait_last(rdev
);
734 if (!rdev
->new_init_path
) {
735 radeon_cp_disable(rdev
);
736 radeon_gart_disable(rdev
);
737 rdev
->irq
.sw_int
= false;
738 radeon_irq_set(rdev
);
740 radeon_suspend(rdev
);
742 /* evict remaining vram memory */
743 radeon_object_evict_vram(rdev
);
745 pci_save_state(dev
->pdev
);
746 if (state
.event
== PM_EVENT_SUSPEND
) {
747 /* Shut down the device */
748 pci_disable_device(dev
->pdev
);
749 pci_set_power_state(dev
->pdev
, PCI_D3hot
);
751 acquire_console_sem();
752 fb_set_suspend(rdev
->fbdev_info
, 1);
753 release_console_sem();
757 int radeon_resume_kms(struct drm_device
*dev
)
759 struct radeon_device
*rdev
= dev
->dev_private
;
762 acquire_console_sem();
763 pci_set_power_state(dev
->pdev
, PCI_D0
);
764 pci_restore_state(dev
->pdev
);
765 if (pci_enable_device(dev
->pdev
)) {
766 release_console_sem();
769 pci_set_master(dev
->pdev
);
770 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
771 if (!rdev
->new_init_path
) {
772 if (radeon_gpu_reset(rdev
)) {
773 /* FIXME: what do we want to do here ? */
776 if (rdev
->is_atom_bios
) {
777 atom_asic_init(rdev
->mode_info
.atom_context
);
779 radeon_combios_asic_init(rdev
->ddev
);
781 /* Initialize clocks */
782 r
= radeon_clocks_init(rdev
);
784 release_console_sem();
788 rdev
->irq
.sw_int
= true;
789 radeon_irq_set(rdev
);
790 /* Initialize GPU Memory Controller */
791 r
= radeon_mc_init(rdev
);
795 r
= radeon_gart_enable(rdev
);
799 r
= radeon_cp_init(rdev
, rdev
->cp
.ring_size
);
807 fb_set_suspend(rdev
->fbdev_info
, 0);
808 release_console_sem();
810 /* blat the mode back in */
811 drm_helper_resume_force_mode(dev
);
819 struct radeon_debugfs
{
820 struct drm_info_list
*files
;
823 static struct radeon_debugfs _radeon_debugfs
[RADEON_DEBUGFS_MAX_NUM_FILES
];
824 static unsigned _radeon_debugfs_count
= 0;
826 int radeon_debugfs_add_files(struct radeon_device
*rdev
,
827 struct drm_info_list
*files
,
832 for (i
= 0; i
< _radeon_debugfs_count
; i
++) {
833 if (_radeon_debugfs
[i
].files
== files
) {
834 /* Already registered */
838 if ((_radeon_debugfs_count
+ nfiles
) > RADEON_DEBUGFS_MAX_NUM_FILES
) {
839 DRM_ERROR("Reached maximum number of debugfs files.\n");
840 DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
843 _radeon_debugfs
[_radeon_debugfs_count
].files
= files
;
844 _radeon_debugfs
[_radeon_debugfs_count
].num_files
= nfiles
;
845 _radeon_debugfs_count
++;
846 #if defined(CONFIG_DEBUG_FS)
847 drm_debugfs_create_files(files
, nfiles
,
848 rdev
->ddev
->control
->debugfs_root
,
849 rdev
->ddev
->control
);
850 drm_debugfs_create_files(files
, nfiles
,
851 rdev
->ddev
->primary
->debugfs_root
,
852 rdev
->ddev
->primary
);
857 #if defined(CONFIG_DEBUG_FS)
858 int radeon_debugfs_init(struct drm_minor
*minor
)
863 void radeon_debugfs_cleanup(struct drm_minor
*minor
)
867 for (i
= 0; i
< _radeon_debugfs_count
; i
++) {
868 drm_debugfs_remove_files(_radeon_debugfs
[i
].files
,
869 _radeon_debugfs
[i
].num_files
, minor
);