2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/i915_drm.h>
31 #include "i915_trace.h"
32 #include "intel_drv.h"
33 #include <linux/shmem_fs.h>
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/dma-buf.h>
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
41 static __must_check
int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
43 bool map_and_fenceable
,
45 static int i915_gem_phys_pwrite(struct drm_device
*dev
,
46 struct drm_i915_gem_object
*obj
,
47 struct drm_i915_gem_pwrite
*args
,
48 struct drm_file
*file
);
50 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
51 struct drm_i915_gem_object
*obj
);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
53 struct drm_i915_fence_reg
*fence
,
56 static int i915_gem_inactive_shrink(struct shrinker
*shrinker
,
57 struct shrink_control
*sc
);
58 static long i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
);
59 static void i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
60 static void i915_gem_object_truncate(struct drm_i915_gem_object
*obj
);
62 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object
*obj
)
65 i915_gem_release_mmap(obj
);
67 /* As we do not have an associated fence register, we will force
68 * a tiling change if we ever need to acquire one.
70 obj
->fence_dirty
= false;
71 obj
->fence_reg
= I915_FENCE_REG_NONE
;
74 /* some bookkeeping */
75 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
78 dev_priv
->mm
.object_count
++;
79 dev_priv
->mm
.object_memory
+= size
;
82 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
85 dev_priv
->mm
.object_count
--;
86 dev_priv
->mm
.object_memory
-= size
;
90 i915_gem_wait_for_error(struct drm_device
*dev
)
92 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
93 struct completion
*x
= &dev_priv
->error_completion
;
97 if (!atomic_read(&dev_priv
->mm
.wedged
))
101 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
102 * userspace. If it takes that long something really bad is going on and
103 * we should simply try to bail out and fail as gracefully as possible.
105 ret
= wait_for_completion_interruptible_timeout(x
, 10*HZ
);
107 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
109 } else if (ret
< 0) {
113 if (atomic_read(&dev_priv
->mm
.wedged
)) {
114 /* GPU is hung, bump the completion count to account for
115 * the token we just consumed so that we never hit zero and
116 * end up waiting upon a subsequent completion event that
119 spin_lock_irqsave(&x
->wait
.lock
, flags
);
121 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
126 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
130 ret
= i915_gem_wait_for_error(dev
);
134 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
138 WARN_ON(i915_verify_lists(dev
));
143 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj
)
145 return obj
->gtt_space
&& !obj
->active
;
149 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
150 struct drm_file
*file
)
152 struct drm_i915_gem_init
*args
= data
;
154 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
157 if (args
->gtt_start
>= args
->gtt_end
||
158 (args
->gtt_end
| args
->gtt_start
) & (PAGE_SIZE
- 1))
161 /* GEM with user mode setting was never supported on ilk and later. */
162 if (INTEL_INFO(dev
)->gen
>= 5)
165 mutex_lock(&dev
->struct_mutex
);
166 i915_gem_init_global_gtt(dev
, args
->gtt_start
,
167 args
->gtt_end
, args
->gtt_end
);
168 mutex_unlock(&dev
->struct_mutex
);
174 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
175 struct drm_file
*file
)
177 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
178 struct drm_i915_gem_get_aperture
*args
= data
;
179 struct drm_i915_gem_object
*obj
;
183 mutex_lock(&dev
->struct_mutex
);
184 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, gtt_list
)
186 pinned
+= obj
->gtt_space
->size
;
187 mutex_unlock(&dev
->struct_mutex
);
189 args
->aper_size
= dev_priv
->mm
.gtt_total
;
190 args
->aper_available_size
= args
->aper_size
- pinned
;
196 i915_gem_create(struct drm_file
*file
,
197 struct drm_device
*dev
,
201 struct drm_i915_gem_object
*obj
;
205 size
= roundup(size
, PAGE_SIZE
);
209 /* Allocate the new object */
210 obj
= i915_gem_alloc_object(dev
, size
);
214 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
216 drm_gem_object_release(&obj
->base
);
217 i915_gem_info_remove_obj(dev
->dev_private
, obj
->base
.size
);
222 /* drop reference from allocate - handle holds it now */
223 drm_gem_object_unreference(&obj
->base
);
224 trace_i915_gem_object_create(obj
);
231 i915_gem_dumb_create(struct drm_file
*file
,
232 struct drm_device
*dev
,
233 struct drm_mode_create_dumb
*args
)
235 /* have to work out size/pitch and return them */
236 args
->pitch
= ALIGN(args
->width
* ((args
->bpp
+ 7) / 8), 64);
237 args
->size
= args
->pitch
* args
->height
;
238 return i915_gem_create(file
, dev
,
239 args
->size
, &args
->handle
);
242 int i915_gem_dumb_destroy(struct drm_file
*file
,
243 struct drm_device
*dev
,
246 return drm_gem_handle_delete(file
, handle
);
250 * Creates a new mm object and returns a handle to it.
253 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
254 struct drm_file
*file
)
256 struct drm_i915_gem_create
*args
= data
;
258 return i915_gem_create(file
, dev
,
259 args
->size
, &args
->handle
);
262 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
264 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
266 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
267 obj
->tiling_mode
!= I915_TILING_NONE
;
271 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
272 const char *gpu_vaddr
, int gpu_offset
,
275 int ret
, cpu_offset
= 0;
278 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
279 int this_length
= min(cacheline_end
- gpu_offset
, length
);
280 int swizzled_gpu_offset
= gpu_offset
^ 64;
282 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
283 gpu_vaddr
+ swizzled_gpu_offset
,
288 cpu_offset
+= this_length
;
289 gpu_offset
+= this_length
;
290 length
-= this_length
;
297 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
298 const char __user
*cpu_vaddr
,
301 int ret
, cpu_offset
= 0;
304 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
305 int this_length
= min(cacheline_end
- gpu_offset
, length
);
306 int swizzled_gpu_offset
= gpu_offset
^ 64;
308 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
309 cpu_vaddr
+ cpu_offset
,
314 cpu_offset
+= this_length
;
315 gpu_offset
+= this_length
;
316 length
-= this_length
;
322 /* Per-page copy function for the shmem pread fastpath.
323 * Flushes invalid cachelines before reading the target if
324 * needs_clflush is set. */
326 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
327 char __user
*user_data
,
328 bool page_do_bit17_swizzling
, bool needs_clflush
)
333 if (unlikely(page_do_bit17_swizzling
))
336 vaddr
= kmap_atomic(page
);
338 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
340 ret
= __copy_to_user_inatomic(user_data
,
341 vaddr
+ shmem_page_offset
,
343 kunmap_atomic(vaddr
);
345 return ret
? -EFAULT
: 0;
349 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
352 if (unlikely(swizzled
)) {
353 unsigned long start
= (unsigned long) addr
;
354 unsigned long end
= (unsigned long) addr
+ length
;
356 /* For swizzling simply ensure that we always flush both
357 * channels. Lame, but simple and it works. Swizzled
358 * pwrite/pread is far from a hotpath - current userspace
359 * doesn't use it at all. */
360 start
= round_down(start
, 128);
361 end
= round_up(end
, 128);
363 drm_clflush_virt_range((void *)start
, end
- start
);
365 drm_clflush_virt_range(addr
, length
);
370 /* Only difference to the fast-path function is that this can handle bit17
371 * and uses non-atomic copy and kmap functions. */
373 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
374 char __user
*user_data
,
375 bool page_do_bit17_swizzling
, bool needs_clflush
)
382 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
384 page_do_bit17_swizzling
);
386 if (page_do_bit17_swizzling
)
387 ret
= __copy_to_user_swizzled(user_data
,
388 vaddr
, shmem_page_offset
,
391 ret
= __copy_to_user(user_data
,
392 vaddr
+ shmem_page_offset
,
396 return ret
? - EFAULT
: 0;
400 i915_gem_shmem_pread(struct drm_device
*dev
,
401 struct drm_i915_gem_object
*obj
,
402 struct drm_i915_gem_pread
*args
,
403 struct drm_file
*file
)
405 char __user
*user_data
;
408 int shmem_page_offset
, page_length
, ret
= 0;
409 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
411 int needs_clflush
= 0;
412 struct scatterlist
*sg
;
415 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
418 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
420 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
421 /* If we're not in the cpu read domain, set ourself into the gtt
422 * read domain and manually flush cachelines (if required). This
423 * optimizes for the case when the gpu will dirty the data
424 * anyway again before the next pread happens. */
425 if (obj
->cache_level
== I915_CACHE_NONE
)
427 if (obj
->gtt_space
) {
428 ret
= i915_gem_object_set_to_gtt_domain(obj
, false);
434 ret
= i915_gem_object_get_pages(obj
);
438 i915_gem_object_pin_pages(obj
);
440 offset
= args
->offset
;
442 for_each_sg(obj
->pages
->sgl
, sg
, obj
->pages
->nents
, i
) {
445 if (i
< offset
>> PAGE_SHIFT
)
451 /* Operation in this page
453 * shmem_page_offset = offset within page in shmem file
454 * page_length = bytes to copy for this page
456 shmem_page_offset
= offset_in_page(offset
);
457 page_length
= remain
;
458 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
459 page_length
= PAGE_SIZE
- shmem_page_offset
;
462 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
463 (page_to_phys(page
) & (1 << 17)) != 0;
465 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
466 user_data
, page_do_bit17_swizzling
,
471 mutex_unlock(&dev
->struct_mutex
);
474 ret
= fault_in_multipages_writeable(user_data
, remain
);
475 /* Userspace is tricking us, but we've already clobbered
476 * its pages with the prefault and promised to write the
477 * data up to the first fault. Hence ignore any errors
478 * and just continue. */
483 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
484 user_data
, page_do_bit17_swizzling
,
487 mutex_lock(&dev
->struct_mutex
);
490 mark_page_accessed(page
);
495 remain
-= page_length
;
496 user_data
+= page_length
;
497 offset
+= page_length
;
501 i915_gem_object_unpin_pages(obj
);
507 * Reads data from the object referenced by handle.
509 * On error, the contents of *data are undefined.
512 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
513 struct drm_file
*file
)
515 struct drm_i915_gem_pread
*args
= data
;
516 struct drm_i915_gem_object
*obj
;
522 if (!access_ok(VERIFY_WRITE
,
523 (char __user
*)(uintptr_t)args
->data_ptr
,
527 ret
= i915_mutex_lock_interruptible(dev
);
531 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
532 if (&obj
->base
== NULL
) {
537 /* Bounds check source. */
538 if (args
->offset
> obj
->base
.size
||
539 args
->size
> obj
->base
.size
- args
->offset
) {
544 /* prime objects have no backing filp to GEM pread/pwrite
547 if (!obj
->base
.filp
) {
552 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
554 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
557 drm_gem_object_unreference(&obj
->base
);
559 mutex_unlock(&dev
->struct_mutex
);
563 /* This is the fast write path which cannot handle
564 * page faults in the source data
568 fast_user_write(struct io_mapping
*mapping
,
569 loff_t page_base
, int page_offset
,
570 char __user
*user_data
,
573 void __iomem
*vaddr_atomic
;
575 unsigned long unwritten
;
577 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
578 /* We can use the cpu mem copy function because this is X86. */
579 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
580 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
582 io_mapping_unmap_atomic(vaddr_atomic
);
587 * This is the fast pwrite path, where we copy the data directly from the
588 * user into the GTT, uncached.
591 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
592 struct drm_i915_gem_object
*obj
,
593 struct drm_i915_gem_pwrite
*args
,
594 struct drm_file
*file
)
596 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
598 loff_t offset
, page_base
;
599 char __user
*user_data
;
600 int page_offset
, page_length
, ret
;
602 ret
= i915_gem_object_pin(obj
, 0, true, true);
606 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
610 ret
= i915_gem_object_put_fence(obj
);
614 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
617 offset
= obj
->gtt_offset
+ args
->offset
;
620 /* Operation in this page
622 * page_base = page offset within aperture
623 * page_offset = offset within page
624 * page_length = bytes to copy for this page
626 page_base
= offset
& PAGE_MASK
;
627 page_offset
= offset_in_page(offset
);
628 page_length
= remain
;
629 if ((page_offset
+ remain
) > PAGE_SIZE
)
630 page_length
= PAGE_SIZE
- page_offset
;
632 /* If we get a fault while copying data, then (presumably) our
633 * source page isn't available. Return the error and we'll
634 * retry in the slow path.
636 if (fast_user_write(dev_priv
->mm
.gtt_mapping
, page_base
,
637 page_offset
, user_data
, page_length
)) {
642 remain
-= page_length
;
643 user_data
+= page_length
;
644 offset
+= page_length
;
648 i915_gem_object_unpin(obj
);
653 /* Per-page copy function for the shmem pwrite fastpath.
654 * Flushes invalid cachelines before writing to the target if
655 * needs_clflush_before is set and flushes out any written cachelines after
656 * writing if needs_clflush is set. */
658 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
659 char __user
*user_data
,
660 bool page_do_bit17_swizzling
,
661 bool needs_clflush_before
,
662 bool needs_clflush_after
)
667 if (unlikely(page_do_bit17_swizzling
))
670 vaddr
= kmap_atomic(page
);
671 if (needs_clflush_before
)
672 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
674 ret
= __copy_from_user_inatomic_nocache(vaddr
+ shmem_page_offset
,
677 if (needs_clflush_after
)
678 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
680 kunmap_atomic(vaddr
);
682 return ret
? -EFAULT
: 0;
685 /* Only difference to the fast-path function is that this can handle bit17
686 * and uses non-atomic copy and kmap functions. */
688 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
689 char __user
*user_data
,
690 bool page_do_bit17_swizzling
,
691 bool needs_clflush_before
,
692 bool needs_clflush_after
)
698 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
699 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
701 page_do_bit17_swizzling
);
702 if (page_do_bit17_swizzling
)
703 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
707 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
710 if (needs_clflush_after
)
711 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
713 page_do_bit17_swizzling
);
716 return ret
? -EFAULT
: 0;
720 i915_gem_shmem_pwrite(struct drm_device
*dev
,
721 struct drm_i915_gem_object
*obj
,
722 struct drm_i915_gem_pwrite
*args
,
723 struct drm_file
*file
)
727 char __user
*user_data
;
728 int shmem_page_offset
, page_length
, ret
= 0;
729 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
730 int hit_slowpath
= 0;
731 int needs_clflush_after
= 0;
732 int needs_clflush_before
= 0;
734 struct scatterlist
*sg
;
736 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
739 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
741 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
742 /* If we're not in the cpu write domain, set ourself into the gtt
743 * write domain and manually flush cachelines (if required). This
744 * optimizes for the case when the gpu will use the data
745 * right away and we therefore have to clflush anyway. */
746 if (obj
->cache_level
== I915_CACHE_NONE
)
747 needs_clflush_after
= 1;
748 if (obj
->gtt_space
) {
749 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
754 /* Same trick applies for invalidate partially written cachelines before
756 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)
757 && obj
->cache_level
== I915_CACHE_NONE
)
758 needs_clflush_before
= 1;
760 ret
= i915_gem_object_get_pages(obj
);
764 i915_gem_object_pin_pages(obj
);
766 offset
= args
->offset
;
769 for_each_sg(obj
->pages
->sgl
, sg
, obj
->pages
->nents
, i
) {
771 int partial_cacheline_write
;
773 if (i
< offset
>> PAGE_SHIFT
)
779 /* Operation in this page
781 * shmem_page_offset = offset within page in shmem file
782 * page_length = bytes to copy for this page
784 shmem_page_offset
= offset_in_page(offset
);
786 page_length
= remain
;
787 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
788 page_length
= PAGE_SIZE
- shmem_page_offset
;
790 /* If we don't overwrite a cacheline completely we need to be
791 * careful to have up-to-date data by first clflushing. Don't
792 * overcomplicate things and flush the entire patch. */
793 partial_cacheline_write
= needs_clflush_before
&&
794 ((shmem_page_offset
| page_length
)
795 & (boot_cpu_data
.x86_clflush_size
- 1));
798 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
799 (page_to_phys(page
) & (1 << 17)) != 0;
801 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
802 user_data
, page_do_bit17_swizzling
,
803 partial_cacheline_write
,
804 needs_clflush_after
);
809 mutex_unlock(&dev
->struct_mutex
);
810 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
811 user_data
, page_do_bit17_swizzling
,
812 partial_cacheline_write
,
813 needs_clflush_after
);
815 mutex_lock(&dev
->struct_mutex
);
818 set_page_dirty(page
);
819 mark_page_accessed(page
);
824 remain
-= page_length
;
825 user_data
+= page_length
;
826 offset
+= page_length
;
830 i915_gem_object_unpin_pages(obj
);
833 /* Fixup: Flush dirty cachelines in case the object isn't in the
834 * cpu write domain anymore. */
835 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
836 i915_gem_clflush_object(obj
);
837 i915_gem_chipset_flush(dev
);
841 if (needs_clflush_after
)
842 i915_gem_chipset_flush(dev
);
848 * Writes data to the object referenced by handle.
850 * On error, the contents of the buffer that were to be modified are undefined.
853 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
854 struct drm_file
*file
)
856 struct drm_i915_gem_pwrite
*args
= data
;
857 struct drm_i915_gem_object
*obj
;
863 if (!access_ok(VERIFY_READ
,
864 (char __user
*)(uintptr_t)args
->data_ptr
,
868 ret
= fault_in_multipages_readable((char __user
*)(uintptr_t)args
->data_ptr
,
873 ret
= i915_mutex_lock_interruptible(dev
);
877 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
878 if (&obj
->base
== NULL
) {
883 /* Bounds check destination. */
884 if (args
->offset
> obj
->base
.size
||
885 args
->size
> obj
->base
.size
- args
->offset
) {
890 /* prime objects have no backing filp to GEM pread/pwrite
893 if (!obj
->base
.filp
) {
898 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
901 /* We can only do the GTT pwrite on untiled buffers, as otherwise
902 * it would end up going through the fenced access, and we'll get
903 * different detiling behavior between reading and writing.
904 * pread/pwrite currently are reading and writing from the CPU
905 * perspective, requiring manual detiling by the client.
908 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file
);
912 if (obj
->cache_level
== I915_CACHE_NONE
&&
913 obj
->tiling_mode
== I915_TILING_NONE
&&
914 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
915 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
916 /* Note that the gtt paths might fail with non-page-backed user
917 * pointers (e.g. gtt mappings when moving data between
918 * textures). Fallback to the shmem path in that case. */
921 if (ret
== -EFAULT
|| ret
== -ENOSPC
)
922 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
925 drm_gem_object_unreference(&obj
->base
);
927 mutex_unlock(&dev
->struct_mutex
);
932 i915_gem_check_wedge(struct drm_i915_private
*dev_priv
,
935 if (atomic_read(&dev_priv
->mm
.wedged
)) {
936 struct completion
*x
= &dev_priv
->error_completion
;
937 bool recovery_complete
;
940 /* Give the error handler a chance to run. */
941 spin_lock_irqsave(&x
->wait
.lock
, flags
);
942 recovery_complete
= x
->done
> 0;
943 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
945 /* Non-interruptible callers can't handle -EAGAIN, hence return
946 * -EIO unconditionally for these. */
950 /* Recovery complete, but still wedged means reset failure. */
951 if (recovery_complete
)
961 * Compare seqno against outstanding lazy request. Emit a request if they are
965 i915_gem_check_olr(struct intel_ring_buffer
*ring
, u32 seqno
)
969 BUG_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
972 if (seqno
== ring
->outstanding_lazy_request
)
973 ret
= i915_add_request(ring
, NULL
, NULL
);
979 * __wait_seqno - wait until execution of seqno has finished
980 * @ring: the ring expected to report seqno
982 * @interruptible: do an interruptible wait (normally yes)
983 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
985 * Returns 0 if the seqno was found within the alloted time. Else returns the
986 * errno with remaining time filled in timeout argument.
988 static int __wait_seqno(struct intel_ring_buffer
*ring
, u32 seqno
,
989 bool interruptible
, struct timespec
*timeout
)
991 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
992 struct timespec before
, now
, wait_time
={1,0};
993 unsigned long timeout_jiffies
;
995 bool wait_forever
= true;
998 if (i915_seqno_passed(ring
->get_seqno(ring
, true), seqno
))
1001 trace_i915_gem_request_wait_begin(ring
, seqno
);
1003 if (timeout
!= NULL
) {
1004 wait_time
= *timeout
;
1005 wait_forever
= false;
1008 timeout_jiffies
= timespec_to_jiffies(&wait_time
);
1010 if (WARN_ON(!ring
->irq_get(ring
)))
1013 /* Record current time in case interrupted by signal, or wedged * */
1014 getrawmonotonic(&before
);
1017 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1018 atomic_read(&dev_priv->mm.wedged))
1021 end
= wait_event_interruptible_timeout(ring
->irq_queue
,
1025 end
= wait_event_timeout(ring
->irq_queue
, EXIT_COND
,
1028 ret
= i915_gem_check_wedge(dev_priv
, interruptible
);
1031 } while (end
== 0 && wait_forever
);
1033 getrawmonotonic(&now
);
1035 ring
->irq_put(ring
);
1036 trace_i915_gem_request_wait_end(ring
, seqno
);
1040 struct timespec sleep_time
= timespec_sub(now
, before
);
1041 *timeout
= timespec_sub(*timeout
, sleep_time
);
1046 case -EAGAIN
: /* Wedged */
1047 case -ERESTARTSYS
: /* Signal */
1049 case 0: /* Timeout */
1051 set_normalized_timespec(timeout
, 0, 0);
1053 default: /* Completed */
1054 WARN_ON(end
< 0); /* We're not aware of other errors */
1060 * Waits for a sequence number to be signaled, and cleans up the
1061 * request and object lists appropriately for that event.
1064 i915_wait_seqno(struct intel_ring_buffer
*ring
, uint32_t seqno
)
1066 struct drm_device
*dev
= ring
->dev
;
1067 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1068 bool interruptible
= dev_priv
->mm
.interruptible
;
1071 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1074 ret
= i915_gem_check_wedge(dev_priv
, interruptible
);
1078 ret
= i915_gem_check_olr(ring
, seqno
);
1082 return __wait_seqno(ring
, seqno
, interruptible
, NULL
);
1086 * Ensures that all rendering to the object has completed and the object is
1087 * safe to unbind from the GTT or access from the CPU.
1089 static __must_check
int
1090 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1093 struct intel_ring_buffer
*ring
= obj
->ring
;
1097 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1101 ret
= i915_wait_seqno(ring
, seqno
);
1105 i915_gem_retire_requests_ring(ring
);
1107 /* Manually manage the write flush as we may have not yet
1108 * retired the buffer.
1110 if (obj
->last_write_seqno
&&
1111 i915_seqno_passed(seqno
, obj
->last_write_seqno
)) {
1112 obj
->last_write_seqno
= 0;
1113 obj
->base
.write_domain
&= ~I915_GEM_GPU_DOMAINS
;
1119 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1120 * as the object state may change during this call.
1122 static __must_check
int
1123 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1126 struct drm_device
*dev
= obj
->base
.dev
;
1127 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1128 struct intel_ring_buffer
*ring
= obj
->ring
;
1132 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1133 BUG_ON(!dev_priv
->mm
.interruptible
);
1135 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1139 ret
= i915_gem_check_wedge(dev_priv
, true);
1143 ret
= i915_gem_check_olr(ring
, seqno
);
1147 mutex_unlock(&dev
->struct_mutex
);
1148 ret
= __wait_seqno(ring
, seqno
, true, NULL
);
1149 mutex_lock(&dev
->struct_mutex
);
1151 i915_gem_retire_requests_ring(ring
);
1153 /* Manually manage the write flush as we may have not yet
1154 * retired the buffer.
1156 if (obj
->last_write_seqno
&&
1157 i915_seqno_passed(seqno
, obj
->last_write_seqno
)) {
1158 obj
->last_write_seqno
= 0;
1159 obj
->base
.write_domain
&= ~I915_GEM_GPU_DOMAINS
;
1166 * Called when user space prepares to use an object with the CPU, either
1167 * through the mmap ioctl's mapping or a GTT mapping.
1170 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1171 struct drm_file
*file
)
1173 struct drm_i915_gem_set_domain
*args
= data
;
1174 struct drm_i915_gem_object
*obj
;
1175 uint32_t read_domains
= args
->read_domains
;
1176 uint32_t write_domain
= args
->write_domain
;
1179 /* Only handle setting domains to types used by the CPU. */
1180 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1183 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1186 /* Having something in the write domain implies it's in the read
1187 * domain, and only that read domain. Enforce that in the request.
1189 if (write_domain
!= 0 && read_domains
!= write_domain
)
1192 ret
= i915_mutex_lock_interruptible(dev
);
1196 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1197 if (&obj
->base
== NULL
) {
1202 /* Try to flush the object off the GPU without holding the lock.
1203 * We will repeat the flush holding the lock in the normal manner
1204 * to catch cases where we are gazumped.
1206 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, !write_domain
);
1210 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1211 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1213 /* Silently promote "you're not bound, there was nothing to do"
1214 * to success, since the client was just asking us to
1215 * make sure everything was done.
1220 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1224 drm_gem_object_unreference(&obj
->base
);
1226 mutex_unlock(&dev
->struct_mutex
);
1231 * Called when user space has done writes to this buffer
1234 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1235 struct drm_file
*file
)
1237 struct drm_i915_gem_sw_finish
*args
= data
;
1238 struct drm_i915_gem_object
*obj
;
1241 ret
= i915_mutex_lock_interruptible(dev
);
1245 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1246 if (&obj
->base
== NULL
) {
1251 /* Pinned buffers may be scanout, so flush the cache */
1253 i915_gem_object_flush_cpu_write_domain(obj
);
1255 drm_gem_object_unreference(&obj
->base
);
1257 mutex_unlock(&dev
->struct_mutex
);
1262 * Maps the contents of an object, returning the address it is mapped
1265 * While the mapping holds a reference on the contents of the object, it doesn't
1266 * imply a ref on the object itself.
1269 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1270 struct drm_file
*file
)
1272 struct drm_i915_gem_mmap
*args
= data
;
1273 struct drm_gem_object
*obj
;
1276 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1280 /* prime objects have no backing filp to GEM mmap
1284 drm_gem_object_unreference_unlocked(obj
);
1288 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1289 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1291 drm_gem_object_unreference_unlocked(obj
);
1292 if (IS_ERR((void *)addr
))
1295 args
->addr_ptr
= (uint64_t) addr
;
1301 * i915_gem_fault - fault a page into the GTT
1302 * vma: VMA in question
1305 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1306 * from userspace. The fault handler takes care of binding the object to
1307 * the GTT (if needed), allocating and programming a fence register (again,
1308 * only if needed based on whether the old reg is still valid or the object
1309 * is tiled) and inserting a new PTE into the faulting process.
1311 * Note that the faulting process may involve evicting existing objects
1312 * from the GTT and/or fence registers to make room. So performance may
1313 * suffer if the GTT working set is large or there are few fence registers
1316 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1318 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1319 struct drm_device
*dev
= obj
->base
.dev
;
1320 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1321 pgoff_t page_offset
;
1324 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1326 /* We don't use vmf->pgoff since that has the fake offset */
1327 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1330 ret
= i915_mutex_lock_interruptible(dev
);
1334 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1336 /* Now bind it into the GTT if needed */
1337 ret
= i915_gem_object_pin(obj
, 0, true, false);
1341 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1345 ret
= i915_gem_object_get_fence(obj
);
1349 obj
->fault_mappable
= true;
1351 pfn
= ((dev_priv
->mm
.gtt_base_addr
+ obj
->gtt_offset
) >> PAGE_SHIFT
) +
1354 /* Finally, remap it using the new GTT offset */
1355 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1357 i915_gem_object_unpin(obj
);
1359 mutex_unlock(&dev
->struct_mutex
);
1363 /* If this -EIO is due to a gpu hang, give the reset code a
1364 * chance to clean up the mess. Otherwise return the proper
1366 if (!atomic_read(&dev_priv
->mm
.wedged
))
1367 return VM_FAULT_SIGBUS
;
1369 /* Give the error handler a chance to run and move the
1370 * objects off the GPU active list. Next time we service the
1371 * fault, we should be able to transition the page into the
1372 * GTT without touching the GPU (and so avoid further
1373 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1374 * with coherency, just lost writes.
1382 * EBUSY is ok: this just means that another thread
1383 * already did the job.
1385 return VM_FAULT_NOPAGE
;
1387 return VM_FAULT_OOM
;
1389 return VM_FAULT_SIGBUS
;
1391 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1392 return VM_FAULT_SIGBUS
;
1397 * i915_gem_release_mmap - remove physical page mappings
1398 * @obj: obj in question
1400 * Preserve the reservation of the mmapping with the DRM core code, but
1401 * relinquish ownership of the pages back to the system.
1403 * It is vital that we remove the page mapping if we have mapped a tiled
1404 * object through the GTT and then lose the fence register due to
1405 * resource pressure. Similarly if the object has been moved out of the
1406 * aperture, than pages mapped into userspace must be revoked. Removing the
1407 * mapping will then trigger a page fault on the next user access, allowing
1408 * fixup by i915_gem_fault().
1411 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1413 if (!obj
->fault_mappable
)
1416 if (obj
->base
.dev
->dev_mapping
)
1417 unmap_mapping_range(obj
->base
.dev
->dev_mapping
,
1418 (loff_t
)obj
->base
.map_list
.hash
.key
<<PAGE_SHIFT
,
1421 obj
->fault_mappable
= false;
1425 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1429 if (INTEL_INFO(dev
)->gen
>= 4 ||
1430 tiling_mode
== I915_TILING_NONE
)
1433 /* Previous chips need a power-of-two fence region when tiling */
1434 if (INTEL_INFO(dev
)->gen
== 3)
1435 gtt_size
= 1024*1024;
1437 gtt_size
= 512*1024;
1439 while (gtt_size
< size
)
1446 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1447 * @obj: object to check
1449 * Return the required GTT alignment for an object, taking into account
1450 * potential fence register mapping.
1453 i915_gem_get_gtt_alignment(struct drm_device
*dev
,
1458 * Minimum alignment is 4k (GTT page size), but might be greater
1459 * if a fence register is needed for the object.
1461 if (INTEL_INFO(dev
)->gen
>= 4 ||
1462 tiling_mode
== I915_TILING_NONE
)
1466 * Previous chips need to be aligned to the size of the smallest
1467 * fence register that can contain the object.
1469 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1473 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1476 * @size: size of the object
1477 * @tiling_mode: tiling mode of the object
1479 * Return the required GTT alignment for an object, only taking into account
1480 * unfenced tiled surface requirements.
1483 i915_gem_get_unfenced_gtt_alignment(struct drm_device
*dev
,
1488 * Minimum alignment is 4k (GTT page size) for sane hw.
1490 if (INTEL_INFO(dev
)->gen
>= 4 || IS_G33(dev
) ||
1491 tiling_mode
== I915_TILING_NONE
)
1494 /* Previous hardware however needs to be aligned to a power-of-two
1495 * tile height. The simplest method for determining this is to reuse
1496 * the power-of-tile object size.
1498 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1501 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
1503 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1506 if (obj
->base
.map_list
.map
)
1509 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1513 /* Badly fragmented mmap space? The only way we can recover
1514 * space is by destroying unwanted objects. We can't randomly release
1515 * mmap_offsets as userspace expects them to be persistent for the
1516 * lifetime of the objects. The closest we can is to release the
1517 * offsets on purgeable objects by truncating it and marking it purged,
1518 * which prevents userspace from ever using that object again.
1520 i915_gem_purge(dev_priv
, obj
->base
.size
>> PAGE_SHIFT
);
1521 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1525 i915_gem_shrink_all(dev_priv
);
1526 return drm_gem_create_mmap_offset(&obj
->base
);
1529 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
1531 if (!obj
->base
.map_list
.map
)
1534 drm_gem_free_mmap_offset(&obj
->base
);
1538 i915_gem_mmap_gtt(struct drm_file
*file
,
1539 struct drm_device
*dev
,
1543 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1544 struct drm_i915_gem_object
*obj
;
1547 ret
= i915_mutex_lock_interruptible(dev
);
1551 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
1552 if (&obj
->base
== NULL
) {
1557 if (obj
->base
.size
> dev_priv
->mm
.gtt_mappable_end
) {
1562 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1563 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1568 ret
= i915_gem_object_create_mmap_offset(obj
);
1572 *offset
= (u64
)obj
->base
.map_list
.hash
.key
<< PAGE_SHIFT
;
1575 drm_gem_object_unreference(&obj
->base
);
1577 mutex_unlock(&dev
->struct_mutex
);
1582 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1584 * @data: GTT mapping ioctl data
1585 * @file: GEM object info
1587 * Simply returns the fake offset to userspace so it can mmap it.
1588 * The mmap call will end up in drm_gem_mmap(), which will set things
1589 * up so we can get faults in the handler above.
1591 * The fault handler will take care of binding the object into the GTT
1592 * (since it may have been evicted to make room for something), allocating
1593 * a fence register, and mapping the appropriate aperture address into
1597 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1598 struct drm_file
*file
)
1600 struct drm_i915_gem_mmap_gtt
*args
= data
;
1602 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
1605 /* Immediately discard the backing storage */
1607 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
1609 struct inode
*inode
;
1611 i915_gem_object_free_mmap_offset(obj
);
1613 if (obj
->base
.filp
== NULL
)
1616 /* Our goal here is to return as much of the memory as
1617 * is possible back to the system as we are called from OOM.
1618 * To do this we must instruct the shmfs to drop all of its
1619 * backing pages, *now*.
1621 inode
= obj
->base
.filp
->f_path
.dentry
->d_inode
;
1622 shmem_truncate_range(inode
, 0, (loff_t
)-1);
1624 obj
->madv
= __I915_MADV_PURGED
;
1628 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj
)
1630 return obj
->madv
== I915_MADV_DONTNEED
;
1634 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
1636 int page_count
= obj
->base
.size
/ PAGE_SIZE
;
1637 struct scatterlist
*sg
;
1640 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
1642 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
1644 /* In the event of a disaster, abandon all caches and
1645 * hope for the best.
1647 WARN_ON(ret
!= -EIO
);
1648 i915_gem_clflush_object(obj
);
1649 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
1652 if (i915_gem_object_needs_bit17_swizzle(obj
))
1653 i915_gem_object_save_bit_17_swizzle(obj
);
1655 if (obj
->madv
== I915_MADV_DONTNEED
)
1658 for_each_sg(obj
->pages
->sgl
, sg
, page_count
, i
) {
1659 struct page
*page
= sg_page(sg
);
1662 set_page_dirty(page
);
1664 if (obj
->madv
== I915_MADV_WILLNEED
)
1665 mark_page_accessed(page
);
1667 page_cache_release(page
);
1671 sg_free_table(obj
->pages
);
1676 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
1678 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
1680 if (obj
->pages
== NULL
)
1683 BUG_ON(obj
->gtt_space
);
1685 if (obj
->pages_pin_count
)
1688 ops
->put_pages(obj
);
1691 list_del(&obj
->gtt_list
);
1692 if (i915_gem_object_is_purgeable(obj
))
1693 i915_gem_object_truncate(obj
);
1699 i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
)
1701 struct drm_i915_gem_object
*obj
, *next
;
1704 list_for_each_entry_safe(obj
, next
,
1705 &dev_priv
->mm
.unbound_list
,
1707 if (i915_gem_object_is_purgeable(obj
) &&
1708 i915_gem_object_put_pages(obj
) == 0) {
1709 count
+= obj
->base
.size
>> PAGE_SHIFT
;
1710 if (count
>= target
)
1715 list_for_each_entry_safe(obj
, next
,
1716 &dev_priv
->mm
.inactive_list
,
1718 if (i915_gem_object_is_purgeable(obj
) &&
1719 i915_gem_object_unbind(obj
) == 0 &&
1720 i915_gem_object_put_pages(obj
) == 0) {
1721 count
+= obj
->base
.size
>> PAGE_SHIFT
;
1722 if (count
>= target
)
1731 i915_gem_shrink_all(struct drm_i915_private
*dev_priv
)
1733 struct drm_i915_gem_object
*obj
, *next
;
1735 i915_gem_evict_everything(dev_priv
->dev
);
1737 list_for_each_entry_safe(obj
, next
, &dev_priv
->mm
.unbound_list
, gtt_list
)
1738 i915_gem_object_put_pages(obj
);
1742 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
1744 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1746 struct address_space
*mapping
;
1747 struct sg_table
*st
;
1748 struct scatterlist
*sg
;
1752 /* Assert that the object is not currently in any GPU domain. As it
1753 * wasn't in the GTT, there shouldn't be any way it could have been in
1756 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
1757 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
1759 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
1763 page_count
= obj
->base
.size
/ PAGE_SIZE
;
1764 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
1770 /* Get the list of pages out of our struct file. They'll be pinned
1771 * at this point until we release them.
1773 * Fail silently without starting the shrinker
1775 mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
1776 gfp
= mapping_gfp_mask(mapping
);
1777 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
;
1778 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
1779 for_each_sg(st
->sgl
, sg
, page_count
, i
) {
1780 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1782 i915_gem_purge(dev_priv
, page_count
);
1783 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1786 /* We've tried hard to allocate the memory by reaping
1787 * our own buffer, now let the real VM do its job and
1788 * go down in flames if truly OOM.
1790 gfp
&= ~(__GFP_NORETRY
| __GFP_NOWARN
);
1791 gfp
|= __GFP_IO
| __GFP_WAIT
;
1793 i915_gem_shrink_all(dev_priv
);
1794 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1798 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
;
1799 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
1802 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
1807 if (i915_gem_object_needs_bit17_swizzle(obj
))
1808 i915_gem_object_do_bit_17_swizzle(obj
);
1813 for_each_sg(st
->sgl
, sg
, i
, page_count
)
1814 page_cache_release(sg_page(sg
));
1817 return PTR_ERR(page
);
1820 /* Ensure that the associated pages are gathered from the backing storage
1821 * and pinned into our object. i915_gem_object_get_pages() may be called
1822 * multiple times before they are released by a single call to
1823 * i915_gem_object_put_pages() - once the pages are no longer referenced
1824 * either as a result of memory pressure (reaping pages under the shrinker)
1825 * or as the object is itself released.
1828 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
1830 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1831 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
1837 BUG_ON(obj
->pages_pin_count
);
1839 ret
= ops
->get_pages(obj
);
1843 list_add_tail(&obj
->gtt_list
, &dev_priv
->mm
.unbound_list
);
1848 i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1849 struct intel_ring_buffer
*ring
)
1851 struct drm_device
*dev
= obj
->base
.dev
;
1852 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1853 u32 seqno
= intel_ring_get_seqno(ring
);
1855 BUG_ON(ring
== NULL
);
1858 /* Add a reference if we're newly entering the active list. */
1860 drm_gem_object_reference(&obj
->base
);
1864 /* Move from whatever list we were on to the tail of execution. */
1865 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.active_list
);
1866 list_move_tail(&obj
->ring_list
, &ring
->active_list
);
1868 obj
->last_read_seqno
= seqno
;
1870 if (obj
->fenced_gpu_access
) {
1871 obj
->last_fenced_seqno
= seqno
;
1873 /* Bump MRU to take account of the delayed flush */
1874 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1875 struct drm_i915_fence_reg
*reg
;
1877 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
1878 list_move_tail(®
->lru_list
,
1879 &dev_priv
->mm
.fence_list
);
1885 i915_gem_object_move_to_inactive(struct drm_i915_gem_object
*obj
)
1887 struct drm_device
*dev
= obj
->base
.dev
;
1888 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1890 BUG_ON(obj
->base
.write_domain
& ~I915_GEM_GPU_DOMAINS
);
1891 BUG_ON(!obj
->active
);
1893 if (obj
->pin_count
) /* are we a framebuffer? */
1894 intel_mark_fb_idle(obj
);
1896 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
1898 list_del_init(&obj
->ring_list
);
1901 obj
->last_read_seqno
= 0;
1902 obj
->last_write_seqno
= 0;
1903 obj
->base
.write_domain
= 0;
1905 obj
->last_fenced_seqno
= 0;
1906 obj
->fenced_gpu_access
= false;
1909 drm_gem_object_unreference(&obj
->base
);
1911 WARN_ON(i915_verify_lists(dev
));
1915 i915_gem_handle_seqno_wrap(struct drm_device
*dev
)
1917 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1918 struct intel_ring_buffer
*ring
;
1921 /* The hardware uses various monotonic 32-bit counters, if we
1922 * detect that they will wraparound we need to idle the GPU
1923 * and reset those counters.
1926 for_each_ring(ring
, dev_priv
, i
) {
1927 for (j
= 0; j
< ARRAY_SIZE(ring
->sync_seqno
); j
++)
1928 ret
|= ring
->sync_seqno
[j
] != 0;
1933 ret
= i915_gpu_idle(dev
);
1937 i915_gem_retire_requests(dev
);
1938 for_each_ring(ring
, dev_priv
, i
) {
1939 for (j
= 0; j
< ARRAY_SIZE(ring
->sync_seqno
); j
++)
1940 ring
->sync_seqno
[j
] = 0;
1947 i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
)
1949 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1951 /* reserve 0 for non-seqno */
1952 if (dev_priv
->next_seqno
== 0) {
1953 int ret
= i915_gem_handle_seqno_wrap(dev
);
1957 dev_priv
->next_seqno
= 1;
1960 *seqno
= dev_priv
->next_seqno
++;
1965 i915_add_request(struct intel_ring_buffer
*ring
,
1966 struct drm_file
*file
,
1969 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1970 struct drm_i915_gem_request
*request
;
1971 u32 request_ring_position
;
1976 * Emit any outstanding flushes - execbuf can fail to emit the flush
1977 * after having emitted the batchbuffer command. Hence we need to fix
1978 * things up similar to emitting the lazy request. The difference here
1979 * is that the flush _must_ happen before the next request, no matter
1982 ret
= intel_ring_flush_all_caches(ring
);
1986 request
= kmalloc(sizeof(*request
), GFP_KERNEL
);
1987 if (request
== NULL
)
1991 /* Record the position of the start of the request so that
1992 * should we detect the updated seqno part-way through the
1993 * GPU processing the request, we never over-estimate the
1994 * position of the head.
1996 request_ring_position
= intel_ring_get_tail(ring
);
1998 ret
= ring
->add_request(ring
);
2004 request
->seqno
= intel_ring_get_seqno(ring
);
2005 request
->ring
= ring
;
2006 request
->tail
= request_ring_position
;
2007 request
->emitted_jiffies
= jiffies
;
2008 was_empty
= list_empty(&ring
->request_list
);
2009 list_add_tail(&request
->list
, &ring
->request_list
);
2010 request
->file_priv
= NULL
;
2013 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2015 spin_lock(&file_priv
->mm
.lock
);
2016 request
->file_priv
= file_priv
;
2017 list_add_tail(&request
->client_list
,
2018 &file_priv
->mm
.request_list
);
2019 spin_unlock(&file_priv
->mm
.lock
);
2022 trace_i915_gem_request_add(ring
, request
->seqno
);
2023 ring
->outstanding_lazy_request
= 0;
2025 if (!dev_priv
->mm
.suspended
) {
2026 if (i915_enable_hangcheck
) {
2027 mod_timer(&dev_priv
->hangcheck_timer
,
2028 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
2031 queue_delayed_work(dev_priv
->wq
,
2032 &dev_priv
->mm
.retire_work
,
2033 round_jiffies_up_relative(HZ
));
2034 intel_mark_busy(dev_priv
->dev
);
2039 *out_seqno
= request
->seqno
;
2044 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
2046 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
2051 spin_lock(&file_priv
->mm
.lock
);
2052 if (request
->file_priv
) {
2053 list_del(&request
->client_list
);
2054 request
->file_priv
= NULL
;
2056 spin_unlock(&file_priv
->mm
.lock
);
2059 static void i915_gem_reset_ring_lists(struct drm_i915_private
*dev_priv
,
2060 struct intel_ring_buffer
*ring
)
2062 while (!list_empty(&ring
->request_list
)) {
2063 struct drm_i915_gem_request
*request
;
2065 request
= list_first_entry(&ring
->request_list
,
2066 struct drm_i915_gem_request
,
2069 list_del(&request
->list
);
2070 i915_gem_request_remove_from_client(request
);
2074 while (!list_empty(&ring
->active_list
)) {
2075 struct drm_i915_gem_object
*obj
;
2077 obj
= list_first_entry(&ring
->active_list
,
2078 struct drm_i915_gem_object
,
2081 i915_gem_object_move_to_inactive(obj
);
2085 static void i915_gem_reset_fences(struct drm_device
*dev
)
2087 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2090 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2091 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2093 i915_gem_write_fence(dev
, i
, NULL
);
2096 i915_gem_object_fence_lost(reg
->obj
);
2100 INIT_LIST_HEAD(®
->lru_list
);
2103 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
2106 void i915_gem_reset(struct drm_device
*dev
)
2108 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2109 struct drm_i915_gem_object
*obj
;
2110 struct intel_ring_buffer
*ring
;
2113 for_each_ring(ring
, dev_priv
, i
)
2114 i915_gem_reset_ring_lists(dev_priv
, ring
);
2116 /* Move everything out of the GPU domains to ensure we do any
2117 * necessary invalidation upon reuse.
2119 list_for_each_entry(obj
,
2120 &dev_priv
->mm
.inactive_list
,
2123 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
2126 /* The fence registers are invalidated so clear them out */
2127 i915_gem_reset_fences(dev
);
2131 * This function clears the request list as sequence numbers are passed.
2134 i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
)
2138 if (list_empty(&ring
->request_list
))
2141 WARN_ON(i915_verify_lists(ring
->dev
));
2143 seqno
= ring
->get_seqno(ring
, true);
2145 while (!list_empty(&ring
->request_list
)) {
2146 struct drm_i915_gem_request
*request
;
2148 request
= list_first_entry(&ring
->request_list
,
2149 struct drm_i915_gem_request
,
2152 if (!i915_seqno_passed(seqno
, request
->seqno
))
2155 trace_i915_gem_request_retire(ring
, request
->seqno
);
2156 /* We know the GPU must have read the request to have
2157 * sent us the seqno + interrupt, so use the position
2158 * of tail of the request to update the last known position
2161 ring
->last_retired_head
= request
->tail
;
2163 list_del(&request
->list
);
2164 i915_gem_request_remove_from_client(request
);
2168 /* Move any buffers on the active list that are no longer referenced
2169 * by the ringbuffer to the flushing/inactive lists as appropriate.
2171 while (!list_empty(&ring
->active_list
)) {
2172 struct drm_i915_gem_object
*obj
;
2174 obj
= list_first_entry(&ring
->active_list
,
2175 struct drm_i915_gem_object
,
2178 if (!i915_seqno_passed(seqno
, obj
->last_read_seqno
))
2181 i915_gem_object_move_to_inactive(obj
);
2184 if (unlikely(ring
->trace_irq_seqno
&&
2185 i915_seqno_passed(seqno
, ring
->trace_irq_seqno
))) {
2186 ring
->irq_put(ring
);
2187 ring
->trace_irq_seqno
= 0;
2190 WARN_ON(i915_verify_lists(ring
->dev
));
2194 i915_gem_retire_requests(struct drm_device
*dev
)
2196 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2197 struct intel_ring_buffer
*ring
;
2200 for_each_ring(ring
, dev_priv
, i
)
2201 i915_gem_retire_requests_ring(ring
);
2205 i915_gem_retire_work_handler(struct work_struct
*work
)
2207 drm_i915_private_t
*dev_priv
;
2208 struct drm_device
*dev
;
2209 struct intel_ring_buffer
*ring
;
2213 dev_priv
= container_of(work
, drm_i915_private_t
,
2214 mm
.retire_work
.work
);
2215 dev
= dev_priv
->dev
;
2217 /* Come back later if the device is busy... */
2218 if (!mutex_trylock(&dev
->struct_mutex
)) {
2219 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2220 round_jiffies_up_relative(HZ
));
2224 i915_gem_retire_requests(dev
);
2226 /* Send a periodic flush down the ring so we don't hold onto GEM
2227 * objects indefinitely.
2230 for_each_ring(ring
, dev_priv
, i
) {
2231 if (ring
->gpu_caches_dirty
)
2232 i915_add_request(ring
, NULL
, NULL
);
2234 idle
&= list_empty(&ring
->request_list
);
2237 if (!dev_priv
->mm
.suspended
&& !idle
)
2238 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2239 round_jiffies_up_relative(HZ
));
2241 intel_mark_idle(dev
);
2243 mutex_unlock(&dev
->struct_mutex
);
2247 * Ensures that an object will eventually get non-busy by flushing any required
2248 * write domains, emitting any outstanding lazy request and retiring and
2249 * completed requests.
2252 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
2257 ret
= i915_gem_check_olr(obj
->ring
, obj
->last_read_seqno
);
2261 i915_gem_retire_requests_ring(obj
->ring
);
2268 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2269 * @DRM_IOCTL_ARGS: standard ioctl arguments
2271 * Returns 0 if successful, else an error is returned with the remaining time in
2272 * the timeout parameter.
2273 * -ETIME: object is still busy after timeout
2274 * -ERESTARTSYS: signal interrupted the wait
2275 * -ENONENT: object doesn't exist
2276 * Also possible, but rare:
2277 * -EAGAIN: GPU wedged
2279 * -ENODEV: Internal IRQ fail
2280 * -E?: The add request failed
2282 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2283 * non-zero timeout parameter the wait ioctl will wait for the given number of
2284 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2285 * without holding struct_mutex the object may become re-busied before this
2286 * function completes. A similar but shorter * race condition exists in the busy
2290 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
2292 struct drm_i915_gem_wait
*args
= data
;
2293 struct drm_i915_gem_object
*obj
;
2294 struct intel_ring_buffer
*ring
= NULL
;
2295 struct timespec timeout_stack
, *timeout
= NULL
;
2299 if (args
->timeout_ns
>= 0) {
2300 timeout_stack
= ns_to_timespec(args
->timeout_ns
);
2301 timeout
= &timeout_stack
;
2304 ret
= i915_mutex_lock_interruptible(dev
);
2308 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
2309 if (&obj
->base
== NULL
) {
2310 mutex_unlock(&dev
->struct_mutex
);
2314 /* Need to make sure the object gets inactive eventually. */
2315 ret
= i915_gem_object_flush_active(obj
);
2320 seqno
= obj
->last_read_seqno
;
2327 /* Do this after OLR check to make sure we make forward progress polling
2328 * on this IOCTL with a 0 timeout (like busy ioctl)
2330 if (!args
->timeout_ns
) {
2335 drm_gem_object_unreference(&obj
->base
);
2336 mutex_unlock(&dev
->struct_mutex
);
2338 ret
= __wait_seqno(ring
, seqno
, true, timeout
);
2340 WARN_ON(!timespec_valid(timeout
));
2341 args
->timeout_ns
= timespec_to_ns(timeout
);
2346 drm_gem_object_unreference(&obj
->base
);
2347 mutex_unlock(&dev
->struct_mutex
);
2352 * i915_gem_object_sync - sync an object to a ring.
2354 * @obj: object which may be in use on another ring.
2355 * @to: ring we wish to use the object on. May be NULL.
2357 * This code is meant to abstract object synchronization with the GPU.
2358 * Calling with NULL implies synchronizing the object with the CPU
2359 * rather than a particular GPU ring.
2361 * Returns 0 if successful, else propagates up the lower layer error.
2364 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2365 struct intel_ring_buffer
*to
)
2367 struct intel_ring_buffer
*from
= obj
->ring
;
2371 if (from
== NULL
|| to
== from
)
2374 if (to
== NULL
|| !i915_semaphore_is_enabled(obj
->base
.dev
))
2375 return i915_gem_object_wait_rendering(obj
, false);
2377 idx
= intel_ring_sync_index(from
, to
);
2379 seqno
= obj
->last_read_seqno
;
2380 if (seqno
<= from
->sync_seqno
[idx
])
2383 ret
= i915_gem_check_olr(obj
->ring
, seqno
);
2387 ret
= to
->sync_to(to
, from
, seqno
);
2389 /* We use last_read_seqno because sync_to()
2390 * might have just caused seqno wrap under
2393 from
->sync_seqno
[idx
] = obj
->last_read_seqno
;
2398 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
2400 u32 old_write_domain
, old_read_domains
;
2402 /* Act a barrier for all accesses through the GTT */
2405 /* Force a pagefault for domain tracking on next user access */
2406 i915_gem_release_mmap(obj
);
2408 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
2411 old_read_domains
= obj
->base
.read_domains
;
2412 old_write_domain
= obj
->base
.write_domain
;
2414 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
2415 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
2417 trace_i915_gem_object_change_domain(obj
,
2423 * Unbinds an object from the GTT aperture.
2426 i915_gem_object_unbind(struct drm_i915_gem_object
*obj
)
2428 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
2431 if (obj
->gtt_space
== NULL
)
2437 BUG_ON(obj
->pages
== NULL
);
2439 ret
= i915_gem_object_finish_gpu(obj
);
2442 /* Continue on if we fail due to EIO, the GPU is hung so we
2443 * should be safe and we need to cleanup or else we might
2444 * cause memory corruption through use-after-free.
2447 i915_gem_object_finish_gtt(obj
);
2449 /* release the fence reg _after_ flushing */
2450 ret
= i915_gem_object_put_fence(obj
);
2454 trace_i915_gem_object_unbind(obj
);
2456 if (obj
->has_global_gtt_mapping
)
2457 i915_gem_gtt_unbind_object(obj
);
2458 if (obj
->has_aliasing_ppgtt_mapping
) {
2459 i915_ppgtt_unbind_object(dev_priv
->mm
.aliasing_ppgtt
, obj
);
2460 obj
->has_aliasing_ppgtt_mapping
= 0;
2462 i915_gem_gtt_finish_object(obj
);
2464 list_del(&obj
->mm_list
);
2465 list_move_tail(&obj
->gtt_list
, &dev_priv
->mm
.unbound_list
);
2466 /* Avoid an unnecessary call to unbind on rebind. */
2467 obj
->map_and_fenceable
= true;
2469 drm_mm_put_block(obj
->gtt_space
);
2470 obj
->gtt_space
= NULL
;
2471 obj
->gtt_offset
= 0;
2476 int i915_gpu_idle(struct drm_device
*dev
)
2478 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2479 struct intel_ring_buffer
*ring
;
2482 /* Flush everything onto the inactive list. */
2483 for_each_ring(ring
, dev_priv
, i
) {
2484 ret
= i915_switch_context(ring
, NULL
, DEFAULT_CONTEXT_ID
);
2488 ret
= intel_ring_idle(ring
);
2496 static void sandybridge_write_fence_reg(struct drm_device
*dev
, int reg
,
2497 struct drm_i915_gem_object
*obj
)
2499 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2503 u32 size
= obj
->gtt_space
->size
;
2505 val
= (uint64_t)((obj
->gtt_offset
+ size
- 4096) &
2507 val
|= obj
->gtt_offset
& 0xfffff000;
2508 val
|= (uint64_t)((obj
->stride
/ 128) - 1) <<
2509 SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2511 if (obj
->tiling_mode
== I915_TILING_Y
)
2512 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2513 val
|= I965_FENCE_REG_VALID
;
2517 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ reg
* 8, val
);
2518 POSTING_READ(FENCE_REG_SANDYBRIDGE_0
+ reg
* 8);
2521 static void i965_write_fence_reg(struct drm_device
*dev
, int reg
,
2522 struct drm_i915_gem_object
*obj
)
2524 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2528 u32 size
= obj
->gtt_space
->size
;
2530 val
= (uint64_t)((obj
->gtt_offset
+ size
- 4096) &
2532 val
|= obj
->gtt_offset
& 0xfffff000;
2533 val
|= ((obj
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2534 if (obj
->tiling_mode
== I915_TILING_Y
)
2535 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2536 val
|= I965_FENCE_REG_VALID
;
2540 I915_WRITE64(FENCE_REG_965_0
+ reg
* 8, val
);
2541 POSTING_READ(FENCE_REG_965_0
+ reg
* 8);
2544 static void i915_write_fence_reg(struct drm_device
*dev
, int reg
,
2545 struct drm_i915_gem_object
*obj
)
2547 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2551 u32 size
= obj
->gtt_space
->size
;
2555 WARN((obj
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2556 (size
& -size
) != size
||
2557 (obj
->gtt_offset
& (size
- 1)),
2558 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2559 obj
->gtt_offset
, obj
->map_and_fenceable
, size
);
2561 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
2566 /* Note: pitch better be a power of two tile widths */
2567 pitch_val
= obj
->stride
/ tile_width
;
2568 pitch_val
= ffs(pitch_val
) - 1;
2570 val
= obj
->gtt_offset
;
2571 if (obj
->tiling_mode
== I915_TILING_Y
)
2572 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2573 val
|= I915_FENCE_SIZE_BITS(size
);
2574 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2575 val
|= I830_FENCE_REG_VALID
;
2580 reg
= FENCE_REG_830_0
+ reg
* 4;
2582 reg
= FENCE_REG_945_8
+ (reg
- 8) * 4;
2584 I915_WRITE(reg
, val
);
2588 static void i830_write_fence_reg(struct drm_device
*dev
, int reg
,
2589 struct drm_i915_gem_object
*obj
)
2591 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2595 u32 size
= obj
->gtt_space
->size
;
2598 WARN((obj
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2599 (size
& -size
) != size
||
2600 (obj
->gtt_offset
& (size
- 1)),
2601 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2602 obj
->gtt_offset
, size
);
2604 pitch_val
= obj
->stride
/ 128;
2605 pitch_val
= ffs(pitch_val
) - 1;
2607 val
= obj
->gtt_offset
;
2608 if (obj
->tiling_mode
== I915_TILING_Y
)
2609 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2610 val
|= I830_FENCE_SIZE_BITS(size
);
2611 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2612 val
|= I830_FENCE_REG_VALID
;
2616 I915_WRITE(FENCE_REG_830_0
+ reg
* 4, val
);
2617 POSTING_READ(FENCE_REG_830_0
+ reg
* 4);
2620 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
2621 struct drm_i915_gem_object
*obj
)
2623 switch (INTEL_INFO(dev
)->gen
) {
2625 case 6: sandybridge_write_fence_reg(dev
, reg
, obj
); break;
2627 case 4: i965_write_fence_reg(dev
, reg
, obj
); break;
2628 case 3: i915_write_fence_reg(dev
, reg
, obj
); break;
2629 case 2: i830_write_fence_reg(dev
, reg
, obj
); break;
2634 static inline int fence_number(struct drm_i915_private
*dev_priv
,
2635 struct drm_i915_fence_reg
*fence
)
2637 return fence
- dev_priv
->fence_regs
;
2640 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
2641 struct drm_i915_fence_reg
*fence
,
2644 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2645 int reg
= fence_number(dev_priv
, fence
);
2647 i915_gem_write_fence(obj
->base
.dev
, reg
, enable
? obj
: NULL
);
2650 obj
->fence_reg
= reg
;
2652 list_move_tail(&fence
->lru_list
, &dev_priv
->mm
.fence_list
);
2654 obj
->fence_reg
= I915_FENCE_REG_NONE
;
2656 list_del_init(&fence
->lru_list
);
2661 i915_gem_object_flush_fence(struct drm_i915_gem_object
*obj
)
2663 if (obj
->last_fenced_seqno
) {
2664 int ret
= i915_wait_seqno(obj
->ring
, obj
->last_fenced_seqno
);
2668 obj
->last_fenced_seqno
= 0;
2671 /* Ensure that all CPU reads are completed before installing a fence
2672 * and all writes before removing the fence.
2674 if (obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
)
2677 obj
->fenced_gpu_access
= false;
2682 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
2684 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2687 ret
= i915_gem_object_flush_fence(obj
);
2691 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
2694 i915_gem_object_update_fence(obj
,
2695 &dev_priv
->fence_regs
[obj
->fence_reg
],
2697 i915_gem_object_fence_lost(obj
);
2702 static struct drm_i915_fence_reg
*
2703 i915_find_fence_reg(struct drm_device
*dev
)
2705 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2706 struct drm_i915_fence_reg
*reg
, *avail
;
2709 /* First try to find a free reg */
2711 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2712 reg
= &dev_priv
->fence_regs
[i
];
2716 if (!reg
->pin_count
)
2723 /* None available, try to steal one or wait for a user to finish */
2724 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
2735 * i915_gem_object_get_fence - set up fencing for an object
2736 * @obj: object to map through a fence reg
2738 * When mapping objects through the GTT, userspace wants to be able to write
2739 * to them without having to worry about swizzling if the object is tiled.
2740 * This function walks the fence regs looking for a free one for @obj,
2741 * stealing one if it can't find any.
2743 * It then sets up the reg based on the object's properties: address, pitch
2744 * and tiling format.
2746 * For an untiled surface, this removes any existing fence.
2749 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
2751 struct drm_device
*dev
= obj
->base
.dev
;
2752 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2753 bool enable
= obj
->tiling_mode
!= I915_TILING_NONE
;
2754 struct drm_i915_fence_reg
*reg
;
2757 /* Have we updated the tiling parameters upon the object and so
2758 * will need to serialise the write to the associated fence register?
2760 if (obj
->fence_dirty
) {
2761 ret
= i915_gem_object_flush_fence(obj
);
2766 /* Just update our place in the LRU if our fence is getting reused. */
2767 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2768 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
2769 if (!obj
->fence_dirty
) {
2770 list_move_tail(®
->lru_list
,
2771 &dev_priv
->mm
.fence_list
);
2774 } else if (enable
) {
2775 reg
= i915_find_fence_reg(dev
);
2780 struct drm_i915_gem_object
*old
= reg
->obj
;
2782 ret
= i915_gem_object_flush_fence(old
);
2786 i915_gem_object_fence_lost(old
);
2791 i915_gem_object_update_fence(obj
, reg
, enable
);
2792 obj
->fence_dirty
= false;
2797 static bool i915_gem_valid_gtt_space(struct drm_device
*dev
,
2798 struct drm_mm_node
*gtt_space
,
2799 unsigned long cache_level
)
2801 struct drm_mm_node
*other
;
2803 /* On non-LLC machines we have to be careful when putting differing
2804 * types of snoopable memory together to avoid the prefetcher
2805 * crossing memory domains and dieing.
2810 if (gtt_space
== NULL
)
2813 if (list_empty(>t_space
->node_list
))
2816 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
2817 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
2820 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
2821 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
2827 static void i915_gem_verify_gtt(struct drm_device
*dev
)
2830 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2831 struct drm_i915_gem_object
*obj
;
2834 list_for_each_entry(obj
, &dev_priv
->mm
.gtt_list
, gtt_list
) {
2835 if (obj
->gtt_space
== NULL
) {
2836 printk(KERN_ERR
"object found on GTT list with no space reserved\n");
2841 if (obj
->cache_level
!= obj
->gtt_space
->color
) {
2842 printk(KERN_ERR
"object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
2843 obj
->gtt_space
->start
,
2844 obj
->gtt_space
->start
+ obj
->gtt_space
->size
,
2846 obj
->gtt_space
->color
);
2851 if (!i915_gem_valid_gtt_space(dev
,
2853 obj
->cache_level
)) {
2854 printk(KERN_ERR
"invalid GTT space found at [%08lx, %08lx] - color=%x\n",
2855 obj
->gtt_space
->start
,
2856 obj
->gtt_space
->start
+ obj
->gtt_space
->size
,
2868 * Finds free space in the GTT aperture and binds the object there.
2871 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
2873 bool map_and_fenceable
,
2876 struct drm_device
*dev
= obj
->base
.dev
;
2877 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2878 struct drm_mm_node
*free_space
;
2879 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
2880 bool mappable
, fenceable
;
2883 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2884 DRM_ERROR("Attempting to bind a purgeable object\n");
2888 fence_size
= i915_gem_get_gtt_size(dev
,
2891 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
2894 unfenced_alignment
=
2895 i915_gem_get_unfenced_gtt_alignment(dev
,
2900 alignment
= map_and_fenceable
? fence_alignment
:
2902 if (map_and_fenceable
&& alignment
& (fence_alignment
- 1)) {
2903 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2907 size
= map_and_fenceable
? fence_size
: obj
->base
.size
;
2909 /* If the object is bigger than the entire aperture, reject it early
2910 * before evicting everything in a vain attempt to find space.
2912 if (obj
->base
.size
>
2913 (map_and_fenceable
? dev_priv
->mm
.gtt_mappable_end
: dev_priv
->mm
.gtt_total
)) {
2914 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2918 ret
= i915_gem_object_get_pages(obj
);
2922 i915_gem_object_pin_pages(obj
);
2925 if (map_and_fenceable
)
2926 free_space
= drm_mm_search_free_in_range_color(&dev_priv
->mm
.gtt_space
,
2927 size
, alignment
, obj
->cache_level
,
2928 0, dev_priv
->mm
.gtt_mappable_end
,
2931 free_space
= drm_mm_search_free_color(&dev_priv
->mm
.gtt_space
,
2932 size
, alignment
, obj
->cache_level
,
2935 if (free_space
!= NULL
) {
2936 if (map_and_fenceable
)
2938 drm_mm_get_block_range_generic(free_space
,
2939 size
, alignment
, obj
->cache_level
,
2940 0, dev_priv
->mm
.gtt_mappable_end
,
2944 drm_mm_get_block_generic(free_space
,
2945 size
, alignment
, obj
->cache_level
,
2948 if (free_space
== NULL
) {
2949 ret
= i915_gem_evict_something(dev
, size
, alignment
,
2954 i915_gem_object_unpin_pages(obj
);
2960 if (WARN_ON(!i915_gem_valid_gtt_space(dev
,
2962 obj
->cache_level
))) {
2963 i915_gem_object_unpin_pages(obj
);
2964 drm_mm_put_block(free_space
);
2968 ret
= i915_gem_gtt_prepare_object(obj
);
2970 i915_gem_object_unpin_pages(obj
);
2971 drm_mm_put_block(free_space
);
2975 list_move_tail(&obj
->gtt_list
, &dev_priv
->mm
.bound_list
);
2976 list_add_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
2978 obj
->gtt_space
= free_space
;
2979 obj
->gtt_offset
= free_space
->start
;
2982 free_space
->size
== fence_size
&&
2983 (free_space
->start
& (fence_alignment
- 1)) == 0;
2986 obj
->gtt_offset
+ obj
->base
.size
<= dev_priv
->mm
.gtt_mappable_end
;
2988 obj
->map_and_fenceable
= mappable
&& fenceable
;
2990 i915_gem_object_unpin_pages(obj
);
2991 trace_i915_gem_object_bind(obj
, map_and_fenceable
);
2992 i915_gem_verify_gtt(dev
);
2997 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
)
2999 /* If we don't have a page list set up, then we're not pinned
3000 * to GPU, and we can ignore the cache flush because it'll happen
3001 * again at bind time.
3003 if (obj
->pages
== NULL
)
3006 /* If the GPU is snooping the contents of the CPU cache,
3007 * we do not need to manually clear the CPU cache lines. However,
3008 * the caches are only snooped when the render cache is
3009 * flushed/invalidated. As we always have to emit invalidations
3010 * and flushes when moving into and out of the RENDER domain, correct
3011 * snooping behaviour occurs naturally as the result of our domain
3014 if (obj
->cache_level
!= I915_CACHE_NONE
)
3017 trace_i915_gem_object_clflush(obj
);
3019 drm_clflush_sg(obj
->pages
);
3022 /** Flushes the GTT write domain for the object if it's dirty. */
3024 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3026 uint32_t old_write_domain
;
3028 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3031 /* No actual flushing is required for the GTT write domain. Writes
3032 * to it immediately go to main memory as far as we know, so there's
3033 * no chipset flush. It also doesn't land in render cache.
3035 * However, we do have to enforce the order so that all writes through
3036 * the GTT land before any writes to the device, such as updates to
3041 old_write_domain
= obj
->base
.write_domain
;
3042 obj
->base
.write_domain
= 0;
3044 trace_i915_gem_object_change_domain(obj
,
3045 obj
->base
.read_domains
,
3049 /** Flushes the CPU write domain for the object if it's dirty. */
3051 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
3053 uint32_t old_write_domain
;
3055 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3058 i915_gem_clflush_object(obj
);
3059 i915_gem_chipset_flush(obj
->base
.dev
);
3060 old_write_domain
= obj
->base
.write_domain
;
3061 obj
->base
.write_domain
= 0;
3063 trace_i915_gem_object_change_domain(obj
,
3064 obj
->base
.read_domains
,
3069 * Moves a single object to the GTT read, and possibly write domain.
3071 * This function returns when the move is complete, including waiting on
3075 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3077 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
3078 uint32_t old_write_domain
, old_read_domains
;
3081 /* Not valid to be called on unbound objects. */
3082 if (obj
->gtt_space
== NULL
)
3085 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3088 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3092 i915_gem_object_flush_cpu_write_domain(obj
);
3094 old_write_domain
= obj
->base
.write_domain
;
3095 old_read_domains
= obj
->base
.read_domains
;
3097 /* It should now be out of any other write domains, and we can update
3098 * the domain values for our changes.
3100 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3101 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3103 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3104 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3108 trace_i915_gem_object_change_domain(obj
,
3112 /* And bump the LRU for this access */
3113 if (i915_gem_object_is_inactive(obj
))
3114 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
3119 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3120 enum i915_cache_level cache_level
)
3122 struct drm_device
*dev
= obj
->base
.dev
;
3123 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3126 if (obj
->cache_level
== cache_level
)
3129 if (obj
->pin_count
) {
3130 DRM_DEBUG("can not change the cache level of pinned objects\n");
3134 if (!i915_gem_valid_gtt_space(dev
, obj
->gtt_space
, cache_level
)) {
3135 ret
= i915_gem_object_unbind(obj
);
3140 if (obj
->gtt_space
) {
3141 ret
= i915_gem_object_finish_gpu(obj
);
3145 i915_gem_object_finish_gtt(obj
);
3147 /* Before SandyBridge, you could not use tiling or fence
3148 * registers with snooped memory, so relinquish any fences
3149 * currently pointing to our region in the aperture.
3151 if (INTEL_INFO(dev
)->gen
< 6) {
3152 ret
= i915_gem_object_put_fence(obj
);
3157 if (obj
->has_global_gtt_mapping
)
3158 i915_gem_gtt_bind_object(obj
, cache_level
);
3159 if (obj
->has_aliasing_ppgtt_mapping
)
3160 i915_ppgtt_bind_object(dev_priv
->mm
.aliasing_ppgtt
,
3163 obj
->gtt_space
->color
= cache_level
;
3166 if (cache_level
== I915_CACHE_NONE
) {
3167 u32 old_read_domains
, old_write_domain
;
3169 /* If we're coming from LLC cached, then we haven't
3170 * actually been tracking whether the data is in the
3171 * CPU cache or not, since we only allow one bit set
3172 * in obj->write_domain and have been skipping the clflushes.
3173 * Just set it to the CPU cache for now.
3175 WARN_ON(obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
);
3176 WARN_ON(obj
->base
.read_domains
& ~I915_GEM_DOMAIN_CPU
);
3178 old_read_domains
= obj
->base
.read_domains
;
3179 old_write_domain
= obj
->base
.write_domain
;
3181 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3182 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3184 trace_i915_gem_object_change_domain(obj
,
3189 obj
->cache_level
= cache_level
;
3190 i915_gem_verify_gtt(dev
);
3194 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3195 struct drm_file
*file
)
3197 struct drm_i915_gem_caching
*args
= data
;
3198 struct drm_i915_gem_object
*obj
;
3201 ret
= i915_mutex_lock_interruptible(dev
);
3205 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3206 if (&obj
->base
== NULL
) {
3211 args
->caching
= obj
->cache_level
!= I915_CACHE_NONE
;
3213 drm_gem_object_unreference(&obj
->base
);
3215 mutex_unlock(&dev
->struct_mutex
);
3219 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3220 struct drm_file
*file
)
3222 struct drm_i915_gem_caching
*args
= data
;
3223 struct drm_i915_gem_object
*obj
;
3224 enum i915_cache_level level
;
3227 switch (args
->caching
) {
3228 case I915_CACHING_NONE
:
3229 level
= I915_CACHE_NONE
;
3231 case I915_CACHING_CACHED
:
3232 level
= I915_CACHE_LLC
;
3238 ret
= i915_mutex_lock_interruptible(dev
);
3242 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3243 if (&obj
->base
== NULL
) {
3248 ret
= i915_gem_object_set_cache_level(obj
, level
);
3250 drm_gem_object_unreference(&obj
->base
);
3252 mutex_unlock(&dev
->struct_mutex
);
3257 * Prepare buffer for display plane (scanout, cursors, etc).
3258 * Can be called from an uninterruptible phase (modesetting) and allows
3259 * any flushes to be pipelined (for pageflips).
3262 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3264 struct intel_ring_buffer
*pipelined
)
3266 u32 old_read_domains
, old_write_domain
;
3269 if (pipelined
!= obj
->ring
) {
3270 ret
= i915_gem_object_sync(obj
, pipelined
);
3275 /* The display engine is not coherent with the LLC cache on gen6. As
3276 * a result, we make sure that the pinning that is about to occur is
3277 * done with uncached PTEs. This is lowest common denominator for all
3280 * However for gen6+, we could do better by using the GFDT bit instead
3281 * of uncaching, which would allow us to flush all the LLC-cached data
3282 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3284 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_NONE
);
3288 /* As the user may map the buffer once pinned in the display plane
3289 * (e.g. libkms for the bootup splash), we have to ensure that we
3290 * always use map_and_fenceable for all scanout buffers.
3292 ret
= i915_gem_object_pin(obj
, alignment
, true, false);
3296 i915_gem_object_flush_cpu_write_domain(obj
);
3298 old_write_domain
= obj
->base
.write_domain
;
3299 old_read_domains
= obj
->base
.read_domains
;
3301 /* It should now be out of any other write domains, and we can update
3302 * the domain values for our changes.
3304 obj
->base
.write_domain
= 0;
3305 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3307 trace_i915_gem_object_change_domain(obj
,
3315 i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
)
3319 if ((obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
) == 0)
3322 ret
= i915_gem_object_wait_rendering(obj
, false);
3326 /* Ensure that we invalidate the GPU's caches and TLBs. */
3327 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
3332 * Moves a single object to the CPU read, and possibly write domain.
3334 * This function returns when the move is complete, including waiting on
3338 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
3340 uint32_t old_write_domain
, old_read_domains
;
3343 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
3346 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3350 i915_gem_object_flush_gtt_write_domain(obj
);
3352 old_write_domain
= obj
->base
.write_domain
;
3353 old_read_domains
= obj
->base
.read_domains
;
3355 /* Flush the CPU cache if it's still invalid. */
3356 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
3357 i915_gem_clflush_object(obj
);
3359 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
3362 /* It should now be out of any other write domains, and we can update
3363 * the domain values for our changes.
3365 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3367 /* If we're writing through the CPU, then the GPU read domains will
3368 * need to be invalidated at next use.
3371 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3372 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3375 trace_i915_gem_object_change_domain(obj
,
3382 /* Throttle our rendering by waiting until the ring has completed our requests
3383 * emitted over 20 msec ago.
3385 * Note that if we were to use the current jiffies each time around the loop,
3386 * we wouldn't escape the function with any frames outstanding if the time to
3387 * render a frame was over 20ms.
3389 * This should get us reasonable parallelism between CPU and GPU but also
3390 * relatively low latency when blocking on a particular request to finish.
3393 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3395 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3396 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3397 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3398 struct drm_i915_gem_request
*request
;
3399 struct intel_ring_buffer
*ring
= NULL
;
3403 if (atomic_read(&dev_priv
->mm
.wedged
))
3406 spin_lock(&file_priv
->mm
.lock
);
3407 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3408 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3411 ring
= request
->ring
;
3412 seqno
= request
->seqno
;
3414 spin_unlock(&file_priv
->mm
.lock
);
3419 ret
= __wait_seqno(ring
, seqno
, true, NULL
);
3421 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3427 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
3429 bool map_and_fenceable
,
3434 if (WARN_ON(obj
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
3437 if (obj
->gtt_space
!= NULL
) {
3438 if ((alignment
&& obj
->gtt_offset
& (alignment
- 1)) ||
3439 (map_and_fenceable
&& !obj
->map_and_fenceable
)) {
3440 WARN(obj
->pin_count
,
3441 "bo is already pinned with incorrect alignment:"
3442 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3443 " obj->map_and_fenceable=%d\n",
3444 obj
->gtt_offset
, alignment
,
3446 obj
->map_and_fenceable
);
3447 ret
= i915_gem_object_unbind(obj
);
3453 if (obj
->gtt_space
== NULL
) {
3454 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3456 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
,
3462 if (!dev_priv
->mm
.aliasing_ppgtt
)
3463 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
3466 if (!obj
->has_global_gtt_mapping
&& map_and_fenceable
)
3467 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
3470 obj
->pin_mappable
|= map_and_fenceable
;
3476 i915_gem_object_unpin(struct drm_i915_gem_object
*obj
)
3478 BUG_ON(obj
->pin_count
== 0);
3479 BUG_ON(obj
->gtt_space
== NULL
);
3481 if (--obj
->pin_count
== 0)
3482 obj
->pin_mappable
= false;
3486 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
3487 struct drm_file
*file
)
3489 struct drm_i915_gem_pin
*args
= data
;
3490 struct drm_i915_gem_object
*obj
;
3493 ret
= i915_mutex_lock_interruptible(dev
);
3497 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3498 if (&obj
->base
== NULL
) {
3503 if (obj
->madv
!= I915_MADV_WILLNEED
) {
3504 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3509 if (obj
->pin_filp
!= NULL
&& obj
->pin_filp
!= file
) {
3510 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3516 obj
->user_pin_count
++;
3517 obj
->pin_filp
= file
;
3518 if (obj
->user_pin_count
== 1) {
3519 ret
= i915_gem_object_pin(obj
, args
->alignment
, true, false);
3524 /* XXX - flush the CPU caches for pinned objects
3525 * as the X server doesn't manage domains yet
3527 i915_gem_object_flush_cpu_write_domain(obj
);
3528 args
->offset
= obj
->gtt_offset
;
3530 drm_gem_object_unreference(&obj
->base
);
3532 mutex_unlock(&dev
->struct_mutex
);
3537 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
3538 struct drm_file
*file
)
3540 struct drm_i915_gem_pin
*args
= data
;
3541 struct drm_i915_gem_object
*obj
;
3544 ret
= i915_mutex_lock_interruptible(dev
);
3548 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3549 if (&obj
->base
== NULL
) {
3554 if (obj
->pin_filp
!= file
) {
3555 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3560 obj
->user_pin_count
--;
3561 if (obj
->user_pin_count
== 0) {
3562 obj
->pin_filp
= NULL
;
3563 i915_gem_object_unpin(obj
);
3567 drm_gem_object_unreference(&obj
->base
);
3569 mutex_unlock(&dev
->struct_mutex
);
3574 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3575 struct drm_file
*file
)
3577 struct drm_i915_gem_busy
*args
= data
;
3578 struct drm_i915_gem_object
*obj
;
3581 ret
= i915_mutex_lock_interruptible(dev
);
3585 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3586 if (&obj
->base
== NULL
) {
3591 /* Count all active objects as busy, even if they are currently not used
3592 * by the gpu. Users of this interface expect objects to eventually
3593 * become non-busy without any further actions, therefore emit any
3594 * necessary flushes here.
3596 ret
= i915_gem_object_flush_active(obj
);
3598 args
->busy
= obj
->active
;
3600 BUILD_BUG_ON(I915_NUM_RINGS
> 16);
3601 args
->busy
|= intel_ring_flag(obj
->ring
) << 16;
3604 drm_gem_object_unreference(&obj
->base
);
3606 mutex_unlock(&dev
->struct_mutex
);
3611 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3612 struct drm_file
*file_priv
)
3614 return i915_gem_ring_throttle(dev
, file_priv
);
3618 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3619 struct drm_file
*file_priv
)
3621 struct drm_i915_gem_madvise
*args
= data
;
3622 struct drm_i915_gem_object
*obj
;
3625 switch (args
->madv
) {
3626 case I915_MADV_DONTNEED
:
3627 case I915_MADV_WILLNEED
:
3633 ret
= i915_mutex_lock_interruptible(dev
);
3637 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
3638 if (&obj
->base
== NULL
) {
3643 if (obj
->pin_count
) {
3648 if (obj
->madv
!= __I915_MADV_PURGED
)
3649 obj
->madv
= args
->madv
;
3651 /* if the object is no longer attached, discard its backing storage */
3652 if (i915_gem_object_is_purgeable(obj
) && obj
->pages
== NULL
)
3653 i915_gem_object_truncate(obj
);
3655 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
3658 drm_gem_object_unreference(&obj
->base
);
3660 mutex_unlock(&dev
->struct_mutex
);
3664 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
3665 const struct drm_i915_gem_object_ops
*ops
)
3667 INIT_LIST_HEAD(&obj
->mm_list
);
3668 INIT_LIST_HEAD(&obj
->gtt_list
);
3669 INIT_LIST_HEAD(&obj
->ring_list
);
3670 INIT_LIST_HEAD(&obj
->exec_list
);
3674 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3675 obj
->madv
= I915_MADV_WILLNEED
;
3676 /* Avoid an unnecessary call to unbind on the first bind. */
3677 obj
->map_and_fenceable
= true;
3679 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
3682 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
3683 .get_pages
= i915_gem_object_get_pages_gtt
,
3684 .put_pages
= i915_gem_object_put_pages_gtt
,
3687 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
3690 struct drm_i915_gem_object
*obj
;
3691 struct address_space
*mapping
;
3694 obj
= kzalloc(sizeof(*obj
), GFP_KERNEL
);
3698 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
3703 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
3704 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
3705 /* 965gm cannot relocate objects above 4GiB. */
3706 mask
&= ~__GFP_HIGHMEM
;
3707 mask
|= __GFP_DMA32
;
3710 mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
3711 mapping_set_gfp_mask(mapping
, mask
);
3713 i915_gem_object_init(obj
, &i915_gem_object_ops
);
3715 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3716 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3719 /* On some devices, we can have the GPU use the LLC (the CPU
3720 * cache) for about a 10% performance improvement
3721 * compared to uncached. Graphics requests other than
3722 * display scanout are coherent with the CPU in
3723 * accessing this cache. This means in this mode we
3724 * don't need to clflush on the CPU side, and on the
3725 * GPU side we only need to flush internal caches to
3726 * get data visible to the CPU.
3728 * However, we maintain the display planes as UC, and so
3729 * need to rebind when first used as such.
3731 obj
->cache_level
= I915_CACHE_LLC
;
3733 obj
->cache_level
= I915_CACHE_NONE
;
3738 int i915_gem_init_object(struct drm_gem_object
*obj
)
3745 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
3747 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
3748 struct drm_device
*dev
= obj
->base
.dev
;
3749 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3751 trace_i915_gem_object_destroy(obj
);
3754 i915_gem_detach_phys_object(dev
, obj
);
3757 if (WARN_ON(i915_gem_object_unbind(obj
) == -ERESTARTSYS
)) {
3758 bool was_interruptible
;
3760 was_interruptible
= dev_priv
->mm
.interruptible
;
3761 dev_priv
->mm
.interruptible
= false;
3763 WARN_ON(i915_gem_object_unbind(obj
));
3765 dev_priv
->mm
.interruptible
= was_interruptible
;
3768 obj
->pages_pin_count
= 0;
3769 i915_gem_object_put_pages(obj
);
3770 i915_gem_object_free_mmap_offset(obj
);
3774 if (obj
->base
.import_attach
)
3775 drm_prime_gem_destroy(&obj
->base
, NULL
);
3777 drm_gem_object_release(&obj
->base
);
3778 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
3785 i915_gem_idle(struct drm_device
*dev
)
3787 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3790 mutex_lock(&dev
->struct_mutex
);
3792 if (dev_priv
->mm
.suspended
) {
3793 mutex_unlock(&dev
->struct_mutex
);
3797 ret
= i915_gpu_idle(dev
);
3799 mutex_unlock(&dev
->struct_mutex
);
3802 i915_gem_retire_requests(dev
);
3804 /* Under UMS, be paranoid and evict. */
3805 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
3806 i915_gem_evict_everything(dev
);
3808 i915_gem_reset_fences(dev
);
3810 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3811 * We need to replace this with a semaphore, or something.
3812 * And not confound mm.suspended!
3814 dev_priv
->mm
.suspended
= 1;
3815 del_timer_sync(&dev_priv
->hangcheck_timer
);
3817 i915_kernel_lost_context(dev
);
3818 i915_gem_cleanup_ringbuffer(dev
);
3820 mutex_unlock(&dev
->struct_mutex
);
3822 /* Cancel the retire work handler, which should be idle now. */
3823 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
3828 void i915_gem_l3_remap(struct drm_device
*dev
)
3830 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3834 if (!IS_IVYBRIDGE(dev
))
3837 if (!dev_priv
->l3_parity
.remap_info
)
3840 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
3841 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
3842 POSTING_READ(GEN7_MISCCPCTL
);
3844 for (i
= 0; i
< GEN7_L3LOG_SIZE
; i
+= 4) {
3845 u32 remap
= I915_READ(GEN7_L3LOG_BASE
+ i
);
3846 if (remap
&& remap
!= dev_priv
->l3_parity
.remap_info
[i
/4])
3847 DRM_DEBUG("0x%x was already programmed to %x\n",
3848 GEN7_L3LOG_BASE
+ i
, remap
);
3849 if (remap
&& !dev_priv
->l3_parity
.remap_info
[i
/4])
3850 DRM_DEBUG_DRIVER("Clearing remapped register\n");
3851 I915_WRITE(GEN7_L3LOG_BASE
+ i
, dev_priv
->l3_parity
.remap_info
[i
/4]);
3854 /* Make sure all the writes land before disabling dop clock gating */
3855 POSTING_READ(GEN7_L3LOG_BASE
);
3857 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
3860 void i915_gem_init_swizzling(struct drm_device
*dev
)
3862 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3864 if (INTEL_INFO(dev
)->gen
< 5 ||
3865 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
3868 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
3869 DISP_TILE_SURFACE_SWIZZLING
);
3874 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
3876 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
3878 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
3882 intel_enable_blt(struct drm_device
*dev
)
3887 /* The blitter was dysfunctional on early prototypes */
3888 if (IS_GEN6(dev
) && dev
->pdev
->revision
< 8) {
3889 DRM_INFO("BLT not supported on this pre-production hardware;"
3890 " graphics performance will be degraded.\n");
3898 i915_gem_init_hw(struct drm_device
*dev
)
3900 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3903 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
3906 if (IS_HASWELL(dev
) && (I915_READ(0x120010) == 1))
3907 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
3909 i915_gem_l3_remap(dev
);
3911 i915_gem_init_swizzling(dev
);
3913 ret
= intel_init_render_ring_buffer(dev
);
3918 ret
= intel_init_bsd_ring_buffer(dev
);
3920 goto cleanup_render_ring
;
3923 if (intel_enable_blt(dev
)) {
3924 ret
= intel_init_blt_ring_buffer(dev
);
3926 goto cleanup_bsd_ring
;
3929 dev_priv
->next_seqno
= 1;
3932 * XXX: There was some w/a described somewhere suggesting loading
3933 * contexts before PPGTT.
3935 i915_gem_context_init(dev
);
3936 i915_gem_init_ppgtt(dev
);
3941 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
3942 cleanup_render_ring
:
3943 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
3948 intel_enable_ppgtt(struct drm_device
*dev
)
3950 if (i915_enable_ppgtt
>= 0)
3951 return i915_enable_ppgtt
;
3953 #ifdef CONFIG_INTEL_IOMMU
3954 /* Disable ppgtt on SNB if VT-d is on. */
3955 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
)
3962 int i915_gem_init(struct drm_device
*dev
)
3964 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3965 unsigned long gtt_size
, mappable_size
;
3968 gtt_size
= dev_priv
->mm
.gtt
->gtt_total_entries
<< PAGE_SHIFT
;
3969 mappable_size
= dev_priv
->mm
.gtt
->gtt_mappable_entries
<< PAGE_SHIFT
;
3971 mutex_lock(&dev
->struct_mutex
);
3972 if (intel_enable_ppgtt(dev
) && HAS_ALIASING_PPGTT(dev
)) {
3973 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
3974 * aperture accordingly when using aliasing ppgtt. */
3975 gtt_size
-= I915_PPGTT_PD_ENTRIES
*PAGE_SIZE
;
3977 i915_gem_init_global_gtt(dev
, 0, mappable_size
, gtt_size
);
3979 ret
= i915_gem_init_aliasing_ppgtt(dev
);
3981 mutex_unlock(&dev
->struct_mutex
);
3985 /* Let GEM Manage all of the aperture.
3987 * However, leave one page at the end still bound to the scratch
3988 * page. There are a number of places where the hardware
3989 * apparently prefetches past the end of the object, and we've
3990 * seen multiple hangs with the GPU head pointer stuck in a
3991 * batchbuffer bound at the last page of the aperture. One page
3992 * should be enough to keep any prefetching inside of the
3995 i915_gem_init_global_gtt(dev
, 0, mappable_size
,
3999 ret
= i915_gem_init_hw(dev
);
4000 mutex_unlock(&dev
->struct_mutex
);
4002 i915_gem_cleanup_aliasing_ppgtt(dev
);
4006 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4007 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4008 dev_priv
->dri1
.allow_batchbuffer
= 1;
4013 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4015 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4016 struct intel_ring_buffer
*ring
;
4019 for_each_ring(ring
, dev_priv
, i
)
4020 intel_cleanup_ring_buffer(ring
);
4024 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4025 struct drm_file
*file_priv
)
4027 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4030 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4033 if (atomic_read(&dev_priv
->mm
.wedged
)) {
4034 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4035 atomic_set(&dev_priv
->mm
.wedged
, 0);
4038 mutex_lock(&dev
->struct_mutex
);
4039 dev_priv
->mm
.suspended
= 0;
4041 ret
= i915_gem_init_hw(dev
);
4043 mutex_unlock(&dev
->struct_mutex
);
4047 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
4048 mutex_unlock(&dev
->struct_mutex
);
4050 ret
= drm_irq_install(dev
);
4052 goto cleanup_ringbuffer
;
4057 mutex_lock(&dev
->struct_mutex
);
4058 i915_gem_cleanup_ringbuffer(dev
);
4059 dev_priv
->mm
.suspended
= 1;
4060 mutex_unlock(&dev
->struct_mutex
);
4066 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4067 struct drm_file
*file_priv
)
4069 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4072 drm_irq_uninstall(dev
);
4073 return i915_gem_idle(dev
);
4077 i915_gem_lastclose(struct drm_device
*dev
)
4081 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4084 ret
= i915_gem_idle(dev
);
4086 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4090 init_ring_lists(struct intel_ring_buffer
*ring
)
4092 INIT_LIST_HEAD(&ring
->active_list
);
4093 INIT_LIST_HEAD(&ring
->request_list
);
4097 i915_gem_load(struct drm_device
*dev
)
4100 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4102 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
4103 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4104 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
4105 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
4106 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4107 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
4108 init_ring_lists(&dev_priv
->ring
[i
]);
4109 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
4110 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4111 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4112 i915_gem_retire_work_handler
);
4113 init_completion(&dev_priv
->error_completion
);
4115 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4117 I915_WRITE(MI_ARB_STATE
,
4118 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
4121 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
4123 /* Old X drivers will take 0-2 for front, back, depth buffers */
4124 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4125 dev_priv
->fence_reg_start
= 3;
4127 if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4128 dev_priv
->num_fence_regs
= 16;
4130 dev_priv
->num_fence_regs
= 8;
4132 /* Initialize fence registers to zero */
4133 i915_gem_reset_fences(dev
);
4135 i915_gem_detect_bit_6_swizzle(dev
);
4136 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4138 dev_priv
->mm
.interruptible
= true;
4140 dev_priv
->mm
.inactive_shrinker
.shrink
= i915_gem_inactive_shrink
;
4141 dev_priv
->mm
.inactive_shrinker
.seeks
= DEFAULT_SEEKS
;
4142 register_shrinker(&dev_priv
->mm
.inactive_shrinker
);
4146 * Create a physically contiguous memory object for this object
4147 * e.g. for cursor + overlay regs
4149 static int i915_gem_init_phys_object(struct drm_device
*dev
,
4150 int id
, int size
, int align
)
4152 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4153 struct drm_i915_gem_phys_object
*phys_obj
;
4156 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4159 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4165 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
4166 if (!phys_obj
->handle
) {
4171 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4174 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4182 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4184 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4185 struct drm_i915_gem_phys_object
*phys_obj
;
4187 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4190 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4191 if (phys_obj
->cur_obj
) {
4192 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4196 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4198 drm_pci_free(dev
, phys_obj
->handle
);
4200 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4203 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4207 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4208 i915_gem_free_phys_object(dev
, i
);
4211 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4212 struct drm_i915_gem_object
*obj
)
4214 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
4221 vaddr
= obj
->phys_obj
->handle
->vaddr
;
4223 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4224 for (i
= 0; i
< page_count
; i
++) {
4225 struct page
*page
= shmem_read_mapping_page(mapping
, i
);
4226 if (!IS_ERR(page
)) {
4227 char *dst
= kmap_atomic(page
);
4228 memcpy(dst
, vaddr
+ i
*PAGE_SIZE
, PAGE_SIZE
);
4231 drm_clflush_pages(&page
, 1);
4233 set_page_dirty(page
);
4234 mark_page_accessed(page
);
4235 page_cache_release(page
);
4238 i915_gem_chipset_flush(dev
);
4240 obj
->phys_obj
->cur_obj
= NULL
;
4241 obj
->phys_obj
= NULL
;
4245 i915_gem_attach_phys_object(struct drm_device
*dev
,
4246 struct drm_i915_gem_object
*obj
,
4250 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
4251 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4256 if (id
> I915_MAX_PHYS_OBJECT
)
4259 if (obj
->phys_obj
) {
4260 if (obj
->phys_obj
->id
== id
)
4262 i915_gem_detach_phys_object(dev
, obj
);
4265 /* create a new object */
4266 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4267 ret
= i915_gem_init_phys_object(dev
, id
,
4268 obj
->base
.size
, align
);
4270 DRM_ERROR("failed to init phys object %d size: %zu\n",
4271 id
, obj
->base
.size
);
4276 /* bind to the object */
4277 obj
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4278 obj
->phys_obj
->cur_obj
= obj
;
4280 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4282 for (i
= 0; i
< page_count
; i
++) {
4286 page
= shmem_read_mapping_page(mapping
, i
);
4288 return PTR_ERR(page
);
4290 src
= kmap_atomic(page
);
4291 dst
= obj
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4292 memcpy(dst
, src
, PAGE_SIZE
);
4295 mark_page_accessed(page
);
4296 page_cache_release(page
);
4303 i915_gem_phys_pwrite(struct drm_device
*dev
,
4304 struct drm_i915_gem_object
*obj
,
4305 struct drm_i915_gem_pwrite
*args
,
4306 struct drm_file
*file_priv
)
4308 void *vaddr
= obj
->phys_obj
->handle
->vaddr
+ args
->offset
;
4309 char __user
*user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
4311 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
4312 unsigned long unwritten
;
4314 /* The physical object once assigned is fixed for the lifetime
4315 * of the obj, so we can safely drop the lock and continue
4318 mutex_unlock(&dev
->struct_mutex
);
4319 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
4320 mutex_lock(&dev
->struct_mutex
);
4325 i915_gem_chipset_flush(dev
);
4329 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
4331 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4333 /* Clean up our request list when the client is going away, so that
4334 * later retire_requests won't dereference our soon-to-be-gone
4337 spin_lock(&file_priv
->mm
.lock
);
4338 while (!list_empty(&file_priv
->mm
.request_list
)) {
4339 struct drm_i915_gem_request
*request
;
4341 request
= list_first_entry(&file_priv
->mm
.request_list
,
4342 struct drm_i915_gem_request
,
4344 list_del(&request
->client_list
);
4345 request
->file_priv
= NULL
;
4347 spin_unlock(&file_priv
->mm
.lock
);
4350 static bool mutex_is_locked_by(struct mutex
*mutex
, struct task_struct
*task
)
4352 if (!mutex_is_locked(mutex
))
4355 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4356 return mutex
->owner
== task
;
4358 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4364 i915_gem_inactive_shrink(struct shrinker
*shrinker
, struct shrink_control
*sc
)
4366 struct drm_i915_private
*dev_priv
=
4367 container_of(shrinker
,
4368 struct drm_i915_private
,
4369 mm
.inactive_shrinker
);
4370 struct drm_device
*dev
= dev_priv
->dev
;
4371 struct drm_i915_gem_object
*obj
;
4372 int nr_to_scan
= sc
->nr_to_scan
;
4376 if (!mutex_trylock(&dev
->struct_mutex
)) {
4377 if (!mutex_is_locked_by(&dev
->struct_mutex
, current
))
4384 nr_to_scan
-= i915_gem_purge(dev_priv
, nr_to_scan
);
4386 i915_gem_shrink_all(dev_priv
);
4390 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, gtt_list
)
4391 if (obj
->pages_pin_count
== 0)
4392 cnt
+= obj
->base
.size
>> PAGE_SHIFT
;
4393 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, gtt_list
)
4394 if (obj
->pin_count
== 0 && obj
->pages_pin_count
== 0)
4395 cnt
+= obj
->base
.size
>> PAGE_SHIFT
;
4398 mutex_unlock(&dev
->struct_mutex
);