1 /* linux/arch/arm/plat-s3c64xx/clock.c
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * S3C64XX Base clock support
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/ioport.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
23 #include <mach/hardware.h>
26 #include <mach/regs-sys.h>
27 #include <mach/regs-clock.h>
30 #include <plat/devs.h>
31 #include <plat/cpu-freq.h>
32 #include <plat/clock.h>
33 #include <plat/clock-clksrc.h>
36 /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
37 * ext_xtal_mux for want of an actual name from the manual.
40 static struct clk clk_ext_xtal_mux
= {
44 #define clk_fin_apll clk_ext_xtal_mux
45 #define clk_fin_mpll clk_ext_xtal_mux
46 #define clk_fin_epll clk_ext_xtal_mux
48 #define clk_fout_mpll clk_mpll
49 #define clk_fout_epll clk_epll
56 struct clk clk_27m
= {
61 static int clk_48m_ctrl(struct clk
*clk
, int enable
)
66 /* can't rely on clock lock, this register has other usages */
67 local_irq_save(flags
);
69 val
= __raw_readl(S3C64XX_OTHERS
);
71 val
|= S3C64XX_OTHERS_USBMASK
;
73 val
&= ~S3C64XX_OTHERS_USBMASK
;
75 __raw_writel(val
, S3C64XX_OTHERS
);
76 local_irq_restore(flags
);
81 struct clk clk_48m
= {
84 .enable
= clk_48m_ctrl
,
87 struct clk clk_xusbxti
= {
92 static int inline s3c64xx_gate(void __iomem
*reg
,
96 unsigned int ctrlbit
= clk
->ctrlbit
;
99 con
= __raw_readl(reg
);
106 __raw_writel(con
, reg
);
110 static int s3c64xx_pclk_ctrl(struct clk
*clk
, int enable
)
112 return s3c64xx_gate(S3C_PCLK_GATE
, clk
, enable
);
115 static int s3c64xx_hclk_ctrl(struct clk
*clk
, int enable
)
117 return s3c64xx_gate(S3C_HCLK_GATE
, clk
, enable
);
120 int s3c64xx_sclk_ctrl(struct clk
*clk
, int enable
)
122 return s3c64xx_gate(S3C_SCLK_GATE
, clk
, enable
);
125 static struct clk init_clocks_off
[] = {
132 .enable
= s3c64xx_pclk_ctrl
,
133 .ctrlbit
= S3C_CLKCON_PCLK_RTC
,
137 .enable
= s3c64xx_pclk_ctrl
,
138 .ctrlbit
= S3C_CLKCON_PCLK_TSADC
,
142 .enable
= s3c64xx_pclk_ctrl
,
143 .ctrlbit
= S3C_CLKCON_PCLK_IIC
,
146 .devname
= "s3c2440-i2c.1",
148 .enable
= s3c64xx_pclk_ctrl
,
149 .ctrlbit
= S3C6410_CLKCON_PCLK_I2C1
,
152 .devname
= "samsung-i2s.0",
154 .enable
= s3c64xx_pclk_ctrl
,
155 .ctrlbit
= S3C_CLKCON_PCLK_IIS0
,
158 .devname
= "samsung-i2s.1",
160 .enable
= s3c64xx_pclk_ctrl
,
161 .ctrlbit
= S3C_CLKCON_PCLK_IIS1
,
163 #ifdef CONFIG_CPU_S3C6410
166 .enable
= s3c64xx_pclk_ctrl
,
167 .ctrlbit
= S3C6410_CLKCON_PCLK_IIS2
,
172 .enable
= s3c64xx_pclk_ctrl
,
173 .ctrlbit
= S3C_CLKCON_PCLK_KEYPAD
,
176 .devname
= "s3c64xx-spi.0",
178 .enable
= s3c64xx_pclk_ctrl
,
179 .ctrlbit
= S3C_CLKCON_PCLK_SPI0
,
182 .devname
= "s3c64xx-spi.1",
184 .enable
= s3c64xx_pclk_ctrl
,
185 .ctrlbit
= S3C_CLKCON_PCLK_SPI1
,
188 .devname
= "s3c64xx-spi.0",
190 .enable
= s3c64xx_sclk_ctrl
,
191 .ctrlbit
= S3C_CLKCON_SCLK_SPI0_48
,
194 .devname
= "s3c64xx-spi.1",
196 .enable
= s3c64xx_sclk_ctrl
,
197 .ctrlbit
= S3C_CLKCON_SCLK_SPI1_48
,
200 .devname
= "s3c-sdhci.0",
202 .enable
= s3c64xx_sclk_ctrl
,
203 .ctrlbit
= S3C_CLKCON_SCLK_MMC0_48
,
206 .devname
= "s3c-sdhci.1",
208 .enable
= s3c64xx_sclk_ctrl
,
209 .ctrlbit
= S3C_CLKCON_SCLK_MMC1_48
,
212 .devname
= "s3c-sdhci.2",
214 .enable
= s3c64xx_sclk_ctrl
,
215 .ctrlbit
= S3C_CLKCON_SCLK_MMC2_48
,
219 .enable
= s3c64xx_hclk_ctrl
,
220 .ctrlbit
= S3C_CLKCON_HCLK_DMA0
,
224 .enable
= s3c64xx_hclk_ctrl
,
225 .ctrlbit
= S3C_CLKCON_HCLK_DMA1
,
229 static struct clk init_clocks
[] = {
233 .enable
= s3c64xx_hclk_ctrl
,
234 .ctrlbit
= S3C_CLKCON_HCLK_LCD
,
238 .enable
= s3c64xx_pclk_ctrl
,
239 .ctrlbit
= S3C_CLKCON_PCLK_GPIO
,
243 .enable
= s3c64xx_hclk_ctrl
,
244 .ctrlbit
= S3C_CLKCON_HCLK_UHOST
,
248 .enable
= s3c64xx_hclk_ctrl
,
249 .ctrlbit
= S3C_CLKCON_HCLK_USB
,
253 .enable
= s3c64xx_pclk_ctrl
,
254 .ctrlbit
= S3C_CLKCON_PCLK_PWM
,
257 .devname
= "s3c6400-uart.0",
259 .enable
= s3c64xx_pclk_ctrl
,
260 .ctrlbit
= S3C_CLKCON_PCLK_UART0
,
263 .devname
= "s3c6400-uart.1",
265 .enable
= s3c64xx_pclk_ctrl
,
266 .ctrlbit
= S3C_CLKCON_PCLK_UART1
,
269 .devname
= "s3c6400-uart.2",
271 .enable
= s3c64xx_pclk_ctrl
,
272 .ctrlbit
= S3C_CLKCON_PCLK_UART2
,
275 .devname
= "s3c6400-uart.3",
277 .enable
= s3c64xx_pclk_ctrl
,
278 .ctrlbit
= S3C_CLKCON_PCLK_UART3
,
282 .ctrlbit
= S3C_CLKCON_PCLK_WDT
,
286 .ctrlbit
= S3C_CLKCON_PCLK_AC97
,
290 .enable
= s3c64xx_hclk_ctrl
,
291 .ctrlbit
= S3C_CLKCON_HCLK_IHOST
,
295 static struct clk clk_hsmmc0
= {
297 .devname
= "s3c-sdhci.0",
299 .enable
= s3c64xx_hclk_ctrl
,
300 .ctrlbit
= S3C_CLKCON_HCLK_HSMMC0
,
303 static struct clk clk_hsmmc1
= {
305 .devname
= "s3c-sdhci.1",
307 .enable
= s3c64xx_hclk_ctrl
,
308 .ctrlbit
= S3C_CLKCON_HCLK_HSMMC1
,
311 static struct clk clk_hsmmc2
= {
313 .devname
= "s3c-sdhci.2",
315 .enable
= s3c64xx_hclk_ctrl
,
316 .ctrlbit
= S3C_CLKCON_HCLK_HSMMC2
,
319 static struct clk clk_fout_apll
= {
323 static struct clk
*clk_src_apll_list
[] = {
325 [1] = &clk_fout_apll
,
328 static struct clksrc_sources clk_src_apll
= {
329 .sources
= clk_src_apll_list
,
330 .nr_sources
= ARRAY_SIZE(clk_src_apll_list
),
333 static struct clksrc_clk clk_mout_apll
= {
337 .reg_src
= { .reg
= S3C_CLK_SRC
, .shift
= 0, .size
= 1 },
338 .sources
= &clk_src_apll
,
341 static struct clk
*clk_src_epll_list
[] = {
343 [1] = &clk_fout_epll
,
346 static struct clksrc_sources clk_src_epll
= {
347 .sources
= clk_src_epll_list
,
348 .nr_sources
= ARRAY_SIZE(clk_src_epll_list
),
351 static struct clksrc_clk clk_mout_epll
= {
355 .reg_src
= { .reg
= S3C_CLK_SRC
, .shift
= 2, .size
= 1 },
356 .sources
= &clk_src_epll
,
359 static struct clk
*clk_src_mpll_list
[] = {
361 [1] = &clk_fout_mpll
,
364 static struct clksrc_sources clk_src_mpll
= {
365 .sources
= clk_src_mpll_list
,
366 .nr_sources
= ARRAY_SIZE(clk_src_mpll_list
),
369 static struct clksrc_clk clk_mout_mpll
= {
373 .reg_src
= { .reg
= S3C_CLK_SRC
, .shift
= 1, .size
= 1 },
374 .sources
= &clk_src_mpll
,
377 static unsigned int armclk_mask
;
379 static unsigned long s3c64xx_clk_arm_get_rate(struct clk
*clk
)
381 unsigned long rate
= clk_get_rate(clk
->parent
);
384 /* divisor mask starts at bit0, so no need to shift */
385 clkdiv
= __raw_readl(S3C_CLK_DIV0
) & armclk_mask
;
387 return rate
/ (clkdiv
+ 1);
390 static unsigned long s3c64xx_clk_arm_round_rate(struct clk
*clk
,
393 unsigned long parent
= clk_get_rate(clk
->parent
);
399 div
= (parent
/ rate
) - 1;
400 if (div
> armclk_mask
)
403 return parent
/ (div
+ 1);
406 static int s3c64xx_clk_arm_set_rate(struct clk
*clk
, unsigned long rate
)
408 unsigned long parent
= clk_get_rate(clk
->parent
);
412 if (rate
< parent
/ (armclk_mask
+ 1))
415 rate
= clk_round_rate(clk
, rate
);
416 div
= clk_get_rate(clk
->parent
) / rate
;
418 val
= __raw_readl(S3C_CLK_DIV0
);
421 __raw_writel(val
, S3C_CLK_DIV0
);
427 static struct clk clk_arm
= {
429 .parent
= &clk_mout_apll
.clk
,
430 .ops
= &(struct clk_ops
) {
431 .get_rate
= s3c64xx_clk_arm_get_rate
,
432 .set_rate
= s3c64xx_clk_arm_set_rate
,
433 .round_rate
= s3c64xx_clk_arm_round_rate
,
437 static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk
*clk
)
439 unsigned long rate
= clk_get_rate(clk
->parent
);
441 printk(KERN_DEBUG
"%s: parent is %ld\n", __func__
, rate
);
443 if (__raw_readl(S3C_CLK_DIV0
) & S3C6400_CLKDIV0_MPLL_MASK
)
449 static struct clk_ops clk_dout_ops
= {
450 .get_rate
= s3c64xx_clk_doutmpll_get_rate
,
453 static struct clk clk_dout_mpll
= {
455 .parent
= &clk_mout_mpll
.clk
,
456 .ops
= &clk_dout_ops
,
459 static struct clk
*clkset_spi_mmc_list
[] = {
466 static struct clksrc_sources clkset_spi_mmc
= {
467 .sources
= clkset_spi_mmc_list
,
468 .nr_sources
= ARRAY_SIZE(clkset_spi_mmc_list
),
471 static struct clk
*clkset_irda_list
[] = {
478 static struct clksrc_sources clkset_irda
= {
479 .sources
= clkset_irda_list
,
480 .nr_sources
= ARRAY_SIZE(clkset_irda_list
),
483 static struct clk
*clkset_uart_list
[] = {
490 static struct clksrc_sources clkset_uart
= {
491 .sources
= clkset_uart_list
,
492 .nr_sources
= ARRAY_SIZE(clkset_uart_list
),
495 static struct clk
*clkset_uhost_list
[] = {
502 static struct clksrc_sources clkset_uhost
= {
503 .sources
= clkset_uhost_list
,
504 .nr_sources
= ARRAY_SIZE(clkset_uhost_list
),
507 /* The peripheral clocks are all controlled via clocksource followed
508 * by an optional divider and gate stage. We currently roll this into
509 * one clock which hides the intermediate clock from the mux.
511 * Note, the JPEG clock can only be an even divider...
513 * The scaler and LCD clocks depend on the S3C64XX version, and also
514 * have a common parent divisor so are not included here.
517 /* clocks that feed other parts of the clock source tree */
519 static struct clk clk_iis_cd0
= {
520 .name
= "iis_cdclk0",
523 static struct clk clk_iis_cd1
= {
524 .name
= "iis_cdclk1",
527 static struct clk clk_iisv4_cd
= {
528 .name
= "iis_cdclk_v4",
531 static struct clk clk_pcm_cd
= {
535 static struct clk
*clkset_audio0_list
[] = {
536 [0] = &clk_mout_epll
.clk
,
537 [1] = &clk_dout_mpll
,
543 static struct clksrc_sources clkset_audio0
= {
544 .sources
= clkset_audio0_list
,
545 .nr_sources
= ARRAY_SIZE(clkset_audio0_list
),
548 static struct clk
*clkset_audio1_list
[] = {
549 [0] = &clk_mout_epll
.clk
,
550 [1] = &clk_dout_mpll
,
556 static struct clksrc_sources clkset_audio1
= {
557 .sources
= clkset_audio1_list
,
558 .nr_sources
= ARRAY_SIZE(clkset_audio1_list
),
561 static struct clk
*clkset_audio2_list
[] = {
562 [0] = &clk_mout_epll
.clk
,
563 [1] = &clk_dout_mpll
,
569 static struct clksrc_sources clkset_audio2
= {
570 .sources
= clkset_audio2_list
,
571 .nr_sources
= ARRAY_SIZE(clkset_audio2_list
),
574 static struct clk
*clkset_camif_list
[] = {
578 static struct clksrc_sources clkset_camif
= {
579 .sources
= clkset_camif_list
,
580 .nr_sources
= ARRAY_SIZE(clkset_camif_list
),
583 static struct clksrc_clk clksrcs
[] = {
586 .name
= "usb-bus-host",
587 .ctrlbit
= S3C_CLKCON_SCLK_UHOST
,
588 .enable
= s3c64xx_sclk_ctrl
,
590 .reg_src
= { .reg
= S3C_CLK_SRC
, .shift
= 5, .size
= 2 },
591 .reg_div
= { .reg
= S3C_CLK_DIV1
, .shift
= 20, .size
= 4 },
592 .sources
= &clkset_uhost
,
596 .devname
= "s3c64xx-spi.0",
597 .ctrlbit
= S3C_CLKCON_SCLK_SPI0
,
598 .enable
= s3c64xx_sclk_ctrl
,
600 .reg_src
= { .reg
= S3C_CLK_SRC
, .shift
= 14, .size
= 2 },
601 .reg_div
= { .reg
= S3C_CLK_DIV2
, .shift
= 0, .size
= 4 },
602 .sources
= &clkset_spi_mmc
,
606 .devname
= "s3c64xx-spi.1",
607 .enable
= s3c64xx_sclk_ctrl
,
609 .reg_src
= { .reg
= S3C_CLK_SRC
, .shift
= 16, .size
= 2 },
610 .reg_div
= { .reg
= S3C_CLK_DIV2
, .shift
= 4, .size
= 4 },
611 .sources
= &clkset_spi_mmc
,
615 .devname
= "samsung-i2s.0",
616 .ctrlbit
= S3C_CLKCON_SCLK_AUDIO0
,
617 .enable
= s3c64xx_sclk_ctrl
,
619 .reg_src
= { .reg
= S3C_CLK_SRC
, .shift
= 7, .size
= 3 },
620 .reg_div
= { .reg
= S3C_CLK_DIV2
, .shift
= 8, .size
= 4 },
621 .sources
= &clkset_audio0
,
625 .devname
= "samsung-i2s.1",
626 .ctrlbit
= S3C_CLKCON_SCLK_AUDIO1
,
627 .enable
= s3c64xx_sclk_ctrl
,
629 .reg_src
= { .reg
= S3C_CLK_SRC
, .shift
= 10, .size
= 3 },
630 .reg_div
= { .reg
= S3C_CLK_DIV2
, .shift
= 12, .size
= 4 },
631 .sources
= &clkset_audio1
,
635 .devname
= "samsung-i2s.2",
636 .ctrlbit
= S3C6410_CLKCON_SCLK_AUDIO2
,
637 .enable
= s3c64xx_sclk_ctrl
,
639 .reg_src
= { .reg
= S3C6410_CLK_SRC2
, .shift
= 0, .size
= 3 },
640 .reg_div
= { .reg
= S3C_CLK_DIV2
, .shift
= 24, .size
= 4 },
641 .sources
= &clkset_audio2
,
645 .ctrlbit
= S3C_CLKCON_SCLK_IRDA
,
646 .enable
= s3c64xx_sclk_ctrl
,
648 .reg_src
= { .reg
= S3C_CLK_SRC
, .shift
= 24, .size
= 2 },
649 .reg_div
= { .reg
= S3C_CLK_DIV2
, .shift
= 20, .size
= 4 },
650 .sources
= &clkset_irda
,
654 .ctrlbit
= S3C_CLKCON_SCLK_CAM
,
655 .enable
= s3c64xx_sclk_ctrl
,
657 .reg_div
= { .reg
= S3C_CLK_DIV0
, .shift
= 20, .size
= 4 },
658 .reg_src
= { .reg
= NULL
, .shift
= 0, .size
= 0 },
659 .sources
= &clkset_camif
,
663 /* Where does UCLK0 come from? */
664 static struct clksrc_clk clk_sclk_uclk
= {
667 .ctrlbit
= S3C_CLKCON_SCLK_UART
,
668 .enable
= s3c64xx_sclk_ctrl
,
670 .reg_src
= { .reg
= S3C_CLK_SRC
, .shift
= 13, .size
= 1 },
671 .reg_div
= { .reg
= S3C_CLK_DIV2
, .shift
= 16, .size
= 4 },
672 .sources
= &clkset_uart
,
675 static struct clksrc_clk clk_sclk_mmc0
= {
678 .devname
= "s3c-sdhci.0",
679 .ctrlbit
= S3C_CLKCON_SCLK_MMC0
,
680 .enable
= s3c64xx_sclk_ctrl
,
682 .reg_src
= { .reg
= S3C_CLK_SRC
, .shift
= 18, .size
= 2 },
683 .reg_div
= { .reg
= S3C_CLK_DIV1
, .shift
= 0, .size
= 4 },
684 .sources
= &clkset_spi_mmc
,
687 static struct clksrc_clk clk_sclk_mmc1
= {
690 .devname
= "s3c-sdhci.1",
691 .ctrlbit
= S3C_CLKCON_SCLK_MMC1
,
692 .enable
= s3c64xx_sclk_ctrl
,
694 .reg_src
= { .reg
= S3C_CLK_SRC
, .shift
= 20, .size
= 2 },
695 .reg_div
= { .reg
= S3C_CLK_DIV1
, .shift
= 4, .size
= 4 },
696 .sources
= &clkset_spi_mmc
,
699 static struct clksrc_clk clk_sclk_mmc2
= {
702 .devname
= "s3c-sdhci.2",
703 .ctrlbit
= S3C_CLKCON_SCLK_MMC2
,
704 .enable
= s3c64xx_sclk_ctrl
,
706 .reg_src
= { .reg
= S3C_CLK_SRC
, .shift
= 22, .size
= 2 },
707 .reg_div
= { .reg
= S3C_CLK_DIV1
, .shift
= 8, .size
= 4 },
708 .sources
= &clkset_spi_mmc
,
711 /* Clock initialisation code */
713 static struct clksrc_clk
*init_parents
[] = {
719 static struct clksrc_clk
*clksrc_cdev
[] = {
726 static struct clk
*clk_cdev
[] = {
732 static struct clk_lookup s3c64xx_clk_lookup
[] = {
733 CLKDEV_INIT(NULL
, "clk_uart_baud2", &clk_p
),
734 CLKDEV_INIT(NULL
, "clk_uart_baud3", &clk_sclk_uclk
.clk
),
735 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0
),
736 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1
),
737 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2
),
738 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0
.clk
),
739 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1
.clk
),
740 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2
.clk
),
743 #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
745 void __init_or_cpufreq
s3c6400_setup_clocks(void)
747 struct clk
*xtal_clk
;
759 printk(KERN_DEBUG
"%s: registering clocks\n", __func__
);
761 clkdiv0
= __raw_readl(S3C_CLK_DIV0
);
762 printk(KERN_DEBUG
"%s: clkdiv0 = %08x\n", __func__
, clkdiv0
);
764 xtal_clk
= clk_get(NULL
, "xtal");
765 BUG_ON(IS_ERR(xtal_clk
));
767 xtal
= clk_get_rate(xtal_clk
);
770 printk(KERN_DEBUG
"%s: xtal is %ld\n", __func__
, xtal
);
772 /* For now assume the mux always selects the crystal */
773 clk_ext_xtal_mux
.parent
= xtal_clk
;
775 epll
= s3c_get_pll6553x(xtal
, __raw_readl(S3C_EPLL_CON0
),
776 __raw_readl(S3C_EPLL_CON1
));
777 mpll
= s3c6400_get_pll(xtal
, __raw_readl(S3C_MPLL_CON
));
778 apll
= s3c6400_get_pll(xtal
, __raw_readl(S3C_APLL_CON
));
782 printk(KERN_INFO
"S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
785 if(__raw_readl(S3C64XX_OTHERS
) & S3C64XX_OTHERS_SYNCMUXSEL
)
786 /* Synchronous mode */
787 hclk2
= apll
/ GET_DIV(clkdiv0
, S3C6400_CLKDIV0_HCLK2
);
789 /* Asynchronous mode */
790 hclk2
= mpll
/ GET_DIV(clkdiv0
, S3C6400_CLKDIV0_HCLK2
);
792 hclk
= hclk2
/ GET_DIV(clkdiv0
, S3C6400_CLKDIV0_HCLK
);
793 pclk
= hclk2
/ GET_DIV(clkdiv0
, S3C6400_CLKDIV0_PCLK
);
795 printk(KERN_INFO
"S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n",
798 clk_fout_mpll
.rate
= mpll
;
799 clk_fout_epll
.rate
= epll
;
800 clk_fout_apll
.rate
= apll
;
807 for (ptr
= 0; ptr
< ARRAY_SIZE(init_parents
); ptr
++)
808 s3c_set_clksrc(init_parents
[ptr
], true);
810 for (ptr
= 0; ptr
< ARRAY_SIZE(clksrcs
); ptr
++)
811 s3c_set_clksrc(&clksrcs
[ptr
], true);
814 static struct clk
*clks1
[] __initdata
= {
826 static struct clk
*clks
[] __initdata
= {
836 * s3c64xx_register_clocks - register clocks for s3c6400 and s3c6410
837 * @xtal: The rate for the clock crystal feeding the PLLs.
838 * @armclk_divlimit: Divisor mask for ARMCLK.
840 * Register the clocks for the S3C6400 and S3C6410 SoC range, such
841 * as ARMCLK as well as the necessary parent clocks.
843 * This call does not setup the clocks, which is left to the
844 * s3c6400_setup_clocks() call which may be needed by the cpufreq
845 * or resume code to re-set the clocks if the bootloader has changed
848 void __init
s3c64xx_register_clocks(unsigned long xtal
,
849 unsigned armclk_divlimit
)
853 armclk_mask
= armclk_divlimit
;
855 s3c24xx_register_baseclocks(xtal
);
856 s3c24xx_register_clocks(clks
, ARRAY_SIZE(clks
));
858 s3c_register_clocks(init_clocks
, ARRAY_SIZE(init_clocks
));
860 s3c_register_clocks(init_clocks_off
, ARRAY_SIZE(init_clocks_off
));
861 s3c_disable_clocks(init_clocks_off
, ARRAY_SIZE(init_clocks_off
));
863 s3c24xx_register_clocks(clk_cdev
, ARRAY_SIZE(clk_cdev
));
864 for (cnt
= 0; cnt
< ARRAY_SIZE(clk_cdev
); cnt
++)
865 s3c_disable_clocks(clk_cdev
[cnt
], 1);
867 s3c24xx_register_clocks(clks1
, ARRAY_SIZE(clks1
));
868 s3c_register_clksrc(clksrcs
, ARRAY_SIZE(clksrcs
));
869 for (cnt
= 0; cnt
< ARRAY_SIZE(clksrc_cdev
); cnt
++)
870 s3c_register_clksrc(clksrc_cdev
[cnt
], 1);
871 clkdev_add_table(s3c64xx_clk_lookup
, ARRAY_SIZE(s3c64xx_clk_lookup
));