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sfc: Make efx_for_each_channel_rx_queue() more efficient
[linux-2.6/btrfs-unstable.git] / arch / x86 / kvm / x86_emulate.c
blobf2f90468f8b1c90042cc468f77eee4b5b19412ba
1 /******************************************************************************
2 * x86_emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
9 * privileged instructions:
10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22 #ifndef __KERNEL__
23 #include <stdio.h>
24 #include <stdint.h>
25 #include <public/xen.h>
26 #define DPRINTF(_f, _a ...) printf(_f , ## _a)
27 #else
28 #include <linux/kvm_host.h>
29 #define DPRINTF(x...) do {} while (0)
30 #endif
31 #include <linux/module.h>
32 #include <asm/kvm_x86_emulate.h>
33
34 /*
35 * Opcode effective-address decode tables.
36 * Note that we only emulate instructions that have at least one memory
37 * operand (excluding implicit stack references). We assume that stack
38 * references and instruction fetches will never occur in special memory
39 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
40 * not be handled.
41 */
42
43 /* Operand sizes: 8-bit operands or specified/overridden size. */
44 #define ByteOp (1<<0) /* 8-bit operands. */
45 /* Destination operand type. */
46 #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
47 #define DstReg (2<<1) /* Register operand. */
48 #define DstMem (3<<1) /* Memory operand. */
49 #define DstMask (3<<1)
50 /* Source operand type. */
51 #define SrcNone (0<<3) /* No source operand. */
52 #define SrcImplicit (0<<3) /* Source operand is implicit in the opcode. */
53 #define SrcReg (1<<3) /* Register operand. */
54 #define SrcMem (2<<3) /* Memory operand. */
55 #define SrcMem16 (3<<3) /* Memory operand (16-bit). */
56 #define SrcMem32 (4<<3) /* Memory operand (32-bit). */
57 #define SrcImm (5<<3) /* Immediate operand. */
58 #define SrcImmByte (6<<3) /* 8-bit sign-extended immediate operand. */
59 #define SrcMask (7<<3)
60 /* Generic ModRM decode. */
61 #define ModRM (1<<6)
62 /* Destination is only written; never read. */
63 #define Mov (1<<7)
64 #define BitOp (1<<8)
65 #define MemAbs (1<<9) /* Memory operand is absolute displacement */
66 #define String (1<<10) /* String instruction (rep capable) */
67 #define Stack (1<<11) /* Stack instruction (push/pop) */
68 #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
69 #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
70 #define GroupMask 0xff /* Group number stored in bits 0:7 */
71
72 enum {
73 Group1_80, Group1_81, Group1_82, Group1_83,
74 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
75 };
76
77 static u16 opcode_table[256] = {
78 /* 0x00 - 0x07 */
79 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
80 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
81 0, 0, 0, 0,
82 /* 0x08 - 0x0F */
83 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
84 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
85 0, 0, 0, 0,
86 /* 0x10 - 0x17 */
87 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
88 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
89 0, 0, 0, 0,
90 /* 0x18 - 0x1F */
91 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
92 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
93 0, 0, 0, 0,
94 /* 0x20 - 0x27 */
95 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
96 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
97 SrcImmByte, SrcImm, 0, 0,
98 /* 0x28 - 0x2F */
99 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
100 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
101 0, 0, 0, 0,
102 /* 0x30 - 0x37 */
103 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
104 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
105 0, 0, 0, 0,
106 /* 0x38 - 0x3F */
107 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
108 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
109 0, 0, 0, 0,
110 /* 0x40 - 0x47 */
111 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
112 /* 0x48 - 0x4F */
113 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
114 /* 0x50 - 0x57 */
115 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
116 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
117 /* 0x58 - 0x5F */
118 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
119 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
120 /* 0x60 - 0x67 */
121 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
122 0, 0, 0, 0,
123 /* 0x68 - 0x6F */
124 SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0,
125 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
126 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
127 /* 0x70 - 0x77 */
128 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
129 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
130 /* 0x78 - 0x7F */
131 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
132 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
133 /* 0x80 - 0x87 */
134 Group | Group1_80, Group | Group1_81,
135 Group | Group1_82, Group | Group1_83,
136 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
137 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
138 /* 0x88 - 0x8F */
139 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
140 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
141 DstMem | SrcReg | ModRM | Mov, ModRM | DstReg,
142 DstReg | SrcMem | ModRM | Mov, Group | Group1A,
143 /* 0x90 - 0x97 */
144 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
145 /* 0x98 - 0x9F */
146 0, 0, 0, 0, ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
147 /* 0xA0 - 0xA7 */
148 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
149 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
150 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
151 ByteOp | ImplicitOps | String, ImplicitOps | String,
152 /* 0xA8 - 0xAF */
153 0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
154 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
155 ByteOp | ImplicitOps | String, ImplicitOps | String,
156 /* 0xB0 - 0xBF */
157 0, 0, 0, 0, 0, 0, 0, 0,
158 DstReg | SrcImm | Mov, 0, 0, 0, 0, 0, 0, 0,
159 /* 0xC0 - 0xC7 */
160 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
161 0, ImplicitOps | Stack, 0, 0,
162 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
163 /* 0xC8 - 0xCF */
164 0, 0, 0, 0, 0, 0, 0, 0,
165 /* 0xD0 - 0xD7 */
166 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
167 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
168 0, 0, 0, 0,
169 /* 0xD8 - 0xDF */
170 0, 0, 0, 0, 0, 0, 0, 0,
171 /* 0xE0 - 0xE7 */
172 0, 0, 0, 0, 0, 0, 0, 0,
173 /* 0xE8 - 0xEF */
174 ImplicitOps | Stack, SrcImm | ImplicitOps,
175 ImplicitOps, SrcImmByte | ImplicitOps,
176 0, 0, 0, 0,
177 /* 0xF0 - 0xF7 */
178 0, 0, 0, 0,
179 ImplicitOps, ImplicitOps, Group | Group3_Byte, Group | Group3,
180 /* 0xF8 - 0xFF */
181 ImplicitOps, 0, ImplicitOps, ImplicitOps,
182 0, 0, Group | Group4, Group | Group5,
183 };
184
185 static u16 twobyte_table[256] = {
186 /* 0x00 - 0x0F */
187 0, Group | GroupDual | Group7, 0, 0, 0, 0, ImplicitOps, 0,
188 ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
189 /* 0x10 - 0x1F */
190 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
191 /* 0x20 - 0x2F */
192 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
193 0, 0, 0, 0, 0, 0, 0, 0,
194 /* 0x30 - 0x3F */
195 ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
196 /* 0x40 - 0x47 */
197 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
198 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
199 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
200 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
201 /* 0x48 - 0x4F */
202 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
203 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
204 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
205 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
206 /* 0x50 - 0x5F */
207 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
208 /* 0x60 - 0x6F */
209 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
210 /* 0x70 - 0x7F */
211 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
212 /* 0x80 - 0x8F */
213 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
214 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
215 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
216 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
217 /* 0x90 - 0x9F */
218 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
219 /* 0xA0 - 0xA7 */
220 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
221 /* 0xA8 - 0xAF */
222 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, ModRM, 0,
223 /* 0xB0 - 0xB7 */
224 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
225 DstMem | SrcReg | ModRM | BitOp,
226 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
227 DstReg | SrcMem16 | ModRM | Mov,
228 /* 0xB8 - 0xBF */
229 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
230 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
231 DstReg | SrcMem16 | ModRM | Mov,
232 /* 0xC0 - 0xCF */
233 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
234 0, 0, 0, 0, 0, 0, 0, 0,
235 /* 0xD0 - 0xDF */
236 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
237 /* 0xE0 - 0xEF */
238 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
239 /* 0xF0 - 0xFF */
240 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
241 };
242
243 static u16 group_table[] = {
244 [Group1_80*8] =
245 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
246 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
247 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
248 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
249 [Group1_81*8] =
250 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
251 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
252 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
253 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
254 [Group1_82*8] =
255 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
256 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
257 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
258 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
259 [Group1_83*8] =
260 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
261 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
262 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
263 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
264 [Group1A*8] =
265 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
266 [Group3_Byte*8] =
267 ByteOp | SrcImm | DstMem | ModRM, 0,
268 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
269 0, 0, 0, 0,
270 [Group3*8] =
271 DstMem | SrcImm | ModRM | SrcImm, 0,
272 DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
273 0, 0, 0, 0,
274 [Group4*8] =
275 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
276 0, 0, 0, 0, 0, 0,
277 [Group5*8] =
278 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM, 0, 0,
279 SrcMem | ModRM, 0, SrcMem | ModRM | Stack, 0,
280 [Group7*8] =
281 0, 0, ModRM | SrcMem, ModRM | SrcMem,
282 SrcNone | ModRM | DstMem | Mov, 0,
283 SrcMem16 | ModRM | Mov, SrcMem | ModRM | ByteOp,
284 };
285
286 static u16 group2_table[] = {
287 [Group7*8] =
288 SrcNone | ModRM, 0, 0, 0,
289 SrcNone | ModRM | DstMem | Mov, 0,
290 SrcMem16 | ModRM | Mov, 0,
291 };
292
293 /* EFLAGS bit definitions. */
294 #define EFLG_OF (1<<11)
295 #define EFLG_DF (1<<10)
296 #define EFLG_SF (1<<7)
297 #define EFLG_ZF (1<<6)
298 #define EFLG_AF (1<<4)
299 #define EFLG_PF (1<<2)
300 #define EFLG_CF (1<<0)
301
302 /*
303 * Instruction emulation:
304 * Most instructions are emulated directly via a fragment of inline assembly
305 * code. This allows us to save/restore EFLAGS and thus very easily pick up
306 * any modified flags.
307 */
308
309 #if defined(CONFIG_X86_64)
310 #define _LO32 "k" /* force 32-bit operand */
311 #define _STK "%%rsp" /* stack pointer */
312 #elif defined(__i386__)
313 #define _LO32 "" /* force 32-bit operand */
314 #define _STK "%%esp" /* stack pointer */
315 #endif
316
317 /*
318 * These EFLAGS bits are restored from saved value during emulation, and
319 * any changes are written back to the saved value after emulation.
320 */
321 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
322
323 /* Before executing instruction: restore necessary bits in EFLAGS. */
324 #define _PRE_EFLAGS(_sav, _msk, _tmp) \
325 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
326 "movl %"_sav",%"_LO32 _tmp"; " \
327 "push %"_tmp"; " \
328 "push %"_tmp"; " \
329 "movl %"_msk",%"_LO32 _tmp"; " \
330 "andl %"_LO32 _tmp",("_STK"); " \
331 "pushf; " \
332 "notl %"_LO32 _tmp"; " \
333 "andl %"_LO32 _tmp",("_STK"); " \
334 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
335 "pop %"_tmp"; " \
336 "orl %"_LO32 _tmp",("_STK"); " \
337 "popf; " \
338 "pop %"_sav"; "
339
340 /* After executing instruction: write-back necessary bits in EFLAGS. */
341 #define _POST_EFLAGS(_sav, _msk, _tmp) \
342 /* _sav |= EFLAGS & _msk; */ \
343 "pushf; " \
344 "pop %"_tmp"; " \
345 "andl %"_msk",%"_LO32 _tmp"; " \
346 "orl %"_LO32 _tmp",%"_sav"; "
347
348 /* Raw emulation: instruction has two explicit operands. */
349 #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
350 do { \
351 unsigned long _tmp; \
352 \
353 switch ((_dst).bytes) { \
354 case 2: \
355 __asm__ __volatile__ ( \
356 _PRE_EFLAGS("0", "4", "2") \
357 _op"w %"_wx"3,%1; " \
358 _POST_EFLAGS("0", "4", "2") \
359 : "=m" (_eflags), "=m" ((_dst).val), \
360 "=&r" (_tmp) \
361 : _wy ((_src).val), "i" (EFLAGS_MASK)); \
362 break; \
363 case 4: \
364 __asm__ __volatile__ ( \
365 _PRE_EFLAGS("0", "4", "2") \
366 _op"l %"_lx"3,%1; " \
367 _POST_EFLAGS("0", "4", "2") \
368 : "=m" (_eflags), "=m" ((_dst).val), \
369 "=&r" (_tmp) \
370 : _ly ((_src).val), "i" (EFLAGS_MASK)); \
371 break; \
372 case 8: \
373 __emulate_2op_8byte(_op, _src, _dst, \
374 _eflags, _qx, _qy); \
375 break; \
376 } \
377 } while (0)
378
379 #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
380 do { \
381 unsigned long __tmp; \
382 switch ((_dst).bytes) { \
383 case 1: \
384 __asm__ __volatile__ ( \
385 _PRE_EFLAGS("0", "4", "2") \
386 _op"b %"_bx"3,%1; " \
387 _POST_EFLAGS("0", "4", "2") \
388 : "=m" (_eflags), "=m" ((_dst).val), \
389 "=&r" (__tmp) \
390 : _by ((_src).val), "i" (EFLAGS_MASK)); \
391 break; \
392 default: \
393 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
394 _wx, _wy, _lx, _ly, _qx, _qy); \
395 break; \
396 } \
397 } while (0)
398
399 /* Source operand is byte-sized and may be restricted to just %cl. */
400 #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
401 __emulate_2op(_op, _src, _dst, _eflags, \
402 "b", "c", "b", "c", "b", "c", "b", "c")
403
404 /* Source operand is byte, word, long or quad sized. */
405 #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
406 __emulate_2op(_op, _src, _dst, _eflags, \
407 "b", "q", "w", "r", _LO32, "r", "", "r")
408
409 /* Source operand is word, long or quad sized. */
410 #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
411 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
412 "w", "r", _LO32, "r", "", "r")
413
414 /* Instruction has only one explicit operand (no source operand). */
415 #define emulate_1op(_op, _dst, _eflags) \
416 do { \
417 unsigned long _tmp; \
418 \
419 switch ((_dst).bytes) { \
420 case 1: \
421 __asm__ __volatile__ ( \
422 _PRE_EFLAGS("0", "3", "2") \
423 _op"b %1; " \
424 _POST_EFLAGS("0", "3", "2") \
425 : "=m" (_eflags), "=m" ((_dst).val), \
426 "=&r" (_tmp) \
427 : "i" (EFLAGS_MASK)); \
428 break; \
429 case 2: \
430 __asm__ __volatile__ ( \
431 _PRE_EFLAGS("0", "3", "2") \
432 _op"w %1; " \
433 _POST_EFLAGS("0", "3", "2") \
434 : "=m" (_eflags), "=m" ((_dst).val), \
435 "=&r" (_tmp) \
436 : "i" (EFLAGS_MASK)); \
437 break; \
438 case 4: \
439 __asm__ __volatile__ ( \
440 _PRE_EFLAGS("0", "3", "2") \
441 _op"l %1; " \
442 _POST_EFLAGS("0", "3", "2") \
443 : "=m" (_eflags), "=m" ((_dst).val), \
444 "=&r" (_tmp) \
445 : "i" (EFLAGS_MASK)); \
446 break; \
447 case 8: \
448 __emulate_1op_8byte(_op, _dst, _eflags); \
449 break; \
450 } \
451 } while (0)
452
453 /* Emulate an instruction with quadword operands (x86/64 only). */
454 #if defined(CONFIG_X86_64)
455 #define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy) \
456 do { \
457 __asm__ __volatile__ ( \
458 _PRE_EFLAGS("0", "4", "2") \
459 _op"q %"_qx"3,%1; " \
460 _POST_EFLAGS("0", "4", "2") \
461 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
462 : _qy ((_src).val), "i" (EFLAGS_MASK)); \
463 } while (0)
464
465 #define __emulate_1op_8byte(_op, _dst, _eflags) \
466 do { \
467 __asm__ __volatile__ ( \
468 _PRE_EFLAGS("0", "3", "2") \
469 _op"q %1; " \
470 _POST_EFLAGS("0", "3", "2") \
471 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
472 : "i" (EFLAGS_MASK)); \
473 } while (0)
474
475 #elif defined(__i386__)
476 #define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy)
477 #define __emulate_1op_8byte(_op, _dst, _eflags)
478 #endif /* __i386__ */
479
480 /* Fetch next part of the instruction being emulated. */
481 #define insn_fetch(_type, _size, _eip) \
482 ({ unsigned long _x; \
483 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
484 if (rc != 0) \
485 goto done; \
486 (_eip) += (_size); \
487 (_type)_x; \
488 })
489
490 static inline unsigned long ad_mask(struct decode_cache *c)
491 {
492 return (1UL << (c->ad_bytes << 3)) - 1;
493 }
494
495 /* Access/update address held in a register, based on addressing mode. */
496 static inline unsigned long
497 address_mask(struct decode_cache *c, unsigned long reg)
498 {
499 if (c->ad_bytes == sizeof(unsigned long))
500 return reg;
501 else
502 return reg & ad_mask(c);
503 }
504
505 static inline unsigned long
506 register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
507 {
508 return base + address_mask(c, reg);
509 }
510
511 static inline void
512 register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
513 {
514 if (c->ad_bytes == sizeof(unsigned long))
515 *reg += inc;
516 else
517 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
518 }
519
520 static inline void jmp_rel(struct decode_cache *c, int rel)
521 {
522 register_address_increment(c, &c->eip, rel);
523 }
524
525 static void set_seg_override(struct decode_cache *c, int seg)
526 {
527 c->has_seg_override = true;
528 c->seg_override = seg;
529 }
530
531 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
532 {
533 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
534 return 0;
535
536 return kvm_x86_ops->get_segment_base(ctxt->vcpu, seg);
537 }
538
539 static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
540 struct decode_cache *c)
541 {
542 if (!c->has_seg_override)
543 return 0;
544
545 return seg_base(ctxt, c->seg_override);
546 }
547
548 static unsigned long es_base(struct x86_emulate_ctxt *ctxt)
549 {
550 return seg_base(ctxt, VCPU_SREG_ES);
551 }
552
553 static unsigned long ss_base(struct x86_emulate_ctxt *ctxt)
554 {
555 return seg_base(ctxt, VCPU_SREG_SS);
556 }
557
558 static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
559 struct x86_emulate_ops *ops,
560 unsigned long linear, u8 *dest)
561 {
562 struct fetch_cache *fc = &ctxt->decode.fetch;
563 int rc;
564 int size;
565
566 if (linear < fc->start || linear >= fc->end) {
567 size = min(15UL, PAGE_SIZE - offset_in_page(linear));
568 rc = ops->read_std(linear, fc->data, size, ctxt->vcpu);
569 if (rc)
570 return rc;
571 fc->start = linear;
572 fc->end = linear + size;
573 }
574 *dest = fc->data[linear - fc->start];
575 return 0;
576 }
577
578 static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
579 struct x86_emulate_ops *ops,
580 unsigned long eip, void *dest, unsigned size)
581 {
582 int rc = 0;
583
584 eip += ctxt->cs_base;
585 while (size--) {
586 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
587 if (rc)
588 return rc;
589 }
590 return 0;
591 }
592
593 /*
594 * Given the 'reg' portion of a ModRM byte, and a register block, return a
595 * pointer into the block that addresses the relevant register.
596 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
597 */
598 static void *decode_register(u8 modrm_reg, unsigned long *regs,
599 int highbyte_regs)
600 {
601 void *p;
602
603 p = &regs[modrm_reg];
604 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
605 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
606 return p;
607 }
608
609 static int read_descriptor(struct x86_emulate_ctxt *ctxt,
610 struct x86_emulate_ops *ops,
611 void *ptr,
612 u16 *size, unsigned long *address, int op_bytes)
613 {
614 int rc;
615
616 if (op_bytes == 2)
617 op_bytes = 3;
618 *address = 0;
619 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
620 ctxt->vcpu);
621 if (rc)
622 return rc;
623 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
624 ctxt->vcpu);
625 return rc;
626 }
627
628 static int test_cc(unsigned int condition, unsigned int flags)
629 {
630 int rc = 0;
631
632 switch ((condition & 15) >> 1) {
633 case 0: /* o */
634 rc |= (flags & EFLG_OF);
635 break;
636 case 1: /* b/c/nae */
637 rc |= (flags & EFLG_CF);
638 break;
639 case 2: /* z/e */
640 rc |= (flags & EFLG_ZF);
641 break;
642 case 3: /* be/na */
643 rc |= (flags & (EFLG_CF|EFLG_ZF));
644 break;
645 case 4: /* s */
646 rc |= (flags & EFLG_SF);
647 break;
648 case 5: /* p/pe */
649 rc |= (flags & EFLG_PF);
650 break;
651 case 7: /* le/ng */
652 rc |= (flags & EFLG_ZF);
653 /* fall through */
654 case 6: /* l/nge */
655 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
656 break;
657 }
658
659 /* Odd condition identifiers (lsb == 1) have inverted sense. */
660 return (!!rc ^ (condition & 1));
661 }
662
663 static void decode_register_operand(struct operand *op,
664 struct decode_cache *c,
665 int inhibit_bytereg)
666 {
667 unsigned reg = c->modrm_reg;
668 int highbyte_regs = c->rex_prefix == 0;
669
670 if (!(c->d & ModRM))
671 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
672 op->type = OP_REG;
673 if ((c->d & ByteOp) && !inhibit_bytereg) {
674 op->ptr = decode_register(reg, c->regs, highbyte_regs);
675 op->val = *(u8 *)op->ptr;
676 op->bytes = 1;
677 } else {
678 op->ptr = decode_register(reg, c->regs, 0);
679 op->bytes = c->op_bytes;
680 switch (op->bytes) {
681 case 2:
682 op->val = *(u16 *)op->ptr;
683 break;
684 case 4:
685 op->val = *(u32 *)op->ptr;
686 break;
687 case 8:
688 op->val = *(u64 *) op->ptr;
689 break;
690 }
691 }
692 op->orig_val = op->val;
693 }
694
695 static int decode_modrm(struct x86_emulate_ctxt *ctxt,
696 struct x86_emulate_ops *ops)
697 {
698 struct decode_cache *c = &ctxt->decode;
699 u8 sib;
700 int index_reg = 0, base_reg = 0, scale;
701 int rc = 0;
702
703 if (c->rex_prefix) {
704 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
705 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
706 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
707 }
708
709 c->modrm = insn_fetch(u8, 1, c->eip);
710 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
711 c->modrm_reg |= (c->modrm & 0x38) >> 3;
712 c->modrm_rm |= (c->modrm & 0x07);
713 c->modrm_ea = 0;
714 c->use_modrm_ea = 1;
715
716 if (c->modrm_mod == 3) {
717 c->modrm_ptr = decode_register(c->modrm_rm,
718 c->regs, c->d & ByteOp);
719 c->modrm_val = *(unsigned long *)c->modrm_ptr;
720 return rc;
721 }
722
723 if (c->ad_bytes == 2) {
724 unsigned bx = c->regs[VCPU_REGS_RBX];
725 unsigned bp = c->regs[VCPU_REGS_RBP];
726 unsigned si = c->regs[VCPU_REGS_RSI];
727 unsigned di = c->regs[VCPU_REGS_RDI];
728
729 /* 16-bit ModR/M decode. */
730 switch (c->modrm_mod) {
731 case 0:
732 if (c->modrm_rm == 6)
733 c->modrm_ea += insn_fetch(u16, 2, c->eip);
734 break;
735 case 1:
736 c->modrm_ea += insn_fetch(s8, 1, c->eip);
737 break;
738 case 2:
739 c->modrm_ea += insn_fetch(u16, 2, c->eip);
740 break;
741 }
742 switch (c->modrm_rm) {
743 case 0:
744 c->modrm_ea += bx + si;
745 break;
746 case 1:
747 c->modrm_ea += bx + di;
748 break;
749 case 2:
750 c->modrm_ea += bp + si;
751 break;
752 case 3:
753 c->modrm_ea += bp + di;
754 break;
755 case 4:
756 c->modrm_ea += si;
757 break;
758 case 5:
759 c->modrm_ea += di;
760 break;
761 case 6:
762 if (c->modrm_mod != 0)
763 c->modrm_ea += bp;
764 break;
765 case 7:
766 c->modrm_ea += bx;
767 break;
768 }
769 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
770 (c->modrm_rm == 6 && c->modrm_mod != 0))
771 if (!c->has_seg_override)
772 set_seg_override(c, VCPU_SREG_SS);
773 c->modrm_ea = (u16)c->modrm_ea;
774 } else {
775 /* 32/64-bit ModR/M decode. */
776 if ((c->modrm_rm & 7) == 4) {
777 sib = insn_fetch(u8, 1, c->eip);
778 index_reg |= (sib >> 3) & 7;
779 base_reg |= sib & 7;
780 scale = sib >> 6;
781
782 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
783 c->modrm_ea += insn_fetch(s32, 4, c->eip);
784 else
785 c->modrm_ea += c->regs[base_reg];
786 if (index_reg != 4)
787 c->modrm_ea += c->regs[index_reg] << scale;
788 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
789 if (ctxt->mode == X86EMUL_MODE_PROT64)
790 c->rip_relative = 1;
791 } else
792 c->modrm_ea += c->regs[c->modrm_rm];
793 switch (c->modrm_mod) {
794 case 0:
795 if (c->modrm_rm == 5)
796 c->modrm_ea += insn_fetch(s32, 4, c->eip);
797 break;
798 case 1:
799 c->modrm_ea += insn_fetch(s8, 1, c->eip);
800 break;
801 case 2:
802 c->modrm_ea += insn_fetch(s32, 4, c->eip);
803 break;
804 }
805 }
806 done:
807 return rc;
808 }
809
810 static int decode_abs(struct x86_emulate_ctxt *ctxt,
811 struct x86_emulate_ops *ops)
812 {
813 struct decode_cache *c = &ctxt->decode;
814 int rc = 0;
815
816 switch (c->ad_bytes) {
817 case 2:
818 c->modrm_ea = insn_fetch(u16, 2, c->eip);
819 break;
820 case 4:
821 c->modrm_ea = insn_fetch(u32, 4, c->eip);
822 break;
823 case 8:
824 c->modrm_ea = insn_fetch(u64, 8, c->eip);
825 break;
826 }
827 done:
828 return rc;
829 }
830
831 int
832 x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
833 {
834 struct decode_cache *c = &ctxt->decode;
835 int rc = 0;
836 int mode = ctxt->mode;
837 int def_op_bytes, def_ad_bytes, group;
838
839 /* Shadow copy of register state. Committed on successful emulation. */
840
841 memset(c, 0, sizeof(struct decode_cache));
842 c->eip = ctxt->vcpu->arch.rip;
843 ctxt->cs_base = seg_base(ctxt, VCPU_SREG_CS);
844 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
845
846 switch (mode) {
847 case X86EMUL_MODE_REAL:
848 case X86EMUL_MODE_PROT16:
849 def_op_bytes = def_ad_bytes = 2;
850 break;
851 case X86EMUL_MODE_PROT32:
852 def_op_bytes = def_ad_bytes = 4;
853 break;
854 #ifdef CONFIG_X86_64
855 case X86EMUL_MODE_PROT64:
856 def_op_bytes = 4;
857 def_ad_bytes = 8;
858 break;
859 #endif
860 default:
861 return -1;
862 }
863
864 c->op_bytes = def_op_bytes;
865 c->ad_bytes = def_ad_bytes;
866
867 /* Legacy prefixes. */
868 for (;;) {
869 switch (c->b = insn_fetch(u8, 1, c->eip)) {
870 case 0x66: /* operand-size override */
871 /* switch between 2/4 bytes */
872 c->op_bytes = def_op_bytes ^ 6;
873 break;
874 case 0x67: /* address-size override */
875 if (mode == X86EMUL_MODE_PROT64)
876 /* switch between 4/8 bytes */
877 c->ad_bytes = def_ad_bytes ^ 12;
878 else
879 /* switch between 2/4 bytes */
880 c->ad_bytes = def_ad_bytes ^ 6;
881 break;
882 case 0x26: /* ES override */
883 case 0x2e: /* CS override */
884 case 0x36: /* SS override */
885 case 0x3e: /* DS override */
886 set_seg_override(c, (c->b >> 3) & 3);
887 break;
888 case 0x64: /* FS override */
889 case 0x65: /* GS override */
890 set_seg_override(c, c->b & 7);
891 break;
892 case 0x40 ... 0x4f: /* REX */
893 if (mode != X86EMUL_MODE_PROT64)
894 goto done_prefixes;
895 c->rex_prefix = c->b;
896 continue;
897 case 0xf0: /* LOCK */
898 c->lock_prefix = 1;
899 break;
900 case 0xf2: /* REPNE/REPNZ */
901 c->rep_prefix = REPNE_PREFIX;
902 break;
903 case 0xf3: /* REP/REPE/REPZ */
904 c->rep_prefix = REPE_PREFIX;
905 break;
906 default:
907 goto done_prefixes;
908 }
909
910 /* Any legacy prefix after a REX prefix nullifies its effect. */
911
912 c->rex_prefix = 0;
913 }
914
915 done_prefixes:
916
917 /* REX prefix. */
918 if (c->rex_prefix)
919 if (c->rex_prefix & 8)
920 c->op_bytes = 8; /* REX.W */
921
922 /* Opcode byte(s). */
923 c->d = opcode_table[c->b];
924 if (c->d == 0) {
925 /* Two-byte opcode? */
926 if (c->b == 0x0f) {
927 c->twobyte = 1;
928 c->b = insn_fetch(u8, 1, c->eip);
929 c->d = twobyte_table[c->b];
930 }
931 }
932
933 if (c->d & Group) {
934 group = c->d & GroupMask;
935 c->modrm = insn_fetch(u8, 1, c->eip);
936 --c->eip;
937
938 group = (group << 3) + ((c->modrm >> 3) & 7);
939 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
940 c->d = group2_table[group];
941 else
942 c->d = group_table[group];
943 }
944
945 /* Unrecognised? */
946 if (c->d == 0) {
947 DPRINTF("Cannot emulate %02x\n", c->b);
948 return -1;
949 }
950
951 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
952 c->op_bytes = 8;
953
954 /* ModRM and SIB bytes. */
955 if (c->d & ModRM)
956 rc = decode_modrm(ctxt, ops);
957 else if (c->d & MemAbs)
958 rc = decode_abs(ctxt, ops);
959 if (rc)
960 goto done;
961
962 if (!c->has_seg_override)
963 set_seg_override(c, VCPU_SREG_DS);
964
965 if (!(!c->twobyte && c->b == 0x8d))
966 c->modrm_ea += seg_override_base(ctxt, c);
967
968 if (c->ad_bytes != 8)
969 c->modrm_ea = (u32)c->modrm_ea;
970 /*
971 * Decode and fetch the source operand: register, memory
972 * or immediate.
973 */
974 switch (c->d & SrcMask) {
975 case SrcNone:
976 break;
977 case SrcReg:
978 decode_register_operand(&c->src, c, 0);
979 break;
980 case SrcMem16:
981 c->src.bytes = 2;
982 goto srcmem_common;
983 case SrcMem32:
984 c->src.bytes = 4;
985 goto srcmem_common;
986 case SrcMem:
987 c->src.bytes = (c->d & ByteOp) ? 1 :
988 c->op_bytes;
989 /* Don't fetch the address for invlpg: it could be unmapped. */
990 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
991 break;
992 srcmem_common:
993 /*
994 * For instructions with a ModR/M byte, switch to register
995 * access if Mod = 3.
996 */
997 if ((c->d & ModRM) && c->modrm_mod == 3) {
998 c->src.type = OP_REG;
999 c->src.val = c->modrm_val;
1000 c->src.ptr = c->modrm_ptr;
1001 break;
1002 }
1003 c->src.type = OP_MEM;
1004 break;
1005 case SrcImm:
1006 c->src.type = OP_IMM;
1007 c->src.ptr = (unsigned long *)c->eip;
1008 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1009 if (c->src.bytes == 8)
1010 c->src.bytes = 4;
1011 /* NB. Immediates are sign-extended as necessary. */
1012 switch (c->src.bytes) {
1013 case 1:
1014 c->src.val = insn_fetch(s8, 1, c->eip);
1015 break;
1016 case 2:
1017 c->src.val = insn_fetch(s16, 2, c->eip);
1018 break;
1019 case 4:
1020 c->src.val = insn_fetch(s32, 4, c->eip);
1021 break;
1022 }
1023 break;
1024 case SrcImmByte:
1025 c->src.type = OP_IMM;
1026 c->src.ptr = (unsigned long *)c->eip;
1027 c->src.bytes = 1;
1028 c->src.val = insn_fetch(s8, 1, c->eip);
1029 break;
1030 }
1031
1032 /* Decode and fetch the destination operand: register or memory. */
1033 switch (c->d & DstMask) {
1034 case ImplicitOps:
1035 /* Special instructions do their own operand decoding. */
1036 return 0;
1037 case DstReg:
1038 decode_register_operand(&c->dst, c,
1039 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
1040 break;
1041 case DstMem:
1042 if ((c->d & ModRM) && c->modrm_mod == 3) {
1043 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1044 c->dst.type = OP_REG;
1045 c->dst.val = c->dst.orig_val = c->modrm_val;
1046 c->dst.ptr = c->modrm_ptr;
1047 break;
1048 }
1049 c->dst.type = OP_MEM;
1050 break;
1051 }
1052
1053 if (c->rip_relative)
1054 c->modrm_ea += c->eip;
1055
1056 done:
1057 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1058 }
1059
1060 static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
1061 {
1062 struct decode_cache *c = &ctxt->decode;
1063
1064 c->dst.type = OP_MEM;
1065 c->dst.bytes = c->op_bytes;
1066 c->dst.val = c->src.val;
1067 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
1068 c->dst.ptr = (void *) register_address(c, ss_base(ctxt),
1069 c->regs[VCPU_REGS_RSP]);
1070 }
1071
1072 static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1073 struct x86_emulate_ops *ops)
1074 {
1075 struct decode_cache *c = &ctxt->decode;
1076 int rc;
1077
1078 rc = ops->read_std(register_address(c, ss_base(ctxt),
1079 c->regs[VCPU_REGS_RSP]),
1080 &c->dst.val, c->dst.bytes, ctxt->vcpu);
1081 if (rc != 0)
1082 return rc;
1083
1084 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->dst.bytes);
1085
1086 return 0;
1087 }
1088
1089 static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
1090 {
1091 struct decode_cache *c = &ctxt->decode;
1092 switch (c->modrm_reg) {
1093 case 0: /* rol */
1094 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
1095 break;
1096 case 1: /* ror */
1097 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
1098 break;
1099 case 2: /* rcl */
1100 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
1101 break;
1102 case 3: /* rcr */
1103 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
1104 break;
1105 case 4: /* sal/shl */
1106 case 6: /* sal/shl */
1107 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
1108 break;
1109 case 5: /* shr */
1110 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
1111 break;
1112 case 7: /* sar */
1113 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
1114 break;
1115 }
1116 }
1117
1118 static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
1119 struct x86_emulate_ops *ops)
1120 {
1121 struct decode_cache *c = &ctxt->decode;
1122 int rc = 0;
1123
1124 switch (c->modrm_reg) {
1125 case 0 ... 1: /* test */
1126 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1127 break;
1128 case 2: /* not */
1129 c->dst.val = ~c->dst.val;
1130 break;
1131 case 3: /* neg */
1132 emulate_1op("neg", c->dst, ctxt->eflags);
1133 break;
1134 default:
1135 DPRINTF("Cannot emulate %02x\n", c->b);
1136 rc = X86EMUL_UNHANDLEABLE;
1137 break;
1138 }
1139 return rc;
1140 }
1141
1142 static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
1143 struct x86_emulate_ops *ops)
1144 {
1145 struct decode_cache *c = &ctxt->decode;
1146
1147 switch (c->modrm_reg) {
1148 case 0: /* inc */
1149 emulate_1op("inc", c->dst, ctxt->eflags);
1150 break;
1151 case 1: /* dec */
1152 emulate_1op("dec", c->dst, ctxt->eflags);
1153 break;
1154 case 4: /* jmp abs */
1155 c->eip = c->src.val;
1156 break;
1157 case 6: /* push */
1158 emulate_push(ctxt);
1159 break;
1160 }
1161 return 0;
1162 }
1163
1164 static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1165 struct x86_emulate_ops *ops,
1166 unsigned long memop)
1167 {
1168 struct decode_cache *c = &ctxt->decode;
1169 u64 old, new;
1170 int rc;
1171
1172 rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu);
1173 if (rc != 0)
1174 return rc;
1175
1176 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1177 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1178
1179 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1180 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
1181 ctxt->eflags &= ~EFLG_ZF;
1182
1183 } else {
1184 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1185 (u32) c->regs[VCPU_REGS_RBX];
1186
1187 rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu);
1188 if (rc != 0)
1189 return rc;
1190 ctxt->eflags |= EFLG_ZF;
1191 }
1192 return 0;
1193 }
1194
1195 static inline int writeback(struct x86_emulate_ctxt *ctxt,
1196 struct x86_emulate_ops *ops)
1197 {
1198 int rc;
1199 struct decode_cache *c = &ctxt->decode;
1200
1201 switch (c->dst.type) {
1202 case OP_REG:
1203 /* The 4-byte case *is* correct:
1204 * in 64-bit mode we zero-extend.
1205 */
1206 switch (c->dst.bytes) {
1207 case 1:
1208 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1209 break;
1210 case 2:
1211 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1212 break;
1213 case 4:
1214 *c->dst.ptr = (u32)c->dst.val;
1215 break; /* 64b: zero-ext */
1216 case 8:
1217 *c->dst.ptr = c->dst.val;
1218 break;
1219 }
1220 break;
1221 case OP_MEM:
1222 if (c->lock_prefix)
1223 rc = ops->cmpxchg_emulated(
1224 (unsigned long)c->dst.ptr,
1225 &c->dst.orig_val,
1226 &c->dst.val,
1227 c->dst.bytes,
1228 ctxt->vcpu);
1229 else
1230 rc = ops->write_emulated(
1231 (unsigned long)c->dst.ptr,
1232 &c->dst.val,
1233 c->dst.bytes,
1234 ctxt->vcpu);
1235 if (rc != 0)
1236 return rc;
1237 break;
1238 case OP_NONE:
1239 /* no writeback */
1240 break;
1241 default:
1242 break;
1243 }
1244 return 0;
1245 }
1246
1247 int
1248 x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1249 {
1250 unsigned long memop = 0;
1251 u64 msr_data;
1252 unsigned long saved_eip = 0;
1253 struct decode_cache *c = &ctxt->decode;
1254 int rc = 0;
1255
1256 /* Shadow copy of register state. Committed on successful emulation.
1257 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
1258 * modify them.
1259 */
1260
1261 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
1262 saved_eip = c->eip;
1263
1264 if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs))
1265 memop = c->modrm_ea;
1266
1267 if (c->rep_prefix && (c->d & String)) {
1268 /* All REP prefixes have the same first termination condition */
1269 if (c->regs[VCPU_REGS_RCX] == 0) {
1270 ctxt->vcpu->arch.rip = c->eip;
1271 goto done;
1272 }
1273 /* The second termination condition only applies for REPE
1274 * and REPNE. Test if the repeat string operation prefix is
1275 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
1276 * corresponding termination condition according to:
1277 * - if REPE/REPZ and ZF = 0 then done
1278 * - if REPNE/REPNZ and ZF = 1 then done
1279 */
1280 if ((c->b == 0xa6) || (c->b == 0xa7) ||
1281 (c->b == 0xae) || (c->b == 0xaf)) {
1282 if ((c->rep_prefix == REPE_PREFIX) &&
1283 ((ctxt->eflags & EFLG_ZF) == 0)) {
1284 ctxt->vcpu->arch.rip = c->eip;
1285 goto done;
1286 }
1287 if ((c->rep_prefix == REPNE_PREFIX) &&
1288 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) {
1289 ctxt->vcpu->arch.rip = c->eip;
1290 goto done;
1291 }
1292 }
1293 c->regs[VCPU_REGS_RCX]--;
1294 c->eip = ctxt->vcpu->arch.rip;
1295 }
1296
1297 if (c->src.type == OP_MEM) {
1298 c->src.ptr = (unsigned long *)memop;
1299 c->src.val = 0;
1300 rc = ops->read_emulated((unsigned long)c->src.ptr,
1301 &c->src.val,
1302 c->src.bytes,
1303 ctxt->vcpu);
1304 if (rc != 0)
1305 goto done;
1306 c->src.orig_val = c->src.val;
1307 }
1308
1309 if ((c->d & DstMask) == ImplicitOps)
1310 goto special_insn;
1311
1312
1313 if (c->dst.type == OP_MEM) {
1314 c->dst.ptr = (unsigned long *)memop;
1315 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1316 c->dst.val = 0;
1317 if (c->d & BitOp) {
1318 unsigned long mask = ~(c->dst.bytes * 8 - 1);
1319
1320 c->dst.ptr = (void *)c->dst.ptr +
1321 (c->src.val & mask) / 8;
1322 }
1323 if (!(c->d & Mov) &&
1324 /* optimisation - avoid slow emulated read */
1325 ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1326 &c->dst.val,
1327 c->dst.bytes, ctxt->vcpu)) != 0))
1328 goto done;
1329 }
1330 c->dst.orig_val = c->dst.val;
1331
1332 special_insn:
1333
1334 if (c->twobyte)
1335 goto twobyte_insn;
1336
1337 switch (c->b) {
1338 case 0x00 ... 0x05:
1339 add: /* add */
1340 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
1341 break;
1342 case 0x08 ... 0x0d:
1343 or: /* or */
1344 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
1345 break;
1346 case 0x10 ... 0x15:
1347 adc: /* adc */
1348 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
1349 break;
1350 case 0x18 ... 0x1d:
1351 sbb: /* sbb */
1352 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
1353 break;
1354 case 0x20 ... 0x23:
1355 and: /* and */
1356 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
1357 break;
1358 case 0x24: /* and al imm8 */
1359 c->dst.type = OP_REG;
1360 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1361 c->dst.val = *(u8 *)c->dst.ptr;
1362 c->dst.bytes = 1;
1363 c->dst.orig_val = c->dst.val;
1364 goto and;
1365 case 0x25: /* and ax imm16, or eax imm32 */
1366 c->dst.type = OP_REG;
1367 c->dst.bytes = c->op_bytes;
1368 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1369 if (c->op_bytes == 2)
1370 c->dst.val = *(u16 *)c->dst.ptr;
1371 else
1372 c->dst.val = *(u32 *)c->dst.ptr;
1373 c->dst.orig_val = c->dst.val;
1374 goto and;
1375 case 0x28 ... 0x2d:
1376 sub: /* sub */
1377 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
1378 break;
1379 case 0x30 ... 0x35:
1380 xor: /* xor */
1381 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
1382 break;
1383 case 0x38 ... 0x3d:
1384 cmp: /* cmp */
1385 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1386 break;
1387 case 0x40 ... 0x47: /* inc r16/r32 */
1388 emulate_1op("inc", c->dst, ctxt->eflags);
1389 break;
1390 case 0x48 ... 0x4f: /* dec r16/r32 */
1391 emulate_1op("dec", c->dst, ctxt->eflags);
1392 break;
1393 case 0x50 ... 0x57: /* push reg */
1394 c->dst.type = OP_MEM;
1395 c->dst.bytes = c->op_bytes;
1396 c->dst.val = c->src.val;
1397 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1398 -c->op_bytes);
1399 c->dst.ptr = (void *) register_address(
1400 c, ss_base(ctxt), c->regs[VCPU_REGS_RSP]);
1401 break;
1402 case 0x58 ... 0x5f: /* pop reg */
1403 pop_instruction:
1404 if ((rc = ops->read_std(register_address(c, ss_base(ctxt),
1405 c->regs[VCPU_REGS_RSP]), c->dst.ptr,
1406 c->op_bytes, ctxt->vcpu)) != 0)
1407 goto done;
1408
1409 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1410 c->op_bytes);
1411 c->dst.type = OP_NONE; /* Disable writeback. */
1412 break;
1413 case 0x63: /* movsxd */
1414 if (ctxt->mode != X86EMUL_MODE_PROT64)
1415 goto cannot_emulate;
1416 c->dst.val = (s32) c->src.val;
1417 break;
1418 case 0x68: /* push imm */
1419 case 0x6a: /* push imm8 */
1420 emulate_push(ctxt);
1421 break;
1422 case 0x6c: /* insb */
1423 case 0x6d: /* insw/insd */
1424 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1425 1,
1426 (c->d & ByteOp) ? 1 : c->op_bytes,
1427 c->rep_prefix ?
1428 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
1429 (ctxt->eflags & EFLG_DF),
1430 register_address(c, es_base(ctxt),
1431 c->regs[VCPU_REGS_RDI]),
1432 c->rep_prefix,
1433 c->regs[VCPU_REGS_RDX]) == 0) {
1434 c->eip = saved_eip;
1435 return -1;
1436 }
1437 return 0;
1438 case 0x6e: /* outsb */
1439 case 0x6f: /* outsw/outsd */
1440 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1441 0,
1442 (c->d & ByteOp) ? 1 : c->op_bytes,
1443 c->rep_prefix ?
1444 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
1445 (ctxt->eflags & EFLG_DF),
1446 register_address(c,
1447 seg_override_base(ctxt, c),
1448 c->regs[VCPU_REGS_RSI]),
1449 c->rep_prefix,
1450 c->regs[VCPU_REGS_RDX]) == 0) {
1451 c->eip = saved_eip;
1452 return -1;
1453 }
1454 return 0;
1455 case 0x70 ... 0x7f: /* jcc (short) */ {
1456 int rel = insn_fetch(s8, 1, c->eip);
1457
1458 if (test_cc(c->b, ctxt->eflags))
1459 jmp_rel(c, rel);
1460 break;
1461 }
1462 case 0x80 ... 0x83: /* Grp1 */
1463 switch (c->modrm_reg) {
1464 case 0:
1465 goto add;
1466 case 1:
1467 goto or;
1468 case 2:
1469 goto adc;
1470 case 3:
1471 goto sbb;
1472 case 4:
1473 goto and;
1474 case 5:
1475 goto sub;
1476 case 6:
1477 goto xor;
1478 case 7:
1479 goto cmp;
1480 }
1481 break;
1482 case 0x84 ... 0x85:
1483 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1484 break;
1485 case 0x86 ... 0x87: /* xchg */
1486 xchg:
1487 /* Write back the register source. */
1488 switch (c->dst.bytes) {
1489 case 1:
1490 *(u8 *) c->src.ptr = (u8) c->dst.val;
1491 break;
1492 case 2:
1493 *(u16 *) c->src.ptr = (u16) c->dst.val;
1494 break;
1495 case 4:
1496 *c->src.ptr = (u32) c->dst.val;
1497 break; /* 64b reg: zero-extend */
1498 case 8:
1499 *c->src.ptr = c->dst.val;
1500 break;
1501 }
1502 /*
1503 * Write back the memory destination with implicit LOCK
1504 * prefix.
1505 */
1506 c->dst.val = c->src.val;
1507 c->lock_prefix = 1;
1508 break;
1509 case 0x88 ... 0x8b: /* mov */
1510 goto mov;
1511 case 0x8c: { /* mov r/m, sreg */
1512 struct kvm_segment segreg;
1513
1514 if (c->modrm_reg <= 5)
1515 kvm_get_segment(ctxt->vcpu, &segreg, c->modrm_reg);
1516 else {
1517 printk(KERN_INFO "0x8c: Invalid segreg in modrm byte 0x%02x\n",
1518 c->modrm);
1519 goto cannot_emulate;
1520 }
1521 c->dst.val = segreg.selector;
1522 break;
1523 }
1524 case 0x8d: /* lea r16/r32, m */
1525 c->dst.val = c->modrm_ea;
1526 break;
1527 case 0x8e: { /* mov seg, r/m16 */
1528 uint16_t sel;
1529 int type_bits;
1530 int err;
1531
1532 sel = c->src.val;
1533 if (c->modrm_reg <= 5) {
1534 type_bits = (c->modrm_reg == 1) ? 9 : 1;
1535 err = kvm_load_segment_descriptor(ctxt->vcpu, sel,
1536 type_bits, c->modrm_reg);
1537 } else {
1538 printk(KERN_INFO "Invalid segreg in modrm byte 0x%02x\n",
1539 c->modrm);
1540 goto cannot_emulate;
1541 }
1542
1543 if (err < 0)
1544 goto cannot_emulate;
1545
1546 c->dst.type = OP_NONE; /* Disable writeback. */
1547 break;
1548 }
1549 case 0x8f: /* pop (sole member of Grp1a) */
1550 rc = emulate_grp1a(ctxt, ops);
1551 if (rc != 0)
1552 goto done;
1553 break;
1554 case 0x90: /* nop / xchg r8,rax */
1555 if (!(c->rex_prefix & 1)) { /* nop */
1556 c->dst.type = OP_NONE;
1557 break;
1558 }
1559 case 0x91 ... 0x97: /* xchg reg,rax */
1560 c->src.type = c->dst.type = OP_REG;
1561 c->src.bytes = c->dst.bytes = c->op_bytes;
1562 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
1563 c->src.val = *(c->src.ptr);
1564 goto xchg;
1565 case 0x9c: /* pushf */
1566 c->src.val = (unsigned long) ctxt->eflags;
1567 emulate_push(ctxt);
1568 break;
1569 case 0x9d: /* popf */
1570 c->dst.ptr = (unsigned long *) &ctxt->eflags;
1571 goto pop_instruction;
1572 case 0xa0 ... 0xa1: /* mov */
1573 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1574 c->dst.val = c->src.val;
1575 break;
1576 case 0xa2 ... 0xa3: /* mov */
1577 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
1578 break;
1579 case 0xa4 ... 0xa5: /* movs */
1580 c->dst.type = OP_MEM;
1581 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1582 c->dst.ptr = (unsigned long *)register_address(c,
1583 es_base(ctxt),
1584 c->regs[VCPU_REGS_RDI]);
1585 if ((rc = ops->read_emulated(register_address(c,
1586 seg_override_base(ctxt, c),
1587 c->regs[VCPU_REGS_RSI]),
1588 &c->dst.val,
1589 c->dst.bytes, ctxt->vcpu)) != 0)
1590 goto done;
1591 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
1592 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1593 : c->dst.bytes);
1594 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
1595 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1596 : c->dst.bytes);
1597 break;
1598 case 0xa6 ... 0xa7: /* cmps */
1599 c->src.type = OP_NONE; /* Disable writeback. */
1600 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1601 c->src.ptr = (unsigned long *)register_address(c,
1602 seg_override_base(ctxt, c),
1603 c->regs[VCPU_REGS_RSI]);
1604 if ((rc = ops->read_emulated((unsigned long)c->src.ptr,
1605 &c->src.val,
1606 c->src.bytes,
1607 ctxt->vcpu)) != 0)
1608 goto done;
1609
1610 c->dst.type = OP_NONE; /* Disable writeback. */
1611 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1612 c->dst.ptr = (unsigned long *)register_address(c,
1613 es_base(ctxt),
1614 c->regs[VCPU_REGS_RDI]);
1615 if ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1616 &c->dst.val,
1617 c->dst.bytes,
1618 ctxt->vcpu)) != 0)
1619 goto done;
1620
1621 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
1622
1623 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1624
1625 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
1626 (ctxt->eflags & EFLG_DF) ? -c->src.bytes
1627 : c->src.bytes);
1628 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
1629 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1630 : c->dst.bytes);
1631
1632 break;
1633 case 0xaa ... 0xab: /* stos */
1634 c->dst.type = OP_MEM;
1635 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1636 c->dst.ptr = (unsigned long *)register_address(c,
1637 es_base(ctxt),
1638 c->regs[VCPU_REGS_RDI]);
1639 c->dst.val = c->regs[VCPU_REGS_RAX];
1640 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
1641 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1642 : c->dst.bytes);
1643 break;
1644 case 0xac ... 0xad: /* lods */
1645 c->dst.type = OP_REG;
1646 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1647 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1648 if ((rc = ops->read_emulated(register_address(c,
1649 seg_override_base(ctxt, c),
1650 c->regs[VCPU_REGS_RSI]),
1651 &c->dst.val,
1652 c->dst.bytes,
1653 ctxt->vcpu)) != 0)
1654 goto done;
1655 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
1656 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1657 : c->dst.bytes);
1658 break;
1659 case 0xae ... 0xaf: /* scas */
1660 DPRINTF("Urk! I don't handle SCAS.\n");
1661 goto cannot_emulate;
1662 case 0xb8: /* mov r, imm */
1663 goto mov;
1664 case 0xc0 ... 0xc1:
1665 emulate_grp2(ctxt);
1666 break;
1667 case 0xc3: /* ret */
1668 c->dst.ptr = &c->eip;
1669 goto pop_instruction;
1670 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
1671 mov:
1672 c->dst.val = c->src.val;
1673 break;
1674 case 0xd0 ... 0xd1: /* Grp2 */
1675 c->src.val = 1;
1676 emulate_grp2(ctxt);
1677 break;
1678 case 0xd2 ... 0xd3: /* Grp2 */
1679 c->src.val = c->regs[VCPU_REGS_RCX];
1680 emulate_grp2(ctxt);
1681 break;
1682 case 0xe8: /* call (near) */ {
1683 long int rel;
1684 switch (c->op_bytes) {
1685 case 2:
1686 rel = insn_fetch(s16, 2, c->eip);
1687 break;
1688 case 4:
1689 rel = insn_fetch(s32, 4, c->eip);
1690 break;
1691 default:
1692 DPRINTF("Call: Invalid op_bytes\n");
1693 goto cannot_emulate;
1694 }
1695 c->src.val = (unsigned long) c->eip;
1696 jmp_rel(c, rel);
1697 c->op_bytes = c->ad_bytes;
1698 emulate_push(ctxt);
1699 break;
1700 }
1701 case 0xe9: /* jmp rel */
1702 goto jmp;
1703 case 0xea: /* jmp far */ {
1704 uint32_t eip;
1705 uint16_t sel;
1706
1707 switch (c->op_bytes) {
1708 case 2:
1709 eip = insn_fetch(u16, 2, c->eip);
1710 break;
1711 case 4:
1712 eip = insn_fetch(u32, 4, c->eip);
1713 break;
1714 default:
1715 DPRINTF("jmp far: Invalid op_bytes\n");
1716 goto cannot_emulate;
1717 }
1718 sel = insn_fetch(u16, 2, c->eip);
1719 if (kvm_load_segment_descriptor(ctxt->vcpu, sel, 9, VCPU_SREG_CS) < 0) {
1720 DPRINTF("jmp far: Failed to load CS descriptor\n");
1721 goto cannot_emulate;
1722 }
1723
1724 c->eip = eip;
1725 break;
1726 }
1727 case 0xeb:
1728 jmp: /* jmp rel short */
1729 jmp_rel(c, c->src.val);
1730 c->dst.type = OP_NONE; /* Disable writeback. */
1731 break;
1732 case 0xf4: /* hlt */
1733 ctxt->vcpu->arch.halt_request = 1;
1734 break;
1735 case 0xf5: /* cmc */
1736 /* complement carry flag from eflags reg */
1737 ctxt->eflags ^= EFLG_CF;
1738 c->dst.type = OP_NONE; /* Disable writeback. */
1739 break;
1740 case 0xf6 ... 0xf7: /* Grp3 */
1741 rc = emulate_grp3(ctxt, ops);
1742 if (rc != 0)
1743 goto done;
1744 break;
1745 case 0xf8: /* clc */
1746 ctxt->eflags &= ~EFLG_CF;
1747 c->dst.type = OP_NONE; /* Disable writeback. */
1748 break;
1749 case 0xfa: /* cli */
1750 ctxt->eflags &= ~X86_EFLAGS_IF;
1751 c->dst.type = OP_NONE; /* Disable writeback. */
1752 break;
1753 case 0xfb: /* sti */
1754 ctxt->eflags |= X86_EFLAGS_IF;
1755 c->dst.type = OP_NONE; /* Disable writeback. */
1756 break;
1757 case 0xfe ... 0xff: /* Grp4/Grp5 */
1758 rc = emulate_grp45(ctxt, ops);
1759 if (rc != 0)
1760 goto done;
1761 break;
1762 }
1763
1764 writeback:
1765 rc = writeback(ctxt, ops);
1766 if (rc != 0)
1767 goto done;
1768
1769 /* Commit shadow register state. */
1770 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
1771 ctxt->vcpu->arch.rip = c->eip;
1772
1773 done:
1774 if (rc == X86EMUL_UNHANDLEABLE) {
1775 c->eip = saved_eip;
1776 return -1;
1777 }
1778 return 0;
1779
1780 twobyte_insn:
1781 switch (c->b) {
1782 case 0x01: /* lgdt, lidt, lmsw */
1783 switch (c->modrm_reg) {
1784 u16 size;
1785 unsigned long address;
1786
1787 case 0: /* vmcall */
1788 if (c->modrm_mod != 3 || c->modrm_rm != 1)
1789 goto cannot_emulate;
1790
1791 rc = kvm_fix_hypercall(ctxt->vcpu);
1792 if (rc)
1793 goto done;
1794
1795 /* Let the processor re-execute the fixed hypercall */
1796 c->eip = ctxt->vcpu->arch.rip;
1797 /* Disable writeback. */
1798 c->dst.type = OP_NONE;
1799 break;
1800 case 2: /* lgdt */
1801 rc = read_descriptor(ctxt, ops, c->src.ptr,
1802 &size, &address, c->op_bytes);
1803 if (rc)
1804 goto done;
1805 realmode_lgdt(ctxt->vcpu, size, address);
1806 /* Disable writeback. */
1807 c->dst.type = OP_NONE;
1808 break;
1809 case 3: /* lidt/vmmcall */
1810 if (c->modrm_mod == 3 && c->modrm_rm == 1) {
1811 rc = kvm_fix_hypercall(ctxt->vcpu);
1812 if (rc)
1813 goto done;
1814 kvm_emulate_hypercall(ctxt->vcpu);
1815 } else {
1816 rc = read_descriptor(ctxt, ops, c->src.ptr,
1817 &size, &address,
1818 c->op_bytes);
1819 if (rc)
1820 goto done;
1821 realmode_lidt(ctxt->vcpu, size, address);
1822 }
1823 /* Disable writeback. */
1824 c->dst.type = OP_NONE;
1825 break;
1826 case 4: /* smsw */
1827 c->dst.bytes = 2;
1828 c->dst.val = realmode_get_cr(ctxt->vcpu, 0);
1829 break;
1830 case 6: /* lmsw */
1831 realmode_lmsw(ctxt->vcpu, (u16)c->src.val,
1832 &ctxt->eflags);
1833 c->dst.type = OP_NONE;
1834 break;
1835 case 7: /* invlpg*/
1836 emulate_invlpg(ctxt->vcpu, memop);
1837 /* Disable writeback. */
1838 c->dst.type = OP_NONE;
1839 break;
1840 default:
1841 goto cannot_emulate;
1842 }
1843 break;
1844 case 0x06:
1845 emulate_clts(ctxt->vcpu);
1846 c->dst.type = OP_NONE;
1847 break;
1848 case 0x08: /* invd */
1849 case 0x09: /* wbinvd */
1850 case 0x0d: /* GrpP (prefetch) */
1851 case 0x18: /* Grp16 (prefetch/nop) */
1852 c->dst.type = OP_NONE;
1853 break;
1854 case 0x20: /* mov cr, reg */
1855 if (c->modrm_mod != 3)
1856 goto cannot_emulate;
1857 c->regs[c->modrm_rm] =
1858 realmode_get_cr(ctxt->vcpu, c->modrm_reg);
1859 c->dst.type = OP_NONE; /* no writeback */
1860 break;
1861 case 0x21: /* mov from dr to reg */
1862 if (c->modrm_mod != 3)
1863 goto cannot_emulate;
1864 rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
1865 if (rc)
1866 goto cannot_emulate;
1867 c->dst.type = OP_NONE; /* no writeback */
1868 break;
1869 case 0x22: /* mov reg, cr */
1870 if (c->modrm_mod != 3)
1871 goto cannot_emulate;
1872 realmode_set_cr(ctxt->vcpu,
1873 c->modrm_reg, c->modrm_val, &ctxt->eflags);
1874 c->dst.type = OP_NONE;
1875 break;
1876 case 0x23: /* mov from reg to dr */
1877 if (c->modrm_mod != 3)
1878 goto cannot_emulate;
1879 rc = emulator_set_dr(ctxt, c->modrm_reg,
1880 c->regs[c->modrm_rm]);
1881 if (rc)
1882 goto cannot_emulate;
1883 c->dst.type = OP_NONE; /* no writeback */
1884 break;
1885 case 0x30:
1886 /* wrmsr */
1887 msr_data = (u32)c->regs[VCPU_REGS_RAX]
1888 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
1889 rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
1890 if (rc) {
1891 kvm_inject_gp(ctxt->vcpu, 0);
1892 c->eip = ctxt->vcpu->arch.rip;
1893 }
1894 rc = X86EMUL_CONTINUE;
1895 c->dst.type = OP_NONE;
1896 break;
1897 case 0x32:
1898 /* rdmsr */
1899 rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data);
1900 if (rc) {
1901 kvm_inject_gp(ctxt->vcpu, 0);
1902 c->eip = ctxt->vcpu->arch.rip;
1903 } else {
1904 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
1905 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
1906 }
1907 rc = X86EMUL_CONTINUE;
1908 c->dst.type = OP_NONE;
1909 break;
1910 case 0x40 ... 0x4f: /* cmov */
1911 c->dst.val = c->dst.orig_val = c->src.val;
1912 if (!test_cc(c->b, ctxt->eflags))
1913 c->dst.type = OP_NONE; /* no writeback */
1914 break;
1915 case 0x80 ... 0x8f: /* jnz rel, etc*/ {
1916 long int rel;
1917
1918 switch (c->op_bytes) {
1919 case 2:
1920 rel = insn_fetch(s16, 2, c->eip);
1921 break;
1922 case 4:
1923 rel = insn_fetch(s32, 4, c->eip);
1924 break;
1925 case 8:
1926 rel = insn_fetch(s64, 8, c->eip);
1927 break;
1928 default:
1929 DPRINTF("jnz: Invalid op_bytes\n");
1930 goto cannot_emulate;
1931 }
1932 if (test_cc(c->b, ctxt->eflags))
1933 jmp_rel(c, rel);
1934 c->dst.type = OP_NONE;
1935 break;
1936 }
1937 case 0xa3:
1938 bt: /* bt */
1939 c->dst.type = OP_NONE;
1940 /* only subword offset */
1941 c->src.val &= (c->dst.bytes << 3) - 1;
1942 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
1943 break;
1944 case 0xab:
1945 bts: /* bts */
1946 /* only subword offset */
1947 c->src.val &= (c->dst.bytes << 3) - 1;
1948 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
1949 break;
1950 case 0xae: /* clflush */
1951 break;
1952 case 0xb0 ... 0xb1: /* cmpxchg */
1953 /*
1954 * Save real source value, then compare EAX against
1955 * destination.
1956 */
1957 c->src.orig_val = c->src.val;
1958 c->src.val = c->regs[VCPU_REGS_RAX];
1959 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1960 if (ctxt->eflags & EFLG_ZF) {
1961 /* Success: write back to memory. */
1962 c->dst.val = c->src.orig_val;
1963 } else {
1964 /* Failure: write the value we saw to EAX. */
1965 c->dst.type = OP_REG;
1966 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1967 }
1968 break;
1969 case 0xb3:
1970 btr: /* btr */
1971 /* only subword offset */
1972 c->src.val &= (c->dst.bytes << 3) - 1;
1973 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
1974 break;
1975 case 0xb6 ... 0xb7: /* movzx */
1976 c->dst.bytes = c->op_bytes;
1977 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
1978 : (u16) c->src.val;
1979 break;
1980 case 0xba: /* Grp8 */
1981 switch (c->modrm_reg & 3) {
1982 case 0:
1983 goto bt;
1984 case 1:
1985 goto bts;
1986 case 2:
1987 goto btr;
1988 case 3:
1989 goto btc;
1990 }
1991 break;
1992 case 0xbb:
1993 btc: /* btc */
1994 /* only subword offset */
1995 c->src.val &= (c->dst.bytes << 3) - 1;
1996 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
1997 break;
1998 case 0xbe ... 0xbf: /* movsx */
1999 c->dst.bytes = c->op_bytes;
2000 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
2001 (s16) c->src.val;
2002 break;
2003 case 0xc3: /* movnti */
2004 c->dst.bytes = c->op_bytes;
2005 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
2006 (u64) c->src.val;
2007 break;
2008 case 0xc7: /* Grp9 (cmpxchg8b) */
2009 rc = emulate_grp9(ctxt, ops, memop);
2010 if (rc != 0)
2011 goto done;
2012 c->dst.type = OP_NONE;
2013 break;
2014 }
2015 goto writeback;
2016
2017 cannot_emulate:
2018 DPRINTF("Cannot emulate %02x\n", c->b);
2019 c->eip = saved_eip;
2020 return -1;
2021 }
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