drivers/gpu/drm/radeon/radeon.h

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #ifndef __RADEON_H__
  29 #define __RADEON_H__
  30
  31 #include "radeon_object.h"
  32
  33 /* TODO: Here are things that needs to be done :
  34  *      - surface allocator & initializer : (bit like scratch reg) should
  35  *        initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
  36  *        related to surface
  37  *      - WB : write back stuff (do it bit like scratch reg things)
  38  *      - Vblank : look at Jesse's rework and what we should do
  39  *      - r600/r700: gart & cp
  40  *      - cs : clean cs ioctl use bitmap & things like that.
  41  *      - power management stuff
  42  *      - Barrier in gart code
  43  *      - Unmappabled vram ?
  44  *      - TESTING, TESTING, TESTING
  45  */
  46
  47 #include <asm/atomic.h>
  48 #include <linux/wait.h>
  49 #include <linux/list.h>
  50 #include <linux/kref.h>
  51
  52 #include "radeon_mode.h"
  53 #include "radeon_share.h"
  54 #include "radeon_reg.h"
  55
  56 /*
  57  * Modules parameters.
  58  */
  59 extern int radeon_no_wb;
  60 extern int radeon_modeset;
  61 extern int radeon_dynclks;
  62 extern int radeon_r4xx_atom;
  63 extern int radeon_agpmode;
  64 extern int radeon_vram_limit;
  65 extern int radeon_gart_size;
  66 extern int radeon_benchmarking;
  67 extern int radeon_testing;
  68 extern int radeon_connector_table;
  69 extern int radeon_tv;
  70
  71 /*
  72  * Copy from radeon_drv.h so we don't have to include both and have conflicting
  73  * symbol;
  74  */
  75 #define RADEON_MAX_USEC_TIMEOUT         100000  /* 100 ms */
  76 #define RADEON_IB_POOL_SIZE             16
  77 #define RADEON_DEBUGFS_MAX_NUM_FILES    32
  78 #define RADEONFB_CONN_LIMIT             4
  79
  80 enum radeon_family {
  81         CHIP_R100,
  82         CHIP_RV100,
  83         CHIP_RS100,
  84         CHIP_RV200,
  85         CHIP_RS200,
  86         CHIP_R200,
  87         CHIP_RV250,
  88         CHIP_RS300,
  89         CHIP_RV280,
  90         CHIP_R300,
  91         CHIP_R350,
  92         CHIP_RV350,
  93         CHIP_RV380,
  94         CHIP_R420,
  95         CHIP_R423,
  96         CHIP_RV410,
  97         CHIP_RS400,
  98         CHIP_RS480,
  99         CHIP_RS600,
 100         CHIP_RS690,
 101         CHIP_RS740,
 102         CHIP_RV515,
 103         CHIP_R520,
 104         CHIP_RV530,
 105         CHIP_RV560,
 106         CHIP_RV570,
 107         CHIP_R580,
 108         CHIP_R600,
 109         CHIP_RV610,
 110         CHIP_RV630,
 111         CHIP_RV620,
 112         CHIP_RV635,
 113         CHIP_RV670,
 114         CHIP_RS780,
 115         CHIP_RS880,
 116         CHIP_RV770,
 117         CHIP_RV730,
 118         CHIP_RV710,
 119         CHIP_RV740,
 120         CHIP_LAST,
 121 };
 122
 123 enum radeon_chip_flags {
 124         RADEON_FAMILY_MASK = 0x0000ffffUL,
 125         RADEON_FLAGS_MASK = 0xffff0000UL,
 126         RADEON_IS_MOBILITY = 0x00010000UL,
 127         RADEON_IS_IGP = 0x00020000UL,
 128         RADEON_SINGLE_CRTC = 0x00040000UL,
 129         RADEON_IS_AGP = 0x00080000UL,
 130         RADEON_HAS_HIERZ = 0x00100000UL,
 131         RADEON_IS_PCIE = 0x00200000UL,
 132         RADEON_NEW_MEMMAP = 0x00400000UL,
 133         RADEON_IS_PCI = 0x00800000UL,
 134         RADEON_IS_IGPGART = 0x01000000UL,
 135 };
 136
 137
 138 /*
 139  * Errata workarounds.
 140  */
 141 enum radeon_pll_errata {
 142         CHIP_ERRATA_R300_CG             = 0x00000001,
 143         CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
 144         CHIP_ERRATA_PLL_DELAY           = 0x00000004
 145 };
 146
 147
 148 struct radeon_device;
 149
 150
 151 /*
 152  * BIOS.
 153  */
 154 bool radeon_get_bios(struct radeon_device *rdev);
 155
 156
 157 /*
 158  * Dummy page
 159  */
 160 struct radeon_dummy_page {
 161         struct page     *page;
 162         dma_addr_t      addr;
 163 };
 164 int radeon_dummy_page_init(struct radeon_device *rdev);
 165 void radeon_dummy_page_fini(struct radeon_device *rdev);
 166
 167
 168 /*
 169  * Clocks
 170  */
 171 struct radeon_clock {
 172         struct radeon_pll p1pll;
 173         struct radeon_pll p2pll;
 174         struct radeon_pll spll;
 175         struct radeon_pll mpll;
 176         /* 10 Khz units */
 177         uint32_t default_mclk;
 178         uint32_t default_sclk;
 179 };
 180
 181
 182 /*
 183  * Fences.
 184  */
 185 struct radeon_fence_driver {
 186         uint32_t                        scratch_reg;
 187         atomic_t                        seq;
 188         uint32_t                        last_seq;
 189         unsigned long                   count_timeout;
 190         wait_queue_head_t               queue;
 191         rwlock_t                        lock;
 192         struct list_head                created;
 193         struct list_head                emited;
 194         struct list_head                signaled;
 195 };
 196
 197 struct radeon_fence {
 198         struct radeon_device            *rdev;
 199         struct kref                     kref;
 200         struct list_head                list;
 201         /* protected by radeon_fence.lock */
 202         uint32_t                        seq;
 203         unsigned long                   timeout;
 204         bool                            emited;
 205         bool                            signaled;
 206 };
 207
 208 int radeon_fence_driver_init(struct radeon_device *rdev);
 209 void radeon_fence_driver_fini(struct radeon_device *rdev);
 210 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
 211 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
 212 void radeon_fence_process(struct radeon_device *rdev);
 213 bool radeon_fence_signaled(struct radeon_fence *fence);
 214 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
 215 int radeon_fence_wait_next(struct radeon_device *rdev);
 216 int radeon_fence_wait_last(struct radeon_device *rdev);
 217 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
 218 void radeon_fence_unref(struct radeon_fence **fence);
 219
 220 /*
 221  * Tiling registers
 222  */
 223 struct radeon_surface_reg {
 224         struct radeon_object *robj;
 225 };
 226
 227 #define RADEON_GEM_MAX_SURFACES 8
 228
 229 /*
 230  * Radeon buffer.
 231  */
 232 struct radeon_object;
 233
 234 struct radeon_object_list {
 235         struct list_head        list;
 236         struct radeon_object    *robj;
 237         uint64_t                gpu_offset;
 238         unsigned                rdomain;
 239         unsigned                wdomain;
 240         uint32_t                tiling_flags;
 241 };
 242
 243 int radeon_object_init(struct radeon_device *rdev);
 244 void radeon_object_fini(struct radeon_device *rdev);
 245 int radeon_object_create(struct radeon_device *rdev,
 246                          struct drm_gem_object *gobj,
 247                          unsigned long size,
 248                          bool kernel,
 249                          uint32_t domain,
 250                          bool interruptible,
 251                          struct radeon_object **robj_ptr);
 252 int radeon_object_kmap(struct radeon_object *robj, void **ptr);
 253 void radeon_object_kunmap(struct radeon_object *robj);
 254 void radeon_object_unref(struct radeon_object **robj);
 255 int radeon_object_pin(struct radeon_object *robj, uint32_t domain,
 256                       uint64_t *gpu_addr);
 257 void radeon_object_unpin(struct radeon_object *robj);
 258 int radeon_object_wait(struct radeon_object *robj);
 259 int radeon_object_busy_domain(struct radeon_object *robj, uint32_t *cur_placement);
 260 int radeon_object_evict_vram(struct radeon_device *rdev);
 261 int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset);
 262 void radeon_object_force_delete(struct radeon_device *rdev);
 263 void radeon_object_list_add_object(struct radeon_object_list *lobj,
 264                                    struct list_head *head);
 265 int radeon_object_list_validate(struct list_head *head, void *fence);
 266 void radeon_object_list_unvalidate(struct list_head *head);
 267 void radeon_object_list_clean(struct list_head *head);
 268 int radeon_object_fbdev_mmap(struct radeon_object *robj,
 269                              struct vm_area_struct *vma);
 270 unsigned long radeon_object_size(struct radeon_object *robj);
 271 void radeon_object_clear_surface_reg(struct radeon_object *robj);
 272 int radeon_object_check_tiling(struct radeon_object *robj, bool has_moved,
 273                                bool force_drop);
 274 void radeon_object_set_tiling_flags(struct radeon_object *robj,
 275                                     uint32_t tiling_flags, uint32_t pitch);
 276 void radeon_object_get_tiling_flags(struct radeon_object *robj, uint32_t *tiling_flags, uint32_t *pitch);
 277 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
 278                            struct ttm_mem_reg *mem);
 279 void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
 280 /*
 281  * GEM objects.
 282  */
 283 struct radeon_gem {
 284         struct list_head        objects;
 285 };
 286
 287 int radeon_gem_init(struct radeon_device *rdev);
 288 void radeon_gem_fini(struct radeon_device *rdev);
 289 int radeon_gem_object_create(struct radeon_device *rdev, int size,
 290                              int alignment, int initial_domain,
 291                              bool discardable, bool kernel,
 292                              bool interruptible,
 293                              struct drm_gem_object **obj);
 294 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
 295                           uint64_t *gpu_addr);
 296 void radeon_gem_object_unpin(struct drm_gem_object *obj);
 297
 298
 299 /*
 300  * GART structures, functions & helpers
 301  */
 302 struct radeon_mc;
 303
 304 struct radeon_gart_table_ram {
 305         volatile uint32_t               *ptr;
 306 };
 307
 308 struct radeon_gart_table_vram {
 309         struct radeon_object            *robj;
 310         volatile uint32_t               *ptr;
 311 };
 312
 313 union radeon_gart_table {
 314         struct radeon_gart_table_ram    ram;
 315         struct radeon_gart_table_vram   vram;
 316 };
 317
 318 struct radeon_gart {
 319         dma_addr_t                      table_addr;
 320         unsigned                        num_gpu_pages;
 321         unsigned                        num_cpu_pages;
 322         unsigned                        table_size;
 323         union radeon_gart_table         table;
 324         struct page                     **pages;
 325         dma_addr_t                      *pages_addr;
 326         bool                            ready;
 327 };
 328
 329 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
 330 void radeon_gart_table_ram_free(struct radeon_device *rdev);
 331 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
 332 void radeon_gart_table_vram_free(struct radeon_device *rdev);
 333 int radeon_gart_init(struct radeon_device *rdev);
 334 void radeon_gart_fini(struct radeon_device *rdev);
 335 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
 336                         int pages);
 337 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
 338                      int pages, struct page **pagelist);
 339
 340
 341 /*
 342  * GPU MC structures, functions & helpers
 343  */
 344 struct radeon_mc {
 345         resource_size_t         aper_size;
 346         resource_size_t         aper_base;
 347         resource_size_t         agp_base;
 348         /* for some chips with <= 32MB we need to lie
 349          * about vram size near mc fb location */
 350         u64                     mc_vram_size;
 351         u64                     gtt_location;
 352         u64                     gtt_size;
 353         u64                     gtt_start;
 354         u64                     gtt_end;
 355         u64                     vram_location;
 356         u64                     vram_start;
 357         u64                     vram_end;
 358         unsigned                vram_width;
 359         u64                     real_vram_size;
 360         int                     vram_mtrr;
 361         bool                    vram_is_ddr;
 362 };
 363
 364 int radeon_mc_setup(struct radeon_device *rdev);
 365
 366
 367 /*
 368  * GPU scratch registers structures, functions & helpers
 369  */
 370 struct radeon_scratch {
 371         unsigned                num_reg;
 372         bool                    free[32];
 373         uint32_t                reg[32];
 374 };
 375
 376 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
 377 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
 378
 379
 380 /*
 381  * IRQS.
 382  */
 383 struct radeon_irq {
 384         bool            installed;
 385         bool            sw_int;
 386         /* FIXME: use a define max crtc rather than hardcode it */
 387         bool            crtc_vblank_int[2];
 388 };
 389
 390 int radeon_irq_kms_init(struct radeon_device *rdev);
 391 void radeon_irq_kms_fini(struct radeon_device *rdev);
 392
 393
 394 /*
 395  * CP & ring.
 396  */
 397 struct radeon_ib {
 398         struct list_head        list;
 399         unsigned long           idx;
 400         uint64_t                gpu_addr;
 401         struct radeon_fence     *fence;
 402         volatile uint32_t       *ptr;
 403         uint32_t                length_dw;
 404 };
 405
 406 struct radeon_ib_pool {
 407         struct mutex            mutex;
 408         struct radeon_object    *robj;
 409         struct list_head        scheduled_ibs;
 410         struct radeon_ib        ibs[RADEON_IB_POOL_SIZE];
 411         bool                    ready;
 412         DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
 413 };
 414
 415 struct radeon_cp {
 416         struct radeon_object    *ring_obj;
 417         volatile uint32_t       *ring;
 418         unsigned                rptr;
 419         unsigned                wptr;
 420         unsigned                wptr_old;
 421         unsigned                ring_size;
 422         unsigned                ring_free_dw;
 423         int                     count_dw;
 424         uint64_t                gpu_addr;
 425         uint32_t                align_mask;
 426         uint32_t                ptr_mask;
 427         struct mutex            mutex;
 428         bool                    ready;
 429 };
 430
 431 struct r600_blit {
 432         struct radeon_object    *shader_obj;
 433         u64 shader_gpu_addr;
 434         u32 vs_offset, ps_offset;
 435         u32 state_offset;
 436         u32 state_len;
 437         u32 vb_used, vb_total;
 438         struct radeon_ib *vb_ib;
 439 };
 440
 441 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
 442 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
 443 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
 444 int radeon_ib_pool_init(struct radeon_device *rdev);
 445 void radeon_ib_pool_fini(struct radeon_device *rdev);
 446 int radeon_ib_test(struct radeon_device *rdev);
 447 /* Ring access between begin & end cannot sleep */
 448 void radeon_ring_free_size(struct radeon_device *rdev);
 449 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
 450 void radeon_ring_unlock_commit(struct radeon_device *rdev);
 451 void radeon_ring_unlock_undo(struct radeon_device *rdev);
 452 int radeon_ring_test(struct radeon_device *rdev);
 453 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
 454 void radeon_ring_fini(struct radeon_device *rdev);
 455
 456
 457 /*
 458  * CS.
 459  */
 460 struct radeon_cs_reloc {
 461         struct drm_gem_object           *gobj;
 462         struct radeon_object            *robj;
 463         struct radeon_object_list       lobj;
 464         uint32_t                        handle;
 465         uint32_t                        flags;
 466 };
 467
 468 struct radeon_cs_chunk {
 469         uint32_t                chunk_id;
 470         uint32_t                length_dw;
 471         uint32_t                *kdata;
 472 };
 473
 474 struct radeon_cs_parser {
 475         struct radeon_device    *rdev;
 476         struct drm_file         *filp;
 477         /* chunks */
 478         unsigned                nchunks;
 479         struct radeon_cs_chunk  *chunks;
 480         uint64_t                *chunks_array;
 481         /* IB */
 482         unsigned                idx;
 483         /* relocations */
 484         unsigned                nrelocs;
 485         struct radeon_cs_reloc  *relocs;
 486         struct radeon_cs_reloc  **relocs_ptr;
 487         struct list_head        validated;
 488         /* indices of various chunks */
 489         int                     chunk_ib_idx;
 490         int                     chunk_relocs_idx;
 491         struct radeon_ib        *ib;
 492         void                    *track;
 493         unsigned                family;
 494 };
 495
 496 struct radeon_cs_packet {
 497         unsigned        idx;
 498         unsigned        type;
 499         unsigned        reg;
 500         unsigned        opcode;
 501         int             count;
 502         unsigned        one_reg_wr;
 503 };
 504
 505 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
 506                                       struct radeon_cs_packet *pkt,
 507                                       unsigned idx, unsigned reg);
 508 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
 509                                       struct radeon_cs_packet *pkt);
 510
 511
 512 /*
 513  * AGP
 514  */
 515 int radeon_agp_init(struct radeon_device *rdev);
 516 void radeon_agp_fini(struct radeon_device *rdev);
 517
 518
 519 /*
 520  * Writeback
 521  */
 522 struct radeon_wb {
 523         struct radeon_object    *wb_obj;
 524         volatile uint32_t       *wb;
 525         uint64_t                gpu_addr;
 526 };
 527
 528 /**
 529  * struct radeon_pm - power management datas
 530  * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
 531  * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
 532  * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
 533  * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
 534  * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
 535  * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
 536  * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
 537  * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
 538  * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
 539  * @sclk:               GPU clock Mhz (core bandwith depends of this clock)
 540  * @needed_bandwidth:   current bandwidth needs
 541  *
 542  * It keeps track of various data needed to take powermanagement decision.
 543  * Bandwith need is used to determine minimun clock of the GPU and memory.
 544  * Equation between gpu/memory clock and available bandwidth is hw dependent
 545  * (type of memory, bus size, efficiency, ...)
 546  */
 547 struct radeon_pm {
 548         fixed20_12              max_bandwidth;
 549         fixed20_12              igp_sideport_mclk;
 550         fixed20_12              igp_system_mclk;
 551         fixed20_12              igp_ht_link_clk;
 552         fixed20_12              igp_ht_link_width;
 553         fixed20_12              k8_bandwidth;
 554         fixed20_12              sideport_bandwidth;
 555         fixed20_12              ht_bandwidth;
 556         fixed20_12              core_bandwidth;
 557         fixed20_12              sclk;
 558         fixed20_12              needed_bandwidth;
 559 };
 560
 561
 562 /*
 563  * Benchmarking
 564  */
 565 void radeon_benchmark(struct radeon_device *rdev);
 566
 567
 568 /*
 569  * Testing
 570  */
 571 void radeon_test_moves(struct radeon_device *rdev);
 572
 573
 574 /*
 575  * Debugfs
 576  */
 577 int radeon_debugfs_add_files(struct radeon_device *rdev,
 578                              struct drm_info_list *files,
 579                              unsigned nfiles);
 580 int radeon_debugfs_fence_init(struct radeon_device *rdev);
 581 int r100_debugfs_rbbm_init(struct radeon_device *rdev);
 582 int r100_debugfs_cp_init(struct radeon_device *rdev);
 583
 584
 585 /*
 586  * ASIC specific functions.
 587  */
 588 struct radeon_asic {
 589         int (*init)(struct radeon_device *rdev);
 590         void (*fini)(struct radeon_device *rdev);
 591         int (*resume)(struct radeon_device *rdev);
 592         int (*suspend)(struct radeon_device *rdev);
 593         void (*errata)(struct radeon_device *rdev);
 594         void (*vram_info)(struct radeon_device *rdev);
 595         int (*gpu_reset)(struct radeon_device *rdev);
 596         int (*mc_init)(struct radeon_device *rdev);
 597         void (*mc_fini)(struct radeon_device *rdev);
 598         int (*wb_init)(struct radeon_device *rdev);
 599         void (*wb_fini)(struct radeon_device *rdev);
 600         int (*gart_enable)(struct radeon_device *rdev);
 601         void (*gart_disable)(struct radeon_device *rdev);
 602         void (*gart_tlb_flush)(struct radeon_device *rdev);
 603         int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
 604         int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
 605         void (*cp_fini)(struct radeon_device *rdev);
 606         void (*cp_disable)(struct radeon_device *rdev);
 607         void (*cp_commit)(struct radeon_device *rdev);
 608         void (*ring_start)(struct radeon_device *rdev);
 609         int (*ring_test)(struct radeon_device *rdev);
 610         void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
 611         int (*ib_test)(struct radeon_device *rdev);
 612         int (*irq_set)(struct radeon_device *rdev);
 613         int (*irq_process)(struct radeon_device *rdev);
 614         u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
 615         void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
 616         int (*cs_parse)(struct radeon_cs_parser *p);
 617         int (*copy_blit)(struct radeon_device *rdev,
 618                          uint64_t src_offset,
 619                          uint64_t dst_offset,
 620                          unsigned num_pages,
 621                          struct radeon_fence *fence);
 622         int (*copy_dma)(struct radeon_device *rdev,
 623                         uint64_t src_offset,
 624                         uint64_t dst_offset,
 625                         unsigned num_pages,
 626                         struct radeon_fence *fence);
 627         int (*copy)(struct radeon_device *rdev,
 628                     uint64_t src_offset,
 629                     uint64_t dst_offset,
 630                     unsigned num_pages,
 631                     struct radeon_fence *fence);
 632         void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
 633         void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
 634         void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
 635         void (*set_clock_gating)(struct radeon_device *rdev, int enable);
 636         int (*set_surface_reg)(struct radeon_device *rdev, int reg,
 637                                uint32_t tiling_flags, uint32_t pitch,
 638                                uint32_t offset, uint32_t obj_size);
 639         int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
 640         void (*bandwidth_update)(struct radeon_device *rdev);
 641 };
 642
 643 struct r100_asic {
 644         const unsigned  *reg_safe_bm;
 645         unsigned        reg_safe_bm_size;
 646 };
 647
 648 union radeon_asic_config {
 649         struct r300_asic        r300;
 650         struct r100_asic        r100;
 651         struct r600_asic        r600;
 652         struct rv770_asic       rv770;
 653 };
 654
 655
 656 /*
 657  * IOCTL.
 658  */
 659 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
 660                           struct drm_file *filp);
 661 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
 662                             struct drm_file *filp);
 663 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
 664                          struct drm_file *file_priv);
 665 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
 666                            struct drm_file *file_priv);
 667 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 668                             struct drm_file *file_priv);
 669 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
 670                            struct drm_file *file_priv);
 671 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 672                                 struct drm_file *filp);
 673 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
 674                           struct drm_file *filp);
 675 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
 676                           struct drm_file *filp);
 677 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
 678                               struct drm_file *filp);
 679 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
 680 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
 681                                 struct drm_file *filp);
 682 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
 683                                 struct drm_file *filp);
 684
 685
 686 /*
 687  * Core structure, functions and helpers.
 688  */
 689 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
 690 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
 691
 692 struct radeon_device {
 693         struct drm_device               *ddev;
 694         struct pci_dev                  *pdev;
 695         /* ASIC */
 696         union radeon_asic_config        config;
 697         enum radeon_family              family;
 698         unsigned long                   flags;
 699         int                             usec_timeout;
 700         enum radeon_pll_errata          pll_errata;
 701         int                             num_gb_pipes;
 702         int                             num_z_pipes;
 703         int                             disp_priority;
 704         /* BIOS */
 705         uint8_t                         *bios;
 706         bool                            is_atom_bios;
 707         uint16_t                        bios_header_start;
 708         struct radeon_object            *stollen_vga_memory;
 709         struct fb_info                  *fbdev_info;
 710         struct radeon_object            *fbdev_robj;
 711         struct radeon_framebuffer       *fbdev_rfb;
 712         /* Register mmio */
 713         resource_size_t                 rmmio_base;
 714         resource_size_t                 rmmio_size;
 715         void                            *rmmio;
 716         radeon_rreg_t                   mc_rreg;
 717         radeon_wreg_t                   mc_wreg;
 718         radeon_rreg_t                   pll_rreg;
 719         radeon_wreg_t                   pll_wreg;
 720         uint32_t                        pcie_reg_mask;
 721         radeon_rreg_t                   pciep_rreg;
 722         radeon_wreg_t                   pciep_wreg;
 723         struct radeon_clock             clock;
 724         struct radeon_mc                mc;
 725         struct radeon_gart              gart;
 726         struct radeon_mode_info         mode_info;
 727         struct radeon_scratch           scratch;
 728         struct radeon_mman              mman;
 729         struct radeon_fence_driver      fence_drv;
 730         struct radeon_cp                cp;
 731         struct radeon_ib_pool           ib_pool;
 732         struct radeon_irq               irq;
 733         struct radeon_asic              *asic;
 734         struct radeon_gem               gem;
 735         struct radeon_pm                pm;
 736         struct mutex                    cs_mutex;
 737         struct radeon_wb                wb;
 738         struct radeon_dummy_page        dummy_page;
 739         bool                            gpu_lockup;
 740         bool                            shutdown;
 741         bool                            suspend;
 742         bool                            need_dma32;
 743         bool                            new_init_path;
 744         struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
 745         const struct firmware *me_fw;   /* all family ME firmware */
 746         const struct firmware *pfp_fw;  /* r6/700 PFP firmware */
 747         struct r600_blit r600_blit;
 748 };
 749
 750 int radeon_device_init(struct radeon_device *rdev,
 751                        struct drm_device *ddev,
 752                        struct pci_dev *pdev,
 753                        uint32_t flags);
 754 void radeon_device_fini(struct radeon_device *rdev);
 755 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
 756
 757 /* r600 blit */
 758 int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
 759 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
 760 void r600_kms_blit_copy(struct radeon_device *rdev,
 761                         u64 src_gpu_addr, u64 dst_gpu_addr,
 762                         int size_bytes);
 763
 764 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
 765 {
 766         if (reg < 0x10000)
 767                 return readl(((void __iomem *)rdev->rmmio) + reg);
 768         else {
 769                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
 770                 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
 771         }
 772 }
 773
 774 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 775 {
 776         if (reg < 0x10000)
 777                 writel(v, ((void __iomem *)rdev->rmmio) + reg);
 778         else {
 779                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
 780                 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
 781         }
 782 }
 783
 784
 785 /*
 786  * Registers read & write functions.
 787  */
 788 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
 789 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
 790 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
 791 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
 792 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
 793 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
 794 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
 795 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
 796 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
 797 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
 798 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
 799 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
 800 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
 801 #define WREG32_P(reg, val, mask)                                \
 802         do {                                                    \
 803                 uint32_t tmp_ = RREG32(reg);                    \
 804                 tmp_ &= (mask);                                 \
 805                 tmp_ |= ((val) & ~(mask));                      \
 806                 WREG32(reg, tmp_);                              \
 807         } while (0)
 808 #define WREG32_PLL_P(reg, val, mask)                            \
 809         do {                                                    \
 810                 uint32_t tmp_ = RREG32_PLL(reg);                \
 811                 tmp_ &= (mask);                                 \
 812                 tmp_ |= ((val) & ~(mask));                      \
 813                 WREG32_PLL(reg, tmp_);                          \
 814         } while (0)
 815 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
 816
 817 /*
 818  * Indirect registers accessor
 819  */
 820 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
 821 {
 822         uint32_t r;
 823
 824         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
 825         r = RREG32(RADEON_PCIE_DATA);
 826         return r;
 827 }
 828
 829 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 830 {
 831         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
 832         WREG32(RADEON_PCIE_DATA, (v));
 833 }
 834
 835 void r100_pll_errata_after_index(struct radeon_device *rdev);
 836
 837
 838 /*
 839  * ASICs helpers.
 840  */
 841 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
 842                             (rdev->pdev->device == 0x5969))
 843 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
 844                 (rdev->family == CHIP_RV200) || \
 845                 (rdev->family == CHIP_RS100) || \
 846                 (rdev->family == CHIP_RS200) || \
 847                 (rdev->family == CHIP_RV250) || \
 848                 (rdev->family == CHIP_RV280) || \
 849                 (rdev->family == CHIP_RS300))
 850 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  ||     \
 851                 (rdev->family == CHIP_RV350) ||                 \
 852                 (rdev->family == CHIP_R350)  ||                 \
 853                 (rdev->family == CHIP_RV380) ||                 \
 854                 (rdev->family == CHIP_R420)  ||                 \
 855                 (rdev->family == CHIP_R423)  ||                 \
 856                 (rdev->family == CHIP_RV410) ||                 \
 857                 (rdev->family == CHIP_RS400) ||                 \
 858                 (rdev->family == CHIP_RS480))
 859 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
 860 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
 861 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
 862
 863
 864 /*
 865  * BIOS helpers.
 866  */
 867 #define RBIOS8(i) (rdev->bios[i])
 868 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
 869 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
 870
 871 int radeon_combios_init(struct radeon_device *rdev);
 872 void radeon_combios_fini(struct radeon_device *rdev);
 873 int radeon_atombios_init(struct radeon_device *rdev);
 874 void radeon_atombios_fini(struct radeon_device *rdev);
 875
 876
 877 /*
 878  * RING helpers.
 879  */
 880 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
 881 {
 882 #if DRM_DEBUG_CODE
 883         if (rdev->cp.count_dw <= 0) {
 884                 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
 885         }
 886 #endif
 887         rdev->cp.ring[rdev->cp.wptr++] = v;
 888         rdev->cp.wptr &= rdev->cp.ptr_mask;
 889         rdev->cp.count_dw--;
 890         rdev->cp.ring_free_dw--;
 891 }
 892
 893
 894 /*
 895  * ASICs macro.
 896  */
 897 #define radeon_init(rdev) (rdev)->asic->init((rdev))
 898 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
 899 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
 900 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
 901 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
 902 #define radeon_errata(rdev) (rdev)->asic->errata((rdev))
 903 #define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev))
 904 #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
 905 #define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev))
 906 #define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev))
 907 #define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev))
 908 #define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev))
 909 #define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev))
 910 #define radeon_gart_disable(rdev) (rdev)->asic->gart_disable((rdev))
 911 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
 912 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
 913 #define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize))
 914 #define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev))
 915 #define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev))
 916 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
 917 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
 918 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
 919 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
 920 #define radeon_ib_test(rdev) (rdev)->asic->ib_test((rdev))
 921 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
 922 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
 923 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
 924 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
 925 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
 926 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
 927 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
 928 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
 929 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
 930 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
 931 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
 932 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
 933 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
 934 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
 935
 936 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
 937 void r100_cp_disable(struct radeon_device *rdev);
 938
 939 #endif