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iommu/arm-smmu: avoid calling request_irq in atomic context
[linux-2.6/btrfs-unstable.git] / drivers / iommu / arm-smmu.c
blob98fcd87cbacb72e6b921bef3e2ab8dab930cd430
1 /*
2 * IOMMU API for ARM architected SMMU implementations.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
16 *
17 * Copyright (C) 2013 ARM Limited
18 *
19 * Author: Will Deacon <will.deacon@arm.com>
20 *
21 * This driver currently supports:
22 * - SMMUv1 and v2 implementations
23 * - Stream-matching and stream-indexing
24 * - v7/v8 long-descriptor format
25 * - Non-secure access to the SMMU
26 * - 4k and 64k pages, with contiguous pte hints.
27 * - Up to 42-bit addressing (dependent on VA_BITS)
28 * - Context fault reporting
29 */
30
31 #define pr_fmt(fmt) "arm-smmu: " fmt
32
33 #include <linux/delay.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/err.h>
36 #include <linux/interrupt.h>
37 #include <linux/io.h>
38 #include <linux/iommu.h>
39 #include <linux/mm.h>
40 #include <linux/module.h>
41 #include <linux/of.h>
42 #include <linux/pci.h>
43 #include <linux/platform_device.h>
44 #include <linux/slab.h>
45 #include <linux/spinlock.h>
46
47 #include <linux/amba/bus.h>
48
49 #include <asm/pgalloc.h>
50
51 /* Maximum number of stream IDs assigned to a single device */
52 #define MAX_MASTER_STREAMIDS MAX_PHANDLE_ARGS
53
54 /* Maximum number of context banks per SMMU */
55 #define ARM_SMMU_MAX_CBS 128
56
57 /* Maximum number of mapping groups per SMMU */
58 #define ARM_SMMU_MAX_SMRS 128
59
60 /* SMMU global address space */
61 #define ARM_SMMU_GR0(smmu) ((smmu)->base)
62 #define ARM_SMMU_GR1(smmu) ((smmu)->base + (smmu)->pagesize)
63
64 /*
65 * SMMU global address space with conditional offset to access secure
66 * aliases of non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448,
67 * nsGFSYNR0: 0x450)
68 */
69 #define ARM_SMMU_GR0_NS(smmu) \
70 ((smmu)->base + \
71 ((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS) \
72 ? 0x400 : 0))
73
74 /* Page table bits */
75 #define ARM_SMMU_PTE_XN (((pteval_t)3) << 53)
76 #define ARM_SMMU_PTE_CONT (((pteval_t)1) << 52)
77 #define ARM_SMMU_PTE_AF (((pteval_t)1) << 10)
78 #define ARM_SMMU_PTE_SH_NS (((pteval_t)0) << 8)
79 #define ARM_SMMU_PTE_SH_OS (((pteval_t)2) << 8)
80 #define ARM_SMMU_PTE_SH_IS (((pteval_t)3) << 8)
81 #define ARM_SMMU_PTE_PAGE (((pteval_t)3) << 0)
82
83 #if PAGE_SIZE == SZ_4K
84 #define ARM_SMMU_PTE_CONT_ENTRIES 16
85 #elif PAGE_SIZE == SZ_64K
86 #define ARM_SMMU_PTE_CONT_ENTRIES 32
87 #else
88 #define ARM_SMMU_PTE_CONT_ENTRIES 1
89 #endif
90
91 #define ARM_SMMU_PTE_CONT_SIZE (PAGE_SIZE * ARM_SMMU_PTE_CONT_ENTRIES)
92 #define ARM_SMMU_PTE_CONT_MASK (~(ARM_SMMU_PTE_CONT_SIZE - 1))
93
94 /* Stage-1 PTE */
95 #define ARM_SMMU_PTE_AP_UNPRIV (((pteval_t)1) << 6)
96 #define ARM_SMMU_PTE_AP_RDONLY (((pteval_t)2) << 6)
97 #define ARM_SMMU_PTE_ATTRINDX_SHIFT 2
98 #define ARM_SMMU_PTE_nG (((pteval_t)1) << 11)
99
100 /* Stage-2 PTE */
101 #define ARM_SMMU_PTE_HAP_FAULT (((pteval_t)0) << 6)
102 #define ARM_SMMU_PTE_HAP_READ (((pteval_t)1) << 6)
103 #define ARM_SMMU_PTE_HAP_WRITE (((pteval_t)2) << 6)
104 #define ARM_SMMU_PTE_MEMATTR_OIWB (((pteval_t)0xf) << 2)
105 #define ARM_SMMU_PTE_MEMATTR_NC (((pteval_t)0x5) << 2)
106 #define ARM_SMMU_PTE_MEMATTR_DEV (((pteval_t)0x1) << 2)
107
108 /* Configuration registers */
109 #define ARM_SMMU_GR0_sCR0 0x0
110 #define sCR0_CLIENTPD (1 << 0)
111 #define sCR0_GFRE (1 << 1)
112 #define sCR0_GFIE (1 << 2)
113 #define sCR0_GCFGFRE (1 << 4)
114 #define sCR0_GCFGFIE (1 << 5)
115 #define sCR0_USFCFG (1 << 10)
116 #define sCR0_VMIDPNE (1 << 11)
117 #define sCR0_PTM (1 << 12)
118 #define sCR0_FB (1 << 13)
119 #define sCR0_BSU_SHIFT 14
120 #define sCR0_BSU_MASK 0x3
121
122 /* Identification registers */
123 #define ARM_SMMU_GR0_ID0 0x20
124 #define ARM_SMMU_GR0_ID1 0x24
125 #define ARM_SMMU_GR0_ID2 0x28
126 #define ARM_SMMU_GR0_ID3 0x2c
127 #define ARM_SMMU_GR0_ID4 0x30
128 #define ARM_SMMU_GR0_ID5 0x34
129 #define ARM_SMMU_GR0_ID6 0x38
130 #define ARM_SMMU_GR0_ID7 0x3c
131 #define ARM_SMMU_GR0_sGFSR 0x48
132 #define ARM_SMMU_GR0_sGFSYNR0 0x50
133 #define ARM_SMMU_GR0_sGFSYNR1 0x54
134 #define ARM_SMMU_GR0_sGFSYNR2 0x58
135 #define ARM_SMMU_GR0_PIDR0 0xfe0
136 #define ARM_SMMU_GR0_PIDR1 0xfe4
137 #define ARM_SMMU_GR0_PIDR2 0xfe8
138
139 #define ID0_S1TS (1 << 30)
140 #define ID0_S2TS (1 << 29)
141 #define ID0_NTS (1 << 28)
142 #define ID0_SMS (1 << 27)
143 #define ID0_PTFS_SHIFT 24
144 #define ID0_PTFS_MASK 0x2
145 #define ID0_PTFS_V8_ONLY 0x2
146 #define ID0_CTTW (1 << 14)
147 #define ID0_NUMIRPT_SHIFT 16
148 #define ID0_NUMIRPT_MASK 0xff
149 #define ID0_NUMSMRG_SHIFT 0
150 #define ID0_NUMSMRG_MASK 0xff
151
152 #define ID1_PAGESIZE (1 << 31)
153 #define ID1_NUMPAGENDXB_SHIFT 28
154 #define ID1_NUMPAGENDXB_MASK 7
155 #define ID1_NUMS2CB_SHIFT 16
156 #define ID1_NUMS2CB_MASK 0xff
157 #define ID1_NUMCB_SHIFT 0
158 #define ID1_NUMCB_MASK 0xff
159
160 #define ID2_OAS_SHIFT 4
161 #define ID2_OAS_MASK 0xf
162 #define ID2_IAS_SHIFT 0
163 #define ID2_IAS_MASK 0xf
164 #define ID2_UBS_SHIFT 8
165 #define ID2_UBS_MASK 0xf
166 #define ID2_PTFS_4K (1 << 12)
167 #define ID2_PTFS_16K (1 << 13)
168 #define ID2_PTFS_64K (1 << 14)
169
170 #define PIDR2_ARCH_SHIFT 4
171 #define PIDR2_ARCH_MASK 0xf
172
173 /* Global TLB invalidation */
174 #define ARM_SMMU_GR0_STLBIALL 0x60
175 #define ARM_SMMU_GR0_TLBIVMID 0x64
176 #define ARM_SMMU_GR0_TLBIALLNSNH 0x68
177 #define ARM_SMMU_GR0_TLBIALLH 0x6c
178 #define ARM_SMMU_GR0_sTLBGSYNC 0x70
179 #define ARM_SMMU_GR0_sTLBGSTATUS 0x74
180 #define sTLBGSTATUS_GSACTIVE (1 << 0)
181 #define TLB_LOOP_TIMEOUT 1000000 /* 1s! */
182
183 /* Stream mapping registers */
184 #define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2))
185 #define SMR_VALID (1 << 31)
186 #define SMR_MASK_SHIFT 16
187 #define SMR_MASK_MASK 0x7fff
188 #define SMR_ID_SHIFT 0
189 #define SMR_ID_MASK 0x7fff
190
191 #define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2))
192 #define S2CR_CBNDX_SHIFT 0
193 #define S2CR_CBNDX_MASK 0xff
194 #define S2CR_TYPE_SHIFT 16
195 #define S2CR_TYPE_MASK 0x3
196 #define S2CR_TYPE_TRANS (0 << S2CR_TYPE_SHIFT)
197 #define S2CR_TYPE_BYPASS (1 << S2CR_TYPE_SHIFT)
198 #define S2CR_TYPE_FAULT (2 << S2CR_TYPE_SHIFT)
199
200 /* Context bank attribute registers */
201 #define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2))
202 #define CBAR_VMID_SHIFT 0
203 #define CBAR_VMID_MASK 0xff
204 #define CBAR_S1_BPSHCFG_SHIFT 8
205 #define CBAR_S1_BPSHCFG_MASK 3
206 #define CBAR_S1_BPSHCFG_NSH 3
207 #define CBAR_S1_MEMATTR_SHIFT 12
208 #define CBAR_S1_MEMATTR_MASK 0xf
209 #define CBAR_S1_MEMATTR_WB 0xf
210 #define CBAR_TYPE_SHIFT 16
211 #define CBAR_TYPE_MASK 0x3
212 #define CBAR_TYPE_S2_TRANS (0 << CBAR_TYPE_SHIFT)
213 #define CBAR_TYPE_S1_TRANS_S2_BYPASS (1 << CBAR_TYPE_SHIFT)
214 #define CBAR_TYPE_S1_TRANS_S2_FAULT (2 << CBAR_TYPE_SHIFT)
215 #define CBAR_TYPE_S1_TRANS_S2_TRANS (3 << CBAR_TYPE_SHIFT)
216 #define CBAR_IRPTNDX_SHIFT 24
217 #define CBAR_IRPTNDX_MASK 0xff
218
219 #define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2))
220 #define CBA2R_RW64_32BIT (0 << 0)
221 #define CBA2R_RW64_64BIT (1 << 0)
222
223 /* Translation context bank */
224 #define ARM_SMMU_CB_BASE(smmu) ((smmu)->base + ((smmu)->size >> 1))
225 #define ARM_SMMU_CB(smmu, n) ((n) * (smmu)->pagesize)
226
227 #define ARM_SMMU_CB_SCTLR 0x0
228 #define ARM_SMMU_CB_RESUME 0x8
229 #define ARM_SMMU_CB_TTBCR2 0x10
230 #define ARM_SMMU_CB_TTBR0_LO 0x20
231 #define ARM_SMMU_CB_TTBR0_HI 0x24
232 #define ARM_SMMU_CB_TTBCR 0x30
233 #define ARM_SMMU_CB_S1_MAIR0 0x38
234 #define ARM_SMMU_CB_FSR 0x58
235 #define ARM_SMMU_CB_FAR_LO 0x60
236 #define ARM_SMMU_CB_FAR_HI 0x64
237 #define ARM_SMMU_CB_FSYNR0 0x68
238 #define ARM_SMMU_CB_S1_TLBIASID 0x610
239
240 #define SCTLR_S1_ASIDPNE (1 << 12)
241 #define SCTLR_CFCFG (1 << 7)
242 #define SCTLR_CFIE (1 << 6)
243 #define SCTLR_CFRE (1 << 5)
244 #define SCTLR_E (1 << 4)
245 #define SCTLR_AFE (1 << 2)
246 #define SCTLR_TRE (1 << 1)
247 #define SCTLR_M (1 << 0)
248 #define SCTLR_EAE_SBOP (SCTLR_AFE | SCTLR_TRE)
249
250 #define RESUME_RETRY (0 << 0)
251 #define RESUME_TERMINATE (1 << 0)
252
253 #define TTBCR_EAE (1 << 31)
254
255 #define TTBCR_PASIZE_SHIFT 16
256 #define TTBCR_PASIZE_MASK 0x7
257
258 #define TTBCR_TG0_4K (0 << 14)
259 #define TTBCR_TG0_64K (1 << 14)
260
261 #define TTBCR_SH0_SHIFT 12
262 #define TTBCR_SH0_MASK 0x3
263 #define TTBCR_SH_NS 0
264 #define TTBCR_SH_OS 2
265 #define TTBCR_SH_IS 3
266
267 #define TTBCR_ORGN0_SHIFT 10
268 #define TTBCR_IRGN0_SHIFT 8
269 #define TTBCR_RGN_MASK 0x3
270 #define TTBCR_RGN_NC 0
271 #define TTBCR_RGN_WBWA 1
272 #define TTBCR_RGN_WT 2
273 #define TTBCR_RGN_WB 3
274
275 #define TTBCR_SL0_SHIFT 6
276 #define TTBCR_SL0_MASK 0x3
277 #define TTBCR_SL0_LVL_2 0
278 #define TTBCR_SL0_LVL_1 1
279
280 #define TTBCR_T1SZ_SHIFT 16
281 #define TTBCR_T0SZ_SHIFT 0
282 #define TTBCR_SZ_MASK 0xf
283
284 #define TTBCR2_SEP_SHIFT 15
285 #define TTBCR2_SEP_MASK 0x7
286
287 #define TTBCR2_PASIZE_SHIFT 0
288 #define TTBCR2_PASIZE_MASK 0x7
289
290 /* Common definitions for PASize and SEP fields */
291 #define TTBCR2_ADDR_32 0
292 #define TTBCR2_ADDR_36 1
293 #define TTBCR2_ADDR_40 2
294 #define TTBCR2_ADDR_42 3
295 #define TTBCR2_ADDR_44 4
296 #define TTBCR2_ADDR_48 5
297
298 #define TTBRn_HI_ASID_SHIFT 16
299
300 #define MAIR_ATTR_SHIFT(n) ((n) << 3)
301 #define MAIR_ATTR_MASK 0xff
302 #define MAIR_ATTR_DEVICE 0x04
303 #define MAIR_ATTR_NC 0x44
304 #define MAIR_ATTR_WBRWA 0xff
305 #define MAIR_ATTR_IDX_NC 0
306 #define MAIR_ATTR_IDX_CACHE 1
307 #define MAIR_ATTR_IDX_DEV 2
308
309 #define FSR_MULTI (1 << 31)
310 #define FSR_SS (1 << 30)
311 #define FSR_UUT (1 << 8)
312 #define FSR_ASF (1 << 7)
313 #define FSR_TLBLKF (1 << 6)
314 #define FSR_TLBMCF (1 << 5)
315 #define FSR_EF (1 << 4)
316 #define FSR_PF (1 << 3)
317 #define FSR_AFF (1 << 2)
318 #define FSR_TF (1 << 1)
319
320 #define FSR_IGN (FSR_AFF | FSR_ASF | \
321 FSR_TLBMCF | FSR_TLBLKF)
322 #define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \
323 FSR_EF | FSR_PF | FSR_TF | FSR_IGN)
324
325 #define FSYNR0_WNR (1 << 4)
326
327 struct arm_smmu_smr {
328 u8 idx;
329 u16 mask;
330 u16 id;
331 };
332
333 struct arm_smmu_master_cfg {
334 int num_streamids;
335 u16 streamids[MAX_MASTER_STREAMIDS];
336 struct arm_smmu_smr *smrs;
337 };
338
339 struct arm_smmu_master {
340 struct device_node *of_node;
341 struct rb_node node;
342 struct arm_smmu_master_cfg cfg;
343 };
344
345 struct arm_smmu_device {
346 struct device *dev;
347
348 void __iomem *base;
349 unsigned long size;
350 unsigned long pagesize;
351
352 #define ARM_SMMU_FEAT_COHERENT_WALK (1 << 0)
353 #define ARM_SMMU_FEAT_STREAM_MATCH (1 << 1)
354 #define ARM_SMMU_FEAT_TRANS_S1 (1 << 2)
355 #define ARM_SMMU_FEAT_TRANS_S2 (1 << 3)
356 #define ARM_SMMU_FEAT_TRANS_NESTED (1 << 4)
357 u32 features;
358
359 #define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0)
360 u32 options;
361 int version;
362
363 u32 num_context_banks;
364 u32 num_s2_context_banks;
365 DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS);
366 atomic_t irptndx;
367
368 u32 num_mapping_groups;
369 DECLARE_BITMAP(smr_map, ARM_SMMU_MAX_SMRS);
370
371 unsigned long input_size;
372 unsigned long s1_output_size;
373 unsigned long s2_output_size;
374
375 u32 num_global_irqs;
376 u32 num_context_irqs;
377 unsigned int *irqs;
378
379 struct list_head list;
380 struct rb_root masters;
381 };
382
383 struct arm_smmu_cfg {
384 u8 cbndx;
385 u8 irptndx;
386 u32 cbar;
387 pgd_t *pgd;
388 };
389 #define INVALID_IRPTNDX 0xff
390
391 #define ARM_SMMU_CB_ASID(cfg) ((cfg)->cbndx)
392 #define ARM_SMMU_CB_VMID(cfg) ((cfg)->cbndx + 1)
393
394 struct arm_smmu_domain {
395 struct arm_smmu_device *smmu;
396 struct arm_smmu_cfg cfg;
397 spinlock_t lock;
398 };
399
400 static DEFINE_SPINLOCK(arm_smmu_devices_lock);
401 static LIST_HEAD(arm_smmu_devices);
402
403 struct arm_smmu_option_prop {
404 u32 opt;
405 const char *prop;
406 };
407
408 static struct arm_smmu_option_prop arm_smmu_options[] = {
409 { ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" },
410 { 0, NULL},
411 };
412
413 static void parse_driver_options(struct arm_smmu_device *smmu)
414 {
415 int i = 0;
416
417 do {
418 if (of_property_read_bool(smmu->dev->of_node,
419 arm_smmu_options[i].prop)) {
420 smmu->options |= arm_smmu_options[i].opt;
421 dev_notice(smmu->dev, "option %s\n",
422 arm_smmu_options[i].prop);
423 }
424 } while (arm_smmu_options[++i].opt);
425 }
426
427 static struct device *dev_get_master_dev(struct device *dev)
428 {
429 if (dev_is_pci(dev)) {
430 struct pci_bus *bus = to_pci_dev(dev)->bus;
431
432 while (!pci_is_root_bus(bus))
433 bus = bus->parent;
434 return bus->bridge->parent;
435 }
436
437 return dev;
438 }
439
440 static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu,
441 struct device_node *dev_node)
442 {
443 struct rb_node *node = smmu->masters.rb_node;
444
445 while (node) {
446 struct arm_smmu_master *master;
447
448 master = container_of(node, struct arm_smmu_master, node);
449
450 if (dev_node < master->of_node)
451 node = node->rb_left;
452 else if (dev_node > master->of_node)
453 node = node->rb_right;
454 else
455 return master;
456 }
457
458 return NULL;
459 }
460
461 static struct arm_smmu_master_cfg *
462 find_smmu_master_cfg(struct arm_smmu_device *smmu, struct device *dev)
463 {
464 struct arm_smmu_master *master;
465
466 if (dev_is_pci(dev))
467 return dev->archdata.iommu;
468
469 master = find_smmu_master(smmu, dev->of_node);
470 return master ? &master->cfg : NULL;
471 }
472
473 static int insert_smmu_master(struct arm_smmu_device *smmu,
474 struct arm_smmu_master *master)
475 {
476 struct rb_node **new, *parent;
477
478 new = &smmu->masters.rb_node;
479 parent = NULL;
480 while (*new) {
481 struct arm_smmu_master *this
482 = container_of(*new, struct arm_smmu_master, node);
483
484 parent = *new;
485 if (master->of_node < this->of_node)
486 new = &((*new)->rb_left);
487 else if (master->of_node > this->of_node)
488 new = &((*new)->rb_right);
489 else
490 return -EEXIST;
491 }
492
493 rb_link_node(&master->node, parent, new);
494 rb_insert_color(&master->node, &smmu->masters);
495 return 0;
496 }
497
498 static int register_smmu_master(struct arm_smmu_device *smmu,
499 struct device *dev,
500 struct of_phandle_args *masterspec)
501 {
502 int i;
503 struct arm_smmu_master *master;
504
505 master = find_smmu_master(smmu, masterspec->np);
506 if (master) {
507 dev_err(dev,
508 "rejecting multiple registrations for master device %s\n",
509 masterspec->np->name);
510 return -EBUSY;
511 }
512
513 if (masterspec->args_count > MAX_MASTER_STREAMIDS) {
514 dev_err(dev,
515 "reached maximum number (%d) of stream IDs for master device %s\n",
516 MAX_MASTER_STREAMIDS, masterspec->np->name);
517 return -ENOSPC;
518 }
519
520 master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL);
521 if (!master)
522 return -ENOMEM;
523
524 master->of_node = masterspec->np;
525 master->cfg.num_streamids = masterspec->args_count;
526
527 for (i = 0; i < master->cfg.num_streamids; ++i)
528 master->cfg.streamids[i] = masterspec->args[i];
529
530 return insert_smmu_master(smmu, master);
531 }
532
533 static struct arm_smmu_device *find_smmu_for_device(struct device *dev)
534 {
535 struct arm_smmu_device *smmu;
536 struct arm_smmu_master *master = NULL;
537 struct device_node *dev_node = dev_get_master_dev(dev)->of_node;
538
539 spin_lock(&arm_smmu_devices_lock);
540 list_for_each_entry(smmu, &arm_smmu_devices, list) {
541 master = find_smmu_master(smmu, dev_node);
542 if (master)
543 break;
544 }
545 spin_unlock(&arm_smmu_devices_lock);
546
547 return master ? smmu : NULL;
548 }
549
550 static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end)
551 {
552 int idx;
553
554 do {
555 idx = find_next_zero_bit(map, end, start);
556 if (idx == end)
557 return -ENOSPC;
558 } while (test_and_set_bit(idx, map));
559
560 return idx;
561 }
562
563 static void __arm_smmu_free_bitmap(unsigned long *map, int idx)
564 {
565 clear_bit(idx, map);
566 }
567
568 /* Wait for any pending TLB invalidations to complete */
569 static void arm_smmu_tlb_sync(struct arm_smmu_device *smmu)
570 {
571 int count = 0;
572 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
573
574 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC);
575 while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS)
576 & sTLBGSTATUS_GSACTIVE) {
577 cpu_relax();
578 if (++count == TLB_LOOP_TIMEOUT) {
579 dev_err_ratelimited(smmu->dev,
580 "TLB sync timed out -- SMMU may be deadlocked\n");
581 return;
582 }
583 udelay(1);
584 }
585 }
586
587 static void arm_smmu_tlb_inv_context(struct arm_smmu_domain *smmu_domain)
588 {
589 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
590 struct arm_smmu_device *smmu = smmu_domain->smmu;
591 void __iomem *base = ARM_SMMU_GR0(smmu);
592 bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
593
594 if (stage1) {
595 base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
596 writel_relaxed(ARM_SMMU_CB_ASID(cfg),
597 base + ARM_SMMU_CB_S1_TLBIASID);
598 } else {
599 base = ARM_SMMU_GR0(smmu);
600 writel_relaxed(ARM_SMMU_CB_VMID(cfg),
601 base + ARM_SMMU_GR0_TLBIVMID);
602 }
603
604 arm_smmu_tlb_sync(smmu);
605 }
606
607 static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
608 {
609 int flags, ret;
610 u32 fsr, far, fsynr, resume;
611 unsigned long iova;
612 struct iommu_domain *domain = dev;
613 struct arm_smmu_domain *smmu_domain = domain->priv;
614 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
615 struct arm_smmu_device *smmu = smmu_domain->smmu;
616 void __iomem *cb_base;
617
618 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
619 fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR);
620
621 if (!(fsr & FSR_FAULT))
622 return IRQ_NONE;
623
624 if (fsr & FSR_IGN)
625 dev_err_ratelimited(smmu->dev,
626 "Unexpected context fault (fsr 0x%u)\n",
627 fsr);
628
629 fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
630 flags = fsynr & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ;
631
632 far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_LO);
633 iova = far;
634 #ifdef CONFIG_64BIT
635 far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_HI);
636 iova |= ((unsigned long)far << 32);
637 #endif
638
639 if (!report_iommu_fault(domain, smmu->dev, iova, flags)) {
640 ret = IRQ_HANDLED;
641 resume = RESUME_RETRY;
642 } else {
643 dev_err_ratelimited(smmu->dev,
644 "Unhandled context fault: iova=0x%08lx, fsynr=0x%x, cb=%d\n",
645 iova, fsynr, cfg->cbndx);
646 ret = IRQ_NONE;
647 resume = RESUME_TERMINATE;
648 }
649
650 /* Clear the faulting FSR */
651 writel(fsr, cb_base + ARM_SMMU_CB_FSR);
652
653 /* Retry or terminate any stalled transactions */
654 if (fsr & FSR_SS)
655 writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME);
656
657 return ret;
658 }
659
660 static irqreturn_t arm_smmu_global_fault(int irq, void *dev)
661 {
662 u32 gfsr, gfsynr0, gfsynr1, gfsynr2;
663 struct arm_smmu_device *smmu = dev;
664 void __iomem *gr0_base = ARM_SMMU_GR0_NS(smmu);
665
666 gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
667 gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0);
668 gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1);
669 gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2);
670
671 if (!gfsr)
672 return IRQ_NONE;
673
674 dev_err_ratelimited(smmu->dev,
675 "Unexpected global fault, this could be serious\n");
676 dev_err_ratelimited(smmu->dev,
677 "\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n",
678 gfsr, gfsynr0, gfsynr1, gfsynr2);
679
680 writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR);
681 return IRQ_HANDLED;
682 }
683
684 static void arm_smmu_flush_pgtable(struct arm_smmu_device *smmu, void *addr,
685 size_t size)
686 {
687 unsigned long offset = (unsigned long)addr & ~PAGE_MASK;
688
689
690 /* Ensure new page tables are visible to the hardware walker */
691 if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) {
692 dsb(ishst);
693 } else {
694 /*
695 * If the SMMU can't walk tables in the CPU caches, treat them
696 * like non-coherent DMA since we need to flush the new entries
697 * all the way out to memory. There's no possibility of
698 * recursion here as the SMMU table walker will not be wired
699 * through another SMMU.
700 */
701 dma_map_page(smmu->dev, virt_to_page(addr), offset, size,
702 DMA_TO_DEVICE);
703 }
704 }
705
706 static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
707 {
708 u32 reg;
709 bool stage1;
710 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
711 struct arm_smmu_device *smmu = smmu_domain->smmu;
712 void __iomem *cb_base, *gr0_base, *gr1_base;
713
714 gr0_base = ARM_SMMU_GR0(smmu);
715 gr1_base = ARM_SMMU_GR1(smmu);
716 stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
717 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
718
719 /* CBAR */
720 reg = cfg->cbar;
721 if (smmu->version == 1)
722 reg |= cfg->irptndx << CBAR_IRPTNDX_SHIFT;
723
724 /*
725 * Use the weakest shareability/memory types, so they are
726 * overridden by the ttbcr/pte.
727 */
728 if (stage1) {
729 reg |= (CBAR_S1_BPSHCFG_NSH << CBAR_S1_BPSHCFG_SHIFT) |
730 (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT);
731 } else {
732 reg |= ARM_SMMU_CB_VMID(cfg) << CBAR_VMID_SHIFT;
733 }
734 writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx));
735
736 if (smmu->version > 1) {
737 /* CBA2R */
738 #ifdef CONFIG_64BIT
739 reg = CBA2R_RW64_64BIT;
740 #else
741 reg = CBA2R_RW64_32BIT;
742 #endif
743 writel_relaxed(reg,
744 gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx));
745
746 /* TTBCR2 */
747 switch (smmu->input_size) {
748 case 32:
749 reg = (TTBCR2_ADDR_32 << TTBCR2_SEP_SHIFT);
750 break;
751 case 36:
752 reg = (TTBCR2_ADDR_36 << TTBCR2_SEP_SHIFT);
753 break;
754 case 39:
755 reg = (TTBCR2_ADDR_40 << TTBCR2_SEP_SHIFT);
756 break;
757 case 42:
758 reg = (TTBCR2_ADDR_42 << TTBCR2_SEP_SHIFT);
759 break;
760 case 44:
761 reg = (TTBCR2_ADDR_44 << TTBCR2_SEP_SHIFT);
762 break;
763 case 48:
764 reg = (TTBCR2_ADDR_48 << TTBCR2_SEP_SHIFT);
765 break;
766 }
767
768 switch (smmu->s1_output_size) {
769 case 32:
770 reg |= (TTBCR2_ADDR_32 << TTBCR2_PASIZE_SHIFT);
771 break;
772 case 36:
773 reg |= (TTBCR2_ADDR_36 << TTBCR2_PASIZE_SHIFT);
774 break;
775 case 39:
776 reg |= (TTBCR2_ADDR_40 << TTBCR2_PASIZE_SHIFT);
777 break;
778 case 42:
779 reg |= (TTBCR2_ADDR_42 << TTBCR2_PASIZE_SHIFT);
780 break;
781 case 44:
782 reg |= (TTBCR2_ADDR_44 << TTBCR2_PASIZE_SHIFT);
783 break;
784 case 48:
785 reg |= (TTBCR2_ADDR_48 << TTBCR2_PASIZE_SHIFT);
786 break;
787 }
788
789 if (stage1)
790 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2);
791 }
792
793 /* TTBR0 */
794 arm_smmu_flush_pgtable(smmu, cfg->pgd,
795 PTRS_PER_PGD * sizeof(pgd_t));
796 reg = __pa(cfg->pgd);
797 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO);
798 reg = (phys_addr_t)__pa(cfg->pgd) >> 32;
799 if (stage1)
800 reg |= ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT;
801 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI);
802
803 /*
804 * TTBCR
805 * We use long descriptor, with inner-shareable WBWA tables in TTBR0.
806 */
807 if (smmu->version > 1) {
808 if (PAGE_SIZE == SZ_4K)
809 reg = TTBCR_TG0_4K;
810 else
811 reg = TTBCR_TG0_64K;
812
813 if (!stage1) {
814 reg |= (64 - smmu->s1_output_size) << TTBCR_T0SZ_SHIFT;
815
816 switch (smmu->s2_output_size) {
817 case 32:
818 reg |= (TTBCR2_ADDR_32 << TTBCR_PASIZE_SHIFT);
819 break;
820 case 36:
821 reg |= (TTBCR2_ADDR_36 << TTBCR_PASIZE_SHIFT);
822 break;
823 case 40:
824 reg |= (TTBCR2_ADDR_40 << TTBCR_PASIZE_SHIFT);
825 break;
826 case 42:
827 reg |= (TTBCR2_ADDR_42 << TTBCR_PASIZE_SHIFT);
828 break;
829 case 44:
830 reg |= (TTBCR2_ADDR_44 << TTBCR_PASIZE_SHIFT);
831 break;
832 case 48:
833 reg |= (TTBCR2_ADDR_48 << TTBCR_PASIZE_SHIFT);
834 break;
835 }
836 } else {
837 reg |= (64 - smmu->input_size) << TTBCR_T0SZ_SHIFT;
838 }
839 } else {
840 reg = 0;
841 }
842
843 reg |= TTBCR_EAE |
844 (TTBCR_SH_IS << TTBCR_SH0_SHIFT) |
845 (TTBCR_RGN_WBWA << TTBCR_ORGN0_SHIFT) |
846 (TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT) |
847 (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT);
848 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);
849
850 /* MAIR0 (stage-1 only) */
851 if (stage1) {
852 reg = (MAIR_ATTR_NC << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_NC)) |
853 (MAIR_ATTR_WBRWA << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_CACHE)) |
854 (MAIR_ATTR_DEVICE << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_DEV));
855 writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0);
856 }
857
858 /* SCTLR */
859 reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP;
860 if (stage1)
861 reg |= SCTLR_S1_ASIDPNE;
862 #ifdef __BIG_ENDIAN
863 reg |= SCTLR_E;
864 #endif
865 writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR);
866 }
867
868 static int arm_smmu_init_domain_context(struct iommu_domain *domain,
869 struct arm_smmu_device *smmu)
870 {
871 int irq, start, ret = 0;
872 unsigned long flags;
873 struct arm_smmu_domain *smmu_domain = domain->priv;
874 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
875
876 spin_lock_irqsave(&smmu_domain->lock, flags);
877 if (smmu_domain->smmu)
878 goto out_unlock;
879
880 if (smmu->features & ARM_SMMU_FEAT_TRANS_NESTED) {
881 /*
882 * We will likely want to change this if/when KVM gets
883 * involved.
884 */
885 cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
886 start = smmu->num_s2_context_banks;
887 } else if (smmu->features & ARM_SMMU_FEAT_TRANS_S1) {
888 cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
889 start = smmu->num_s2_context_banks;
890 } else {
891 cfg->cbar = CBAR_TYPE_S2_TRANS;
892 start = 0;
893 }
894
895 ret = __arm_smmu_alloc_bitmap(smmu->context_map, start,
896 smmu->num_context_banks);
897 if (IS_ERR_VALUE(ret))
898 goto out_unlock;
899
900 cfg->cbndx = ret;
901 if (smmu->version == 1) {
902 cfg->irptndx = atomic_inc_return(&smmu->irptndx);
903 cfg->irptndx %= smmu->num_context_irqs;
904 } else {
905 cfg->irptndx = cfg->cbndx;
906 }
907
908 ACCESS_ONCE(smmu_domain->smmu) = smmu;
909 arm_smmu_init_context_bank(smmu_domain);
910 spin_unlock_irqrestore(&smmu_domain->lock, flags);
911
912 irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
913 ret = request_irq(irq, arm_smmu_context_fault, IRQF_SHARED,
914 "arm-smmu-context-fault", domain);
915 if (IS_ERR_VALUE(ret)) {
916 dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n",
917 cfg->irptndx, irq);
918 cfg->irptndx = INVALID_IRPTNDX;
919 }
920
921 return 0;
922
923 out_unlock:
924 spin_unlock_irqrestore(&smmu_domain->lock, flags);
925 return ret;
926 }
927
928 static void arm_smmu_destroy_domain_context(struct iommu_domain *domain)
929 {
930 struct arm_smmu_domain *smmu_domain = domain->priv;
931 struct arm_smmu_device *smmu = smmu_domain->smmu;
932 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
933 void __iomem *cb_base;
934 int irq;
935
936 if (!smmu)
937 return;
938
939 /* Disable the context bank and nuke the TLB before freeing it. */
940 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
941 writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
942 arm_smmu_tlb_inv_context(smmu_domain);
943
944 if (cfg->irptndx != INVALID_IRPTNDX) {
945 irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
946 free_irq(irq, domain);
947 }
948
949 __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx);
950 }
951
952 static int arm_smmu_domain_init(struct iommu_domain *domain)
953 {
954 struct arm_smmu_domain *smmu_domain;
955 pgd_t *pgd;
956
957 /*
958 * Allocate the domain and initialise some of its data structures.
959 * We can't really do anything meaningful until we've added a
960 * master.
961 */
962 smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL);
963 if (!smmu_domain)
964 return -ENOMEM;
965
966 pgd = kcalloc(PTRS_PER_PGD, sizeof(pgd_t), GFP_KERNEL);
967 if (!pgd)
968 goto out_free_domain;
969 smmu_domain->cfg.pgd = pgd;
970
971 spin_lock_init(&smmu_domain->lock);
972 domain->priv = smmu_domain;
973 return 0;
974
975 out_free_domain:
976 kfree(smmu_domain);
977 return -ENOMEM;
978 }
979
980 static void arm_smmu_free_ptes(pmd_t *pmd)
981 {
982 pgtable_t table = pmd_pgtable(*pmd);
983
984 pgtable_page_dtor(table);
985 __free_page(table);
986 }
987
988 static void arm_smmu_free_pmds(pud_t *pud)
989 {
990 int i;
991 pmd_t *pmd, *pmd_base = pmd_offset(pud, 0);
992
993 pmd = pmd_base;
994 for (i = 0; i < PTRS_PER_PMD; ++i) {
995 if (pmd_none(*pmd))
996 continue;
997
998 arm_smmu_free_ptes(pmd);
999 pmd++;
1000 }
1001
1002 pmd_free(NULL, pmd_base);
1003 }
1004
1005 static void arm_smmu_free_puds(pgd_t *pgd)
1006 {
1007 int i;
1008 pud_t *pud, *pud_base = pud_offset(pgd, 0);
1009
1010 pud = pud_base;
1011 for (i = 0; i < PTRS_PER_PUD; ++i) {
1012 if (pud_none(*pud))
1013 continue;
1014
1015 arm_smmu_free_pmds(pud);
1016 pud++;
1017 }
1018
1019 pud_free(NULL, pud_base);
1020 }
1021
1022 static void arm_smmu_free_pgtables(struct arm_smmu_domain *smmu_domain)
1023 {
1024 int i;
1025 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
1026 pgd_t *pgd, *pgd_base = cfg->pgd;
1027
1028 /*
1029 * Recursively free the page tables for this domain. We don't
1030 * care about speculative TLB filling because the tables should
1031 * not be active in any context bank at this point (SCTLR.M is 0).
1032 */
1033 pgd = pgd_base;
1034 for (i = 0; i < PTRS_PER_PGD; ++i) {
1035 if (pgd_none(*pgd))
1036 continue;
1037 arm_smmu_free_puds(pgd);
1038 pgd++;
1039 }
1040
1041 kfree(pgd_base);
1042 }
1043
1044 static void arm_smmu_domain_destroy(struct iommu_domain *domain)
1045 {
1046 struct arm_smmu_domain *smmu_domain = domain->priv;
1047
1048 /*
1049 * Free the domain resources. We assume that all devices have
1050 * already been detached.
1051 */
1052 arm_smmu_destroy_domain_context(domain);
1053 arm_smmu_free_pgtables(smmu_domain);
1054 kfree(smmu_domain);
1055 }
1056
1057 static int arm_smmu_master_configure_smrs(struct arm_smmu_device *smmu,
1058 struct arm_smmu_master_cfg *cfg)
1059 {
1060 int i;
1061 struct arm_smmu_smr *smrs;
1062 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1063
1064 if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH))
1065 return 0;
1066
1067 if (cfg->smrs)
1068 return -EEXIST;
1069
1070 smrs = kmalloc_array(cfg->num_streamids, sizeof(*smrs), GFP_KERNEL);
1071 if (!smrs) {
1072 dev_err(smmu->dev, "failed to allocate %d SMRs\n",
1073 cfg->num_streamids);
1074 return -ENOMEM;
1075 }
1076
1077 /* Allocate the SMRs on the SMMU */
1078 for (i = 0; i < cfg->num_streamids; ++i) {
1079 int idx = __arm_smmu_alloc_bitmap(smmu->smr_map, 0,
1080 smmu->num_mapping_groups);
1081 if (IS_ERR_VALUE(idx)) {
1082 dev_err(smmu->dev, "failed to allocate free SMR\n");
1083 goto err_free_smrs;
1084 }
1085
1086 smrs[i] = (struct arm_smmu_smr) {
1087 .idx = idx,
1088 .mask = 0, /* We don't currently share SMRs */
1089 .id = cfg->streamids[i],
1090 };
1091 }
1092
1093 /* It worked! Now, poke the actual hardware */
1094 for (i = 0; i < cfg->num_streamids; ++i) {
1095 u32 reg = SMR_VALID | smrs[i].id << SMR_ID_SHIFT |
1096 smrs[i].mask << SMR_MASK_SHIFT;
1097 writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx));
1098 }
1099
1100 cfg->smrs = smrs;
1101 return 0;
1102
1103 err_free_smrs:
1104 while (--i >= 0)
1105 __arm_smmu_free_bitmap(smmu->smr_map, smrs[i].idx);
1106 kfree(smrs);
1107 return -ENOSPC;
1108 }
1109
1110 static void arm_smmu_master_free_smrs(struct arm_smmu_device *smmu,
1111 struct arm_smmu_master_cfg *cfg)
1112 {
1113 int i;
1114 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1115 struct arm_smmu_smr *smrs = cfg->smrs;
1116
1117 /* Invalidate the SMRs before freeing back to the allocator */
1118 for (i = 0; i < cfg->num_streamids; ++i) {
1119 u8 idx = smrs[i].idx;
1120
1121 writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx));
1122 __arm_smmu_free_bitmap(smmu->smr_map, idx);
1123 }
1124
1125 cfg->smrs = NULL;
1126 kfree(smrs);
1127 }
1128
1129 static void arm_smmu_bypass_stream_mapping(struct arm_smmu_device *smmu,
1130 struct arm_smmu_master_cfg *cfg)
1131 {
1132 int i;
1133 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1134
1135 for (i = 0; i < cfg->num_streamids; ++i) {
1136 u16 sid = cfg->streamids[i];
1137
1138 writel_relaxed(S2CR_TYPE_BYPASS,
1139 gr0_base + ARM_SMMU_GR0_S2CR(sid));
1140 }
1141 }
1142
1143 static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
1144 struct arm_smmu_master_cfg *cfg)
1145 {
1146 int i, ret;
1147 struct arm_smmu_device *smmu = smmu_domain->smmu;
1148 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1149
1150 ret = arm_smmu_master_configure_smrs(smmu, cfg);
1151 if (ret)
1152 return ret;
1153
1154 for (i = 0; i < cfg->num_streamids; ++i) {
1155 u32 idx, s2cr;
1156
1157 idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i];
1158 s2cr = S2CR_TYPE_TRANS |
1159 (smmu_domain->cfg.cbndx << S2CR_CBNDX_SHIFT);
1160 writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx));
1161 }
1162
1163 return 0;
1164 }
1165
1166 static void arm_smmu_domain_remove_master(struct arm_smmu_domain *smmu_domain,
1167 struct arm_smmu_master_cfg *cfg)
1168 {
1169 struct arm_smmu_device *smmu = smmu_domain->smmu;
1170
1171 /*
1172 * We *must* clear the S2CR first, because freeing the SMR means
1173 * that it can be re-allocated immediately.
1174 */
1175 arm_smmu_bypass_stream_mapping(smmu, cfg);
1176 arm_smmu_master_free_smrs(smmu, cfg);
1177 }
1178
1179 static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
1180 {
1181 int ret;
1182 struct arm_smmu_domain *smmu_domain = domain->priv;
1183 struct arm_smmu_device *smmu, *dom_smmu;
1184 struct arm_smmu_master_cfg *cfg;
1185
1186 smmu = dev_get_master_dev(dev)->archdata.iommu;
1187 if (!smmu) {
1188 dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n");
1189 return -ENXIO;
1190 }
1191
1192 /*
1193 * Sanity check the domain. We don't support domains across
1194 * different SMMUs.
1195 */
1196 dom_smmu = ACCESS_ONCE(smmu_domain->smmu);
1197 if (!dom_smmu) {
1198 /* Now that we have a master, we can finalise the domain */
1199 ret = arm_smmu_init_domain_context(domain, smmu);
1200 if (IS_ERR_VALUE(ret))
1201 return ret;
1202
1203 dom_smmu = smmu_domain->smmu;
1204 }
1205
1206 if (dom_smmu != smmu) {
1207 dev_err(dev,
1208 "cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n",
1209 dev_name(smmu_domain->smmu->dev), dev_name(smmu->dev));
1210 return -EINVAL;
1211 }
1212
1213 /* Looks ok, so add the device to the domain */
1214 cfg = find_smmu_master_cfg(smmu_domain->smmu, dev);
1215 if (!cfg)
1216 return -ENODEV;
1217
1218 return arm_smmu_domain_add_master(smmu_domain, cfg);
1219 }
1220
1221 static void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev)
1222 {
1223 struct arm_smmu_domain *smmu_domain = domain->priv;
1224 struct arm_smmu_master_cfg *cfg;
1225
1226 cfg = find_smmu_master_cfg(smmu_domain->smmu, dev);
1227 if (cfg)
1228 arm_smmu_domain_remove_master(smmu_domain, cfg);
1229 }
1230
1231 static bool arm_smmu_pte_is_contiguous_range(unsigned long addr,
1232 unsigned long end)
1233 {
1234 return !(addr & ~ARM_SMMU_PTE_CONT_MASK) &&
1235 (addr + ARM_SMMU_PTE_CONT_SIZE <= end);
1236 }
1237
1238 static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd,
1239 unsigned long addr, unsigned long end,
1240 unsigned long pfn, int prot, int stage)
1241 {
1242 pte_t *pte, *start;
1243 pteval_t pteval = ARM_SMMU_PTE_PAGE | ARM_SMMU_PTE_AF | ARM_SMMU_PTE_XN;
1244
1245 if (pmd_none(*pmd)) {
1246 /* Allocate a new set of tables */
1247 pgtable_t table = alloc_page(GFP_ATOMIC|__GFP_ZERO);
1248
1249 if (!table)
1250 return -ENOMEM;
1251
1252 arm_smmu_flush_pgtable(smmu, page_address(table), PAGE_SIZE);
1253 if (!pgtable_page_ctor(table)) {
1254 __free_page(table);
1255 return -ENOMEM;
1256 }
1257 pmd_populate(NULL, pmd, table);
1258 arm_smmu_flush_pgtable(smmu, pmd, sizeof(*pmd));
1259 }
1260
1261 if (stage == 1) {
1262 pteval |= ARM_SMMU_PTE_AP_UNPRIV | ARM_SMMU_PTE_nG;
1263 if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ))
1264 pteval |= ARM_SMMU_PTE_AP_RDONLY;
1265
1266 if (prot & IOMMU_CACHE)
1267 pteval |= (MAIR_ATTR_IDX_CACHE <<
1268 ARM_SMMU_PTE_ATTRINDX_SHIFT);
1269 } else {
1270 pteval |= ARM_SMMU_PTE_HAP_FAULT;
1271 if (prot & IOMMU_READ)
1272 pteval |= ARM_SMMU_PTE_HAP_READ;
1273 if (prot & IOMMU_WRITE)
1274 pteval |= ARM_SMMU_PTE_HAP_WRITE;
1275 if (prot & IOMMU_CACHE)
1276 pteval |= ARM_SMMU_PTE_MEMATTR_OIWB;
1277 else
1278 pteval |= ARM_SMMU_PTE_MEMATTR_NC;
1279 }
1280
1281 /* If no access, create a faulting entry to avoid TLB fills */
1282 if (prot & IOMMU_EXEC)
1283 pteval &= ~ARM_SMMU_PTE_XN;
1284 else if (!(prot & (IOMMU_READ | IOMMU_WRITE)))
1285 pteval &= ~ARM_SMMU_PTE_PAGE;
1286
1287 pteval |= ARM_SMMU_PTE_SH_IS;
1288 start = pmd_page_vaddr(*pmd) + pte_index(addr);
1289 pte = start;
1290
1291 /*
1292 * Install the page table entries. This is fairly complicated
1293 * since we attempt to make use of the contiguous hint in the
1294 * ptes where possible. The contiguous hint indicates a series
1295 * of ARM_SMMU_PTE_CONT_ENTRIES ptes mapping a physically
1296 * contiguous region with the following constraints:
1297 *
1298 * - The region start is aligned to ARM_SMMU_PTE_CONT_SIZE
1299 * - Each pte in the region has the contiguous hint bit set
1300 *
1301 * This complicates unmapping (also handled by this code, when
1302 * neither IOMMU_READ or IOMMU_WRITE are set) because it is
1303 * possible, yet highly unlikely, that a client may unmap only
1304 * part of a contiguous range. This requires clearing of the
1305 * contiguous hint bits in the range before installing the new
1306 * faulting entries.
1307 *
1308 * Note that re-mapping an address range without first unmapping
1309 * it is not supported, so TLB invalidation is not required here
1310 * and is instead performed at unmap and domain-init time.
1311 */
1312 do {
1313 int i = 1;
1314
1315 pteval &= ~ARM_SMMU_PTE_CONT;
1316
1317 if (arm_smmu_pte_is_contiguous_range(addr, end)) {
1318 i = ARM_SMMU_PTE_CONT_ENTRIES;
1319 pteval |= ARM_SMMU_PTE_CONT;
1320 } else if (pte_val(*pte) &
1321 (ARM_SMMU_PTE_CONT | ARM_SMMU_PTE_PAGE)) {
1322 int j;
1323 pte_t *cont_start;
1324 unsigned long idx = pte_index(addr);
1325
1326 idx &= ~(ARM_SMMU_PTE_CONT_ENTRIES - 1);
1327 cont_start = pmd_page_vaddr(*pmd) + idx;
1328 for (j = 0; j < ARM_SMMU_PTE_CONT_ENTRIES; ++j)
1329 pte_val(*(cont_start + j)) &=
1330 ~ARM_SMMU_PTE_CONT;
1331
1332 arm_smmu_flush_pgtable(smmu, cont_start,
1333 sizeof(*pte) *
1334 ARM_SMMU_PTE_CONT_ENTRIES);
1335 }
1336
1337 do {
1338 *pte = pfn_pte(pfn, __pgprot(pteval));
1339 } while (pte++, pfn++, addr += PAGE_SIZE, --i);
1340 } while (addr != end);
1341
1342 arm_smmu_flush_pgtable(smmu, start, sizeof(*pte) * (pte - start));
1343 return 0;
1344 }
1345
1346 static int arm_smmu_alloc_init_pmd(struct arm_smmu_device *smmu, pud_t *pud,
1347 unsigned long addr, unsigned long end,
1348 phys_addr_t phys, int prot, int stage)
1349 {
1350 int ret;
1351 pmd_t *pmd;
1352 unsigned long next, pfn = __phys_to_pfn(phys);
1353
1354 #ifndef __PAGETABLE_PMD_FOLDED
1355 if (pud_none(*pud)) {
1356 pmd = (pmd_t *)get_zeroed_page(GFP_ATOMIC);
1357 if (!pmd)
1358 return -ENOMEM;
1359
1360 arm_smmu_flush_pgtable(smmu, pmd, PAGE_SIZE);
1361 pud_populate(NULL, pud, pmd);
1362 arm_smmu_flush_pgtable(smmu, pud, sizeof(*pud));
1363
1364 pmd += pmd_index(addr);
1365 } else
1366 #endif
1367 pmd = pmd_offset(pud, addr);
1368
1369 do {
1370 next = pmd_addr_end(addr, end);
1371 ret = arm_smmu_alloc_init_pte(smmu, pmd, addr, next, pfn,
1372 prot, stage);
1373 phys += next - addr;
1374 } while (pmd++, addr = next, addr < end);
1375
1376 return ret;
1377 }
1378
1379 static int arm_smmu_alloc_init_pud(struct arm_smmu_device *smmu, pgd_t *pgd,
1380 unsigned long addr, unsigned long end,
1381 phys_addr_t phys, int prot, int stage)
1382 {
1383 int ret = 0;
1384 pud_t *pud;
1385 unsigned long next;
1386
1387 #ifndef __PAGETABLE_PUD_FOLDED
1388 if (pgd_none(*pgd)) {
1389 pud = (pud_t *)get_zeroed_page(GFP_ATOMIC);
1390 if (!pud)
1391 return -ENOMEM;
1392
1393 arm_smmu_flush_pgtable(smmu, pud, PAGE_SIZE);
1394 pgd_populate(NULL, pgd, pud);
1395 arm_smmu_flush_pgtable(smmu, pgd, sizeof(*pgd));
1396
1397 pud += pud_index(addr);
1398 } else
1399 #endif
1400 pud = pud_offset(pgd, addr);
1401
1402 do {
1403 next = pud_addr_end(addr, end);
1404 ret = arm_smmu_alloc_init_pmd(smmu, pud, addr, next, phys,
1405 prot, stage);
1406 phys += next - addr;
1407 } while (pud++, addr = next, addr < end);
1408
1409 return ret;
1410 }
1411
1412 static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain,
1413 unsigned long iova, phys_addr_t paddr,
1414 size_t size, int prot)
1415 {
1416 int ret, stage;
1417 unsigned long end;
1418 phys_addr_t input_mask, output_mask;
1419 struct arm_smmu_device *smmu = smmu_domain->smmu;
1420 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
1421 pgd_t *pgd = cfg->pgd;
1422 unsigned long flags;
1423
1424 if (cfg->cbar == CBAR_TYPE_S2_TRANS) {
1425 stage = 2;
1426 output_mask = (1ULL << smmu->s2_output_size) - 1;
1427 } else {
1428 stage = 1;
1429 output_mask = (1ULL << smmu->s1_output_size) - 1;
1430 }
1431
1432 if (!pgd)
1433 return -EINVAL;
1434
1435 if (size & ~PAGE_MASK)
1436 return -EINVAL;
1437
1438 input_mask = (1ULL << smmu->input_size) - 1;
1439 if ((phys_addr_t)iova & ~input_mask)
1440 return -ERANGE;
1441
1442 if (paddr & ~output_mask)
1443 return -ERANGE;
1444
1445 spin_lock_irqsave(&smmu_domain->lock, flags);
1446 pgd += pgd_index(iova);
1447 end = iova + size;
1448 do {
1449 unsigned long next = pgd_addr_end(iova, end);
1450
1451 ret = arm_smmu_alloc_init_pud(smmu, pgd, iova, next, paddr,
1452 prot, stage);
1453 if (ret)
1454 goto out_unlock;
1455
1456 paddr += next - iova;
1457 iova = next;
1458 } while (pgd++, iova != end);
1459
1460 out_unlock:
1461 spin_unlock_irqrestore(&smmu_domain->lock, flags);
1462
1463 return ret;
1464 }
1465
1466 static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova,
1467 phys_addr_t paddr, size_t size, int prot)
1468 {
1469 struct arm_smmu_domain *smmu_domain = domain->priv;
1470
1471 if (!smmu_domain)
1472 return -ENODEV;
1473
1474 return arm_smmu_handle_mapping(smmu_domain, iova, paddr, size, prot);
1475 }
1476
1477 static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova,
1478 size_t size)
1479 {
1480 int ret;
1481 struct arm_smmu_domain *smmu_domain = domain->priv;
1482
1483 ret = arm_smmu_handle_mapping(smmu_domain, iova, 0, size, 0);
1484 arm_smmu_tlb_inv_context(smmu_domain);
1485 return ret ? 0 : size;
1486 }
1487
1488 static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain,
1489 dma_addr_t iova)
1490 {
1491 pgd_t *pgdp, pgd;
1492 pud_t pud;
1493 pmd_t pmd;
1494 pte_t pte;
1495 struct arm_smmu_domain *smmu_domain = domain->priv;
1496 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
1497
1498 pgdp = cfg->pgd;
1499 if (!pgdp)
1500 return 0;
1501
1502 pgd = *(pgdp + pgd_index(iova));
1503 if (pgd_none(pgd))
1504 return 0;
1505
1506 pud = *pud_offset(&pgd, iova);
1507 if (pud_none(pud))
1508 return 0;
1509
1510 pmd = *pmd_offset(&pud, iova);
1511 if (pmd_none(pmd))
1512 return 0;
1513
1514 pte = *(pmd_page_vaddr(pmd) + pte_index(iova));
1515 if (pte_none(pte))
1516 return 0;
1517
1518 return __pfn_to_phys(pte_pfn(pte)) | (iova & ~PAGE_MASK);
1519 }
1520
1521 static int arm_smmu_domain_has_cap(struct iommu_domain *domain,
1522 unsigned long cap)
1523 {
1524 struct arm_smmu_domain *smmu_domain = domain->priv;
1525 struct arm_smmu_device *smmu = smmu_domain->smmu;
1526 u32 features = smmu ? smmu->features : 0;
1527
1528 switch (cap) {
1529 case IOMMU_CAP_CACHE_COHERENCY:
1530 return features & ARM_SMMU_FEAT_COHERENT_WALK;
1531 case IOMMU_CAP_INTR_REMAP:
1532 return 1; /* MSIs are just memory writes */
1533 default:
1534 return 0;
1535 }
1536 }
1537
1538 static int __arm_smmu_get_pci_sid(struct pci_dev *pdev, u16 alias, void *data)
1539 {
1540 *((u16 *)data) = alias;
1541 return 0; /* Continue walking */
1542 }
1543
1544 static int arm_smmu_add_device(struct device *dev)
1545 {
1546 struct arm_smmu_device *smmu;
1547 struct iommu_group *group;
1548 int ret;
1549
1550 if (dev->archdata.iommu) {
1551 dev_warn(dev, "IOMMU driver already assigned to device\n");
1552 return -EINVAL;
1553 }
1554
1555 smmu = find_smmu_for_device(dev);
1556 if (!smmu)
1557 return -ENODEV;
1558
1559 group = iommu_group_alloc();
1560 if (IS_ERR(group)) {
1561 dev_err(dev, "Failed to allocate IOMMU group\n");
1562 return PTR_ERR(group);
1563 }
1564
1565 if (dev_is_pci(dev)) {
1566 struct arm_smmu_master_cfg *cfg;
1567 struct pci_dev *pdev = to_pci_dev(dev);
1568
1569 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1570 if (!cfg) {
1571 ret = -ENOMEM;
1572 goto out_put_group;
1573 }
1574
1575 cfg->num_streamids = 1;
1576 /*
1577 * Assume Stream ID == Requester ID for now.
1578 * We need a way to describe the ID mappings in FDT.
1579 */
1580 pci_for_each_dma_alias(pdev, __arm_smmu_get_pci_sid,
1581 &cfg->streamids[0]);
1582 dev->archdata.iommu = cfg;
1583 } else {
1584 dev->archdata.iommu = smmu;
1585 }
1586
1587 ret = iommu_group_add_device(group, dev);
1588
1589 out_put_group:
1590 iommu_group_put(group);
1591 return ret;
1592 }
1593
1594 static void arm_smmu_remove_device(struct device *dev)
1595 {
1596 if (dev_is_pci(dev))
1597 kfree(dev->archdata.iommu);
1598
1599 dev->archdata.iommu = NULL;
1600 iommu_group_remove_device(dev);
1601 }
1602
1603 static const struct iommu_ops arm_smmu_ops = {
1604 .domain_init = arm_smmu_domain_init,
1605 .domain_destroy = arm_smmu_domain_destroy,
1606 .attach_dev = arm_smmu_attach_dev,
1607 .detach_dev = arm_smmu_detach_dev,
1608 .map = arm_smmu_map,
1609 .unmap = arm_smmu_unmap,
1610 .iova_to_phys = arm_smmu_iova_to_phys,
1611 .domain_has_cap = arm_smmu_domain_has_cap,
1612 .add_device = arm_smmu_add_device,
1613 .remove_device = arm_smmu_remove_device,
1614 .pgsize_bitmap = (SECTION_SIZE |
1615 ARM_SMMU_PTE_CONT_SIZE |
1616 PAGE_SIZE),
1617 };
1618
1619 static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
1620 {
1621 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1622 void __iomem *cb_base;
1623 int i = 0;
1624 u32 reg;
1625
1626 /* clear global FSR */
1627 reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
1628 writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
1629
1630 /* Mark all SMRn as invalid and all S2CRn as bypass */
1631 for (i = 0; i < smmu->num_mapping_groups; ++i) {
1632 writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(i));
1633 writel_relaxed(S2CR_TYPE_BYPASS,
1634 gr0_base + ARM_SMMU_GR0_S2CR(i));
1635 }
1636
1637 /* Make sure all context banks are disabled and clear CB_FSR */
1638 for (i = 0; i < smmu->num_context_banks; ++i) {
1639 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i);
1640 writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
1641 writel_relaxed(FSR_FAULT, cb_base + ARM_SMMU_CB_FSR);
1642 }
1643
1644 /* Invalidate the TLB, just in case */
1645 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_STLBIALL);
1646 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH);
1647 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH);
1648
1649 reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1650
1651 /* Enable fault reporting */
1652 reg |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE);
1653
1654 /* Disable TLB broadcasting. */
1655 reg |= (sCR0_VMIDPNE | sCR0_PTM);
1656
1657 /* Enable client access, but bypass when no mapping is found */
1658 reg &= ~(sCR0_CLIENTPD | sCR0_USFCFG);
1659
1660 /* Disable forced broadcasting */
1661 reg &= ~sCR0_FB;
1662
1663 /* Don't upgrade barriers */
1664 reg &= ~(sCR0_BSU_MASK << sCR0_BSU_SHIFT);
1665
1666 /* Push the button */
1667 arm_smmu_tlb_sync(smmu);
1668 writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1669 }
1670
1671 static int arm_smmu_id_size_to_bits(int size)
1672 {
1673 switch (size) {
1674 case 0:
1675 return 32;
1676 case 1:
1677 return 36;
1678 case 2:
1679 return 40;
1680 case 3:
1681 return 42;
1682 case 4:
1683 return 44;
1684 case 5:
1685 default:
1686 return 48;
1687 }
1688 }
1689
1690 static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
1691 {
1692 unsigned long size;
1693 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1694 u32 id;
1695
1696 dev_notice(smmu->dev, "probing hardware configuration...\n");
1697
1698 /* Primecell ID */
1699 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_PIDR2);
1700 smmu->version = ((id >> PIDR2_ARCH_SHIFT) & PIDR2_ARCH_MASK) + 1;
1701 dev_notice(smmu->dev, "SMMUv%d with:\n", smmu->version);
1702
1703 /* ID0 */
1704 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0);
1705 #ifndef CONFIG_64BIT
1706 if (((id >> ID0_PTFS_SHIFT) & ID0_PTFS_MASK) == ID0_PTFS_V8_ONLY) {
1707 dev_err(smmu->dev, "\tno v7 descriptor support!\n");
1708 return -ENODEV;
1709 }
1710 #endif
1711 if (id & ID0_S1TS) {
1712 smmu->features |= ARM_SMMU_FEAT_TRANS_S1;
1713 dev_notice(smmu->dev, "\tstage 1 translation\n");
1714 }
1715
1716 if (id & ID0_S2TS) {
1717 smmu->features |= ARM_SMMU_FEAT_TRANS_S2;
1718 dev_notice(smmu->dev, "\tstage 2 translation\n");
1719 }
1720
1721 if (id & ID0_NTS) {
1722 smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED;
1723 dev_notice(smmu->dev, "\tnested translation\n");
1724 }
1725
1726 if (!(smmu->features &
1727 (ARM_SMMU_FEAT_TRANS_S1 | ARM_SMMU_FEAT_TRANS_S2 |
1728 ARM_SMMU_FEAT_TRANS_NESTED))) {
1729 dev_err(smmu->dev, "\tno translation support!\n");
1730 return -ENODEV;
1731 }
1732
1733 if (id & ID0_CTTW) {
1734 smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK;
1735 dev_notice(smmu->dev, "\tcoherent table walk\n");
1736 }
1737
1738 if (id & ID0_SMS) {
1739 u32 smr, sid, mask;
1740
1741 smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH;
1742 smmu->num_mapping_groups = (id >> ID0_NUMSMRG_SHIFT) &
1743 ID0_NUMSMRG_MASK;
1744 if (smmu->num_mapping_groups == 0) {
1745 dev_err(smmu->dev,
1746 "stream-matching supported, but no SMRs present!\n");
1747 return -ENODEV;
1748 }
1749
1750 smr = SMR_MASK_MASK << SMR_MASK_SHIFT;
1751 smr |= (SMR_ID_MASK << SMR_ID_SHIFT);
1752 writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0));
1753 smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0));
1754
1755 mask = (smr >> SMR_MASK_SHIFT) & SMR_MASK_MASK;
1756 sid = (smr >> SMR_ID_SHIFT) & SMR_ID_MASK;
1757 if ((mask & sid) != sid) {
1758 dev_err(smmu->dev,
1759 "SMR mask bits (0x%x) insufficient for ID field (0x%x)\n",
1760 mask, sid);
1761 return -ENODEV;
1762 }
1763
1764 dev_notice(smmu->dev,
1765 "\tstream matching with %u register groups, mask 0x%x",
1766 smmu->num_mapping_groups, mask);
1767 }
1768
1769 /* ID1 */
1770 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID1);
1771 smmu->pagesize = (id & ID1_PAGESIZE) ? SZ_64K : SZ_4K;
1772
1773 /* Check for size mismatch of SMMU address space from mapped region */
1774 size = 1 <<
1775 (((id >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1);
1776 size *= (smmu->pagesize << 1);
1777 if (smmu->size != size)
1778 dev_warn(smmu->dev,
1779 "SMMU address space size (0x%lx) differs from mapped region size (0x%lx)!\n",
1780 size, smmu->size);
1781
1782 smmu->num_s2_context_banks = (id >> ID1_NUMS2CB_SHIFT) &
1783 ID1_NUMS2CB_MASK;
1784 smmu->num_context_banks = (id >> ID1_NUMCB_SHIFT) & ID1_NUMCB_MASK;
1785 if (smmu->num_s2_context_banks > smmu->num_context_banks) {
1786 dev_err(smmu->dev, "impossible number of S2 context banks!\n");
1787 return -ENODEV;
1788 }
1789 dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n",
1790 smmu->num_context_banks, smmu->num_s2_context_banks);
1791
1792 /* ID2 */
1793 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2);
1794 size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK);
1795
1796 /*
1797 * Stage-1 output limited by stage-2 input size due to pgd
1798 * allocation (PTRS_PER_PGD).
1799 */
1800 #ifdef CONFIG_64BIT
1801 smmu->s1_output_size = min_t(unsigned long, VA_BITS, size);
1802 #else
1803 smmu->s1_output_size = min(32UL, size);
1804 #endif
1805
1806 /* The stage-2 output mask is also applied for bypass */
1807 size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK);
1808 smmu->s2_output_size = min_t(unsigned long, PHYS_MASK_SHIFT, size);
1809
1810 if (smmu->version == 1) {
1811 smmu->input_size = 32;
1812 } else {
1813 #ifdef CONFIG_64BIT
1814 size = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK;
1815 size = min(VA_BITS, arm_smmu_id_size_to_bits(size));
1816 #else
1817 size = 32;
1818 #endif
1819 smmu->input_size = size;
1820
1821 if ((PAGE_SIZE == SZ_4K && !(id & ID2_PTFS_4K)) ||
1822 (PAGE_SIZE == SZ_64K && !(id & ID2_PTFS_64K)) ||
1823 (PAGE_SIZE != SZ_4K && PAGE_SIZE != SZ_64K)) {
1824 dev_err(smmu->dev, "CPU page size 0x%lx unsupported\n",
1825 PAGE_SIZE);
1826 return -ENODEV;
1827 }
1828 }
1829
1830 dev_notice(smmu->dev,
1831 "\t%lu-bit VA, %lu-bit IPA, %lu-bit PA\n",
1832 smmu->input_size, smmu->s1_output_size,
1833 smmu->s2_output_size);
1834 return 0;
1835 }
1836
1837 static int arm_smmu_device_dt_probe(struct platform_device *pdev)
1838 {
1839 struct resource *res;
1840 struct arm_smmu_device *smmu;
1841 struct device *dev = &pdev->dev;
1842 struct rb_node *node;
1843 struct of_phandle_args masterspec;
1844 int num_irqs, i, err;
1845
1846 smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
1847 if (!smmu) {
1848 dev_err(dev, "failed to allocate arm_smmu_device\n");
1849 return -ENOMEM;
1850 }
1851 smmu->dev = dev;
1852
1853 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1854 smmu->base = devm_ioremap_resource(dev, res);
1855 if (IS_ERR(smmu->base))
1856 return PTR_ERR(smmu->base);
1857 smmu->size = resource_size(res);
1858
1859 if (of_property_read_u32(dev->of_node, "#global-interrupts",
1860 &smmu->num_global_irqs)) {
1861 dev_err(dev, "missing #global-interrupts property\n");
1862 return -ENODEV;
1863 }
1864
1865 num_irqs = 0;
1866 while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, num_irqs))) {
1867 num_irqs++;
1868 if (num_irqs > smmu->num_global_irqs)
1869 smmu->num_context_irqs++;
1870 }
1871
1872 if (!smmu->num_context_irqs) {
1873 dev_err(dev, "found %d interrupts but expected at least %d\n",
1874 num_irqs, smmu->num_global_irqs + 1);
1875 return -ENODEV;
1876 }
1877
1878 smmu->irqs = devm_kzalloc(dev, sizeof(*smmu->irqs) * num_irqs,
1879 GFP_KERNEL);
1880 if (!smmu->irqs) {
1881 dev_err(dev, "failed to allocate %d irqs\n", num_irqs);
1882 return -ENOMEM;
1883 }
1884
1885 for (i = 0; i < num_irqs; ++i) {
1886 int irq = platform_get_irq(pdev, i);
1887
1888 if (irq < 0) {
1889 dev_err(dev, "failed to get irq index %d\n", i);
1890 return -ENODEV;
1891 }
1892 smmu->irqs[i] = irq;
1893 }
1894
1895 i = 0;
1896 smmu->masters = RB_ROOT;
1897 while (!of_parse_phandle_with_args(dev->of_node, "mmu-masters",
1898 "#stream-id-cells", i,
1899 &masterspec)) {
1900 err = register_smmu_master(smmu, dev, &masterspec);
1901 if (err) {
1902 dev_err(dev, "failed to add master %s\n",
1903 masterspec.np->name);
1904 goto out_put_masters;
1905 }
1906
1907 i++;
1908 }
1909 dev_notice(dev, "registered %d master devices\n", i);
1910
1911 err = arm_smmu_device_cfg_probe(smmu);
1912 if (err)
1913 goto out_put_masters;
1914
1915 parse_driver_options(smmu);
1916
1917 if (smmu->version > 1 &&
1918 smmu->num_context_banks != smmu->num_context_irqs) {
1919 dev_err(dev,
1920 "found only %d context interrupt(s) but %d required\n",
1921 smmu->num_context_irqs, smmu->num_context_banks);
1922 err = -ENODEV;
1923 goto out_put_masters;
1924 }
1925
1926 for (i = 0; i < smmu->num_global_irqs; ++i) {
1927 err = request_irq(smmu->irqs[i],
1928 arm_smmu_global_fault,
1929 IRQF_SHARED,
1930 "arm-smmu global fault",
1931 smmu);
1932 if (err) {
1933 dev_err(dev, "failed to request global IRQ %d (%u)\n",
1934 i, smmu->irqs[i]);
1935 goto out_free_irqs;
1936 }
1937 }
1938
1939 INIT_LIST_HEAD(&smmu->list);
1940 spin_lock(&arm_smmu_devices_lock);
1941 list_add(&smmu->list, &arm_smmu_devices);
1942 spin_unlock(&arm_smmu_devices_lock);
1943
1944 arm_smmu_device_reset(smmu);
1945 return 0;
1946
1947 out_free_irqs:
1948 while (i--)
1949 free_irq(smmu->irqs[i], smmu);
1950
1951 out_put_masters:
1952 for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
1953 struct arm_smmu_master *master
1954 = container_of(node, struct arm_smmu_master, node);
1955 of_node_put(master->of_node);
1956 }
1957
1958 return err;
1959 }
1960
1961 static int arm_smmu_device_remove(struct platform_device *pdev)
1962 {
1963 int i;
1964 struct device *dev = &pdev->dev;
1965 struct arm_smmu_device *curr, *smmu = NULL;
1966 struct rb_node *node;
1967
1968 spin_lock(&arm_smmu_devices_lock);
1969 list_for_each_entry(curr, &arm_smmu_devices, list) {
1970 if (curr->dev == dev) {
1971 smmu = curr;
1972 list_del(&smmu->list);
1973 break;
1974 }
1975 }
1976 spin_unlock(&arm_smmu_devices_lock);
1977
1978 if (!smmu)
1979 return -ENODEV;
1980
1981 for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
1982 struct arm_smmu_master *master
1983 = container_of(node, struct arm_smmu_master, node);
1984 of_node_put(master->of_node);
1985 }
1986
1987 if (!bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS))
1988 dev_err(dev, "removing device with active domains!\n");
1989
1990 for (i = 0; i < smmu->num_global_irqs; ++i)
1991 free_irq(smmu->irqs[i], smmu);
1992
1993 /* Turn the thing off */
1994 writel(sCR0_CLIENTPD, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1995 return 0;
1996 }
1997
1998 #ifdef CONFIG_OF
1999 static struct of_device_id arm_smmu_of_match[] = {
2000 { .compatible = "arm,smmu-v1", },
2001 { .compatible = "arm,smmu-v2", },
2002 { .compatible = "arm,mmu-400", },
2003 { .compatible = "arm,mmu-500", },
2004 { },
2005 };
2006 MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
2007 #endif
2008
2009 static struct platform_driver arm_smmu_driver = {
2010 .driver = {
2011 .owner = THIS_MODULE,
2012 .name = "arm-smmu",
2013 .of_match_table = of_match_ptr(arm_smmu_of_match),
2014 },
2015 .probe = arm_smmu_device_dt_probe,
2016 .remove = arm_smmu_device_remove,
2017 };
2018
2019 static int __init arm_smmu_init(void)
2020 {
2021 int ret;
2022
2023 ret = platform_driver_register(&arm_smmu_driver);
2024 if (ret)
2025 return ret;
2026
2027 /* Oh, for a proper bus abstraction */
2028 if (!iommu_present(&platform_bus_type))
2029 bus_set_iommu(&platform_bus_type, &arm_smmu_ops);
2030
2031 #ifdef CONFIG_ARM_AMBA
2032 if (!iommu_present(&amba_bustype))
2033 bus_set_iommu(&amba_bustype, &arm_smmu_ops);
2034 #endif
2035
2036 #ifdef CONFIG_PCI
2037 if (!iommu_present(&pci_bus_type))
2038 bus_set_iommu(&pci_bus_type, &arm_smmu_ops);
2039 #endif
2040
2041 return 0;
2042 }
2043
2044 static void __exit arm_smmu_exit(void)
2045 {
2046 return platform_driver_unregister(&arm_smmu_driver);
2047 }
2048
2049 subsys_initcall(arm_smmu_init);
2050 module_exit(arm_smmu_exit);
2051
2052 MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations");
2053 MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
2054 MODULE_LICENSE("GPL v2");
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